1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
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18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
36 * This file implements HCD Core. All code in this file is portable and doesn't
37 * use any OS specific functions.
38 * Interface provided by HCD Core is defined in <code><hcd_if.h></code>
42 #include "dwc_otg_hcd.h"
43 #include "dwc_otg_regs.h"
44 #include "usbdev_rk.h"
45 #include "dwc_otg_driver.h"
46 #include <linux/usb.h>
47 #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35)
48 #include <../drivers/usb/core/hcd.h>
50 #include <linux/usb/hcd.h>
53 dwc_otg_hcd_t *dwc_otg_hcd_alloc_hcd(void)
55 return DWC_ALLOC(sizeof(dwc_otg_hcd_t));
59 * Connection timeout function. An OTG host is required to display a
60 * message if the device does not connect within 10 seconds.
62 void dwc_otg_hcd_connect_timeout(void *ptr)
65 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, ptr);
66 DWC_PRINTF("Connect Timeout\n");
67 __DWC_ERROR("Device Not Connected/Responding\n");
68 /** Remove buspower after 10s */
70 if (hcd->core_if->otg_ver)
71 dwc_otg_set_prtpower(hcd->core_if, 0);
75 static void dump_channel_info(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
77 if (qh->channel != NULL) {
78 dwc_hc_t *hc = qh->channel;
79 dwc_list_link_t *item;
80 dwc_otg_qh_t *qh_item;
81 int num_channels = hcd->core_if->core_params->host_channels;
84 dwc_otg_hc_regs_t *hc_regs;
90 hc_regs = hcd->core_if->host_if->hc_regs[hc->hc_num];
91 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
92 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
93 hctsiz.d32 = DWC_READ_REG32(&hc_regs->hctsiz);
94 hcdma = DWC_READ_REG32(&hc_regs->hcdma);
96 DWC_PRINTF(" Assigned to channel %p:\n", hc);
97 DWC_PRINTF(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32,
99 DWC_PRINTF(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32,
101 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
102 hc->dev_addr, hc->ep_num, hc->ep_is_in);
103 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
104 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
105 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
106 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
107 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
108 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
109 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
110 DWC_PRINTF(" qh: %p\n", hc->qh);
111 DWC_PRINTF(" NP inactive sched:\n");
112 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_inactive) {
114 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
115 DWC_PRINTF(" %p\n", qh_item);
117 DWC_PRINTF(" NP active sched:\n");
118 DWC_LIST_FOREACH(item, &hcd->non_periodic_sched_active) {
120 DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
121 DWC_PRINTF(" %p\n", qh_item);
123 DWC_PRINTF(" Channels: \n");
124 for (i = 0; i < num_channels; i++) {
125 dwc_hc_t *hc = hcd->hc_ptr_array[i];
126 DWC_PRINTF(" %2d: %p\n", i, hc);
133 * Work queue function for starting the HCD when A-Cable is connected.
134 * The hcd_start() must be called in a process context.
136 static void hcd_start_func(void *_vp)
138 dwc_otg_hcd_t *hcd = (dwc_otg_hcd_t *) _vp;
140 DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, hcd);
142 hcd->fops->start(hcd);
146 static void del_xfer_timers(dwc_otg_hcd_t *hcd)
150 int num_channels = hcd->core_if->core_params->host_channels;
151 for (i = 0; i < num_channels; i++) {
152 DWC_TIMER_CANCEL(hcd->core_if->hc_xfer_timer[i]);
157 static void del_timers(dwc_otg_hcd_t *hcd)
159 del_xfer_timers(hcd);
160 DWC_TIMER_CANCEL(hcd->conn_timer);
164 * Processes all the URBs in a single list of QHs. Completes them with
165 * -ETIMEDOUT and frees the QTD.
167 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
169 dwc_list_link_t *qh_item;
171 dwc_otg_qtd_t *qtd, *qtd_tmp;
173 DWC_LIST_FOREACH(qh_item, qh_list) {
174 qh = DWC_LIST_ENTRY(qh_item, dwc_otg_qh_t, qh_list_entry);
175 DWC_CIRCLEQ_FOREACH_SAFE(qtd, qtd_tmp,
176 &qh->qtd_list, qtd_list_entry) {
177 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
178 if (qtd->urb != NULL) {
179 hcd->fops->complete(hcd, qtd->urb->priv,
180 qtd->urb, -DWC_E_SHUTDOWN);
181 dwc_otg_hcd_qtd_remove_and_free(hcd, qtd, qh);
189 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
190 * and periodic schedules. The QTD associated with each URB is removed from
191 * the schedule and freed. This function may be called when a disconnect is
192 * detected or when the HCD is being stopped.
194 static void kill_all_urbs(dwc_otg_hcd_t *hcd)
196 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_inactive);
197 kill_urbs_in_qh_list(hcd, &hcd->non_periodic_sched_active);
198 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_inactive);
199 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_ready);
200 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_assigned);
201 kill_urbs_in_qh_list(hcd, &hcd->periodic_sched_queued);
205 * Start the connection timer. An OTG host is required to display a
206 * message if the device does not connect within 10 seconds. The
207 * timer is deleted if a port connect interrupt occurs before the
210 static void dwc_otg_hcd_start_connect_timer(dwc_otg_hcd_t *hcd)
212 DWC_TIMER_SCHEDULE(hcd->conn_timer, 10000 /* 10 secs */);
216 * HCD Callback function for disconnect of the HCD.
218 * @param p void pointer to the <code>struct usb_hcd</code>
220 static int32_t dwc_otg_hcd_session_start_cb(void *p)
222 dwc_otg_hcd_t *dwc_otg_hcd;
223 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
225 dwc_otg_hcd_start_connect_timer(dwc_otg_hcd);
230 * HCD Callback function for starting the HCD when A-Cable is
233 * @param p void pointer to the <code>struct usb_hcd</code>
235 static int32_t dwc_otg_hcd_start_cb(void *p)
237 dwc_otg_hcd_t *dwc_otg_hcd = p;
238 dwc_otg_core_if_t *core_if;
240 uint32_t timeout = 50;
242 core_if = dwc_otg_hcd->core_if;
244 if (core_if->op_state == B_HOST) {
246 * Reset the port. During a HNP mode switch the reset
247 * needs to occur within 1ms and have a duration of at
250 hprt0.d32 = dwc_otg_read_hprt0(core_if);
252 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
253 if (core_if->otg_ver) {
255 hprt0.d32 = dwc_otg_read_hprt0(core_if);
257 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
260 /**@todo vahrama: Check the timeout value for OTG 2.0 */
261 if (core_if->otg_ver)
263 DWC_WORKQ_SCHEDULE_DELAYED(core_if->wq_otg,
264 hcd_start_func, dwc_otg_hcd, timeout,
271 * HCD Callback function for disconnect of the HCD.
273 * @param p void pointer to the <code>struct usb_hcd</code>
275 static int32_t dwc_otg_hcd_disconnect_cb(void *p)
278 dwc_otg_hcd_t *dwc_otg_hcd = p;
281 dwc_otg_hcd->non_periodic_qh_ptr = &dwc_otg_hcd->non_periodic_sched_active;
282 dwc_otg_hcd->non_periodic_channels = 0;
283 dwc_otg_hcd->periodic_channels = 0;
285 hprt0.d32 = DWC_READ_REG32(dwc_otg_hcd->core_if->host_if->hprt0);
286 /* In some case, we don't disconnect a usb device, but
287 * disconnect intr was triggered, so check hprt0 here. */
288 if ((!hprt0.b.prtenchng)
289 && (!hprt0.b.prtconndet)
290 && hprt0.b.prtconnsts) {
291 DWC_PRINTF("%s: hprt0 = 0x%08x\n", __func__, hprt0.d32);
295 * Set status flags for the hub driver.
297 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
298 dwc_otg_hcd->flags.b.port_connect_status = 0;
301 * Shutdown any transfers in process by clearing the Tx FIFO Empty
302 * interrupt mask and status bits and disabling subsequent host
303 * channel interrupts.
306 intr.b.nptxfempty = 1;
307 intr.b.ptxfempty = 1;
309 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk,
311 DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintsts,
315 * Turn off the vbus power only if the core has transitioned to device
316 * mode. If still in host mode, need to keep power on to detect a
319 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
320 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
321 hprt0_data_t hprt0 = {.d32 = 0 };
322 DWC_PRINTF("Disconnect: PortPower off\n");
324 DWC_WRITE_REG32(dwc_otg_hcd->core_if->host_if->hprt0,
327 /** Delete timers if become device */
328 del_timers(dwc_otg_hcd);
329 dwc_otg_disable_host_interrupts(dwc_otg_hcd->core_if);
333 /* Respond with an error status to all URBs in the schedule. */
334 kill_all_urbs(dwc_otg_hcd);
336 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
337 /* Clean up any host channels that were in use. */
341 dwc_otg_hc_regs_t *hc_regs;
342 hcchar_data_t hcchar;
344 DWC_PRINTF("Disconnect cb-Host\n");
345 if (dwc_otg_hcd->core_if->otg_ver == 1)
346 del_xfer_timers(dwc_otg_hcd);
348 del_timers(dwc_otg_hcd);
350 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
352 if (!dwc_otg_hcd->core_if->dma_enable) {
353 /* Flush out any channel requests in slave mode. */
354 for (i = 0; i < num_channels; i++) {
355 channel = dwc_otg_hcd->hc_ptr_array[i];
356 if (DWC_CIRCLEQ_EMPTY_ENTRY
357 (channel, hc_list_entry)) {
359 dwc_otg_hcd->core_if->host_if->
362 DWC_READ_REG32(&hc_regs->hcchar);
375 for (i = 0; i < num_channels; i++) {
376 channel = dwc_otg_hcd->hc_ptr_array[i];
377 if (DWC_CIRCLEQ_EMPTY_ENTRY(channel, hc_list_entry)) {
379 dwc_otg_hcd->core_if->host_if->hc_regs[i];
380 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
382 /* Halt the channel. */
384 DWC_WRITE_REG32(&hc_regs->hcchar,
388 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if,
390 DWC_CIRCLEQ_INSERT_TAIL
391 (&dwc_otg_hcd->free_hc_list, channel,
394 * Added for Descriptor DMA to prevent channel double cleanup
395 * in release_channel_ddma(). Which called from ep_disable
396 * when device disconnect.
404 if (dwc_otg_hcd->fops->disconnect) {
405 dwc_otg_hcd->fops->disconnect(dwc_otg_hcd);
412 * HCD Callback function for stopping the HCD.
414 * @param p void pointer to the <code>struct usb_hcd</code>
416 static int32_t dwc_otg_hcd_stop_cb(void *p)
418 dwc_otg_hcd_t *dwc_otg_hcd = p;
420 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, p);
421 dwc_otg_hcd_stop(dwc_otg_hcd);
425 #ifdef CONFIG_USB_DWC_OTG_LPM
427 * HCD Callback function for sleep of HCD.
429 * @param p void pointer to the <code>struct usb_hcd</code>
431 static int dwc_otg_hcd_sleep_cb(void *p)
433 dwc_otg_hcd_t *hcd = p;
435 dwc_otg_hcd_free_hc_from_lpm(hcd);
442 * HCD Callback function for Remote Wakeup.
444 * @param p void pointer to the <code>struct usb_hcd</code>
446 extern inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd);
447 static int dwc_otg_hcd_rem_wakeup_cb(void *p)
449 dwc_otg_hcd_t *dwc_otg_hcd = p;
450 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
452 if (dwc_otg_hcd->core_if->lx_state == DWC_OTG_L2) {
453 dwc_otg_hcd->flags.b.port_suspend_change = 1;
454 usb_hcd_resume_root_hub(hcd);
456 #ifdef CONFIG_USB_DWC_OTG_LPM
458 dwc_otg_hcd->flags.b.port_l1_change = 1;
465 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
468 void dwc_otg_hcd_stop(dwc_otg_hcd_t *hcd)
470 hprt0_data_t hprt0 = {.d32 = 0 };
471 struct dwc_otg_platform_data *pldata;
472 pldata = hcd->core_if->otg_dev->pldata;
474 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
477 * The root hub should be disconnected before this function is called.
478 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
479 * and the QH lists (via ..._hcd_endpoint_disable).
482 /* Turn off all host-specific interrupts. */
483 dwc_otg_disable_host_interrupts(hcd->core_if);
485 /* Turn off the vbus power */
486 DWC_PRINTF("PortPower off\n");
488 DWC_WRITE_REG32(hcd->core_if->host_if->hprt0, hprt0.d32);
490 if (pldata->power_enable)
491 pldata->power_enable(0);
496 int dwc_otg_hcd_urb_enqueue(dwc_otg_hcd_t *hcd,
497 dwc_otg_hcd_urb_t *dwc_otg_urb, void **ep_handle,
500 dwc_irqflags_t flags;
503 gintmsk_data_t intr_mask = {.d32 = 0 };
505 if (!hcd->flags.b.port_connect_status) {
506 /* No longer connected. */
507 DWC_DEBUG("Not connected\n");
508 return -DWC_E_NO_DEVICE;
511 qtd = dwc_otg_hcd_qtd_create(dwc_otg_urb, atomic_alloc);
513 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
514 return -DWC_E_NO_MEMORY;
516 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
518 dwc_otg_hcd_qtd_add(qtd, hcd, (dwc_otg_qh_t **) ep_handle, 1);
521 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
522 "Error status %d\n", retval);
523 dwc_otg_hcd_qtd_free(qtd);
526 DWC_READ_REG32(&hcd->core_if->core_global_regs->gintmsk);
527 if (!intr_mask.b.sofintr && retval == 0) {
528 dwc_otg_transaction_type_e tr_type;
529 if ((qtd->qh->ep_type == UE_BULK)
530 && !(qtd->urb->flags & URB_GIVEBACK_ASAP)) {
531 /* Do not schedule SG transactions until qtd has URB_GIVEBACK_ASAP set */
535 tr_type = dwc_otg_hcd_select_transactions(hcd);
536 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
537 dwc_otg_hcd_queue_transactions(hcd, tr_type);
541 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
545 int dwc_otg_hcd_urb_dequeue(dwc_otg_hcd_t *hcd,
546 dwc_otg_hcd_urb_t *dwc_otg_urb)
549 dwc_otg_qtd_t *urb_qtd;
551 urb_qtd = dwc_otg_urb->qtd;
552 if (((uint32_t) urb_qtd & 0xf0000000) == 0) {
553 DWC_PRINTF("%s error: urb_qtd is %p dwc_otg_urb %p!!!\n",
554 __func__, urb_qtd, dwc_otg_urb);
559 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
560 if (urb_qtd->in_process) {
561 dump_channel_info(hcd, qh);
565 if (urb_qtd->in_process && qh->channel) {
566 /* The QTD is in process (it has been assigned to a channel). */
567 if (hcd->flags.b.port_connect_status) {
569 * If still connected (i.e. in host mode), halt the
570 * channel so it can be used for other transfers. If
571 * no longer connected, the host registers can't be
572 * written to halt the channel since the core is in
575 dwc_otg_hc_halt(hcd->core_if, qh->channel,
576 DWC_OTG_HC_XFER_URB_DEQUEUE);
581 * Free the QTD and clean up the associated QH. Leave the QH in the
582 * schedule if it has any remaining QTDs.
585 if (!hcd->core_if->dma_desc_enable) {
586 uint8_t b = urb_qtd->in_process;
587 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
589 dwc_otg_hcd_qh_deactivate(hcd, qh, 0);
591 } else if (DWC_CIRCLEQ_EMPTY(&qh->qtd_list)) {
592 dwc_otg_hcd_qh_remove(hcd, qh);
595 dwc_otg_hcd_qtd_remove_and_free(hcd, urb_qtd, qh);
600 int dwc_otg_hcd_endpoint_disable(dwc_otg_hcd_t *hcd, void *ep_handle,
603 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
605 dwc_irqflags_t flags;
608 retval = -DWC_E_INVALID;
613 retval = -DWC_E_INVALID;
617 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
619 while (!DWC_CIRCLEQ_EMPTY(&qh->qtd_list) && retry) {
620 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
623 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
626 dwc_otg_hcd_qh_remove(hcd, qh);
628 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
630 * Split dwc_otg_hcd_qh_remove_and_free() into qh_remove
631 * and qh_free to prevent stack dump on DWC_DMA_FREE() with
632 * irq_disabled (spinlock_irqsave) in dwc_otg_hcd_desc_list_free()
633 * and dwc_otg_hcd_frame_list_alloc().
635 dwc_otg_hcd_qh_free(hcd, qh);
641 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 30)
642 int dwc_otg_hcd_endpoint_reset(dwc_otg_hcd_t *hcd, void *ep_handle)
645 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
647 return -DWC_E_INVALID;
649 qh->data_toggle = DWC_OTG_HC_PID_DATA0;
655 * HCD Callback structure for handling mode switching.
657 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
658 .start = dwc_otg_hcd_start_cb,
659 .stop = dwc_otg_hcd_stop_cb,
660 .disconnect = dwc_otg_hcd_disconnect_cb,
661 .session_start = dwc_otg_hcd_session_start_cb,
662 .resume_wakeup = dwc_otg_hcd_rem_wakeup_cb,
663 #ifdef CONFIG_USB_DWC_OTG_LPM
664 .sleep = dwc_otg_hcd_sleep_cb,
670 * Reset tasklet function
672 static void reset_tasklet_func(void *data)
674 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *) data;
675 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
678 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
680 hprt0.d32 = dwc_otg_read_hprt0(core_if);
682 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
686 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
687 dwc_otg_hcd->flags.b.port_reset_change = 1;
690 static void qh_list_free(dwc_otg_hcd_t *hcd, dwc_list_link_t *qh_list)
692 dwc_list_link_t *item;
694 dwc_irqflags_t flags;
696 if (!qh_list->next) {
697 /* The list hasn't been initialized yet. */
701 * Hold spinlock here. Not needed in that case if bellow
702 * function is being called from ISR
704 DWC_SPINLOCK_IRQSAVE(hcd->lock, &flags);
705 /* Ensure there are no QTDs or URBs left. */
706 kill_urbs_in_qh_list(hcd, qh_list);
707 DWC_SPINUNLOCK_IRQRESTORE(hcd->lock, flags);
709 DWC_LIST_FOREACH(item, qh_list) {
710 qh = DWC_LIST_ENTRY(item, dwc_otg_qh_t, qh_list_entry);
711 dwc_otg_hcd_qh_remove_and_free(hcd, qh);
716 * Exit from Hibernation if Host did not detect SRP from connected SRP capable
717 * Device during SRP time by host power up.
719 void dwc_otg_hcd_power_up(void *ptr)
721 gpwrdn_data_t gpwrdn = {.d32 = 0 };
722 dwc_otg_core_if_t *core_if = (dwc_otg_core_if_t *) ptr;
724 DWC_PRINTF("%s called\n", __FUNCTION__);
726 if (!core_if->hibernation_suspend) {
727 DWC_PRINTF("Already exited from Hibernation\n");
731 /* Switch on the voltage to the core */
732 gpwrdn.b.pwrdnswtch = 1;
733 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
738 gpwrdn.b.pwrdnrstn = 1;
739 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
742 /* Disable power clamps */
744 gpwrdn.b.pwrdnclmp = 1;
745 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
747 /* Remove reset the core signal */
749 gpwrdn.b.pwrdnrstn = 1;
750 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
753 /* Disable PMU interrupt */
755 gpwrdn.b.pmuintsel = 1;
756 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
758 core_if->hibernation_suspend = 0;
762 gpwrdn.b.pmuactv = 1;
763 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
768 gpwrdn.b.dis_vbus = 1;
769 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
771 core_if->op_state = A_HOST;
772 dwc_otg_core_init(core_if);
773 dwc_otg_enable_global_interrupts(core_if);
774 cil_hcd_start(core_if);
778 * Frees secondary storage associated with the dwc_otg_hcd structure contained
779 * in the struct usb_hcd field.
781 static void dwc_otg_hcd_free(dwc_otg_hcd_t *dwc_otg_hcd)
785 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
787 del_timers(dwc_otg_hcd);
789 /* Free memory for QH/QTD lists */
790 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
791 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
792 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
793 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
794 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
795 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
797 /* Free memory for the host channels. */
798 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
799 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
802 if (dwc_otg_hcd->core_if->hc_xfer_timer[i]) {
803 DWC_TIMER_FREE(dwc_otg_hcd->core_if->hc_xfer_timer[i]);
807 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n",
813 if (dwc_otg_hcd->core_if->dma_enable) {
814 if (dwc_otg_hcd->status_buf_dma) {
815 DWC_DMA_FREE(DWC_OTG_HCD_STATUS_BUF_SIZE,
816 dwc_otg_hcd->status_buf,
817 dwc_otg_hcd->status_buf_dma);
819 } else if (dwc_otg_hcd->status_buf != NULL) {
820 DWC_FREE(dwc_otg_hcd->status_buf);
822 DWC_SPINLOCK_FREE(dwc_otg_hcd->lock);
823 /* Set core_if's lock pointer to NULL */
824 dwc_otg_hcd->core_if->lock = NULL;
826 DWC_TIMER_FREE(dwc_otg_hcd->conn_timer);
827 DWC_TASK_FREE(dwc_otg_hcd->reset_tasklet);
829 #ifdef DWC_DEV_SRPCAP
830 if (dwc_otg_hcd->core_if->power_down == 2 &&
831 dwc_otg_hcd->core_if->pwron_timer) {
832 DWC_TIMER_FREE(dwc_otg_hcd->core_if->pwron_timer);
835 DWC_FREE(dwc_otg_hcd);
838 int dwc_otg_hcd_init(dwc_otg_hcd_t *hcd, dwc_otg_core_if_t *core_if)
845 hcd->lock = DWC_SPINLOCK_ALLOC();
847 DWC_ERROR("Could not allocate lock for pcd");
849 retval = -DWC_E_NO_MEMORY;
852 hcd->core_if = core_if;
854 /* Register the HCD CIL Callbacks */
855 dwc_otg_cil_register_hcd_callbacks(hcd->core_if,
856 &hcd_cil_callbacks, hcd);
858 /* Initialize the non-periodic schedule. */
859 DWC_LIST_INIT(&hcd->non_periodic_sched_inactive);
860 DWC_LIST_INIT(&hcd->non_periodic_sched_active);
862 /* Initialize the periodic schedule. */
863 DWC_LIST_INIT(&hcd->periodic_sched_inactive);
864 DWC_LIST_INIT(&hcd->periodic_sched_ready);
865 DWC_LIST_INIT(&hcd->periodic_sched_assigned);
866 DWC_LIST_INIT(&hcd->periodic_sched_queued);
869 * Create a host channel descriptor for each host channel implemented
870 * in the controller. Initialize the channel descriptor array.
872 DWC_CIRCLEQ_INIT(&hcd->free_hc_list);
873 num_channels = hcd->core_if->core_params->host_channels;
874 DWC_MEMSET(hcd->hc_ptr_array, 0, sizeof(hcd->hc_ptr_array));
875 for (i = 0; i < num_channels; i++) {
876 channel = DWC_ALLOC(sizeof(dwc_hc_t));
877 if (channel == NULL) {
878 retval = -DWC_E_NO_MEMORY;
879 DWC_ERROR("%s: host channel allocation failed\n",
881 dwc_otg_hcd_free(hcd);
885 hcd->hc_ptr_array[i] = channel;
887 hcd->core_if->hc_xfer_timer[i] =
888 DWC_TIMER_ALLOC("hc timer", hc_xfer_timeout,
889 &hcd->core_if->hc_xfer_info[i]);
891 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i,
895 /* Initialize the Connection timeout timer. */
896 hcd->conn_timer = DWC_TIMER_ALLOC("Connection timer",
897 dwc_otg_hcd_connect_timeout, hcd);
899 /* Initialize reset tasklet. */
901 DWC_TASK_ALLOC("reset_tasklet", reset_tasklet_func, hcd);
902 #ifdef DWC_DEV_SRPCAP
903 if (hcd->core_if->power_down == 2) {
904 /* Initialize Power on timer for Host power up in case hibernation */
905 hcd->core_if->pwron_timer = DWC_TIMER_ALLOC("PWRON TIMER",
906 dwc_otg_hcd_power_up,
912 * Allocate space for storing data on status transactions. Normally no
913 * data is sent, but this space acts as a bit bucket. This must be
914 * done after usb_add_hcd since that function allocates the DMA buffer
917 if (hcd->core_if->dma_enable) {
919 DWC_DMA_ALLOC_ATOMIC(DWC_OTG_HCD_STATUS_BUF_SIZE,
920 &hcd->status_buf_dma);
922 hcd->status_buf = DWC_ALLOC(DWC_OTG_HCD_STATUS_BUF_SIZE);
924 if (!hcd->status_buf) {
925 retval = -DWC_E_NO_MEMORY;
926 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
927 dwc_otg_hcd_free(hcd);
932 hcd->frame_list = NULL;
933 hcd->frame_list_dma = 0;
934 hcd->periodic_qh_count = 0;
939 void dwc_otg_hcd_remove(dwc_otg_hcd_t *hcd)
941 /* Turn off all host-specific interrupts. */
942 dwc_otg_disable_host_interrupts(hcd->core_if);
944 dwc_otg_hcd_free(hcd);
948 * Initializes dynamic portions of the DWC_otg HCD state.
950 static void dwc_otg_hcd_reinit(dwc_otg_hcd_t *hcd)
955 dwc_hc_t *channel_tmp;
959 hcd->non_periodic_qh_ptr = &hcd->non_periodic_sched_active;
960 hcd->non_periodic_channels = 0;
961 hcd->periodic_channels = 0;
964 * Put all channels in the free channel list and clean up channel
967 DWC_CIRCLEQ_FOREACH_SAFE(channel, channel_tmp,
968 &hcd->free_hc_list, hc_list_entry) {
969 DWC_CIRCLEQ_REMOVE(&hcd->free_hc_list, channel, hc_list_entry);
972 num_channels = hcd->core_if->core_params->host_channels;
973 for (i = 0; i < num_channels; i++) {
974 channel = hcd->hc_ptr_array[i];
975 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, channel,
977 dwc_otg_hc_cleanup(hcd->core_if, channel);
980 /* Initialize the DWC core for host mode operation. */
981 dwc_otg_core_host_init(hcd->core_if);
983 /* Set core_if's lock pointer to the hcd->lock */
984 hcd->core_if->lock = hcd->lock;
988 * Assigns transactions from a QTD to a free host channel and initializes the
989 * host channel to perform the transactions. The host channel is removed from
992 * @param hcd The HCD state structure.
993 * @param qh Transactions from the first QTD for this QH are selected and
994 * assigned to a free host channel.
996 static int assign_and_init_hc(dwc_otg_hcd_t *hcd, dwc_otg_qh_t *qh)
1000 dwc_otg_hcd_urb_t *urb;
1004 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, hcd, qh);
1006 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
1008 /* Remove the host channel from the free list. */
1009 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
1011 qtd = DWC_CIRCLEQ_FIRST(&qh->qtd_list);
1015 printk("%s : urb is NULL\n", __func__);
1022 qtd->in_process = 1;
1025 * Use usb_pipedevice to determine device address. This address is
1026 * 0 before the SET_ADDRESS command and the correct address afterward.
1028 hc->dev_addr = dwc_otg_hcd_get_dev_addr(&urb->pipe_info);
1029 hc->ep_num = dwc_otg_hcd_get_ep_num(&urb->pipe_info);
1030 hc->speed = qh->dev_speed;
1031 hc->max_packet = dwc_max_packet(qh->maxp);
1033 hc->xfer_started = 0;
1034 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1035 hc->error_state = (qtd->error_count > 0);
1036 hc->halt_on_queue = 0;
1037 hc->halt_pending = 0;
1041 * The following values may be modified in the transfer type section
1042 * below. The xfer_len value may be reduced when the transfer is
1043 * started to accommodate the max widths of the XferSize and PktCnt
1044 * fields in the HCTSIZn register.
1047 hc->ep_is_in = (dwc_otg_hcd_is_pipe_in(&urb->pipe_info) != 0);
1051 hc->do_ping = qh->ping_state;
1053 hc->data_pid_start = qh->data_toggle;
1054 hc->multi_count = 1;
1056 if (hcd->core_if->dma_enable) {
1057 hc->xfer_buff = (uint8_t *) urb->dma + urb->actual_length;
1059 /* For non-dword aligned case */
1060 if (((unsigned long)hc->xfer_buff & 0x3)
1061 && !hcd->core_if->dma_desc_enable) {
1062 ptr = (uint8_t *) urb->buf + urb->actual_length;
1065 hc->xfer_buff = (uint8_t *) urb->buf + urb->actual_length;
1067 hc->xfer_len = urb->length - urb->actual_length;
1071 * Set the split attributes
1075 uint32_t hub_addr, port_addr;
1077 hc->xact_pos = qtd->isoc_split_pos;
1078 hc->complete_split = qtd->complete_split;
1079 hcd->fops->hub_info(hcd, urb->priv, &hub_addr, &port_addr);
1080 hc->hub_addr = (uint8_t) hub_addr;
1081 hc->port_addr = (uint8_t) port_addr;
1084 switch (dwc_otg_hcd_get_pipe_type(&urb->pipe_info)) {
1086 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
1087 switch (qtd->control_phase) {
1088 case DWC_OTG_CONTROL_SETUP:
1089 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
1092 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
1093 if (hcd->core_if->dma_enable)
1094 hc->xfer_buff = (uint8_t *) urb->setup_dma;
1096 hc->xfer_buff = (uint8_t *) urb->setup_packet;
1101 case DWC_OTG_CONTROL_DATA:
1102 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
1103 hc->data_pid_start = qtd->data_toggle;
1105 case DWC_OTG_CONTROL_STATUS:
1107 * Direction is opposite of data direction or IN if no
1110 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
1111 if (urb->length == 0) {
1115 dwc_otg_hcd_is_pipe_out(&urb->pipe_info);
1120 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
1123 if (hcd->core_if->dma_enable)
1124 hc->xfer_buff = (uint8_t *) hcd->status_buf_dma;
1126 hc->xfer_buff = (uint8_t *) hcd->status_buf;
1133 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
1136 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
1138 case UE_ISOCHRONOUS:
1140 struct dwc_otg_hcd_iso_packet_desc *frame_desc;
1142 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
1144 if (hcd->core_if->dma_desc_enable)
1147 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
1149 frame_desc->status = 0;
1151 if (hcd->core_if->dma_enable) {
1152 hc->xfer_buff = (uint8_t *) urb->dma;
1154 hc->xfer_buff = (uint8_t *) urb->buf;
1157 frame_desc->offset + qtd->isoc_split_offset;
1159 frame_desc->length - qtd->isoc_split_offset;
1161 /* For non-dword aligned buffers */
1162 if (((unsigned long)hc->xfer_buff & 0x3)
1163 && hcd->core_if->dma_enable) {
1165 (uint8_t *) urb->buf + frame_desc->offset +
1166 qtd->isoc_split_offset;
1170 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
1171 if (hc->xfer_len <= 188) {
1172 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
1175 DWC_HCSPLIT_XACTPOS_BEGIN;
1181 /* non DWORD-aligned buffer case */
1184 if (hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1185 buf_size = hcd->core_if->core_params->max_transfer_size;
1189 if (!qh->dw_align_buf) {
1190 qh->dw_align_buf = DWC_DMA_ALLOC_ATOMIC(buf_size,
1193 if (!qh->dw_align_buf) {
1195 ("%s: Failed to allocate memory to handle "
1196 "non-dword aligned buffer case\n",
1201 if (!hc->ep_is_in) {
1202 dwc_memcpy(qh->dw_align_buf, ptr, hc->xfer_len);
1204 hc->align_buff = qh->dw_align_buf_dma;
1209 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1210 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1212 * This value may be modified when the transfer is started to
1213 * reflect the actual transfer length.
1215 hc->multi_count = dwc_hb_mult(qh->maxp);
1218 if (hcd->core_if->dma_desc_enable)
1219 hc->desc_list_addr = qh->desc_list_dma;
1221 dwc_otg_hc_init(hcd->core_if, hc);
1227 * This function selects transactions from the HCD transfer schedule and
1228 * assigns them to available host channels. It is called from HCD interrupt
1229 * handler functions.
1231 * @param hcd The HCD state structure.
1233 * @return The types of new transactions that were assigned to host channels.
1235 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *hcd)
1237 dwc_list_link_t *qh_ptr;
1240 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
1244 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
1247 /* Process entries in the periodic ready list. */
1248 qh_ptr = DWC_LIST_FIRST(&hcd->periodic_sched_ready);
1250 while (qh_ptr != &hcd->periodic_sched_ready &&
1251 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1253 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1254 assign_and_init_hc(hcd, qh);
1257 * Move the QH from the periodic ready schedule to the
1258 * periodic assigned schedule.
1260 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1261 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_assigned,
1262 &qh->qh_list_entry);
1264 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
1268 * Process entries in the inactive portion of the non-periodic
1269 * schedule. Some free host channels may not be used if they are
1270 * reserved for periodic transfers.
1272 qh_ptr = hcd->non_periodic_sched_inactive.next;
1273 num_channels = hcd->core_if->core_params->host_channels;
1274 while (qh_ptr != &hcd->non_periodic_sched_inactive &&
1275 (hcd->non_periodic_channels <
1276 num_channels - hcd->periodic_channels) &&
1277 !DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
1279 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1281 err = assign_and_init_hc(hcd, qh);
1284 * Move the QH from the non-periodic inactive schedule to the
1285 * non-periodic active schedule.
1287 qh_ptr = DWC_LIST_NEXT(qh_ptr);
1290 DWC_LIST_MOVE_HEAD(&hcd->non_periodic_sched_active,
1291 &qh->qh_list_entry);
1293 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
1294 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
1296 ret_val = DWC_OTG_TRANSACTION_ALL;
1299 hcd->non_periodic_channels++;
1306 * Attempts to queue a single transaction request for a host channel
1307 * associated with either a periodic or non-periodic transfer. This function
1308 * assumes that there is space available in the appropriate request queue. For
1309 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
1310 * is available in the appropriate Tx FIFO.
1312 * @param hcd The HCD state structure.
1313 * @param hc Host channel descriptor associated with either a periodic or
1314 * non-periodic transfer.
1315 * @param fifo_dwords_avail Number of DWORDs available in the periodic Tx
1316 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
1319 * @return 1 if a request is queued and more requests may be needed to
1320 * complete the transfer, 0 if no more requests are required for this
1321 * transfer, -1 if there is insufficient space in the Tx FIFO.
1323 static int queue_transaction(dwc_otg_hcd_t *hcd,
1324 dwc_hc_t *hc, uint16_t fifo_dwords_avail)
1328 if (hcd->core_if->dma_enable) {
1329 if (hcd->core_if->dma_desc_enable) {
1330 if (!hc->xfer_started
1331 || (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1332 dwc_otg_hcd_start_xfer_ddma(hcd, hc->qh);
1333 hc->qh->ping_state = 0;
1335 } else if (!hc->xfer_started) {
1336 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1337 hc->qh->ping_state = 0;
1340 } else if (hc->halt_pending) {
1341 /* Don't queue a request if the channel has been halted. */
1343 } else if (hc->halt_on_queue) {
1344 dwc_otg_hc_halt(hcd->core_if, hc, hc->halt_status);
1346 } else if (hc->do_ping) {
1347 if (!hc->xfer_started) {
1348 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1351 } else if (!hc->ep_is_in || hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
1352 if ((fifo_dwords_avail * 4) >= hc->max_packet) {
1353 if (!hc->xfer_started) {
1354 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1358 dwc_otg_hc_continue_transfer(hcd->core_if,
1365 if (!hc->xfer_started) {
1366 dwc_otg_hc_start_transfer(hcd->core_if, hc);
1369 retval = dwc_otg_hc_continue_transfer(hcd->core_if, hc);
1377 * Processes periodic channels for the next frame and queues transactions for
1378 * these channels to the DWC_otg controller. After queueing transactions, the
1379 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1380 * to queue as Periodic Tx FIFO or request queue space becomes available.
1381 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1383 static void process_periodic_channels(dwc_otg_hcd_t *hcd)
1385 hptxsts_data_t tx_status;
1386 dwc_list_link_t *qh_ptr;
1389 int no_queue_space = 0;
1390 int no_fifo_space = 0;
1392 dwc_otg_host_global_regs_t *host_regs;
1393 host_regs = hcd->core_if->host_if->host_global_regs;
1395 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
1397 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1398 DWC_DEBUGPL(DBG_HCDV,
1399 " P Tx Req Queue Space Avail (before queue): %d\n",
1400 tx_status.b.ptxqspcavail);
1401 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
1402 tx_status.b.ptxfspcavail);
1405 qh_ptr = hcd->periodic_sched_assigned.next;
1406 while (qh_ptr != &hcd->periodic_sched_assigned) {
1407 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1408 if (tx_status.b.ptxqspcavail == 0) {
1413 qh = DWC_LIST_ENTRY(qh_ptr, dwc_otg_qh_t, qh_list_entry);
1416 * Set a flag if we're queuing high-bandwidth in slave mode.
1417 * The flag prevents any halts to get into the request queue in
1418 * the middle of multiple high-bandwidth packets getting queued.
1420 if (!hcd->core_if->dma_enable && qh->channel->multi_count > 1) {
1421 hcd->core_if->queuing_high_bandwidth = 1;
1424 queue_transaction(hcd, qh->channel,
1425 tx_status.b.ptxfspcavail);
1432 * In Slave mode, stay on the current transfer until there is
1433 * nothing more to do or the high-bandwidth request count is
1434 * reached. In DMA mode, only need to queue one request. The
1435 * controller automatically handles multiple packets for
1436 * high-bandwidth transfers.
1438 if (hcd->core_if->dma_enable || status == 0 ||
1439 qh->channel->requests == qh->channel->multi_count) {
1440 qh_ptr = qh_ptr->next;
1442 * Move the QH from the periodic assigned schedule to
1443 * the periodic queued schedule.
1445 DWC_LIST_MOVE_HEAD(&hcd->periodic_sched_queued,
1446 &qh->qh_list_entry);
1448 /* done queuing high bandwidth */
1449 hcd->core_if->queuing_high_bandwidth = 0;
1453 if (!hcd->core_if->dma_enable) {
1454 dwc_otg_core_global_regs_t *global_regs;
1455 gintmsk_data_t intr_mask = {.d32 = 0 };
1457 global_regs = hcd->core_if->core_global_regs;
1458 intr_mask.b.ptxfempty = 1;
1460 tx_status.d32 = DWC_READ_REG32(&host_regs->hptxsts);
1461 DWC_DEBUGPL(DBG_HCDV,
1462 " P Tx Req Queue Space Avail (after queue): %d\n",
1463 tx_status.b.ptxqspcavail);
1464 DWC_DEBUGPL(DBG_HCDV,
1465 " P Tx FIFO Space Avail (after queue): %d\n",
1466 tx_status.b.ptxfspcavail);
1468 if (!DWC_LIST_EMPTY(&hcd->periodic_sched_assigned) ||
1469 no_queue_space || no_fifo_space) {
1471 * May need to queue more transactions as the request
1472 * queue or Tx FIFO empties. Enable the periodic Tx
1473 * FIFO empty interrupt. (Always use the half-empty
1474 * level to ensure that new requests are loaded as
1475 * soon as possible.)
1477 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1481 * Disable the Tx FIFO empty interrupt since there are
1482 * no more transactions that need to be queued right
1483 * now. This function is called from interrupt
1484 * handlers to queue more transactions as transfer
1487 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1494 * Processes active non-periodic channels and queues transactions for these
1495 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1496 * FIFO Empty interrupt is enabled if there are more transactions to queue as
1497 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1498 * FIFO Empty interrupt is disabled.
1500 static void process_non_periodic_channels(dwc_otg_hcd_t *hcd)
1502 gnptxsts_data_t tx_status;
1503 dwc_list_link_t *orig_qh_ptr;
1506 int no_queue_space = 0;
1507 int no_fifo_space = 0;
1510 dwc_otg_core_global_regs_t *global_regs =
1511 hcd->core_if->core_global_regs;
1513 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
1515 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1516 DWC_DEBUGPL(DBG_HCDV,
1517 " NP Tx Req Queue Space Avail (before queue): %d\n",
1518 tx_status.b.nptxqspcavail);
1519 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
1520 tx_status.b.nptxfspcavail);
1523 * Keep track of the starting point. Skip over the start-of-list
1526 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1527 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1529 orig_qh_ptr = hcd->non_periodic_qh_ptr;
1532 * Process once through the active list or until no more space is
1533 * available in the request queue or the Tx FIFO.
1536 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1537 if (!hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
1542 qh = DWC_LIST_ENTRY(hcd->non_periodic_qh_ptr, dwc_otg_qh_t,
1545 queue_transaction(hcd, qh->channel,
1546 tx_status.b.nptxfspcavail);
1550 } else if (status < 0) {
1555 /* Advance to next QH, skipping start-of-list entry. */
1556 hcd->non_periodic_qh_ptr = hcd->non_periodic_qh_ptr->next;
1557 if (hcd->non_periodic_qh_ptr == &hcd->non_periodic_sched_active) {
1558 hcd->non_periodic_qh_ptr =
1559 hcd->non_periodic_qh_ptr->next;
1562 } while (hcd->non_periodic_qh_ptr != orig_qh_ptr);
1564 if (!hcd->core_if->dma_enable) {
1565 gintmsk_data_t intr_mask = {.d32 = 0 };
1566 intr_mask.b.nptxfempty = 1;
1569 tx_status.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
1570 DWC_DEBUGPL(DBG_HCDV,
1571 " NP Tx Req Queue Space Avail (after queue): %d\n",
1572 tx_status.b.nptxqspcavail);
1573 DWC_DEBUGPL(DBG_HCDV,
1574 " NP Tx FIFO Space Avail (after queue): %d\n",
1575 tx_status.b.nptxfspcavail);
1577 if (more_to_do || no_queue_space || no_fifo_space) {
1579 * May need to queue more transactions as the request
1580 * queue or Tx FIFO empties. Enable the non-periodic
1581 * Tx FIFO empty interrupt. (Always use the half-empty
1582 * level to ensure that new requests are loaded as
1583 * soon as possible.)
1585 DWC_MODIFY_REG32(&global_regs->gintmsk, 0,
1589 * Disable the Tx FIFO empty interrupt since there are
1590 * no more transactions that need to be queued right
1591 * now. This function is called from interrupt
1592 * handlers to queue more transactions as transfer
1595 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32,
1602 * This function processes the currently active host channels and queues
1603 * transactions for these channels to the DWC_otg controller. It is called
1604 * from HCD interrupt handler functions.
1606 * @param hcd The HCD state structure.
1607 * @param tr_type The type(s) of transactions to queue (non-periodic,
1608 * periodic, or both).
1610 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *hcd,
1611 dwc_otg_transaction_type_e tr_type)
1614 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
1616 /* Process host channels associated with periodic transfers. */
1617 if ((tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
1618 tr_type == DWC_OTG_TRANSACTION_ALL) &&
1619 !DWC_LIST_EMPTY(&hcd->periodic_sched_assigned)) {
1621 process_periodic_channels(hcd);
1624 /* Process host channels associated with non-periodic transfers. */
1625 if (tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
1626 tr_type == DWC_OTG_TRANSACTION_ALL) {
1627 if (!DWC_LIST_EMPTY(&hcd->non_periodic_sched_active)) {
1628 process_non_periodic_channels(hcd);
1631 * Ensure NP Tx FIFO empty interrupt is disabled when
1632 * there are no non-periodic transfers to process.
1634 gintmsk_data_t gintmsk = {.d32 = 0 };
1635 gintmsk.b.nptxfempty = 1;
1636 DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->
1637 gintmsk, gintmsk.d32, 0);
1642 #ifdef DWC_HS_ELECT_TST
1644 * Quick and dirty hack to implement the HS Electrical Test
1645 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1647 * This code was copied from our userspace app "hset". It sends a
1648 * Get Device Descriptor control sequence in two parts, first the
1649 * Setup packet by itself, followed some time later by the In and
1650 * Ack packets. Rather than trying to figure out how to add this
1651 * functionality to the normal driver code, we just hijack the
1652 * hardware, using these two function to drive the hardware
1656 static dwc_otg_core_global_regs_t *global_regs;
1657 static dwc_otg_host_global_regs_t *hc_global_regs;
1658 static dwc_otg_hc_regs_t *hc_regs;
1659 static uint32_t *data_fifo;
1661 static void do_setup(void)
1663 gintsts_data_t gintsts;
1664 hctsiz_data_t hctsiz;
1665 hcchar_data_t hcchar;
1670 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1673 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1676 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1679 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1682 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1685 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1688 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1691 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1694 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1697 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1700 * Send Setup packet (Get Device Descriptor)
1703 /* Make sure channel is disabled */
1704 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1705 if (hcchar.b.chen) {
1707 /* hcchar.b.chen = 1; */
1708 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1713 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1716 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1719 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1722 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1725 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1728 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1731 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1733 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1738 hctsiz.b.xfersize = 8;
1739 hctsiz.b.pktcnt = 1;
1740 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1741 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1744 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1745 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1750 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1752 /* Fill FIFO with Setup data for Get Device Descriptor */
1753 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1754 DWC_WRITE_REG32(data_fifo++, 0x01000680);
1755 DWC_WRITE_REG32(data_fifo++, 0x00080000);
1757 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1759 /* Wait for host channel interrupt */
1761 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1762 } while (gintsts.b.hcintr == 0);
1764 /* Disable HCINTs */
1765 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
1767 /* Disable HAINTs */
1768 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
1771 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1774 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1777 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1780 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1783 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1786 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1789 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1792 static void do_in_ack(void)
1794 gintsts_data_t gintsts;
1795 hctsiz_data_t hctsiz;
1796 hcchar_data_t hcchar;
1799 host_grxsts_data_t grxsts;
1802 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0001);
1805 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x04a3);
1808 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1811 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1814 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1817 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1820 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1823 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1826 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1829 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1832 * Receive Control In packet
1835 /* Make sure channel is disabled */
1836 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1837 if (hcchar.b.chen) {
1840 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1845 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1848 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1851 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1854 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1857 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1860 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1863 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1865 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1870 hctsiz.b.xfersize = 8;
1871 hctsiz.b.pktcnt = 1;
1872 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1873 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
1876 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1877 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1882 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
1884 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1886 /* Wait for receive status queue interrupt */
1888 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1889 } while (gintsts.b.rxstsqlvl == 0);
1892 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1894 /* Clear RXSTSQLVL in GINTSTS */
1896 gintsts.b.rxstsqlvl = 1;
1897 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1899 switch (grxsts.b.pktsts) {
1900 case DWC_GRXSTS_PKTSTS_IN:
1901 /* Read the data into the host buffer */
1902 if (grxsts.b.bcnt > 0) {
1904 int word_count = (grxsts.b.bcnt + 3) / 4;
1906 data_fifo = (uint32_t *) ((char *)global_regs + 0x1000);
1908 for (i = 0; i < word_count; i++) {
1909 (void)DWC_READ_REG32(data_fifo++);
1918 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1920 /* Wait for receive status queue interrupt */
1922 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1923 } while (gintsts.b.rxstsqlvl == 0);
1926 grxsts.d32 = DWC_READ_REG32(&global_regs->grxstsp);
1928 /* Clear RXSTSQLVL in GINTSTS */
1930 gintsts.b.rxstsqlvl = 1;
1931 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1933 switch (grxsts.b.pktsts) {
1934 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1941 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1943 /* Wait for host channel interrupt */
1945 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1946 } while (gintsts.b.hcintr == 0);
1949 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1952 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1955 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1958 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1961 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1964 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1967 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1969 /* usleep(100000); */
1974 * Send handshake packet
1978 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
1981 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
1984 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
1987 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
1990 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
1993 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
1996 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
1998 /* Make sure channel is disabled */
1999 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2000 if (hcchar.b.chen) {
2003 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2008 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2011 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2014 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2017 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2020 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2023 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2026 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2028 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2033 hctsiz.b.xfersize = 0;
2034 hctsiz.b.pktcnt = 1;
2035 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2036 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2039 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2040 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2045 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2047 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2049 /* Wait for host channel interrupt */
2051 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2052 } while (gintsts.b.hcintr == 0);
2054 /* Disable HCINTs */
2055 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0x0000);
2057 /* Disable HAINTs */
2058 DWC_WRITE_REG32(&hc_global_regs->haintmsk, 0x0000);
2061 haint.d32 = DWC_READ_REG32(&hc_global_regs->haint);
2064 hcint.d32 = DWC_READ_REG32(&hc_regs->hcint);
2067 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2070 DWC_WRITE_REG32(&hc_regs->hcint, hcint.d32);
2073 DWC_WRITE_REG32(&hc_global_regs->haint, haint.d32);
2076 DWC_WRITE_REG32(&global_regs->gintsts, gintsts.d32);
2079 gintsts.d32 = DWC_READ_REG32(&global_regs->gintsts);
2083 /** Handles hub class-specific requests. */
2084 int dwc_otg_hcd_hub_control(dwc_otg_hcd_t *dwc_otg_hcd,
2087 uint16_t wIndex, uint8_t *buf, uint16_t wLength)
2091 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
2092 usb_hub_descriptor_t *hub_desc;
2093 hprt0_data_t hprt0 = {.d32 = 0 };
2095 uint32_t port_status;
2098 case UCR_CLEAR_HUB_FEATURE:
2099 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2100 "ClearHubFeature 0x%x\n", wValue);
2102 case UHF_C_HUB_LOCAL_POWER:
2103 case UHF_C_HUB_OVER_CURRENT:
2104 /* Nothing required here */
2107 retval = -DWC_E_INVALID;
2108 DWC_ERROR("DWC OTG HCD - "
2109 "ClearHubFeature request %xh unknown\n",
2113 case UCR_CLEAR_PORT_FEATURE:
2114 #ifdef CONFIG_USB_DWC_OTG_LPM
2115 if (wValue != UHF_PORT_L1)
2117 if (!wIndex || wIndex > 1)
2121 case UHF_PORT_ENABLE:
2122 DWC_DEBUGPL(DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2123 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2124 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2126 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2128 case UHF_PORT_SUSPEND:
2129 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2130 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2132 if (core_if->power_down == 2) {
2133 dwc_otg_host_hibernation_restore(core_if, 0, 0);
2135 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2138 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2140 DWC_WRITE_REG32(core_if->host_if->hprt0,
2142 hprt0.b.prtsusp = 0;
2143 /* Clear Resume bit */
2146 DWC_WRITE_REG32(core_if->host_if->hprt0,
2150 #ifdef CONFIG_USB_DWC_OTG_LPM
2153 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2154 glpmcfg_data_t lpmcfg = {.d32 = 0 };
2157 DWC_READ_REG32(&core_if->core_global_regs->
2159 lpmcfg.b.en_utmi_sleep = 0;
2160 lpmcfg.b.hird_thres &= (~(1 << 4));
2161 lpmcfg.b.prt_sleep_sts = 1;
2162 DWC_WRITE_REG32(&core_if->core_global_regs->
2163 glpmcfg, lpmcfg.d32);
2165 /* Clear Enbl_L1Gating bit. */
2166 pcgcctl.b.enbl_sleep_gating = 1;
2167 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2172 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2174 DWC_WRITE_REG32(core_if->host_if->hprt0,
2176 /* This bit will be cleared in wakeup interrupt handle */
2180 case UHF_PORT_POWER:
2181 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2182 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2183 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2185 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2187 case UHF_PORT_INDICATOR:
2188 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2189 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2190 /* Port inidicator not supported */
2192 case UHF_C_PORT_CONNECTION:
2193 /* Clears drivers internal connect status change
2195 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2196 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2197 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2199 case UHF_C_PORT_RESET:
2200 /* Clears the driver's internal Port Reset Change
2202 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2203 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2204 dwc_otg_hcd->flags.b.port_reset_change = 0;
2206 case UHF_C_PORT_ENABLE:
2207 /* Clears the driver's internal Port
2208 * Enable/Disable Change flag */
2209 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2210 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2211 dwc_otg_hcd->flags.b.port_enable_change = 0;
2213 case UHF_C_PORT_SUSPEND:
2214 /* Clears the driver's internal Port Suspend
2215 * Change flag, which is set when resume signaling on
2216 * the host port is complete */
2217 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2218 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2219 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2221 #ifdef CONFIG_USB_DWC_OTG_LPM
2223 dwc_otg_hcd->flags.b.port_l1_change = 0;
2226 case UHF_C_PORT_OVER_CURRENT:
2227 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2228 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2229 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2232 retval = -DWC_E_INVALID;
2233 DWC_ERROR("DWC OTG HCD - "
2234 "ClearPortFeature request %xh "
2235 "unknown or unsupported\n", wValue);
2238 case UCR_GET_HUB_DESCRIPTOR:
2239 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2240 "GetHubDescriptor\n");
2241 hub_desc = (usb_hub_descriptor_t *) buf;
2242 hub_desc->bDescLength = 9;
2243 hub_desc->bDescriptorType = 0x29;
2244 hub_desc->bNbrPorts = 1;
2245 USETW(hub_desc->wHubCharacteristics, 0x08);
2246 hub_desc->bPwrOn2PwrGood = 1;
2247 hub_desc->bHubContrCurrent = 0;
2248 hub_desc->DeviceRemovable[0] = 0;
2249 hub_desc->DeviceRemovable[1] = 0xff;
2251 case UCR_GET_HUB_STATUS:
2252 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2254 DWC_MEMSET(buf, 0, 4);
2256 case UCR_GET_PORT_STATUS:
2257 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2258 "GetPortStatus wIndex = 0x%04x FLAGS=0x%08x\n",
2259 wIndex, dwc_otg_hcd->flags.d32);
2260 if (!wIndex || wIndex > 1)
2265 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2266 port_status |= (1 << UHF_C_PORT_CONNECTION);
2268 if (dwc_otg_hcd->flags.b.port_enable_change)
2269 port_status |= (1 << UHF_C_PORT_ENABLE);
2271 if (dwc_otg_hcd->flags.b.port_suspend_change)
2272 port_status |= (1 << UHF_C_PORT_SUSPEND);
2274 if (dwc_otg_hcd->flags.b.port_l1_change)
2275 port_status |= (1 << UHF_C_PORT_L1);
2277 if (dwc_otg_hcd->flags.b.port_reset_change) {
2278 port_status |= (1 << UHF_C_PORT_RESET);
2281 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2282 DWC_WARN("Overcurrent change detected\n");
2283 port_status |= (1 << UHF_C_PORT_OVER_CURRENT);
2286 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2288 * The port is disconnected, which means the core is
2289 * either in device mode or it soon will be. Just
2290 * return 0's for the remainder of the port status
2291 * since the port register can't be read if the core
2292 * is in device mode.
2294 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2298 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
2299 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2301 if (hprt0.b.prtconnsts)
2302 port_status |= (1 << UHF_PORT_CONNECTION);
2305 port_status |= (1 << UHF_PORT_ENABLE);
2307 if (hprt0.b.prtsusp)
2308 port_status |= (1 << UHF_PORT_SUSPEND);
2310 if (hprt0.b.prtovrcurract)
2311 port_status |= (1 << UHF_PORT_OVER_CURRENT);
2314 port_status |= (1 << UHF_PORT_RESET);
2317 port_status |= (1 << UHF_PORT_POWER);
2319 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2320 port_status |= (1 << UHF_PORT_HIGH_SPEED);
2321 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2322 port_status |= (1 << UHF_PORT_LOW_SPEED);
2324 if (hprt0.b.prttstctl)
2325 port_status |= (1 << UHF_PORT_TEST);
2326 if (dwc_otg_get_lpm_portsleepstatus(dwc_otg_hcd->core_if)) {
2327 port_status |= (1 << UHF_PORT_L1);
2330 For Synopsys HW emulation of Power down wkup_control asserts the
2331 hreset_n and prst_n on suspned. This causes the HPRT0 to be zero.
2332 We intentionally tell the software that port is in L2Suspend state.
2335 if ((core_if->power_down == 2)
2336 && (core_if->hibernation_suspend == 1)) {
2337 port_status |= (1 << UHF_PORT_SUSPEND);
2339 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2341 *((__le32 *) buf) = dwc_cpu_to_le32(&port_status);
2344 case UCR_SET_HUB_FEATURE:
2345 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2347 /* No HUB features supported */
2349 case UCR_SET_PORT_FEATURE:
2350 if (wValue != UHF_PORT_TEST && (!wIndex || wIndex > 1))
2353 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2355 * The port is disconnected, which means the core is
2356 * either in device mode or it soon will be. Just
2357 * return without doing anything since the port
2358 * register can't be written if the core is in device
2365 case UHF_PORT_SUSPEND:
2366 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2367 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2368 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) != wIndex) {
2371 if (core_if->power_down == 2) {
2373 dwc_irqflags_t flags;
2374 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2375 gpwrdn_data_t gpwrdn = {.d32 = 0 };
2376 gusbcfg_data_t gusbcfg = {.d32 = 0 };
2377 #ifdef DWC_DEV_SRPCAP
2378 int32_t otg_cap_param =
2379 core_if->core_params->otg_cap;
2382 ("Preparing for complete power-off\n");
2384 /* Save registers before hibernation */
2385 dwc_otg_save_global_regs(core_if);
2386 dwc_otg_save_host_regs(core_if);
2388 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2389 hprt0.b.prtsusp = 1;
2391 DWC_WRITE_REG32(core_if->host_if->hprt0,
2393 /* Spin hprt0.b.prtsusp to became 1 */
2395 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2396 if (hprt0.b.prtsusp) {
2400 } while (--timeout);
2402 DWC_WARN("Suspend wasn't genereted\n");
2407 * We need to disable interrupts to prevent servicing of any IRQ
2408 * during going to hibernation
2410 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2411 core_if->lx_state = DWC_OTG_L2;
2412 #ifdef DWC_DEV_SRPCAP
2413 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2416 DWC_WRITE_REG32(core_if->host_if->hprt0,
2420 DWC_READ_REG32(&core_if->
2421 core_global_regs->gusbcfg);
2422 if (gusbcfg.b.ulpi_utmi_sel == 1) {
2423 /* ULPI interface */
2424 /* Suspend the Phy Clock */
2426 pcgcctl.b.stoppclk = 1;
2427 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2430 gpwrdn.b.pmuactv = 1;
2432 (&core_if->core_global_regs->gpwrdn,
2435 /* UTMI+ Interface */
2436 gpwrdn.b.pmuactv = 1;
2438 (&core_if->core_global_regs->gpwrdn,
2441 pcgcctl.b.stoppclk = 1;
2442 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2446 #ifdef DWC_DEV_SRPCAP
2448 gpwrdn.b.dis_vbus = 1;
2449 DWC_MODIFY_REG32(&core_if->
2450 core_global_regs->gpwrdn, 0,
2454 gpwrdn.b.pmuintsel = 1;
2455 DWC_MODIFY_REG32(&core_if->
2456 core_global_regs->gpwrdn, 0,
2461 #ifdef DWC_DEV_SRPCAP
2462 gpwrdn.b.srp_det_msk = 1;
2464 gpwrdn.b.disconn_det_msk = 1;
2465 gpwrdn.b.lnstchng_msk = 1;
2466 gpwrdn.b.sts_chngint_msk = 1;
2467 DWC_MODIFY_REG32(&core_if->
2468 core_global_regs->gpwrdn, 0,
2472 /* Enable Power Down Clamp and all interrupts in GPWRDN */
2474 gpwrdn.b.pwrdnclmp = 1;
2475 DWC_MODIFY_REG32(&core_if->
2476 core_global_regs->gpwrdn, 0,
2480 /* Switch off VDD */
2482 gpwrdn.b.pwrdnswtch = 1;
2483 DWC_MODIFY_REG32(&core_if->
2484 core_global_regs->gpwrdn, 0,
2487 #ifdef DWC_DEV_SRPCAP
2488 if (otg_cap_param ==
2489 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE) {
2490 core_if->pwron_timer_started = 1;
2491 DWC_TIMER_SCHEDULE(core_if->pwron_timer,
2495 /* Save gpwrdn register for further usage if stschng interrupt */
2496 core_if->gr_backup->gpwrdn_local =
2497 DWC_READ_REG32(&core_if->core_global_regs->
2500 /* Set flag to indicate that we are in hibernation */
2501 core_if->hibernation_suspend = 1;
2502 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2505 DWC_PRINTF("Host hibernation completed\n");
2506 /* Exit from case statement */
2510 if (dwc_otg_hcd_otg_port(dwc_otg_hcd) == wIndex &&
2511 dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2512 gotgctl_data_t gotgctl = {.d32 = 0 };
2513 gotgctl.b.hstsethnpen = 1;
2514 DWC_MODIFY_REG32(&core_if->
2515 core_global_regs->gotgctl, 0,
2517 core_if->op_state = A_SUSPEND;
2519 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2520 hprt0.b.prtsusp = 1;
2521 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2523 dwc_irqflags_t flags;
2524 /* Update lx_state */
2525 DWC_SPINLOCK_IRQSAVE(dwc_otg_hcd->lock, &flags);
2526 core_if->lx_state = DWC_OTG_L2;
2527 DWC_SPINUNLOCK_IRQRESTORE(dwc_otg_hcd->lock,
2530 /* Suspend the Phy Clock */
2531 if (core_if->otg_ver == 0) {
2532 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2533 pcgcctl.b.stoppclk = 1;
2534 DWC_MODIFY_REG32(core_if->pcgcctl, 0,
2539 /* For HNP the bus must be suspended for at least 200ms. */
2540 if (dwc_otg_hcd->fops->get_b_hnp_enable(dwc_otg_hcd)) {
2541 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2542 pcgcctl.b.stoppclk = 1;
2543 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32,
2548 /** @todo - check how sw can wait for 1 sec to check asesvld??? */
2550 if (core_if->adp_enable) {
2551 gotgctl_data_t gotgctl = {.d32 = 0 };
2552 gpwrdn_data_t gpwrdn;
2554 while (gotgctl.b.asesvld == 1) {
2557 (&core_if->core_global_regs->gotgctl);
2561 /* Enable Power Down Logic */
2563 gpwrdn.b.pmuactv = 1;
2564 DWC_MODIFY_REG32(&core_if->
2565 core_global_regs->gpwrdn, 0,
2568 /* Unmask SRP detected interrupt from Power Down Logic */
2570 gpwrdn.b.srp_det_msk = 1;
2571 DWC_MODIFY_REG32(&core_if->
2572 core_global_regs->gpwrdn, 0,
2575 dwc_otg_adp_probe_start(core_if);
2579 case UHF_PORT_POWER:
2580 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2581 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2582 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2584 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
2586 case UHF_PORT_RESET:
2587 if ((core_if->power_down == 2)
2588 && (core_if->hibernation_suspend == 1)) {
2589 /* If we are going to exit from Hibernated
2590 * state via USB RESET.
2592 dwc_otg_host_hibernation_restore(core_if, 0, 1);
2594 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2596 DWC_DEBUGPL(DBG_HCD,
2597 "DWC OTG HCD HUB CONTROL - "
2598 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2600 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2601 pcgcctl.b.enbl_sleep_gating = 1;
2602 pcgcctl.b.stoppclk = 1;
2603 DWC_MODIFY_REG32(core_if->pcgcctl,
2605 DWC_WRITE_REG32(core_if->pcgcctl, 0);
2607 #ifdef CONFIG_USB_DWC_OTG_LPM
2609 glpmcfg_data_t lpmcfg;
2611 DWC_READ_REG32(&core_if->
2614 if (lpmcfg.b.prt_sleep_sts) {
2615 lpmcfg.b.en_utmi_sleep = 0;
2616 lpmcfg.b.hird_thres &=
2618 DWC_WRITE_REG32(&core_if->
2626 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2627 /* Clear suspend bit if resetting from suspended state. */
2628 hprt0.b.prtsusp = 0;
2629 /* When B-Host the Port reset bit is set in
2630 * the Start HCD Callback function, so that
2631 * the reset is started within 1ms of the HNP
2632 * success interrupt. */
2633 if (!dwc_otg_hcd_is_b_host(dwc_otg_hcd)) {
2637 ("Indeed it is in host mode hprt0 = %08x\n",
2639 DWC_WRITE_REG32(core_if->host_if->hprt0,
2642 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2645 DWC_WRITE_REG32(core_if->host_if->hprt0,
2647 core_if->lx_state = DWC_OTG_L0; /* Now back to the on state */
2650 #ifdef DWC_HS_ELECT_TST
2654 gintmsk_data_t gintmsk;
2656 t = (wIndex >> 8); /* MSB wIndex USB */
2657 DWC_DEBUGPL(DBG_HCD,
2658 "DWC OTG HCD HUB CONTROL - "
2659 "SetPortFeature - USB_PORT_FEAT_TEST %d\n",
2661 DWC_WARN("USB_PORT_FEAT_TEST %d\n", t);
2663 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2664 hprt0.b.prttstctl = t;
2665 DWC_WRITE_REG32(core_if->host_if->hprt0,
2668 /* Setup global vars with reg addresses (quick and
2669 * dirty hack, should be cleaned up)
2671 global_regs = core_if->core_global_regs;
2673 core_if->host_if->host_global_regs;
2675 (dwc_otg_hc_regs_t *) ((char *)
2679 (uint32_t *) ((char *)global_regs +
2682 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2683 /* Save current interrupt mask */
2686 (&global_regs->gintmsk);
2688 /* Disable all interrupts while we muck with
2689 * the hardware directly
2691 DWC_WRITE_REG32(&global_regs->
2694 /* 15 second delay per the test spec */
2697 /* Drive suspend on the root port */
2699 dwc_otg_read_hprt0(core_if);
2700 hprt0.b.prtsusp = 1;
2702 DWC_WRITE_REG32(core_if->
2706 /* 15 second delay per the test spec */
2709 /* Drive resume on the root port */
2711 dwc_otg_read_hprt0(core_if);
2712 hprt0.b.prtsusp = 0;
2714 DWC_WRITE_REG32(core_if->
2719 /* Clear the resume bit */
2721 DWC_WRITE_REG32(core_if->
2725 /* Restore interrupts */
2726 DWC_WRITE_REG32(&global_regs->
2729 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2730 /* Save current interrupt mask */
2733 (&global_regs->gintmsk);
2735 /* Disable all interrupts while we muck with
2736 * the hardware directly
2738 DWC_WRITE_REG32(&global_regs->
2741 /* 15 second delay per the test spec */
2744 /* Send the Setup packet */
2747 /* 15 second delay so nothing else happens for awhile */
2750 /* Restore interrupts */
2751 DWC_WRITE_REG32(&global_regs->
2754 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2755 /* Save current interrupt mask */
2758 (&global_regs->gintmsk);
2760 /* Disable all interrupts while we muck with
2761 * the hardware directly
2763 DWC_WRITE_REG32(&global_regs->
2766 /* Send the Setup packet */
2769 /* 15 second delay so nothing else happens for awhile */
2772 /* Send the In and Ack packets */
2775 /* 15 second delay so nothing else happens for awhile */
2778 /* Restore interrupts */
2779 DWC_WRITE_REG32(&global_regs->
2786 #endif /* DWC_HS_ELECT_TST */
2788 case UHF_PORT_INDICATOR:
2789 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2790 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2794 retval = -DWC_E_INVALID;
2795 DWC_ERROR("DWC OTG HCD - "
2796 "SetPortFeature request %xh "
2797 "unknown or unsupported\n", wValue);
2801 #ifdef CONFIG_USB_DWC_OTG_LPM
2802 case UCR_SET_AND_TEST_PORT_FEATURE:
2803 if (wValue != UHF_PORT_L1) {
2807 int portnum, hird, devaddr, remwake;
2808 glpmcfg_data_t lpmcfg;
2809 uint32_t time_usecs;
2810 gintsts_data_t gintsts;
2811 gintmsk_data_t gintmsk;
2813 if (!dwc_otg_get_param_lpm_enable(core_if)) {
2816 if (wValue != UHF_PORT_L1 || wLength != 1) {
2819 /* Check if the port currently is in SLEEP state */
2821 DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
2822 if (lpmcfg.b.prt_sleep_sts) {
2823 DWC_INFO("Port is already in sleep mode\n");
2824 buf[0] = 0; /* Return success */
2828 portnum = wIndex & 0xf;
2829 hird = (wIndex >> 4) & 0xf;
2830 devaddr = (wIndex >> 8) & 0x7f;
2831 remwake = (wIndex >> 15);
2834 retval = -DWC_E_INVALID;
2836 ("Wrong port number(%d) in SetandTestPortFeature request\n",
2842 ("SetandTestPortFeature request: portnum = %d, hird = %d, devaddr = %d, rewake = %d\n",
2843 portnum, hird, devaddr, remwake);
2844 /* Disable LPM interrupt */
2846 gintmsk.b.lpmtranrcvd = 1;
2847 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk,
2850 if (dwc_otg_hcd_send_lpm
2851 (dwc_otg_hcd, devaddr, hird, remwake)) {
2852 retval = -DWC_E_INVALID;
2856 time_usecs = 10 * (lpmcfg.b.retry_count + 1);
2857 /* We will consider timeout if time_usecs microseconds pass,
2858 * and we don't receive LPM transaction status.
2859 * After receiving non-error responce(ACK/NYET/STALL) from device,
2860 * core will set lpmtranrcvd bit.
2864 DWC_READ_REG32(&core_if->core_global_regs->
2866 if (gintsts.b.lpmtranrcvd) {
2870 } while (--time_usecs);
2871 /* lpm_int bit will be cleared in LPM interrupt handler */
2878 if (!gintsts.b.lpmtranrcvd) {
2879 buf[0] = 0x3; /* Completion code is Timeout */
2880 dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd);
2883 DWC_READ_REG32(&core_if->core_global_regs->
2885 if (lpmcfg.b.lpm_resp == 0x3) {
2886 /* ACK responce from the device */
2887 buf[0] = 0x00; /* Success */
2888 } else if (lpmcfg.b.lpm_resp == 0x2) {
2889 /* NYET responce from the device */
2892 /* Otherwise responce with Timeout */
2896 DWC_PRINTF("Device responce to LPM trans is %x\n",
2898 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0,
2903 #endif /* CONFIG_USB_DWC_OTG_LPM */
2906 retval = -DWC_E_INVALID;
2907 DWC_WARN("DWC OTG HCD - "
2908 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2909 typeReq, wIndex, wValue);
2916 #ifdef CONFIG_USB_DWC_OTG_LPM
2917 /** Returns index of host channel to perform LPM transaction. */
2918 int dwc_otg_hcd_get_hc_for_lpm_tran(dwc_otg_hcd_t *hcd, uint8_t devaddr)
2920 dwc_otg_core_if_t *core_if = hcd->core_if;
2922 hcchar_data_t hcchar;
2923 gintmsk_data_t gintmsk = {.d32 = 0 };
2925 if (DWC_CIRCLEQ_EMPTY(&hcd->free_hc_list)) {
2926 DWC_PRINTF("No free channel to select for LPM transaction\n");
2930 hc = DWC_CIRCLEQ_FIRST(&hcd->free_hc_list);
2932 /* Mask host channel interrupts. */
2933 gintmsk.b.hcintr = 1;
2934 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
2936 /* Fill fields that core needs for LPM transaction */
2937 hcchar.b.devaddr = devaddr;
2939 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2941 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2942 hcchar.b.epdir = 0; /* OUT */
2943 DWC_WRITE_REG32(&core_if->host_if->hc_regs[hc->hc_num]->hcchar,
2946 /* Remove the host channel from the free list. */
2947 DWC_CIRCLEQ_REMOVE_INIT(&hcd->free_hc_list, hc, hc_list_entry);
2949 DWC_PRINTF("hcnum = %d devaddr = %d\n", hc->hc_num, devaddr);
2954 /** Release hc after performing LPM transaction */
2955 void dwc_otg_hcd_free_hc_from_lpm(dwc_otg_hcd_t *hcd)
2958 glpmcfg_data_t lpmcfg;
2961 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2962 hc_num = lpmcfg.b.lpm_chan_index;
2964 hc = hcd->hc_ptr_array[hc_num];
2966 DWC_PRINTF("Freeing channel %d after LPM\n", hc_num);
2967 /* Return host channel to free list */
2968 DWC_CIRCLEQ_INSERT_TAIL(&hcd->free_hc_list, hc, hc_list_entry);
2971 int dwc_otg_hcd_send_lpm(dwc_otg_hcd_t *hcd, uint8_t devaddr, uint8_t hird,
2972 uint8_t bRemoteWake)
2974 glpmcfg_data_t lpmcfg;
2975 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2978 channel = dwc_otg_hcd_get_hc_for_lpm_tran(hcd, devaddr);
2983 pcgcctl.b.enbl_sleep_gating = 1;
2984 DWC_MODIFY_REG32(hcd->core_if->pcgcctl, 0, pcgcctl.d32);
2986 /* Read LPM config register */
2987 lpmcfg.d32 = DWC_READ_REG32(&hcd->core_if->core_global_regs->glpmcfg);
2989 /* Program LPM transaction fields */
2990 lpmcfg.b.rem_wkup_en = bRemoteWake;
2991 lpmcfg.b.hird = hird;
2993 if (dwc_otg_get_param_besl_enable(hcd->core_if)) {
2994 lpmcfg.b.hird_thres = 0x16;
2995 lpmcfg.b.en_besl = 1;
2997 lpmcfg.b.hird_thres = 0x1c;
3000 lpmcfg.b.lpm_chan_index = channel;
3001 lpmcfg.b.en_utmi_sleep = 1;
3002 /* Program LPM config register */
3003 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3005 /* Send LPM transaction */
3006 lpmcfg.b.send_lpm = 1;
3007 DWC_WRITE_REG32(&hcd->core_if->core_global_regs->glpmcfg, lpmcfg.d32);
3012 #endif /* CONFIG_USB_DWC_OTG_LPM */
3014 int dwc_otg_hcd_is_status_changed(dwc_otg_hcd_t *hcd, int port)
3019 return -DWC_E_INVALID;
3022 retval = (hcd->flags.b.port_connect_status_change ||
3023 hcd->flags.b.port_reset_change ||
3024 hcd->flags.b.port_enable_change ||
3025 hcd->flags.b.port_suspend_change ||
3026 hcd->flags.b.port_over_current_change);
3029 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
3030 " Root port status changed\n");
3031 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
3032 hcd->flags.b.port_connect_status_change);
3033 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
3034 hcd->flags.b.port_reset_change);
3035 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
3036 hcd->flags.b.port_enable_change);
3037 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
3038 hcd->flags.b.port_suspend_change);
3039 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
3040 hcd->flags.b.port_over_current_change);
3046 int dwc_otg_hcd_get_frame_number(dwc_otg_hcd_t *dwc_otg_hcd)
3050 DWC_READ_REG32(&dwc_otg_hcd->core_if->host_if->
3051 host_global_regs->hfnum);
3054 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n",
3057 return hfnum.b.frnum;
3060 int dwc_otg_hcd_start(dwc_otg_hcd_t *hcd,
3061 struct dwc_otg_hcd_function_ops *fops)
3066 if (!dwc_otg_is_device_mode(hcd->core_if) &&
3067 (!hcd->core_if->adp_enable || hcd->core_if->adp.adp_started)) {
3068 dwc_otg_hcd_reinit(hcd);
3070 retval = -DWC_E_NO_DEVICE;
3076 void *dwc_otg_hcd_get_priv_data(dwc_otg_hcd_t *hcd)
3081 void dwc_otg_hcd_set_priv_data(dwc_otg_hcd_t *hcd, void *priv_data)
3083 hcd->priv = priv_data;
3086 uint32_t dwc_otg_hcd_otg_port(dwc_otg_hcd_t *hcd)
3088 return hcd->otg_port;
3091 uint32_t dwc_otg_hcd_is_b_host(dwc_otg_hcd_t *hcd)
3094 if (hcd->core_if->op_state == B_HOST) {
3103 dwc_otg_hcd_urb_t *dwc_otg_hcd_urb_alloc(dwc_otg_hcd_t *hcd,
3104 int iso_desc_count, int atomic_alloc)
3106 dwc_otg_hcd_urb_t *dwc_otg_urb;
3110 sizeof(*dwc_otg_urb) +
3111 iso_desc_count * sizeof(struct dwc_otg_hcd_iso_packet_desc);
3113 dwc_otg_urb = DWC_ALLOC_ATOMIC(size);
3115 dwc_otg_urb = DWC_ALLOC(size);
3117 dwc_otg_urb->packet_count = iso_desc_count;
3122 void dwc_otg_hcd_urb_set_pipeinfo(dwc_otg_hcd_urb_t *dwc_otg_urb,
3123 uint8_t dev_addr, uint8_t ep_num,
3124 uint8_t ep_type, uint8_t ep_dir, uint16_t mps)
3126 dwc_otg_hcd_fill_pipe(&dwc_otg_urb->pipe_info, dev_addr, ep_num,
3127 ep_type, ep_dir, mps);
3130 ("addr = %d, ep_num = %d, ep_dir = 0x%x, ep_type = 0x%x, mps = %d\n",
3131 dev_addr, ep_num, ep_dir, ep_type, mps);
3135 void dwc_otg_hcd_urb_set_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3136 void *urb_handle, void *buf, dwc_dma_t dma,
3137 uint32_t buflen, void *setup_packet,
3138 dwc_dma_t setup_dma, uint32_t flags,
3141 dwc_otg_urb->priv = urb_handle;
3142 dwc_otg_urb->buf = buf;
3143 dwc_otg_urb->dma = dma;
3144 dwc_otg_urb->length = buflen;
3145 dwc_otg_urb->setup_packet = setup_packet;
3146 dwc_otg_urb->setup_dma = setup_dma;
3147 dwc_otg_urb->flags = flags;
3148 dwc_otg_urb->interval = interval;
3149 dwc_otg_urb->status = -DWC_E_IN_PROGRESS;
3152 uint32_t dwc_otg_hcd_urb_get_status(dwc_otg_hcd_urb_t *dwc_otg_urb)
3154 return dwc_otg_urb->status;
3157 uint32_t dwc_otg_hcd_urb_get_actual_length(dwc_otg_hcd_urb_t *dwc_otg_urb)
3159 return dwc_otg_urb->actual_length;
3162 uint32_t dwc_otg_hcd_urb_get_error_count(dwc_otg_hcd_urb_t *dwc_otg_urb)
3164 return dwc_otg_urb->error_count;
3167 void dwc_otg_hcd_urb_set_iso_desc_params(dwc_otg_hcd_urb_t *dwc_otg_urb,
3168 int desc_num, uint32_t offset,
3171 dwc_otg_urb->iso_descs[desc_num].offset = offset;
3172 dwc_otg_urb->iso_descs[desc_num].length = length;
3175 uint32_t dwc_otg_hcd_urb_get_iso_desc_status(dwc_otg_hcd_urb_t *dwc_otg_urb,
3178 return dwc_otg_urb->iso_descs[desc_num].status;
3181 uint32_t dwc_otg_hcd_urb_get_iso_desc_actual_length(dwc_otg_hcd_urb_t *
3182 dwc_otg_urb, int desc_num)
3184 return dwc_otg_urb->iso_descs[desc_num].actual_length;
3187 int dwc_otg_hcd_is_bandwidth_allocated(dwc_otg_hcd_t *hcd, void *ep_handle)
3190 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3193 if (!DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3200 int dwc_otg_hcd_is_bandwidth_freed(dwc_otg_hcd_t *hcd, void *ep_handle)
3202 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3204 DWC_ASSERT(qh, "qh is not allocated\n");
3206 if (DWC_LIST_EMPTY(&qh->qh_list_entry)) {
3213 uint8_t dwc_otg_hcd_get_ep_bandwidth(dwc_otg_hcd_t *hcd, void *ep_handle)
3215 dwc_otg_qh_t *qh = (dwc_otg_qh_t *) ep_handle;
3216 DWC_ASSERT(qh, "qh is not allocated\n");
3220 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *hcd)
3225 gnptxsts_data_t np_tx_status;
3226 hptxsts_data_t p_tx_status;
3228 num_channels = hcd->core_if->core_params->host_channels;
3231 ("************************************************************\n");
3232 DWC_PRINTF("HCD State:\n");
3233 DWC_PRINTF(" Num channels: %d\n", num_channels);
3234 for (i = 0; i < num_channels; i++) {
3235 dwc_hc_t *hc = hcd->hc_ptr_array[i];
3236 DWC_PRINTF(" Channel %d:\n", i);
3237 DWC_PRINTF(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3238 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3239 DWC_PRINTF(" speed: %d\n", hc->speed);
3240 DWC_PRINTF(" ep_type: %d\n", hc->ep_type);
3241 DWC_PRINTF(" max_packet: %d\n", hc->max_packet);
3242 DWC_PRINTF(" data_pid_start: %d\n", hc->data_pid_start);
3243 DWC_PRINTF(" multi_count: %d\n", hc->multi_count);
3244 DWC_PRINTF(" xfer_started: %d\n", hc->xfer_started);
3245 DWC_PRINTF(" xfer_buff: %p\n", hc->xfer_buff);
3246 DWC_PRINTF(" xfer_len: %d\n", hc->xfer_len);
3247 DWC_PRINTF(" xfer_count: %d\n", hc->xfer_count);
3248 DWC_PRINTF(" halt_on_queue: %d\n", hc->halt_on_queue);
3249 DWC_PRINTF(" halt_pending: %d\n", hc->halt_pending);
3250 DWC_PRINTF(" halt_status: %d\n", hc->halt_status);
3251 DWC_PRINTF(" do_split: %d\n", hc->do_split);
3252 DWC_PRINTF(" complete_split: %d\n", hc->complete_split);
3253 DWC_PRINTF(" hub_addr: %d\n", hc->hub_addr);
3254 DWC_PRINTF(" port_addr: %d\n", hc->port_addr);
3255 DWC_PRINTF(" xact_pos: %d\n", hc->xact_pos);
3256 DWC_PRINTF(" requests: %d\n", hc->requests);
3257 DWC_PRINTF(" qh: %p\n", hc->qh);
3258 if (hc->xfer_started) {
3260 hcchar_data_t hcchar;
3261 hctsiz_data_t hctsiz;
3263 hcintmsk_data_t hcintmsk;
3265 DWC_READ_REG32(&hcd->core_if->host_if->
3266 host_global_regs->hfnum);
3268 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3271 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3274 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3277 DWC_READ_REG32(&hcd->core_if->host_if->hc_regs[i]->
3279 DWC_PRINTF(" hfnum: 0x%08x\n", hfnum.d32);
3280 DWC_PRINTF(" hcchar: 0x%08x\n", hcchar.d32);
3281 DWC_PRINTF(" hctsiz: 0x%08x\n", hctsiz.d32);
3282 DWC_PRINTF(" hcint: 0x%08x\n", hcint.d32);
3283 DWC_PRINTF(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3285 if (hc->xfer_started && hc->qh) {
3287 dwc_otg_hcd_urb_t *urb;
3289 DWC_CIRCLEQ_FOREACH(qtd, &hc->qh->qtd_list,
3291 if (!qtd->in_process)
3295 DWC_PRINTF(" URB Info:\n");
3296 DWC_PRINTF(" qtd: %p, urb: %p\n", qtd,
3299 DWC_PRINTF(" Dev: %d, EP: %d %s\n",
3300 dwc_otg_hcd_get_dev_addr
3302 dwc_otg_hcd_get_ep_num
3304 dwc_otg_hcd_is_pipe_in
3305 (&urb->pipe_info) ? "IN" :
3308 (" Max packet size: %d\n",
3312 (" transfer_buffer: %p\n",
3314 DWC_PRINTF(" transfer_dma: %p\n",
3317 (" transfer_buffer_length: %d\n",
3319 DWC_PRINTF(" actual_length: %d\n",
3320 urb->actual_length);
3325 DWC_PRINTF(" non_periodic_channels: %d\n", hcd->non_periodic_channels);
3326 DWC_PRINTF(" periodic_channels: %d\n", hcd->periodic_channels);
3327 DWC_PRINTF(" periodic_usecs: %d\n", hcd->periodic_usecs);
3329 DWC_READ_REG32(&hcd->core_if->core_global_regs->gnptxsts);
3330 DWC_PRINTF(" NP Tx Req Queue Space Avail: %d\n",
3331 np_tx_status.b.nptxqspcavail);
3332 DWC_PRINTF(" NP Tx FIFO Space Avail: %d\n",
3333 np_tx_status.b.nptxfspcavail);
3335 DWC_READ_REG32(&hcd->core_if->host_if->host_global_regs->hptxsts);
3336 DWC_PRINTF(" P Tx Req Queue Space Avail: %d\n",
3337 p_tx_status.b.ptxqspcavail);
3338 DWC_PRINTF(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3339 dwc_otg_hcd_dump_frrem(hcd);
3340 dwc_otg_dump_global_registers(hcd->core_if);
3341 dwc_otg_dump_host_registers(hcd->core_if);
3343 ("************************************************************\n");
3349 void dwc_print_setup_data(uint8_t *setup)
3352 if (CHK_DEBUG_LEVEL(DBG_HCD)) {
3353 DWC_PRINTF("Setup Data = MSB ");
3354 for (i = 7; i >= 0; i--)
3355 DWC_PRINTF("%02x ", setup[i]);
3357 DWC_PRINTF(" bmRequestType Tranfer = %s\n",
3358 (setup[0] & 0x80) ? "Device-to-Host" :
3360 DWC_PRINTF(" bmRequestType Type = ");
3361 switch ((setup[0] & 0x60) >> 5) {
3363 DWC_PRINTF("Standard\n");
3366 DWC_PRINTF("Class\n");
3369 DWC_PRINTF("Vendor\n");
3372 DWC_PRINTF("Reserved\n");
3375 DWC_PRINTF(" bmRequestType Recipient = ");
3376 switch (setup[0] & 0x1f) {
3378 DWC_PRINTF("Device\n");
3381 DWC_PRINTF("Interface\n");
3384 DWC_PRINTF("Endpoint\n");
3387 DWC_PRINTF("Other\n");
3390 DWC_PRINTF("Reserved\n");
3393 DWC_PRINTF(" bRequest = 0x%0x\n", setup[1]);
3394 DWC_PRINTF(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3395 DWC_PRINTF(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3396 DWC_PRINTF(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3401 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *hcd)
3404 DWC_PRINTF("Frame remaining at SOF:\n");
3405 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3406 hcd->frrem_samples, hcd->frrem_accum,
3407 (hcd->frrem_samples > 0) ?
3408 hcd->frrem_accum / hcd->frrem_samples : 0);
3411 DWC_PRINTF("Frame remaining at start_transfer (uframe 7):\n");
3412 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3413 hcd->core_if->hfnum_7_samples,
3414 hcd->core_if->hfnum_7_frrem_accum,
3415 (hcd->core_if->hfnum_7_samples >
3416 0) ? hcd->core_if->hfnum_7_frrem_accum /
3417 hcd->core_if->hfnum_7_samples : 0);
3418 DWC_PRINTF("Frame remaining at start_transfer (uframe 0):\n");
3419 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3420 hcd->core_if->hfnum_0_samples,
3421 hcd->core_if->hfnum_0_frrem_accum,
3422 (hcd->core_if->hfnum_0_samples >
3423 0) ? hcd->core_if->hfnum_0_frrem_accum /
3424 hcd->core_if->hfnum_0_samples : 0);
3425 DWC_PRINTF("Frame remaining at start_transfer (uframe 1-6):\n");
3426 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3427 hcd->core_if->hfnum_other_samples,
3428 hcd->core_if->hfnum_other_frrem_accum,
3429 (hcd->core_if->hfnum_other_samples >
3430 0) ? hcd->core_if->hfnum_other_frrem_accum /
3431 hcd->core_if->hfnum_other_samples : 0);
3434 DWC_PRINTF("Frame remaining at sample point A (uframe 7):\n");
3435 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3436 hcd->hfnum_7_samples_a, hcd->hfnum_7_frrem_accum_a,
3437 (hcd->hfnum_7_samples_a > 0) ?
3438 hcd->hfnum_7_frrem_accum_a / hcd->hfnum_7_samples_a : 0);
3439 DWC_PRINTF("Frame remaining at sample point A (uframe 0):\n");
3440 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3441 hcd->hfnum_0_samples_a, hcd->hfnum_0_frrem_accum_a,
3442 (hcd->hfnum_0_samples_a > 0) ?
3443 hcd->hfnum_0_frrem_accum_a / hcd->hfnum_0_samples_a : 0);
3444 DWC_PRINTF("Frame remaining at sample point A (uframe 1-6):\n");
3445 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3446 hcd->hfnum_other_samples_a, hcd->hfnum_other_frrem_accum_a,
3447 (hcd->hfnum_other_samples_a > 0) ?
3448 hcd->hfnum_other_frrem_accum_a /
3449 hcd->hfnum_other_samples_a : 0);
3452 DWC_PRINTF("Frame remaining at sample point B (uframe 7):\n");
3453 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3454 hcd->hfnum_7_samples_b, hcd->hfnum_7_frrem_accum_b,
3455 (hcd->hfnum_7_samples_b > 0) ?
3456 hcd->hfnum_7_frrem_accum_b / hcd->hfnum_7_samples_b : 0);
3457 DWC_PRINTF("Frame remaining at sample point B (uframe 0):\n");
3458 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3459 hcd->hfnum_0_samples_b, hcd->hfnum_0_frrem_accum_b,
3460 (hcd->hfnum_0_samples_b > 0) ?
3461 hcd->hfnum_0_frrem_accum_b / hcd->hfnum_0_samples_b : 0);
3462 DWC_PRINTF("Frame remaining at sample point B (uframe 1-6):\n");
3463 DWC_PRINTF(" samples %u, accum %llu, avg %llu\n",
3464 hcd->hfnum_other_samples_b, hcd->hfnum_other_frrem_accum_b,
3465 (hcd->hfnum_other_samples_b > 0) ?
3466 hcd->hfnum_other_frrem_accum_b /
3467 hcd->hfnum_other_samples_b : 0);
3471 #endif /* DWC_DEVICE_ONLY */