1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t *g_otgdev;
72 extern int pcd_init(struct platform_device *_dev);
73 extern int otg20_hcd_init(struct platform_device *_dev);
74 extern int host20_hcd_init(struct platform_device *_dev);
75 extern int pcd_remove(struct platform_device *_dev);
76 extern void hcd_remove(struct platform_device *_dev);
77 extern void dwc_otg_adp_start(dwc_otg_core_if_t *core_if, uint8_t is_host);
80 #ifdef CONFIG_RK_USB_UART
81 static u32 usb_to_uart_status;
83 /*-------------------------------------------------------------------------*/
84 /* Encapsulate the module parameter settings */
86 struct dwc_otg_driver_module_params {
90 int32_t dma_desc_enable;
91 int32_t dma_burst_size;
93 int32_t host_support_fs_ls_low_power;
94 int32_t host_ls_low_power_phy_clk;
95 int32_t enable_dynamic_fifo;
96 int32_t data_fifo_size;
97 int32_t dev_rx_fifo_size;
98 int32_t dev_nperio_tx_fifo_size;
99 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
100 int32_t host_rx_fifo_size;
101 int32_t host_nperio_tx_fifo_size;
102 int32_t host_perio_tx_fifo_size;
103 int32_t max_transfer_size;
104 int32_t max_packet_count;
105 int32_t host_channels;
106 int32_t dev_endpoints;
108 int32_t phy_utmi_width;
109 int32_t phy_ulpi_ddr;
110 int32_t phy_ulpi_ext_vbus;
114 int32_t en_multiple_tx_fifo;
115 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
117 uint32_t tx_thr_length;
118 uint32_t rx_thr_length;
123 int32_t baseline_besl;
126 int32_t ahb_thr_ratio;
136 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
138 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
140 .dma_desc_enable = 0,
141 .dma_burst_size = -1,
143 .host_support_fs_ls_low_power = -1,
144 .host_ls_low_power_phy_clk = -1,
145 .enable_dynamic_fifo = 1,
146 .data_fifo_size = -1,
147 .dev_rx_fifo_size = 0x120,
148 .dev_nperio_tx_fifo_size = 0x10,
149 .dev_perio_tx_fifo_size = {
150 /* dev_perio_tx_fifo_size_1 */
168 .host_rx_fifo_size = -1,
169 .host_nperio_tx_fifo_size = -1,
170 .host_perio_tx_fifo_size = -1,
171 .max_transfer_size = -1,
172 .max_packet_count = -1,
176 .phy_utmi_width = -1,
178 .phy_ulpi_ext_vbus = -1,
182 .en_multiple_tx_fifo = -1,
183 .dev_tx_fifo_size = {
184 /* dev_tx_fifo_size */
222 #ifdef CONFIG_USB20_HOST
223 static struct dwc_otg_driver_module_params dwc_host_module_params = {
225 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
227 .dma_desc_enable = 0,
228 .dma_burst_size = -1,
230 .host_support_fs_ls_low_power = -1,
231 .host_ls_low_power_phy_clk = -1,
232 .enable_dynamic_fifo = -1,
233 .data_fifo_size = -1,
234 .dev_rx_fifo_size = -1,
235 .dev_nperio_tx_fifo_size = -1,
236 .dev_perio_tx_fifo_size = {
237 /* dev_perio_tx_fifo_size_1 */
255 .host_rx_fifo_size = -1,
256 .host_nperio_tx_fifo_size = -1,
257 .host_perio_tx_fifo_size = -1,
258 .max_transfer_size = -1,
259 .max_packet_count = -1,
263 .phy_utmi_width = -1,
265 .phy_ulpi_ext_vbus = -1,
269 .en_multiple_tx_fifo = -1,
270 .dev_tx_fifo_size = {
271 /* dev_tx_fifo_size */
311 * This function shows the Driver Version.
313 static ssize_t version_show(struct device_driver *dev, char *buf)
315 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
319 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
322 * Global Debug Level Mask.
324 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
327 * This function shows the driver Debug Level.
329 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
331 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
335 * This function stores the driver Debug Level.
337 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
340 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
344 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
347 extern void hcd_start(dwc_otg_core_if_t *core_if);
348 extern struct usb_hub *g_dwc_otg_root_hub20;
349 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
351 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
353 dwc_otg_device_t *otg_dev = core_if->otg_dev;
354 dctl_data_t dctl = {.d32 = 0 };
357 if (core_if->op_state == A_HOST) {
358 printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
361 core_if->op_state = A_HOST;
363 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
364 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
365 dctl.b.sftdiscon = 1;
366 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
368 local_irq_save(flags);
369 cil_pcd_stop(core_if);
371 * Initialize the Core for Host mode.
374 dwc_otg_core_init(core_if);
375 dwc_otg_enable_global_interrupts(core_if);
376 cil_hcd_start(core_if);
377 local_irq_restore(flags);
380 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
382 dwc_otg_device_t *otg_dev = core_if->otg_dev;
385 local_irq_save(flags);
387 if (core_if->op_state == B_PERIPHERAL) {
389 ("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
392 core_if->op_state = B_PERIPHERAL;
393 cil_hcd_stop(core_if);
394 /* dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20); */
395 otg_dev->pcd->phy_suspend = 1;
396 otg_dev->pcd->vbus_status = 0;
397 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
399 /* Reset the Controller */
400 dwc_otg_core_reset(core_if);
402 dwc_otg_core_init(core_if);
403 dwc_otg_disable_global_interrupts(core_if);
404 cil_pcd_start(core_if);
406 local_irq_restore(flags);
409 static ssize_t force_usb_mode_show(struct device_driver *drv, char *buf)
411 dwc_otg_device_t *otg_dev = g_otgdev;
412 dwc_otg_core_if_t *core_if = otg_dev->core_if;
414 return sprintf(buf, "%d\n", core_if->usb_mode);
417 static ssize_t force_usb_mode_store(struct device_driver *drv, const char *buf,
420 int new_mode = simple_strtoul(buf, NULL, 16);
421 dwc_otg_device_t *otg_dev = g_otgdev;
422 dwc_otg_core_if_t *core_if;
423 struct dwc_otg_platform_data *pldata;
428 core_if = otg_dev->core_if;
429 pldata = otg_dev->pldata;
431 DWC_PRINTF("%s %d->%d\n", __func__, core_if->usb_mode, new_mode);
433 if (core_if->usb_mode == new_mode) {
437 if (pldata->phy_status == USB_PHY_SUSPEND) {
438 pldata->clock_enable(pldata, 1);
439 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
443 case USB_MODE_FORCE_HOST:
444 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
446 core_if->usb_mode = new_mode;
447 dwc_otg_force_host(core_if);
448 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
449 core_if->usb_mode = new_mode;
450 if (dwc_otg_is_host_mode(core_if))
451 dwc_otg_set_force_mode(core_if, new_mode);
453 dwc_otg_force_host(core_if);
457 case USB_MODE_FORCE_DEVICE:
458 if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
459 core_if->usb_mode = new_mode;
460 dwc_otg_force_device(core_if);
461 } else if (USB_MODE_NORMAL == core_if->usb_mode) {
462 core_if->usb_mode = new_mode;
463 if (dwc_otg_is_device_mode(core_if))
464 dwc_otg_set_force_mode(core_if, new_mode);
466 dwc_otg_force_device(core_if);
470 case USB_MODE_NORMAL:
471 if (USB_MODE_FORCE_DEVICE == core_if->usb_mode) {
472 core_if->usb_mode = new_mode;
473 cancel_delayed_work(&otg_dev->pcd->check_vbus_work);
474 dwc_otg_set_force_mode(core_if, new_mode);
476 if (dwc_otg_is_host_mode(core_if)) {
477 dwc_otg_force_host(core_if);
479 dwc_otg_pcd_start_check_vbus_work(otg_dev->pcd);
481 } else if (USB_MODE_FORCE_HOST == core_if->usb_mode) {
482 core_if->usb_mode = new_mode;
483 dwc_otg_set_force_mode(core_if, new_mode);
485 if (dwc_otg_is_device_mode(core_if)) {
486 dwc_otg_force_device(core_if);
497 static DRIVER_ATTR(force_usb_mode, S_IRUGO | S_IWUSR, force_usb_mode_show,
498 force_usb_mode_store);
500 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
503 dwc_otg_device_t *otg_dev = g_otgdev;
504 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
505 return sprintf(_buf, "%d\n", _pcd->conn_en);
509 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv,
510 const char *_buf, size_t _count)
512 int enable = simple_strtoul(_buf, NULL, 10);
513 dwc_otg_device_t *otg_dev = g_otgdev;
514 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
515 DWC_PRINTF("%s %d->%d\n", __func__, _pcd->conn_en, enable);
517 _pcd->conn_en = enable;
521 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO | S_IWUSR, dwc_otg_conn_en_show,
522 dwc_otg_conn_en_store);
524 /* used for product vbus power control, SDK not need.
525 * If dwc_otg is host mode, enable vbus power.
526 * If dwc_otg is device mode, disable vbus power.
527 * return 1 - host mode, 0 - device mode.
529 int dwc_otg_usb_state(void)
531 dwc_otg_device_t *otg_dev = g_otgdev;
534 /* op_state is A_HOST */
535 if (1 == otg_dev->core_if->op_state)
537 /* op_state is B_PERIPHERAL */
538 else if (4 == otg_dev->core_if->op_state)
543 DWC_WARN("g_otgdev is NULL, maybe otg probe is failed!\n");
547 EXPORT_SYMBOL(dwc_otg_usb_state);
549 static ssize_t dwc_otg_op_state_show(struct device_driver *_drv, char *_buf)
551 dwc_otg_device_t *otg_dev = g_otgdev;
554 return sprintf(_buf, "%d\n", otg_dev->core_if->op_state);
556 return sprintf(_buf, "%d\n", 0);
559 static DRIVER_ATTR(op_state, S_IRUGO, dwc_otg_op_state_show, NULL);
561 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
563 dwc_otg_device_t *otg_dev = g_otgdev;
564 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
565 return sprintf(_buf, "%d\n", _pcd->vbus_status);
568 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
571 * This function is called during module intialization
572 * to pass module parameters to the DWC_OTG CORE.
574 static int set_parameters(dwc_otg_core_if_t *core_if,
575 struct dwc_otg_driver_module_params module_params)
580 if (module_params.otg_cap != -1) {
582 dwc_otg_set_param_otg_cap(core_if, module_params.otg_cap);
584 if (module_params.dma_enable != -1) {
586 dwc_otg_set_param_dma_enable(core_if,
587 module_params.dma_enable);
589 if (module_params.dma_desc_enable != -1) {
591 dwc_otg_set_param_dma_desc_enable(core_if,
592 module_params.dma_desc_enable);
594 if (module_params.opt != -1) {
595 retval += dwc_otg_set_param_opt(core_if, module_params.opt);
597 if (module_params.dma_burst_size != -1) {
599 dwc_otg_set_param_dma_burst_size(core_if,
600 module_params.dma_burst_size);
602 if (module_params.host_support_fs_ls_low_power != -1) {
604 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
605 module_params.host_support_fs_ls_low_power);
607 if (module_params.enable_dynamic_fifo != -1) {
609 dwc_otg_set_param_enable_dynamic_fifo(core_if,
610 module_params.enable_dynamic_fifo);
612 if (module_params.data_fifo_size != -1) {
614 dwc_otg_set_param_data_fifo_size(core_if,
615 module_params.data_fifo_size);
617 if (module_params.dev_rx_fifo_size != -1) {
619 dwc_otg_set_param_dev_rx_fifo_size(core_if,
620 module_params.dev_rx_fifo_size);
622 if (module_params.dev_nperio_tx_fifo_size != -1) {
624 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
625 module_params.dev_nperio_tx_fifo_size);
627 if (module_params.host_rx_fifo_size != -1) {
629 dwc_otg_set_param_host_rx_fifo_size(core_if,
633 if (module_params.host_nperio_tx_fifo_size != -1) {
635 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
636 module_params.host_nperio_tx_fifo_size);
638 if (module_params.host_perio_tx_fifo_size != -1) {
640 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
641 module_params.host_perio_tx_fifo_size);
643 if (module_params.max_transfer_size != -1) {
645 dwc_otg_set_param_max_transfer_size(core_if,
646 module_params.max_transfer_size);
648 if (module_params.max_packet_count != -1) {
650 dwc_otg_set_param_max_packet_count(core_if,
651 module_params.max_packet_count);
653 if (module_params.host_channels != -1) {
655 dwc_otg_set_param_host_channels(core_if,
656 module_params.host_channels);
658 if (module_params.dev_endpoints != -1) {
660 dwc_otg_set_param_dev_endpoints(core_if,
661 module_params.dev_endpoints);
663 if (module_params.phy_type != -1) {
665 dwc_otg_set_param_phy_type(core_if, module_params.phy_type);
667 if (module_params.speed != -1) {
668 retval += dwc_otg_set_param_speed(core_if, module_params.speed);
670 if (module_params.host_ls_low_power_phy_clk != -1) {
672 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
673 module_params.host_ls_low_power_phy_clk);
675 if (module_params.phy_ulpi_ddr != -1) {
677 dwc_otg_set_param_phy_ulpi_ddr(core_if,
678 module_params.phy_ulpi_ddr);
680 if (module_params.phy_ulpi_ext_vbus != -1) {
682 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
683 module_params.phy_ulpi_ext_vbus);
685 if (module_params.phy_utmi_width != -1) {
687 dwc_otg_set_param_phy_utmi_width(core_if,
688 module_params.phy_utmi_width);
690 if (module_params.ulpi_fs_ls != -1) {
692 dwc_otg_set_param_ulpi_fs_ls(core_if,
693 module_params.ulpi_fs_ls);
695 if (module_params.ts_dline != -1) {
697 dwc_otg_set_param_ts_dline(core_if, module_params.ts_dline);
699 if (module_params.i2c_enable != -1) {
701 dwc_otg_set_param_i2c_enable(core_if,
702 module_params.i2c_enable);
704 if (module_params.en_multiple_tx_fifo != -1) {
706 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
707 module_params.en_multiple_tx_fifo);
709 for (i = 0; i < 15; i++) {
710 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
712 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
713 module_params.dev_perio_tx_fifo_size
718 for (i = 0; i < 15; i++) {
719 if (module_params.dev_tx_fifo_size[i] != -1) {
720 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
721 module_params.dev_tx_fifo_size
725 if (module_params.thr_ctl != -1) {
727 dwc_otg_set_param_thr_ctl(core_if, module_params.thr_ctl);
729 if (module_params.mpi_enable != -1) {
731 dwc_otg_set_param_mpi_enable(core_if,
732 module_params.mpi_enable);
734 if (module_params.pti_enable != -1) {
736 dwc_otg_set_param_pti_enable(core_if,
737 module_params.pti_enable);
739 if (module_params.lpm_enable != -1) {
741 dwc_otg_set_param_lpm_enable(core_if,
742 module_params.lpm_enable);
744 if (module_params.besl_enable != -1) {
746 dwc_otg_set_param_besl_enable(core_if,
747 module_params.besl_enable);
749 if (module_params.baseline_besl != -1) {
751 dwc_otg_set_param_baseline_besl(core_if,
752 module_params.baseline_besl);
754 if (module_params.deep_besl != -1) {
756 dwc_otg_set_param_deep_besl(core_if,
757 module_params.deep_besl);
759 if (module_params.ic_usb_cap != -1) {
761 dwc_otg_set_param_ic_usb_cap(core_if,
762 module_params.ic_usb_cap);
764 if (module_params.tx_thr_length != -1) {
766 dwc_otg_set_param_tx_thr_length(core_if,
770 if (module_params.rx_thr_length != -1) {
772 dwc_otg_set_param_rx_thr_length(core_if,
773 module_params.rx_thr_length);
775 if (module_params.ahb_thr_ratio != -1) {
777 dwc_otg_set_param_ahb_thr_ratio(core_if,
781 if (module_params.power_down != -1) {
783 dwc_otg_set_param_power_down(core_if,
784 module_params.power_down);
786 if (module_params.reload_ctl != -1) {
788 dwc_otg_set_param_reload_ctl(core_if,
789 module_params.reload_ctl);
792 if (module_params.dev_out_nak != -1) {
794 dwc_otg_set_param_dev_out_nak(core_if,
795 module_params.dev_out_nak);
798 if (module_params.cont_on_bna != -1) {
800 dwc_otg_set_param_cont_on_bna(core_if,
801 module_params.cont_on_bna);
804 if (module_params.ahb_single != -1) {
806 dwc_otg_set_param_ahb_single(core_if,
807 module_params.ahb_single);
810 if (module_params.otg_ver != -1) {
812 dwc_otg_set_param_otg_ver(core_if, module_params.otg_ver);
814 if (module_params.adp_enable != -1) {
816 dwc_otg_set_param_adp_enable(core_if,
817 module_params.adp_enable);
823 * This function is the top level interrupt handler for the Common
824 * (Device and host modes) interrupts.
826 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
828 int32_t retval = IRQ_NONE;
830 retval = dwc_otg_handle_common_intr(dev);
832 /* S3C2410X_CLEAR_EINTPEND(); */
834 return IRQ_RETVAL(retval);
837 #ifdef CONFIG_USB20_HOST
839 * This function is called when a lm_device is unregistered with the
840 * dwc_otg_driver. This happens, for example, when the rmmod command is
841 * executed. The device may or may not be electrically present. If it is
842 * present, the driver stops device processing. Any resources used on behalf
843 * of this device are freed.
847 static int host20_driver_remove(struct platform_device *_dev)
850 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
851 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
854 /* Memory allocation for the dwc_otg_device failed. */
855 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
858 #ifndef DWC_DEVICE_ONLY
862 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
867 #ifndef DWC_HOST_ONLY
871 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
879 if (otg_dev->common_irq_installed) {
880 /* free_irq(_dev->irq, otg_dev); */
881 free_irq(platform_get_irq(_dev, 0), otg_dev);
883 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
888 if (otg_dev->core_if) {
889 dwc_otg_cil_remove(otg_dev->core_if);
891 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
896 * Remove the device attributes
898 dwc_otg_attr_remove(_dev);
903 if (otg_dev->os_dep.base) {
904 iounmap(otg_dev->os_dep.base);
909 * Clear the drvdata pointer.
912 dwc_set_device_platform_data(_dev, 0);
917 static const struct of_device_id usb20_host_of_match[] = {
919 .compatible = "rockchip,rk3188_usb20_host",
920 .data = &usb20host_pdata_rk3188,
923 .compatible = "rockchip,rk3288_usb20_host",
924 .data = &usb20host_pdata_rk3288,
927 .compatible = "rockchip,rk3036_usb20_host",
928 .data = &usb20host_pdata_rk3036,
931 .compatible = "rockchip,rk3126_usb20_host",
932 .data = &usb20host_pdata_rk3126,
937 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
940 * This function is called when an lm_device is bound to a
941 * dwc_otg_driver. It creates the driver components required to
942 * control the device (CIL, HCD, and PCD) and it initializes the
943 * device. The driver components are stored in a dwc_otg_device
944 * structure. A reference to the dwc_otg_device is saved in the
945 * lm_device. This allows the driver to access the dwc_otg_device
946 * structure on subsequent calls to driver methods for this device.
948 * @param _dev Bus device
950 static int host20_driver_probe(struct platform_device *_dev)
954 struct resource *res_base;
955 dwc_otg_device_t *dwc_otg_device;
956 struct device *dev = &_dev->dev;
957 struct device_node *node = _dev->dev.of_node;
958 struct dwc_otg_platform_data *pldata;
959 const struct of_device_id *match =
960 of_match_device(of_match_ptr(usb20_host_of_match), &_dev->dev);
962 if (match && match->data) {
963 pldata = (void *)match->data;
966 dev_err(dev, "usb20otg match failed\n");
971 dev_err(dev, "device node not found\n");
978 if (pldata->clock_init) {
979 pldata->clock_init(pldata);
980 pldata->clock_enable(pldata, 1);
983 if (pldata->phy_suspend)
984 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
986 if (pldata->soft_reset)
987 pldata->soft_reset(pldata, RST_POR);
989 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
991 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
993 if (!dwc_otg_device) {
994 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
999 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1000 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1003 * Map the DWC_otg Core memory into virtual address space.
1006 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1008 if (!dwc_otg_device->os_dep.base) {
1009 dev_err(&_dev->dev, "ioremap() failed\n");
1010 DWC_FREE(dwc_otg_device);
1014 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1016 /* Set device flags indicating whether the HCD supports DMA. */
1017 if (!_dev->dev.dma_mask)
1018 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1019 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1024 * Initialize driver data to point to the global DWC_otg
1028 dwc_set_device_platform_data(_dev, dwc_otg_device);
1029 pldata->privdata = dwc_otg_device;
1030 dwc_otg_device->pldata = (void *)pldata;
1032 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1034 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1036 if (!dwc_otg_device->core_if) {
1037 dev_err(&_dev->dev, "CIL initialization failed!\n");
1042 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1045 * Attempt to ensure this device is really a DWC_otg Controller.
1046 * Read and verify the SNPSID register contents. The value should be
1047 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1048 * as in "OTG version 2.XX" or "OTG version 3.XX".
1051 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1053 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1055 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1056 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1062 * Validate parameter values.
1064 if (set_parameters(dwc_otg_device->core_if, dwc_host_module_params)) {
1070 * Create Device Attributes in sysfs
1072 dwc_otg_attr_create(_dev);
1075 * Disable the global interrupt until all the interrupt
1076 * handlers are installed.
1078 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1081 * Install the interrupt handler for the common interrupts before
1082 * enabling common interrupts in core_init below.
1084 irq = platform_get_irq(_dev, 0);
1085 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1086 retval = request_irq(irq, dwc_otg_common_irq,
1087 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1089 DWC_ERROR("request of irq%d failed\n", irq);
1093 dwc_otg_device->common_irq_installed = 1;
1097 * Initialize the DWC_otg core.
1098 * In order to reduce the time of initialization,
1099 * we do core soft reset after connection detected.
1101 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1104 * Initialize the HCD
1106 retval = host20_hcd_init(_dev);
1108 DWC_ERROR("hcd_init failed\n");
1109 dwc_otg_device->hcd = NULL;
1113 clk_set_rate(pldata->phyclk_480m, 480000000);
1115 * Enable the global interrupt after all the interrupt
1116 * handlers are installed if there is no ADP support else
1117 * perform initial actions required for Internal ADP logic.
1119 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1120 if (pldata->phy_status == USB_PHY_ENABLED) {
1121 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1123 pldata->clock_enable(pldata, 0);
1125 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1127 dwc_otg_adp_start(dwc_otg_device->core_if,
1128 dwc_otg_is_host_mode(dwc_otg_device->
1134 host20_driver_remove(_dev);
1136 if (pldata->clock_enable)
1137 pldata->clock_enable(pldata, 0);
1143 static int dwc_otg_driver_suspend(struct platform_device *_dev,
1149 static int dwc_otg_driver_resume(struct platform_device *_dev)
1154 static void dwc_otg_driver_shutdown(struct platform_device *_dev)
1156 struct device *dev = &_dev->dev;
1157 dwc_otg_device_t *otg_dev = dev->platform_data;
1158 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1159 struct dwc_otg_platform_data *pldata = otg_dev->pldata;
1160 dctl_data_t dctl = {.d32 = 0 };
1161 dwc_otg_pcd_t *pcd = core_if->otg_dev->pcd;
1163 DWC_PRINTF("%s: disconnect USB %s mode\n", __func__,
1164 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1166 if (dwc_otg_is_host_mode(core_if)) {
1167 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1168 core_if->hcd_cb->stop(core_if->hcd_cb_p);
1170 cancel_delayed_work_sync(&pcd->check_vbus_work);
1171 /* soft disconnect */
1173 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
1174 dctl.b.sftdiscon = 1;
1175 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
1178 /* Clear any pending interrupts */
1179 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1181 if (pldata->dwc_otg_uart_mode != NULL)
1182 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1183 if (pldata->phy_suspend != NULL)
1184 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1189 * This structure defines the methods to be called by a bus driver
1190 * during the lifecycle of a device on that bus. Both drivers and
1191 * devices are registered with a bus driver. The bus driver matches
1192 * devices to drivers based on information in the device and driver
1195 * The probe function is called when the bus driver matches a device
1196 * to this driver. The remove function is called when a device is
1197 * unregistered with the bus driver.
1199 #ifdef CONFIG_USB20_HOST
1200 static struct platform_driver dwc_host_driver = {
1202 .name = (char *)dwc_host20_driver_name,
1203 .of_match_table = of_match_ptr(usb20_host_of_match),
1205 .probe = host20_driver_probe,
1206 .remove = host20_driver_remove,
1207 .suspend = dwc_otg_driver_suspend,
1208 .resume = dwc_otg_driver_resume,
1212 #ifdef CONFIG_USB20_OTG
1214 * This function is called when a lm_device is unregistered with the
1215 * dwc_otg_driver. This happens, for example, when the rmmod command is
1216 * executed. The device may or may not be electrically present. If it is
1217 * present, the driver stops device processing. Any resources used on behalf
1218 * of this device are freed.
1222 static int otg20_driver_remove(struct platform_device *_dev)
1225 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1226 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1229 /* Memory allocation for the dwc_otg_device failed. */
1230 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1233 #ifndef DWC_DEVICE_ONLY
1237 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1242 #ifndef DWC_HOST_ONLY
1246 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1253 if (otg_dev->common_irq_installed) {
1254 /* free_irq(_dev->irq, otg_dev); */
1255 free_irq(platform_get_irq(_dev, 0), otg_dev);
1257 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n",
1262 if (otg_dev->core_if) {
1263 dwc_otg_cil_remove(otg_dev->core_if);
1265 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1270 * Remove the device attributes
1272 dwc_otg_attr_remove(_dev);
1275 * Return the memory.
1277 if (otg_dev->os_dep.base)
1278 iounmap(otg_dev->os_dep.base);
1282 * Clear the drvdata pointer.
1285 dwc_set_device_platform_data(_dev, 0);
1290 static const struct of_device_id usb20_otg_of_match[] = {
1292 .compatible = "rockchip,rk3188_usb20_otg",
1293 .data = &usb20otg_pdata_rk3188,
1296 .compatible = "rockchip,rk3288_usb20_otg",
1297 .data = &usb20otg_pdata_rk3288,
1300 .compatible = "rockchip,rk3036_usb20_otg",
1301 .data = &usb20otg_pdata_rk3036,
1304 .compatible = "rockchip,rk3126_usb20_otg",
1305 .data = &usb20otg_pdata_rk3126,
1308 .compatible = "rockchip,rk3368_usb20_otg",
1309 .data = &usb20otg_pdata_rk3368,
1314 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1317 * This function is called when an lm_device is bound to a
1318 * dwc_otg_driver. It creates the driver components required to
1319 * control the device (CIL, HCD, and PCD) and it initializes the
1320 * device. The driver components are stored in a dwc_otg_device
1321 * structure. A reference to the dwc_otg_device is saved in the
1322 * lm_device. This allows the driver to access the dwc_otg_device
1323 * structure on subsequent calls to driver methods for this device.
1325 * @param _dev Bus device
1327 static int otg20_driver_probe(struct platform_device *_dev)
1332 struct resource *res_base;
1333 dwc_otg_device_t *dwc_otg_device;
1334 struct device *dev = &_dev->dev;
1335 struct device_node *node = _dev->dev.of_node;
1336 struct dwc_otg_platform_data *pldata;
1337 const struct of_device_id *match =
1338 of_match_device(of_match_ptr(usb20_otg_of_match), &_dev->dev);
1340 if (match && match->data) {
1341 pldata = (void *)match->data;
1344 dev_err(dev, "usb20otg match failed\n");
1349 dev_err(dev, "device node not found\n");
1353 if (pldata->hw_init)
1356 if (pldata->clock_init) {
1357 pldata->clock_init(pldata);
1358 pldata->clock_enable(pldata, 1);
1361 if (pldata->phy_suspend)
1362 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1364 if (pldata->dwc_otg_uart_mode)
1365 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1367 /* do reset later, because reset need about
1368 * 100ms to ensure otg id state change.
1371 if(pldata->soft_reset)
1372 pldata->soft_reset();
1376 res_base = platform_get_resource(_dev, IORESOURCE_MEM, 0);
1378 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1380 if (!dwc_otg_device) {
1381 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1386 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1387 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1390 * Map the DWC_otg Core memory into virtual address space.
1393 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1395 if (!dwc_otg_device->os_dep.base) {
1396 dev_err(&_dev->dev, "ioremap() failed\n");
1397 DWC_FREE(dwc_otg_device);
1401 dev_dbg(&_dev->dev, "base=0x%p\n", dwc_otg_device->os_dep.base);
1403 /* Set device flags indicating whether the HCD supports DMA. */
1404 if (!_dev->dev.dma_mask)
1405 _dev->dev.dma_mask = &_dev->dev.coherent_dma_mask;
1406 retval = dma_set_coherent_mask(&_dev->dev, DMA_BIT_MASK(32));
1411 * Initialize driver data to point to the global DWC_otg
1415 g_otgdev = dwc_otg_device;
1416 pldata->privdata = dwc_otg_device;
1417 dwc_otg_device->pldata = pldata;
1419 dwc_set_device_platform_data(_dev, dwc_otg_device);
1421 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1423 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1424 if (!dwc_otg_device->core_if) {
1425 dev_err(&_dev->dev, "CIL initialization failed!\n");
1430 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1432 * Attempt to ensure this device is really a DWC_otg Controller.
1433 * Read and verify the SNPSID register contents. The value should be
1434 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1435 * as in "OTG version 2.XX" or "OTG version 3.XX".
1438 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1440 && ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) !=
1442 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1443 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1449 * Validate parameter values.
1451 if (set_parameters(dwc_otg_device->core_if, dwc_otg_module_params)) {
1457 * Create Device Attributes in sysfs
1459 dwc_otg_attr_create(_dev);
1462 * Disable the global interrupt until all the interrupt
1463 * handlers are installed.
1465 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1468 * Install the interrupt handler for the common interrupts before
1469 * enabling common interrupts in core_init below.
1471 irq = platform_get_irq(_dev, 0);
1472 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n", irq);
1473 retval = request_irq(irq, dwc_otg_common_irq,
1474 IRQF_SHARED, "dwc_otg", dwc_otg_device);
1476 DWC_ERROR("request of irq%d failed\n", irq);
1480 dwc_otg_device->common_irq_installed = 1;
1484 * Initialize the DWC_otg core.
1485 * In order to reduce the time of initialization,
1486 * we do core soft reset after connection detected.
1488 dwc_otg_core_init_no_reset(dwc_otg_device->core_if);
1491 * 0 - USB_MODE_NORMAL
1492 * 1 - USB_MODE_FORCE_HOST
1493 * 2 - USB_MODE_FORCE_DEVICE
1495 of_property_read_u32(node, "rockchip,usb-mode", &val);
1496 dwc_otg_device->core_if->usb_mode = val;
1498 #ifndef DWC_HOST_ONLY
1500 * Initialize the PCD
1502 retval = pcd_init(_dev);
1504 DWC_ERROR("pcd_init failed\n");
1505 dwc_otg_device->pcd = NULL;
1509 #ifndef DWC_DEVICE_ONLY
1511 * Initialize the HCD
1513 retval = otg20_hcd_init(_dev);
1515 DWC_ERROR("hcd_init failed\n");
1516 dwc_otg_device->hcd = NULL;
1521 * Enable the global interrupt after all the interrupt
1522 * handlers are installed if there is no ADP support else
1523 * perform initial actions required for Internal ADP logic.
1525 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if)) {
1526 if (dwc_otg_device->core_if->usb_mode == USB_MODE_NORMAL &&
1527 pldata->phy_status == USB_PHY_ENABLED) {
1528 pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1530 pldata->clock_enable(pldata, 0);
1532 /* dwc_otg_enable_global_interrupts(dwc_otg_device->core_if); */
1534 dwc_otg_adp_start(dwc_otg_device->core_if,
1535 dwc_otg_is_host_mode(dwc_otg_device->
1541 otg20_driver_remove(_dev);
1544 if (pldata->clock_enable)
1545 pldata->clock_enable(pldata, 0);
1551 static int dwc_otg_pm_suspend(struct device *dev)
1553 dwc_otg_device_t *dwc_otg_device;
1554 struct dwc_otg_platform_data *pdata_otg;
1556 dwc_otg_device = dev_get_platdata(dev);
1558 dev_dbg(dev, "dwc_otg PM suspend\n");
1560 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1563 pdata_otg = dwc_otg_device->pldata;
1564 pdata_otg->phy_suspend(pdata_otg, USB_PHY_SUSPEND);
1569 static int dwc_otg_pm_resume(struct device *dev)
1571 dwc_otg_device_t *dwc_otg_device;
1572 struct dwc_otg_platform_data *pdata_otg;
1574 dwc_otg_device = dev_get_platdata(dev);
1576 dev_dbg(dev, "dwc_otg PM resume\n");
1578 if (dwc_otg_device->core_if->op_state == B_PERIPHERAL)
1581 pdata_otg = dwc_otg_device->pldata;
1582 pdata_otg->phy_suspend(pdata_otg, USB_PHY_ENABLED);
1587 #define dwc_otg_pm_suspend NULL
1588 #define dwc_otg_pm_resume NULL
1591 static const struct dev_pm_ops dwc_otg_dev_pm_ops = {
1592 .suspend = dwc_otg_pm_suspend,
1593 .resume = dwc_otg_pm_resume,
1596 static struct platform_driver dwc_otg_driver = {
1598 .name = (char *)dwc_otg20_driver_name,
1599 .of_match_table = of_match_ptr(usb20_otg_of_match),
1601 .pm = &dwc_otg_dev_pm_ops,
1604 .probe = otg20_driver_probe,
1605 .remove = otg20_driver_remove,
1606 .suspend = dwc_otg_driver_suspend,
1607 .resume = dwc_otg_driver_resume,
1608 .shutdown = dwc_otg_driver_shutdown,
1612 void rk_usb_power_up(void)
1614 struct dwc_otg_platform_data *pldata_otg;
1615 struct dwc_otg_platform_data *pldata_host;
1616 struct rkehci_platform_data *pldata_ehci;
1618 if (cpu_is_rk3288()) {
1619 #ifdef CONFIG_RK_USB_UART
1620 /* enable USB bypass UART function */
1621 writel_relaxed(0x00c00000 | usb_to_uart_status,
1622 RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1625 /* unset siddq,the analog blocks are powered up */
1626 #ifdef CONFIG_USB20_OTG
1627 pldata_otg = &usb20otg_pdata_rk3288;
1629 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1630 writel_relaxed((0x01 << 13) << 16,
1632 RK3288_GRF_UOC0_CON0);
1635 #ifdef CONFIG_USB20_HOST
1636 pldata_host = &usb20host_pdata_rk3288;
1638 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1639 writel_relaxed((0x01 << 13) << 16,
1641 RK3288_GRF_UOC2_CON0);
1644 #ifdef CONFIG_USB_EHCI_RK
1645 pldata_ehci = &rkehci_pdata_rk3288;
1647 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1648 writel_relaxed((0x01 << 13) << 16,
1650 RK3288_GRF_UOC1_CON0);
1655 dwc_otg_device_t *otg_dev = g_otgdev;
1660 pldata_otg = otg_dev->pldata;
1661 if (pldata_otg && pldata_otg->phy_power_down)
1662 pldata_otg->phy_power_down(PHY_POWER_UP);
1666 void rk_usb_power_down(void)
1668 struct dwc_otg_platform_data *pldata_otg;
1669 struct dwc_otg_platform_data *pldata_host;
1670 struct rkehci_platform_data *pldata_ehci;
1672 if (cpu_is_rk3288()) {
1673 #ifdef CONFIG_RK_USB_UART
1674 /* disable USB bypass UART function */
1675 usb_to_uart_status =
1676 readl_relaxed(RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1677 writel_relaxed(0x00c00000, RK_GRF_VIRT + RK3288_GRF_UOC0_CON3);
1679 /* set siddq,the analog blocks are powered down
1681 * 1. Before asserting SIDDQ, ensure that VDATSRCENB0,
1682 * VDATDETENB0, DCDENB0, BYPASSSEL0, ADPPRBENB0,
1683 * and TESTBURNIN are set to 1'b0.
1684 * 2. Before asserting SIDDQ, ensure that phy enter suspend.*/
1685 #ifdef CONFIG_USB20_OTG
1686 pldata_otg = &usb20otg_pdata_rk3288;
1688 if (pldata_otg->phy_status == USB_PHY_SUSPEND)
1689 writel_relaxed((0x01 << 13) |
1690 ((0x01 << 13) << 16),
1692 RK3288_GRF_UOC0_CON0);
1695 #ifdef CONFIG_USB20_HOST
1696 pldata_host = &usb20host_pdata_rk3288;
1698 if (pldata_host->phy_status == USB_PHY_SUSPEND)
1699 writel_relaxed((0x01 << 13) |
1700 ((0x01 << 13) << 16),
1702 RK3288_GRF_UOC2_CON0);
1705 #ifdef CONFIG_USB_EHCI_RK
1706 pldata_ehci = &rkehci_pdata_rk3288;
1708 if (pldata_ehci->phy_status == USB_PHY_SUSPEND)
1709 writel_relaxed((0x01 << 13) |
1710 ((0x01 << 13) << 16),
1712 RK3288_GRF_UOC1_CON0);
1716 dwc_otg_device_t *otg_dev = g_otgdev;
1721 pldata_otg = otg_dev->pldata;
1722 if (pldata_otg && pldata_otg->phy_power_down)
1723 pldata_otg->phy_power_down(PHY_POWER_DOWN);
1727 EXPORT_SYMBOL(rk_usb_power_up);
1728 EXPORT_SYMBOL(rk_usb_power_down);
1730 * This function is called when the dwc_otg_driver is installed with the
1731 * insmod command. It registers the dwc_otg_driver structure with the
1732 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1733 * to be called. In addition, the bus driver will automatically expose
1734 * attributes defined for the device and driver in the special sysfs file
1739 static int __init dwc_otg_driver_init(void)
1744 #ifdef CONFIG_USB20_OTG
1745 /* register otg20 */
1746 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1747 DWC_DRIVER_VERSION);
1749 retval = platform_driver_register(&dwc_otg_driver);
1751 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1756 driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1758 driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1760 driver_create_file(&dwc_otg_driver.driver,
1761 &driver_attr_dwc_otg_conn_en);
1763 driver_create_file(&dwc_otg_driver.driver,
1764 &driver_attr_vbus_status);
1766 driver_create_file(&dwc_otg_driver.driver,
1767 &driver_attr_force_usb_mode);
1769 driver_create_file(&dwc_otg_driver.driver,
1770 &driver_attr_op_state);
1774 /* register host20 */
1775 #ifdef CONFIG_USB20_HOST
1776 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1777 DWC_DRIVER_VERSION);
1779 retval = platform_driver_register(&dwc_host_driver);
1781 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1786 driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1788 driver_create_file(&dwc_host_driver.driver,
1789 &driver_attr_debuglevel);
1794 module_init(dwc_otg_driver_init);
1797 * This function is called when the driver is removed from the kernel
1798 * with the rmmod command. The driver unregisters itself with its bus
1802 static void __exit dwc_otg_driver_cleanup(void)
1804 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1806 #ifdef CONFIG_USB20_HOST
1808 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1809 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1810 platform_driver_unregister(&dwc_host_driver);
1811 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1814 #ifdef CONFIG_USB20_OTG
1816 driver_remove_file(&dwc_otg_driver.driver,
1817 &driver_attr_dwc_otg_conn_en);
1818 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1819 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1820 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1821 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1822 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_op_state);
1823 platform_driver_unregister(&dwc_otg_driver);
1824 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1828 module_exit(dwc_otg_driver_cleanup);
1830 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1831 MODULE_AUTHOR("Synopsys Inc.");
1832 MODULE_LICENSE("GPL");
1834 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1835 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1836 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1837 MODULE_PARM_DESC(opt, "OPT Mode");
1838 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1839 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1841 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1843 MODULE_PARM_DESC(dma_desc_enable,
1844 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1846 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1848 MODULE_PARM_DESC(dma_burst_size,
1849 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1850 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1851 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1852 module_param_named(host_support_fs_ls_low_power,
1853 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1855 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1856 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1857 module_param_named(host_ls_low_power_phy_clk,
1858 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1859 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1860 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1861 module_param_named(enable_dynamic_fifo,
1862 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1863 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1864 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1866 MODULE_PARM_DESC(data_fifo_size,
1867 "Total number of words in the data FIFO memory 32-32768");
1868 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1870 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1871 module_param_named(dev_nperio_tx_fifo_size,
1872 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1873 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1874 "Number of words in the non-periodic Tx FIFO 16-32768");
1875 module_param_named(dev_perio_tx_fifo_size_1,
1876 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1877 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1878 "Number of words in the periodic Tx FIFO 4-768");
1879 module_param_named(dev_perio_tx_fifo_size_2,
1880 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1881 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1882 "Number of words in the periodic Tx FIFO 4-768");
1883 module_param_named(dev_perio_tx_fifo_size_3,
1884 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1885 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1886 "Number of words in the periodic Tx FIFO 4-768");
1887 module_param_named(dev_perio_tx_fifo_size_4,
1888 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1889 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1890 "Number of words in the periodic Tx FIFO 4-768");
1891 module_param_named(dev_perio_tx_fifo_size_5,
1892 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1893 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1894 "Number of words in the periodic Tx FIFO 4-768");
1895 module_param_named(dev_perio_tx_fifo_size_6,
1896 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1897 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1898 "Number of words in the periodic Tx FIFO 4-768");
1899 module_param_named(dev_perio_tx_fifo_size_7,
1900 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1901 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1902 "Number of words in the periodic Tx FIFO 4-768");
1903 module_param_named(dev_perio_tx_fifo_size_8,
1904 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1905 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1906 "Number of words in the periodic Tx FIFO 4-768");
1907 module_param_named(dev_perio_tx_fifo_size_9,
1908 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1909 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1910 "Number of words in the periodic Tx FIFO 4-768");
1911 module_param_named(dev_perio_tx_fifo_size_10,
1912 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1913 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1914 "Number of words in the periodic Tx FIFO 4-768");
1915 module_param_named(dev_perio_tx_fifo_size_11,
1916 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1917 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1918 "Number of words in the periodic Tx FIFO 4-768");
1919 module_param_named(dev_perio_tx_fifo_size_12,
1920 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1921 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1922 "Number of words in the periodic Tx FIFO 4-768");
1923 module_param_named(dev_perio_tx_fifo_size_13,
1924 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1925 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1926 "Number of words in the periodic Tx FIFO 4-768");
1927 module_param_named(dev_perio_tx_fifo_size_14,
1928 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1929 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1930 "Number of words in the periodic Tx FIFO 4-768");
1931 module_param_named(dev_perio_tx_fifo_size_15,
1932 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1933 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1934 "Number of words in the periodic Tx FIFO 4-768");
1935 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1937 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1938 module_param_named(host_nperio_tx_fifo_size,
1939 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1940 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1941 "Number of words in the non-periodic Tx FIFO 16-32768");
1942 module_param_named(host_perio_tx_fifo_size,
1943 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1944 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1945 "Number of words in the host periodic Tx FIFO 16-32768");
1946 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1948 /** @todo Set the max to 512K, modify checks */
1949 MODULE_PARM_DESC(max_transfer_size,
1950 "The maximum transfer size supported in bytes 2047-65535");
1951 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1953 MODULE_PARM_DESC(max_packet_count,
1954 "The maximum number of packets in a transfer 15-511");
1955 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1957 MODULE_PARM_DESC(host_channels,
1958 "The number of host channel registers to use 1-16");
1959 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1961 MODULE_PARM_DESC(dev_endpoints,
1962 "The number of endpoints in addition to EP0 available for device mode 1-15");
1963 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1964 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1965 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1967 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1968 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1969 MODULE_PARM_DESC(phy_ulpi_ddr,
1970 "ULPI at double or single data rate 0=Single 1=Double");
1971 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1973 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1974 "ULPI PHY using internal or external vbus 0=Internal");
1975 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1976 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1977 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1978 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1979 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1980 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1981 module_param_named(debug, g_dbg_lvl, int, 0444);
1982 MODULE_PARM_DESC(debug, "");
1984 module_param_named(en_multiple_tx_fifo,
1985 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1986 MODULE_PARM_DESC(en_multiple_tx_fifo,
1987 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1988 module_param_named(dev_tx_fifo_size_1,
1989 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1990 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1991 module_param_named(dev_tx_fifo_size_2,
1992 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1993 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1994 module_param_named(dev_tx_fifo_size_3,
1995 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1996 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1997 module_param_named(dev_tx_fifo_size_4,
1998 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1999 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2000 module_param_named(dev_tx_fifo_size_5,
2001 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_6,
2004 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2005 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2006 module_param_named(dev_tx_fifo_size_7,
2007 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_8,
2010 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2011 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2012 module_param_named(dev_tx_fifo_size_9,
2013 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2015 module_param_named(dev_tx_fifo_size_10,
2016 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2017 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2018 module_param_named(dev_tx_fifo_size_11,
2019 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2020 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2021 module_param_named(dev_tx_fifo_size_12,
2022 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2023 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2024 module_param_named(dev_tx_fifo_size_13,
2025 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2026 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2027 module_param_named(dev_tx_fifo_size_14,
2028 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2029 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2030 module_param_named(dev_tx_fifo_size_15,
2031 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2032 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2034 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2035 MODULE_PARM_DESC(thr_ctl,
2036 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2037 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
2039 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2040 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
2042 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2044 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
2045 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
2046 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
2047 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
2049 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
2050 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
2051 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int,
2053 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
2054 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
2055 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
2057 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
2058 MODULE_PARM_DESC(ic_usb_cap,
2059 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
2060 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
2062 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
2063 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
2064 MODULE_PARM_DESC(power_down, "Power Down Mode");
2065 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
2066 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
2067 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
2068 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
2069 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
2070 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
2071 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
2072 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
2073 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
2074 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
2075 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
2076 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
2078 /** @page "Module Parameters"
2080 * The following parameters may be specified when starting the module.
2081 * These parameters define how the DWC_otg controller should be
2082 * configured. Parameter values are passed to the CIL initialization
2083 * function dwc_otg_cil_init
2085 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2089 <tr><td>Parameter Name</td><td>Meaning</td></tr>
2093 <td>Specifies the OTG capabilities. The driver will automatically detect the
2094 value for this parameter if none is specified.
2095 - 0: HNP and SRP capable (default, if available)
2096 - 1: SRP Only capable
2097 - 2: No HNP/SRP capable
2102 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2103 The driver will automatically detect the value for this parameter if none is
2106 - 1: DMA (default, if available)
2110 <td>dma_burst_size</td>
2111 <td>The DMA Burst size (applicable only for External DMA Mode).
2112 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2117 <td>Specifies the maximum speed of operation in host and device mode. The
2118 actual speed depends on the speed of the attached device and the value of
2120 - 0: High Speed (default)
2125 <td>host_support_fs_ls_low_power</td>
2126 <td>Specifies whether low power mode is supported when attached to a Full
2127 Speed or Low Speed device in host mode.
2128 - 0: Don't support low power mode (default)
2129 - 1: Support low power mode
2133 <td>host_ls_low_power_phy_clk</td>
2134 <td>Specifies the PHY clock rate in low power mode when connected to a Low
2135 Speed device in host mode. This parameter is applicable only if
2136 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2137 - 0: 48 MHz (default)
2142 <td>enable_dynamic_fifo</td>
2143 <td> Specifies whether FIFOs may be resized by the driver software.
2144 - 0: Use cC FIFO size parameters
2145 - 1: Allow dynamic FIFO sizing (default)
2149 <td>data_fifo_size</td>
2150 <td>Total number of 4-byte words in the data FIFO memory. This memory
2151 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2152 - Values: 32 to 32768 (default 8192)
2154 Note: The total FIFO memory depth in the FPGA configuration is 8192.
2158 <td>dev_rx_fifo_size</td>
2159 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2160 FIFO sizing is enabled.
2161 - Values: 16 to 32768 (default 1064)
2165 <td>dev_nperio_tx_fifo_size</td>
2166 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2167 dynamic FIFO sizing is enabled.
2168 - Values: 16 to 32768 (default 1024)
2172 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2173 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2174 when dynamic FIFO sizing is enabled.
2175 - Values: 4 to 768 (default 256)
2179 <td>host_rx_fifo_size</td>
2180 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2182 - Values: 16 to 32768 (default 1024)
2186 <td>host_nperio_tx_fifo_size</td>
2187 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2188 dynamic FIFO sizing is enabled in the core.
2189 - Values: 16 to 32768 (default 1024)
2193 <td>host_perio_tx_fifo_size</td>
2194 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2196 - Values: 16 to 32768 (default 1024)
2200 <td>max_transfer_size</td>
2201 <td>The maximum transfer size supported in bytes.
2202 - Values: 2047 to 65,535 (default 65,535)
2206 <td>max_packet_count</td>
2207 <td>The maximum number of packets in a transfer.
2208 - Values: 15 to 511 (default 511)
2212 <td>host_channels</td>
2213 <td>The number of host channel registers to use.
2214 - Values: 1 to 16 (default 12)
2216 Note: The FPGA configuration supports a maximum of 12 host channels.
2220 <td>dev_endpoints</td>
2221 <td>The number of endpoints in addition to EP0 available for device mode
2223 - Values: 1 to 15 (default 6 IN and OUT)
2225 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2231 <td>Specifies the type of PHY interface to use. By default, the driver will
2232 automatically detect the phy_type.
2234 - 1: UTMI+ (default, if available)
2239 <td>phy_utmi_width</td>
2240 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2241 phy_type of UTMI+. Also, this parameter is applicable only if the
2242 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2243 core has been configured to work at either data path width.
2244 - Values: 8 or 16 bits (default 16)
2248 <td>phy_ulpi_ddr</td>
2249 <td>Specifies whether the ULPI operates at double or single data rate. This
2250 parameter is only applicable if phy_type is ULPI.
2251 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2252 - 1: double data rate ULPI interface with 4 bit wide data bus
2257 <td>Specifies whether to use the I2C interface for full speed PHY. This
2258 parameter is only applicable if PHY_TYPE is FS.
2259 - 0: Disabled (default)
2265 <td>Specifies whether to use ULPI FS/LS mode only.
2266 - 0: Disabled (default)
2272 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
2273 - 0: Disabled (default)
2278 <td>en_multiple_tx_fifo</td>
2279 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2280 The driver will automatically detect the value for this parameter if none is
2283 - 1: Enabled (default, if available)
2287 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2288 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2289 when dynamic FIFO sizing is enabled.
2290 - Values: 4 to 768 (default 256)
2294 <td>tx_thr_length</td>
2295 <td>Transmit Threshold length in 32 bit double words
2296 - Values: 8 to 128 (default 64)
2300 <td>rx_thr_length</td>
2301 <td>Receive Threshold length in 32 bit double words
2302 - Values: 8 to 128 (default 64)
2307 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
2308 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
2309 Rx transfers accordingly.
2310 The driver will automatically detect the value for this parameter if none is
2312 - Values: 0 to 7 (default 0)
2313 Bit values indicate:
2314 - 0: Thresholding disabled
2315 - 1: Thresholding enabled
2319 <td>dma_desc_enable</td>
2320 <td>Specifies whether to enable Descriptor DMA mode.
2321 The driver will automatically detect the value for this parameter if none is
2323 - 0: Descriptor DMA disabled
2324 - 1: Descriptor DMA (default, if available)
2329 <td>Specifies whether to enable MPI enhancement mode.
2330 The driver will automatically detect the value for this parameter if none is
2332 - 0: MPI disabled (default)
2338 <td>Specifies whether to enable PTI enhancement support.
2339 The driver will automatically detect the value for this parameter if none is
2341 - 0: PTI disabled (default)
2347 <td>Specifies whether to enable LPM support.
2348 The driver will automatically detect the value for this parameter if none is
2351 - 1: LPM enable (default, if available)
2355 <td>besl_enable</td>
2356 <td>Specifies whether to enable LPM Errata support.
2357 The driver will automatically detect the value for this parameter if none is
2359 - 0: LPM Errata disabled (default)
2360 - 1: LPM Errata enable
2364 <td>baseline_besl</td>
2365 <td>Specifies the baseline besl value.
2366 - Values: 0 to 15 (default 0)
2371 <td>Specifies the deep besl value.
2372 - Values: 0 to 15 (default 15)
2377 <td>Specifies whether to enable IC_USB capability.
2378 The driver will automatically detect the value for this parameter if none is
2380 - 0: IC_USB disabled (default, if available)
2385 <td>ahb_thr_ratio</td>
2386 <td>Specifies AHB Threshold ratio.
2387 - Values: 0 to 3 (default 0)
2392 <td>Specifies Power Down(Hibernation) Mode.
2393 The driver will automatically detect the value for this parameter if none is
2395 - 0: Power Down disabled (default)
2396 - 2: Power Down enabled
2401 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2402 run time. The driver will automatically detect the value for this parameter if
2403 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2404 the core might misbehave.
2405 - 0: Reload Control disabled (default)
2406 - 1: Reload Control enabled
2410 <td>dev_out_nak</td>
2411 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2412 The driver will automatically detect the value for this parameter if
2413 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2414 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2415 - 1: The core sets NAK after Bulk OUT transfer complete
2419 <td>cont_on_bna</td>
2420 <td>Specifies whether Enable Continue on BNA enabled or no.
2421 After receiving BNA interrupt the core disables the endpoint,when the
2422 endpoint is re-enabled by the application the
2423 - 0: Core starts processing from the DOEPDMA descriptor (default)
2424 - 1: Core starts processing from the descriptor which received the BNA.
2425 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2430 <td>This bit when programmed supports SINGLE transfers for remainder data
2431 in a transfer for DMA mode of operation.
2432 - 0: The remainder data will be sent using INCR burst size (default)
2433 - 1: The remainder data will be sent using SINGLE burst size.
2438 <td>Specifies whether ADP feature is enabled.
2439 The driver will automatically detect the value for this parameter if none is
2441 - 0: ADP feature disabled (default)
2442 - 1: ADP feature enabled
2447 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2449 - 0: OTG 2.0 support disabled (default)
2450 - 1: OTG 2.0 support enabled