1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_driver.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
35 * The dwc_otg_driver module provides the initialization and cleanup entry
36 * points for the DWC_otg driver. This module will be dynamically installed
37 * after Linux is booted using the insmod command. When the module is
38 * installed, the dwc_otg_driver_init function is called. When the module is
39 * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
41 * This module also defines a data structure for the dwc_otg_driver, which is
42 * used in conjunction with the standard ARM lm_device structure. These
43 * structures allow the OTG driver to comply with the standard Linux driver
44 * model in which devices and drivers are registered with a bus driver. This
45 * has the benefit that Linux can expose attributes of the driver and device
46 * in its special sysfs file system. Users can then read or write files in
47 * this file system to perform diagnostics on the driver components or the
51 #include "dwc_otg_os_dep.h"
52 #include "common_port/dwc_os.h"
53 #include "dwc_otg_dbg.h"
54 #include "dwc_otg_driver.h"
55 #include "dwc_otg_attr.h"
56 #include "dwc_otg_core_if.h"
57 #include "dwc_otg_pcd_if.h"
58 #include "dwc_otg_hcd_if.h"
59 #include "dwc_otg_cil.h"
60 #include "dwc_otg_pcd.h"
62 #include "usbdev_rk.h"
64 #define DWC_DRIVER_VERSION "3.10a 21-DEC-2012"
65 #define DWC_DRIVER_DESC "HS OTG USB Controller driver"
67 static const char dwc_host20_driver_name[] = "usb20_host";
68 static const char dwc_otg20_driver_name[] = "usb20_otg";
70 dwc_otg_device_t* g_otgdev = NULL;
72 extern int pcd_init( struct platform_device *_dev );
73 extern int otg20_hcd_init( struct platform_device *_dev );
74 extern int host20_hcd_init( struct platform_device *_dev );
75 extern int pcd_remove( struct platform_device *_dev );
76 extern void hcd_remove( struct platform_device *_dev);
77 extern void dwc_otg_adp_start( dwc_otg_core_if_t * core_if, uint8_t is_host);
79 static struct usb20otg_pdata_id usb20otg_pdata[] = {
81 .name = "rk3188-usb20otg",
82 .pdata = &usb20otg_pdata_rk3188,
85 .name = "rk3288-usb20otg",
86 .pdata = &usb20otg_pdata_rk3288,
91 static struct usb20host_pdata_id usb20host_pdata[] = {
93 .name = "rk3188-usb20host",
94 .pdata = &usb20host_pdata_rk3188,
97 .name = "rk3288-usb20host",
98 .pdata = &usb20host_pdata_rk3288,
103 /*-------------------------------------------------------------------------*/
104 /* Encapsulate the module parameter settings */
106 struct dwc_otg_driver_module_params {
110 int32_t dma_desc_enable;
111 int32_t dma_burst_size;
113 int32_t host_support_fs_ls_low_power;
114 int32_t host_ls_low_power_phy_clk;
115 int32_t enable_dynamic_fifo;
116 int32_t data_fifo_size;
117 int32_t dev_rx_fifo_size;
118 int32_t dev_nperio_tx_fifo_size;
119 uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS];
120 int32_t host_rx_fifo_size;
121 int32_t host_nperio_tx_fifo_size;
122 int32_t host_perio_tx_fifo_size;
123 int32_t max_transfer_size;
124 int32_t max_packet_count;
125 int32_t host_channels;
126 int32_t dev_endpoints;
128 int32_t phy_utmi_width;
129 int32_t phy_ulpi_ddr;
130 int32_t phy_ulpi_ext_vbus;
134 int32_t en_multiple_tx_fifo;
135 uint32_t dev_tx_fifo_size[MAX_TX_FIFOS];
137 uint32_t tx_thr_length;
138 uint32_t rx_thr_length;
143 int32_t baseline_besl;
146 int32_t ahb_thr_ratio;
156 static struct dwc_otg_driver_module_params dwc_otg_module_params = {
158 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
160 .dma_desc_enable = 0,
161 .dma_burst_size = -1,
163 .host_support_fs_ls_low_power = -1,
164 .host_ls_low_power_phy_clk = -1,
165 .enable_dynamic_fifo = 1,
166 .data_fifo_size = -1,
167 .dev_rx_fifo_size = 0x120,
168 .dev_nperio_tx_fifo_size = 0x10,
169 .dev_perio_tx_fifo_size = {
170 /* dev_perio_tx_fifo_size_1 */
188 .host_rx_fifo_size = -1,
189 .host_nperio_tx_fifo_size = -1,
190 .host_perio_tx_fifo_size = -1,
191 .max_transfer_size = -1,
192 .max_packet_count = -1,
196 .phy_utmi_width = -1,
198 .phy_ulpi_ext_vbus = -1,
202 .en_multiple_tx_fifo = -1,
203 .dev_tx_fifo_size = {
204 /* dev_tx_fifo_size */
243 static struct dwc_otg_driver_module_params dwc_host_module_params = {
245 .otg_cap = DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE,
247 .dma_desc_enable = 0,
248 .dma_burst_size = -1,
250 .host_support_fs_ls_low_power = -1,
251 .host_ls_low_power_phy_clk = -1,
252 .enable_dynamic_fifo = -1,
253 .data_fifo_size = -1,
254 .dev_rx_fifo_size = -1,
255 .dev_nperio_tx_fifo_size = -1,
256 .dev_perio_tx_fifo_size = {
257 /* dev_perio_tx_fifo_size_1 */
275 .host_rx_fifo_size = -1,
276 .host_nperio_tx_fifo_size = -1,
277 .host_perio_tx_fifo_size = -1,
278 .max_transfer_size = -1,
279 .max_packet_count = -1,
283 .phy_utmi_width = -1,
285 .phy_ulpi_ext_vbus = -1,
289 .en_multiple_tx_fifo = -1,
290 .dev_tx_fifo_size = {
291 /* dev_tx_fifo_size */
331 * This function shows the Driver Version.
333 static ssize_t version_show(struct device_driver *dev, char *buf)
335 return snprintf(buf, sizeof(DWC_DRIVER_VERSION) + 2, "%s\n",
339 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
342 * Global Debug Level Mask.
344 uint32_t g_dbg_lvl = DBG_OFF; /* OFF */
347 * This function shows the driver Debug Level.
349 static ssize_t dbg_level_show(struct device_driver *drv, char *buf)
351 return sprintf(buf, "0x%0x\n", g_dbg_lvl);
355 * This function stores the driver Debug Level.
357 static ssize_t dbg_level_store(struct device_driver *drv, const char *buf,
360 g_dbg_lvl = simple_strtoul(buf, NULL, 16);
364 static DRIVER_ATTR(debuglevel, S_IRUGO | S_IWUSR, dbg_level_show,
368 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
371 dwc_otg_device_t *otg_dev = g_otgdev;
372 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
373 return sprintf (_buf, "%d\n", _pcd->conn_en);
377 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
380 int enable = simple_strtoul(_buf, NULL, 10);
381 dwc_otg_device_t *otg_dev = g_otgdev;
382 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
383 DWC_PRINTF("%s %d->%d\n",__func__, _pcd->conn_en, enable);
385 _pcd->conn_en = enable;
388 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
390 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
392 dwc_otg_device_t *otg_dev = g_otgdev;
393 dwc_otg_pcd_t *_pcd = otg_dev->pcd;
394 return sprintf (_buf, "%d\n", _pcd->vbus_status);
396 static DRIVER_ATTR(vbus_status, S_IRUGO, vbus_status_show, NULL);
399 * This function is called during module intialization
400 * to pass module parameters to the DWC_OTG CORE.
402 static int set_parameters(dwc_otg_core_if_t * core_if, struct dwc_otg_driver_module_params module_params)
407 if (module_params.otg_cap != -1) {
409 dwc_otg_set_param_otg_cap(core_if,
410 module_params.otg_cap);
412 if (module_params.dma_enable != -1) {
414 dwc_otg_set_param_dma_enable(core_if,
418 if (module_params.dma_desc_enable != -1) {
420 dwc_otg_set_param_dma_desc_enable(core_if,
424 if (module_params.opt != -1) {
426 dwc_otg_set_param_opt(core_if, module_params.opt);
428 if (module_params.dma_burst_size != -1) {
430 dwc_otg_set_param_dma_burst_size(core_if,
434 if (module_params.host_support_fs_ls_low_power != -1) {
436 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
438 host_support_fs_ls_low_power);
440 if (module_params.enable_dynamic_fifo != -1) {
442 dwc_otg_set_param_enable_dynamic_fifo(core_if,
444 enable_dynamic_fifo);
446 if (module_params.data_fifo_size != -1) {
448 dwc_otg_set_param_data_fifo_size(core_if,
452 if (module_params.dev_rx_fifo_size != -1) {
454 dwc_otg_set_param_dev_rx_fifo_size(core_if,
458 if (module_params.dev_nperio_tx_fifo_size != -1) {
460 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
462 dev_nperio_tx_fifo_size);
464 if (module_params.host_rx_fifo_size != -1) {
466 dwc_otg_set_param_host_rx_fifo_size(core_if,
467 module_params.host_rx_fifo_size);
469 if (module_params.host_nperio_tx_fifo_size != -1) {
471 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
473 host_nperio_tx_fifo_size);
475 if (module_params.host_perio_tx_fifo_size != -1) {
477 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
479 host_perio_tx_fifo_size);
481 if (module_params.max_transfer_size != -1) {
483 dwc_otg_set_param_max_transfer_size(core_if,
487 if (module_params.max_packet_count != -1) {
489 dwc_otg_set_param_max_packet_count(core_if,
493 if (module_params.host_channels != -1) {
495 dwc_otg_set_param_host_channels(core_if,
499 if (module_params.dev_endpoints != -1) {
501 dwc_otg_set_param_dev_endpoints(core_if,
505 if (module_params.phy_type != -1) {
507 dwc_otg_set_param_phy_type(core_if,
508 module_params.phy_type);
510 if (module_params.speed != -1) {
512 dwc_otg_set_param_speed(core_if,
513 module_params.speed);
515 if (module_params.host_ls_low_power_phy_clk != -1) {
517 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
519 host_ls_low_power_phy_clk);
521 if (module_params.phy_ulpi_ddr != -1) {
523 dwc_otg_set_param_phy_ulpi_ddr(core_if,
527 if (module_params.phy_ulpi_ext_vbus != -1) {
529 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
533 if (module_params.phy_utmi_width != -1) {
535 dwc_otg_set_param_phy_utmi_width(core_if,
539 if (module_params.ulpi_fs_ls != -1) {
541 dwc_otg_set_param_ulpi_fs_ls(core_if,
542 module_params.ulpi_fs_ls);
544 if (module_params.ts_dline != -1) {
546 dwc_otg_set_param_ts_dline(core_if,
547 module_params.ts_dline);
549 if (module_params.i2c_enable != -1) {
551 dwc_otg_set_param_i2c_enable(core_if,
555 if (module_params.en_multiple_tx_fifo != -1) {
557 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
559 en_multiple_tx_fifo);
561 for (i = 0; i < 15; i++) {
562 if (module_params.dev_perio_tx_fifo_size[i] != -1) {
564 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
566 dev_perio_tx_fifo_size
571 for (i = 0; i < 15; i++) {
572 if (module_params.dev_tx_fifo_size[i] != -1) {
573 retval += dwc_otg_set_param_dev_tx_fifo_size(core_if,
579 if (module_params.thr_ctl != -1) {
581 dwc_otg_set_param_thr_ctl(core_if,
582 module_params.thr_ctl);
584 if (module_params.mpi_enable != -1) {
586 dwc_otg_set_param_mpi_enable(core_if,
590 if (module_params.pti_enable != -1) {
592 dwc_otg_set_param_pti_enable(core_if,
596 if (module_params.lpm_enable != -1) {
598 dwc_otg_set_param_lpm_enable(core_if,
602 if (module_params.besl_enable != -1) {
604 dwc_otg_set_param_besl_enable(core_if,
608 if (module_params.baseline_besl != -1) {
610 dwc_otg_set_param_baseline_besl(core_if,
614 if (module_params.deep_besl != -1) {
616 dwc_otg_set_param_deep_besl(core_if,
620 if (module_params.ic_usb_cap != -1) {
622 dwc_otg_set_param_ic_usb_cap(core_if,
626 if (module_params.tx_thr_length != -1) {
628 dwc_otg_set_param_tx_thr_length(core_if,
629 module_params.tx_thr_length);
631 if (module_params.rx_thr_length != -1) {
633 dwc_otg_set_param_rx_thr_length(core_if,
637 if (module_params.ahb_thr_ratio != -1) {
639 dwc_otg_set_param_ahb_thr_ratio(core_if,
640 module_params.ahb_thr_ratio);
642 if (module_params.power_down != -1) {
644 dwc_otg_set_param_power_down(core_if,
645 module_params.power_down);
647 if (module_params.reload_ctl != -1) {
649 dwc_otg_set_param_reload_ctl(core_if,
650 module_params.reload_ctl);
653 if (module_params.dev_out_nak != -1) {
655 dwc_otg_set_param_dev_out_nak(core_if,
656 module_params.dev_out_nak);
659 if (module_params.cont_on_bna != -1) {
661 dwc_otg_set_param_cont_on_bna(core_if,
662 module_params.cont_on_bna);
665 if (module_params.ahb_single != -1) {
667 dwc_otg_set_param_ahb_single(core_if,
668 module_params.ahb_single);
671 if (module_params.otg_ver != -1) {
673 dwc_otg_set_param_otg_ver(core_if,
674 module_params.otg_ver);
676 if (module_params.adp_enable != -1) {
678 dwc_otg_set_param_adp_enable(core_if,
686 * This function is the top level interrupt handler for the Common
687 * (Device and host modes) interrupts.
689 static irqreturn_t dwc_otg_common_irq(int irq, void *dev)
691 int32_t retval = IRQ_NONE;
693 retval = dwc_otg_handle_common_intr(dev);
695 //S3C2410X_CLEAR_EINTPEND();
697 return IRQ_RETVAL(retval);
701 * This function is called when a lm_device is unregistered with the
702 * dwc_otg_driver. This happens, for example, when the rmmod command is
703 * executed. The device may or may not be electrically present. If it is
704 * present, the driver stops device processing. Any resources used on behalf
705 * of this device are freed.
709 static int host20_driver_remove( struct platform_device *_dev )
712 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
713 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
716 /* Memory allocation for the dwc_otg_device failed. */
717 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
721 #ifndef DWC_DEVICE_ONLY
725 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
730 #ifndef DWC_HOST_ONLY
734 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
742 if (otg_dev->common_irq_installed) {
743 //free_irq(_dev->irq, otg_dev);
744 free_irq(platform_get_irq(_dev,0), otg_dev );
746 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
750 if (otg_dev->core_if) {
751 dwc_otg_cil_remove(otg_dev->core_if);
753 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
758 * Remove the device attributes
760 dwc_otg_attr_remove(_dev);
765 if (otg_dev->os_dep.base) {
766 iounmap(otg_dev->os_dep.base);
771 * Clear the drvdata pointer.
774 dwc_set_device_platform_data(_dev, 0);
779 static const struct of_device_id usb20_host_of_match[] = {
781 .compatible = "rockchip,rk3188_usb20_host",
782 .data = &usb20host_pdata[RK3188_USB_CTLR],
785 .compatible = "rockchip,rk3288_usb20_host",
786 .data = &usb20host_pdata[RK3288_USB_CTLR],
790 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
793 * This function is called when an lm_device is bound to a
794 * dwc_otg_driver. It creates the driver components required to
795 * control the device (CIL, HCD, and PCD) and it initializes the
796 * device. The driver components are stored in a dwc_otg_device
797 * structure. A reference to the dwc_otg_device is saved in the
798 * lm_device. This allows the driver to access the dwc_otg_device
799 * structure on subsequent calls to driver methods for this device.
801 * @param _dev Bus device
803 static int host20_driver_probe(struct platform_device *_dev)
807 struct resource *res_base;
808 dwc_otg_device_t *dwc_otg_device;
809 struct device *dev = &_dev->dev;
810 struct device_node *node = _dev->dev.of_node;
811 struct dwc_otg_platform_data *pldata;
812 struct usb20host_pdata_id *p;
813 const struct of_device_id *match =
814 of_match_device(of_match_ptr( usb20_host_of_match ), &_dev->dev);
817 p = (struct usb20host_pdata_id *)match->data;
819 dev_err(dev, "usb20host match failed\n");
823 dev->platform_data = p->pdata;
824 pldata = dev->platform_data;
828 dev_err(dev, "device node not found\n");
835 if(pldata->clock_init){
836 pldata->clock_init(pldata);
837 pldata->clock_enable(pldata, 1);
840 if(pldata->phy_suspend)
841 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
843 if(pldata->soft_reset)
844 pldata->soft_reset();
846 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
848 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
850 if (!dwc_otg_device) {
851 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
856 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
857 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
860 * Map the DWC_otg Core memory into virtual address space.
863 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
865 if (!dwc_otg_device->os_dep.base) {
866 dev_err(&_dev->dev, "ioremap() failed\n");
867 DWC_FREE(dwc_otg_device);
871 dev_dbg(&_dev->dev, "base=0x%08x\n",
872 (unsigned)dwc_otg_device->os_dep.base);
875 * Initialize driver data to point to the global DWC_otg
879 dwc_set_device_platform_data(_dev, dwc_otg_device);
880 pldata->privdata = dwc_otg_device;
881 dwc_otg_device->pldata = (void *)pldata;
883 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
885 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
888 if (!dwc_otg_device->core_if) {
889 dev_err(&_dev->dev, "CIL initialization failed!\n");
894 dwc_otg_device->core_if->otg_dev= dwc_otg_device;
897 * Attempt to ensure this device is really a DWC_otg Controller.
898 * Read and verify the SNPSID register contents. The value should be
899 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
900 * as in "OTG version 2.XX" or "OTG version 3.XX".
903 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
904 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
905 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
906 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
912 * Validate parameter values.
914 if (set_parameters(dwc_otg_device->core_if ,dwc_host_module_params )) {
920 * Create Device Attributes in sysfs
922 dwc_otg_attr_create(_dev);
925 * Disable the global interrupt until all the interrupt
926 * handlers are installed.
928 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
931 * Install the interrupt handler for the common interrupts before
932 * enabling common interrupts in core_init below.
934 irq = platform_get_irq(_dev,0);
935 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
937 retval = request_irq(irq, dwc_otg_common_irq,
938 IRQF_SHARED , "dwc_otg",
941 DWC_ERROR("request of irq%d failed\n", irq);
945 dwc_otg_device->common_irq_installed = 1;
949 * Initialize the DWC_otg core.
951 dwc_otg_core_init(dwc_otg_device->core_if);
956 retval = host20_hcd_init(_dev);
958 DWC_ERROR("hcd_init failed\n");
959 dwc_otg_device->hcd = NULL;
964 * Enable the global interrupt after all the interrupt
965 * handlers are installed if there is no ADP support else
966 * perform initial actions required for Internal ADP logic.
968 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))
969 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
971 dwc_otg_adp_start(dwc_otg_device->core_if,
972 dwc_otg_is_host_mode(dwc_otg_device->core_if));
977 host20_driver_remove(_dev);
979 if(pldata->clock_enable)
980 pldata->clock_enable(pldata, 0);
985 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
990 static int dwc_otg_driver_resume(struct platform_device *_dev )
995 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
997 struct device *dev = &_dev->dev;
998 dwc_otg_device_t *otg_dev = dev->platform_data;
999 dwc_otg_core_if_t *core_if = otg_dev->core_if;
1000 dctl_data_t dctl = {.d32=0};
1002 DWC_PRINTF("%s: disconnect USB %s mode\n" , __func__ ,
1003 dwc_otg_is_host_mode(core_if) ? "host" : "device");
1004 if(dwc_otg_is_host_mode(core_if))
1006 if (core_if->hcd_cb && core_if->hcd_cb->stop)
1008 core_if->hcd_cb->stop( core_if->hcd_cb_p);
1013 /* soft disconnect */
1014 dctl.d32 = DWC_READ_REG32( &core_if->dev_if->dev_global_regs->dctl );
1015 dctl.b.sftdiscon = 1;
1016 DWC_WRITE_REG32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1018 /* Clear any pending interrupts */
1019 DWC_WRITE_REG32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1025 * This structure defines the methods to be called by a bus driver
1026 * during the lifecycle of a device on that bus. Both drivers and
1027 * devices are registered with a bus driver. The bus driver matches
1028 * devices to drivers based on information in the device and driver
1031 * The probe function is called when the bus driver matches a device
1032 * to this driver. The remove function is called when a device is
1033 * unregistered with the bus driver.
1036 static struct platform_driver dwc_host_driver = {
1038 .name = (char *)dwc_host20_driver_name,
1039 .of_match_table = of_match_ptr(usb20_host_of_match),
1041 .probe = host20_driver_probe,
1042 .remove = host20_driver_remove,
1043 .suspend = dwc_otg_driver_suspend,
1044 .resume = dwc_otg_driver_resume,
1049 * This function is called when a lm_device is unregistered with the
1050 * dwc_otg_driver. This happens, for example, when the rmmod command is
1051 * executed. The device may or may not be electrically present. If it is
1052 * present, the driver stops device processing. Any resources used on behalf
1053 * of this device are freed.
1057 static int otg20_driver_remove( struct platform_device *_dev )
1060 dwc_otg_device_t *otg_dev = dwc_get_device_platform_data(_dev);
1061 DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev);
1064 /* Memory allocation for the dwc_otg_device failed. */
1065 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev NULL!\n", __func__);
1068 #ifndef DWC_DEVICE_ONLY
1072 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->hcd NULL!\n", __func__);
1077 #ifndef DWC_HOST_ONLY
1081 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->pcd NULL!\n", __func__);
1088 if (otg_dev->common_irq_installed) {
1089 //free_irq(_dev->irq, otg_dev);
1090 free_irq(platform_get_irq(_dev,0), otg_dev );
1092 DWC_DEBUGPL(DBG_ANY, "%s: There is no installed irq!\n", __func__);
1096 if (otg_dev->core_if) {
1097 dwc_otg_cil_remove(otg_dev->core_if);
1099 DWC_DEBUGPL(DBG_ANY, "%s: otg_dev->core_if NULL!\n", __func__);
1104 * Remove the device attributes
1106 dwc_otg_attr_remove(_dev);
1109 * Return the memory.
1111 if (otg_dev->os_dep.base) {
1112 iounmap(otg_dev->os_dep.base);
1117 * Clear the drvdata pointer.
1120 dwc_set_device_platform_data(_dev, 0);
1125 static const struct of_device_id usb20_otg_of_match[] = {
1127 .compatible = "rockchip,rk3188_usb20_otg",
1128 .data = &usb20otg_pdata[RK3188_USB_CTLR],
1131 .compatible = "rockchip,rk3288_usb20_otg",
1132 .data = &usb20otg_pdata[RK3288_USB_CTLR],
1137 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1140 * This function is called when an lm_device is bound to a
1141 * dwc_otg_driver. It creates the driver components required to
1142 * control the device (CIL, HCD, and PCD) and it initializes the
1143 * device. The driver components are stored in a dwc_otg_device
1144 * structure. A reference to the dwc_otg_device is saved in the
1145 * lm_device. This allows the driver to access the dwc_otg_device
1146 * structure on subsequent calls to driver methods for this device.
1148 * @param _dev Bus device
1150 static int otg20_driver_probe(struct platform_device *_dev)
1154 struct resource *res_base;
1155 dwc_otg_device_t *dwc_otg_device;
1156 struct device *dev = &_dev->dev;
1157 struct device_node *node = _dev->dev.of_node;
1158 struct dwc_otg_platform_data *pldata;
1159 struct usb20otg_pdata_id *p;
1160 const struct of_device_id *match =
1161 of_match_device(of_match_ptr( usb20_otg_of_match ), &_dev->dev);
1164 p = (struct usb20otg_pdata_id *)match->data;
1166 dev_err(dev, "usb20otg match failed\n");
1170 dev->platform_data = p->pdata;
1171 // dev->platform_data = &usb20otg_pdata;
1172 pldata = dev->platform_data;
1176 dev_err(dev, "device node not found\n");
1179 /*todo : move to usbdev_rk-XX.c*/
1183 if(pldata->clock_init){
1184 pldata->clock_init(pldata);
1185 pldata->clock_enable(pldata, 1);
1188 if(pldata->phy_suspend)
1189 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1190 if(pldata->dwc_otg_uart_mode)
1191 pldata->dwc_otg_uart_mode(pldata, PHY_USB_MODE);
1192 if(pldata->soft_reset)
1193 pldata->soft_reset();
1196 res_base=platform_get_resource(_dev, IORESOURCE_MEM, 0);
1198 dwc_otg_device = DWC_ALLOC(sizeof(dwc_otg_device_t));
1200 if (!dwc_otg_device) {
1201 dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n");
1206 memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1207 dwc_otg_device->os_dep.reg_offset = 0xFFFFFFFF;
1210 * Map the DWC_otg Core memory into virtual address space.
1213 dwc_otg_device->os_dep.base = devm_ioremap_resource(dev, res_base);
1215 if (!dwc_otg_device->os_dep.base) {
1216 dev_err(&_dev->dev, "ioremap() failed\n");
1217 DWC_FREE(dwc_otg_device);
1221 dev_dbg(&_dev->dev, "base=0x%08x\n",
1222 (unsigned)dwc_otg_device->os_dep.base);
1225 * Initialize driver data to point to the global DWC_otg
1229 g_otgdev = dwc_otg_device;
1230 pldata->privdata = dwc_otg_device;
1231 dwc_otg_device->pldata = pldata;
1233 dwc_set_device_platform_data(_dev, dwc_otg_device);
1235 dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1237 dwc_otg_device->core_if = dwc_otg_cil_init(dwc_otg_device->os_dep.base);
1238 if (!dwc_otg_device->core_if) {
1239 dev_err(&_dev->dev, "CIL initialization failed!\n");
1244 dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1246 * Attempt to ensure this device is really a DWC_otg Controller.
1247 * Read and verify the SNPSID register contents. The value should be
1248 * 0x45F42XXX or 0x45F42XXX, which corresponds to either "OT2" or "OTG3",
1249 * as in "OTG version 2.XX" or "OTG version 3.XX".
1252 if (((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F542000) &&
1253 ((dwc_otg_get_gsnpsid(dwc_otg_device->core_if) & 0xFFFFF000) != 0x4F543000)) {
1254 dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n",
1255 dwc_otg_get_gsnpsid(dwc_otg_device->core_if));
1261 * Validate parameter values.
1263 if (set_parameters(dwc_otg_device->core_if ,dwc_otg_module_params)) {
1269 * Create Device Attributes in sysfs
1271 dwc_otg_attr_create(_dev);
1274 * Disable the global interrupt until all the interrupt
1275 * handlers are installed.
1277 dwc_otg_disable_global_interrupts(dwc_otg_device->core_if);
1280 * Install the interrupt handler for the common interrupts before
1281 * enabling common interrupts in core_init below.
1283 irq = platform_get_irq(_dev,0);
1284 DWC_DEBUGPL(DBG_CIL, "registering (common) handler for irq%d\n",
1286 retval = request_irq(irq, dwc_otg_common_irq,
1287 IRQF_SHARED , "dwc_otg",
1290 DWC_ERROR("request of irq%d failed\n", irq);
1294 dwc_otg_device->common_irq_installed = 1;
1298 * Initialize the DWC_otg core.
1300 dwc_otg_core_init(dwc_otg_device->core_if);
1302 #ifndef DWC_HOST_ONLY
1304 * Initialize the PCD
1306 retval = pcd_init(_dev);
1308 DWC_ERROR("pcd_init failed\n");
1309 dwc_otg_device->pcd = NULL;
1313 #ifndef DWC_DEVICE_ONLY
1315 * Initialize the HCD
1317 retval = otg20_hcd_init(_dev);
1319 DWC_ERROR("hcd_init failed\n");
1320 dwc_otg_device->hcd = NULL;
1325 * Enable the global interrupt after all the interrupt
1326 * handlers are installed if there is no ADP support else
1327 * perform initial actions required for Internal ADP logic.
1329 if (!dwc_otg_get_param_adp_enable(dwc_otg_device->core_if))
1330 dwc_otg_enable_global_interrupts(dwc_otg_device->core_if);
1332 dwc_otg_adp_start(dwc_otg_device->core_if,
1333 dwc_otg_is_host_mode(dwc_otg_device->core_if));
1338 otg20_driver_remove(_dev);
1341 if(pldata->clock_enable)
1342 pldata->clock_enable(pldata, 0);
1347 static struct platform_driver dwc_otg_driver = {
1349 .name = (char *)dwc_otg20_driver_name,
1350 .of_match_table = of_match_ptr(usb20_otg_of_match),
1352 .probe = otg20_driver_probe,
1353 .remove = otg20_driver_remove,
1354 .suspend = dwc_otg_driver_suspend,
1355 .resume = dwc_otg_driver_resume,
1356 .shutdown = dwc_otg_driver_shutdown,
1361 * This function is called when the dwc_otg_driver is installed with the
1362 * insmod command. It registers the dwc_otg_driver structure with the
1363 * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1364 * to be called. In addition, the bus driver will automatically expose
1365 * attributes defined for the device and driver in the special sysfs file
1370 static int __init dwc_otg_driver_init(void)
1375 printk(KERN_INFO "%s: version %s\n", dwc_host20_driver_name,
1376 DWC_DRIVER_VERSION);
1378 retval = platform_driver_register(&dwc_host_driver);
1380 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1384 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_version);
1385 error = driver_create_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1388 printk(KERN_INFO "%s: version %s\n", dwc_otg20_driver_name,
1389 DWC_DRIVER_VERSION);
1391 retval = platform_driver_register(&dwc_otg_driver);
1393 printk(KERN_ERR "%s retval=%d\n", __func__, retval);
1397 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version);
1398 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1399 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1400 error = driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1405 module_init(dwc_otg_driver_init);
1408 * This function is called when the driver is removed from the kernel
1409 * with the rmmod command. The driver unregisters itself with its bus
1413 static void __exit dwc_otg_driver_cleanup(void)
1415 printk(KERN_DEBUG "dwc_otg_driver_cleanup()\n");
1418 driver_remove_file(&dwc_host_driver.driver, &driver_attr_debuglevel);
1419 driver_remove_file(&dwc_host_driver.driver, &driver_attr_version);
1420 platform_driver_unregister(&dwc_host_driver);
1421 printk(KERN_INFO "%s module removed\n", dwc_host20_driver_name);
1424 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1425 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1426 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1427 driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1428 platform_driver_unregister(&dwc_otg_driver);
1429 printk(KERN_INFO "%s module removed\n", dwc_otg20_driver_name);
1432 module_exit(dwc_otg_driver_cleanup);
1434 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1435 MODULE_AUTHOR("Synopsys Inc.");
1436 MODULE_LICENSE("GPL");
1438 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1439 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1440 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1441 MODULE_PARM_DESC(opt, "OPT Mode");
1442 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1443 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1445 module_param_named(dma_desc_enable, dwc_otg_module_params.dma_desc_enable, int,
1447 MODULE_PARM_DESC(dma_desc_enable,
1448 "DMA Desc Mode 0=Address DMA 1=DMA Descriptor enabled");
1450 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int,
1452 MODULE_PARM_DESC(dma_burst_size,
1453 "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1454 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1455 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1456 module_param_named(host_support_fs_ls_low_power,
1457 dwc_otg_module_params.host_support_fs_ls_low_power, int,
1459 MODULE_PARM_DESC(host_support_fs_ls_low_power,
1460 "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1461 module_param_named(host_ls_low_power_phy_clk,
1462 dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1463 MODULE_PARM_DESC(host_ls_low_power_phy_clk,
1464 "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1465 module_param_named(enable_dynamic_fifo,
1466 dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1467 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1468 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int,
1470 MODULE_PARM_DESC(data_fifo_size,
1471 "Total number of words in the data FIFO memory 32-32768");
1472 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size,
1474 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1475 module_param_named(dev_nperio_tx_fifo_size,
1476 dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1477 MODULE_PARM_DESC(dev_nperio_tx_fifo_size,
1478 "Number of words in the non-periodic Tx FIFO 16-32768");
1479 module_param_named(dev_perio_tx_fifo_size_1,
1480 dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1481 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1,
1482 "Number of words in the periodic Tx FIFO 4-768");
1483 module_param_named(dev_perio_tx_fifo_size_2,
1484 dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1485 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2,
1486 "Number of words in the periodic Tx FIFO 4-768");
1487 module_param_named(dev_perio_tx_fifo_size_3,
1488 dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1489 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3,
1490 "Number of words in the periodic Tx FIFO 4-768");
1491 module_param_named(dev_perio_tx_fifo_size_4,
1492 dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1493 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4,
1494 "Number of words in the periodic Tx FIFO 4-768");
1495 module_param_named(dev_perio_tx_fifo_size_5,
1496 dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1497 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5,
1498 "Number of words in the periodic Tx FIFO 4-768");
1499 module_param_named(dev_perio_tx_fifo_size_6,
1500 dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1501 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6,
1502 "Number of words in the periodic Tx FIFO 4-768");
1503 module_param_named(dev_perio_tx_fifo_size_7,
1504 dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1505 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7,
1506 "Number of words in the periodic Tx FIFO 4-768");
1507 module_param_named(dev_perio_tx_fifo_size_8,
1508 dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1509 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8,
1510 "Number of words in the periodic Tx FIFO 4-768");
1511 module_param_named(dev_perio_tx_fifo_size_9,
1512 dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1513 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9,
1514 "Number of words in the periodic Tx FIFO 4-768");
1515 module_param_named(dev_perio_tx_fifo_size_10,
1516 dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1517 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10,
1518 "Number of words in the periodic Tx FIFO 4-768");
1519 module_param_named(dev_perio_tx_fifo_size_11,
1520 dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1521 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11,
1522 "Number of words in the periodic Tx FIFO 4-768");
1523 module_param_named(dev_perio_tx_fifo_size_12,
1524 dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1525 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12,
1526 "Number of words in the periodic Tx FIFO 4-768");
1527 module_param_named(dev_perio_tx_fifo_size_13,
1528 dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1529 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13,
1530 "Number of words in the periodic Tx FIFO 4-768");
1531 module_param_named(dev_perio_tx_fifo_size_14,
1532 dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1533 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14,
1534 "Number of words in the periodic Tx FIFO 4-768");
1535 module_param_named(dev_perio_tx_fifo_size_15,
1536 dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1537 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15,
1538 "Number of words in the periodic Tx FIFO 4-768");
1539 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size,
1541 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1542 module_param_named(host_nperio_tx_fifo_size,
1543 dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1544 MODULE_PARM_DESC(host_nperio_tx_fifo_size,
1545 "Number of words in the non-periodic Tx FIFO 16-32768");
1546 module_param_named(host_perio_tx_fifo_size,
1547 dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1548 MODULE_PARM_DESC(host_perio_tx_fifo_size,
1549 "Number of words in the host periodic Tx FIFO 16-32768");
1550 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size,
1552 /** @todo Set the max to 512K, modify checks */
1553 MODULE_PARM_DESC(max_transfer_size,
1554 "The maximum transfer size supported in bytes 2047-65535");
1555 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count,
1557 MODULE_PARM_DESC(max_packet_count,
1558 "The maximum number of packets in a transfer 15-511");
1559 module_param_named(host_channels, dwc_otg_module_params.host_channels, int,
1561 MODULE_PARM_DESC(host_channels,
1562 "The number of host channel registers to use 1-16");
1563 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int,
1565 MODULE_PARM_DESC(dev_endpoints,
1566 "The number of endpoints in addition to EP0 available for device mode 1-15");
1567 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1568 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1569 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int,
1571 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1572 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1573 MODULE_PARM_DESC(phy_ulpi_ddr,
1574 "ULPI at double or single data rate 0=Single 1=Double");
1575 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus,
1577 MODULE_PARM_DESC(phy_ulpi_ext_vbus,
1578 "ULPI PHY using internal or external vbus 0=Internal");
1579 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1580 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1581 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1582 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1583 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1584 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1585 module_param_named(debug, g_dbg_lvl, int, 0444);
1586 MODULE_PARM_DESC(debug, "");
1588 module_param_named(en_multiple_tx_fifo,
1589 dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1590 MODULE_PARM_DESC(en_multiple_tx_fifo,
1591 "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1592 module_param_named(dev_tx_fifo_size_1,
1593 dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
1594 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
1595 module_param_named(dev_tx_fifo_size_2,
1596 dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
1597 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
1598 module_param_named(dev_tx_fifo_size_3,
1599 dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
1600 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
1601 module_param_named(dev_tx_fifo_size_4,
1602 dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
1603 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
1604 module_param_named(dev_tx_fifo_size_5,
1605 dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
1606 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
1607 module_param_named(dev_tx_fifo_size_6,
1608 dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
1609 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
1610 module_param_named(dev_tx_fifo_size_7,
1611 dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
1612 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
1613 module_param_named(dev_tx_fifo_size_8,
1614 dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
1615 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
1616 module_param_named(dev_tx_fifo_size_9,
1617 dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
1618 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
1619 module_param_named(dev_tx_fifo_size_10,
1620 dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
1621 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
1622 module_param_named(dev_tx_fifo_size_11,
1623 dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
1624 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
1625 module_param_named(dev_tx_fifo_size_12,
1626 dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
1627 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
1628 module_param_named(dev_tx_fifo_size_13,
1629 dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
1630 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
1631 module_param_named(dev_tx_fifo_size_14,
1632 dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
1633 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
1634 module_param_named(dev_tx_fifo_size_15,
1635 dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
1636 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
1638 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
1639 MODULE_PARM_DESC(thr_ctl,
1640 "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
1641 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int,
1643 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
1644 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int,
1646 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
1648 module_param_named(pti_enable, dwc_otg_module_params.pti_enable, int, 0444);
1649 module_param_named(mpi_enable, dwc_otg_module_params.mpi_enable, int, 0444);
1650 module_param_named(lpm_enable, dwc_otg_module_params.lpm_enable, int, 0444);
1651 MODULE_PARM_DESC(lpm_enable, "LPM Enable 0=LPM Disabled 1=LPM Enabled");
1653 module_param_named(besl_enable, dwc_otg_module_params.besl_enable, int, 0444);
1654 MODULE_PARM_DESC(besl_enable, "BESL Enable 0=BESL Disabled 1=BESL Enabled");
1655 module_param_named(baseline_besl, dwc_otg_module_params.baseline_besl, int, 0444);
1656 MODULE_PARM_DESC(baseline_besl, "Set the baseline besl value");
1657 module_param_named(deep_besl, dwc_otg_module_params.deep_besl, int, 0444);
1658 MODULE_PARM_DESC(deep_besl, "Set the deep besl value");
1660 module_param_named(ic_usb_cap, dwc_otg_module_params.ic_usb_cap, int, 0444);
1661 MODULE_PARM_DESC(ic_usb_cap,
1662 "IC_USB Capability 0=IC_USB Disabled 1=IC_USB Enabled");
1663 module_param_named(ahb_thr_ratio, dwc_otg_module_params.ahb_thr_ratio, int,
1665 MODULE_PARM_DESC(ahb_thr_ratio, "AHB Threshold Ratio");
1666 module_param_named(power_down, dwc_otg_module_params.power_down, int, 0444);
1667 MODULE_PARM_DESC(power_down, "Power Down Mode");
1668 module_param_named(reload_ctl, dwc_otg_module_params.reload_ctl, int, 0444);
1669 MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control");
1670 module_param_named(dev_out_nak, dwc_otg_module_params.dev_out_nak, int, 0444);
1671 MODULE_PARM_DESC(dev_out_nak, "Enable Device OUT NAK");
1672 module_param_named(cont_on_bna, dwc_otg_module_params.cont_on_bna, int, 0444);
1673 MODULE_PARM_DESC(cont_on_bna, "Enable Enable Continue on BNA");
1674 module_param_named(ahb_single, dwc_otg_module_params.ahb_single, int, 0444);
1675 MODULE_PARM_DESC(ahb_single, "Enable AHB Single Support");
1676 module_param_named(adp_enable, dwc_otg_module_params.adp_enable, int, 0444);
1677 MODULE_PARM_DESC(adp_enable, "ADP Enable 0=ADP Disabled 1=ADP Enabled");
1678 module_param_named(otg_ver, dwc_otg_module_params.otg_ver, int, 0444);
1679 MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=OTG 1.3 1=OTG 2.0");
1681 /** @page "Module Parameters"
1683 * The following parameters may be specified when starting the module.
1684 * These parameters define how the DWC_otg controller should be
1685 * configured. Parameter values are passed to the CIL initialization
1686 * function dwc_otg_cil_init
1688 * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
1692 <tr><td>Parameter Name</td><td>Meaning</td></tr>
1696 <td>Specifies the OTG capabilities. The driver will automatically detect the
1697 value for this parameter if none is specified.
1698 - 0: HNP and SRP capable (default, if available)
1699 - 1: SRP Only capable
1700 - 2: No HNP/SRP capable
1705 <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
1706 The driver will automatically detect the value for this parameter if none is
1709 - 1: DMA (default, if available)
1713 <td>dma_burst_size</td>
1714 <td>The DMA Burst size (applicable only for External DMA Mode).
1715 - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
1720 <td>Specifies the maximum speed of operation in host and device mode. The
1721 actual speed depends on the speed of the attached device and the value of
1723 - 0: High Speed (default)
1728 <td>host_support_fs_ls_low_power</td>
1729 <td>Specifies whether low power mode is supported when attached to a Full
1730 Speed or Low Speed device in host mode.
1731 - 0: Don't support low power mode (default)
1732 - 1: Support low power mode
1736 <td>host_ls_low_power_phy_clk</td>
1737 <td>Specifies the PHY clock rate in low power mode when connected to a Low
1738 Speed device in host mode. This parameter is applicable only if
1739 HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
1740 - 0: 48 MHz (default)
1745 <td>enable_dynamic_fifo</td>
1746 <td> Specifies whether FIFOs may be resized by the driver software.
1747 - 0: Use cC FIFO size parameters
1748 - 1: Allow dynamic FIFO sizing (default)
1752 <td>data_fifo_size</td>
1753 <td>Total number of 4-byte words in the data FIFO memory. This memory
1754 includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
1755 - Values: 32 to 32768 (default 8192)
1757 Note: The total FIFO memory depth in the FPGA configuration is 8192.
1761 <td>dev_rx_fifo_size</td>
1762 <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
1763 FIFO sizing is enabled.
1764 - Values: 16 to 32768 (default 1064)
1768 <td>dev_nperio_tx_fifo_size</td>
1769 <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
1770 dynamic FIFO sizing is enabled.
1771 - Values: 16 to 32768 (default 1024)
1775 <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
1776 <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
1777 when dynamic FIFO sizing is enabled.
1778 - Values: 4 to 768 (default 256)
1782 <td>host_rx_fifo_size</td>
1783 <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
1785 - Values: 16 to 32768 (default 1024)
1789 <td>host_nperio_tx_fifo_size</td>
1790 <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
1791 dynamic FIFO sizing is enabled in the core.
1792 - Values: 16 to 32768 (default 1024)
1796 <td>host_perio_tx_fifo_size</td>
1797 <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
1799 - Values: 16 to 32768 (default 1024)
1803 <td>max_transfer_size</td>
1804 <td>The maximum transfer size supported in bytes.
1805 - Values: 2047 to 65,535 (default 65,535)
1809 <td>max_packet_count</td>
1810 <td>The maximum number of packets in a transfer.
1811 - Values: 15 to 511 (default 511)
1815 <td>host_channels</td>
1816 <td>The number of host channel registers to use.
1817 - Values: 1 to 16 (default 12)
1819 Note: The FPGA configuration supports a maximum of 12 host channels.
1823 <td>dev_endpoints</td>
1824 <td>The number of endpoints in addition to EP0 available for device mode
1826 - Values: 1 to 15 (default 6 IN and OUT)
1828 Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
1834 <td>Specifies the type of PHY interface to use. By default, the driver will
1835 automatically detect the phy_type.
1837 - 1: UTMI+ (default, if available)
1842 <td>phy_utmi_width</td>
1843 <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
1844 phy_type of UTMI+. Also, this parameter is applicable only if the
1845 OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
1846 core has been configured to work at either data path width.
1847 - Values: 8 or 16 bits (default 16)
1851 <td>phy_ulpi_ddr</td>
1852 <td>Specifies whether the ULPI operates at double or single data rate. This
1853 parameter is only applicable if phy_type is ULPI.
1854 - 0: single data rate ULPI interface with 8 bit wide data bus (default)
1855 - 1: double data rate ULPI interface with 4 bit wide data bus
1860 <td>Specifies whether to use the I2C interface for full speed PHY. This
1861 parameter is only applicable if PHY_TYPE is FS.
1862 - 0: Disabled (default)
1868 <td>Specifies whether to use ULPI FS/LS mode only.
1869 - 0: Disabled (default)
1875 <td>Specifies whether term select D-Line pulsing for all PHYs is enabled.
1876 - 0: Disabled (default)
1881 <td>en_multiple_tx_fifo</td>
1882 <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
1883 The driver will automatically detect the value for this parameter if none is
1886 - 1: Enabled (default, if available)
1890 <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
1891 <td>Number of 4-byte words in each of the Tx FIFOs in device mode
1892 when dynamic FIFO sizing is enabled.
1893 - Values: 4 to 768 (default 256)
1897 <td>tx_thr_length</td>
1898 <td>Transmit Threshold length in 32 bit double words
1899 - Values: 8 to 128 (default 64)
1903 <td>rx_thr_length</td>
1904 <td>Receive Threshold length in 32 bit double words
1905 - Values: 8 to 128 (default 64)
1910 <td>Specifies whether to enable Thresholding for Device mode. Bits 0, 1, 2 of
1911 this parmater specifies if thresholding is enabled for non-Iso Tx, Iso Tx and
1912 Rx transfers accordingly.
1913 The driver will automatically detect the value for this parameter if none is
1915 - Values: 0 to 7 (default 0)
1916 Bit values indicate:
1917 - 0: Thresholding disabled
1918 - 1: Thresholding enabled
1922 <td>dma_desc_enable</td>
1923 <td>Specifies whether to enable Descriptor DMA mode.
1924 The driver will automatically detect the value for this parameter if none is
1926 - 0: Descriptor DMA disabled
1927 - 1: Descriptor DMA (default, if available)
1932 <td>Specifies whether to enable MPI enhancement mode.
1933 The driver will automatically detect the value for this parameter if none is
1935 - 0: MPI disabled (default)
1941 <td>Specifies whether to enable PTI enhancement support.
1942 The driver will automatically detect the value for this parameter if none is
1944 - 0: PTI disabled (default)
1950 <td>Specifies whether to enable LPM support.
1951 The driver will automatically detect the value for this parameter if none is
1954 - 1: LPM enable (default, if available)
1958 <td>besl_enable</td>
1959 <td>Specifies whether to enable LPM Errata support.
1960 The driver will automatically detect the value for this parameter if none is
1962 - 0: LPM Errata disabled (default)
1963 - 1: LPM Errata enable
1967 <td>baseline_besl</td>
1968 <td>Specifies the baseline besl value.
1969 - Values: 0 to 15 (default 0)
1974 <td>Specifies the deep besl value.
1975 - Values: 0 to 15 (default 15)
1980 <td>Specifies whether to enable IC_USB capability.
1981 The driver will automatically detect the value for this parameter if none is
1983 - 0: IC_USB disabled (default, if available)
1988 <td>ahb_thr_ratio</td>
1989 <td>Specifies AHB Threshold ratio.
1990 - Values: 0 to 3 (default 0)
1995 <td>Specifies Power Down(Hibernation) Mode.
1996 The driver will automatically detect the value for this parameter if none is
1998 - 0: Power Down disabled (default)
1999 - 2: Power Down enabled
2004 <td>Specifies whether dynamic reloading of the HFIR register is allowed during
2005 run time. The driver will automatically detect the value for this parameter if
2006 none is specified. In case the HFIR value is reloaded when HFIR.RldCtrl == 1'b0
2007 the core might misbehave.
2008 - 0: Reload Control disabled (default)
2009 - 1: Reload Control enabled
2013 <td>dev_out_nak</td>
2014 <td>Specifies whether Device OUT NAK enhancement enabled or no.
2015 The driver will automatically detect the value for this parameter if
2016 none is specified. This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2017 - 0: The core does not set NAK after Bulk OUT transfer complete (default)
2018 - 1: The core sets NAK after Bulk OUT transfer complete
2022 <td>cont_on_bna</td>
2023 <td>Specifies whether Enable Continue on BNA enabled or no.
2024 After receiving BNA interrupt the core disables the endpoint,when the
2025 endpoint is re-enabled by the application the
2026 - 0: Core starts processing from the DOEPDMA descriptor (default)
2027 - 1: Core starts processing from the descriptor which received the BNA.
2028 This parameter is valid only when OTG_EN_DESC_DMA == 1
\92b1.
2033 <td>This bit when programmed supports SINGLE transfers for remainder data
2034 in a transfer for DMA mode of operation.
2035 - 0: The remainder data will be sent using INCR burst size (default)
2036 - 1: The remainder data will be sent using SINGLE burst size.
2041 <td>Specifies whether ADP feature is enabled.
2042 The driver will automatically detect the value for this parameter if none is
2044 - 0: ADP feature disabled (default)
2045 - 1: ADP feature enabled
2050 <td>Specifies whether OTG is performing as USB OTG Revision 2.0 or Revision 1.3
2052 - 0: OTG 2.0 support disabled (default)
2053 - 1: OTG 2.0 support enabled