1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
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19 * below, then you are not authorized to use the Software.
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22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
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26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
36 * The Core Interface Layer provides basic services for accessing and
37 * managing the DWC_otg hardware. These services are used by both the
38 * Host Controller Driver and the Peripheral Controller Driver.
40 * The CIL manages the memory map for the core so that the HCD and PCD
41 * don't have to do this separately. It also handles basic tasks like
42 * reading/writing the registers and data FIFOs in the controller.
43 * Some of the data access functions provide encapsulation of several
44 * operations required to perform a task, such as writing multiple
45 * registers to start a transfer. Finally, the CIL performs basic
46 * services that are not specific to either the host or device modes
47 * of operation. These services include management of the OTG Host
48 * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
49 * Diagnostic API is also provided to allow testing of the controller
52 * The Core Interface Layer has the following requirements:
53 * - Provides basic controller operations.
54 * - Minimal use of OS services.
55 * - The OS services used will be abstracted by using inline functions
60 #include "common_port/dwc_os.h"
61 #include "dwc_otg_regs.h"
62 #include "dwc_otg_cil.h"
63 #include "dwc_otg_driver.h"
64 #include "usbdev_rk.h"
65 #include "dwc_otg_hcd.h"
67 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
70 * This function is called to initialize the DWC_otg CSR data
71 * structures. The register addresses in the device and host
72 * structures are initialized from the base address supplied by the
73 * caller. The calling function must make the OS calls to get the
74 * base address of the DWC_otg controller registers. The core_params
75 * argument holds the parameters that specify how the core should be
78 * @param reg_base_addr Base address of DWC_otg core registers
81 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
83 dwc_otg_core_if_t *core_if = 0;
84 dwc_otg_dev_if_t *dev_if = 0;
85 dwc_otg_host_if_t *host_if = 0;
86 uint8_t *reg_base = (uint8_t *) reg_base_addr;
89 DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
91 core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
93 if (core_if == NULL) {
95 "Allocation of dwc_otg_core_if_t failed\n");
98 core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
101 * Allocate the Device Mode structures.
103 dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
105 if (dev_if == NULL) {
106 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
111 dev_if->dev_global_regs =
112 (dwc_otg_device_global_regs_t *) (reg_base +
113 DWC_DEV_GLOBAL_REG_OFFSET);
115 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
116 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
117 (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
118 (i * DWC_EP_REG_OFFSET));
120 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
121 (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
122 (i * DWC_EP_REG_OFFSET));
123 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
124 i, &dev_if->in_ep_regs[i]->diepctl);
125 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
126 i, &dev_if->out_ep_regs[i]->doepctl);
129 dev_if->speed = 0; // unknown
131 core_if->dev_if = dev_if;
134 * Allocate the Host Mode structures.
136 host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
138 if (host_if == NULL) {
140 "Allocation of dwc_otg_host_if_t failed\n");
146 host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
147 (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
150 (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
152 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
153 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
154 (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
155 (i * DWC_OTG_CHAN_REGS_OFFSET));
156 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
157 i, &host_if->hc_regs[i]->hcchar);
160 host_if->num_host_channels = MAX_EPS_CHANNELS;
161 core_if->host_if = host_if;
163 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
164 core_if->data_fifo[i] =
165 (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
166 (i * DWC_OTG_DATA_FIFO_SIZE));
167 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
168 i, (unsigned long)core_if->data_fifo[i]);
171 core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
173 /* Initiate lx_state to L3 disconnected state */
174 core_if->lx_state = DWC_OTG_L3;
176 * Store the contents of the hardware configuration registers here for
179 core_if->hwcfg1.d32 =
180 DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
181 core_if->hwcfg2.d32 =
182 DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
183 core_if->hwcfg3.d32 =
184 DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
185 core_if->hwcfg4.d32 =
186 DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
188 /* do not get HPTXFSIZ here, it's unused.
189 * set global_regs->hptxfsiz in dwc_otg_core_host_init.
190 * for 3.10a version, host20 FIFO can't be configed,
191 * because host20 hwcfg2.b.dynamic_fifo = 0.
194 /* Force host mode to get HPTXFSIZ exact power on value */
196 gusbcfg_data_t gusbcfg = {.d32 = 0 };
197 gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
198 gusbcfg.b.force_host_mode = 1;
199 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
201 core_if->hptxfsiz.d32 =
202 DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
203 gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
204 gusbcfg.b.force_host_mode = 0;
205 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
210 DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
211 DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
212 DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
213 DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
216 DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
218 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
220 DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
221 DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
223 DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
224 DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
225 DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
226 DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
227 core_if->hwcfg2.b.num_host_chan);
228 DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
229 core_if->hwcfg2.b.nonperio_tx_q_depth);
230 DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
231 core_if->hwcfg2.b.host_perio_tx_q_depth);
232 DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
233 core_if->hwcfg2.b.dev_token_q_depth);
235 DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
236 core_if->hwcfg3.b.dfifo_depth);
237 DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
238 core_if->hwcfg3.b.xfer_size_cntr_width);
241 * Set the SRP sucess bit for FS-I2c
243 core_if->srp_success = 0;
244 core_if->srp_timer_started = 0;
247 * Create new workqueue and init works
249 core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
250 if (core_if->wq_otg == 0) {
251 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
258 core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
259 DWC_PRINTF("%p\n",&core_if->core_global_regs->gsnpsid);
260 DWC_PRINTF("Core Release: %x.%x%x%x\n",
261 (core_if->snpsid >> 12 & 0xF),
262 (core_if->snpsid >> 8 & 0xF),
263 (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
265 core_if->wkp_tasklet = DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
267 if (dwc_otg_setup_params(core_if)) {
268 DWC_WARN("Error while setting core params\n");
271 core_if->hibernation_suspend = 0;
272 if (core_if->otg_ver)
273 core_if->test_mode = 0;
275 /** ADP initialization */
276 dwc_otg_adp_init(core_if);
282 * This function frees the structures allocated by dwc_otg_cil_init().
284 * @param core_if The core interface pointer returned from
285 * dwc_otg_cil_init().
288 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
290 dctl_data_t dctl = {.d32 = 0 };
291 /* Disable all interrupts */
292 DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
293 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
295 dctl.b.sftdiscon = 1;
296 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
297 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
301 if (core_if->wq_otg) {
302 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
303 DWC_WORKQ_FREE(core_if->wq_otg);
305 if (core_if->dev_if) {
306 DWC_FREE(core_if->dev_if);
308 if (core_if->host_if) {
309 DWC_FREE(core_if->host_if);
312 /** Remove ADP Stuff */
313 dwc_otg_adp_remove(core_if);
314 if (core_if->core_params) {
315 DWC_FREE(core_if->core_params);
317 if (core_if->wkp_tasklet){
318 DWC_TASK_FREE(core_if->wkp_tasklet);
320 if (core_if->srp_timer) {
321 DWC_TIMER_FREE(core_if->srp_timer);
327 * This function enables the controller's Global Interrupt in the AHB Config
330 * @param core_if Programming view of DWC_otg controller.
332 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
334 gahbcfg_data_t ahbcfg = {.d32 = 0 };
335 ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */
336 DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
340 * This function disables the controller's Global Interrupt in the AHB Config
343 * @param core_if Programming view of DWC_otg controller.
345 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
347 gahbcfg_data_t ahbcfg = {.d32 = 0 };
348 ahbcfg.b.glblintrmsk = 1; /* Disable interrupts */
349 DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
353 * This function initializes the commmon interrupts, used in both
354 * device and host modes.
356 * @param core_if Programming view of the DWC_otg controller
359 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
361 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
362 gintmsk_data_t intr_mask = {.d32 = 0 };
364 /* Clear any pending OTG Interrupts */
365 DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
367 /* Clear any pending interrupts */
368 DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
371 * Enable the interrupts in the GINTMSK.
373 intr_mask.b.modemismatch = 1;
374 intr_mask.b.otgintr = 1;
376 if (!core_if->dma_enable) {
377 intr_mask.b.rxstsqlvl = 1;
380 intr_mask.b.conidstschng = 1;
381 intr_mask.b.wkupintr = 1;
382 intr_mask.b.disconnect = 0;
383 intr_mask.b.usbsuspend = 1;
384 //intr_mask.b.sessreqintr = 1;
385 #ifdef CONFIG_USB_DWC_OTG_LPM
386 if (core_if->core_params->lpm_enable) {
387 intr_mask.b.lpmtranrcvd = 1;
390 DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
394 * The restore operation is modified to support Synopsys Emulated Powerdown and
395 * Hibernation. This function is for exiting from Device mode hibernation by
396 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
397 * @param core_if Programming view of DWC_otg controller.
398 * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
399 * @param reset - indicates whether resume is initiated by Reset.
401 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
402 int rem_wakeup, int reset)
404 gpwrdn_data_t gpwrdn = {.d32 = 0 };
405 pcgcctl_data_t pcgcctl = {.d32 = 0 };
406 dctl_data_t dctl = {.d32 = 0 };
410 if (!core_if->hibernation_suspend) {
411 DWC_PRINTF("Already exited from Hibernation\n");
415 DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
416 /* Switch-on voltage to the core */
417 gpwrdn.b.pwrdnswtch = 1;
418 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
423 gpwrdn.b.pwrdnrstn = 1;
424 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
427 /* Assert Restore signal */
429 gpwrdn.b.restore = 1;
430 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
433 /* Disable power clamps */
435 gpwrdn.b.pwrdnclmp = 1;
436 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
442 /* Deassert Reset core */
444 gpwrdn.b.pwrdnrstn = 1;
445 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
448 /* Disable PMU interrupt */
450 gpwrdn.b.pmuintsel = 1;
451 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
453 /* Mask interrupts from gpwrdn */
455 gpwrdn.b.connect_det_msk = 1;
456 gpwrdn.b.srp_det_msk = 1;
457 gpwrdn.b.disconn_det_msk = 1;
458 gpwrdn.b.rst_det_msk = 1;
459 gpwrdn.b.lnstchng_msk = 1;
460 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
462 /* Indicates that we are going out from hibernation */
463 core_if->hibernation_suspend = 0;
466 * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
467 * indicates restore from remote_wakeup
469 restore_essential_regs(core_if, rem_wakeup, 0);
472 * Wait a little for seeing new value of variable hibernation_suspend if
473 * Restore done interrupt received before polling
477 if (core_if->hibernation_suspend == 0) {
479 * Wait For Restore_done Interrupt. This mechanism of polling the
480 * interrupt is introduced to avoid any possible race conditions
483 gintsts_data_t gintsts;
485 DWC_READ_REG32(&core_if->core_global_regs->gintsts);
486 if (gintsts.b.restoredone) {
488 gintsts.b.restoredone = 1;
489 DWC_WRITE_REG32(&core_if->core_global_regs->
490 gintsts, gintsts.d32);
491 DWC_PRINTF("Restore Done Interrupt seen\n");
497 DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
500 /* Clear all pending interupts */
501 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
503 /* De-assert Restore */
505 gpwrdn.b.restore = 1;
506 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
511 pcgcctl.b.rstpdwnmodule = 1;
512 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
515 /* Restore GUSBCFG and DCFG */
516 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
517 core_if->gr_backup->gusbcfg_local);
518 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
519 core_if->dr_backup->dcfg);
521 /* De-assert Wakeup Logic */
523 gpwrdn.b.pmuactv = 1;
524 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
528 /* Set Device programming done bit */
529 dctl.b.pwronprgdone = 1;
530 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
532 /* Start Remote Wakeup Signaling */
533 dctl.d32 = core_if->dr_backup->dctl;
534 dctl.b.rmtwkupsig = 1;
535 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
539 /* Clear all pending interupts */
540 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
542 /* Restore global registers */
543 dwc_otg_restore_global_regs(core_if);
544 /* Restore device global registers */
545 dwc_otg_restore_dev_regs(core_if, rem_wakeup);
550 dctl.b.rmtwkupsig = 1;
551 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
554 core_if->hibernation_suspend = 0;
555 /* The core will be in ON STATE */
556 core_if->lx_state = DWC_OTG_L0;
557 DWC_PRINTF("Hibernation recovery completes here\n");
563 * The restore operation is modified to support Synopsys Emulated Powerdown and
564 * Hibernation. This function is for exiting from Host mode hibernation by
565 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
566 * @param core_if Programming view of DWC_otg controller.
567 * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
568 * @param reset - indicates whether resume is initiated by Reset.
570 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
571 int rem_wakeup, int reset)
573 gpwrdn_data_t gpwrdn = {.d32 = 0 };
574 hprt0_data_t hprt0 = {.d32 = 0 };
578 DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
579 /* Switch-on voltage to the core */
580 gpwrdn.b.pwrdnswtch = 1;
581 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
586 gpwrdn.b.pwrdnrstn = 1;
587 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
590 /* Assert Restore signal */
592 gpwrdn.b.restore = 1;
593 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
596 /* Disable power clamps */
598 gpwrdn.b.pwrdnclmp = 1;
599 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
605 /* Deassert Reset core */
607 gpwrdn.b.pwrdnrstn = 1;
608 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
611 /* Disable PMU interrupt */
613 gpwrdn.b.pmuintsel = 1;
614 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
617 gpwrdn.b.connect_det_msk = 1;
618 gpwrdn.b.srp_det_msk = 1;
619 gpwrdn.b.disconn_det_msk = 1;
620 gpwrdn.b.rst_det_msk = 1;
621 gpwrdn.b.lnstchng_msk = 1;
622 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
624 /* Indicates that we are going out from hibernation */
625 core_if->hibernation_suspend = 0;
627 /* Set Restore Essential Regs bit in PCGCCTL register */
628 restore_essential_regs(core_if, rem_wakeup, 1);
630 /* Wait a little for seeing new value of variable hibernation_suspend if
631 * Restore done interrupt received before polling */
634 if (core_if->hibernation_suspend == 0) {
635 /* Wait For Restore_done Interrupt. This mechanism of polling the
636 * interrupt is introduced to avoid any possible race conditions
639 gintsts_data_t gintsts;
640 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
641 if (gintsts.b.restoredone) {
643 gintsts.b.restoredone = 1;
644 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
645 DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
651 DWC_WARN("Restore Done interrupt wasn't generated\n");
655 /* Set the flag's value to 0 again after receiving restore done interrupt */
656 core_if->hibernation_suspend = 0;
658 /* This step is not described in functional spec but if not wait for this
659 * delay, mismatch interrupts occurred because just after restore core is
660 * in Device mode(gintsts.curmode == 0) */
663 /* Clear all pending interrupts */
664 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
666 /* De-assert Restore */
668 gpwrdn.b.restore = 1;
669 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
672 /* Restore GUSBCFG and HCFG */
673 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
674 core_if->gr_backup->gusbcfg_local);
675 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
676 core_if->hr_backup->hcfg_local);
678 /* De-assert Wakeup Logic */
680 gpwrdn.b.pmuactv = 1;
681 DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
684 /* Start the Resume operation by programming HPRT0 */
685 hprt0.d32 = core_if->hr_backup->hprt0_local;
689 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
691 DWC_PRINTF("Resume Starts Now\n");
692 if (!reset) { // Indicates it is Resume Operation
693 hprt0.d32 = core_if->hr_backup->hprt0_local;
698 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
702 /* Wait for Resume time and then program HPRT again */
704 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
706 } else { // Indicates it is Reset Operation
707 hprt0.d32 = core_if->hr_backup->hprt0_local;
712 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
713 /* Wait for Reset time and then program HPRT again */
716 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
718 /* Clear all interrupt status */
719 hprt0.d32 = dwc_otg_read_hprt0(core_if);
720 hprt0.b.prtconndet = 1;
721 hprt0.b.prtenchng = 1;
722 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
724 /* Clear all pending interupts */
725 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
727 /* Restore global registers */
728 dwc_otg_restore_global_regs(core_if);
729 /* Restore host global registers */
730 dwc_otg_restore_host_regs(core_if, reset);
732 /* The core will be in ON STATE */
733 core_if->lx_state = DWC_OTG_L0;
734 DWC_PRINTF("Hibernation recovery is complete here\n");
738 /** Saves some register values into system memory. */
739 int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
741 struct dwc_otg_global_regs_backup *gr;
744 gr = core_if->gr_backup;
746 gr = DWC_ALLOC(sizeof(*gr));
748 return -DWC_E_NO_MEMORY;
750 core_if->gr_backup = gr;
753 gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
754 gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
755 gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
756 gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
757 gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
758 gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
759 gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
760 #ifdef CONFIG_USB_DWC_OTG_LPM
761 gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
763 gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
764 gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
765 gr->gdfifocfg_local =
766 DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
767 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
768 gr->dtxfsiz_local[i] =
769 DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
772 DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
773 DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl = %08x\n", gr->gotgctl_local);
774 DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
775 DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg = %08x\n", gr->gahbcfg_local);
776 DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg = %08x\n", gr->gusbcfg_local);
777 DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz = %08x\n", gr->grxfsiz_local);
778 DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
779 gr->gnptxfsiz_local);
780 DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz = %08x\n",
782 #ifdef CONFIG_USB_DWC_OTG_LPM
783 DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg = %08x\n", gr->glpmcfg_local);
785 DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl = %08x\n", gr->gi2cctl_local);
786 DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl = %08x\n", gr->pcgcctl_local);
787 DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg = %08x\n",gr->gdfifocfg_local);
792 /** Saves GINTMSK register before setting the msk bits. */
793 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
795 struct dwc_otg_global_regs_backup *gr;
797 gr = core_if->gr_backup;
799 gr = DWC_ALLOC(sizeof(*gr));
801 return -DWC_E_NO_MEMORY;
803 core_if->gr_backup = gr;
806 gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
808 DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
809 DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk = %08x\n", gr->gintmsk_local);
814 int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
816 struct dwc_otg_dev_regs_backup *dr;
819 dr = core_if->dr_backup;
821 dr = DWC_ALLOC(sizeof(*dr));
823 return -DWC_E_NO_MEMORY;
825 core_if->dr_backup = dr;
828 dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
829 dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
831 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
833 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
835 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
837 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
839 DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
841 DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
843 DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
847 "=============Backing Host registers==============\n");
848 DWC_DEBUGPL(DBG_ANY, "Backed up dcfg = %08x\n", dr->dcfg);
849 DWC_DEBUGPL(DBG_ANY, "Backed up dctl = %08x\n", dr->dctl);
850 DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk = %08x\n",
852 DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk = %08x\n", dr->diepmsk);
853 DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk = %08x\n", dr->doepmsk);
854 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
855 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d] = %08x\n", i,
857 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d] = %08x\n",
859 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d] = %08x\n", i,
866 int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
868 struct dwc_otg_host_regs_backup *hr;
871 hr = core_if->hr_backup;
873 hr = DWC_ALLOC(sizeof(*hr));
875 return -DWC_E_NO_MEMORY;
877 core_if->hr_backup = hr;
881 DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
883 DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
884 for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
885 hr->hcintmsk_local[i] =
886 DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
888 hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
890 DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
893 "=============Backing Host registers===============\n");
894 DWC_DEBUGPL(DBG_ANY, "Backed up hcfg = %08x\n",
896 DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
897 for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
898 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
899 hr->hcintmsk_local[i]);
901 DWC_DEBUGPL(DBG_ANY, "Backed up hprt0 = %08x\n",
903 DWC_DEBUGPL(DBG_ANY, "Backed up hfir = %08x\n",
909 int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if)
911 struct dwc_otg_global_regs_backup *gr;
914 gr = core_if->gr_backup;
916 return -DWC_E_INVALID;
919 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
920 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
921 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
922 DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
923 DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
924 DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
925 gr->gnptxfsiz_local);
926 DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
928 DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
929 gr->gdfifocfg_local);
930 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
931 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
932 gr->dtxfsiz_local[i]);
935 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
936 DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
937 DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
938 (gr->gahbcfg_local));
942 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
944 struct dwc_otg_dev_regs_backup *dr;
947 dr = core_if->dr_backup;
950 return -DWC_E_INVALID;
954 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
958 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
959 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
960 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
962 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
963 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
964 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
965 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
971 int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
973 struct dwc_otg_host_regs_backup *hr;
975 hr = core_if->hr_backup;
978 return -DWC_E_INVALID;
981 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
984 // DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
987 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
989 for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
990 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
991 hr->hcintmsk_local[i]);
997 int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
999 struct dwc_otg_global_regs_backup *gr;
1001 gr = core_if->gr_backup;
1003 /* Restore values for LPM and I2C */
1004 #ifdef CONFIG_USB_DWC_OTG_LPM
1005 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
1007 DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
1012 int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
1014 struct dwc_otg_global_regs_backup *gr;
1015 pcgcctl_data_t pcgcctl = {.d32 = 0 };
1016 gahbcfg_data_t gahbcfg = {.d32 = 0 };
1017 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1018 gintmsk_data_t gintmsk = {.d32 = 0 };
1020 /* Restore LPM and I2C registers */
1021 restore_lpm_i2c_regs(core_if);
1023 /* Set PCGCCTL to 0 */
1024 DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
1026 gr = core_if->gr_backup;
1027 /* Load restore values for [31:14] bits */
1028 DWC_WRITE_REG32(core_if->pcgcctl,
1029 ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
1031 /* Umnask global Interrupt in GAHBCFG and restore it */
1032 gahbcfg.d32 = gr->gahbcfg_local;
1033 gahbcfg.b.glblintrmsk = 1;
1034 DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
1036 /* Clear all pending interupts */
1037 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1039 /* Unmask restore done interrupt */
1040 gintmsk.b.restoredone = 1;
1041 DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1043 /* Restore GUSBCFG and HCFG/DCFG */
1044 gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
1045 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
1048 hcfg_data_t hcfg = {.d32 = 0 };
1049 hcfg.d32 = core_if->hr_backup->hcfg_local;
1050 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
1053 /* Load restore values for [31:14] bits */
1054 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1055 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1058 pcgcctl.b.restoremode = 1;
1059 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1062 /* Load restore values for [31:14] bits and set EssRegRestored bit */
1063 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
1064 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1065 pcgcctl.b.ess_reg_restored = 1;
1067 pcgcctl.b.restoremode = 1;
1068 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1070 dcfg_data_t dcfg = {.d32 = 0 };
1071 dcfg.d32 = core_if->dr_backup->dcfg;
1072 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1074 /* Load restore values for [31:14] bits */
1075 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1076 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1078 pcgcctl.d32 |= 0x208;
1080 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1083 /* Load restore values for [31:14] bits */
1084 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1085 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1086 pcgcctl.b.ess_reg_restored = 1;
1088 pcgcctl.d32 |= 0x208;
1089 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1096 * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1099 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
1104 if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1105 (core_if->hwcfg2.b.fs_phy_type == 1) &&
1106 (core_if->core_params->ulpi_fs_ls)) ||
1107 (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1108 /* Full speed PHY */
1109 val = DWC_HCFG_48_MHZ;
1111 /* High speed PHY running at full speed or high speed */
1112 val = DWC_HCFG_30_60_MHZ;
1115 DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1116 hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
1117 hcfg.b.fslspclksel = val;
1118 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1122 * Initializes the DevSpd field of the DCFG register depending on the PHY type
1123 * and the enumeration speed of the device.
1125 static void init_devspd(dwc_otg_core_if_t * core_if)
1130 if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1131 (core_if->hwcfg2.b.fs_phy_type == 1) &&
1132 (core_if->core_params->ulpi_fs_ls)) ||
1133 (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1134 /* Full speed PHY */
1136 } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1137 /* High speed PHY running at full speed */
1140 /* High speed PHY running at high speed */
1144 DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1146 dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1147 dcfg.b.devspd = val;
1148 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1152 * This function calculates the number of IN EPS
1153 * using GHWCFG1 and GHWCFG2 registers values
1155 * @param core_if Programming view of the DWC_otg controller
1157 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
1159 uint32_t num_in_eps = 0;
1160 uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1161 uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1162 uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1165 for (i = 0; i < num_eps; ++i) {
1166 if (!(hwcfg1 & 0x1))
1172 if (core_if->hwcfg4.b.ded_fifo_en) {
1174 (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1181 * This function calculates the number of OUT EPS
1182 * using GHWCFG1 and GHWCFG2 registers values
1184 * @param core_if Programming view of the DWC_otg controller
1186 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
1188 uint32_t num_out_eps = 0;
1189 uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1190 uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1193 for (i = 0; i < num_eps; ++i) {
1194 if (!(hwcfg1 & 0x1))
1203 * This function initializes the DWC_otg controller registers and
1204 * prepares the core for device mode or host mode operation.
1206 * @param core_if Programming view of the DWC_otg controller
1209 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
1212 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1213 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1214 gahbcfg_data_t ahbcfg = {.d32 = 0 };
1215 gusbcfg_data_t usbcfg = {.d32 = 0 };
1216 gi2cctl_data_t i2cctl = {.d32 = 0 };
1218 DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1220 /* Common Initialization */
1221 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1223 /* Program the ULPI External VBUS bit if needed */
1224 usbcfg.b.ulpi_ext_vbus_drv =
1225 (core_if->core_params->phy_ulpi_ext_vbus ==
1226 DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1228 /* Set external TS Dline pulsing */
1229 usbcfg.b.term_sel_dl_pulse =
1230 (core_if->core_params->ts_dline == 1) ? 1 : 0;
1231 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1233 /* Reset the Controller */
1234 dwc_otg_core_reset(core_if);
1236 core_if->adp_enable = core_if->core_params->adp_supp_enable;
1237 core_if->power_down = core_if->core_params->power_down;
1239 /* Initialize parameters from Hardware configuration registers. */
1240 dev_if->num_in_eps = calc_num_in_eps(core_if);
1241 dev_if->num_out_eps = calc_num_out_eps(core_if);
1243 DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1244 core_if->hwcfg4.b.num_dev_perio_in_ep);
1246 for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1247 dev_if->perio_tx_fifo_size[i] =
1248 DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1249 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1250 i, dev_if->perio_tx_fifo_size[i]);
1253 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1254 dev_if->tx_fifo_size[i] =
1255 DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1256 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1257 i, dev_if->tx_fifo_size[i]);
1260 core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1261 core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1262 core_if->nperio_tx_fifo_size =
1263 DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1265 DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1266 DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1267 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1268 core_if->nperio_tx_fifo_size);
1270 /* This programming sequence needs to happen in FS mode before any other
1271 * programming occurs */
1272 if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1273 (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1274 /* If FS mode with FS PHY */
1276 /* core_init() is now called on every switch so only call the
1277 * following for the first time through. */
1278 if (!core_if->phy_init_done) {
1279 core_if->phy_init_done = 1;
1280 DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1281 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1282 usbcfg.b.physel = 1;
1283 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1285 /* Reset after a PHY select */
1286 dwc_otg_core_reset(core_if);
1289 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1290 * do this on HNP Dev/Host mode switches (done in dev_init and
1292 if (dwc_otg_is_host_mode(core_if)) {
1293 init_fslspclksel(core_if);
1295 init_devspd(core_if);
1298 if (core_if->core_params->i2c_enable) {
1299 DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1300 /* Program GUSBCFG.OtgUtmifsSel to I2C */
1301 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1302 usbcfg.b.otgutmifssel = 1;
1303 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1305 /* Program GI2CCTL.I2CEn */
1306 i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1307 i2cctl.b.i2cdevaddr = 1;
1309 DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1311 DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1314 } /* endif speed == DWC_SPEED_PARAM_FULL */
1316 /* High speed PHY. */
1317 if (!core_if->phy_init_done) {
1318 core_if->phy_init_done = 1;
1319 /* HS PHY parameters. These parameters are preserved
1320 * during soft reset so only program the first time. Do
1321 * a soft reset immediately after setting phyif. */
1323 if (core_if->core_params->phy_type == 2) {
1324 /* ULPI interface */
1325 usbcfg.b.ulpi_utmi_sel = 1;
1328 core_if->core_params->phy_ulpi_ddr;
1329 } else if (core_if->core_params->phy_type == 1) {
1330 /* UTMI+ interface */
1331 usbcfg.b.ulpi_utmi_sel = 0;
1332 if (core_if->core_params->phy_utmi_width == 16) {
1339 DWC_ERROR("FS PHY TYPE\n");
1341 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1342 /* Reset after setting the PHY parameters */
1343 dwc_otg_core_reset(core_if);
1347 if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1348 (core_if->hwcfg2.b.fs_phy_type == 1) &&
1349 (core_if->core_params->ulpi_fs_ls)) {
1350 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1351 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1352 usbcfg.b.ulpi_fsls = 1;
1353 usbcfg.b.ulpi_clk_sus_m = 1;
1354 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1356 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1357 usbcfg.b.ulpi_fsls = 0;
1358 usbcfg.b.ulpi_clk_sus_m = 0;
1359 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1362 /* Program the GAHBCFG Register. */
1363 switch (core_if->hwcfg2.b.architecture) {
1365 case DWC_SLAVE_ONLY_ARCH:
1366 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1367 ahbcfg.b.nptxfemplvl_txfemplvl =
1368 DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1369 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1370 core_if->dma_enable = 0;
1371 core_if->dma_desc_enable = 0;
1374 case DWC_EXT_DMA_ARCH:
1375 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1377 uint8_t brst_sz = core_if->core_params->dma_burst_size;
1378 ahbcfg.b.hburstlen = 0;
1379 while (brst_sz > 1) {
1380 ahbcfg.b.hburstlen++;
1384 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1385 core_if->dma_desc_enable =
1386 (core_if->core_params->dma_desc_enable != 0);
1389 case DWC_INT_DMA_ARCH:
1390 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1391 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1392 Host mode ISOC in issue fix - vahrama */
1393 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
1394 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1395 core_if->dma_desc_enable =
1396 (core_if->core_params->dma_desc_enable != 0);
1400 if (core_if->dma_enable) {
1401 if (core_if->dma_desc_enable) {
1402 DWC_PRINTF("Using Descriptor DMA mode\n");
1404 DWC_PRINTF("Using Buffer DMA mode\n");
1407 DWC_PRINTF("Using Slave mode\n");
1408 core_if->dma_desc_enable = 0;
1411 if (core_if->core_params->ahb_single) {
1412 ahbcfg.b.ahbsingle = 1;
1415 ahbcfg.b.dmaenable = core_if->dma_enable;
1416 DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1418 core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1420 core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1421 core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1422 DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1423 ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1424 DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1425 ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1428 * Program the GUSBCFG register.
1430 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1432 switch (core_if->hwcfg2.b.op_mode) {
1433 case DWC_MODE_HNP_SRP_CAPABLE:
1434 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1435 DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1436 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1437 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1440 case DWC_MODE_SRP_ONLY_CAPABLE:
1441 usbcfg.b.hnpcap = 0;
1442 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1443 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1446 case DWC_MODE_NO_HNP_SRP_CAPABLE:
1447 usbcfg.b.hnpcap = 0;
1448 usbcfg.b.srpcap = 0;
1451 case DWC_MODE_SRP_CAPABLE_DEVICE:
1452 usbcfg.b.hnpcap = 0;
1453 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1454 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1457 case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1458 usbcfg.b.hnpcap = 0;
1459 usbcfg.b.srpcap = 0;
1462 case DWC_MODE_SRP_CAPABLE_HOST:
1463 usbcfg.b.hnpcap = 0;
1464 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1465 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1468 case DWC_MODE_NO_SRP_CAPABLE_HOST:
1469 usbcfg.b.hnpcap = 0;
1470 usbcfg.b.srpcap = 0;
1474 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1476 #ifdef CONFIG_USB_DWC_OTG_LPM
1477 if (core_if->core_params->lpm_enable) {
1478 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1480 /* To enable LPM support set lpm_cap_en bit */
1481 lpmcfg.b.lpm_cap_en = 1;
1483 /* Make AppL1Res ACK */
1484 lpmcfg.b.appl_resp = 1;
1487 lpmcfg.b.retry_count = 3;
1489 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1494 if (core_if->core_params->ic_usb_cap) {
1495 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1496 gusbcfg.b.ic_usb_cap = 1;
1497 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1501 gotgctl_data_t gotgctl = {.d32 = 0 };
1502 gotgctl.b.otgver = core_if->core_params->otg_ver;
1503 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1505 /* Set OTG version supported */
1506 core_if->otg_ver = core_if->core_params->otg_ver;
1507 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1508 core_if->core_params->otg_ver, core_if->otg_ver);
1511 /* Enable common interrupts */
1512 dwc_otg_enable_common_interrupts(core_if);
1514 /* Do device or host intialization based on mode during PCD
1515 * and HCD initialization */
1516 if (dwc_otg_is_host_mode(core_if)) {
1517 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
1518 core_if->op_state = A_HOST;
1520 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
1521 core_if->op_state = B_PERIPHERAL;
1522 #ifdef DWC_DEVICE_ONLY
1523 dwc_otg_core_dev_init(core_if);
1529 * This function enables the Device mode interrupts.
1531 * @param core_if Programming view of DWC_otg controller
1533 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
1535 gintmsk_data_t intr_mask = {.d32 = 0 };
1536 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1538 DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1540 /* Disable all interrupts. */
1541 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
1543 /* Clear any pending interrupts */
1544 DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
1546 /* Enable the common interrupts */
1547 dwc_otg_enable_common_interrupts(core_if);
1549 /* Enable interrupts */
1550 intr_mask.b.usbreset = 1;
1551 intr_mask.b.enumdone = 1;
1552 /* Disable Disconnect interrupt in Device mode */
1553 intr_mask.b.disconnect = 0;
1555 if (!core_if->multiproc_int_enable) {
1556 intr_mask.b.inepintr = 1;
1557 intr_mask.b.outepintr = 1;
1560 intr_mask.b.erlysuspend = 1;
1562 if (core_if->en_multiple_tx_fifo == 0) {
1563 intr_mask.b.epmismatch = 1;
1566 //intr_mask.b.incomplisoout = 1;
1567 intr_mask.b.incomplisoin = 1;
1569 /* Enable the ignore frame number for ISOC xfers - MAS */
1570 /* Disable to support high bandwith ISOC transfers - manukz */
1572 #ifdef DWC_UTE_PER_IO
1573 if (core_if->dma_enable) {
1574 if (core_if->dma_desc_enable) {
1575 dctl_data_t dctl1 = {.d32 = 0 };
1576 dctl1.b.ifrmnum = 1;
1577 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
1578 dctl, 0, dctl1.d32);
1579 DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
1580 DWC_READ_REG32(&core_if->dev_if->
1581 dev_global_regs->dctl));
1587 if (core_if->dma_enable) {
1588 if (core_if->dma_desc_enable == 0) {
1589 if (core_if->pti_enh_enable) {
1590 dctl_data_t dctl = {.d32 = 0 };
1592 DWC_MODIFY_REG32(&core_if->
1593 dev_if->dev_global_regs->dctl,
1596 intr_mask.b.incomplisoin = 1;
1597 intr_mask.b.incomplisoout = 1;
1601 intr_mask.b.incomplisoin = 1;
1602 intr_mask.b.incomplisoout = 1;
1604 #endif /* DWC_EN_ISOC */
1606 /** @todo NGS: Should this be a module parameter? */
1607 #ifdef USE_PERIODIC_EP
1608 intr_mask.b.isooutdrop = 1;
1609 intr_mask.b.eopframe = 1;
1610 intr_mask.b.incomplisoin = 1;
1611 intr_mask.b.incomplisoout = 1;
1614 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1616 DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1617 DWC_READ_REG32(&global_regs->gintmsk));
1621 * This function initializes the DWC_otg controller registers for
1624 * @param core_if Programming view of DWC_otg controller
1627 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
1630 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1631 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1632 dwc_otg_core_params_t *params = core_if->core_params;
1633 dcfg_data_t dcfg = {.d32 = 0 };
1634 depctl_data_t diepctl = {.d32 = 0 };
1635 grstctl_t resetctl = {.d32 = 0 };
1636 uint32_t rx_fifo_size;
1637 fifosize_data_t nptxfifosize;
1638 fifosize_data_t txfifosize;
1639 dthrctl_data_t dthrctl;
1640 fifosize_data_t ptxfifosize;
1641 // uint16_t rxfsiz, nptxfsiz;
1642 // gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
1643 // hwcfg3_data_t hwcfg3 = {.d32 = 0 };
1644 gotgctl_data_t gotgctl = {.d32 = 0 };
1645 gahbcfg_data_t gahbcfg = {.d32 = 0};
1647 /* Restart the Phy Clock */
1648 pcgcctl_data_t pcgcctl = {.d32 = 0 };
1649 /* Restart the Phy Clock */
1650 pcgcctl.b.stoppclk = 1;
1651 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1654 gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
1655 DWC_MODIFY_REG32(&global_regs->gahbcfg, 0 , gahbcfg.b.hburstlen);
1657 /* Device configuration register */
1658 init_devspd(core_if);
1659 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1660 dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1661 dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1662 /* Enable Device OUT NAK in case of DDMA mode */
1663 if (core_if->core_params->dev_out_nak) {
1664 dcfg.b.endevoutnak = 1;
1667 if (core_if->core_params->cont_on_bna) {
1668 dctl_data_t dctl = {.d32 = 0 };
1669 dctl.b.encontonbna = 1;
1670 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
1672 /** should be done before every reset */
1673 if (core_if->otg_ver) {
1674 core_if->otg_sts = 0;
1675 gotgctl.b.devhnpen = 1;
1676 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, gotgctl.d32, 0);
1679 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1681 /* Configure data FIFO sizes */
1683 if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1685 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
1686 core_if->init_rxfsiz = params->dev_rx_fifo_size;
1688 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1689 DWC_READ_REG32(&global_regs->grxfsiz));
1691 /** Set Periodic Tx FIFO Mask all bits 0 */
1692 core_if->p_tx_msk = 0;
1694 /** Set Tx FIFO Mask all bits 0 */
1695 core_if->tx_msk = 0;
1696 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
1697 * and ded_fifo_en is 1 in default*/
1698 if (core_if->en_multiple_tx_fifo == 0) {
1699 /* Non-periodic Tx FIFO */
1700 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1701 DWC_READ_REG32(&global_regs->gnptxfsiz));
1703 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1704 nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1706 DWC_WRITE_REG32(&global_regs->gnptxfsiz,
1709 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1710 DWC_READ_REG32(&global_regs->gnptxfsiz));
1712 /**@todo NGS: Fix Periodic FIFO Sizing! */
1714 * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1715 * Indexes of the FIFO size module parameters in the
1716 * dev_perio_tx_fifo_size array and the FIFO size registers in
1717 * the dptxfsiz array run from 0 to 14.
1719 /** @todo Finish debug of this */
1720 ptxfifosize.b.startaddr =
1721 nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1722 for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1723 ptxfifosize.b.depth =
1724 params->dev_perio_tx_fifo_size[i];
1725 DWC_DEBUGPL(DBG_CIL,
1726 "initial dtxfsiz[%d]=%08x\n", i,
1727 DWC_READ_REG32(&global_regs->dtxfsiz
1729 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
1731 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
1733 DWC_READ_REG32(&global_regs->dtxfsiz
1735 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
1739 * Tx FIFOs These FIFOs are numbered from 1 to 15.
1740 * Indexes of the FIFO size module parameters in the
1741 * dev_tx_fifo_size array and the FIFO size registers in
1742 * the dtxfsiz array run from 0 to 14.
1745 /* Non-periodic Tx FIFO */
1746 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1747 DWC_READ_REG32(&global_regs->gnptxfsiz));
1750 core_if->pwron_gnptxfsiz =
1751 (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
1752 core_if->init_gnptxfsiz =
1753 params->dev_nperio_tx_fifo_size;
1755 rx_fifo_size = params->dev_rx_fifo_size;
1756 DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
1757 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1758 DWC_READ_REG32(&global_regs->grxfsiz));
1760 nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1761 nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1762 DWC_WRITE_REG32(&global_regs->gnptxfsiz,
1765 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1766 DWC_READ_REG32(&global_regs->gnptxfsiz));
1768 txfifosize.b.startaddr =
1769 nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1771 for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1773 txfifosize.b.depth =
1774 params->dev_tx_fifo_size[i];
1776 DWC_DEBUGPL(DBG_CIL,
1777 "initial dtxfsiz[%d]=%08x\n",
1779 DWC_READ_REG32(&global_regs->dtxfsiz
1783 core_if->pwron_txfsiz[i] =
1785 (&global_regs->dtxfsiz[i]) >> 16);
1786 core_if->init_txfsiz[i] =
1787 params->dev_tx_fifo_size[i];
1789 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
1792 DWC_DEBUGPL(DBG_CIL,
1793 "new dtxfsiz[%d]=%08x\n",
1795 DWC_READ_REG32(&global_regs->dtxfsiz
1798 txfifosize.b.startaddr += txfifosize.b.depth;
1801 /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
1802 * Before 3.00a EpInfoBase was being configured in ep enable/disable
1803 * routine as well. Starting from 3.00a it will be set to the end of
1804 * allocated FIFO space here due to ep 0 OUT always keeping enabled
1806 gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
1807 hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
1808 gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
1809 DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
1810 if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
1811 rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
1812 nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
1813 gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
1815 gdfifocfg.b.epinfobase = txfifosize.b.startaddr;
1817 //DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
1822 /* Flush the FIFOs */
1823 dwc_otg_flush_tx_fifo(core_if, 0x10); /* all Tx FIFOs */
1824 dwc_otg_flush_rx_fifo(core_if);
1826 /* Flush the Learning Queue. */
1827 resetctl.b.intknqflsh = 1;
1828 DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
1830 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
1831 core_if->start_predict = 0;
1832 for (i = 0; i <= core_if->dev_if->num_in_eps; ++i) {
1833 core_if->nextep_seq[i] = 0xff; // 0xff - EP not active
1835 core_if->nextep_seq[0] = 0;
1836 core_if->first_in_nextep_seq = 0;
1837 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
1838 diepctl.b.nextep = 0;
1839 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
1841 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
1842 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1844 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1846 DWC_DEBUGPL(DBG_CILV,
1847 "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
1848 __func__, core_if->first_in_nextep_seq);
1849 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
1850 DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
1852 DWC_DEBUGPL(DBG_CILV, "\n");
1855 /* Clear all pending Device Interrupts */
1856 /** @todo - if the condition needed to be checked
1857 * or in any case all pending interrutps should be cleared?
1859 if (core_if->multiproc_int_enable) {
1860 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
1861 DWC_WRITE_REG32(&dev_if->dev_global_regs->
1862 diepeachintmsk[i], 0);
1865 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
1866 DWC_WRITE_REG32(&dev_if->dev_global_regs->
1867 doepeachintmsk[i], 0);
1870 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
1871 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
1873 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
1874 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
1875 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
1876 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
1879 for (i = 0; i <= dev_if->num_in_eps; i++) {
1880 depctl_data_t depctl;
1881 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
1882 if (depctl.b.epena) {
1890 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1892 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1893 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
1894 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1897 for (i = 1; i <= dev_if->num_out_eps; i++) {
1898 depctl_data_t depctl;
1899 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
1900 if (depctl.b.epena) {
1902 dctl_data_t dctl = {.d32 = 0 };
1903 gintmsk_data_t gintsts = {.d32 = 0 };
1904 doepint_data_t doepint = {.d32 = 0 };
1905 dctl.b.sgoutnak = 1;
1906 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1910 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
1912 DWC_ERROR("SNAK as not set during 10s\n");
1915 } while (!gintsts.b.goutnakeff);
1917 gintsts.b.goutnakeff = 1;
1918 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1924 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1927 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
1928 out_ep_regs[i]->doepint);
1930 DWC_ERROR("EPDIS was not set during 10s\n");
1933 } while (!doepint.b.epdisabled);
1935 doepint.b.epdisabled = 1;
1936 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
1939 dctl.b.cgoutnak = 1;
1940 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1945 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1946 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
1947 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
1948 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
1951 if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
1952 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
1953 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
1954 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
1956 dev_if->rx_thr_length = params->rx_thr_length;
1957 dev_if->tx_thr_length = params->tx_thr_length;
1959 dev_if->setup_desc_index = 0;
1962 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
1963 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
1964 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
1965 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
1966 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
1967 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
1969 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
1972 DWC_DEBUGPL(DBG_CIL,
1973 "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
1974 dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
1975 dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
1976 dthrctl.b.rx_thr_len);
1980 dwc_otg_enable_device_interrupts(core_if);
1983 diepmsk_data_t msk = {.d32 = 0 };
1984 msk.b.txfifoundrn = 1;
1985 if (core_if->multiproc_int_enable) {
1986 DWC_MODIFY_REG32(&dev_if->dev_global_regs->
1987 diepeachintmsk[0], msk.d32, msk.d32);
1989 DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
1994 if (core_if->multiproc_int_enable) {
1995 /* Set NAK on Babble */
1996 dctl_data_t dctl = {.d32 = 0 };
1997 dctl.b.nakonbble = 1;
1998 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
2003 * This function enables the Host mode interrupts.
2005 * @param core_if Programming view of DWC_otg controller
2007 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
2009 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2010 gintmsk_data_t intr_mask = {.d32 = 0 };
2012 DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2014 /* Disable all interrupts. */
2015 DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2017 /* Clear any pending interrupts. */
2018 DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
2020 /* Enable the common interrupts */
2021 dwc_otg_enable_common_interrupts(core_if);
2024 * Enable host mode interrupts without disturbing common
2028 intr_mask.b.disconnect = 1;
2029 intr_mask.b.portintr = 1;
2030 intr_mask.b.hcintr = 1;
2032 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2036 * This function disables the Host Mode interrupts.
2038 * @param core_if Programming view of DWC_otg controller
2040 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
2042 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2043 gintmsk_data_t intr_mask = {.d32 = 0 };
2045 DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2048 * Disable host mode interrupts without disturbing common
2051 intr_mask.b.sofintr = 1;
2052 intr_mask.b.portintr = 1;
2053 intr_mask.b.hcintr = 1;
2054 intr_mask.b.ptxfempty = 1;
2055 intr_mask.b.nptxfempty = 1;
2057 DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
2061 * This function initializes the DWC_otg controller registers for
2064 * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2065 * request queues. Host channels are reset to ensure that they are ready for
2066 * performing transfers.
2068 * @param core_if Programming view of DWC_otg controller
2071 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
2073 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2074 dwc_otg_host_if_t *host_if = core_if->host_if;
2075 dwc_otg_core_params_t *params = core_if->core_params;
2076 hprt0_data_t hprt0 = {.d32 = 0 };
2077 fifosize_data_t nptxfifosize;
2078 fifosize_data_t ptxfifosize;
2079 // uint16_t rxfsiz, nptxfsiz, hptxfsiz;
2080 // gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
2082 hcchar_data_t hcchar;
2085 dwc_otg_hc_regs_t *hc_regs;
2087 gotgctl_data_t gotgctl = {.d32 = 0 };
2088 pcgcctl_data_t pcgcctl = {.d32 = 0 };
2089 struct dwc_otg_platform_data *pldata;
2090 pldata = core_if->otg_dev->pldata;
2094 DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
2096 /* Restart the Phy Clock */
2097 pcgcctl.b.stoppclk = 1;
2098 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2101 if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
2102 DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
2103 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2104 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2105 if (hprt0.b.prtpwr == 0) {
2107 DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2111 /* Initialize Host Configuration Register */
2112 init_fslspclksel(core_if);
2113 if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
2114 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2115 hcfg.b.fslssupp = 1;
2116 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2120 /* This bit allows dynamic reloading of the HFIR register
2121 * during runtime. This bit needs to be programmed during
2122 * initial configuration and its value must not be changed
2124 if (core_if->core_params->reload_ctl == 1) {
2125 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
2126 hfir.b.hfirrldctrl = 1;
2127 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
2130 if (core_if->core_params->dma_desc_enable) {
2131 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
2133 (core_if->hwcfg4.b.desc_dma
2134 && (core_if->snpsid >= OTG_CORE_REV_2_90a)
2135 && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
2136 || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
2138 DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
2139 || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
2141 DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
2143 DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
2144 "Either core version is below 2.90a or "
2145 "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
2146 "To run the driver in Buffer DMA host mode set dma_desc_enable "
2147 "module parameter to 0.\n");
2150 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2152 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2155 /* Configure data FIFO sizes */
2156 if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2157 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
2158 core_if->total_fifo_size);
2159 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
2160 params->host_rx_fifo_size);
2161 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
2162 params->host_nperio_tx_fifo_size);
2163 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
2164 params->host_perio_tx_fifo_size);
2167 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2168 DWC_READ_REG32(&global_regs->grxfsiz));
2169 DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);//params->host_rx_fifo_size);
2170 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2171 DWC_READ_REG32(&global_regs->grxfsiz));
2173 /* Non-periodic Tx FIFO */
2174 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2175 DWC_READ_REG32(&global_regs->gnptxfsiz));
2176 nptxfifosize.b.depth = 0x0080;//params->host_nperio_tx_fifo_size;
2177 nptxfifosize.b.startaddr = 0x0200;//params->host_rx_fifo_size;
2178 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2179 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2180 DWC_READ_REG32(&global_regs->gnptxfsiz));
2182 /* Periodic Tx FIFO */
2183 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
2184 DWC_READ_REG32(&global_regs->hptxfsiz));
2185 ptxfifosize.b.depth = 0x0100;//params->host_perio_tx_fifo_size;
2186 ptxfifosize.b.startaddr = 0x0280;//nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2187 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
2188 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
2189 DWC_READ_REG32(&global_regs->hptxfsiz));
2191 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
2192 * and ded_fifo_en is 1 in default
2194 if (core_if->en_multiple_tx_fifo) {
2195 /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
2196 gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2197 rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
2198 nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2199 hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
2200 gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
2201 DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2206 /* TODO - check this */
2207 /* Clear Host Set HNP Enable in the OTG Control Register */
2208 gotgctl.b.hstsethnpen = 1;
2209 DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2210 /* Make sure the FIFOs are flushed. */
2211 dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
2212 dwc_otg_flush_rx_fifo(core_if);
2214 /* Clear Host Set HNP Enable in the OTG Control Register */
2215 gotgctl.b.hstsethnpen = 1;
2216 DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2218 if (!core_if->core_params->dma_desc_enable) {
2219 /* Flush out any leftover queued requests. */
2220 num_channels = core_if->core_params->host_channels;
2222 for (i = 0; i < num_channels; i++) {
2223 hc_regs = core_if->host_if->hc_regs[i];
2224 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2228 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2231 /* Halt all channels to put them into a known state. */
2232 for (i = 0; i < num_channels; i++) {
2234 hc_regs = core_if->host_if->hc_regs[i];
2235 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2239 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2240 DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2242 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2243 if (++count > 1000) {
2245 ("%s: Unable to clear halt on channel %d\n",
2250 } while (hcchar.b.chen);
2254 /* Turn on the vbus power. */
2255 if ((core_if->otg_ver == 0) && (core_if->op_state == A_HOST)) {
2256 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2257 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2258 if (hprt0.b.prtpwr == 0) {
2260 DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2262 if(pldata->power_enable)
2263 pldata->power_enable(1);
2266 dwc_otg_enable_host_interrupts(core_if);
2270 * Prepares a host channel for transferring packets to/from a specific
2271 * endpoint. The HCCHARn register is set up with the characteristics specified
2272 * in _hc. Host channel interrupts that may need to be serviced while this
2273 * transfer is in progress are enabled.
2275 * @param core_if Programming view of DWC_otg controller
2276 * @param hc Information needed to initialize the host channel
2278 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2280 uint32_t intr_enable;
2281 hcintmsk_data_t hc_intr_mask;
2282 gintmsk_data_t gintmsk = {.d32 = 0 };
2283 hcchar_data_t hcchar;
2284 hcsplt_data_t hcsplt;
2286 uint8_t hc_num = hc->hc_num;
2287 dwc_otg_host_if_t *host_if = core_if->host_if;
2288 dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2290 /* Clear old interrupt conditions for this host channel. */
2291 hc_intr_mask.d32 = 0xFFFFFFFF;
2292 hc_intr_mask.b.reserved14_31 = 0;
2293 DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
2295 /* Enable channel interrupts required for this transfer. */
2296 hc_intr_mask.d32 = 0;
2297 hc_intr_mask.b.chhltd = 1;
2298 if (core_if->dma_enable) {
2299 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
2300 if (!core_if->dma_desc_enable)
2301 hc_intr_mask.b.ahberr = 1;
2303 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2304 hc_intr_mask.b.xfercompl = 1;
2307 if (hc->error_state && !hc->do_split &&
2308 hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2309 hc_intr_mask.b.ack = 1;
2311 hc_intr_mask.b.datatglerr = 1;
2312 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2313 hc_intr_mask.b.nak = 1;
2318 switch (hc->ep_type) {
2319 case DWC_OTG_EP_TYPE_CONTROL:
2320 case DWC_OTG_EP_TYPE_BULK:
2321 hc_intr_mask.b.xfercompl = 1;
2322 hc_intr_mask.b.stall = 1;
2323 hc_intr_mask.b.xacterr = 1;
2324 hc_intr_mask.b.datatglerr = 1;
2326 hc_intr_mask.b.bblerr = 1;
2328 hc_intr_mask.b.nak = 1;
2329 hc_intr_mask.b.nyet = 1;
2331 hc_intr_mask.b.ack = 1;
2336 hc_intr_mask.b.nak = 1;
2337 if (hc->complete_split) {
2338 hc_intr_mask.b.nyet = 1;
2340 hc_intr_mask.b.ack = 1;
2344 if (hc->error_state) {
2345 hc_intr_mask.b.ack = 1;
2348 case DWC_OTG_EP_TYPE_INTR:
2349 hc_intr_mask.b.xfercompl = 1;
2350 hc_intr_mask.b.nak = 1;
2351 hc_intr_mask.b.stall = 1;
2352 hc_intr_mask.b.xacterr = 1;
2353 hc_intr_mask.b.datatglerr = 1;
2354 hc_intr_mask.b.frmovrun = 1;
2357 hc_intr_mask.b.bblerr = 1;
2359 if (hc->error_state) {
2360 hc_intr_mask.b.ack = 1;
2363 if (hc->complete_split) {
2364 hc_intr_mask.b.nyet = 1;
2366 hc_intr_mask.b.ack = 1;
2370 case DWC_OTG_EP_TYPE_ISOC:
2371 hc_intr_mask.b.xfercompl = 1;
2372 hc_intr_mask.b.frmovrun = 1;
2373 hc_intr_mask.b.ack = 1;
2376 hc_intr_mask.b.xacterr = 1;
2377 hc_intr_mask.b.bblerr = 1;
2382 DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2384 /* Enable the top level host channel interrupt. */
2385 intr_enable = (1 << hc_num);
2386 DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2388 /* Make sure host channel interrupts are enabled. */
2389 gintmsk.b.hcintr = 1;
2390 DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2393 * Program the HCCHARn register with the endpoint characteristics for
2394 * the current transfer.
2397 hcchar.b.devaddr = hc->dev_addr;
2398 hcchar.b.epnum = hc->ep_num;
2399 hcchar.b.epdir = hc->ep_is_in;
2400 hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2401 hcchar.b.eptype = hc->ep_type;
2402 hcchar.b.mps = hc->max_packet;
2404 DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2406 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2407 DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr);
2408 DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum);
2409 DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir);
2410 DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev);
2411 DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype);
2412 DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2413 DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt);
2416 * Program the HCSPLIT register for SPLITs
2420 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
2422 hc->complete_split ? "CSPLIT" : "SSPLIT");
2423 hcsplt.b.compsplt = hc->complete_split;
2424 hcsplt.b.xactpos = hc->xact_pos;
2425 hcsplt.b.hubaddr = hc->hub_addr;
2426 hcsplt.b.prtaddr = hc->port_addr;
2427 DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", hc->complete_split);
2428 DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", hc->xact_pos);
2429 DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", hc->hub_addr);
2430 DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", hc->port_addr);
2431 DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", hc->ep_is_in);
2432 DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps);
2433 DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", hc->xfer_len);
2435 DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2440 * Attempts to halt a host channel. This function should only be called in
2441 * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2442 * normal circumstances in DMA mode, the controller halts the channel when the
2443 * transfer is complete or a condition occurs that requires application
2446 * In slave mode, checks for a free request queue entry, then sets the Channel
2447 * Enable and Channel Disable bits of the Host Channel Characteristics
2448 * register of the specified channel to intiate the halt. If there is no free
2449 * request queue entry, sets only the Channel Disable bit of the HCCHARn
2450 * register to flush requests for this channel. In the latter case, sets a
2451 * flag to indicate that the host channel needs to be halted when a request
2452 * queue slot is open.
2454 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2455 * HCCHARn register. The controller ensures there is space in the request
2456 * queue before submitting the halt request.
2458 * Some time may elapse before the core flushes any posted requests for this
2459 * host channel and halts. The Channel Halted interrupt handler completes the
2460 * deactivation of the host channel.
2462 * @param core_if Controller register interface.
2463 * @param hc Host channel to halt.
2464 * @param halt_status Reason for halting the channel.
2466 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
2467 dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
2469 gnptxsts_data_t nptxsts;
2470 hptxsts_data_t hptxsts;
2471 hcchar_data_t hcchar;
2472 dwc_otg_hc_regs_t *hc_regs;
2473 dwc_otg_core_global_regs_t *global_regs;
2474 dwc_otg_host_global_regs_t *host_global_regs;
2476 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2477 global_regs = core_if->core_global_regs;
2478 host_global_regs = core_if->host_if->host_global_regs;
2480 DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
2481 "halt_status = %d\n", halt_status);
2483 if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2484 halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2486 * Disable all channel interrupts except Ch Halted. The QTD
2487 * and QH state associated with this transfer has been cleared
2488 * (in the case of URB_DEQUEUE), so the channel needs to be
2489 * shut down carefully to prevent crashes.
2491 hcintmsk_data_t hcintmsk;
2493 hcintmsk.b.chhltd = 1;
2494 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
2497 * Make sure no other interrupts besides halt are currently
2498 * pending. Handling another interrupt could cause a crash due
2499 * to the QTD and QH state.
2501 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
2504 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2505 * even if the channel was already halted for some other
2508 hc->halt_status = halt_status;
2510 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2511 if (hcchar.b.chen == 0) {
2513 * The channel is either already halted or it hasn't
2514 * started yet. In DMA mode, the transfer may halt if
2515 * it finishes normally or a condition occurs that
2516 * requires driver intervention. Don't want to halt
2517 * the channel again. In either Slave or DMA mode,
2518 * it's possible that the transfer has been assigned
2519 * to a channel, but not started yet when an URB is
2520 * dequeued. Don't want to halt a channel that hasn't
2526 if (hc->halt_pending) {
2528 * A halt has already been issued for this channel. This might
2529 * happen when a transfer is aborted by a higher level in
2534 ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2535 __func__, hc->hc_num);
2541 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2543 /* No need to set the bit in DDMA for disabling the channel */
2544 //TODO check it everywhere channel is disabled
2545 if (!core_if->core_params->dma_desc_enable)
2549 if (!core_if->dma_enable) {
2550 /* Check for space in the request queue to issue the halt. */
2551 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2552 hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2553 nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
2554 if (nptxsts.b.nptxqspcavail == 0) {
2559 DWC_READ_REG32(&host_global_regs->hptxsts);
2560 if ((hptxsts.b.ptxqspcavail == 0)
2561 || (core_if->queuing_high_bandwidth)) {
2566 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2568 hc->halt_status = halt_status;
2570 if (hcchar.b.chen) {
2571 hc->halt_pending = 1;
2572 hc->halt_on_queue = 0;
2574 hc->halt_on_queue = 1;
2577 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2578 DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32);
2579 DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", hc->halt_pending);
2580 DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", hc->halt_on_queue);
2581 DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", hc->halt_status);
2587 * Clears the transfer state for a host channel. This function is normally
2588 * called after a transfer is done and the host channel is being released.
2590 * @param core_if Programming view of DWC_otg controller.
2591 * @param hc Identifies the host channel to clean up.
2593 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2595 dwc_otg_hc_regs_t *hc_regs;
2597 hc->xfer_started = 0;
2600 * Clear channel interrupt enables and any unhandled channel interrupt
2603 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2604 DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
2605 DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
2607 DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
2612 * Sets the channel property that indicates in which frame a periodic transfer
2613 * should occur. This is always set to the _next_ frame. This function has no
2614 * effect on non-periodic transfers.
2616 * @param core_if Programming view of DWC_otg controller.
2617 * @param hc Identifies the host channel to set up and its properties.
2618 * @param hcchar Current value of the HCCHAR register for the specified host
2621 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
2622 dwc_hc_t * hc, hcchar_data_t * hcchar)
2624 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2625 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2628 DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
2630 /* 1 if _next_ frame is odd, 0 if it's even */
2631 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2633 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
2634 && !hc->complete_split) {
2635 switch (hfnum.b.frnum & 0x7) {
2637 core_if->hfnum_7_samples++;
2638 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2641 core_if->hfnum_0_samples++;
2642 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2645 core_if->hfnum_other_samples++;
2646 core_if->hfnum_other_frrem_accum +=
2656 void hc_xfer_timeout(void *ptr)
2658 hc_xfer_info_t *xfer_info = NULL;
2662 xfer_info = (hc_xfer_info_t *) ptr;
2664 if (!xfer_info->hc) {
2665 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
2669 hc_num = xfer_info->hc->hc_num;
2670 DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2671 DWC_WARN(" start_hcchar_val 0x%08x\n",
2672 xfer_info->core_if->start_hcchar_val[hc_num]);
2676 void ep_xfer_timeout(void *ptr)
2678 ep_xfer_info_t *xfer_info = NULL;
2680 dctl_data_t dctl = {.d32 = 0 };
2681 gintsts_data_t gintsts = {.d32 = 0 };
2682 gintmsk_data_t gintmsk = {.d32 = 0 };
2685 xfer_info = (ep_xfer_info_t *) ptr;
2687 if (!xfer_info->ep) {
2688 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
2692 ep_num = xfer_info->ep->num;
2693 DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
2694 /* Put the sate to 2 as it was time outed */
2695 xfer_info->state = 2;
2698 DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
2700 DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
2702 DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
2704 if (!gintmsk.b.goutnakeff) {
2706 gintmsk.b.goutnakeff = 1;
2707 DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
2712 if (!gintsts.b.goutnakeff) {
2713 dctl.b.sgoutnak = 1;
2715 DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
2720 void set_pid_isoc(dwc_hc_t * hc)
2722 /* Set up the initial PID for the transfer. */
2723 if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2725 if (hc->multi_count == 1) {
2726 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2727 } else if (hc->multi_count == 2) {
2728 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2730 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2733 if (hc->multi_count == 1) {
2734 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2736 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2740 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2745 * This function does the setup for a data transfer for a host channel and
2746 * starts the transfer. May be called in either Slave mode or DMA mode. In
2747 * Slave mode, the caller must ensure that there is sufficient space in the
2748 * request queue and Tx Data FIFO.
2750 * For an OUT transfer in Slave mode, it loads a data packet into the
2751 * appropriate FIFO. If necessary, additional data packets will be loaded in
2754 * For an IN transfer in Slave mode, a data packet is requested. The data
2755 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2756 * additional data packets are requested in the Host ISR.
2758 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2759 * register along with a packet count of 1 and the channel is enabled. This
2760 * causes a single PING transaction to occur. Other fields in HCTSIZ are
2761 * simply set to 0 since no data transfer occurs in this case.
2763 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2764 * all the information required to perform the subsequent data transfer. In
2765 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2766 * controller performs the entire PING protocol, then starts the data
2769 * @param core_if Programming view of DWC_otg controller.
2770 * @param hc Information needed to initialize the host channel. The xfer_len
2771 * value may be reduced to accommodate the max widths of the XferSize and
2772 * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2773 * to reflect the final xfer_len value.
2775 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2777 hcchar_data_t hcchar;
2778 hctsiz_data_t hctsiz;
2779 uint16_t num_packets;
2780 uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
2781 uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
2782 dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2787 if (!core_if->dma_enable) {
2788 dwc_otg_hc_do_ping(core_if, hc);
2789 hc->xfer_started = 1;
2799 if (hc->complete_split && !hc->ep_is_in) {
2800 /* For CSPLIT OUT Transfer, set the size to 0 so the
2801 * core doesn't expect any data written to the FIFO */
2803 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
2804 hc->xfer_len = hc->max_packet;
2805 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
2809 hctsiz.b.xfersize = hc->xfer_len;
2812 * Ensure that the transfer length and packet count will fit
2813 * in the widths allocated for them in the HCTSIZn register.
2815 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2816 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2818 * Make sure the transfer size is no larger than one
2819 * (micro)frame's worth of data. (A check was done
2820 * when the periodic transfer was accepted to ensure
2821 * that a (micro)frame's worth of data can be
2822 * programmed into a channel.)
2824 uint32_t max_periodic_len =
2825 hc->multi_count * hc->max_packet;
2826 if (hc->xfer_len > max_periodic_len) {
2827 hc->xfer_len = max_periodic_len;
2830 } else if (hc->xfer_len > max_hc_xfer_size) {
2831 /* Make sure that xfer_len is a multiple of max packet size. */
2832 hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
2835 if (hc->xfer_len > 0) {
2837 (hc->xfer_len + hc->max_packet -
2838 1) / hc->max_packet;
2839 if (num_packets > max_hc_pkt_count) {
2840 num_packets = max_hc_pkt_count;
2841 hc->xfer_len = num_packets * hc->max_packet;
2844 /* Need 1 packet for transfer length of 0. */
2849 /* Always program an integral # of max packets for IN transfers. */
2850 hc->xfer_len = num_packets * hc->max_packet;
2853 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2854 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2856 * Make sure that the multi_count field matches the
2857 * actual transfer length.
2859 hc->multi_count = num_packets;
2862 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2865 hctsiz.b.xfersize = hc->xfer_len;
2868 hc->start_pkt_count = num_packets;
2869 hctsiz.b.pktcnt = num_packets;
2870 hctsiz.b.pid = hc->data_pid_start;
2871 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2873 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2874 DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize);
2875 DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt);
2876 DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2878 if (core_if->dma_enable) {
2880 if (hc->align_buff) {
2881 dma_addr = hc->align_buff;
2883 dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
2885 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
2888 /* Start the split */
2890 hcsplt_data_t hcsplt;
2891 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
2892 hcsplt.b.spltena = 1;
2893 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
2896 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2897 hcchar.b.multicnt = hc->multi_count;
2898 hc_set_even_odd_frame(core_if, hc, &hcchar);
2900 core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2901 if (hcchar.b.chdis) {
2902 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2903 __func__, hc->hc_num, hcchar.d32);
2907 /* Set host channel enable after all other setup is complete. */
2910 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2912 hc->xfer_started = 1;
2915 if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
2916 /* Load OUT packet into the appropriate Tx FIFO. */
2917 dwc_otg_hc_write_packet(core_if, hc);
2920 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2921 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
2922 core_if->hc_xfer_info[hc->hc_num].hc = hc;
2924 /* Start a timer for this transfer. */
2925 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
2931 * This function does the setup for a data transfer for a host channel
2932 * and starts the transfer in Descriptor DMA mode.
2934 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
2935 * Sets PID and NTD values. For periodic transfers
2936 * initializes SCHED_INFO field with micro-frame bitmap.
2938 * Initializes HCDMA register with descriptor list address and CTD value
2939 * then starts the transfer via enabling the channel.
2941 * @param core_if Programming view of DWC_otg controller.
2942 * @param hc Information needed to initialize the host channel.
2944 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2946 dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2947 hcchar_data_t hcchar;
2948 hctsiz_data_t hctsiz;
2954 hctsiz.b_ddma.dopng = 1;
2956 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2959 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
2960 hctsiz.b_ddma.pid = hc->data_pid_start;
2961 hctsiz.b_ddma.ntd = hc->ntd - 1; /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
2962 hctsiz.b_ddma.schinfo = hc->schinfo; /* Non-zero only for high-speed interrupt endpoints */
2964 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2965 DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid);
2966 DWC_DEBUGPL(DBG_HCDV, " NTD: %d\n", hctsiz.b_ddma.ntd);
2968 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2971 hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
2973 /* Always start from first descriptor. */
2975 DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
2977 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2978 hcchar.b.multicnt = hc->multi_count;
2981 core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2982 if (hcchar.b.chdis) {
2983 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2984 __func__, hc->hc_num, hcchar.d32);
2988 /* Set host channel enable after all other setup is complete. */
2992 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2994 hc->xfer_started = 1;
2998 if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
2999 && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
3000 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3001 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3002 /* Start a timer for this transfer. */
3003 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3010 * This function continues a data transfer that was started by previous call
3011 * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
3012 * sufficient space in the request queue and Tx Data FIFO. This function
3013 * should only be called in Slave mode. In DMA mode, the controller acts
3014 * autonomously to complete transfers programmed to a host channel.
3016 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
3017 * if there is any data remaining to be queued. For an IN transfer, another
3018 * data packet is always requested. For the SETUP phase of a control transfer,
3019 * this function does nothing.
3021 * @return 1 if a new request is queued, 0 if no more requests are required
3022 * for this transfer.
3024 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3026 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3029 /* SPLITs always queue just once per channel */
3031 } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3032 /* SETUPs are queued only once since they can't be NAKed. */
3034 } else if (hc->ep_is_in) {
3036 * Always queue another request for other IN transfers. If
3037 * back-to-back INs are issued and NAKs are received for both,
3038 * the driver may still be processing the first NAK when the
3039 * second NAK is received. When the interrupt handler clears
3040 * the NAK interrupt for the first NAK, the second NAK will
3041 * not be seen. So we can't depend on the NAK interrupt
3042 * handler to requeue a NAKed request. Instead, IN requests
3043 * are issued each time this function is called. When the
3044 * transfer completes, the extra requests for the channel will
3047 hcchar_data_t hcchar;
3048 dwc_otg_hc_regs_t *hc_regs =
3049 core_if->host_if->hc_regs[hc->hc_num];
3051 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3052 hc_set_even_odd_frame(core_if, hc, &hcchar);
3055 DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n",
3057 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3061 /* OUT transfers. */
3062 if (hc->xfer_count < hc->xfer_len) {
3063 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3064 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3065 hcchar_data_t hcchar;
3066 dwc_otg_hc_regs_t *hc_regs;
3067 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3068 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3069 hc_set_even_odd_frame(core_if, hc, &hcchar);
3072 /* Load OUT packet into the appropriate Tx FIFO. */
3073 dwc_otg_hc_write_packet(core_if, hc);
3083 * Starts a PING transfer. This function should only be called in Slave mode.
3084 * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
3086 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3088 hcchar_data_t hcchar;
3089 hctsiz_data_t hctsiz;
3090 dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3092 DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3096 hctsiz.b.pktcnt = 1;
3097 DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3099 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3102 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3106 * This function writes a packet into the Tx FIFO associated with the Host
3107 * Channel. For a channel associated with a non-periodic EP, the non-periodic
3108 * Tx FIFO is written. For a channel associated with a periodic EP, the
3109 * periodic Tx FIFO is written. This function should only be called in Slave
3112 * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
3113 * then number of bytes written to the Tx FIFO.
3115 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3118 uint32_t remaining_count;
3119 uint32_t byte_count;
3120 uint32_t dword_count;
3122 uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
3123 uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
3125 remaining_count = hc->xfer_len - hc->xfer_count;
3126 if (remaining_count > hc->max_packet) {
3127 byte_count = hc->max_packet;
3129 byte_count = remaining_count;
3132 dword_count = (byte_count + 3) / 4;
3134 if ((((unsigned long)data_buff) & 0x3) == 0) {
3135 /* xfer_buff is DWORD aligned. */
3136 for (i = 0; i < dword_count; i++, data_buff++) {
3137 DWC_WRITE_REG32(data_fifo, *data_buff);
3140 /* xfer_buff is not DWORD aligned. */
3141 for (i = 0; i < dword_count; i++, data_buff++) {
3144 (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
3145 16 | data_buff[3] << 24);
3146 DWC_WRITE_REG32(data_fifo, data);
3150 hc->xfer_count += byte_count;
3151 hc->xfer_buff += byte_count;
3155 * Gets the current USB frame number. This is the frame number from the last
3158 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
3161 dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
3163 /* read current frame/microframe number from DSTS register */
3164 return dsts.b.soffn;
3168 * Calculates and gets the frame Interval value of HFIR register according PHY
3169 * type and speed.The application can modify a value of HFIR register only after
3170 * the Port Enable bit of the Host Port Control and Status register
3171 * (HPRT.PrtEnaPort) has been set.
3174 uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
3176 gusbcfg_data_t usbcfg;
3177 hwcfg2_data_t hwcfg2;
3179 int clock = 60; // default value
3180 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
3181 hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
3182 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
3183 if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3185 if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
3187 if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3188 !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3190 if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3191 !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3193 if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3194 !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3196 if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
3198 if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
3200 if (hprt0.b.prtspd == 0)
3201 /* High speed case */
3205 return 1000 * clock;
3209 * This function reads a setup packet from the Rx FIFO into the destination
3210 * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3211 * Interrupt routine when a SETUP packet has been received in Slave mode.
3213 * @param core_if Programming view of DWC_otg controller.
3214 * @param dest Destination buffer for packet data.
3216 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
3218 device_grxsts_data_t status;
3219 /* Get the 8 bytes of a setup transaction data */
3221 /* Pop 2 DWORDS off the receive data FIFO into memory */
3222 dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
3223 dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
3224 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
3226 DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
3227 DWC_DEBUGPL(DBG_ANY,
3228 "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
3229 status.b.epnum, status.b.bcnt, status.b.pktsts,
3230 status.b.fn, status.b.fn);
3235 * This function enables EP0 OUT to receive SETUP packets and configures EP0
3236 * IN for transmitting packets. It is normally called when the
3237 * "Enumeration Done" interrupt occurs.
3239 * @param core_if Programming view of DWC_otg controller.
3240 * @param ep The EP0 data.
3242 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3244 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3246 depctl_data_t diepctl;
3247 depctl_data_t doepctl;
3248 dctl_data_t dctl = {.d32 = 0 };
3250 ep->stp_rollover = 0;
3251 /* Read the Device Status and Endpoint 0 Control registers */
3252 dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
3253 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
3254 doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
3256 /* Set the MPS of the IN EP based on the enumeration speed */
3257 switch (dsts.b.enumspd) {
3258 case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3259 case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3260 case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3261 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3263 case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3264 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3268 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3270 /* Enable OUT EP for receive */
3271 if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
3272 doepctl.b.epena = 1;
3273 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3276 DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
3277 DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
3278 DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
3279 DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
3281 dctl.b.cgnpinnak = 1;
3283 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3284 DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
3285 DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
3290 * This function activates an EP. The Device EP control register for
3291 * the EP is configured as defined in the ep structure. Note: This
3292 * function is not used for EP0.
3294 * @param core_if Programming view of DWC_otg controller.
3295 * @param ep The EP to activate.
3297 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3299 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3300 depctl_data_t depctl;
3301 volatile uint32_t *addr;
3302 daint_data_t daintmsk = {.d32 = 0 };
3306 DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3307 (ep->is_in ? "IN" : "OUT"));
3309 #ifdef DWC_UTE_PER_IO
3310 ep->xiso_frame_num = 0xFFFFFFFF;
3311 ep->xiso_active_xfers = 0;
3312 ep->xiso_queued_xfers = 0;
3314 /* Read DEPCTLn register */
3315 if (ep->is_in == 1) {
3316 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3317 daintmsk.ep.in = 1 << ep->num;
3319 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3320 daintmsk.ep.out = 1 << ep->num;
3323 /* If the EP is already active don't change the EP Control
3325 depctl.d32 = DWC_READ_REG32(addr);
3326 if (!depctl.b.usbactep) {
3327 depctl.b.mps = ep->maxpacket;
3328 depctl.b.eptype = ep->type;
3329 depctl.b.txfnum = ep->tx_fifo_num;
3331 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3332 depctl.b.setd0pid = 1; // ???
3334 depctl.b.setd0pid = 1;
3336 depctl.b.usbactep = 1;
3338 /* Update nextep_seq array and EPMSCNT in DCFG */
3339 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) { // NP IN EP
3340 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3341 if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
3344 core_if->nextep_seq[i] = ep->num;
3345 core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
3346 depctl.b.nextep = core_if->nextep_seq[ep->num];
3347 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
3349 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
3351 DWC_DEBUGPL(DBG_PCDV,
3352 "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3353 __func__, core_if->first_in_nextep_seq);
3354 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3355 DWC_DEBUGPL(DBG_PCDV, "%2d\n",
3356 core_if->nextep_seq[i]);
3362 DWC_WRITE_REG32(addr, depctl.d32);
3363 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
3366 /* Enable the Interrupt for this EP */
3367 if (core_if->multiproc_int_enable) {
3368 if (ep->is_in == 1) {
3369 diepmsk_data_t diepmsk = {.d32 = 0 };
3370 diepmsk.b.xfercompl = 1;
3371 diepmsk.b.timeout = 1;
3372 diepmsk.b.epdisabled = 1;
3373 diepmsk.b.ahberr = 1;
3374 diepmsk.b.intknepmis = 1;
3375 if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
3376 diepmsk.b.intknepmis = 0;
3377 diepmsk.b.txfifoundrn = 1; //?????
3378 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3383 if (core_if->dma_desc_enable) {
3388 if (core_if->dma_enable) {
3392 DWC_WRITE_REG32(&dev_if->dev_global_regs->
3393 diepeachintmsk[ep->num], diepmsk.d32);
3396 doepmsk_data_t doepmsk = {.d32 = 0 };
3397 doepmsk.b.xfercompl = 1;
3398 doepmsk.b.ahberr = 1;
3399 doepmsk.b.epdisabled = 1;
3400 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3401 doepmsk.b.outtknepdis = 1;
3405 if (core_if->dma_desc_enable) {
3410 doepmsk.b.babble = 1;
3414 DWC_WRITE_REG32(&dev_if->dev_global_regs->
3415 doepeachintmsk[ep->num], doepmsk.d32);
3417 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
3420 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3422 diepmsk_data_t diepmsk = {.d32 = 0 };
3424 DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
3426 doepmsk_data_t doepmsk = {.d32 = 0 };
3427 doepmsk.b.outtknepdis = 1;
3428 DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
3431 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
3435 DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
3436 DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
3438 ep->stall_clear_flag = 0;
3444 * This function deactivates an EP. This is done by clearing the USB Active
3445 * EP bit in the Device EP control register. Note: This function is not used
3446 * for EP0. EP0 cannot be deactivated.
3448 * @param core_if Programming view of DWC_otg controller.
3449 * @param ep The EP to deactivate.
3451 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3453 depctl_data_t depctl = {.d32 = 0 };
3454 volatile uint32_t *addr;
3455 daint_data_t daintmsk = {.d32 = 0 };
3459 #ifdef DWC_UTE_PER_IO
3460 ep->xiso_frame_num = 0xFFFFFFFF;
3461 ep->xiso_active_xfers = 0;
3462 ep->xiso_queued_xfers = 0;
3465 /* Read DEPCTLn register */
3466 if (ep->is_in == 1) {
3467 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3468 daintmsk.ep.in = 1 << ep->num;
3470 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3471 daintmsk.ep.out = 1 << ep->num;
3474 depctl.d32 = DWC_READ_REG32(addr);
3476 depctl.b.usbactep = 0;
3478 /* Update nextep_seq array and EPMSCNT in DCFG */
3479 if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
3480 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3481 if (core_if->nextep_seq[i] == ep->num)
3484 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
3485 if (core_if->first_in_nextep_seq == ep->num)
3486 core_if->first_in_nextep_seq = i;
3487 core_if->nextep_seq[ep->num] = 0xff;
3488 depctl.b.nextep = 0;
3490 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
3492 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
3495 DWC_DEBUGPL(DBG_PCDV,
3496 "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3497 __func__, core_if->first_in_nextep_seq);
3498 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3499 DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
3504 depctl.b.txfnum = 0;
3506 if (core_if->dma_desc_enable)
3509 DWC_WRITE_REG32(addr, depctl.d32);
3510 depctl.d32 = DWC_READ_REG32(addr);
3511 if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
3512 && depctl.b.epena) {
3513 depctl_data_t depctl = {.d32 = 0 };
3515 diepint_data_t diepint = {.d32 = 0 };
3518 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3519 diepctl, depctl.d32);
3523 DWC_READ_REG32(&core_if->
3524 dev_if->in_ep_regs[ep->num]->
3526 } while (!diepint.b.inepnakeff);
3527 diepint.b.inepnakeff = 1;
3528 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3529 diepint, diepint.d32);
3532 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3533 diepctl, depctl.d32);
3537 DWC_READ_REG32(&core_if->
3538 dev_if->in_ep_regs[ep->num]->
3540 } while (!diepint.b.epdisabled);
3541 diepint.b.epdisabled = 1;
3542 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3543 diepint, diepint.d32);
3545 dctl_data_t dctl = {.d32 = 0};
3546 gintmsk_data_t gintsts = {.d32 = 0};
3547 doepint_data_t doepint = {.d32 = 0};
3548 dctl.b.sgoutnak = 1;
3549 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3553 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
3554 } while (!gintsts.b.goutnakeff);
3556 gintsts.b.goutnakeff = 1;
3557 DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
3562 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
3566 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
3567 out_ep_regs[ep->num]->doepint);
3568 } while (!doepint.b.epdisabled);
3570 doepint.b.epdisabled = 1;
3571 DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
3574 dctl.b.cgoutnak = 1;
3575 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
3579 /* Disable the Interrupt for this EP */
3580 if (core_if->multiproc_int_enable) {
3581 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
3584 if (ep->is_in == 1) {
3585 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
3586 diepeachintmsk[ep->num], 0);
3588 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
3589 doepeachintmsk[ep->num], 0);
3592 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
3599 * This function initializes dma descriptor chain.
3601 * @param core_if Programming view of DWC_otg controller.
3602 * @param ep The EP to start the transfer on.
3604 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3606 dwc_otg_dev_dma_desc_t *dma_desc;
3610 unsigned maxxfer_local, total_len;
3612 if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
3613 (ep->maxpacket % 4)) {
3614 maxxfer_local = ep->maxpacket;
3615 total_len = ep->xfer_len;
3617 maxxfer_local = ep->maxxfer;
3618 total_len = ep->total_len;
3621 ep->desc_cnt = (total_len / maxxfer_local) +
3622 ((total_len % maxxfer_local) ? 1 : 0);
3627 if (ep->desc_cnt > MAX_DMA_DESC_CNT)
3628 ep->desc_cnt = MAX_DMA_DESC_CNT;
3630 dma_desc = ep->desc_addr;
3631 if (maxxfer_local == ep->maxpacket) {
3632 if ((total_len % maxxfer_local) &&
3633 (total_len / maxxfer_local < MAX_DMA_DESC_CNT)) {
3634 xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
3635 (total_len % maxxfer_local);
3637 xfer_est = ep->desc_cnt * maxxfer_local;
3639 xfer_est = total_len;
3641 for (i = 0; i < ep->desc_cnt; ++i) {
3642 /** DMA Descriptor Setup */
3643 if (xfer_est > maxxfer_local) {
3644 dma_desc->status.b.bs = BS_HOST_BUSY;
3645 dma_desc->status.b.l = 0;
3646 dma_desc->status.b.ioc = 0;
3647 dma_desc->status.b.sp = 0;
3648 dma_desc->status.b.bytes = maxxfer_local;
3649 dma_desc->buf = ep->dma_addr + offset;
3650 dma_desc->status.b.sts = 0;
3651 dma_desc->status.b.bs = BS_HOST_READY;
3653 xfer_est -= maxxfer_local;
3654 offset += maxxfer_local;
3656 dma_desc->status.b.bs = BS_HOST_BUSY;
3657 dma_desc->status.b.l = 1;
3658 dma_desc->status.b.ioc = 1;
3660 dma_desc->status.b.sp =
3662 ep->maxpacket) ? 1 : ((ep->
3664 dma_desc->status.b.bytes = xfer_est;
3666 if (maxxfer_local == ep->maxpacket)
3667 dma_desc->status.b.bytes = xfer_est;
3669 dma_desc->status.b.bytes =
3670 xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
3673 dma_desc->buf = ep->dma_addr + offset;
3674 dma_desc->status.b.sts = 0;
3675 dma_desc->status.b.bs = BS_HOST_READY;
3682 * This function is called when to write ISOC data into appropriate dedicated
3685 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
3687 dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3688 dwc_otg_dev_in_ep_regs_t *ep_regs;
3689 dtxfsts_data_t txstatus = {.d32 = 0 };
3691 int epnum = dwc_ep->num;
3694 DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
3696 ep_regs = core_if->dev_if->in_ep_regs[epnum];
3698 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
3700 if (len > dwc_ep->maxpacket) {
3701 len = dwc_ep->maxpacket;
3704 dwords = (len + 3) / 4;
3706 /* While there is space in the queue and space in the FIFO and
3707 * More data to tranfer, Write packets to the Tx FIFO */
3708 txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
3709 DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
3711 while (txstatus.b.txfspcavail > dwords &&
3712 dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
3713 /* Write the FIFO */
3714 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
3716 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
3717 if (len > dwc_ep->maxpacket) {
3718 len = dwc_ep->maxpacket;
3721 dwords = (len + 3) / 4;
3723 DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
3724 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
3728 DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
3729 DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
3735 * This function does the setup for a data transfer for an EP and
3736 * starts the transfer. For an IN transfer, the packets will be
3737 * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3738 * the packets are unloaded from the Rx FIFO in the ISR. the ISR.
3740 * @param core_if Programming view of DWC_otg controller.
3741 * @param ep The EP to start the transfer on.
3744 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3746 depctl_data_t depctl;
3747 deptsiz_data_t deptsiz;
3748 gintmsk_data_t intr_mask = {.d32 = 0 };
3750 DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3751 DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3752 "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
3753 ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
3754 ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
3757 if (ep->is_in == 1) {
3758 dwc_otg_dev_in_ep_regs_t *in_regs =
3759 core_if->dev_if->in_ep_regs[ep->num];
3761 gnptxsts_data_t gtxstatus;
3764 DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
3766 if (core_if->en_multiple_tx_fifo == 0
3767 && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
3769 DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3774 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
3775 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
3777 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
3778 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3779 ep->maxxfer : (ep->total_len - ep->xfer_len);
3781 ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
3782 MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
3785 /* Zero Length Packet? */
3786 if ((ep->xfer_len - ep->xfer_count) == 0) {
3787 deptsiz.b.xfersize = 0;
3788 deptsiz.b.pktcnt = 1;
3790 /* Program the transfer size and packet count
3791 * as follows: xfersize = N * maxpacket +
3792 * short_packet pktcnt = N + (short_packet
3795 deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3797 (ep->xfer_len - ep->xfer_count - 1 +
3798 ep->maxpacket) / ep->maxpacket;
3799 if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
3800 deptsiz.b.pktcnt = MAX_PKT_CNT;
3801 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
3803 if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3804 deptsiz.b.mc = deptsiz.b.pktcnt;
3807 /* Write the DMA register */
3808 if (core_if->dma_enable) {
3809 if (core_if->dma_desc_enable == 0) {
3810 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
3812 DWC_WRITE_REG32(&in_regs->dieptsiz,
3814 DWC_WRITE_REG32(&(in_regs->diepdma),
3815 (uint32_t) ep->dma_addr);
3818 /* The descriptor chain should be already initialized by now */
3819 if (ep->buff_mode != BM_STANDARD) {
3820 DWC_WRITE_REG32(&in_regs->diepdma,
3821 ep->descs_dma_addr);
3824 init_dma_desc_chain(core_if, ep);
3825 /** DIEPDMAn Register write */
3826 DWC_WRITE_REG32(&in_regs->diepdma,
3833 DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
3834 if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
3836 * Enable the Non-Periodic Tx FIFO empty interrupt,
3837 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3838 * the data will be written into the fifo by the ISR.
3840 if (core_if->en_multiple_tx_fifo == 0) {
3841 intr_mask.b.nptxfempty = 1;
3843 (&core_if->core_global_regs->gintmsk,
3844 intr_mask.d32, intr_mask.d32);
3846 /* Enable the Tx FIFO Empty Interrupt for this EP */
3847 if (ep->xfer_len > 0) {
3848 uint32_t fifoemptymsk = 0;
3849 fifoemptymsk = 1 << ep->num;
3851 (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3857 write_isoc_tx_fifo(core_if, ep);
3860 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
3861 depctl.b.nextep = core_if->nextep_seq[ep->num];
3863 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3864 dsts_data_t dsts = {.d32 = 0 };
3865 if (ep->bInterval == 1) {
3867 DWC_READ_REG32(&core_if->dev_if->
3868 dev_global_regs->dsts);
3869 ep->frame_num = dsts.b.soffn + ep->bInterval;
3870 if (ep->frame_num > 0x3FFF) {
3871 ep->frm_overrun = 1;
3872 ep->frame_num &= 0x3FFF;
3874 ep->frm_overrun = 0;
3875 if (ep->frame_num & 0x1) {
3876 depctl.b.setd1pid = 1;
3878 depctl.b.setd0pid = 1;
3882 /* EP enable, IN data in FIFO */
3885 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
3889 dwc_otg_dev_out_ep_regs_t *out_regs =
3890 core_if->dev_if->out_ep_regs[ep->num];
3892 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
3893 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
3895 if (!core_if->dma_desc_enable) {
3896 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
3897 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3898 ep->maxxfer : (ep->total_len - ep->xfer_len);
3900 ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
3901 - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
3904 /* Program the transfer size and packet count as follows:
3907 * xfersize = N * maxpacket
3909 if ((ep->xfer_len - ep->xfer_count) == 0) {
3910 /* Zero Length Packet */
3911 deptsiz.b.xfersize = ep->maxpacket;
3912 deptsiz.b.pktcnt = 1;
3915 (ep->xfer_len - ep->xfer_count +
3916 (ep->maxpacket - 1)) / ep->maxpacket;
3917 if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
3918 deptsiz.b.pktcnt = MAX_PKT_CNT;
3920 if (!core_if->dma_desc_enable) {
3922 deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
3924 deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3927 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3928 ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
3930 if (core_if->dma_enable) {
3931 if (!core_if->dma_desc_enable) {
3932 DWC_WRITE_REG32(&out_regs->doeptsiz,
3935 DWC_WRITE_REG32(&(out_regs->doepdma),
3936 (uint32_t) ep->dma_addr);
3939 /* The descriptor chain should be already initialized by now */
3940 if (ep->buff_mode != BM_STANDARD) {
3941 DWC_WRITE_REG32(&out_regs->doepdma,
3942 ep->descs_dma_addr);
3945 /** This is used for interrupt out transfers*/
3947 ep->xfer_len = ep->total_len;
3948 init_dma_desc_chain(core_if, ep);
3950 if (core_if->core_params->dev_out_nak) {
3951 if (ep->type == DWC_OTG_EP_TYPE_BULK) {
3952 deptsiz.b.pktcnt = (ep->total_len +
3953 (ep->maxpacket - 1)) / ep->maxpacket;
3954 deptsiz.b.xfersize = ep->total_len;
3955 /* Remember initial value of doeptsiz */
3956 core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
3957 DWC_WRITE_REG32(&out_regs->doeptsiz,
3961 /** DOEPDMAn Register write */
3962 DWC_WRITE_REG32(&out_regs->doepdma,
3969 DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
3972 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3973 dsts_data_t dsts = {.d32 = 0 };
3974 if (ep->bInterval == 1) {
3976 DWC_READ_REG32(&core_if->dev_if->
3977 dev_global_regs->dsts);
3978 ep->frame_num = dsts.b.soffn + ep->bInterval;
3979 if (ep->frame_num > 0x3FFF) {
3980 ep->frm_overrun = 1;
3981 ep->frame_num &= 0x3FFF;
3983 ep->frm_overrun = 0;
3985 if (ep->frame_num & 0x1) {
3986 depctl.b.setd1pid = 1;
3988 depctl.b.setd0pid = 1;
3997 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
3999 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
4000 DWC_READ_REG32(&out_regs->doepctl),
4001 DWC_READ_REG32(&out_regs->doeptsiz));
4002 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
4003 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
4005 DWC_READ_REG32(&core_if->core_global_regs->
4008 /* Timer is scheduling only for out bulk transfers for
4009 * "Device DDMA OUT NAK Enhancement" feature to inform user
4010 * about received data payload in case of timeout
4012 if (core_if->core_params->dev_out_nak) {
4013 if (ep->type == DWC_OTG_EP_TYPE_BULK) {
4014 core_if->ep_xfer_info[ep->num].core_if = core_if;
4015 core_if->ep_xfer_info[ep->num].ep = ep;
4016 core_if->ep_xfer_info[ep->num].state = 1;
4018 /* Start a timer for this transfer. */
4019 DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
4026 * This function setup a zero length transfer in Buffer DMA and
4027 * Slave modes for usb requests with zero field set
4029 * @param core_if Programming view of DWC_otg controller.
4030 * @param ep The EP to start the transfer on.
4033 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4036 depctl_data_t depctl;
4037 deptsiz_data_t deptsiz;
4038 gintmsk_data_t intr_mask = {.d32 = 0 };
4040 DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4041 DWC_PRINTF("zero length transfer is called\n");
4044 if (ep->is_in == 1) {
4045 dwc_otg_dev_in_ep_regs_t *in_regs =
4046 core_if->dev_if->in_ep_regs[ep->num];
4048 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4049 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4051 deptsiz.b.xfersize = 0;
4052 deptsiz.b.pktcnt = 1;
4054 /* Write the DMA register */
4055 if (core_if->dma_enable) {
4056 if (core_if->dma_desc_enable == 0) {
4058 DWC_WRITE_REG32(&in_regs->dieptsiz,
4060 DWC_WRITE_REG32(&(in_regs->diepdma),
4061 (uint32_t) ep->dma_addr);
4064 DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4066 * Enable the Non-Periodic Tx FIFO empty interrupt,
4067 * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4068 * the data will be written into the fifo by the ISR.
4070 if (core_if->en_multiple_tx_fifo == 0) {
4071 intr_mask.b.nptxfempty = 1;
4072 DWC_MODIFY_REG32(&core_if->
4073 core_global_regs->gintmsk,
4074 intr_mask.d32, intr_mask.d32);
4076 /* Enable the Tx FIFO Empty Interrupt for this EP */
4077 if (ep->xfer_len > 0) {
4078 uint32_t fifoemptymsk = 0;
4079 fifoemptymsk = 1 << ep->num;
4080 DWC_MODIFY_REG32(&core_if->
4081 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4087 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4088 depctl.b.nextep = core_if->nextep_seq[ep->num];
4089 /* EP enable, IN data in FIFO */
4092 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4096 dwc_otg_dev_out_ep_regs_t *out_regs =
4097 core_if->dev_if->out_ep_regs[ep->num];
4099 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4100 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4102 /* Zero Length Packet */
4103 deptsiz.b.xfersize = ep->maxpacket;
4104 deptsiz.b.pktcnt = 1;
4106 if (core_if->dma_enable) {
4107 if (!core_if->dma_desc_enable) {
4108 DWC_WRITE_REG32(&out_regs->doeptsiz,
4111 DWC_WRITE_REG32(&(out_regs->doepdma),
4112 (uint32_t) ep->dma_addr);
4115 DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4122 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4128 * This function does the setup for a data transfer for EP0 and starts
4129 * the transfer. For an IN transfer, the packets will be loaded into
4130 * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
4131 * unloaded from the Rx FIFO in the ISR.
4133 * @param core_if Programming view of DWC_otg controller.
4134 * @param ep The EP0 data.
4136 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4138 depctl_data_t depctl;
4139 deptsiz0_data_t deptsiz;
4140 gintmsk_data_t intr_mask = {.d32 = 0 };
4141 dwc_otg_dev_dma_desc_t *dma_desc;
4143 DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4144 "xfer_buff=%p start_xfer_buff=%p \n",
4145 ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4146 ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
4148 ep->total_len = ep->xfer_len;
4151 if (ep->is_in == 1) {
4152 dwc_otg_dev_in_ep_regs_t *in_regs =
4153 core_if->dev_if->in_ep_regs[0];
4155 gnptxsts_data_t gtxstatus;
4157 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4158 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4164 DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4166 /* If dedicated FIFO every time flush fifo before enable ep*/
4167 if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
4168 dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
4170 if (core_if->en_multiple_tx_fifo == 0
4171 && gtxstatus.b.nptxqspcavail == 0
4172 && !core_if->dma_enable) {
4174 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4175 DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
4176 DWC_READ_REG32(&in_regs->diepctl));
4177 DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
4179 deptsiz.b.xfersize, deptsiz.b.pktcnt);
4180 DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
4186 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4187 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4189 /* Zero Length Packet? */
4190 if (ep->xfer_len == 0) {
4191 deptsiz.b.xfersize = 0;
4192 deptsiz.b.pktcnt = 1;
4194 /* Program the transfer size and packet count
4195 * as follows: xfersize = N * maxpacket +
4196 * short_packet pktcnt = N + (short_packet
4199 if (ep->xfer_len > ep->maxpacket) {
4200 ep->xfer_len = ep->maxpacket;
4201 deptsiz.b.xfersize = ep->maxpacket;
4203 deptsiz.b.xfersize = ep->xfer_len;
4205 deptsiz.b.pktcnt = 1;
4208 DWC_DEBUGPL(DBG_PCDV,
4209 "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4210 ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4213 /* Write the DMA register */
4214 if (core_if->dma_enable) {
4215 if (core_if->dma_desc_enable == 0) {
4216 DWC_WRITE_REG32(&in_regs->dieptsiz,
4219 DWC_WRITE_REG32(&(in_regs->diepdma),
4220 (uint32_t) ep->dma_addr);
4222 dma_desc = core_if->dev_if->in_desc_addr;
4224 /** DMA Descriptor Setup */
4225 dma_desc->status.b.bs = BS_HOST_BUSY;
4226 dma_desc->status.b.l = 1;
4227 dma_desc->status.b.ioc = 1;
4228 dma_desc->status.b.sp =
4229 (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4230 dma_desc->status.b.bytes = ep->xfer_len;
4231 dma_desc->buf = ep->dma_addr;
4232 dma_desc->status.b.sts = 0;
4233 dma_desc->status.b.bs = BS_HOST_READY;
4235 /** DIEPDMA0 Register write */
4236 DWC_WRITE_REG32(&in_regs->diepdma,
4238 dev_if->dma_in_desc_addr);
4241 DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4244 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4245 depctl.b.nextep = core_if->nextep_seq[ep->num];
4246 /* EP enable, IN data in FIFO */
4249 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4252 * Enable the Non-Periodic Tx FIFO empty interrupt, the
4253 * data will be written into the fifo by the ISR.
4255 if (!core_if->dma_enable) {
4256 if (core_if->en_multiple_tx_fifo == 0) {
4257 intr_mask.b.nptxfempty = 1;
4258 DWC_MODIFY_REG32(&core_if->
4259 core_global_regs->gintmsk,
4260 intr_mask.d32, intr_mask.d32);
4262 /* Enable the Tx FIFO Empty Interrupt for this EP */
4263 if (ep->xfer_len > 0) {
4264 uint32_t fifoemptymsk = 0;
4265 fifoemptymsk |= 1 << ep->num;
4266 DWC_MODIFY_REG32(&core_if->
4267 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4274 dwc_otg_dev_out_ep_regs_t *out_regs =
4275 core_if->dev_if->out_ep_regs[0];
4277 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4278 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4280 /* Program the transfer size and packet count as follows:
4281 * xfersize = N * (maxpacket + 4 - (maxpacket % 4))
4283 /* Zero Length Packet */
4284 deptsiz.b.xfersize = ep->maxpacket;
4285 deptsiz.b.pktcnt = 1;
4286 if (core_if->snpsid >= OTG_CORE_REV_3_00a)
4287 deptsiz.b.supcnt = 3;
4289 DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n",
4290 ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4292 if (core_if->dma_enable) {
4293 if (!core_if->dma_desc_enable) {
4294 DWC_WRITE_REG32(&out_regs->doeptsiz,
4297 DWC_WRITE_REG32(&(out_regs->doepdma),
4298 (uint32_t) ep->dma_addr);
4300 dma_desc = core_if->dev_if->out_desc_addr;
4302 /** DMA Descriptor Setup */
4303 dma_desc->status.b.bs = BS_HOST_BUSY;
4304 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4305 dma_desc->status.b.mtrf = 0;
4306 dma_desc->status.b.sr = 0;
4308 dma_desc->status.b.l = 1;
4309 dma_desc->status.b.ioc = 1;
4310 dma_desc->status.b.bytes = ep->maxpacket;
4311 dma_desc->buf = ep->dma_addr;
4312 dma_desc->status.b.sts = 0;
4313 dma_desc->status.b.bs = BS_HOST_READY;
4315 /** DOEPDMA0 Register write */
4316 DWC_WRITE_REG32(&out_regs->doepdma,
4321 DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4327 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
4332 * This function continues control IN transfers started by
4333 * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
4334 * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
4335 * bit for the packet count.
4337 * @param core_if Programming view of DWC_otg controller.
4338 * @param ep The EP0 data.
4340 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4342 depctl_data_t depctl;
4343 deptsiz0_data_t deptsiz;
4344 gintmsk_data_t intr_mask = {.d32 = 0 };
4345 dwc_otg_dev_dma_desc_t *dma_desc;
4347 if (ep->is_in == 1) {
4348 dwc_otg_dev_in_ep_regs_t *in_regs =
4349 core_if->dev_if->in_ep_regs[0];
4350 gnptxsts_data_t tx_status = {.d32 = 0 };
4353 DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4354 /** @todo Should there be check for room in the Tx
4355 * Status Queue. If not remove the code above this comment. */
4357 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4358 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4360 /* Program the transfer size and packet count
4361 * as follows: xfersize = N * maxpacket +
4362 * short_packet pktcnt = N + (short_packet
4366 if (core_if->dma_desc_enable == 0) {
4367 deptsiz.b.xfersize =
4368 (ep->total_len - ep->xfer_count) >
4369 ep->maxpacket ? ep->maxpacket : (ep->total_len -
4371 deptsiz.b.pktcnt = 1;
4372 if (core_if->dma_enable == 0) {
4373 ep->xfer_len += deptsiz.b.xfersize;
4375 ep->xfer_len = deptsiz.b.xfersize;
4377 DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4380 (ep->total_len - ep->xfer_count) >
4381 ep->maxpacket ? ep->maxpacket : (ep->total_len -
4384 dma_desc = core_if->dev_if->in_desc_addr;
4386 /** DMA Descriptor Setup */
4387 dma_desc->status.b.bs = BS_HOST_BUSY;
4388 dma_desc->status.b.l = 1;
4389 dma_desc->status.b.ioc = 1;
4390 dma_desc->status.b.sp =
4391 (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4392 dma_desc->status.b.bytes = ep->xfer_len;
4393 dma_desc->buf = ep->dma_addr;
4394 dma_desc->status.b.sts = 0;
4395 dma_desc->status.b.bs = BS_HOST_READY;
4397 /** DIEPDMA0 Register write */
4398 DWC_WRITE_REG32(&in_regs->diepdma,
4399 core_if->dev_if->dma_in_desc_addr);
4402 DWC_DEBUGPL(DBG_PCDV,
4403 "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4404 ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4407 /* Write the DMA register */
4408 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4409 if (core_if->dma_desc_enable == 0)
4410 DWC_WRITE_REG32(&(in_regs->diepdma),
4411 (uint32_t) ep->dma_addr);
4413 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4414 depctl.b.nextep = core_if->nextep_seq[ep->num];
4415 /* EP enable, IN data in FIFO */
4418 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4421 * Enable the Non-Periodic Tx FIFO empty interrupt, the
4422 * data will be written into the fifo by the ISR.
4424 if (!core_if->dma_enable) {
4425 if (core_if->en_multiple_tx_fifo == 0) {
4426 /* First clear it from GINTSTS */
4427 intr_mask.b.nptxfempty = 1;
4428 DWC_MODIFY_REG32(&core_if->
4429 core_global_regs->gintmsk,
4430 intr_mask.d32, intr_mask.d32);
4433 /* Enable the Tx FIFO Empty Interrupt for this EP */
4434 if (ep->xfer_len > 0) {
4435 uint32_t fifoemptymsk = 0;
4436 fifoemptymsk |= 1 << ep->num;
4437 DWC_MODIFY_REG32(&core_if->
4438 dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4444 dwc_otg_dev_out_ep_regs_t *out_regs =
4445 core_if->dev_if->out_ep_regs[0];
4447 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4448 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4450 /* Program the transfer size and packet count
4451 * as follows: xfersize = N * maxpacket +
4452 * short_packet pktcnt = N + (short_packet
4455 deptsiz.b.xfersize = ep->maxpacket;
4456 deptsiz.b.pktcnt = 1;
4458 if (core_if->dma_desc_enable == 0) {
4459 DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4461 dma_desc = core_if->dev_if->out_desc_addr;
4463 /** DMA Descriptor Setup */
4464 dma_desc->status.b.bs = BS_HOST_BUSY;
4465 dma_desc->status.b.l = 1;
4466 dma_desc->status.b.ioc = 1;
4467 dma_desc->status.b.bytes = ep->maxpacket;
4468 dma_desc->buf = ep->dma_addr;
4469 dma_desc->status.b.sts = 0;
4470 dma_desc->status.b.bs = BS_HOST_READY;
4472 /** DOEPDMA0 Register write */
4473 DWC_WRITE_REG32(&out_regs->doepdma,
4474 core_if->dev_if->dma_out_desc_addr);
4477 DWC_DEBUGPL(DBG_PCDV,
4478 "IN len=%d xfersize=%d pktcnt=%d [%08x]\n",
4479 ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4482 /* Write the DMA register */
4483 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4484 if (core_if->dma_desc_enable == 0)
4485 DWC_WRITE_REG32(&(out_regs->doepdma),
4486 (uint32_t) ep->dma_addr);
4490 /* EP enable, IN data in FIFO */
4493 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4499 void dump_msg(const u8 * buf, unsigned int length)
4501 unsigned int start, num, i;
4507 while (length > 0) {
4508 num = length < 16u ? length : 16u;
4510 for (i = 0; i < num; ++i) {
4513 DWC_SPRINTF(p, " %02x", buf[i]);
4517 DWC_PRINTF("%6x: %s\n", start, line);
4524 static inline void dump_msg(const u8 * buf, unsigned int length)
4530 * This function writes a packet into the Tx FIFO associated with the
4531 * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For
4532 * periodic EPs the periodic Tx FIFO associated with the EP is written
4533 * with all packets for the next micro-frame.
4535 * @param core_if Programming view of DWC_otg controller.
4536 * @param ep The EP to write packet for.
4537 * @param dma Indicates if DMA is being used.
4539 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
4543 * The buffer is padded to DWORD on a per packet basis in
4544 * slave/dma mode if the MPS is not DWORD aligned. The last
4545 * packet, if short, is also padded to a multiple of DWORD.
4547 * ep->xfer_buff always starts DWORD aligned in memory and is a
4548 * multiple of DWORD in length
4550 * ep->xfer_len can be any number of bytes
4552 * ep->xfer_count is a multiple of ep->maxpacket until the last
4555 * FIFO access is DWORD */
4558 uint32_t byte_count;
4559 uint32_t dword_count;
4561 uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
4563 DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
4565 if (ep->xfer_count >= ep->xfer_len) {
4566 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4570 /* Find the byte length of the packet either short packet or MPS */
4571 if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
4572 byte_count = ep->xfer_len - ep->xfer_count;
4574 byte_count = ep->maxpacket;
4577 /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4578 * is not a multiple of DWORD */
4579 dword_count = (byte_count + 3) / 4;
4582 dump_msg(ep->xfer_buff, byte_count);
4585 /**@todo NGS Where are the Periodic Tx FIFO addresses
4586 * intialized? What should this be? */
4588 fifo = core_if->data_fifo[ep->num];
4590 DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
4591 fifo, data_buff, *data_buff, byte_count);
4594 for (i = 0; i < dword_count; i++, data_buff++) {
4595 DWC_WRITE_REG32(fifo, *data_buff);
4599 ep->xfer_count += byte_count;
4600 ep->xfer_buff += byte_count;
4601 ep->dma_addr += byte_count;
4607 * @param core_if Programming view of DWC_otg controller.
4608 * @param ep The EP to set the stall on.
4610 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4612 depctl_data_t depctl;
4613 volatile uint32_t *depctl_addr;
4615 DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4616 (ep->is_in ? "IN" : "OUT"));
4618 if (ep->is_in == 1) {
4619 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4620 depctl.d32 = DWC_READ_REG32(depctl_addr);
4622 /* set the disable and stall bits */
4623 if (depctl.b.epena) {
4627 DWC_WRITE_REG32(depctl_addr, depctl.d32);
4629 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4630 depctl.d32 = DWC_READ_REG32(depctl_addr);
4632 /* set the stall bit */
4634 DWC_WRITE_REG32(depctl_addr, depctl.d32);
4637 DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
4643 * Clear the EP STALL.
4645 * @param core_if Programming view of DWC_otg controller.
4646 * @param ep The EP to clear stall from.
4648 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4650 depctl_data_t depctl;
4651 volatile uint32_t *depctl_addr;
4653 DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4654 (ep->is_in ? "IN" : "OUT"));
4656 if (ep->is_in == 1) {
4657 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4659 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4662 depctl.d32 = DWC_READ_REG32(depctl_addr);
4664 /* clear the stall bits */
4668 * USB Spec 9.4.5: For endpoints using data toggle, regardless
4669 * of whether an endpoint has the Halt feature set, a
4670 * ClearFeature(ENDPOINT_HALT) request always results in the
4671 * data toggle being reinitialized to DATA0.
4673 if (ep->type == DWC_OTG_EP_TYPE_INTR ||
4674 ep->type == DWC_OTG_EP_TYPE_BULK) {
4675 depctl.b.setd0pid = 1; /* DATA0 */
4678 DWC_WRITE_REG32(depctl_addr, depctl.d32);
4679 DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
4684 * This function reads a packet from the Rx FIFO into the destination
4685 * buffer. To read SETUP data use dwc_otg_read_setup_packet.
4687 * @param core_if Programming view of DWC_otg controller.
4688 * @param dest Destination buffer for the packet.
4689 * @param bytes Number of bytes to copy to the destination.
4691 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
4692 uint8_t * dest, uint16_t bytes)
4695 int word_count = (bytes + 3) / 4;
4697 volatile uint32_t *fifo = core_if->data_fifo[0];
4698 uint32_t *data_buff = (uint32_t *) dest;
4701 * @todo Account for the case where _dest is not dword aligned. This
4702 * requires reading data from the FIFO into a uint32_t temp buffer,
4703 * then moving it into the data buffer.
4706 DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
4707 core_if, dest, bytes);
4709 for (i = 0; i < word_count; i++, data_buff++) {
4710 *data_buff = DWC_READ_REG32(fifo);
4717 * This functions reads the device registers and prints them
4719 * @param core_if Programming view of DWC_otg controller.
4721 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
4724 volatile uint32_t *addr;
4727 hwcfg1 = ~core_if->core_global_regs->ghwcfg1;
4729 DWC_PRINTF("Device Global Registers\n");
4730 addr = &core_if->dev_if->dev_global_regs->dcfg;
4731 DWC_PRINTF("DCFG @0x%08lX : 0x%08X\n",
4732 (unsigned long)addr, DWC_READ_REG32(addr));
4733 addr = &core_if->dev_if->dev_global_regs->dctl;
4734 DWC_PRINTF("DCTL @0x%08lX : 0x%08X\n",
4735 (unsigned long)addr, DWC_READ_REG32(addr));
4736 addr = &core_if->dev_if->dev_global_regs->dsts;
4737 DWC_PRINTF("DSTS @0x%08lX : 0x%08X\n",
4738 (unsigned long)addr, DWC_READ_REG32(addr));
4739 addr = &core_if->dev_if->dev_global_regs->diepmsk;
4740 DWC_PRINTF("DIEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4741 DWC_READ_REG32(addr));
4742 addr = &core_if->dev_if->dev_global_regs->doepmsk;
4743 DWC_PRINTF("DOEPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4744 DWC_READ_REG32(addr));
4745 addr = &core_if->dev_if->dev_global_regs->daint;
4746 DWC_PRINTF("DAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
4747 DWC_READ_REG32(addr));
4748 addr = &core_if->dev_if->dev_global_regs->daintmsk;
4749 DWC_PRINTF("DAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4750 DWC_READ_REG32(addr));
4751 addr = &core_if->dev_if->dev_global_regs->dtknqr1;
4752 DWC_PRINTF("DTKNQR1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
4753 DWC_READ_REG32(addr));
4754 if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
4755 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
4756 DWC_PRINTF("DTKNQR2 @0x%08lX : 0x%08X\n",
4757 (unsigned long)addr, DWC_READ_REG32(addr));
4760 addr = &core_if->dev_if->dev_global_regs->dvbusdis;
4761 DWC_PRINTF("DVBUSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
4762 DWC_READ_REG32(addr));
4764 addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
4765 DWC_PRINTF("DVBUSPULSE @0x%08lX : 0x%08X\n",
4766 (unsigned long)addr, DWC_READ_REG32(addr));
4768 addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
4769 DWC_PRINTF("DTKNQR3_DTHRCTL @0x%08lX : 0x%08X\n",
4770 (unsigned long)addr, DWC_READ_REG32(addr));
4772 if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
4773 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4774 DWC_PRINTF("DTKNQR4 @0x%08lX : 0x%08X\n",
4775 (unsigned long)addr, DWC_READ_REG32(addr));
4778 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4779 DWC_PRINTF("FIFOEMPMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4780 DWC_READ_REG32(addr));
4782 if (core_if->hwcfg2.b.multi_proc_int) {
4784 addr = &core_if->dev_if->dev_global_regs->deachint;
4785 DWC_PRINTF("DEACHINT @0x%08lX : 0x%08X\n",
4786 (unsigned long)addr, DWC_READ_REG32(addr));
4787 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
4788 DWC_PRINTF("DEACHINTMSK @0x%08lX : 0x%08X\n",
4789 (unsigned long)addr, DWC_READ_REG32(addr));
4791 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
4794 dev_global_regs->diepeachintmsk[i];
4795 DWC_PRINTF("DIEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
4796 i, (unsigned long)addr,
4797 DWC_READ_REG32(addr));
4800 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
4803 dev_global_regs->doepeachintmsk[i];
4804 DWC_PRINTF("DOEPEACHINTMSK[%d] @0x%08lX : 0x%08X\n",
4805 i, (unsigned long)addr,
4806 DWC_READ_REG32(addr));
4810 for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
4811 if(hwcfg1 & (2<<(i<<1))){
4812 DWC_PRINTF("Device IN EP %d Registers\n", i);
4813 addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
4814 DWC_PRINTF("DIEPCTL @0x%08lX : 0x%08X\n",
4815 (unsigned long)addr, DWC_READ_REG32(addr));
4816 addr = &core_if->dev_if->in_ep_regs[i]->diepint;
4817 DWC_PRINTF("DIEPINT @0x%08lX : 0x%08X\n",
4818 (unsigned long)addr, DWC_READ_REG32(addr));
4819 addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
4820 DWC_PRINTF("DIETSIZ @0x%08lX : 0x%08X\n",
4821 (unsigned long)addr, DWC_READ_REG32(addr));
4822 addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
4823 DWC_PRINTF("DIEPDMA @0x%08lX : 0x%08X\n",
4824 (unsigned long)addr, DWC_READ_REG32(addr));
4825 addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
4826 DWC_PRINTF("DTXFSTS @0x%08lX : 0x%08X\n",
4827 (unsigned long)addr, DWC_READ_REG32(addr));
4828 addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
4829 DWC_PRINTF("DIEPDMAB @0x%08lX : 0x%08X\n",
4830 (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
4834 for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
4835 if(hwcfg1 & (1<<(i<<1))){
4836 DWC_PRINTF("Device OUT EP %d Registers\n", i);
4837 addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
4838 DWC_PRINTF("DOEPCTL @0x%08lX : 0x%08X\n",
4839 (unsigned long)addr, DWC_READ_REG32(addr));
4840 addr = &core_if->dev_if->out_ep_regs[i]->doepint;
4841 DWC_PRINTF("DOEPINT @0x%08lX : 0x%08X\n",
4842 (unsigned long)addr, DWC_READ_REG32(addr));
4843 addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
4844 DWC_PRINTF("DOETSIZ @0x%08lX : 0x%08X\n",
4845 (unsigned long)addr, DWC_READ_REG32(addr));
4846 addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
4847 DWC_PRINTF("DOEPDMA @0x%08lX : 0x%08X\n",
4848 (unsigned long)addr, DWC_READ_REG32(addr));
4849 if (core_if->dma_enable) { /* Don't access this register in SLAVE mode */
4850 addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
4851 DWC_PRINTF("DOEPDMAB @0x%08lX : 0x%08X\n",
4852 (unsigned long)addr, DWC_READ_REG32(addr));
4860 * This functions reads the SPRAM and prints its content
4862 * @param core_if Programming view of DWC_otg controller.
4864 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
4866 volatile uint8_t *addr, *start_addr, *end_addr;
4868 DWC_PRINTF("SPRAM Data:\n");
4869 start_addr = (void *)core_if->core_global_regs;
4870 DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
4871 start_addr += 0x00028000;
4872 end_addr = (void *)core_if->core_global_regs;
4873 end_addr += 0x000280e0;
4875 for (addr = start_addr; addr < end_addr; addr += 16) {
4877 ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
4878 (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
4879 addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
4880 addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
4888 * This function reads the host registers and prints them
4890 * @param core_if Programming view of DWC_otg controller.
4892 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
4895 volatile uint32_t *addr;
4897 DWC_PRINTF("Host Global Registers\n");
4898 addr = &core_if->host_if->host_global_regs->hcfg;
4899 DWC_PRINTF("HCFG @0x%08lX : 0x%08X\n",
4900 (unsigned long)addr, DWC_READ_REG32(addr));
4901 addr = &core_if->host_if->host_global_regs->hfir;
4902 DWC_PRINTF("HFIR @0x%08lX : 0x%08X\n",
4903 (unsigned long)addr, DWC_READ_REG32(addr));
4904 addr = &core_if->host_if->host_global_regs->hfnum;
4905 DWC_PRINTF("HFNUM @0x%08lX : 0x%08X\n", (unsigned long)addr,
4906 DWC_READ_REG32(addr));
4907 addr = &core_if->host_if->host_global_regs->hptxsts;
4908 DWC_PRINTF("HPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
4909 DWC_READ_REG32(addr));
4910 addr = &core_if->host_if->host_global_regs->haint;
4911 DWC_PRINTF("HAINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
4912 DWC_READ_REG32(addr));
4913 addr = &core_if->host_if->host_global_regs->haintmsk;
4914 DWC_PRINTF("HAINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4915 DWC_READ_REG32(addr));
4916 if (core_if->dma_desc_enable) {
4917 addr = &core_if->host_if->host_global_regs->hflbaddr;
4918 DWC_PRINTF("HFLBADDR @0x%08lX : 0x%08X\n",
4919 (unsigned long)addr, DWC_READ_REG32(addr));
4922 addr = core_if->host_if->hprt0;
4923 DWC_PRINTF("HPRT0 @0x%08lX : 0x%08X\n", (unsigned long)addr,
4924 DWC_READ_REG32(addr));
4926 for (i = 0; i < core_if->core_params->host_channels; i++) {
4927 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
4928 addr = &core_if->host_if->hc_regs[i]->hcchar;
4929 DWC_PRINTF("HCCHAR @0x%08lX : 0x%08X\n",
4930 (unsigned long)addr, DWC_READ_REG32(addr));
4931 addr = &core_if->host_if->hc_regs[i]->hcsplt;
4932 DWC_PRINTF("HCSPLT @0x%08lX : 0x%08X\n",
4933 (unsigned long)addr, DWC_READ_REG32(addr));
4934 addr = &core_if->host_if->hc_regs[i]->hcint;
4935 DWC_PRINTF("HCINT @0x%08lX : 0x%08X\n",
4936 (unsigned long)addr, DWC_READ_REG32(addr));
4937 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
4938 DWC_PRINTF("HCINTMSK @0x%08lX : 0x%08X\n",
4939 (unsigned long)addr, DWC_READ_REG32(addr));
4940 addr = &core_if->host_if->hc_regs[i]->hctsiz;
4941 DWC_PRINTF("HCTSIZ @0x%08lX : 0x%08X\n",
4942 (unsigned long)addr, DWC_READ_REG32(addr));
4943 addr = &core_if->host_if->hc_regs[i]->hcdma;
4944 DWC_PRINTF("HCDMA @0x%08lX : 0x%08X\n",
4945 (unsigned long)addr, DWC_READ_REG32(addr));
4946 if (core_if->dma_desc_enable) {
4947 addr = &core_if->host_if->hc_regs[i]->hcdmab;
4948 DWC_PRINTF("HCDMAB @0x%08lX : 0x%08X\n",
4949 (unsigned long)addr, DWC_READ_REG32(addr));
4957 * This function reads the core global registers and prints them
4959 * @param core_if Programming view of DWC_otg controller.
4961 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
4964 volatile uint32_t *addr;
4967 DWC_PRINTF("Core Global Registers\n");
4968 addr = &core_if->core_global_regs->gotgctl;
4969 DWC_PRINTF("GOTGCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
4970 DWC_READ_REG32(addr));
4971 addr = &core_if->core_global_regs->gotgint;
4972 DWC_PRINTF("GOTGINT @0x%08lX : 0x%08X\n", (unsigned long)addr,
4973 DWC_READ_REG32(addr));
4974 addr = &core_if->core_global_regs->gahbcfg;
4975 DWC_PRINTF("GAHBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
4976 DWC_READ_REG32(addr));
4977 addr = &core_if->core_global_regs->gusbcfg;
4978 DWC_PRINTF("GUSBCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
4979 DWC_READ_REG32(addr));
4980 addr = &core_if->core_global_regs->grstctl;
4981 DWC_PRINTF("GRSTCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
4982 DWC_READ_REG32(addr));
4983 addr = &core_if->core_global_regs->gintsts;
4984 DWC_PRINTF("GINTSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
4985 DWC_READ_REG32(addr));
4986 addr = &core_if->core_global_regs->gintmsk;
4987 DWC_PRINTF("GINTMSK @0x%08lX : 0x%08X\n", (unsigned long)addr,
4988 DWC_READ_REG32(addr));
4989 addr = &core_if->core_global_regs->grxstsr;
4990 DWC_PRINTF("GRXSTSR @0x%08lX : 0x%08X\n", (unsigned long)addr,
4991 DWC_READ_REG32(addr));
4992 addr = &core_if->core_global_regs->grxfsiz;
4993 DWC_PRINTF("GRXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
4994 DWC_READ_REG32(addr));
4995 addr = &core_if->core_global_regs->gnptxfsiz;
4996 DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
4997 DWC_READ_REG32(addr));
4998 addr = &core_if->core_global_regs->gnptxsts;
4999 DWC_PRINTF("GNPTXSTS @0x%08lX : 0x%08X\n", (unsigned long)addr,
5000 DWC_READ_REG32(addr));
5001 addr = &core_if->core_global_regs->gi2cctl;
5002 DWC_PRINTF("GI2CCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
5003 DWC_READ_REG32(addr));
5004 addr = &core_if->core_global_regs->gpvndctl;
5005 DWC_PRINTF("GPVNDCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
5006 DWC_READ_REG32(addr));
5007 addr = &core_if->core_global_regs->ggpio;
5008 DWC_PRINTF("GGPIO @0x%08lX : 0x%08X\n", (unsigned long)addr,
5009 DWC_READ_REG32(addr));
5010 addr = &core_if->core_global_regs->guid;
5011 DWC_PRINTF("GUID @0x%08lX : 0x%08X\n",
5012 (unsigned long)addr, DWC_READ_REG32(addr));
5013 addr = &core_if->core_global_regs->gsnpsid;
5014 DWC_PRINTF("GSNPSID @0x%08lX : 0x%08X\n", (unsigned long)addr,
5015 DWC_READ_REG32(addr));
5016 addr = &core_if->core_global_regs->ghwcfg1;
5017 DWC_PRINTF("GHWCFG1 @0x%08lX : 0x%08X\n", (unsigned long)addr,
5018 DWC_READ_REG32(addr));
5019 addr = &core_if->core_global_regs->ghwcfg2;
5020 DWC_PRINTF("GHWCFG2 @0x%08lX : 0x%08X\n", (unsigned long)addr,
5021 DWC_READ_REG32(addr));
5022 addr = &core_if->core_global_regs->ghwcfg3;
5023 DWC_PRINTF("GHWCFG3 @0x%08lX : 0x%08X\n", (unsigned long)addr,
5024 DWC_READ_REG32(addr));
5025 addr = &core_if->core_global_regs->ghwcfg4;
5026 DWC_PRINTF("GHWCFG4 @0x%08lX : 0x%08X\n", (unsigned long)addr,
5027 DWC_READ_REG32(addr));
5028 addr = &core_if->core_global_regs->glpmcfg;
5029 DWC_PRINTF("GLPMCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
5030 DWC_READ_REG32(addr));
5031 addr = &core_if->core_global_regs->gpwrdn;
5032 DWC_PRINTF("GPWRDN @0x%08lX : 0x%08X\n", (unsigned long)addr,
5033 DWC_READ_REG32(addr));
5034 addr = &core_if->core_global_regs->gdfifocfg;
5035 DWC_PRINTF("GDFIFOCFG @0x%08lX : 0x%08X\n", (unsigned long)addr,
5036 DWC_READ_REG32(addr));
5037 addr = &core_if->core_global_regs->adpctl;
5038 DWC_PRINTF("ADPCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
5039 dwc_otg_adp_read_reg(core_if));
5040 addr = &core_if->core_global_regs->hptxfsiz;
5041 DWC_PRINTF("HPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
5042 DWC_READ_REG32(addr));
5044 if (core_if->en_multiple_tx_fifo == 0) {
5045 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
5046 txfsiz = "DPTXFSIZ";
5048 ep_num = core_if->hwcfg4.b.num_in_eps;
5049 txfsiz = "DIENPTXF";
5051 for (i = 0; i < ep_num; i++) {
5052 addr = &core_if->core_global_regs->dtxfsiz[i];
5053 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
5054 (unsigned long)addr, DWC_READ_REG32(addr));
5056 addr = core_if->pcgcctl;
5057 DWC_PRINTF("PCGCCTL @0x%08lX : 0x%08X\n", (unsigned long)addr,
5058 DWC_READ_REG32(addr));
5064 * @param core_if Programming view of DWC_otg controller.
5065 * @param num Tx FIFO to flush.
5067 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
5069 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5070 volatile grstctl_t greset = {.d32 = 0 };
5073 DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
5075 greset.b.txfflsh = 1;
5076 greset.b.txfnum = num;
5077 DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5080 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5081 if (++count > 10000) {
5082 DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
5083 __func__, greset.d32,
5084 DWC_READ_REG32(&global_regs->gnptxsts));
5088 } while (greset.b.txfflsh == 1);
5090 /* Wait for 3 PHY Clocks */
5097 * @param core_if Programming view of DWC_otg controller.
5099 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
5101 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5102 volatile grstctl_t greset = {.d32 = 0 };
5105 DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
5109 greset.b.rxfflsh = 1;
5110 DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5113 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5114 if (++count > 10000) {
5115 DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
5120 } while (greset.b.rxfflsh == 1);
5122 /* Wait for 3 PHY Clocks */
5127 * Do core a soft reset of the core. Be careful with this because it
5128 * resets all the internal state machines of the core.
5130 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
5132 dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5133 volatile grstctl_t greset = {.d32 = 0 };
5136 DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
5137 /* Wait for AHB master IDLE state. */
5140 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5141 if (++count > 100000) {
5142 DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
5147 while (greset.b.ahbidle == 0);
5149 /* Core Soft Reset */
5151 greset.b.csftrst = 1;
5152 DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5154 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5155 if (++count > 10000) {
5156 DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
5157 __func__, greset.d32);
5162 while (greset.b.csftrst == 1);
5164 /* Wait for 3 PHY Clocks */
5169 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
5171 return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5174 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
5176 return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5180 * Register HCD callbacks. The callbacks are used to start and stop
5181 * the HCD for interrupt processing.
5183 * @param core_if Programming view of DWC_otg controller.
5184 * @param cb the HCD callback structure.
5185 * @param p pointer to be passed to callback function (usb_hcd*).
5187 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
5188 dwc_otg_cil_callbacks_t * cb, void *p)
5190 core_if->hcd_cb = cb;
5192 core_if->hcd_cb_p = p;
5196 * Register PCD callbacks. The callbacks are used to start and stop
5197 * the PCD for interrupt processing.
5199 * @param core_if Programming view of DWC_otg controller.
5200 * @param cb the PCD callback structure.
5201 * @param p pointer to be passed to callback function (pcd*).
5203 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
5204 dwc_otg_cil_callbacks_t * cb, void *p)
5206 core_if->pcd_cb = cb;
5213 * This function writes isoc data per 1 (micro)frame into tx fifo
5215 * @param core_if Programming view of DWC_otg controller.
5216 * @param ep The EP to start the transfer on.
5219 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
5221 dwc_otg_dev_in_ep_regs_t *ep_regs;
5222 dtxfsts_data_t txstatus = {.d32 = 0 };
5226 ep->xfer_len = ep->data_per_frame;
5229 ep_regs = core_if->dev_if->in_ep_regs[ep->num];
5231 len = ep->xfer_len - ep->xfer_count;
5233 if (len > ep->maxpacket) {
5234 len = ep->maxpacket;
5237 dwords = (len + 3) / 4;
5239 /* While there is space in the queue and space in the FIFO and
5240 * More data to tranfer, Write packets to the Tx FIFO */
5242 DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
5243 DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
5245 while (txstatus.b.txfspcavail > dwords &&
5246 ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
5247 /* Write the FIFO */
5248 dwc_otg_ep_write_packet(core_if, ep, 0);
5250 len = ep->xfer_len - ep->xfer_count;
5251 if (len > ep->maxpacket) {
5252 len = ep->maxpacket;
5255 dwords = (len + 3) / 4;
5257 DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
5259 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
5265 * This function initializes a descriptor chain for Isochronous transfer
5267 * @param core_if Programming view of DWC_otg controller.
5268 * @param ep The EP to start the transfer on.
5271 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
5274 deptsiz_data_t deptsiz = {.d32 = 0 };
5275 depctl_data_t depctl = {.d32 = 0 };
5276 dsts_data_t dsts = {.d32 = 0 };
5277 volatile uint32_t *addr;
5280 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
5282 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
5285 ep->xfer_len = ep->data_per_frame;
5287 ep->xfer_buff = ep->cur_pkt_addr;
5288 ep->dma_addr = ep->cur_pkt_dma_addr;
5291 /* Program the transfer size and packet count
5292 * as follows: xfersize = N * maxpacket +
5293 * short_packet pktcnt = N + (short_packet
5296 deptsiz.b.xfersize = ep->xfer_len;
5298 (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
5299 deptsiz.b.mc = deptsiz.b.pktcnt;
5300 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
5303 /* Write the DMA register */
5304 if (core_if->dma_enable) {
5306 (core_if->dev_if->in_ep_regs[ep->num]->
5307 diepdma), (uint32_t) ep->dma_addr);
5311 (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
5312 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
5314 DWC_WRITE_REG32(&core_if->dev_if->
5315 out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
5317 if (core_if->dma_enable) {
5320 out_ep_regs[ep->num]->doepdma),
5321 (uint32_t) ep->dma_addr);
5325 /** Enable endpoint, clear nak */
5328 if (ep->bInterval == 1) {
5330 DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
5331 ep->next_frame = dsts.b.soffn + ep->bInterval;
5333 if (ep->next_frame & 0x1) {
5334 depctl.b.setd1pid = 1;
5336 depctl.b.setd0pid = 1;
5339 ep->next_frame += ep->bInterval;
5341 if (ep->next_frame & 0x1) {
5342 depctl.b.setd1pid = 1;
5344 depctl.b.setd0pid = 1;
5350 DWC_MODIFY_REG32(addr, 0, depctl.d32);
5351 depctl.d32 = DWC_READ_REG32(addr);
5353 if (ep->is_in && core_if->dma_enable == 0) {
5354 write_isoc_frame_data(core_if, ep);
5358 #endif /* DWC_EN_ISOC */
5360 static void dwc_otg_set_uninitialized(int32_t * p, int size)
5363 for (i = 0; i < size; i++) {
5368 static int dwc_otg_param_initialized(int32_t val)
5373 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
5375 gintsts_data_t gintsts;
5376 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
5378 core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
5379 if (!core_if->core_params) {
5380 return -DWC_E_NO_MEMORY;
5382 dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
5383 sizeof(*core_if->core_params) /
5385 DWC_PRINTF("Setting default values for core params\n");
5386 dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
5387 dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
5388 dwc_otg_set_param_dma_desc_enable(core_if,
5389 dwc_param_dma_desc_enable_default);
5390 dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
5391 dwc_otg_set_param_dma_burst_size(core_if,
5392 dwc_param_dma_burst_size_default);
5393 dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
5394 dwc_param_host_support_fs_ls_low_power_default);
5395 dwc_otg_set_param_enable_dynamic_fifo(core_if,
5396 dwc_param_enable_dynamic_fifo_default);
5397 dwc_otg_set_param_data_fifo_size(core_if,
5398 dwc_param_data_fifo_size_default);
5399 dwc_otg_set_param_dev_rx_fifo_size(core_if,
5400 dwc_param_dev_rx_fifo_size_default);
5401 dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
5402 dwc_param_dev_nperio_tx_fifo_size_default);
5403 dwc_otg_set_param_host_rx_fifo_size(core_if,
5404 dwc_param_host_rx_fifo_size_default);
5405 dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
5406 dwc_param_host_nperio_tx_fifo_size_default);
5407 dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
5408 dwc_param_host_perio_tx_fifo_size_default);
5409 dwc_otg_set_param_max_transfer_size(core_if,
5410 dwc_param_max_transfer_size_default);
5411 dwc_otg_set_param_max_packet_count(core_if,
5412 dwc_param_max_packet_count_default);
5413 dwc_otg_set_param_host_channels(core_if,
5414 dwc_param_host_channels_default);
5415 dwc_otg_set_param_dev_endpoints(core_if,
5416 dwc_param_dev_endpoints_default);
5417 dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
5418 dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
5419 dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
5420 dwc_param_host_ls_low_power_phy_clk_default);
5421 dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
5422 dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
5423 dwc_param_phy_ulpi_ext_vbus_default);
5424 dwc_otg_set_param_phy_utmi_width(core_if,
5425 dwc_param_phy_utmi_width_default);
5426 dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
5427 dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
5428 dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
5429 dwc_otg_set_param_en_multiple_tx_fifo(core_if,
5430 dwc_param_en_multiple_tx_fifo_default);
5432 /* do not set dev_perio_tx_fifo_size and dev_tx_fifo_size here
5433 * set validate parameter values in "set_parameters" later.
5436 if (gintsts.b.curmode) {
5437 /* Force device mode to get power-on values of device FIFOs */
5438 gusbcfg_data_t gusbcfg = {.d32 = 0 };
5439 gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5440 gusbcfg.b.force_dev_mode = 1;
5441 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
5443 for (i = 0; i < 15; i++) {
5444 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5445 dwc_param_dev_perio_tx_fifo_size_default, i);
5447 for (i = 0; i < 15; i++) {
5448 dwc_otg_set_param_dev_tx_fifo_size(core_if,
5449 dwc_param_dev_tx_fifo_size_default, i);
5451 gusbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5452 gusbcfg.b.force_dev_mode = 0;
5453 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
5456 for (i = 0; i < 15; i++) {
5457 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5458 dwc_param_dev_perio_tx_fifo_size_default, i);
5460 for (i = 0; i < 15; i++) {
5461 dwc_otg_set_param_dev_tx_fifo_size(core_if,
5462 dwc_param_dev_tx_fifo_size_default, i);
5466 dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
5467 dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
5468 dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
5469 dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
5471 dwc_otg_set_param_besl_enable(core_if, dwc_param_besl_enable_default);
5472 dwc_otg_set_param_baseline_besl(core_if, dwc_param_baseline_besl_default);
5473 dwc_otg_set_param_deep_besl(core_if, dwc_param_deep_besl_default);
5475 dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
5476 dwc_otg_set_param_tx_thr_length(core_if,
5477 dwc_param_tx_thr_length_default);
5478 dwc_otg_set_param_rx_thr_length(core_if,
5479 dwc_param_rx_thr_length_default);
5480 dwc_otg_set_param_ahb_thr_ratio(core_if,
5481 dwc_param_ahb_thr_ratio_default);
5482 dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
5483 dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
5484 dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
5485 dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
5486 dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
5487 dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
5488 dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
5492 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
5494 return core_if->dma_enable;
5497 /* Checks if the parameter is outside of its valid range of values */
5498 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
5499 (((_param_) < (_low_)) || \
5500 ((_param_) > (_high_)))
5502 /* Parameter access functions */
5503 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
5507 if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
5508 DWC_WARN("Wrong value for otg_cap parameter\n");
5509 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
5510 retval = -DWC_E_INVALID;
5516 case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
5517 if (core_if->hwcfg2.b.op_mode !=
5518 DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5521 case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
5522 if ((core_if->hwcfg2.b.op_mode !=
5523 DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5524 && (core_if->hwcfg2.b.op_mode !=
5525 DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5526 && (core_if->hwcfg2.b.op_mode !=
5527 DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5528 && (core_if->hwcfg2.b.op_mode !=
5529 DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
5533 case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
5538 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
5540 ("%d invalid for otg_cap paremter. Check HW configuration.\n",
5544 (((core_if->hwcfg2.b.op_mode ==
5545 DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5546 || (core_if->hwcfg2.b.op_mode ==
5547 DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5548 || (core_if->hwcfg2.b.op_mode ==
5549 DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5550 || (core_if->hwcfg2.b.op_mode ==
5551 DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
5552 DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
5553 DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
5554 retval = -DWC_E_INVALID;
5557 core_if->core_params->otg_cap = val;
5562 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
5564 return core_if->core_params->otg_cap;
5567 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
5569 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5570 DWC_WARN("Wrong value for opt parameter\n");
5571 return -DWC_E_INVALID;
5573 core_if->core_params->opt = val;
5577 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
5579 return core_if->core_params->opt;
5582 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
5585 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5586 DWC_WARN("Wrong value for dma enable\n");
5587 return -DWC_E_INVALID;
5590 if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
5591 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
5593 ("%d invalid for dma_enable paremter. Check HW configuration.\n",
5597 retval = -DWC_E_INVALID;
5600 core_if->core_params->dma_enable = val;
5602 dwc_otg_set_param_dma_desc_enable(core_if, 0);
5607 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
5609 return core_if->core_params->dma_enable;
5612 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
5615 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5616 DWC_WARN("Wrong value for dma_enable\n");
5617 DWC_WARN("dma_desc_enable must be 0 or 1\n");
5618 return -DWC_E_INVALID;
5622 && ((dwc_otg_get_param_dma_enable(core_if) == 0)
5623 || (core_if->hwcfg4.b.desc_dma == 0))) {
5624 if (dwc_otg_param_initialized
5625 (core_if->core_params->dma_desc_enable)) {
5627 ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
5631 retval = -DWC_E_INVALID;
5633 core_if->core_params->dma_desc_enable = val;
5637 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
5639 return core_if->core_params->dma_desc_enable;
5642 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
5645 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5646 DWC_WARN("Wrong value for host_support_fs_low_power\n");
5647 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
5648 return -DWC_E_INVALID;
5650 core_if->core_params->host_support_fs_ls_low_power = val;
5654 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
5657 return core_if->core_params->host_support_fs_ls_low_power;
5660 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
5664 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5665 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
5666 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
5667 return -DWC_E_INVALID;
5670 if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
5671 if (dwc_otg_param_initialized
5672 (core_if->core_params->enable_dynamic_fifo)) {
5674 ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
5678 retval = -DWC_E_INVALID;
5680 core_if->core_params->enable_dynamic_fifo = val;
5684 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
5686 return core_if->core_params->enable_dynamic_fifo;
5689 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
5692 if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
5693 DWC_WARN("Wrong value for data_fifo_size\n");
5694 DWC_WARN("data_fifo_size must be 32-32768\n");
5695 return -DWC_E_INVALID;
5698 if (val > core_if->hwcfg3.b.dfifo_depth) {
5699 if (dwc_otg_param_initialized
5700 (core_if->core_params->data_fifo_size)) {
5702 ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
5705 val = core_if->hwcfg3.b.dfifo_depth;
5706 retval = -DWC_E_INVALID;
5709 core_if->core_params->data_fifo_size = val;
5713 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
5715 return core_if->core_params->data_fifo_size;
5718 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
5721 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5722 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
5723 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
5724 return -DWC_E_INVALID;
5727 if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
5728 if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
5729 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
5731 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
5732 retval = -DWC_E_INVALID;
5735 core_if->core_params->dev_rx_fifo_size = val;
5739 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
5741 return core_if->core_params->dev_rx_fifo_size;
5744 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5749 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5750 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
5751 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
5752 return -DWC_E_INVALID;
5755 if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
5756 if (dwc_otg_param_initialized
5757 (core_if->core_params->dev_nperio_tx_fifo_size)) {
5759 ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
5763 (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
5765 retval = -DWC_E_INVALID;
5768 core_if->core_params->dev_nperio_tx_fifo_size = val;
5772 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5774 return core_if->core_params->dev_nperio_tx_fifo_size;
5777 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
5782 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5783 DWC_WARN("Wrong value for host_rx_fifo_size\n");
5784 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
5785 return -DWC_E_INVALID;
5788 if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
5789 if (dwc_otg_param_initialized
5790 (core_if->core_params->host_rx_fifo_size)) {
5792 ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
5795 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
5796 retval = -DWC_E_INVALID;
5799 core_if->core_params->host_rx_fifo_size = val;
5804 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
5806 return core_if->core_params->host_rx_fifo_size;
5809 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5814 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5815 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
5816 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
5817 return -DWC_E_INVALID;
5820 if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
5821 if (dwc_otg_param_initialized
5822 (core_if->core_params->host_nperio_tx_fifo_size)) {
5824 ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
5828 (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
5830 retval = -DWC_E_INVALID;
5833 core_if->core_params->host_nperio_tx_fifo_size = val;
5837 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5839 return core_if->core_params->host_nperio_tx_fifo_size;
5842 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5846 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5847 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
5848 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
5849 return -DWC_E_INVALID;
5852 if (val > ((core_if->hptxfsiz.d32) >> 16)) {
5853 if (dwc_otg_param_initialized
5854 (core_if->core_params->host_perio_tx_fifo_size)) {
5856 ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
5859 val = (core_if->hptxfsiz.d32) >> 16;
5860 retval = -DWC_E_INVALID;
5863 core_if->core_params->host_perio_tx_fifo_size = val;
5867 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5869 return core_if->core_params->host_perio_tx_fifo_size;
5872 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
5877 if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
5878 DWC_WARN("Wrong value for max_transfer_size\n");
5879 DWC_WARN("max_transfer_size must be 2047-524288\n");
5880 return -DWC_E_INVALID;
5883 if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
5884 if (dwc_otg_param_initialized
5885 (core_if->core_params->max_transfer_size)) {
5887 ("%d invalid for max_transfer_size. Check HW configuration.\n",
5891 ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
5893 retval = -DWC_E_INVALID;
5896 core_if->core_params->max_transfer_size = val;
5900 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
5902 return core_if->core_params->max_transfer_size;
5905 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
5909 if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
5910 DWC_WARN("Wrong value for max_packet_count\n");
5911 DWC_WARN("max_packet_count must be 15-511\n");
5912 return -DWC_E_INVALID;
5915 if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
5916 if (dwc_otg_param_initialized
5917 (core_if->core_params->max_packet_count)) {
5919 ("%d invalid for max_packet_count. Check HW configuration.\n",
5923 ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
5924 retval = -DWC_E_INVALID;
5927 core_if->core_params->max_packet_count = val;
5931 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
5933 return core_if->core_params->max_packet_count;
5936 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
5940 if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
5941 DWC_WARN("Wrong value for host_channels\n");
5942 DWC_WARN("host_channels must be 1-16\n");
5943 return -DWC_E_INVALID;
5946 if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
5947 if (dwc_otg_param_initialized
5948 (core_if->core_params->host_channels)) {
5950 ("%d invalid for host_channels. Check HW configurations.\n",
5953 val = (core_if->hwcfg2.b.num_host_chan + 1);
5954 retval = -DWC_E_INVALID;
5957 core_if->core_params->host_channels = val;
5961 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
5963 return core_if->core_params->host_channels;
5966 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
5970 if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
5971 DWC_WARN("Wrong value for dev_endpoints\n");
5972 DWC_WARN("dev_endpoints must be 1-15\n");
5973 return -DWC_E_INVALID;
5976 if (val > (core_if->hwcfg2.b.num_dev_ep)) {
5977 if (dwc_otg_param_initialized
5978 (core_if->core_params->dev_endpoints)) {
5980 ("%d invalid for dev_endpoints. Check HW configurations.\n",
5983 val = core_if->hwcfg2.b.num_dev_ep;
5984 retval = -DWC_E_INVALID;
5987 core_if->core_params->dev_endpoints = val;
5991 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
5993 return core_if->core_params->dev_endpoints;
5996 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
6001 if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
6002 DWC_WARN("Wrong value for phy_type\n");
6003 DWC_WARN("phy_type must be 0,1 or 2\n");
6004 return -DWC_E_INVALID;
6006 #ifndef NO_FS_PHY_HW_CHECKS
6007 if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
6008 ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6009 (core_if->hwcfg2.b.hs_phy_type == 3))) {
6011 } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
6012 ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6013 (core_if->hwcfg2.b.hs_phy_type == 3))) {
6015 } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
6016 (core_if->hwcfg2.b.fs_phy_type == 1)) {
6020 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
6022 ("%d invalid for phy_type. Check HW configurations.\n",
6025 if (core_if->hwcfg2.b.hs_phy_type) {
6026 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6027 (core_if->hwcfg2.b.hs_phy_type == 1)) {
6028 val = DWC_PHY_TYPE_PARAM_UTMI;
6030 val = DWC_PHY_TYPE_PARAM_ULPI;
6033 retval = -DWC_E_INVALID;
6036 core_if->core_params->phy_type = val;
6040 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
6042 return core_if->core_params->phy_type;
6045 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
6048 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6049 DWC_WARN("Wrong value for speed parameter\n");
6050 DWC_WARN("max_speed parameter must be 0 or 1\n");
6051 return -DWC_E_INVALID;
6054 && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
6055 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
6057 ("%d invalid for speed paremter. Check HW configuration.\n",
6061 (dwc_otg_get_param_phy_type(core_if) ==
6062 DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6063 retval = -DWC_E_INVALID;
6065 core_if->core_params->speed = val;
6069 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
6071 return core_if->core_params->speed;
6074 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
6079 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6081 ("Wrong value for host_ls_low_power_phy_clk parameter\n");
6082 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
6083 return -DWC_E_INVALID;
6086 if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
6087 && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
6088 if (dwc_otg_param_initialized
6089 (core_if->core_params->host_ls_low_power_phy_clk)) {
6091 ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
6095 (dwc_otg_get_param_phy_type(core_if) ==
6096 DWC_PHY_TYPE_PARAM_FS) ?
6097 DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
6098 DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
6099 retval = -DWC_E_INVALID;
6102 core_if->core_params->host_ls_low_power_phy_clk = val;
6106 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
6108 return core_if->core_params->host_ls_low_power_phy_clk;
6111 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
6113 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6114 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
6115 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
6116 return -DWC_E_INVALID;
6119 core_if->core_params->phy_ulpi_ddr = val;
6123 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
6125 return core_if->core_params->phy_ulpi_ddr;
6128 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
6131 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6132 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
6133 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
6134 return -DWC_E_INVALID;
6137 core_if->core_params->phy_ulpi_ext_vbus = val;
6141 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
6143 return core_if->core_params->phy_ulpi_ext_vbus;
6146 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
6148 if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
6149 DWC_WARN("Wrong valaue for phy_utmi_width\n");
6150 DWC_WARN("phy_utmi_width must be 8 or 16\n");
6151 return -DWC_E_INVALID;
6154 core_if->core_params->phy_utmi_width = val;
6158 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
6160 return core_if->core_params->phy_utmi_width;
6163 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
6165 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6166 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
6167 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
6168 return -DWC_E_INVALID;
6171 core_if->core_params->ulpi_fs_ls = val;
6175 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
6177 return core_if->core_params->ulpi_fs_ls;
6180 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
6182 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6183 DWC_WARN("Wrong valaue for ts_dline\n");
6184 DWC_WARN("ts_dline must be 0 or 1\n");
6185 return -DWC_E_INVALID;
6188 core_if->core_params->ts_dline = val;
6192 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
6194 return core_if->core_params->ts_dline;
6197 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
6200 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6201 DWC_WARN("Wrong valaue for i2c_enable\n");
6202 DWC_WARN("i2c_enable must be 0 or 1\n");
6203 return -DWC_E_INVALID;
6205 #ifndef NO_FS_PHY_HW_CHECK
6206 if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
6207 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
6209 ("%d invalid for i2c_enable. Check HW configuration.\n",
6213 retval = -DWC_E_INVALID;
6217 core_if->core_params->i2c_enable = val;
6221 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
6223 return core_if->core_params->i2c_enable;
6226 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
6227 int32_t val, int fifo_num)
6230 gintsts_data_t gintsts;
6231 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6233 if (core_if->hwcfg4.b.ded_fifo_en == 0){
6234 if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
6235 DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
6236 DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
6237 return -DWC_E_INVALID;
6240 if (val > (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
6241 printk("%d ",DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
6242 printk("val = %d fifo_num = %d\n",val,fifo_num);
6243 DWC_WARN("Value is larger then power-on FIFO size\n");
6244 if (dwc_otg_param_initialized
6245 (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
6247 ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
6250 val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
6251 retval = -DWC_E_INVALID;
6254 core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
6259 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
6262 return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
6265 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
6269 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6270 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
6271 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
6272 return -DWC_E_INVALID;
6275 if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
6276 if (dwc_otg_param_initialized
6277 (core_if->core_params->en_multiple_tx_fifo)) {
6279 ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
6283 retval = -DWC_E_INVALID;
6286 core_if->core_params->en_multiple_tx_fifo = val;
6290 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
6292 return core_if->core_params->en_multiple_tx_fifo;
6295 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
6299 fifosize_data_t txfifosize;
6300 txfifosize.d32 = DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
6302 if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6303 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
6304 DWC_WARN("dev_tx_fifo_size must be 16-32768\n");
6305 return -DWC_E_INVALID;
6308 core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
6312 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
6315 return core_if->core_params->dev_tx_fifo_size[fifo_num];
6318 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
6322 if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
6323 DWC_WARN("Wrong value for thr_ctl\n");
6324 DWC_WARN("thr_ctl must be 0-7\n");
6325 return -DWC_E_INVALID;
6329 (!dwc_otg_get_param_dma_enable(core_if) ||
6330 !core_if->hwcfg4.b.ded_fifo_en)) {
6331 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
6333 ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
6337 retval = -DWC_E_INVALID;
6340 core_if->core_params->thr_ctl = val;
6344 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
6346 return core_if->core_params->thr_ctl;
6349 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
6353 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6354 DWC_WARN("Wrong value for lpm_enable\n");
6355 DWC_WARN("lpm_enable must be 0 or 1\n");
6356 return -DWC_E_INVALID;
6359 if (val && !core_if->hwcfg3.b.otg_lpm_en) {
6360 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
6362 ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
6366 retval = -DWC_E_INVALID;
6369 core_if->core_params->lpm_enable = val;
6373 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
6375 return core_if->core_params->lpm_enable;
6378 int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if, int32_t val)
6382 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6383 DWC_WARN("Wrong value for besl_enable\n");
6384 DWC_WARN("besl_enable must be 0 or 1\n");
6385 return -DWC_E_INVALID;
6388 core_if->core_params->besl_enable = val;
6392 retval += dwc_otg_set_param_lpm_enable(core_if,val);
6398 int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if)
6400 return core_if->core_params->besl_enable;
6403 int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if, int32_t val)
6407 if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6408 DWC_WARN("Wrong value for baseline_besl\n");
6409 DWC_WARN("baseline_besl must be 0-15\n");
6410 return -DWC_E_INVALID;
6413 core_if->core_params->baseline_besl = val;
6417 int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if)
6419 return core_if->core_params->baseline_besl;
6422 int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if, int32_t val)
6426 if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6427 DWC_WARN("Wrong value for deep_besl\n");
6428 DWC_WARN("deep_besl must be 0-15\n");
6429 return -DWC_E_INVALID;
6432 core_if->core_params->deep_besl = val;
6436 int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if)
6438 return core_if->core_params->deep_besl;
6441 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
6443 if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6444 DWC_WARN("Wrong valaue for tx_thr_length\n");
6445 DWC_WARN("tx_thr_length must be 8 - 128\n");
6446 return -DWC_E_INVALID;
6449 core_if->core_params->tx_thr_length = val;
6453 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
6455 return core_if->core_params->tx_thr_length;
6458 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
6460 if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6461 DWC_WARN("Wrong valaue for rx_thr_length\n");
6462 DWC_WARN("rx_thr_length must be 8 - 128\n");
6463 return -DWC_E_INVALID;
6466 core_if->core_params->rx_thr_length = val;
6470 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
6472 return core_if->core_params->rx_thr_length;
6475 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
6477 if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
6478 DWC_OTG_PARAM_TEST(val, 4, 4) &&
6479 DWC_OTG_PARAM_TEST(val, 8, 8) &&
6480 DWC_OTG_PARAM_TEST(val, 16, 16) &&
6481 DWC_OTG_PARAM_TEST(val, 32, 32) &&
6482 DWC_OTG_PARAM_TEST(val, 64, 64) &&
6483 DWC_OTG_PARAM_TEST(val, 128, 128) &&
6484 DWC_OTG_PARAM_TEST(val, 256, 256)) {
6485 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
6486 return -DWC_E_INVALID;
6488 core_if->core_params->dma_burst_size = val;
6492 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
6494 return core_if->core_params->dma_burst_size;
6497 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
6500 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6501 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
6502 return -DWC_E_INVALID;
6504 if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
6505 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
6507 ("%d invalid for parameter pti_enable. Check HW configuration.\n",
6510 retval = -DWC_E_INVALID;
6513 core_if->core_params->pti_enable = val;
6517 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
6519 return core_if->core_params->pti_enable;
6522 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
6525 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6526 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
6527 return -DWC_E_INVALID;
6529 if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
6530 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
6532 ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
6535 retval = -DWC_E_INVALID;
6538 core_if->core_params->mpi_enable = val;
6542 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
6544 return core_if->core_params->mpi_enable;
6547 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
6550 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6551 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
6552 return -DWC_E_INVALID;
6554 if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
6555 if (dwc_otg_param_initialized
6556 (core_if->core_params->adp_supp_enable)) {
6558 ("%d invalid for parameter adp_enable. Check HW configuration.\n",
6561 retval = -DWC_E_INVALID;
6564 core_if->core_params->adp_supp_enable = val;
6565 /* Set OTG version 2.0 in case of enabling ADP */
6567 dwc_otg_set_param_otg_ver(core_if, 1);
6572 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
6574 return core_if->core_params->adp_supp_enable;
6577 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
6580 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6581 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
6582 DWC_WARN("ic_usb_cap must be 0 or 1\n");
6583 return -DWC_E_INVALID;
6586 if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
6587 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
6589 ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
6592 retval = -DWC_E_INVALID;
6595 core_if->core_params->ic_usb_cap = val;
6599 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
6601 return core_if->core_params->ic_usb_cap;
6604 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
6609 if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
6610 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
6611 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
6612 return -DWC_E_INVALID;
6616 && (core_if->snpsid < OTG_CORE_REV_2_81a
6617 || !dwc_otg_get_param_thr_ctl(core_if))) {
6620 && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
6625 if (dwc_otg_param_initialized
6626 (core_if->core_params->ahb_thr_ratio)) {
6628 ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
6631 retval = -DWC_E_INVALID;
6635 core_if->core_params->ahb_thr_ratio = val;
6639 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
6641 return core_if->core_params->ahb_thr_ratio;
6644 int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
6648 hwcfg4_data_t hwcfg4 = {.d32 = 0 };
6649 hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
6651 if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
6652 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
6653 DWC_WARN("power_down must be 0 - 2\n");
6654 return -DWC_E_INVALID;
6657 if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
6661 && ((core_if->snpsid < OTG_CORE_REV_3_00a)
6662 || (hwcfg4.b.xhiber == 0))) {
6666 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
6668 ("%d invalid for parameter power_down. Check HW configuration.\n",
6671 retval = -DWC_E_INVALID;
6674 core_if->core_params->power_down = val;
6678 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
6680 return core_if->core_params->power_down;
6683 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
6688 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6689 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
6690 DWC_WARN("reload_ctl must be 0 or 1\n");
6691 return -DWC_E_INVALID;
6694 if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
6698 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
6699 DWC_ERROR("%d invalid for parameter reload_ctl."
6700 "Check HW configuration.\n", val);
6702 retval = -DWC_E_INVALID;
6705 core_if->core_params->reload_ctl = val;
6709 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
6711 return core_if->core_params->reload_ctl;
6714 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
6719 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6720 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
6721 DWC_WARN("dev_out_nak must be 0 or 1\n");
6722 return -DWC_E_INVALID;
6725 if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
6726 !(core_if->core_params->dma_desc_enable))) {
6730 if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
6731 DWC_ERROR("%d invalid for parameter dev_out_nak."
6732 "Check HW configuration.\n", val);
6734 retval = -DWC_E_INVALID;
6737 core_if->core_params->dev_out_nak = val;
6741 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
6743 return core_if->core_params->dev_out_nak;
6746 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
6751 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6752 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
6753 DWC_WARN("cont_on_bna must be 0 or 1\n");
6754 return -DWC_E_INVALID;
6757 if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
6758 !(core_if->core_params->dma_desc_enable))) {
6762 if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
6763 DWC_ERROR("%d invalid for parameter cont_on_bna."
6764 "Check HW configuration.\n", val);
6766 retval = -DWC_E_INVALID;
6769 core_if->core_params->cont_on_bna = val;
6773 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
6775 return core_if->core_params->cont_on_bna;
6778 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
6783 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6784 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
6785 DWC_WARN("ahb_single must be 0 or 1\n");
6786 return -DWC_E_INVALID;
6789 if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
6793 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
6794 DWC_ERROR("%d invalid for parameter ahb_single."
6795 "Check HW configuration.\n", val);
6797 retval = -DWC_E_INVALID;
6800 core_if->core_params->ahb_single = val;
6804 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
6806 return core_if->core_params->ahb_single;
6809 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
6813 if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6814 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
6816 ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
6817 return -DWC_E_INVALID;
6820 core_if->core_params->otg_ver = val;
6824 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
6826 return core_if->core_params->otg_ver;
6829 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
6831 gotgctl_data_t otgctl;
6832 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6833 return otgctl.b.hstnegscs;
6836 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
6838 gotgctl_data_t otgctl;
6839 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6840 return otgctl.b.sesreqscs;
6843 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
6845 if(core_if->otg_ver == 0) {
6846 gotgctl_data_t otgctl;
6847 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6848 otgctl.b.hnpreq = val;
6849 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
6851 core_if->otg_sts = val;
6855 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
6857 return core_if->snpsid;
6860 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
6862 gintsts_data_t gintsts;
6863 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6864 return gintsts.b.curmode;
6867 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
6869 gusbcfg_data_t usbcfg;
6870 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6871 return usbcfg.b.hnpcap;
6874 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
6876 gusbcfg_data_t usbcfg;
6877 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6878 usbcfg.b.hnpcap = val;
6879 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
6882 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
6884 gusbcfg_data_t usbcfg;
6885 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6886 return usbcfg.b.srpcap;
6889 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
6891 gusbcfg_data_t usbcfg;
6892 usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6893 usbcfg.b.srpcap = val;
6894 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
6897 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
6900 dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
6901 return dcfg.b.devspd;
6904 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
6907 dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
6908 dcfg.b.devspd = val;
6909 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
6912 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
6915 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6916 return hprt0.b.prtconnsts;
6919 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
6922 dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
6923 return dsts.b.enumspd;
6926 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
6929 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6930 return hprt0.b.prtpwr;
6934 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
6936 return core_if->hibernation_suspend;
6939 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
6942 hprt0.d32 = dwc_otg_read_hprt0(core_if);
6943 hprt0.b.prtpwr = val;
6944 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
6947 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
6950 hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6951 return hprt0.b.prtsusp;
6955 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
6958 hprt0.d32 = dwc_otg_read_hprt0(core_if);
6959 hprt0.b.prtsusp = val;
6960 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
6963 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
6966 hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
6967 return hfir.b.frint;
6971 void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
6975 fram_int = calc_frame_interval(core_if);
6976 hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
6977 if (!core_if->core_params->reload_ctl) {
6978 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
6979 "not set to 1.\nShould load driver with reload_ctl=1"
6980 " module parameter\n");
6985 if ((val < 3350) || (val > 4150)) {
6986 DWC_WARN("HFIR interval for HS core and 30 MHz"
6987 "clock freq should be from 3350 to 4150\n");
6992 if ((val < 26820) || (val > 33180)) {
6993 DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
6994 "clock freq should be from 26820 to 33180\n");
6999 if ((val < 5360) || (val > 6640)) {
7000 DWC_WARN("HFIR interval for HS core and 48 MHz"
7001 "clock freq should be from 5360 to 6640\n");
7006 if ((val < 42912) || (val > 53088)) {
7007 DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
7008 "clock freq should be from 42912 to 53088\n");
7013 if ((val < 6700) || (val > 8300)) {
7014 DWC_WARN("HFIR interval for HS core and 60 MHz"
7015 "clock freq should be from 6700 to 8300\n");
7020 if ((val < 53640) || (val > 65536)) {
7021 DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
7022 "clock freq should be from 53640 to 65536\n");
7027 DWC_WARN("Unknown frame interval\n");
7033 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
7036 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
7039 hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7040 return hcfg.b.modechtimen;
7044 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
7047 hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7048 hcfg.b.modechtimen = val;
7049 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
7052 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
7055 hprt0.d32 = dwc_otg_read_hprt0(core_if);
7056 hprt0.b.prtres = val;
7057 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7060 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
7063 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7064 return dctl.b.rmtwkupsig;
7067 uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if)
7070 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7071 return dctl.b.besl_reject;
7074 void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val)
7077 dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7078 dctl.b.besl_reject = val;
7079 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
7081 uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if)
7083 glpmcfg_data_t lpmcfg;
7084 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7085 return lpmcfg.b.hird_thres;
7088 void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val)
7090 glpmcfg_data_t lpmcfg;
7092 if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
7093 DWC_WARN("Wrong valaue for hird_thres\n");
7094 DWC_WARN("hird_thres must be 0-f\n");
7098 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7099 lpmcfg.b.hird_thres |= val;
7100 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7103 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
7105 glpmcfg_data_t lpmcfg;
7106 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7109 ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
7110 "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
7111 core_if->lx_state, lpmcfg.b.prt_sleep_sts);
7113 return lpmcfg.b.prt_sleep_sts;
7116 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
7118 glpmcfg_data_t lpmcfg;
7119 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7120 return lpmcfg.b.rem_wkup_en;
7123 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
7125 glpmcfg_data_t lpmcfg;
7126 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7127 return lpmcfg.b.appl_resp;
7130 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
7132 glpmcfg_data_t lpmcfg;
7133 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7134 lpmcfg.b.appl_resp = val;
7135 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7138 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
7140 glpmcfg_data_t lpmcfg;
7141 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7142 return lpmcfg.b.hsic_connect;
7145 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
7147 glpmcfg_data_t lpmcfg;
7148 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7149 lpmcfg.b.hsic_connect = val;
7150 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7153 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
7155 glpmcfg_data_t lpmcfg;
7156 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7157 return lpmcfg.b.inv_sel_hsic;
7161 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
7163 glpmcfg_data_t lpmcfg;
7164 lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7165 lpmcfg.b.inv_sel_hsic = val;
7166 DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7169 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
7171 return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7174 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
7176 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
7179 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
7181 return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7184 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
7186 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
7189 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
7191 return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
7194 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
7196 DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
7199 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
7201 return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
7204 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
7206 DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
7209 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
7211 return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
7214 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
7216 DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
7219 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
7221 return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
7224 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
7226 DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
7229 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
7231 return DWC_READ_REG32(core_if->host_if->hprt0);
7235 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
7237 DWC_WRITE_REG32(core_if->host_if->hprt0, val);
7240 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
7242 return DWC_READ_REG32(&core_if->core_global_regs->guid);
7245 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
7247 DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
7250 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
7252 return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
7255 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
7257 return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
7261 * Start the SRP timer to detect when the SRP does not complete within
7264 * @param core_if the pointer to core_if strucure.
7266 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
7268 core_if->srp_timer_started = 1;
7269 DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
7272 void dwc_otg_initiate_srp(void * p)
7274 dwc_otg_core_if_t * core_if = p;
7275 uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
7279 val.d32 = DWC_READ_REG32(addr);
7281 DWC_ERROR("Session Request Already active!\n");
7285 DWC_INFO("Session Request Initated\n"); //NOTICE
7286 mem.d32 = DWC_READ_REG32(addr);
7288 DWC_WRITE_REG32(addr, mem.d32);
7290 /* Start the SRP timer */
7291 dwc_otg_pcd_start_srp_timer(core_if);
7295 int dwc_otg_check_haps_status(dwc_otg_core_if_t * core_if)
7299 if(DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff)