drivers/usb/dwc_otg_310/dwc_otg_cil.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg/linux/drivers/dwc_otg_cil.c $
   3  * $Revision: #198 $
   4  * $Date: 2012/12/21 $
   5  * $Change: 2131568 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  *
  36  * The Core Interface Layer provides basic services for accessing and
  37  * managing the DWC_otg hardware. These services are used by both the
  38  * Host Controller Driver and the Peripheral Controller Driver.
  39  *
  40  * The CIL manages the memory map for the core so that the HCD and PCD
  41  * don't have to do this separately. It also handles basic tasks like
  42  * reading/writing the registers and data FIFOs in the controller.
  43  * Some of the data access functions provide encapsulation of several
  44  * operations required to perform a task, such as writing multiple
  45  * registers to start a transfer. Finally, the CIL performs basic
  46  * services that are not specific to either the host or device modes
  47  * of operation. These services include management of the OTG Host
  48  * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A
  49  * Diagnostic API is also provided to allow testing of the controller
  50  * hardware.
  51  *
  52  * The Core Interface Layer has the following requirements:
  53  * - Provides basic controller operations.
  54  * - Minimal use of OS services.
  55  * - The OS services used will be abstracted by using inline functions
  56  *       or macros.
  57  *
  58  */
  59
  60 #include "common_port/dwc_os.h"
  61 #include "dwc_otg_regs.h"
  62 #include "dwc_otg_cil.h"
  63 #include "dwc_otg_driver.h"
  64 #include "usbdev_rk.h"
  65 #include "dwc_otg_hcd.h"
  66
  67 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if);
  68
  69 /**
  70  * This function is called to initialize the DWC_otg CSR data
  71  * structures. The register addresses in the device and host
  72  * structures are initialized from the base address supplied by the
  73  * caller. The calling function must make the OS calls to get the
  74  * base address of the DWC_otg controller registers. The core_params
  75  * argument holds the parameters that specify how the core should be
  76  * configured.
  77  *
  78  * @param reg_base_addr Base address of DWC_otg core registers
  79  *
  80  */
  81 dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t * reg_base_addr)
  82 {
  83         dwc_otg_core_if_t *core_if = 0;
  84         dwc_otg_dev_if_t *dev_if = 0;
  85         dwc_otg_host_if_t *host_if = 0;
  86         uint8_t *reg_base = (uint8_t *) reg_base_addr;
  87         int i = 0;
  88
  89         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, reg_base_addr);
  90
  91         core_if = DWC_ALLOC(sizeof(dwc_otg_core_if_t));
  92
  93         if (core_if == NULL) {
  94                 DWC_DEBUGPL(DBG_CIL,
  95                             "Allocation of dwc_otg_core_if_t failed\n");
  96                 return 0;
  97         }
  98         core_if->core_global_regs = (dwc_otg_core_global_regs_t *) reg_base;
  99
 100         /*
 101          * Allocate the Device Mode structures.
 102          */
 103         dev_if = DWC_ALLOC(sizeof(dwc_otg_dev_if_t));
 104
 105         if (dev_if == NULL) {
 106                 DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n");
 107                 DWC_FREE(core_if);
 108                 return 0;
 109         }
 110
 111         dev_if->dev_global_regs =
 112             (dwc_otg_device_global_regs_t *) (reg_base +
 113                                               DWC_DEV_GLOBAL_REG_OFFSET);
 114
 115         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 116                 dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *)
 117                     (reg_base + DWC_DEV_IN_EP_REG_OFFSET +
 118                      (i * DWC_EP_REG_OFFSET));
 119
 120                 dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *)
 121                     (reg_base + DWC_DEV_OUT_EP_REG_OFFSET +
 122                      (i * DWC_EP_REG_OFFSET));
 123                 DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n",
 124                             i, &dev_if->in_ep_regs[i]->diepctl);
 125                 DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n",
 126                             i, &dev_if->out_ep_regs[i]->doepctl);
 127         }
 128
 129         dev_if->speed = 0;      // unknown
 130
 131         core_if->dev_if = dev_if;
 132
 133         /*
 134          * Allocate the Host Mode structures.
 135          */
 136         host_if = DWC_ALLOC(sizeof(dwc_otg_host_if_t));
 137
 138         if (host_if == NULL) {
 139                 DWC_DEBUGPL(DBG_CIL,
 140                             "Allocation of dwc_otg_host_if_t failed\n");
 141                 DWC_FREE(dev_if);
 142                 DWC_FREE(core_if);
 143                 return 0;
 144         }
 145
 146         host_if->host_global_regs = (dwc_otg_host_global_regs_t *)
 147             (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET);
 148
 149         host_if->hprt0 =
 150             (uint32_t *) (reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET);
 151
 152         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 153                 host_if->hc_regs[i] = (dwc_otg_hc_regs_t *)
 154                     (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET +
 155                      (i * DWC_OTG_CHAN_REGS_OFFSET));
 156                 DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n",
 157                             i, &host_if->hc_regs[i]->hcchar);
 158         }
 159
 160         host_if->num_host_channels = MAX_EPS_CHANNELS;
 161         core_if->host_if = host_if;
 162
 163         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 164                 core_if->data_fifo[i] =
 165                     (uint32_t *) (reg_base + DWC_OTG_DATA_FIFO_OFFSET +
 166                                   (i * DWC_OTG_DATA_FIFO_SIZE));
 167                 DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08lx\n",
 168                             i, (unsigned long)core_if->data_fifo[i]);
 169         }
 170
 171         core_if->pcgcctl = (uint32_t *) (reg_base + DWC_OTG_PCGCCTL_OFFSET);
 172
 173         /* Initiate lx_state to L3 disconnected state */
 174         core_if->lx_state = DWC_OTG_L3;
 175         /*
 176          * Store the contents of the hardware configuration registers here for
 177          * easy access later.
 178          */
 179         core_if->hwcfg1.d32 =
 180             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg1);
 181         core_if->hwcfg2.d32 =
 182             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
 183         core_if->hwcfg3.d32 =
 184             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg3);
 185         core_if->hwcfg4.d32 =
 186             DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
 187
 188         /* do not get HPTXFSIZ here, it's unused.
 189          * set global_regs->hptxfsiz in dwc_otg_core_host_init.
 190          * for 3.10a version, host20 FIFO can't be configed,
 191          * because host20 hwcfg2.b.dynamic_fifo = 0.
 192          */
 193 #if 0
 194         /* Force host mode to get HPTXFSIZ exact power on value */
 195         {
 196                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
 197                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 198                 gusbcfg.b.force_host_mode = 1;
 199                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
 200                 dwc_mdelay(100);
 201                 core_if->hptxfsiz.d32 =
 202                     DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 203                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 204                 gusbcfg.b.force_host_mode = 0;
 205                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
 206                 dwc_mdelay(100);
 207         }
 208 #endif
 209
 210         DWC_DEBUGPL(DBG_CILV, "hwcfg1=%08x\n", core_if->hwcfg1.d32);
 211         DWC_DEBUGPL(DBG_CILV, "hwcfg2=%08x\n", core_if->hwcfg2.d32);
 212         DWC_DEBUGPL(DBG_CILV, "hwcfg3=%08x\n", core_if->hwcfg3.d32);
 213         DWC_DEBUGPL(DBG_CILV, "hwcfg4=%08x\n", core_if->hwcfg4.d32);
 214
 215         core_if->hcfg.d32 =
 216             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 217         core_if->dcfg.d32 =
 218             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 219
 220         DWC_DEBUGPL(DBG_CILV, "hcfg=%08x\n", core_if->hcfg.d32);
 221         DWC_DEBUGPL(DBG_CILV, "dcfg=%08x\n", core_if->dcfg.d32);
 222
 223         DWC_DEBUGPL(DBG_CILV, "op_mode=%0x\n", core_if->hwcfg2.b.op_mode);
 224         DWC_DEBUGPL(DBG_CILV, "arch=%0x\n", core_if->hwcfg2.b.architecture);
 225         DWC_DEBUGPL(DBG_CILV, "num_dev_ep=%d\n", core_if->hwcfg2.b.num_dev_ep);
 226         DWC_DEBUGPL(DBG_CILV, "num_host_chan=%d\n",
 227                     core_if->hwcfg2.b.num_host_chan);
 228         DWC_DEBUGPL(DBG_CILV, "nonperio_tx_q_depth=0x%0x\n",
 229                     core_if->hwcfg2.b.nonperio_tx_q_depth);
 230         DWC_DEBUGPL(DBG_CILV, "host_perio_tx_q_depth=0x%0x\n",
 231                     core_if->hwcfg2.b.host_perio_tx_q_depth);
 232         DWC_DEBUGPL(DBG_CILV, "dev_token_q_depth=0x%0x\n",
 233                     core_if->hwcfg2.b.dev_token_q_depth);
 234
 235         DWC_DEBUGPL(DBG_CILV, "Total FIFO SZ=%d\n",
 236                     core_if->hwcfg3.b.dfifo_depth);
 237         DWC_DEBUGPL(DBG_CILV, "xfer_size_cntr_width=%0x\n",
 238                     core_if->hwcfg3.b.xfer_size_cntr_width);
 239
 240         /*
 241          * Set the SRP sucess bit for FS-I2c
 242          */
 243         core_if->srp_success = 0;
 244         core_if->srp_timer_started = 0;
 245
 246         /*
 247          * Create new workqueue and init works
 248          */
 249         core_if->wq_otg = DWC_WORKQ_ALLOC("dwc_otg");
 250         if (core_if->wq_otg == 0) {
 251                 DWC_WARN("DWC_WORKQ_ALLOC failed\n");
 252                 DWC_FREE(host_if);
 253                 DWC_FREE(dev_if);
 254                 DWC_FREE(core_if);
 255                 return 0;
 256         }
 257
 258         core_if->snpsid = DWC_READ_REG32(&core_if->core_global_regs->gsnpsid);
 259         DWC_PRINTF("%p\n",&core_if->core_global_regs->gsnpsid);
 260         DWC_PRINTF("Core Release: %x.%x%x%x\n",
 261                    (core_if->snpsid >> 12 & 0xF),
 262                    (core_if->snpsid >> 8 & 0xF),
 263                    (core_if->snpsid >> 4 & 0xF), (core_if->snpsid & 0xF));
 264
 265         core_if->wkp_tasklet = DWC_TASK_ALLOC("wkp_tasklet", w_wakeup_detected, core_if);
 266
 267         if (dwc_otg_setup_params(core_if)) {
 268                 DWC_WARN("Error while setting core params\n");
 269         }
 270
 271         core_if->hibernation_suspend = 0;
 272         if (core_if->otg_ver)
 273                 core_if->test_mode = 0;
 274
 275         /** ADP initialization */
 276         dwc_otg_adp_init(core_if);
 277
 278         return core_if;
 279 }
 280
 281 /**
 282  * This function frees the structures allocated by dwc_otg_cil_init().
 283  *
 284  * @param core_if The core interface pointer returned from
 285  *                dwc_otg_cil_init().
 286  *
 287  */
 288 void dwc_otg_cil_remove(dwc_otg_core_if_t * core_if)
 289 {
 290         dctl_data_t dctl = {.d32 = 0 };
 291         /* Disable all interrupts */
 292         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 1, 0);
 293         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, 0);
 294
 295         dctl.b.sftdiscon = 1;
 296         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
 297                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0,
 298                                  dctl.d32);
 299         }
 300
 301         if (core_if->wq_otg) {
 302                 DWC_WORKQ_WAIT_WORK_DONE(core_if->wq_otg, 500);
 303                 DWC_WORKQ_FREE(core_if->wq_otg);
 304         }
 305         if (core_if->dev_if) {
 306                 DWC_FREE(core_if->dev_if);
 307         }
 308         if (core_if->host_if) {
 309                 DWC_FREE(core_if->host_if);
 310         }
 311
 312         /** Remove ADP Stuff  */
 313         dwc_otg_adp_remove(core_if);
 314         if (core_if->core_params) {
 315                 DWC_FREE(core_if->core_params);
 316         }
 317         if (core_if->wkp_tasklet){
 318                 DWC_TASK_FREE(core_if->wkp_tasklet);
 319         }
 320         if (core_if->srp_timer) {
 321                 DWC_TIMER_FREE(core_if->srp_timer);
 322         }
 323         DWC_FREE(core_if);
 324 }
 325
 326 /**
 327  * This function enables the controller's Global Interrupt in the AHB Config
 328  * register.
 329  *
 330  * @param core_if Programming view of DWC_otg controller.
 331  */
 332 void dwc_otg_enable_global_interrupts(dwc_otg_core_if_t * core_if)
 333 {
 334         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 335         ahbcfg.b.glblintrmsk = 1;       /* Enable interrupts */
 336         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32);
 337 }
 338
 339 /**
 340  * This function disables the controller's Global Interrupt in the AHB Config
 341  * register.
 342  *
 343  * @param core_if Programming view of DWC_otg controller.
 344  */
 345 void dwc_otg_disable_global_interrupts(dwc_otg_core_if_t * core_if)
 346 {
 347         gahbcfg_data_t ahbcfg = {.d32 = 0 };
 348         ahbcfg.b.glblintrmsk = 1;       /* Disable interrupts */
 349         DWC_MODIFY_REG32(&core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0);
 350 }
 351
 352 /**
 353  * This function initializes the commmon interrupts, used in both
 354  * device and host modes.
 355  *
 356  * @param core_if Programming view of the DWC_otg controller
 357  *
 358  */
 359 static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t * core_if)
 360 {
 361         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
 362         gintmsk_data_t intr_mask = {.d32 = 0 };
 363
 364         /* Clear any pending OTG Interrupts */
 365         DWC_WRITE_REG32(&global_regs->gotgint, 0xFFFFFFFF);
 366
 367         /* Clear any pending interrupts */
 368         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
 369
 370         /*
 371          * Enable the interrupts in the GINTMSK.
 372          */
 373         intr_mask.b.modemismatch = 1;
 374         intr_mask.b.otgintr = 1;
 375
 376         if (!core_if->dma_enable) {
 377                 intr_mask.b.rxstsqlvl = 1;
 378         }
 379
 380         intr_mask.b.conidstschng = 1;
 381         intr_mask.b.wkupintr = 1;
 382         intr_mask.b.disconnect = 0;
 383         intr_mask.b.usbsuspend = 1;
 384         //intr_mask.b.sessreqintr = 1;
 385 #ifdef CONFIG_USB_DWC_OTG_LPM
 386         if (core_if->core_params->lpm_enable) {
 387                 intr_mask.b.lpmtranrcvd = 1;
 388         }
 389 #endif
 390         DWC_WRITE_REG32(&global_regs->gintmsk, intr_mask.d32);
 391 }
 392
 393 /*
 394  * The restore operation is modified to support Synopsys Emulated Powerdown and
 395  * Hibernation. This function is for exiting from Device mode hibernation by
 396  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 397  * @param core_if Programming view of DWC_otg controller.
 398  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 399  * @param reset - indicates whether resume is initiated by Reset.
 400  */
 401 int dwc_otg_device_hibernation_restore(dwc_otg_core_if_t * core_if,
 402                                        int rem_wakeup, int reset)
 403 {
 404         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 405         pcgcctl_data_t pcgcctl = {.d32 = 0 };
 406         dctl_data_t dctl = {.d32 = 0 };
 407
 408         int timeout = 2000;
 409
 410         if (!core_if->hibernation_suspend) {
 411                 DWC_PRINTF("Already exited from Hibernation\n");
 412                 return 1;
 413         }
 414
 415         DWC_DEBUGPL(DBG_PCD, "%s called\n", __FUNCTION__);
 416         /* Switch-on voltage to the core */
 417         gpwrdn.b.pwrdnswtch = 1;
 418         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 419         dwc_udelay(10);
 420
 421         /* Reset core */
 422         gpwrdn.d32 = 0;
 423         gpwrdn.b.pwrdnrstn = 1;
 424         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 425         dwc_udelay(10);
 426
 427         /* Assert Restore signal */
 428         gpwrdn.d32 = 0;
 429         gpwrdn.b.restore = 1;
 430         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 431         dwc_udelay(10);
 432
 433         /* Disable power clamps */
 434         gpwrdn.d32 = 0;
 435         gpwrdn.b.pwrdnclmp = 1;
 436         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 437
 438         if (rem_wakeup) {
 439                 dwc_udelay(70);
 440         }
 441
 442         /* Deassert Reset core */
 443         gpwrdn.d32 = 0;
 444         gpwrdn.b.pwrdnrstn = 1;
 445         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 446         dwc_udelay(10);
 447
 448         /* Disable PMU interrupt */
 449         gpwrdn.d32 = 0;
 450         gpwrdn.b.pmuintsel = 1;
 451         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 452
 453         /* Mask interrupts from gpwrdn */
 454         gpwrdn.d32 = 0;
 455         gpwrdn.b.connect_det_msk = 1;
 456         gpwrdn.b.srp_det_msk = 1;
 457         gpwrdn.b.disconn_det_msk = 1;
 458         gpwrdn.b.rst_det_msk = 1;
 459         gpwrdn.b.lnstchng_msk = 1;
 460         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 461
 462         /* Indicates that we are going out from hibernation */
 463         core_if->hibernation_suspend = 0;
 464
 465         /*
 466          * Set Restore Essential Regs bit in PCGCCTL register, restore_mode = 1
 467          * indicates restore from remote_wakeup
 468          */
 469         restore_essential_regs(core_if, rem_wakeup, 0);
 470
 471         /*
 472          * Wait a little for seeing new value of variable hibernation_suspend if
 473          * Restore done interrupt received before polling
 474          */
 475         dwc_udelay(10);
 476
 477         if (core_if->hibernation_suspend == 0) {
 478                 /*
 479                  * Wait For Restore_done Interrupt. This mechanism of polling the
 480                  * interrupt is introduced to avoid any possible race conditions
 481                  */
 482                 do {
 483                         gintsts_data_t gintsts;
 484                         gintsts.d32 =
 485                             DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 486                         if (gintsts.b.restoredone) {
 487                                 gintsts.d32 = 0;
 488                                 gintsts.b.restoredone = 1;
 489                                 DWC_WRITE_REG32(&core_if->core_global_regs->
 490                                                 gintsts, gintsts.d32);
 491                                 DWC_PRINTF("Restore Done Interrupt seen\n");
 492                                 break;
 493                         }
 494                         dwc_udelay(10);
 495                 } while (--timeout);
 496                 if (!timeout) {
 497                         DWC_PRINTF("Restore Done interrupt wasn't generated here\n");
 498                 }
 499         }
 500         /* Clear all pending interupts */
 501         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 502
 503         /* De-assert Restore */
 504         gpwrdn.d32 = 0;
 505         gpwrdn.b.restore = 1;
 506         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 507         dwc_udelay(10);
 508
 509         if (!rem_wakeup) {
 510                 pcgcctl.d32 = 0;
 511                 pcgcctl.b.rstpdwnmodule = 1;
 512                 DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
 513         }
 514
 515         /* Restore GUSBCFG and DCFG */
 516         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 517                         core_if->gr_backup->gusbcfg_local);
 518         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
 519                         core_if->dr_backup->dcfg);
 520
 521         /* De-assert Wakeup Logic */
 522         gpwrdn.d32 = 0;
 523         gpwrdn.b.pmuactv = 1;
 524         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 525         dwc_udelay(10);
 526
 527         if (!rem_wakeup) {
 528                 /* Set Device programming done bit */
 529                 dctl.b.pwronprgdone = 1;
 530                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
 531         } else {
 532                 /* Start Remote Wakeup Signaling */
 533                 dctl.d32 = core_if->dr_backup->dctl;
 534                 dctl.b.rmtwkupsig = 1;
 535                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
 536         }
 537
 538         dwc_mdelay(2);
 539         /* Clear all pending interupts */
 540         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 541
 542         /* Restore global registers */
 543         dwc_otg_restore_global_regs(core_if);
 544         /* Restore device global registers */
 545         dwc_otg_restore_dev_regs(core_if, rem_wakeup);
 546
 547         if (rem_wakeup) {
 548                 dwc_mdelay(7);
 549                 dctl.d32 = 0;
 550                 dctl.b.rmtwkupsig = 1;
 551                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32, 0);
 552         }
 553
 554         core_if->hibernation_suspend = 0;
 555         /* The core will be in ON STATE */
 556         core_if->lx_state = DWC_OTG_L0;
 557         DWC_PRINTF("Hibernation recovery completes here\n");
 558
 559         return 1;
 560 }
 561
 562 /*
 563  * The restore operation is modified to support Synopsys Emulated Powerdown and
 564  * Hibernation. This function is for exiting from Host mode hibernation by
 565  * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
 566  * @param core_if Programming view of DWC_otg controller.
 567  * @param rem_wakeup - indicates whether resume is initiated by Device or Host.
 568  * @param reset - indicates whether resume is initiated by Reset.
 569  */
 570 int dwc_otg_host_hibernation_restore(dwc_otg_core_if_t * core_if,
 571                                      int rem_wakeup, int reset)
 572 {
 573         gpwrdn_data_t gpwrdn = {.d32 = 0 };
 574         hprt0_data_t hprt0 = {.d32 = 0 };
 575
 576         int timeout = 2000;
 577
 578         DWC_DEBUGPL(DBG_HCD, "%s called\n", __FUNCTION__);
 579         /* Switch-on voltage to the core */
 580         gpwrdn.b.pwrdnswtch = 1;
 581         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 582         dwc_udelay(10);
 583
 584         /* Reset core */
 585         gpwrdn.d32 = 0;
 586         gpwrdn.b.pwrdnrstn = 1;
 587         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 588         dwc_udelay(10);
 589
 590         /* Assert Restore signal */
 591         gpwrdn.d32 = 0;
 592         gpwrdn.b.restore = 1;
 593         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 594         dwc_udelay(10);
 595
 596         /* Disable power clamps */
 597         gpwrdn.d32 = 0;
 598         gpwrdn.b.pwrdnclmp = 1;
 599         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 600
 601         if (!rem_wakeup) {
 602                 dwc_udelay(50);
 603         }
 604
 605         /* Deassert Reset core */
 606         gpwrdn.d32 = 0;
 607         gpwrdn.b.pwrdnrstn = 1;
 608         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, 0, gpwrdn.d32);
 609         dwc_udelay(10);
 610
 611         /* Disable PMU interrupt */
 612         gpwrdn.d32 = 0;
 613         gpwrdn.b.pmuintsel = 1;
 614         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 615
 616         gpwrdn.d32 = 0;
 617         gpwrdn.b.connect_det_msk = 1;
 618         gpwrdn.b.srp_det_msk = 1;
 619         gpwrdn.b.disconn_det_msk = 1;
 620         gpwrdn.b.rst_det_msk = 1;
 621         gpwrdn.b.lnstchng_msk = 1;
 622         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 623
 624         /* Indicates that we are going out from hibernation */
 625         core_if->hibernation_suspend = 0;
 626
 627         /* Set Restore Essential Regs bit in PCGCCTL register */
 628         restore_essential_regs(core_if, rem_wakeup, 1);
 629
 630         /* Wait a little for seeing new value of variable hibernation_suspend if
 631          * Restore done interrupt received before polling */
 632         dwc_udelay(10);
 633
 634         if (core_if->hibernation_suspend == 0) {
 635                 /* Wait For Restore_done Interrupt. This mechanism of polling the
 636                  * interrupt is introduced to avoid any possible race conditions
 637                  */
 638                 do {
 639                         gintsts_data_t gintsts;
 640                         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
 641                         if (gintsts.b.restoredone) {
 642                                 gintsts.d32 = 0;
 643                                 gintsts.b.restoredone = 1;
 644                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
 645                                 DWC_DEBUGPL(DBG_HCD,"Restore Done Interrupt seen\n");
 646                                 break;
 647                         }
 648                         dwc_udelay(10);
 649                 } while (--timeout);
 650                 if (!timeout) {
 651                         DWC_WARN("Restore Done interrupt wasn't generated\n");
 652                 }
 653         }
 654
 655         /* Set the flag's value to 0 again after receiving restore done interrupt */
 656         core_if->hibernation_suspend = 0;
 657
 658         /* This step is not described in functional spec but if not wait for this
 659          * delay, mismatch interrupts occurred because just after restore core is
 660          * in Device mode(gintsts.curmode == 0) */
 661         dwc_mdelay(100);
 662
 663         /* Clear all pending interrupts */
 664         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 665
 666         /* De-assert Restore */
 667         gpwrdn.d32 = 0;
 668         gpwrdn.b.restore = 1;
 669         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 670         dwc_udelay(10);
 671
 672         /* Restore GUSBCFG and HCFG */
 673         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg,
 674                         core_if->gr_backup->gusbcfg_local);
 675         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
 676                         core_if->hr_backup->hcfg_local);
 677
 678         /* De-assert Wakeup Logic */
 679         gpwrdn.d32 = 0;
 680         gpwrdn.b.pmuactv = 1;
 681         DWC_MODIFY_REG32(&core_if->core_global_regs->gpwrdn, gpwrdn.d32, 0);
 682         dwc_udelay(10);
 683
 684         /* Start the Resume operation by programming HPRT0 */
 685         hprt0.d32 = core_if->hr_backup->hprt0_local;
 686         hprt0.b.prtpwr = 1;
 687         hprt0.b.prtena = 0;
 688         hprt0.b.prtsusp = 0;
 689         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 690
 691         DWC_PRINTF("Resume Starts Now\n");
 692         if (!reset) {           // Indicates it is Resume Operation
 693                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 694                 hprt0.b.prtres = 1;
 695                 hprt0.b.prtpwr = 1;
 696                 hprt0.b.prtena = 0;
 697                 hprt0.b.prtsusp = 0;
 698                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 699
 700                 if (!rem_wakeup)
 701                         hprt0.b.prtres = 0;
 702                 /* Wait for Resume time and then program HPRT again */
 703                 dwc_mdelay(100);
 704                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 705
 706         } else {                // Indicates it is Reset Operation
 707                 hprt0.d32 = core_if->hr_backup->hprt0_local;
 708                 hprt0.b.prtrst = 1;
 709                 hprt0.b.prtpwr = 1;
 710                 hprt0.b.prtena = 0;
 711                 hprt0.b.prtsusp = 0;
 712                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 713                 /* Wait for Reset time and then program HPRT again */
 714                 dwc_mdelay(60);
 715                 hprt0.b.prtrst = 0;
 716                 DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 717         }
 718         /* Clear all interrupt status */
 719         hprt0.d32 = dwc_otg_read_hprt0(core_if);
 720         hprt0.b.prtconndet = 1;
 721         hprt0.b.prtenchng = 1;
 722         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
 723
 724         /* Clear all pending interupts */
 725         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 726
 727         /* Restore global registers */
 728         dwc_otg_restore_global_regs(core_if);
 729         /* Restore host global registers */
 730         dwc_otg_restore_host_regs(core_if, reset);
 731
 732         /* The core will be in ON STATE */
 733         core_if->lx_state = DWC_OTG_L0;
 734         DWC_PRINTF("Hibernation recovery is complete here\n");
 735         return 0;
 736 }
 737
 738 /** Saves some register values into system memory. */
 739 int dwc_otg_save_global_regs(dwc_otg_core_if_t * core_if)
 740 {
 741         struct dwc_otg_global_regs_backup *gr;
 742         int i;
 743
 744         gr = core_if->gr_backup;
 745         if (!gr) {
 746                 gr = DWC_ALLOC(sizeof(*gr));
 747                 if (!gr) {
 748                         return -DWC_E_NO_MEMORY;
 749                 }
 750                 core_if->gr_backup = gr;
 751         }
 752
 753         gr->gotgctl_local = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
 754         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 755         gr->gahbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gahbcfg);
 756         gr->gusbcfg_local = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
 757         gr->grxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
 758         gr->gnptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
 759         gr->hptxfsiz_local = DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
 760 #ifdef CONFIG_USB_DWC_OTG_LPM
 761         gr->glpmcfg_local = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
 762 #endif
 763         gr->gi2cctl_local = DWC_READ_REG32(&core_if->core_global_regs->gi2cctl);
 764         gr->pcgcctl_local = DWC_READ_REG32(core_if->pcgcctl);
 765         gr->gdfifocfg_local =
 766             DWC_READ_REG32(&core_if->core_global_regs->gdfifocfg);
 767         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 768                 gr->dtxfsiz_local[i] =
 769                     DWC_READ_REG32(&(core_if->core_global_regs->dtxfsiz[i]));
 770         }
 771
 772         DWC_DEBUGPL(DBG_ANY, "===========Backing Global registers==========\n");
 773         DWC_DEBUGPL(DBG_ANY, "Backed up gotgctl   = %08x\n", gr->gotgctl_local);
 774         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 775         DWC_DEBUGPL(DBG_ANY, "Backed up gahbcfg   = %08x\n", gr->gahbcfg_local);
 776         DWC_DEBUGPL(DBG_ANY, "Backed up gusbcfg   = %08x\n", gr->gusbcfg_local);
 777         DWC_DEBUGPL(DBG_ANY, "Backed up grxfsiz   = %08x\n", gr->grxfsiz_local);
 778         DWC_DEBUGPL(DBG_ANY, "Backed up gnptxfsiz = %08x\n",
 779                     gr->gnptxfsiz_local);
 780         DWC_DEBUGPL(DBG_ANY, "Backed up hptxfsiz  = %08x\n",
 781                     gr->hptxfsiz_local);
 782 #ifdef CONFIG_USB_DWC_OTG_LPM
 783         DWC_DEBUGPL(DBG_ANY, "Backed up glpmcfg   = %08x\n", gr->glpmcfg_local);
 784 #endif
 785         DWC_DEBUGPL(DBG_ANY, "Backed up gi2cctl   = %08x\n", gr->gi2cctl_local);
 786         DWC_DEBUGPL(DBG_ANY, "Backed up pcgcctl   = %08x\n", gr->pcgcctl_local);
 787         DWC_DEBUGPL(DBG_ANY,"Backed up gdfifocfg   = %08x\n",gr->gdfifocfg_local);
 788
 789         return 0;
 790 }
 791
 792 /** Saves GINTMSK register before setting the msk bits. */
 793 int dwc_otg_save_gintmsk_reg(dwc_otg_core_if_t * core_if)
 794 {
 795         struct dwc_otg_global_regs_backup *gr;
 796
 797         gr = core_if->gr_backup;
 798         if (!gr) {
 799                 gr = DWC_ALLOC(sizeof(*gr));
 800                 if (!gr) {
 801                         return -DWC_E_NO_MEMORY;
 802                 }
 803                 core_if->gr_backup = gr;
 804         }
 805
 806         gr->gintmsk_local = DWC_READ_REG32(&core_if->core_global_regs->gintmsk);
 807
 808         DWC_DEBUGPL(DBG_ANY,"=============Backing GINTMSK registers============\n");
 809         DWC_DEBUGPL(DBG_ANY, "Backed up gintmsk   = %08x\n", gr->gintmsk_local);
 810
 811         return 0;
 812 }
 813
 814 int dwc_otg_save_dev_regs(dwc_otg_core_if_t * core_if)
 815 {
 816         struct dwc_otg_dev_regs_backup *dr;
 817         int i;
 818
 819         dr = core_if->dr_backup;
 820         if (!dr) {
 821                 dr = DWC_ALLOC(sizeof(*dr));
 822                 if (!dr) {
 823                         return -DWC_E_NO_MEMORY;
 824                 }
 825                 core_if->dr_backup = dr;
 826         }
 827
 828         dr->dcfg = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
 829         dr->dctl = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
 830         dr->daintmsk =
 831             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->daintmsk);
 832         dr->diepmsk =
 833             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->diepmsk);
 834         dr->doepmsk =
 835             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->doepmsk);
 836
 837         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 838                 dr->diepctl[i] =
 839                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl);
 840                 dr->dieptsiz[i] =
 841                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz);
 842                 dr->diepdma[i] =
 843                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma);
 844         }
 845
 846         DWC_DEBUGPL(DBG_ANY,
 847                     "=============Backing Host registers==============\n");
 848         DWC_DEBUGPL(DBG_ANY, "Backed up dcfg            = %08x\n", dr->dcfg);
 849         DWC_DEBUGPL(DBG_ANY, "Backed up dctl        = %08x\n", dr->dctl);
 850         DWC_DEBUGPL(DBG_ANY, "Backed up daintmsk            = %08x\n",
 851                     dr->daintmsk);
 852         DWC_DEBUGPL(DBG_ANY, "Backed up diepmsk        = %08x\n", dr->diepmsk);
 853         DWC_DEBUGPL(DBG_ANY, "Backed up doepmsk        = %08x\n", dr->doepmsk);
 854         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 855                 DWC_DEBUGPL(DBG_ANY, "Backed up diepctl[%d]        = %08x\n", i,
 856                             dr->diepctl[i]);
 857                 DWC_DEBUGPL(DBG_ANY, "Backed up dieptsiz[%d]        = %08x\n",
 858                             i, dr->dieptsiz[i]);
 859                 DWC_DEBUGPL(DBG_ANY, "Backed up diepdma[%d]        = %08x\n", i,
 860                             dr->diepdma[i]);
 861         }
 862
 863         return 0;
 864 }
 865
 866 int dwc_otg_save_host_regs(dwc_otg_core_if_t * core_if)
 867 {
 868         struct dwc_otg_host_regs_backup *hr;
 869         int i;
 870
 871         hr = core_if->hr_backup;
 872         if (!hr) {
 873                 hr = DWC_ALLOC(sizeof(*hr));
 874                 if (!hr) {
 875                         return -DWC_E_NO_MEMORY;
 876                 }
 877                 core_if->hr_backup = hr;
 878         }
 879
 880         hr->hcfg_local =
 881             DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
 882         hr->haintmsk_local =
 883             DWC_READ_REG32(&core_if->host_if->host_global_regs->haintmsk);
 884         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 885                 hr->hcintmsk_local[i] =
 886                     DWC_READ_REG32(&core_if->host_if->hc_regs[i]->hcintmsk);
 887         }
 888         hr->hprt0_local = DWC_READ_REG32(core_if->host_if->hprt0);
 889         hr->hfir_local =
 890             DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
 891
 892         DWC_DEBUGPL(DBG_ANY,
 893                     "=============Backing Host registers===============\n");
 894         DWC_DEBUGPL(DBG_ANY, "Backed up hcfg            = %08x\n",
 895                     hr->hcfg_local);
 896         DWC_DEBUGPL(DBG_ANY, "Backed up haintmsk = %08x\n", hr->haintmsk_local);
 897         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 898                 DWC_DEBUGPL(DBG_ANY, "Backed up hcintmsk[%02d]=%08x\n", i,
 899                             hr->hcintmsk_local[i]);
 900         }
 901         DWC_DEBUGPL(DBG_ANY, "Backed up hprt0           = %08x\n",
 902                     hr->hprt0_local);
 903         DWC_DEBUGPL(DBG_ANY, "Backed up hfir           = %08x\n",
 904                     hr->hfir_local);
 905
 906         return 0;
 907 }
 908
 909 int dwc_otg_restore_global_regs(dwc_otg_core_if_t * core_if)
 910 {
 911         struct dwc_otg_global_regs_backup *gr;
 912         int i;
 913
 914         gr = core_if->gr_backup;
 915         if (!gr) {
 916                 return -DWC_E_INVALID;
 917         }
 918
 919         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, gr->gotgctl_local);
 920         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gr->gintmsk_local);
 921         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gr->gusbcfg_local);
 922         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gr->gahbcfg_local);
 923         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, gr->grxfsiz_local);
 924         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz,
 925                         gr->gnptxfsiz_local);
 926         DWC_WRITE_REG32(&core_if->core_global_regs->hptxfsiz,
 927                         gr->hptxfsiz_local);
 928         DWC_WRITE_REG32(&core_if->core_global_regs->gdfifocfg,
 929                         gr->gdfifocfg_local);
 930         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
 931                 DWC_WRITE_REG32(&core_if->core_global_regs->dtxfsiz[i],
 932                                 gr->dtxfsiz_local[i]);
 933         }
 934
 935         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
 936         DWC_WRITE_REG32(core_if->host_if->hprt0, 0x0000100A);
 937         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg,
 938                         (gr->gahbcfg_local));
 939         return 0;
 940 }
 941
 942 int dwc_otg_restore_dev_regs(dwc_otg_core_if_t * core_if, int rem_wakeup)
 943 {
 944         struct dwc_otg_dev_regs_backup *dr;
 945         int i;
 946
 947         dr = core_if->dr_backup;
 948
 949         if (!dr) {
 950                 return -DWC_E_INVALID;
 951         }
 952
 953         if (!rem_wakeup) {
 954                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl,
 955                                 dr->dctl);
 956         }
 957
 958         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->daintmsk, dr->daintmsk);
 959         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->diepmsk, dr->diepmsk);
 960         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->doepmsk, dr->doepmsk);
 961
 962         for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
 963                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->dieptsiz, dr->dieptsiz[i]);
 964                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepdma, dr->diepdma[i]);
 965                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[i]->diepctl, dr->diepctl[i]);
 966         }
 967
 968         return 0;
 969 }
 970
 971 int dwc_otg_restore_host_regs(dwc_otg_core_if_t * core_if, int reset)
 972 {
 973         struct dwc_otg_host_regs_backup *hr;
 974         int i;
 975         hr = core_if->hr_backup;
 976
 977         if (!hr) {
 978                 return -DWC_E_INVALID;
 979         }
 980
 981         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hr->hcfg_local);
 982         //if (!reset)
 983         //{
 984         //      DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hr->hfir_local);
 985         //}
 986
 987         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->haintmsk,
 988                         hr->haintmsk_local);
 989         for (i = 0; i < dwc_otg_get_param_host_channels(core_if); ++i) {
 990                 DWC_WRITE_REG32(&core_if->host_if->hc_regs[i]->hcintmsk,
 991                                 hr->hcintmsk_local[i]);
 992         }
 993
 994         return 0;
 995 }
 996
 997 int restore_lpm_i2c_regs(dwc_otg_core_if_t * core_if)
 998 {
 999         struct dwc_otg_global_regs_backup *gr;
1000
1001         gr = core_if->gr_backup;
1002
1003         /* Restore values for LPM and I2C */
1004 #ifdef CONFIG_USB_DWC_OTG_LPM
1005         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, gr->glpmcfg_local);
1006 #endif
1007         DWC_WRITE_REG32(&core_if->core_global_regs->gi2cctl, gr->gi2cctl_local);
1008
1009         return 0;
1010 }
1011
1012 int restore_essential_regs(dwc_otg_core_if_t * core_if, int rmode, int is_host)
1013 {
1014         struct dwc_otg_global_regs_backup *gr;
1015         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1016         gahbcfg_data_t gahbcfg = {.d32 = 0 };
1017         gusbcfg_data_t gusbcfg = {.d32 = 0 };
1018         gintmsk_data_t gintmsk = {.d32 = 0 };
1019
1020         /* Restore LPM and I2C registers */
1021         restore_lpm_i2c_regs(core_if);
1022
1023         /* Set PCGCCTL to 0 */
1024         DWC_WRITE_REG32(core_if->pcgcctl, 0x00000000);
1025
1026         gr = core_if->gr_backup;
1027         /* Load restore values for [31:14] bits */
1028         DWC_WRITE_REG32(core_if->pcgcctl,
1029                         ((gr->pcgcctl_local & 0xffffc000) | 0x00020000));
1030
1031         /* Umnask global Interrupt in GAHBCFG and restore it */
1032         gahbcfg.d32 = gr->gahbcfg_local;
1033         gahbcfg.b.glblintrmsk = 1;
1034         DWC_WRITE_REG32(&core_if->core_global_regs->gahbcfg, gahbcfg.d32);
1035
1036         /* Clear all pending interupts */
1037         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1038
1039         /* Unmask restore done interrupt */
1040         gintmsk.b.restoredone = 1;
1041         DWC_WRITE_REG32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
1042
1043         /* Restore GUSBCFG and HCFG/DCFG */
1044         gusbcfg.d32 = core_if->gr_backup->gusbcfg_local;
1045         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
1046
1047         if (is_host) {
1048                 hcfg_data_t hcfg = {.d32 = 0 };
1049                 hcfg.d32 = core_if->hr_backup->hcfg_local;
1050                 DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg,
1051                                 hcfg.d32);
1052
1053                 /* Load restore values for [31:14] bits */
1054                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1055                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1056
1057                 if (rmode)
1058                         pcgcctl.b.restoremode = 1;
1059                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1060                 dwc_udelay(10);
1061
1062                 /* Load restore values for [31:14] bits and set EssRegRestored bit */
1063                 pcgcctl.d32 = gr->pcgcctl_local | 0xffffc000;
1064                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1065                 pcgcctl.b.ess_reg_restored = 1;
1066                 if (rmode)
1067                         pcgcctl.b.restoremode = 1;
1068                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1069         } else {
1070                 dcfg_data_t dcfg = {.d32 = 0 };
1071                 dcfg.d32 = core_if->dr_backup->dcfg;
1072                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1073
1074                 /* Load restore values for [31:14] bits */
1075                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1076                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1077                 if (!rmode) {
1078                         pcgcctl.d32 |= 0x208;
1079                 }
1080                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1081                 dwc_udelay(10);
1082
1083                 /* Load restore values for [31:14] bits */
1084                 pcgcctl.d32 = gr->pcgcctl_local & 0xffffc000;
1085                 pcgcctl.d32 = gr->pcgcctl_local | 0x00020000;
1086                 pcgcctl.b.ess_reg_restored = 1;
1087                 if (!rmode)
1088                         pcgcctl.d32 |= 0x208;
1089                 DWC_WRITE_REG32(core_if->pcgcctl, pcgcctl.d32);
1090         }
1091
1092         return 0;
1093 }
1094
1095 /**
1096  * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY
1097  * type.
1098  */
1099 static void init_fslspclksel(dwc_otg_core_if_t * core_if)
1100 {
1101         uint32_t val;
1102         hcfg_data_t hcfg;
1103
1104         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1105              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1106              (core_if->core_params->ulpi_fs_ls)) ||
1107             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1108                 /* Full speed PHY */
1109                 val = DWC_HCFG_48_MHZ;
1110         } else {
1111                 /* High speed PHY running at full speed or high speed */
1112                 val = DWC_HCFG_30_60_MHZ;
1113         }
1114
1115         DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val);
1116         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
1117         hcfg.b.fslspclksel = val;
1118         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
1119 }
1120
1121 /**
1122  * Initializes the DevSpd field of the DCFG register depending on the PHY type
1123  * and the enumeration speed of the device.
1124  */
1125 static void init_devspd(dwc_otg_core_if_t * core_if)
1126 {
1127         uint32_t val;
1128         dcfg_data_t dcfg;
1129
1130         if (((core_if->hwcfg2.b.hs_phy_type == 2) &&
1131              (core_if->hwcfg2.b.fs_phy_type == 1) &&
1132              (core_if->core_params->ulpi_fs_ls)) ||
1133             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1134                 /* Full speed PHY */
1135                 val = 0x3;
1136         } else if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
1137                 /* High speed PHY running at full speed */
1138                 val = 0x1;
1139         } else {
1140                 /* High speed PHY running at high speed */
1141                 val = 0x0;
1142         }
1143
1144         DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val);
1145
1146         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
1147         dcfg.b.devspd = val;
1148         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
1149 }
1150
1151 /**
1152  * This function calculates the number of IN EPS
1153  * using GHWCFG1 and GHWCFG2 registers values
1154  *
1155  * @param core_if Programming view of the DWC_otg controller
1156  */
1157 static uint32_t calc_num_in_eps(dwc_otg_core_if_t * core_if)
1158 {
1159         uint32_t num_in_eps = 0;
1160         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1161         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 3;
1162         uint32_t num_tx_fifos = core_if->hwcfg4.b.num_in_eps;
1163         int i;
1164
1165         for (i = 0; i < num_eps; ++i) {
1166                 if (!(hwcfg1 & 0x1))
1167                         num_in_eps++;
1168
1169                 hwcfg1 >>= 2;
1170         }
1171
1172         if (core_if->hwcfg4.b.ded_fifo_en) {
1173                 num_in_eps =
1174                     (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps;
1175         }
1176
1177         return num_in_eps;
1178 }
1179
1180 /**
1181  * This function calculates the number of OUT EPS
1182  * using GHWCFG1 and GHWCFG2 registers values
1183  *
1184  * @param core_if Programming view of the DWC_otg controller
1185  */
1186 static uint32_t calc_num_out_eps(dwc_otg_core_if_t * core_if)
1187 {
1188         uint32_t num_out_eps = 0;
1189         uint32_t num_eps = core_if->hwcfg2.b.num_dev_ep;
1190         uint32_t hwcfg1 = core_if->hwcfg1.d32 >> 2;
1191         int i;
1192
1193         for (i = 0; i < num_eps; ++i) {
1194                 if (!(hwcfg1 & 0x1))
1195                         num_out_eps++;
1196
1197                 hwcfg1 >>= 2;
1198         }
1199         return num_out_eps;
1200 }
1201
1202 /**
1203  * This function initializes the DWC_otg controller registers and
1204  * prepares the core for device mode or host mode operation.
1205  *
1206  * @param core_if Programming view of the DWC_otg controller
1207  *
1208  */
1209 void dwc_otg_core_init(dwc_otg_core_if_t * core_if)
1210 {
1211         int i = 0;
1212         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1213         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1214         gahbcfg_data_t ahbcfg = {.d32 = 0 };
1215         gusbcfg_data_t usbcfg = {.d32 = 0 };
1216         gi2cctl_data_t i2cctl = {.d32 = 0 };
1217
1218         DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n", core_if);
1219
1220         /* Common Initialization */
1221         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1222
1223         /* Program the ULPI External VBUS bit if needed */
1224         usbcfg.b.ulpi_ext_vbus_drv =
1225             (core_if->core_params->phy_ulpi_ext_vbus ==
1226              DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0;
1227
1228         /* Set external TS Dline pulsing */
1229         usbcfg.b.term_sel_dl_pulse =
1230             (core_if->core_params->ts_dline == 1) ? 1 : 0;
1231         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1232
1233         /* Reset the Controller */
1234         dwc_otg_core_reset(core_if);
1235
1236         core_if->adp_enable = core_if->core_params->adp_supp_enable;
1237         core_if->power_down = core_if->core_params->power_down;
1238
1239         /* Initialize parameters from Hardware configuration registers. */
1240         dev_if->num_in_eps = calc_num_in_eps(core_if);
1241         dev_if->num_out_eps = calc_num_out_eps(core_if);
1242
1243         DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",
1244                     core_if->hwcfg4.b.num_dev_perio_in_ep);
1245
1246         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1247                 dev_if->perio_tx_fifo_size[i] =
1248                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1249                 DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n",
1250                             i, dev_if->perio_tx_fifo_size[i]);
1251         }
1252
1253         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1254                 dev_if->tx_fifo_size[i] =
1255                     DWC_READ_REG32(&global_regs->dtxfsiz[i]) >> 16;
1256                 DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n",
1257                             i, dev_if->tx_fifo_size[i]);
1258         }
1259
1260         core_if->total_fifo_size = core_if->hwcfg3.b.dfifo_depth;
1261         core_if->rx_fifo_size = DWC_READ_REG32(&global_regs->grxfsiz);
1262         core_if->nperio_tx_fifo_size =
1263             DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16;
1264
1265         DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", core_if->total_fifo_size);
1266         DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", core_if->rx_fifo_size);
1267         DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n",
1268                     core_if->nperio_tx_fifo_size);
1269
1270         /* This programming sequence needs to happen in FS mode before any other
1271          * programming occurs */
1272         if ((core_if->core_params->speed == DWC_SPEED_PARAM_FULL) &&
1273             (core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) {
1274                 /* If FS mode with FS PHY */
1275
1276                 /* core_init() is now called on every switch so only call the
1277                  * following for the first time through. */
1278                 if (!core_if->phy_init_done) {
1279                         core_if->phy_init_done = 1;
1280                         DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n");
1281                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1282                         usbcfg.b.physel = 1;
1283                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1284
1285                         /* Reset after a PHY select */
1286                         dwc_otg_core_reset(core_if);
1287                 }
1288
1289                 /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.      Also
1290                  * do this on HNP Dev/Host mode switches (done in dev_init and
1291                  * host_init). */
1292                 if (dwc_otg_is_host_mode(core_if)) {
1293                         init_fslspclksel(core_if);
1294                 } else {
1295                         init_devspd(core_if);
1296                 }
1297
1298                 if (core_if->core_params->i2c_enable) {
1299                         DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n");
1300                         /* Program GUSBCFG.OtgUtmifsSel to I2C */
1301                         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1302                         usbcfg.b.otgutmifssel = 1;
1303                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1304
1305                         /* Program GI2CCTL.I2CEn */
1306                         i2cctl.d32 = DWC_READ_REG32(&global_regs->gi2cctl);
1307                         i2cctl.b.i2cdevaddr = 1;
1308                         i2cctl.b.i2cen = 0;
1309                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1310                         i2cctl.b.i2cen = 1;
1311                         DWC_WRITE_REG32(&global_regs->gi2cctl, i2cctl.d32);
1312                 }
1313
1314         } /* endif speed == DWC_SPEED_PARAM_FULL */
1315         else {
1316                 /* High speed PHY. */
1317                 if (!core_if->phy_init_done) {
1318                         core_if->phy_init_done = 1;
1319                         /* HS PHY parameters.  These parameters are preserved
1320                          * during soft reset so only program the first time.  Do
1321                          * a soft reset immediately after setting phyif.  */
1322
1323                         if (core_if->core_params->phy_type == 2) {
1324                                 /* ULPI interface */
1325                                 usbcfg.b.ulpi_utmi_sel = 1;
1326                                 usbcfg.b.phyif = 0;
1327                                 usbcfg.b.ddrsel =
1328                                     core_if->core_params->phy_ulpi_ddr;
1329                         } else if (core_if->core_params->phy_type == 1) {
1330                                 /* UTMI+ interface */
1331                                 usbcfg.b.ulpi_utmi_sel = 0;
1332                                 if (core_if->core_params->phy_utmi_width == 16) {
1333                                         usbcfg.b.phyif = 1;
1334
1335                                 } else {
1336                                         usbcfg.b.phyif = 0;
1337                                 }
1338                         } else {
1339                                 DWC_ERROR("FS PHY TYPE\n");
1340                         }
1341                         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1342                         /* Reset after setting the PHY parameters */
1343                         dwc_otg_core_reset(core_if);
1344                 }
1345         }
1346
1347         if ((core_if->hwcfg2.b.hs_phy_type == 2) &&
1348             (core_if->hwcfg2.b.fs_phy_type == 1) &&
1349             (core_if->core_params->ulpi_fs_ls)) {
1350                 DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n");
1351                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1352                 usbcfg.b.ulpi_fsls = 1;
1353                 usbcfg.b.ulpi_clk_sus_m = 1;
1354                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1355         } else {
1356                 usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1357                 usbcfg.b.ulpi_fsls = 0;
1358                 usbcfg.b.ulpi_clk_sus_m = 0;
1359                 DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1360         }
1361
1362         /* Program the GAHBCFG Register. */
1363         switch (core_if->hwcfg2.b.architecture) {
1364
1365         case DWC_SLAVE_ONLY_ARCH:
1366                 DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n");
1367                 ahbcfg.b.nptxfemplvl_txfemplvl =
1368                     DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1369                 ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY;
1370                 core_if->dma_enable = 0;
1371                 core_if->dma_desc_enable = 0;
1372                 break;
1373
1374         case DWC_EXT_DMA_ARCH:
1375                 DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n");
1376                 {
1377                         uint8_t brst_sz = core_if->core_params->dma_burst_size;
1378                         ahbcfg.b.hburstlen = 0;
1379                         while (brst_sz > 1) {
1380                                 ahbcfg.b.hburstlen++;
1381                                 brst_sz >>= 1;
1382                         }
1383                 }
1384                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1385                 core_if->dma_desc_enable =
1386                     (core_if->core_params->dma_desc_enable != 0);
1387                 break;
1388
1389         case DWC_INT_DMA_ARCH:
1390                 DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n");
1391                 /* Old value was DWC_GAHBCFG_INT_DMA_BURST_INCR - done for
1392                    Host mode ISOC in issue fix - vahrama */
1393                 ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
1394                 core_if->dma_enable = (core_if->core_params->dma_enable != 0);
1395                 core_if->dma_desc_enable =
1396                     (core_if->core_params->dma_desc_enable != 0);
1397                 break;
1398
1399         }
1400         if (core_if->dma_enable) {
1401                 if (core_if->dma_desc_enable) {
1402                         DWC_PRINTF("Using Descriptor DMA mode\n");
1403                 } else {
1404                         DWC_PRINTF("Using Buffer DMA mode\n");
1405                 }
1406         } else {
1407                 DWC_PRINTF("Using Slave mode\n");
1408                 core_if->dma_desc_enable = 0;
1409         }
1410
1411         if (core_if->core_params->ahb_single) {
1412                 ahbcfg.b.ahbsingle = 1;
1413         }
1414
1415         ahbcfg.b.dmaenable = core_if->dma_enable;
1416         DWC_WRITE_REG32(&global_regs->gahbcfg, ahbcfg.d32);
1417
1418         core_if->en_multiple_tx_fifo = core_if->hwcfg4.b.ded_fifo_en;
1419
1420         core_if->pti_enh_enable = core_if->core_params->pti_enable != 0;
1421         core_if->multiproc_int_enable = core_if->core_params->mpi_enable;
1422         DWC_PRINTF("Periodic Transfer Interrupt Enhancement - %s\n",
1423                    ((core_if->pti_enh_enable) ? "enabled" : "disabled"));
1424         DWC_PRINTF("Multiprocessor Interrupt Enhancement - %s\n",
1425                    ((core_if->multiproc_int_enable) ? "enabled" : "disabled"));
1426
1427         /*
1428          * Program the GUSBCFG register.
1429          */
1430         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
1431
1432         switch (core_if->hwcfg2.b.op_mode) {
1433         case DWC_MODE_HNP_SRP_CAPABLE:
1434                 usbcfg.b.hnpcap = (core_if->core_params->otg_cap ==
1435                                    DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE);
1436                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1437                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1438                 break;
1439
1440         case DWC_MODE_SRP_ONLY_CAPABLE:
1441                 usbcfg.b.hnpcap = 0;
1442                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1443                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1444                 break;
1445
1446         case DWC_MODE_NO_HNP_SRP_CAPABLE:
1447                 usbcfg.b.hnpcap = 0;
1448                 usbcfg.b.srpcap = 0;
1449                 break;
1450
1451         case DWC_MODE_SRP_CAPABLE_DEVICE:
1452                 usbcfg.b.hnpcap = 0;
1453                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1454                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1455                 break;
1456
1457         case DWC_MODE_NO_SRP_CAPABLE_DEVICE:
1458                 usbcfg.b.hnpcap = 0;
1459                 usbcfg.b.srpcap = 0;
1460                 break;
1461
1462         case DWC_MODE_SRP_CAPABLE_HOST:
1463                 usbcfg.b.hnpcap = 0;
1464                 usbcfg.b.srpcap = (core_if->core_params->otg_cap !=
1465                                    DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
1466                 break;
1467
1468         case DWC_MODE_NO_SRP_CAPABLE_HOST:
1469                 usbcfg.b.hnpcap = 0;
1470                 usbcfg.b.srpcap = 0;
1471                 break;
1472         }
1473
1474         DWC_WRITE_REG32(&global_regs->gusbcfg, usbcfg.d32);
1475
1476 #ifdef CONFIG_USB_DWC_OTG_LPM
1477         if (core_if->core_params->lpm_enable) {
1478                 glpmcfg_data_t lpmcfg = {.d32 = 0 };
1479
1480                 /* To enable LPM support set lpm_cap_en bit */
1481                 lpmcfg.b.lpm_cap_en = 1;
1482
1483                 /* Make AppL1Res ACK */
1484                 lpmcfg.b.appl_resp = 1;
1485
1486                 /* Retry 3 times */
1487                 lpmcfg.b.retry_count = 3;
1488
1489                 DWC_MODIFY_REG32(&core_if->core_global_regs->glpmcfg,
1490                                  0, lpmcfg.d32);
1491
1492         }
1493 #endif
1494         if (core_if->core_params->ic_usb_cap) {
1495                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
1496                 gusbcfg.b.ic_usb_cap = 1;
1497                 DWC_MODIFY_REG32(&core_if->core_global_regs->gusbcfg,
1498                                  0, gusbcfg.d32);
1499         }
1500         {
1501                 gotgctl_data_t gotgctl = {.d32 = 0 };
1502                 gotgctl.b.otgver = core_if->core_params->otg_ver;
1503                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, 0,
1504                                  gotgctl.d32);
1505                 /* Set OTG version supported */
1506                 core_if->otg_ver = core_if->core_params->otg_ver;
1507                 DWC_PRINTF("OTG VER PARAM: %d, OTG VER FLAG: %d\n",
1508                            core_if->core_params->otg_ver, core_if->otg_ver);
1509         }
1510
1511         /* Enable common interrupts */
1512         dwc_otg_enable_common_interrupts(core_if);
1513
1514         /* Do device or host intialization based on mode during PCD
1515          * and HCD initialization  */
1516         if (dwc_otg_is_host_mode(core_if)) {
1517                 DWC_DEBUGPL(DBG_ANY, "Host Mode\n");
1518                 core_if->op_state = A_HOST;
1519         } else {
1520                 DWC_DEBUGPL(DBG_ANY, "Device Mode\n");
1521                 core_if->op_state = B_PERIPHERAL;
1522 #ifdef DWC_DEVICE_ONLY
1523                 dwc_otg_core_dev_init(core_if);
1524 #endif
1525         }
1526 }
1527
1528 /**
1529  * This function enables the Device mode interrupts.
1530  *
1531  * @param core_if Programming view of DWC_otg controller
1532  */
1533 void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t * core_if)
1534 {
1535         gintmsk_data_t intr_mask = {.d32 = 0 };
1536         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1537
1538         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
1539
1540         /* Disable all interrupts. */
1541         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
1542
1543         /* Clear any pending interrupts */
1544         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
1545
1546         /* Enable the common interrupts */
1547         dwc_otg_enable_common_interrupts(core_if);
1548
1549         /* Enable interrupts */
1550         intr_mask.b.usbreset = 1;
1551         intr_mask.b.enumdone = 1;
1552         /* Disable Disconnect interrupt in Device mode */
1553         intr_mask.b.disconnect = 0;
1554
1555         if (!core_if->multiproc_int_enable) {
1556                 intr_mask.b.inepintr = 1;
1557                 intr_mask.b.outepintr = 1;
1558         }
1559
1560         intr_mask.b.erlysuspend = 1;
1561
1562         if (core_if->en_multiple_tx_fifo == 0) {
1563                 intr_mask.b.epmismatch = 1;
1564         }
1565
1566         //intr_mask.b.incomplisoout = 1;
1567         intr_mask.b.incomplisoin = 1;
1568
1569 /* Enable the ignore frame number for ISOC xfers - MAS */
1570 /* Disable to support high bandwith ISOC transfers - manukz */
1571 #if 0
1572 #ifdef DWC_UTE_PER_IO
1573         if (core_if->dma_enable) {
1574                 if (core_if->dma_desc_enable) {
1575                         dctl_data_t dctl1 = {.d32 = 0 };
1576                         dctl1.b.ifrmnum = 1;
1577                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
1578                                          dctl, 0, dctl1.d32);
1579                         DWC_DEBUG("----Enabled Ignore frame number (0x%08x)",
1580                                   DWC_READ_REG32(&core_if->dev_if->
1581                                                  dev_global_regs->dctl));
1582                 }
1583         }
1584 #endif
1585 #endif
1586 #ifdef DWC_EN_ISOC
1587         if (core_if->dma_enable) {
1588                 if (core_if->dma_desc_enable == 0) {
1589                         if (core_if->pti_enh_enable) {
1590                                 dctl_data_t dctl = {.d32 = 0 };
1591                                 dctl.b.ifrmnum = 1;
1592                                 DWC_MODIFY_REG32(&core_if->
1593                                                  dev_if->dev_global_regs->dctl,
1594                                                  0, dctl.d32);
1595                         } else {
1596                                 intr_mask.b.incomplisoin = 1;
1597                                 intr_mask.b.incomplisoout = 1;
1598                         }
1599                 }
1600         } else {
1601                 intr_mask.b.incomplisoin = 1;
1602                 intr_mask.b.incomplisoout = 1;
1603         }
1604 #endif /* DWC_EN_ISOC */
1605
1606         /** @todo NGS: Should this be a module parameter? */
1607 #ifdef USE_PERIODIC_EP
1608         intr_mask.b.isooutdrop = 1;
1609         intr_mask.b.eopframe = 1;
1610         intr_mask.b.incomplisoin = 1;
1611         intr_mask.b.incomplisoout = 1;
1612 #endif
1613
1614         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
1615
1616         DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__,
1617                     DWC_READ_REG32(&global_regs->gintmsk));
1618 }
1619
1620 /**
1621  * This function initializes the DWC_otg controller registers for
1622  * device mode.
1623  *
1624  * @param core_if Programming view of DWC_otg controller
1625  *
1626  */
1627 void dwc_otg_core_dev_init(dwc_otg_core_if_t * core_if)
1628 {
1629         int i;
1630         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
1631         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
1632         dwc_otg_core_params_t *params = core_if->core_params;
1633         dcfg_data_t dcfg = {.d32 = 0 };
1634         depctl_data_t diepctl = {.d32 = 0 };
1635         grstctl_t resetctl = {.d32 = 0 };
1636         uint32_t rx_fifo_size;
1637         fifosize_data_t nptxfifosize;
1638         fifosize_data_t txfifosize;
1639         dthrctl_data_t dthrctl;
1640         fifosize_data_t ptxfifosize;
1641 //      uint16_t rxfsiz, nptxfsiz;
1642 //      gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
1643 //      hwcfg3_data_t hwcfg3 = {.d32 = 0 };
1644         gotgctl_data_t gotgctl = {.d32 = 0 };
1645         gahbcfg_data_t gahbcfg = {.d32 = 0};
1646
1647         /* Restart the Phy Clock */
1648         pcgcctl_data_t pcgcctl = {.d32 = 0 };
1649         /* Restart the Phy Clock */
1650         pcgcctl.b.stoppclk = 1;
1651         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
1652         dwc_udelay(10);
1653
1654         gahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR16;
1655         DWC_MODIFY_REG32(&global_regs->gahbcfg, 0 , gahbcfg.b.hburstlen);
1656
1657         /* Device configuration register */
1658         init_devspd(core_if);
1659         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1660         dcfg.b.descdma = (core_if->dma_desc_enable) ? 1 : 0;
1661         dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80;
1662         /* Enable Device OUT NAK in case of DDMA mode */
1663         if (core_if->core_params->dev_out_nak) {
1664                 dcfg.b.endevoutnak = 1;
1665         }
1666
1667         if (core_if->core_params->cont_on_bna) {
1668                 dctl_data_t dctl = {.d32 = 0 };
1669                 dctl.b.encontonbna = 1;
1670                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
1671         }
1672         /** should be done before every reset */
1673         if (core_if->otg_ver) {
1674                 core_if->otg_sts = 0;
1675                 gotgctl.b.devhnpen = 1;
1676                 DWC_MODIFY_REG32(&core_if->core_global_regs->gotgctl, gotgctl.d32, 0);
1677         }
1678
1679         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1680
1681         /* Configure data FIFO sizes */
1682
1683         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
1684 #ifdef DWC_UTE_CFI
1685                 core_if->pwron_rxfsiz = DWC_READ_REG32(&global_regs->grxfsiz);
1686                 core_if->init_rxfsiz = params->dev_rx_fifo_size;
1687 #endif
1688                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
1689                             DWC_READ_REG32(&global_regs->grxfsiz));
1690
1691                 /** Set Periodic Tx FIFO Mask all bits 0 */
1692                 core_if->p_tx_msk = 0;
1693
1694                 /** Set Tx FIFO Mask all bits 0 */
1695                 core_if->tx_msk = 0;
1696                 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
1697                  * and ded_fifo_en is 1 in default*/
1698                 if (core_if->en_multiple_tx_fifo == 0) {
1699                         /* Non-periodic Tx FIFO */
1700                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1701                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
1702
1703                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1704                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1705
1706                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
1707                                         nptxfifosize.d32);
1708
1709                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1710                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
1711
1712                         /**@todo NGS: Fix Periodic FIFO Sizing! */
1713                         /*
1714                          * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15.
1715                          * Indexes of the FIFO size module parameters in the
1716                          * dev_perio_tx_fifo_size array and the FIFO size registers in
1717                          * the dptxfsiz array run from 0 to 14.
1718                          */
1719                         /** @todo Finish debug of this */
1720                         ptxfifosize.b.startaddr =
1721                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1722                         for (i = 0; i < core_if->hwcfg4.b.num_dev_perio_in_ep; i++) {
1723                                 ptxfifosize.b.depth =
1724                                     params->dev_perio_tx_fifo_size[i];
1725                                 DWC_DEBUGPL(DBG_CIL,
1726                                             "initial dtxfsiz[%d]=%08x\n", i,
1727                                             DWC_READ_REG32(&global_regs->dtxfsiz
1728                                                            [i]));
1729                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
1730                                                 ptxfifosize.d32);
1731                                 DWC_DEBUGPL(DBG_CIL, "new dtxfsiz[%d]=%08x\n",
1732                                             i,
1733                                             DWC_READ_REG32(&global_regs->dtxfsiz
1734                                                            [i]));
1735                                 ptxfifosize.b.startaddr += ptxfifosize.b.depth;
1736                         }
1737                 } else {
1738                         /*
1739                          * Tx FIFOs These FIFOs are numbered from 1 to 15.
1740                          * Indexes of the FIFO size module parameters in the
1741                          * dev_tx_fifo_size array and the FIFO size registers in
1742                          * the dtxfsiz array run from 0 to 14.
1743                          */
1744
1745                         /* Non-periodic Tx FIFO */
1746                         DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
1747                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
1748
1749 #ifdef DWC_UTE_CFI
1750                         core_if->pwron_gnptxfsiz =
1751                             (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
1752                         core_if->init_gnptxfsiz =
1753                             params->dev_nperio_tx_fifo_size;
1754 #endif
1755                         rx_fifo_size = params->dev_rx_fifo_size;
1756                         DWC_WRITE_REG32(&global_regs->grxfsiz, rx_fifo_size);
1757                         DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
1758                                     DWC_READ_REG32(&global_regs->grxfsiz));
1759
1760                         nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size;
1761                         nptxfifosize.b.startaddr = params->dev_rx_fifo_size;
1762                         DWC_WRITE_REG32(&global_regs->gnptxfsiz,
1763                                         nptxfifosize.d32);
1764
1765                         DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
1766                                     DWC_READ_REG32(&global_regs->gnptxfsiz));
1767
1768                         txfifosize.b.startaddr =
1769                             nptxfifosize.b.startaddr + nptxfifosize.b.depth;
1770
1771                         for (i = 0; i < core_if->hwcfg4.b.num_in_eps; i++) {
1772
1773                                 txfifosize.b.depth =
1774                                     params->dev_tx_fifo_size[i];
1775
1776                                 DWC_DEBUGPL(DBG_CIL,
1777                                             "initial dtxfsiz[%d]=%08x\n",
1778                                             i,
1779                                             DWC_READ_REG32(&global_regs->dtxfsiz
1780                                                            [i]));
1781
1782 #ifdef DWC_UTE_CFI
1783                                 core_if->pwron_txfsiz[i] =
1784                                     (DWC_READ_REG32
1785                                      (&global_regs->dtxfsiz[i]) >> 16);
1786                                 core_if->init_txfsiz[i] =
1787                                     params->dev_tx_fifo_size[i];
1788 #endif
1789                                 DWC_WRITE_REG32(&global_regs->dtxfsiz[i],
1790                                                 txfifosize.d32);
1791
1792                                 DWC_DEBUGPL(DBG_CIL,
1793                                             "new dtxfsiz[%d]=%08x\n",
1794                                             i,
1795                                             DWC_READ_REG32(&global_regs->dtxfsiz
1796                                                            [i]));
1797
1798                                 txfifosize.b.startaddr += txfifosize.b.depth;
1799                         }
1800                         #if 0
1801                         /* Calculating DFIFOCFG for Device mode to include RxFIFO and NPTXFIFO
1802                          * Before 3.00a EpInfoBase was being configured in ep enable/disable
1803                          * routine as well. Starting from 3.00a it will be set to the end of
1804                          * allocated FIFO space here due to ep 0 OUT always keeping enabled
1805                          */
1806                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
1807                         hwcfg3.d32 = DWC_READ_REG32(&global_regs->ghwcfg3);
1808                         gdfifocfg.b.gdfifocfg = (DWC_READ_REG32(&global_regs->ghwcfg3) >> 16);
1809                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
1810                         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
1811                                 rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
1812                                 nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
1813                                 gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz;
1814                         } else {
1815                                 gdfifocfg.b.epinfobase = txfifosize.b.startaddr;
1816                         }
1817                         //DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
1818                         #endif
1819                 }
1820         }
1821
1822         /* Flush the FIFOs */
1823         dwc_otg_flush_tx_fifo(core_if, 0x10);   /* all Tx FIFOs */
1824         dwc_otg_flush_rx_fifo(core_if);
1825
1826         /* Flush the Learning Queue. */
1827         resetctl.b.intknqflsh = 1;
1828         DWC_WRITE_REG32(&core_if->core_global_regs->grstctl, resetctl.d32);
1829
1830         if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable) {
1831                 core_if->start_predict = 0;
1832                 for (i = 0; i <= core_if->dev_if->num_in_eps; ++i) {
1833                         core_if->nextep_seq[i] = 0xff;  // 0xff - EP not active
1834                 }
1835                 core_if->nextep_seq[0] = 0;
1836                 core_if->first_in_nextep_seq = 0;
1837                 diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
1838                 diepctl.b.nextep = 0;
1839                 DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
1840
1841                 /* Update IN Endpoint Mismatch Count by active IN NP EP count + 1 */
1842                 dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
1843                 dcfg.b.epmscnt = 2;
1844                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
1845
1846                 DWC_DEBUGPL(DBG_CILV,
1847                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
1848                             __func__, core_if->first_in_nextep_seq);
1849                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
1850                         DWC_DEBUGPL(DBG_CILV, "%2d ", core_if->nextep_seq[i]);
1851                 }
1852                 DWC_DEBUGPL(DBG_CILV, "\n");
1853         }
1854
1855         /* Clear all pending Device Interrupts */
1856         /** @todo - if the condition needed to be checked
1857          *  or in any case all pending interrutps should be cleared?
1858      */
1859         if (core_if->multiproc_int_enable) {
1860                 for (i = 0; i < core_if->dev_if->num_in_eps; ++i) {
1861                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
1862                                         diepeachintmsk[i], 0);
1863                 }
1864
1865                 for (i = 0; i < core_if->dev_if->num_out_eps; ++i) {
1866                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
1867                                         doepeachintmsk[i], 0);
1868                 }
1869
1870                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachint, 0xFFFFFFFF);
1871                 DWC_WRITE_REG32(&dev_if->dev_global_regs->deachintmsk, 0);
1872         } else {
1873                 DWC_WRITE_REG32(&dev_if->dev_global_regs->diepmsk, 0);
1874                 DWC_WRITE_REG32(&dev_if->dev_global_regs->doepmsk, 0);
1875                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daint, 0xFFFFFFFF);
1876                 DWC_WRITE_REG32(&dev_if->dev_global_regs->daintmsk, 0);
1877         }
1878
1879         for (i = 0; i <= dev_if->num_in_eps; i++) {
1880                 depctl_data_t depctl;
1881                 depctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[i]->diepctl);
1882                 if (depctl.b.epena) {
1883                         depctl.d32 = 0;
1884                         depctl.b.epdis = 1;
1885                         depctl.b.snak = 1;
1886                 } else {
1887                         depctl.d32 = 0;
1888                 }
1889
1890                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepctl, depctl.d32);
1891
1892                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->dieptsiz, 0);
1893                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepdma, 0);
1894                 DWC_WRITE_REG32(&dev_if->in_ep_regs[i]->diepint, 0xFF);
1895         }
1896
1897         for (i = 1; i <= dev_if->num_out_eps; i++) {
1898                 depctl_data_t depctl;
1899                 depctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[i]->doepctl);
1900                 if (depctl.b.epena) {
1901                         int j = 0;
1902                         dctl_data_t dctl = {.d32 = 0 };
1903                         gintmsk_data_t gintsts = {.d32 = 0 };
1904                         doepint_data_t doepint = {.d32 = 0 };
1905                         dctl.b.sgoutnak = 1;
1906                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1907                         do {
1908                                 j++;
1909                                 dwc_udelay(10);
1910                                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
1911                                 if (j == 100000) {
1912                                         DWC_ERROR("SNAK as not set during 10s\n");
1913                                         break;
1914                                 }
1915                         } while (!gintsts.b.goutnakeff);
1916                         gintsts.d32 = 0;
1917                         gintsts.b.goutnakeff = 1;
1918                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
1919
1920                         depctl.d32 = 0;
1921                         depctl.b.epdis = 1;
1922                         depctl.b.snak = 1;
1923                         j = 0;
1924                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1925                         do {
1926                                 dwc_udelay(10);
1927                                 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
1928                                         out_ep_regs[i]->doepint);
1929                                 if (j == 100000) {
1930                                         DWC_ERROR("EPDIS was not set during 10s\n");
1931                                         break;
1932                                 }
1933                         } while (!doepint.b.epdisabled);
1934
1935                         doepint.b.epdisabled = 1;
1936                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[i]->doepint, doepint.d32);
1937
1938                         dctl.d32 = 0;
1939                         dctl.b.cgoutnak = 1;
1940                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
1941                 } else {
1942                         depctl.d32 = 0;
1943                 }
1944
1945                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepctl, depctl.d32);
1946                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doeptsiz, 0);
1947                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepdma, 0);
1948                 DWC_WRITE_REG32(&dev_if->out_ep_regs[i]->doepint, 0xFF);
1949         }
1950
1951         if (core_if->en_multiple_tx_fifo && core_if->dma_enable) {
1952                 dev_if->non_iso_tx_thr_en = params->thr_ctl & 0x1;
1953                 dev_if->iso_tx_thr_en = (params->thr_ctl >> 1) & 0x1;
1954                 dev_if->rx_thr_en = (params->thr_ctl >> 2) & 0x1;
1955
1956                 dev_if->rx_thr_length = params->rx_thr_length;
1957                 dev_if->tx_thr_length = params->tx_thr_length;
1958
1959                 dev_if->setup_desc_index = 0;
1960
1961                 dthrctl.d32 = 0;
1962                 dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en;
1963                 dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en;
1964                 dthrctl.b.tx_thr_len = dev_if->tx_thr_length;
1965                 dthrctl.b.rx_thr_en = dev_if->rx_thr_en;
1966                 dthrctl.b.rx_thr_len = dev_if->rx_thr_length;
1967                 dthrctl.b.ahb_thr_ratio = params->ahb_thr_ratio;
1968
1969                 DWC_WRITE_REG32(&dev_if->dev_global_regs->dtknqr3_dthrctl,
1970                                 dthrctl.d32);
1971
1972                 DWC_DEBUGPL(DBG_CIL,
1973                             "Non ISO Tx Thr - %d\nISO Tx Thr - %d\nRx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n",
1974                             dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en,
1975                             dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len,
1976                             dthrctl.b.rx_thr_len);
1977
1978         }
1979
1980         dwc_otg_enable_device_interrupts(core_if);
1981
1982         {
1983                 diepmsk_data_t msk = {.d32 = 0 };
1984                 msk.b.txfifoundrn = 1;
1985                 if (core_if->multiproc_int_enable) {
1986                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->
1987                                          diepeachintmsk[0], msk.d32, msk.d32);
1988                 } else {
1989                         DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk,
1990                                          msk.d32, msk.d32);
1991                 }
1992         }
1993
1994         if (core_if->multiproc_int_enable) {
1995                 /* Set NAK on Babble */
1996                 dctl_data_t dctl = {.d32 = 0 };
1997                 dctl.b.nakonbble = 1;
1998                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, 0, dctl.d32);
1999         }
2000 }
2001
2002 /**
2003  * This function enables the Host mode interrupts.
2004  *
2005  * @param core_if Programming view of DWC_otg controller
2006  */
2007 void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t * core_if)
2008 {
2009         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2010         gintmsk_data_t intr_mask = {.d32 = 0 };
2011
2012         DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__);
2013
2014         /* Disable all interrupts. */
2015         DWC_WRITE_REG32(&global_regs->gintmsk, 0);
2016
2017         /* Clear any pending interrupts. */
2018         DWC_WRITE_REG32(&global_regs->gintsts, 0xFFFFFFFF);
2019
2020         /* Enable the common interrupts */
2021         dwc_otg_enable_common_interrupts(core_if);
2022
2023         /*
2024          * Enable host mode interrupts without disturbing common
2025          * interrupts.
2026          */
2027
2028         intr_mask.b.disconnect = 1;
2029         intr_mask.b.portintr = 1;
2030         intr_mask.b.hcintr = 1;
2031
2032         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
2033 }
2034
2035 /**
2036  * This function disables the Host Mode interrupts.
2037  *
2038  * @param core_if Programming view of DWC_otg controller
2039  */
2040 void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t * core_if)
2041 {
2042         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2043         gintmsk_data_t intr_mask = {.d32 = 0 };
2044
2045         DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__);
2046
2047         /*
2048          * Disable host mode interrupts without disturbing common
2049          * interrupts.
2050          */
2051         intr_mask.b.sofintr = 1;
2052         intr_mask.b.portintr = 1;
2053         intr_mask.b.hcintr = 1;
2054         intr_mask.b.ptxfempty = 1;
2055         intr_mask.b.nptxfempty = 1;
2056
2057         DWC_MODIFY_REG32(&global_regs->gintmsk, intr_mask.d32, 0);
2058 }
2059
2060 /**
2061  * This function initializes the DWC_otg controller registers for
2062  * host mode.
2063  *
2064  * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
2065  * request queues. Host channels are reset to ensure that they are ready for
2066  * performing transfers.
2067  *
2068  * @param core_if Programming view of DWC_otg controller
2069  *
2070  */
2071 void dwc_otg_core_host_init(dwc_otg_core_if_t * core_if)
2072 {
2073         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
2074         dwc_otg_host_if_t *host_if = core_if->host_if;
2075         dwc_otg_core_params_t *params = core_if->core_params;
2076         hprt0_data_t hprt0 = {.d32 = 0 };
2077         fifosize_data_t nptxfifosize;
2078         fifosize_data_t ptxfifosize;
2079 //      uint16_t rxfsiz, nptxfsiz, hptxfsiz;
2080 //      gdfifocfg_data_t gdfifocfg = {.d32 = 0 };
2081         int i;
2082         hcchar_data_t hcchar;
2083         hcfg_data_t hcfg;
2084         hfir_data_t hfir;
2085         dwc_otg_hc_regs_t *hc_regs;
2086         int num_channels;
2087         gotgctl_data_t gotgctl = {.d32 = 0 };
2088         pcgcctl_data_t pcgcctl = {.d32 = 0 };
2089         struct dwc_otg_platform_data *pldata;
2090         pldata = core_if->otg_dev->pldata;
2091
2092
2093
2094         DWC_DEBUGPL(DBG_CILV, "%s(%p)\n", __func__, core_if);
2095
2096         /* Restart the Phy Clock */
2097         pcgcctl.b.stoppclk = 1;
2098         DWC_MODIFY_REG32(core_if->pcgcctl, pcgcctl.d32, 0);
2099         dwc_udelay(10);
2100
2101         if ((core_if->otg_ver == 1) && (core_if->op_state == A_HOST)) {
2102                 DWC_PRINTF("Init: Port Power? op_state=%d\n", core_if->op_state);
2103                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2104                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2105                 if (hprt0.b.prtpwr == 0) {
2106                         hprt0.b.prtpwr = 1;
2107                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2108                 }
2109         }
2110
2111         /* Initialize Host Configuration Register */
2112         init_fslspclksel(core_if);
2113         if (core_if->core_params->speed == DWC_SPEED_PARAM_FULL) {
2114                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2115                 hcfg.b.fslssupp = 1;
2116                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2117
2118         }
2119
2120         /* This bit allows dynamic reloading of the HFIR register
2121          * during runtime. This bit needs to be programmed during
2122          * initial configuration and its value must not be changed
2123          * during runtime.*/
2124         if (core_if->core_params->reload_ctl == 1) {
2125                 hfir.d32 = DWC_READ_REG32(&host_if->host_global_regs->hfir);
2126                 hfir.b.hfirrldctrl = 1;
2127                 DWC_WRITE_REG32(&host_if->host_global_regs->hfir, hfir.d32);
2128         }
2129
2130         if (core_if->core_params->dma_desc_enable) {
2131                 uint8_t op_mode = core_if->hwcfg2.b.op_mode;
2132                 if (!
2133                     (core_if->hwcfg4.b.desc_dma
2134                      && (core_if->snpsid >= OTG_CORE_REV_2_90a)
2135                      && ((op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
2136                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
2137                          || (op_mode ==
2138                              DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG)
2139                          || (op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)
2140                          || (op_mode ==
2141                              DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST)))) {
2142
2143                         DWC_ERROR("Host can't operate in Descriptor DMA mode.\n"
2144                                   "Either core version is below 2.90a or "
2145                                   "GHWCFG2, GHWCFG4 registers' values do not allow Descriptor DMA in host mode.\n"
2146                                   "To run the driver in Buffer DMA host mode set dma_desc_enable "
2147                                   "module parameter to 0.\n");
2148                         return;
2149                 }
2150                 hcfg.d32 = DWC_READ_REG32(&host_if->host_global_regs->hcfg);
2151                 hcfg.b.descdma = 1;
2152                 DWC_WRITE_REG32(&host_if->host_global_regs->hcfg, hcfg.d32);
2153         }
2154
2155         /* Configure data FIFO sizes */
2156         if (core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) {
2157                 DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n",
2158                             core_if->total_fifo_size);
2159                 DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n",
2160                             params->host_rx_fifo_size);
2161                 DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n",
2162                             params->host_nperio_tx_fifo_size);
2163                 DWC_DEBUGPL(DBG_CIL, "P Tx FIFO Size=%d\n",
2164                             params->host_perio_tx_fifo_size);
2165
2166                 /* Rx FIFO */
2167                 DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n",
2168                             DWC_READ_REG32(&global_regs->grxfsiz));
2169                 DWC_WRITE_REG32(&global_regs->grxfsiz, 0x0200);//params->host_rx_fifo_size);
2170                 DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n",
2171                             DWC_READ_REG32(&global_regs->grxfsiz));
2172
2173                 /* Non-periodic Tx FIFO */
2174                 DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n",
2175                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2176                 nptxfifosize.b.depth = 0x0080;//params->host_nperio_tx_fifo_size;
2177                 nptxfifosize.b.startaddr = 0x0200;//params->host_rx_fifo_size;
2178                 DWC_WRITE_REG32(&global_regs->gnptxfsiz, nptxfifosize.d32);
2179                 DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n",
2180                             DWC_READ_REG32(&global_regs->gnptxfsiz));
2181
2182                 /* Periodic Tx FIFO */
2183                 DWC_DEBUGPL(DBG_CIL, "initial hptxfsiz=%08x\n",
2184                             DWC_READ_REG32(&global_regs->hptxfsiz));
2185                 ptxfifosize.b.depth = 0x0100;//params->host_perio_tx_fifo_size;
2186                 ptxfifosize.b.startaddr = 0x0280;//nptxfifosize.b.startaddr + nptxfifosize.b.depth;
2187                 DWC_WRITE_REG32(&global_regs->hptxfsiz, ptxfifosize.d32);
2188                 DWC_DEBUGPL(DBG_CIL, "new hptxfsiz=%08x\n",
2189                             DWC_READ_REG32(&global_regs->hptxfsiz));
2190         #if 0
2191                 /* core_if->en_multiple_tx_fifo equals core_if->hwcfg4.b.ded_fifo_en,
2192                  * and ded_fifo_en is 1 in default
2193                  */
2194                 if (core_if->en_multiple_tx_fifo) {
2195                         /* Global DFIFOCFG calculation for Host mode - include RxFIFO, NPTXFIFO and HPTXFIFO */
2196                         gdfifocfg.d32 = DWC_READ_REG32(&global_regs->gdfifocfg);
2197                         rxfsiz = (DWC_READ_REG32(&global_regs->grxfsiz) & 0x0000ffff);
2198                         nptxfsiz = (DWC_READ_REG32(&global_regs->gnptxfsiz) >> 16);
2199                         hptxfsiz = (DWC_READ_REG32(&global_regs->hptxfsiz) >> 16);
2200                         gdfifocfg.b.epinfobase = rxfsiz + nptxfsiz + hptxfsiz;
2201                         DWC_WRITE_REG32(&global_regs->gdfifocfg, gdfifocfg.d32);
2202                 }
2203                 #endif
2204         }
2205
2206         /* TODO - check this */
2207         /* Clear Host Set HNP Enable in the OTG Control Register */
2208         gotgctl.b.hstsethnpen = 1;
2209         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2210         /* Make sure the FIFOs are flushed. */
2211         dwc_otg_flush_tx_fifo(core_if, 0x10 /* all TX FIFOs */ );
2212         dwc_otg_flush_rx_fifo(core_if);
2213
2214         /* Clear Host Set HNP Enable in the OTG Control Register */
2215         gotgctl.b.hstsethnpen = 1;
2216         DWC_MODIFY_REG32(&global_regs->gotgctl, gotgctl.d32, 0);
2217
2218         if (!core_if->core_params->dma_desc_enable) {
2219                 /* Flush out any leftover queued requests. */
2220                 num_channels = core_if->core_params->host_channels;
2221
2222                 for (i = 0; i < num_channels; i++) {
2223                         hc_regs = core_if->host_if->hc_regs[i];
2224                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2225                         hcchar.b.chen = 0;
2226                         hcchar.b.chdis = 1;
2227                         hcchar.b.epdir = 0;
2228                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2229                 }
2230
2231                 /* Halt all channels to put them into a known state. */
2232                 for (i = 0; i < num_channels; i++) {
2233                         int count = 0;
2234                         hc_regs = core_if->host_if->hc_regs[i];
2235                         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2236                         hcchar.b.chen = 1;
2237                         hcchar.b.chdis = 1;
2238                         hcchar.b.epdir = 0;
2239                         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2240                         DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i);
2241                         do {
2242                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2243                                 if (++count > 1000) {
2244                                         DWC_ERROR
2245                                             ("%s: Unable to clear halt on channel %d\n",
2246                                              __func__, i);
2247                                         break;
2248                                 }
2249                                 dwc_udelay(1);
2250                         } while (hcchar.b.chen);
2251                 }
2252         }
2253
2254         /* Turn on the vbus power. */
2255         if ((core_if->otg_ver == 0) && (core_if->op_state == A_HOST)) {
2256                 hprt0.d32 = dwc_otg_read_hprt0(core_if);
2257                 DWC_PRINTF("Init: Power Port (%d)\n", hprt0.b.prtpwr);
2258                 if (hprt0.b.prtpwr == 0) {
2259                         hprt0.b.prtpwr = 1;
2260                         DWC_WRITE_REG32(host_if->hprt0, hprt0.d32);
2261                 }
2262                 if(pldata->power_enable)
2263                     pldata->power_enable(1);
2264         }
2265
2266         dwc_otg_enable_host_interrupts(core_if);
2267 }
2268
2269 /**
2270  * Prepares a host channel for transferring packets to/from a specific
2271  * endpoint. The HCCHARn register is set up with the characteristics specified
2272  * in _hc. Host channel interrupts that may need to be serviced while this
2273  * transfer is in progress are enabled.
2274  *
2275  * @param core_if Programming view of DWC_otg controller
2276  * @param hc Information needed to initialize the host channel
2277  */
2278 void dwc_otg_hc_init(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2279 {
2280         uint32_t intr_enable;
2281         hcintmsk_data_t hc_intr_mask;
2282         gintmsk_data_t gintmsk = {.d32 = 0 };
2283         hcchar_data_t hcchar;
2284         hcsplt_data_t hcsplt;
2285
2286         uint8_t hc_num = hc->hc_num;
2287         dwc_otg_host_if_t *host_if = core_if->host_if;
2288         dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num];
2289
2290         /* Clear old interrupt conditions for this host channel. */
2291         hc_intr_mask.d32 = 0xFFFFFFFF;
2292         hc_intr_mask.b.reserved14_31 = 0;
2293         DWC_WRITE_REG32(&hc_regs->hcint, hc_intr_mask.d32);
2294
2295         /* Enable channel interrupts required for this transfer. */
2296         hc_intr_mask.d32 = 0;
2297         hc_intr_mask.b.chhltd = 1;
2298         if (core_if->dma_enable) {
2299                 /* For Descriptor DMA mode core halts the channel on AHB error. Interrupt is not required */
2300                 if (!core_if->dma_desc_enable)
2301                         hc_intr_mask.b.ahberr = 1;
2302                 else {
2303                         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2304                                 hc_intr_mask.b.xfercompl = 1;
2305                 }
2306
2307                 if (hc->error_state && !hc->do_split &&
2308                     hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
2309                         hc_intr_mask.b.ack = 1;
2310                         if (hc->ep_is_in) {
2311                                 hc_intr_mask.b.datatglerr = 1;
2312                                 if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2313                                         hc_intr_mask.b.nak = 1;
2314                                 }
2315                         }
2316                 }
2317         } else {
2318                 switch (hc->ep_type) {
2319                 case DWC_OTG_EP_TYPE_CONTROL:
2320                 case DWC_OTG_EP_TYPE_BULK:
2321                         hc_intr_mask.b.xfercompl = 1;
2322                         hc_intr_mask.b.stall = 1;
2323                         hc_intr_mask.b.xacterr = 1;
2324                         hc_intr_mask.b.datatglerr = 1;
2325                         if (hc->ep_is_in) {
2326                                 hc_intr_mask.b.bblerr = 1;
2327                         } else {
2328                                 hc_intr_mask.b.nak = 1;
2329                                 hc_intr_mask.b.nyet = 1;
2330                                 if (hc->do_ping) {
2331                                         hc_intr_mask.b.ack = 1;
2332                                 }
2333                         }
2334
2335                         if (hc->do_split) {
2336                                 hc_intr_mask.b.nak = 1;
2337                                 if (hc->complete_split) {
2338                                         hc_intr_mask.b.nyet = 1;
2339                                 } else {
2340                                         hc_intr_mask.b.ack = 1;
2341                                 }
2342                         }
2343
2344                         if (hc->error_state) {
2345                                 hc_intr_mask.b.ack = 1;
2346                         }
2347                         break;
2348                 case DWC_OTG_EP_TYPE_INTR:
2349                         hc_intr_mask.b.xfercompl = 1;
2350                         hc_intr_mask.b.nak = 1;
2351                         hc_intr_mask.b.stall = 1;
2352                         hc_intr_mask.b.xacterr = 1;
2353                         hc_intr_mask.b.datatglerr = 1;
2354                         hc_intr_mask.b.frmovrun = 1;
2355
2356                         if (hc->ep_is_in) {
2357                                 hc_intr_mask.b.bblerr = 1;
2358                         }
2359                         if (hc->error_state) {
2360                                 hc_intr_mask.b.ack = 1;
2361                         }
2362                         if (hc->do_split) {
2363                                 if (hc->complete_split) {
2364                                         hc_intr_mask.b.nyet = 1;
2365                                 } else {
2366                                         hc_intr_mask.b.ack = 1;
2367                                 }
2368                         }
2369                         break;
2370                 case DWC_OTG_EP_TYPE_ISOC:
2371                         hc_intr_mask.b.xfercompl = 1;
2372                         hc_intr_mask.b.frmovrun = 1;
2373                         hc_intr_mask.b.ack = 1;
2374
2375                         if (hc->ep_is_in) {
2376                                 hc_intr_mask.b.xacterr = 1;
2377                                 hc_intr_mask.b.bblerr = 1;
2378                         }
2379                         break;
2380                 }
2381         }
2382         DWC_WRITE_REG32(&hc_regs->hcintmsk, hc_intr_mask.d32);
2383
2384         /* Enable the top level host channel interrupt. */
2385         intr_enable = (1 << hc_num);
2386         DWC_MODIFY_REG32(&host_if->host_global_regs->haintmsk, 0, intr_enable);
2387
2388         /* Make sure host channel interrupts are enabled. */
2389         gintmsk.b.hcintr = 1;
2390         DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
2391
2392         /*
2393          * Program the HCCHARn register with the endpoint characteristics for
2394          * the current transfer.
2395          */
2396         hcchar.d32 = 0;
2397         hcchar.b.devaddr = hc->dev_addr;
2398         hcchar.b.epnum = hc->ep_num;
2399         hcchar.b.epdir = hc->ep_is_in;
2400         hcchar.b.lspddev = (hc->speed == DWC_OTG_EP_SPEED_LOW);
2401         hcchar.b.eptype = hc->ep_type;
2402         hcchar.b.mps = hc->max_packet;
2403
2404         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32);
2405
2406         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2407         DWC_DEBUGPL(DBG_HCDV, "  Dev Addr: %d\n", hcchar.b.devaddr);
2408         DWC_DEBUGPL(DBG_HCDV, "  Ep Num: %d\n", hcchar.b.epnum);
2409         DWC_DEBUGPL(DBG_HCDV, "  Is In: %d\n", hcchar.b.epdir);
2410         DWC_DEBUGPL(DBG_HCDV, "  Is Low Speed: %d\n", hcchar.b.lspddev);
2411         DWC_DEBUGPL(DBG_HCDV, "  Ep Type: %d\n", hcchar.b.eptype);
2412         DWC_DEBUGPL(DBG_HCDV, "  Max Pkt: %d\n", hcchar.b.mps);
2413         DWC_DEBUGPL(DBG_HCDV, "  Multi Cnt: %d\n", hcchar.b.multicnt);
2414
2415         /*
2416          * Program the HCSPLIT register for SPLITs
2417          */
2418         hcsplt.d32 = 0;
2419         if (hc->do_split) {
2420                 DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n",
2421                             hc->hc_num,
2422                             hc->complete_split ? "CSPLIT" : "SSPLIT");
2423                 hcsplt.b.compsplt = hc->complete_split;
2424                 hcsplt.b.xactpos = hc->xact_pos;
2425                 hcsplt.b.hubaddr = hc->hub_addr;
2426                 hcsplt.b.prtaddr = hc->port_addr;
2427                 DWC_DEBUGPL(DBG_HCDV, "   comp split %d\n", hc->complete_split);
2428                 DWC_DEBUGPL(DBG_HCDV, "   xact pos %d\n", hc->xact_pos);
2429                 DWC_DEBUGPL(DBG_HCDV, "   hub addr %d\n", hc->hub_addr);
2430                 DWC_DEBUGPL(DBG_HCDV, "   port addr %d\n", hc->port_addr);
2431                 DWC_DEBUGPL(DBG_HCDV, "   is_in %d\n", hc->ep_is_in);
2432                 DWC_DEBUGPL(DBG_HCDV, "   Max Pkt: %d\n", hcchar.b.mps);
2433                 DWC_DEBUGPL(DBG_HCDV, "   xferlen: %d\n", hc->xfer_len);
2434         }
2435         DWC_WRITE_REG32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32);
2436
2437 }
2438
2439 /**
2440  * Attempts to halt a host channel. This function should only be called in
2441  * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under
2442  * normal circumstances in DMA mode, the controller halts the channel when the
2443  * transfer is complete or a condition occurs that requires application
2444  * intervention.
2445  *
2446  * In slave mode, checks for a free request queue entry, then sets the Channel
2447  * Enable and Channel Disable bits of the Host Channel Characteristics
2448  * register of the specified channel to intiate the halt. If there is no free
2449  * request queue entry, sets only the Channel Disable bit of the HCCHARn
2450  * register to flush requests for this channel. In the latter case, sets a
2451  * flag to indicate that the host channel needs to be halted when a request
2452  * queue slot is open.
2453  *
2454  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
2455  * HCCHARn register. The controller ensures there is space in the request
2456  * queue before submitting the halt request.
2457  *
2458  * Some time may elapse before the core flushes any posted requests for this
2459  * host channel and halts. The Channel Halted interrupt handler completes the
2460  * deactivation of the host channel.
2461  *
2462  * @param core_if Controller register interface.
2463  * @param hc Host channel to halt.
2464  * @param halt_status Reason for halting the channel.
2465  */
2466 void dwc_otg_hc_halt(dwc_otg_core_if_t * core_if,
2467                      dwc_hc_t * hc, dwc_otg_halt_status_e halt_status)
2468 {
2469         gnptxsts_data_t nptxsts;
2470         hptxsts_data_t hptxsts;
2471         hcchar_data_t hcchar;
2472         dwc_otg_hc_regs_t *hc_regs;
2473         dwc_otg_core_global_regs_t *global_regs;
2474         dwc_otg_host_global_regs_t *host_global_regs;
2475
2476         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2477         global_regs = core_if->core_global_regs;
2478         host_global_regs = core_if->host_if->host_global_regs;
2479
2480         DWC_ASSERT(!(halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS),
2481                    "halt_status = %d\n", halt_status);
2482
2483         if (halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
2484             halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
2485                 /*
2486                  * Disable all channel interrupts except Ch Halted. The QTD
2487                  * and QH state associated with this transfer has been cleared
2488                  * (in the case of URB_DEQUEUE), so the channel needs to be
2489                  * shut down carefully to prevent crashes.
2490                  */
2491                 hcintmsk_data_t hcintmsk;
2492                 hcintmsk.d32 = 0;
2493                 hcintmsk.b.chhltd = 1;
2494                 DWC_WRITE_REG32(&hc_regs->hcintmsk, hcintmsk.d32);
2495
2496                 /*
2497                  * Make sure no other interrupts besides halt are currently
2498                  * pending. Handling another interrupt could cause a crash due
2499                  * to the QTD and QH state.
2500                  */
2501                 DWC_WRITE_REG32(&hc_regs->hcint, ~hcintmsk.d32);
2502
2503                 /*
2504                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
2505                  * even if the channel was already halted for some other
2506                  * reason.
2507                  */
2508                 hc->halt_status = halt_status;
2509
2510                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2511                 if (hcchar.b.chen == 0) {
2512                         /*
2513                          * The channel is either already halted or it hasn't
2514                          * started yet. In DMA mode, the transfer may halt if
2515                          * it finishes normally or a condition occurs that
2516                          * requires driver intervention. Don't want to halt
2517                          * the channel again. In either Slave or DMA mode,
2518                          * it's possible that the transfer has been assigned
2519                          * to a channel, but not started yet when an URB is
2520                          * dequeued. Don't want to halt a channel that hasn't
2521                          * started yet.
2522                          */
2523                         return;
2524                 }
2525         }
2526         if (hc->halt_pending) {
2527                 /*
2528                  * A halt has already been issued for this channel. This might
2529                  * happen when a transfer is aborted by a higher level in
2530                  * the stack.
2531                  */
2532 #ifdef DEBUG
2533                 DWC_PRINTF
2534                     ("*** %s: Channel %d, _hc->halt_pending already set ***\n",
2535                      __func__, hc->hc_num);
2536
2537 #endif
2538                 return;
2539         }
2540
2541         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2542
2543         /* No need to set the bit in DDMA for disabling the channel */
2544         //TODO check it everywhere channel is disabled
2545         if (!core_if->core_params->dma_desc_enable)
2546                 hcchar.b.chen = 1;
2547         hcchar.b.chdis = 1;
2548
2549         if (!core_if->dma_enable) {
2550                 /* Check for space in the request queue to issue the halt. */
2551                 if (hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
2552                     hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
2553                         nptxsts.d32 = DWC_READ_REG32(&global_regs->gnptxsts);
2554                         if (nptxsts.b.nptxqspcavail == 0) {
2555                                 hcchar.b.chen = 0;
2556                         }
2557                 } else {
2558                         hptxsts.d32 =
2559                             DWC_READ_REG32(&host_global_regs->hptxsts);
2560                         if ((hptxsts.b.ptxqspcavail == 0)
2561                             || (core_if->queuing_high_bandwidth)) {
2562                                 hcchar.b.chen = 0;
2563                         }
2564                 }
2565         }
2566         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2567
2568         hc->halt_status = halt_status;
2569
2570         if (hcchar.b.chen) {
2571                 hc->halt_pending = 1;
2572                 hc->halt_on_queue = 0;
2573         } else {
2574                 hc->halt_on_queue = 1;
2575         }
2576
2577         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2578         DWC_DEBUGPL(DBG_HCDV, "  hcchar: 0x%08x\n", hcchar.d32);
2579         DWC_DEBUGPL(DBG_HCDV, "  halt_pending: %d\n", hc->halt_pending);
2580         DWC_DEBUGPL(DBG_HCDV, "  halt_on_queue: %d\n", hc->halt_on_queue);
2581         DWC_DEBUGPL(DBG_HCDV, "  halt_status: %d\n", hc->halt_status);
2582
2583         return;
2584 }
2585
2586 /**
2587  * Clears the transfer state for a host channel. This function is normally
2588  * called after a transfer is done and the host channel is being released.
2589  *
2590  * @param core_if Programming view of DWC_otg controller.
2591  * @param hc Identifies the host channel to clean up.
2592  */
2593 void dwc_otg_hc_cleanup(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2594 {
2595         dwc_otg_hc_regs_t *hc_regs;
2596
2597         hc->xfer_started = 0;
2598
2599         /*
2600          * Clear channel interrupt enables and any unhandled channel interrupt
2601          * conditions.
2602          */
2603         hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2604         DWC_WRITE_REG32(&hc_regs->hcintmsk, 0);
2605         DWC_WRITE_REG32(&hc_regs->hcint, 0xFFFFFFFF);
2606 #ifdef DEBUG
2607         DWC_TIMER_CANCEL(core_if->hc_xfer_timer[hc->hc_num]);
2608 #endif
2609 }
2610
2611 /**
2612  * Sets the channel property that indicates in which frame a periodic transfer
2613  * should occur. This is always set to the _next_ frame. This function has no
2614  * effect on non-periodic transfers.
2615  *
2616  * @param core_if Programming view of DWC_otg controller.
2617  * @param hc Identifies the host channel to set up and its properties.
2618  * @param hcchar Current value of the HCCHAR register for the specified host
2619  * channel.
2620  */
2621 static inline void hc_set_even_odd_frame(dwc_otg_core_if_t * core_if,
2622                                          dwc_hc_t * hc, hcchar_data_t * hcchar)
2623 {
2624         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2625             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2626                 hfnum_data_t hfnum;
2627                 hfnum.d32 =
2628                     DWC_READ_REG32(&core_if->host_if->host_global_regs->hfnum);
2629
2630                 /* 1 if _next_ frame is odd, 0 if it's even */
2631                 hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1;
2632 #ifdef DEBUG
2633                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR && hc->do_split
2634                     && !hc->complete_split) {
2635                         switch (hfnum.b.frnum & 0x7) {
2636                         case 7:
2637                                 core_if->hfnum_7_samples++;
2638                                 core_if->hfnum_7_frrem_accum += hfnum.b.frrem;
2639                                 break;
2640                         case 0:
2641                                 core_if->hfnum_0_samples++;
2642                                 core_if->hfnum_0_frrem_accum += hfnum.b.frrem;
2643                                 break;
2644                         default:
2645                                 core_if->hfnum_other_samples++;
2646                                 core_if->hfnum_other_frrem_accum +=
2647                                     hfnum.b.frrem;
2648                                 break;
2649                         }
2650                 }
2651 #endif
2652         }
2653 }
2654
2655 #ifdef DEBUG
2656 void hc_xfer_timeout(void *ptr)
2657 {
2658         hc_xfer_info_t *xfer_info = NULL;
2659         int hc_num = 0;
2660
2661         if (ptr)
2662                 xfer_info = (hc_xfer_info_t *) ptr;
2663
2664         if (!xfer_info->hc) {
2665                 DWC_ERROR("xfer_info->hc = %p\n", xfer_info->hc);
2666                 return;
2667         }
2668
2669         hc_num = xfer_info->hc->hc_num;
2670         DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num);
2671         DWC_WARN("      start_hcchar_val 0x%08x\n",
2672                  xfer_info->core_if->start_hcchar_val[hc_num]);
2673 }
2674 #endif
2675
2676 void ep_xfer_timeout(void *ptr)
2677 {
2678         ep_xfer_info_t *xfer_info = NULL;
2679         int ep_num = 0;
2680         dctl_data_t dctl = {.d32 = 0 };
2681         gintsts_data_t gintsts = {.d32 = 0 };
2682         gintmsk_data_t gintmsk = {.d32 = 0 };
2683
2684         if (ptr)
2685                 xfer_info = (ep_xfer_info_t *) ptr;
2686
2687         if (!xfer_info->ep) {
2688                 DWC_ERROR("xfer_info->ep = %p\n", xfer_info->ep);
2689                 return;
2690         }
2691
2692         ep_num = xfer_info->ep->num;
2693         DWC_WARN("%s: timeout on endpoit %d\n", __func__, ep_num);
2694         /* Put the sate to 2 as it was time outed */
2695         xfer_info->state = 2;
2696
2697         dctl.d32 =
2698             DWC_READ_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl);
2699         gintsts.d32 =
2700             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintsts);
2701         gintmsk.d32 =
2702             DWC_READ_REG32(&xfer_info->core_if->core_global_regs->gintmsk);
2703
2704         if (!gintmsk.b.goutnakeff) {
2705                 /* Unmask it */
2706                 gintmsk.b.goutnakeff = 1;
2707                 DWC_WRITE_REG32(&xfer_info->core_if->core_global_regs->gintmsk,
2708                                 gintmsk.d32);
2709
2710         }
2711
2712         if (!gintsts.b.goutnakeff) {
2713                 dctl.b.sgoutnak = 1;
2714         }
2715         DWC_WRITE_REG32(&xfer_info->core_if->dev_if->dev_global_regs->dctl,
2716                         dctl.d32);
2717
2718 }
2719
2720 void set_pid_isoc(dwc_hc_t * hc)
2721 {
2722         /* Set up the initial PID for the transfer. */
2723         if (hc->speed == DWC_OTG_EP_SPEED_HIGH) {
2724                 if (hc->ep_is_in) {
2725                         if (hc->multi_count == 1) {
2726                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2727                         } else if (hc->multi_count == 2) {
2728                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2729                         } else {
2730                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA2;
2731                         }
2732                 } else {
2733                         if (hc->multi_count == 1) {
2734                                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2735                         } else {
2736                                 hc->data_pid_start = DWC_OTG_HC_PID_MDATA;
2737                         }
2738                 }
2739         } else {
2740                 hc->data_pid_start = DWC_OTG_HC_PID_DATA0;
2741         }
2742 }
2743
2744 /**
2745  * This function does the setup for a data transfer for a host channel and
2746  * starts the transfer. May be called in either Slave mode or DMA mode. In
2747  * Slave mode, the caller must ensure that there is sufficient space in the
2748  * request queue and Tx Data FIFO.
2749  *
2750  * For an OUT transfer in Slave mode, it loads a data packet into the
2751  * appropriate FIFO. If necessary, additional data packets will be loaded in
2752  * the Host ISR.
2753  *
2754  * For an IN transfer in Slave mode, a data packet is requested. The data
2755  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
2756  * additional data packets are requested in the Host ISR.
2757  *
2758  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
2759  * register along with a packet count of 1 and the channel is enabled. This
2760  * causes a single PING transaction to occur. Other fields in HCTSIZ are
2761  * simply set to 0 since no data transfer occurs in this case.
2762  *
2763  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
2764  * all the information required to perform the subsequent data transfer. In
2765  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
2766  * controller performs the entire PING protocol, then starts the data
2767  * transfer.
2768  *
2769  * @param core_if Programming view of DWC_otg controller.
2770  * @param hc Information needed to initialize the host channel. The xfer_len
2771  * value may be reduced to accommodate the max widths of the XferSize and
2772  * PktCnt fields in the HCTSIZn register. The multi_count value may be changed
2773  * to reflect the final xfer_len value.
2774  */
2775 void dwc_otg_hc_start_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2776 {
2777         hcchar_data_t hcchar;
2778         hctsiz_data_t hctsiz;
2779         uint16_t num_packets;
2780         uint32_t max_hc_xfer_size = core_if->core_params->max_transfer_size;
2781         uint16_t max_hc_pkt_count = core_if->core_params->max_packet_count;
2782         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2783
2784         hctsiz.d32 = 0;
2785
2786         if (hc->do_ping) {
2787                 if (!core_if->dma_enable) {
2788                         dwc_otg_hc_do_ping(core_if, hc);
2789                         hc->xfer_started = 1;
2790                         return;
2791                 } else {
2792                         hctsiz.b.dopng = 1;
2793                 }
2794         }
2795
2796         if (hc->do_split) {
2797                 num_packets = 1;
2798
2799                 if (hc->complete_split && !hc->ep_is_in) {
2800                         /* For CSPLIT OUT Transfer, set the size to 0 so the
2801                          * core doesn't expect any data written to the FIFO */
2802                         hc->xfer_len = 0;
2803                 } else if (hc->ep_is_in || (hc->xfer_len > hc->max_packet)) {
2804                         hc->xfer_len = hc->max_packet;
2805                 } else if (!hc->ep_is_in && (hc->xfer_len > 188)) {
2806                         hc->xfer_len = 188;
2807                 }
2808
2809                 hctsiz.b.xfersize = hc->xfer_len;
2810         } else {
2811                 /*
2812                  * Ensure that the transfer length and packet count will fit
2813                  * in the widths allocated for them in the HCTSIZn register.
2814                  */
2815                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2816                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2817                         /*
2818                          * Make sure the transfer size is no larger than one
2819                          * (micro)frame's worth of data. (A check was done
2820                          * when the periodic transfer was accepted to ensure
2821                          * that a (micro)frame's worth of data can be
2822                          * programmed into a channel.)
2823                          */
2824                         uint32_t max_periodic_len =
2825                             hc->multi_count * hc->max_packet;
2826                         if (hc->xfer_len > max_periodic_len) {
2827                                 hc->xfer_len = max_periodic_len;
2828                         } else {
2829                         }
2830                 } else if (hc->xfer_len > max_hc_xfer_size) {
2831                         /* Make sure that xfer_len is a multiple of max packet size. */
2832                         hc->xfer_len = max_hc_xfer_size - hc->max_packet + 1;
2833                 }
2834
2835                 if (hc->xfer_len > 0) {
2836                         num_packets =
2837                             (hc->xfer_len + hc->max_packet -
2838                              1) / hc->max_packet;
2839                         if (num_packets > max_hc_pkt_count) {
2840                                 num_packets = max_hc_pkt_count;
2841                                 hc->xfer_len = num_packets * hc->max_packet;
2842                         }
2843                 } else {
2844                         /* Need 1 packet for transfer length of 0. */
2845                         num_packets = 1;
2846                 }
2847
2848                 if (hc->ep_is_in) {
2849                         /* Always program an integral # of max packets for IN transfers. */
2850                         hc->xfer_len = num_packets * hc->max_packet;
2851                 }
2852
2853                 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2854                     hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2855                         /*
2856                          * Make sure that the multi_count field matches the
2857                          * actual transfer length.
2858                          */
2859                         hc->multi_count = num_packets;
2860                 }
2861
2862                 if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2863                         set_pid_isoc(hc);
2864
2865                 hctsiz.b.xfersize = hc->xfer_len;
2866         }
2867
2868         hc->start_pkt_count = num_packets;
2869         hctsiz.b.pktcnt = num_packets;
2870         hctsiz.b.pid = hc->data_pid_start;
2871         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2872
2873         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2874         DWC_DEBUGPL(DBG_HCDV, "  Xfer Size: %d\n", hctsiz.b.xfersize);
2875         DWC_DEBUGPL(DBG_HCDV, "  Num Pkts: %d\n", hctsiz.b.pktcnt);
2876         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
2877
2878         if (core_if->dma_enable) {
2879                 dwc_dma_t dma_addr;
2880                 if (hc->align_buff) {
2881                         dma_addr = hc->align_buff;
2882                 } else {
2883                         dma_addr = ((unsigned long)hc->xfer_buff & 0xffffffff);
2884                 }
2885                 DWC_WRITE_REG32(&hc_regs->hcdma, dma_addr);
2886         }
2887
2888         /* Start the split */
2889         if (hc->do_split) {
2890                 hcsplt_data_t hcsplt;
2891                 hcsplt.d32 = DWC_READ_REG32(&hc_regs->hcsplt);
2892                 hcsplt.b.spltena = 1;
2893                 DWC_WRITE_REG32(&hc_regs->hcsplt, hcsplt.d32);
2894         }
2895
2896         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2897         hcchar.b.multicnt = hc->multi_count;
2898         hc_set_even_odd_frame(core_if, hc, &hcchar);
2899 #ifdef DEBUG
2900         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2901         if (hcchar.b.chdis) {
2902                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2903                          __func__, hc->hc_num, hcchar.d32);
2904         }
2905 #endif
2906
2907         /* Set host channel enable after all other setup is complete. */
2908         hcchar.b.chen = 1;
2909         hcchar.b.chdis = 0;
2910         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2911
2912         hc->xfer_started = 1;
2913         hc->requests++;
2914
2915         if (!core_if->dma_enable && !hc->ep_is_in && hc->xfer_len > 0) {
2916                 /* Load OUT packet into the appropriate Tx FIFO. */
2917                 dwc_otg_hc_write_packet(core_if, hc);
2918         }
2919 #ifdef DEBUG
2920         if (hc->ep_type != DWC_OTG_EP_TYPE_INTR) {
2921                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
2922                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
2923
2924                 /* Start a timer for this transfer. */
2925                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
2926         }
2927 #endif
2928 }
2929
2930 /**
2931  * This function does the setup for a data transfer for a host channel
2932  * and starts the transfer in Descriptor DMA mode.
2933  *
2934  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
2935  * Sets PID and NTD values. For periodic transfers
2936  * initializes SCHED_INFO field with micro-frame bitmap.
2937  *
2938  * Initializes HCDMA register with descriptor list address and CTD value
2939  * then starts the transfer via enabling the channel.
2940  *
2941  * @param core_if Programming view of DWC_otg controller.
2942  * @param hc Information needed to initialize the host channel.
2943  */
2944 void dwc_otg_hc_start_transfer_ddma(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
2945 {
2946         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
2947         hcchar_data_t hcchar;
2948         hctsiz_data_t hctsiz;
2949         hcdma_data_t hcdma;
2950
2951         hctsiz.d32 = 0;
2952
2953         if (hc->do_ping)
2954                 hctsiz.b_ddma.dopng = 1;
2955
2956         if (hc->ep_type == DWC_OTG_EP_TYPE_ISOC)
2957                 set_pid_isoc(hc);
2958
2959         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
2960         hctsiz.b_ddma.pid = hc->data_pid_start;
2961         hctsiz.b_ddma.ntd = hc->ntd - 1;        /* 0 - 1 descriptor, 1 - 2 descriptors, etc. */
2962         hctsiz.b_ddma.schinfo = hc->schinfo;    /* Non-zero only for high-speed interrupt endpoints */
2963
2964         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
2965         DWC_DEBUGPL(DBG_HCDV, "  Start PID: %d\n", hctsiz.b.pid);
2966         DWC_DEBUGPL(DBG_HCDV, "  NTD: %d\n", hctsiz.b_ddma.ntd);
2967
2968         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
2969
2970         hcdma.d32 = 0;
2971         hcdma.b.dma_addr = ((uint32_t) hc->desc_list_addr) >> 11;
2972
2973         /* Always start from first descriptor. */
2974         hcdma.b.ctd = 0;
2975         DWC_WRITE_REG32(&hc_regs->hcdma, hcdma.d32);
2976
2977         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
2978         hcchar.b.multicnt = hc->multi_count;
2979
2980 #ifdef DEBUG
2981         core_if->start_hcchar_val[hc->hc_num] = hcchar.d32;
2982         if (hcchar.b.chdis) {
2983                 DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n",
2984                          __func__, hc->hc_num, hcchar.d32);
2985         }
2986 #endif
2987
2988         /* Set host channel enable after all other setup is complete. */
2989         hcchar.b.chen = 1;
2990         hcchar.b.chdis = 0;
2991
2992         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
2993
2994         hc->xfer_started = 1;
2995         hc->requests++;
2996
2997 #ifdef DEBUG
2998         if ((hc->ep_type != DWC_OTG_EP_TYPE_INTR)
2999             && (hc->ep_type != DWC_OTG_EP_TYPE_ISOC)) {
3000                 core_if->hc_xfer_info[hc->hc_num].core_if = core_if;
3001                 core_if->hc_xfer_info[hc->hc_num].hc = hc;
3002                 /* Start a timer for this transfer. */
3003                 DWC_TIMER_SCHEDULE(core_if->hc_xfer_timer[hc->hc_num], 10000);
3004         }
3005 #endif
3006
3007 }
3008
3009 /**
3010  * This function continues a data transfer that was started by previous call
3011  * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is
3012  * sufficient space in the request queue and Tx Data FIFO. This function
3013  * should only be called in Slave mode. In DMA mode, the controller acts
3014  * autonomously to complete transfers programmed to a host channel.
3015  *
3016  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
3017  * if there is any data remaining to be queued. For an IN transfer, another
3018  * data packet is always requested. For the SETUP phase of a control transfer,
3019  * this function does nothing.
3020  *
3021  * @return 1 if a new request is queued, 0 if no more requests are required
3022  * for this transfer.
3023  */
3024 int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3025 {
3026         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3027
3028         if (hc->do_split) {
3029                 /* SPLITs always queue just once per channel */
3030                 return 0;
3031         } else if (hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3032                 /* SETUPs are queued only once since they can't be NAKed. */
3033                 return 0;
3034         } else if (hc->ep_is_in) {
3035                 /*
3036                  * Always queue another request for other IN transfers. If
3037                  * back-to-back INs are issued and NAKs are received for both,
3038                  * the driver may still be processing the first NAK when the
3039                  * second NAK is received. When the interrupt handler clears
3040                  * the NAK interrupt for the first NAK, the second NAK will
3041                  * not be seen. So we can't depend on the NAK interrupt
3042                  * handler to requeue a NAKed request. Instead, IN requests
3043                  * are issued each time this function is called. When the
3044                  * transfer completes, the extra requests for the channel will
3045                  * be flushed.
3046                  */
3047                 hcchar_data_t hcchar;
3048                 dwc_otg_hc_regs_t *hc_regs =
3049                     core_if->host_if->hc_regs[hc->hc_num];
3050
3051                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3052                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3053                 hcchar.b.chen = 1;
3054                 hcchar.b.chdis = 0;
3055                 DWC_DEBUGPL(DBG_HCDV, "  IN xfer: hcchar = 0x%08x\n",
3056                             hcchar.d32);
3057                 DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3058                 hc->requests++;
3059                 return 1;
3060         } else {
3061                 /* OUT transfers. */
3062                 if (hc->xfer_count < hc->xfer_len) {
3063                         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
3064                             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
3065                                 hcchar_data_t hcchar;
3066                                 dwc_otg_hc_regs_t *hc_regs;
3067                                 hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3068                                 hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3069                                 hc_set_even_odd_frame(core_if, hc, &hcchar);
3070                         }
3071
3072                         /* Load OUT packet into the appropriate Tx FIFO. */
3073                         dwc_otg_hc_write_packet(core_if, hc);
3074                         hc->requests++;
3075                         return 1;
3076                 } else {
3077                         return 0;
3078                 }
3079         }
3080 }
3081
3082 /**
3083  * Starts a PING transfer. This function should only be called in Slave mode.
3084  * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled.
3085  */
3086 void dwc_otg_hc_do_ping(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3087 {
3088         hcchar_data_t hcchar;
3089         hctsiz_data_t hctsiz;
3090         dwc_otg_hc_regs_t *hc_regs = core_if->host_if->hc_regs[hc->hc_num];
3091
3092         DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, hc->hc_num);
3093
3094         hctsiz.d32 = 0;
3095         hctsiz.b.dopng = 1;
3096         hctsiz.b.pktcnt = 1;
3097         DWC_WRITE_REG32(&hc_regs->hctsiz, hctsiz.d32);
3098
3099         hcchar.d32 = DWC_READ_REG32(&hc_regs->hcchar);
3100         hcchar.b.chen = 1;
3101         hcchar.b.chdis = 0;
3102         DWC_WRITE_REG32(&hc_regs->hcchar, hcchar.d32);
3103 }
3104
3105 /*
3106  * This function writes a packet into the Tx FIFO associated with the Host
3107  * Channel. For a channel associated with a non-periodic EP, the non-periodic
3108  * Tx FIFO is written. For a channel associated with a periodic EP, the
3109  * periodic Tx FIFO is written. This function should only be called in Slave
3110  * mode.
3111  *
3112  * Upon return the xfer_buff and xfer_count fields in _hc are incremented by
3113  * then number of bytes written to the Tx FIFO.
3114  */
3115 void dwc_otg_hc_write_packet(dwc_otg_core_if_t * core_if, dwc_hc_t * hc)
3116 {
3117         uint32_t i;
3118         uint32_t remaining_count;
3119         uint32_t byte_count;
3120         uint32_t dword_count;
3121
3122         uint32_t *data_buff = (uint32_t *) (hc->xfer_buff);
3123         uint32_t *data_fifo = core_if->data_fifo[hc->hc_num];
3124
3125         remaining_count = hc->xfer_len - hc->xfer_count;
3126         if (remaining_count > hc->max_packet) {
3127                 byte_count = hc->max_packet;
3128         } else {
3129                 byte_count = remaining_count;
3130         }
3131
3132         dword_count = (byte_count + 3) / 4;
3133
3134         if ((((unsigned long)data_buff) & 0x3) == 0) {
3135                 /* xfer_buff is DWORD aligned. */
3136                 for (i = 0; i < dword_count; i++, data_buff++) {
3137                         DWC_WRITE_REG32(data_fifo, *data_buff);
3138                 }
3139         } else {
3140                 /* xfer_buff is not DWORD aligned. */
3141                 for (i = 0; i < dword_count; i++, data_buff++) {
3142                         uint32_t data;
3143                         data =
3144                             (data_buff[0] | data_buff[1] << 8 | data_buff[2] <<
3145                              16 | data_buff[3] << 24);
3146                         DWC_WRITE_REG32(data_fifo, data);
3147                 }
3148         }
3149
3150         hc->xfer_count += byte_count;
3151         hc->xfer_buff += byte_count;
3152 }
3153
3154 /**
3155  * Gets the current USB frame number. This is the frame number from the last
3156  * SOF packet.
3157  */
3158 uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t * core_if)
3159 {
3160         dsts_data_t dsts;
3161         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
3162
3163         /* read current frame/microframe number from DSTS register */
3164         return dsts.b.soffn;
3165 }
3166
3167 /**
3168  * Calculates and gets the frame Interval value of HFIR register according PHY
3169  * type and speed.The application can modify a value of HFIR register only after
3170  * the Port Enable bit of the Host Port Control and Status register
3171  * (HPRT.PrtEnaPort) has been set.
3172 */
3173
3174 uint32_t calc_frame_interval(dwc_otg_core_if_t * core_if)
3175 {
3176         gusbcfg_data_t usbcfg;
3177         hwcfg2_data_t hwcfg2;
3178         hprt0_data_t hprt0;
3179         int clock = 60;         // default value
3180         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
3181         hwcfg2.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg2);
3182         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
3183         if (!usbcfg.b.physel && usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3184                 clock = 60;
3185         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 3)
3186                 clock = 48;
3187         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3188             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3189                 clock = 30;
3190         if (!usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3191             !usbcfg.b.ulpi_utmi_sel && !usbcfg.b.phyif)
3192                 clock = 60;
3193         if (usbcfg.b.phylpwrclksel && !usbcfg.b.physel &&
3194             !usbcfg.b.ulpi_utmi_sel && usbcfg.b.phyif)
3195                 clock = 48;
3196         if (usbcfg.b.physel && !usbcfg.b.phyif && hwcfg2.b.fs_phy_type == 2)
3197                 clock = 48;
3198         if (usbcfg.b.physel && hwcfg2.b.fs_phy_type == 1)
3199                 clock = 48;
3200         if (hprt0.b.prtspd == 0)
3201                 /* High speed case */
3202                 return 125 * clock;
3203         else
3204                 /* FS/LS case */
3205                 return 1000 * clock;
3206 }
3207
3208 /**
3209  * This function reads a setup packet from the Rx FIFO into the destination
3210  * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl)
3211  * Interrupt routine when a SETUP packet has been received in Slave mode.
3212  *
3213  * @param core_if Programming view of DWC_otg controller.
3214  * @param dest Destination buffer for packet data.
3215  */
3216 void dwc_otg_read_setup_packet(dwc_otg_core_if_t * core_if, uint32_t * dest)
3217 {
3218         device_grxsts_data_t status;
3219         /* Get the 8 bytes of a setup transaction data */
3220
3221         /* Pop 2 DWORDS off the receive data FIFO into memory */
3222         dest[0] = DWC_READ_REG32(core_if->data_fifo[0]);
3223         dest[1] = DWC_READ_REG32(core_if->data_fifo[0]);
3224         if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
3225                 status.d32 =
3226                     DWC_READ_REG32(&core_if->core_global_regs->grxstsp);
3227                 DWC_DEBUGPL(DBG_ANY,
3228                             "EP:%d BCnt:%d " "pktsts:%x Frame:%d(0x%0x)\n",
3229                             status.b.epnum, status.b.bcnt, status.b.pktsts,
3230                             status.b.fn, status.b.fn);
3231         }
3232 }
3233
3234 /**
3235  * This function enables EP0 OUT to receive SETUP packets and configures EP0
3236  * IN for transmitting packets. It is normally called when the
3237  * "Enumeration Done" interrupt occurs.
3238  *
3239  * @param core_if Programming view of DWC_otg controller.
3240  * @param ep The EP0 data.
3241  */
3242 void dwc_otg_ep0_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3243 {
3244         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3245         dsts_data_t dsts;
3246         depctl_data_t diepctl;
3247         depctl_data_t doepctl;
3248         dctl_data_t dctl = {.d32 = 0 };
3249
3250         ep->stp_rollover = 0;
3251         /* Read the Device Status and Endpoint 0 Control registers */
3252         dsts.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dsts);
3253         diepctl.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl);
3254         doepctl.d32 = DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl);
3255
3256         /* Set the MPS of the IN EP based on the enumeration speed */
3257         switch (dsts.b.enumspd) {
3258         case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
3259         case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
3260         case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ:
3261                 diepctl.b.mps = DWC_DEP0CTL_MPS_64;
3262                 break;
3263         case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ:
3264                 diepctl.b.mps = DWC_DEP0CTL_MPS_8;
3265                 break;
3266         }
3267
3268         DWC_WRITE_REG32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32);
3269
3270         /* Enable OUT EP for receive */
3271         if (core_if->snpsid <= OTG_CORE_REV_2_94a) {
3272                 doepctl.b.epena = 1;
3273                 DWC_WRITE_REG32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32);
3274         }
3275 #ifdef VERBOSE
3276         DWC_DEBUGPL(DBG_PCDV, "doepctl0=%0x\n",
3277                     DWC_READ_REG32(&dev_if->out_ep_regs[0]->doepctl));
3278         DWC_DEBUGPL(DBG_PCDV, "diepctl0=%0x\n",
3279                     DWC_READ_REG32(&dev_if->in_ep_regs[0]->diepctl));
3280 #endif
3281         dctl.b.cgnpinnak = 1;
3282
3283         DWC_MODIFY_REG32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32);
3284         DWC_DEBUGPL(DBG_PCDV, "dctl=%0x\n",
3285                     DWC_READ_REG32(&dev_if->dev_global_regs->dctl));
3286
3287 }
3288
3289 /**
3290  * This function activates an EP.  The Device EP control register for
3291  * the EP is configured as defined in the ep structure. Note: This
3292  * function is not used for EP0.
3293  *
3294  * @param core_if Programming view of DWC_otg controller.
3295  * @param ep The EP to activate.
3296  */
3297 void dwc_otg_ep_activate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3298 {
3299         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3300         depctl_data_t depctl;
3301         volatile uint32_t *addr;
3302         daint_data_t daintmsk = {.d32 = 0 };
3303         dcfg_data_t dcfg;
3304         uint8_t i;
3305
3306         DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, ep->num,
3307                     (ep->is_in ? "IN" : "OUT"));
3308
3309 #ifdef DWC_UTE_PER_IO
3310         ep->xiso_frame_num = 0xFFFFFFFF;
3311         ep->xiso_active_xfers = 0;
3312         ep->xiso_queued_xfers = 0;
3313 #endif
3314         /* Read DEPCTLn register */
3315         if (ep->is_in == 1) {
3316                 addr = &dev_if->in_ep_regs[ep->num]->diepctl;
3317                 daintmsk.ep.in = 1 << ep->num;
3318         } else {
3319                 addr = &dev_if->out_ep_regs[ep->num]->doepctl;
3320                 daintmsk.ep.out = 1 << ep->num;
3321         }
3322
3323         /* If the EP is already active don't change the EP Control
3324          * register. */
3325         depctl.d32 = DWC_READ_REG32(addr);
3326         if (!depctl.b.usbactep) {
3327                 depctl.b.mps = ep->maxpacket;
3328                 depctl.b.eptype = ep->type;
3329                 depctl.b.txfnum = ep->tx_fifo_num;
3330
3331                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3332                         depctl.b.setd0pid = 1;  // ???
3333                 } else {
3334                         depctl.b.setd0pid = 1;
3335                 }
3336                 depctl.b.usbactep = 1;
3337
3338                 /* Update nextep_seq array and EPMSCNT in DCFG */
3339                 if (!(depctl.b.eptype & 1) && (ep->is_in == 1)) {       // NP IN EP
3340                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3341                                 if (core_if->nextep_seq[i] == core_if->first_in_nextep_seq)
3342                                         break;
3343                         }
3344                         core_if->nextep_seq[i] = ep->num;
3345                         core_if->nextep_seq[ep->num] = core_if->first_in_nextep_seq;
3346                         depctl.b.nextep = core_if->nextep_seq[ep->num];
3347                         dcfg.d32 = DWC_READ_REG32(&dev_if->dev_global_regs->dcfg);
3348                         dcfg.b.epmscnt++;
3349                         DWC_WRITE_REG32(&dev_if->dev_global_regs->dcfg, dcfg.d32);
3350
3351                         DWC_DEBUGPL(DBG_PCDV,
3352                                     "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3353                                     __func__, core_if->first_in_nextep_seq);
3354                         for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3355                                 DWC_DEBUGPL(DBG_PCDV, "%2d\n",
3356                                             core_if->nextep_seq[i]);
3357                         }
3358
3359                 }
3360
3361
3362                 DWC_WRITE_REG32(addr, depctl.d32);
3363                 DWC_DEBUGPL(DBG_PCDV, "DEPCTL=%08x\n", DWC_READ_REG32(addr));
3364         }
3365
3366         /* Enable the Interrupt for this EP */
3367         if (core_if->multiproc_int_enable) {
3368                 if (ep->is_in == 1) {
3369                         diepmsk_data_t diepmsk = {.d32 = 0 };
3370                         diepmsk.b.xfercompl = 1;
3371                         diepmsk.b.timeout = 1;
3372                         diepmsk.b.epdisabled = 1;
3373                         diepmsk.b.ahberr = 1;
3374                         diepmsk.b.intknepmis = 1;
3375                         if (!core_if->en_multiple_tx_fifo && core_if->dma_enable)
3376                                 diepmsk.b.intknepmis = 0;
3377                         diepmsk.b.txfifoundrn = 1;      //?????
3378                         if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3379                                 diepmsk.b.nak = 1;
3380                         }
3381
3382 /*
3383                         if (core_if->dma_desc_enable) {
3384                                 diepmsk.b.bna = 1;
3385                         }
3386 */
3387 /*
3388                         if (core_if->dma_enable) {
3389                                 doepmsk.b.nak = 1;
3390                         }
3391 */
3392                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
3393                                         diepeachintmsk[ep->num], diepmsk.d32);
3394
3395                 } else {
3396                         doepmsk_data_t doepmsk = {.d32 = 0 };
3397                         doepmsk.b.xfercompl = 1;
3398                         doepmsk.b.ahberr = 1;
3399                         doepmsk.b.epdisabled = 1;
3400                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3401                                 doepmsk.b.outtknepdis = 1;
3402
3403 /*
3404
3405                         if (core_if->dma_desc_enable) {
3406                                 doepmsk.b.bna = 1;
3407                         }
3408 */
3409 /*
3410                         doepmsk.b.babble = 1;
3411                         doepmsk.b.nyet = 1;
3412                         doepmsk.b.nak = 1;
3413 */
3414                         DWC_WRITE_REG32(&dev_if->dev_global_regs->
3415                                         doepeachintmsk[ep->num], doepmsk.d32);
3416                 }
3417                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->deachintmsk,
3418                                  0, daintmsk.d32);
3419         } else {
3420                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3421                         if (ep->is_in) {
3422                                 diepmsk_data_t diepmsk = {.d32 = 0 };
3423                                 diepmsk.b.nak = 1;
3424                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->diepmsk, 0, diepmsk.d32);
3425                         } else {
3426                                 doepmsk_data_t doepmsk = {.d32 = 0 };
3427                                 doepmsk.b.outtknepdis = 1;
3428                                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->doepmsk, 0, doepmsk.d32);
3429                         }
3430                 }
3431                 DWC_MODIFY_REG32(&dev_if->dev_global_regs->daintmsk,
3432                                  0, daintmsk.d32);
3433         }
3434
3435         DWC_DEBUGPL(DBG_PCDV, "DAINTMSK=%0x\n",
3436                     DWC_READ_REG32(&dev_if->dev_global_regs->daintmsk));
3437
3438         ep->stall_clear_flag = 0;
3439
3440         return;
3441 }
3442
3443 /**
3444  * This function deactivates an EP. This is done by clearing the USB Active
3445  * EP bit in the Device EP control register. Note: This function is not used
3446  * for EP0. EP0 cannot be deactivated.
3447  *
3448  * @param core_if Programming view of DWC_otg controller.
3449  * @param ep The EP to deactivate.
3450  */
3451 void dwc_otg_ep_deactivate(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3452 {
3453         depctl_data_t depctl = {.d32 = 0 };
3454         volatile uint32_t *addr;
3455         daint_data_t daintmsk = {.d32 = 0 };
3456         dcfg_data_t dcfg;
3457         uint8_t i = 0;
3458
3459 #ifdef DWC_UTE_PER_IO
3460         ep->xiso_frame_num = 0xFFFFFFFF;
3461         ep->xiso_active_xfers = 0;
3462         ep->xiso_queued_xfers = 0;
3463 #endif
3464
3465         /* Read DEPCTLn register */
3466         if (ep->is_in == 1) {
3467                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
3468                 daintmsk.ep.in = 1 << ep->num;
3469         } else {
3470                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
3471                 daintmsk.ep.out = 1 << ep->num;
3472         }
3473
3474         depctl.d32 = DWC_READ_REG32(addr);
3475
3476         depctl.b.usbactep = 0;
3477
3478         /* Update nextep_seq array and EPMSCNT in DCFG */
3479         if (!(depctl.b.eptype & 1) && ep->is_in == 1) { // NP EP IN
3480                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3481                         if (core_if->nextep_seq[i] == ep->num)
3482                                 break;
3483                 }
3484                 core_if->nextep_seq[i] = core_if->nextep_seq[ep->num];
3485                 if (core_if->first_in_nextep_seq == ep->num)
3486                         core_if->first_in_nextep_seq = i;
3487                 core_if->nextep_seq[ep->num] = 0xff;
3488                 depctl.b.nextep = 0;
3489                 dcfg.d32 =
3490                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
3491                 dcfg.b.epmscnt--;
3492                 DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg,
3493                                 dcfg.d32);
3494
3495                 DWC_DEBUGPL(DBG_PCDV,
3496                             "%s first_in_nextep_seq= %2d; nextep_seq[]:\n",
3497                             __func__, core_if->first_in_nextep_seq);
3498                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
3499                         DWC_DEBUGPL(DBG_PCDV, "%2d\n", core_if->nextep_seq[i]);
3500                 }
3501         }
3502
3503         if (ep->is_in == 1)
3504                 depctl.b.txfnum = 0;
3505
3506         if (core_if->dma_desc_enable)
3507                 depctl.b.epdis = 1;
3508
3509         DWC_WRITE_REG32(addr, depctl.d32);
3510         depctl.d32 = DWC_READ_REG32(addr);
3511         if (core_if->dma_enable && ep->type == DWC_OTG_EP_TYPE_ISOC
3512             && depctl.b.epena) {
3513                 depctl_data_t depctl = {.d32 = 0 };
3514                 if (ep->is_in) {
3515                         diepint_data_t diepint = {.d32 = 0 };
3516
3517                         depctl.b.snak = 1;
3518                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3519                                         diepctl, depctl.d32);
3520                         do {
3521                                 dwc_udelay(10);
3522                                 diepint.d32 =
3523                                     DWC_READ_REG32(&core_if->
3524                                                    dev_if->in_ep_regs[ep->num]->
3525                                                    diepint);
3526                         } while (!diepint.b.inepnakeff);
3527                         diepint.b.inepnakeff = 1;
3528                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3529                                         diepint, diepint.d32);
3530                         depctl.d32 = 0;
3531                         depctl.b.epdis = 1;
3532                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3533                                         diepctl, depctl.d32);
3534                         do {
3535                                 dwc_udelay(10);
3536                                 diepint.d32 =
3537                                     DWC_READ_REG32(&core_if->
3538                                                    dev_if->in_ep_regs[ep->num]->
3539                                                    diepint);
3540                         } while (!diepint.b.epdisabled);
3541                         diepint.b.epdisabled = 1;
3542                         DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
3543                                         diepint, diepint.d32);
3544                 } else {
3545                         dctl_data_t dctl = {.d32 = 0};
3546                         gintmsk_data_t gintsts = {.d32 = 0};
3547                         doepint_data_t doepint = {.d32 = 0};
3548                         dctl.b.sgoutnak = 1;
3549                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->
3550                                          dctl, 0, dctl.d32);
3551                         do {
3552                                 dwc_udelay(10);
3553                                 gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
3554                         } while (!gintsts.b.goutnakeff);
3555                         gintsts.d32 = 0;
3556                         gintsts.b.goutnakeff = 1;
3557                         DWC_WRITE_REG32(&core_if->core_global_regs->gintsts, gintsts.d32);
3558
3559                         depctl.d32 = 0;
3560                         depctl.b.epdis = 1;
3561                         depctl.b.snak = 1;
3562                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepctl, depctl.d32);
3563                         do
3564                         {
3565                                 dwc_udelay(10);
3566                                 doepint.d32 = DWC_READ_REG32(&core_if->dev_if->
3567                                                                                         out_ep_regs[ep->num]->doepint);
3568                         } while (!doepint.b.epdisabled);
3569
3570                         doepint.b.epdisabled = 1;
3571                         DWC_WRITE_REG32(&core_if->dev_if->out_ep_regs[ep->num]->doepint, doepint.d32);
3572
3573                         dctl.d32 = 0;
3574                         dctl.b.cgoutnak = 1;
3575                         DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->dctl, 0, dctl.d32);
3576                 }
3577         }
3578
3579         /* Disable the Interrupt for this EP */
3580         if (core_if->multiproc_int_enable) {
3581                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->deachintmsk,
3582                                  daintmsk.d32, 0);
3583
3584                 if (ep->is_in == 1) {
3585                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
3586                                         diepeachintmsk[ep->num], 0);
3587                 } else {
3588                         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->
3589                                         doepeachintmsk[ep->num], 0);
3590                 }
3591         } else {
3592                 DWC_MODIFY_REG32(&core_if->dev_if->dev_global_regs->daintmsk,
3593                                  daintmsk.d32, 0);
3594         }
3595
3596 }
3597
3598 /**
3599  * This function initializes dma descriptor chain.
3600  *
3601  * @param core_if Programming view of DWC_otg controller.
3602  * @param ep The EP to start the transfer on.
3603  */
3604 static void init_dma_desc_chain(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3605 {
3606         dwc_otg_dev_dma_desc_t *dma_desc;
3607         uint32_t offset;
3608         uint32_t xfer_est;
3609         int i;
3610         unsigned maxxfer_local, total_len;
3611
3612         if (!ep->is_in && ep->type == DWC_OTG_EP_TYPE_INTR &&
3613             (ep->maxpacket % 4)) {
3614                 maxxfer_local = ep->maxpacket;
3615                 total_len = ep->xfer_len;
3616         } else {
3617                 maxxfer_local = ep->maxxfer;
3618                 total_len = ep->total_len;
3619         }
3620
3621         ep->desc_cnt = (total_len / maxxfer_local) +
3622             ((total_len % maxxfer_local) ? 1 : 0);
3623
3624         if (!ep->desc_cnt)
3625                 ep->desc_cnt = 1;
3626
3627         if (ep->desc_cnt > MAX_DMA_DESC_CNT)
3628                 ep->desc_cnt = MAX_DMA_DESC_CNT;
3629
3630         dma_desc = ep->desc_addr;
3631         if (maxxfer_local == ep->maxpacket) {
3632                 if ((total_len % maxxfer_local) &&
3633                     (total_len / maxxfer_local < MAX_DMA_DESC_CNT)) {
3634                         xfer_est = (ep->desc_cnt - 1) * maxxfer_local +
3635                             (total_len % maxxfer_local);
3636                 } else
3637                         xfer_est = ep->desc_cnt * maxxfer_local;
3638         } else
3639                 xfer_est = total_len;
3640         offset = 0;
3641         for (i = 0; i < ep->desc_cnt; ++i) {
3642                 /** DMA Descriptor Setup */
3643                 if (xfer_est > maxxfer_local) {
3644                         dma_desc->status.b.bs = BS_HOST_BUSY;
3645                         dma_desc->status.b.l = 0;
3646                         dma_desc->status.b.ioc = 0;
3647                         dma_desc->status.b.sp = 0;
3648                         dma_desc->status.b.bytes = maxxfer_local;
3649                         dma_desc->buf = ep->dma_addr + offset;
3650                         dma_desc->status.b.sts = 0;
3651                         dma_desc->status.b.bs = BS_HOST_READY;
3652
3653                         xfer_est -= maxxfer_local;
3654                         offset += maxxfer_local;
3655                 } else {
3656                         dma_desc->status.b.bs = BS_HOST_BUSY;
3657                         dma_desc->status.b.l = 1;
3658                         dma_desc->status.b.ioc = 1;
3659                         if (ep->is_in) {
3660                                 dma_desc->status.b.sp =
3661                                     (xfer_est %
3662                                      ep->maxpacket) ? 1 : ((ep->
3663                                                             sent_zlp) ? 1 : 0);
3664                                 dma_desc->status.b.bytes = xfer_est;
3665                         } else {
3666                                 if (maxxfer_local == ep->maxpacket)
3667                                         dma_desc->status.b.bytes = xfer_est;
3668                                 else
3669                                         dma_desc->status.b.bytes =
3670                                                 xfer_est + ((4 - (xfer_est & 0x3)) & 0x3);
3671                         }
3672
3673                         dma_desc->buf = ep->dma_addr + offset;
3674                         dma_desc->status.b.sts = 0;
3675                         dma_desc->status.b.bs = BS_HOST_READY;
3676                 }
3677                 dma_desc++;
3678         }
3679 }
3680
3681 /**
3682  * This function is called when to write ISOC data into appropriate dedicated
3683  * periodic FIFO.
3684  */
3685 static int32_t write_isoc_tx_fifo(dwc_otg_core_if_t * core_if, dwc_ep_t * dwc_ep)
3686 {
3687         dwc_otg_dev_if_t *dev_if = core_if->dev_if;
3688         dwc_otg_dev_in_ep_regs_t *ep_regs;
3689         dtxfsts_data_t txstatus = {.d32 = 0 };
3690         uint32_t len = 0;
3691         int epnum = dwc_ep->num;
3692         int dwords;
3693
3694         DWC_DEBUGPL(DBG_PCD, "Dedicated TxFifo Empty: %d \n", epnum);
3695
3696         ep_regs = core_if->dev_if->in_ep_regs[epnum];
3697
3698         len = dwc_ep->xfer_len - dwc_ep->xfer_count;
3699
3700         if (len > dwc_ep->maxpacket) {
3701                 len = dwc_ep->maxpacket;
3702         }
3703
3704         dwords = (len + 3) / 4;
3705
3706         /* While there is space in the queue and space in the FIFO and
3707          * More data to tranfer, Write packets to the Tx FIFO */
3708         txstatus.d32 = DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
3709         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum, txstatus.d32);
3710
3711         while (txstatus.b.txfspcavail > dwords &&
3712                dwc_ep->xfer_count < dwc_ep->xfer_len && dwc_ep->xfer_len != 0) {
3713                 /* Write the FIFO */
3714                 dwc_otg_ep_write_packet(core_if, dwc_ep, 0);
3715
3716                 len = dwc_ep->xfer_len - dwc_ep->xfer_count;
3717                 if (len > dwc_ep->maxpacket) {
3718                         len = dwc_ep->maxpacket;
3719                 }
3720
3721                 dwords = (len + 3) / 4;
3722                 txstatus.d32 =
3723                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts);
3724                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", epnum,
3725                             txstatus.d32);
3726         }
3727
3728         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", epnum,
3729                     DWC_READ_REG32(&dev_if->in_ep_regs[epnum]->dtxfsts));
3730
3731         return 1;
3732 }
3733
3734 /**
3735  * This function does the setup for a data transfer for an EP and
3736  * starts the transfer. For an IN transfer, the packets will be
3737  * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers,
3738  * the packets are unloaded from the Rx FIFO in the ISR.  the ISR.
3739  *
3740  * @param core_if Programming view of DWC_otg controller.
3741  * @param ep The EP to start the transfer on.
3742  */
3743
3744 void dwc_otg_ep_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
3745 {
3746         depctl_data_t depctl;
3747         deptsiz_data_t deptsiz;
3748         gintmsk_data_t intr_mask = {.d32 = 0 };
3749
3750         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
3751         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
3752                     "xfer_buff=%p start_xfer_buff=%p, total_len = %d\n",
3753                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
3754                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff,
3755                     ep->total_len);
3756         /* IN endpoint */
3757         if (ep->is_in == 1) {
3758                 dwc_otg_dev_in_ep_regs_t *in_regs =
3759                     core_if->dev_if->in_ep_regs[ep->num];
3760
3761                 gnptxsts_data_t gtxstatus;
3762
3763                 gtxstatus.d32 =
3764                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
3765
3766                 if (core_if->en_multiple_tx_fifo == 0
3767                     && gtxstatus.b.nptxqspcavail == 0 && !core_if->dma_enable) {
3768 #ifdef DEBUG
3769                         DWC_PRINTF("TX Queue Full (0x%0x)\n", gtxstatus.d32);
3770 #endif
3771                         return;
3772                 }
3773
3774                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
3775                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
3776
3777                 if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
3778                         ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3779                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
3780                 else
3781                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len - ep->xfer_len)) ?
3782                                  MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
3783
3784
3785                 /* Zero Length Packet? */
3786                 if ((ep->xfer_len - ep->xfer_count) == 0) {
3787                         deptsiz.b.xfersize = 0;
3788                         deptsiz.b.pktcnt = 1;
3789                 } else {
3790                         /* Program the transfer size and packet count
3791                          *      as follows: xfersize = N * maxpacket +
3792                          *      short_packet pktcnt = N + (short_packet
3793                          *      exist ? 1 : 0)
3794                          */
3795                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3796                         deptsiz.b.pktcnt =
3797                             (ep->xfer_len - ep->xfer_count - 1 +
3798                              ep->maxpacket) / ep->maxpacket;
3799                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
3800                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
3801                                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
3802                         }
3803                         if (ep->type == DWC_OTG_EP_TYPE_ISOC)
3804                                 deptsiz.b.mc = deptsiz.b.pktcnt;
3805                 }
3806
3807                 /* Write the DMA register */
3808                 if (core_if->dma_enable) {
3809                         if (core_if->dma_desc_enable == 0) {
3810                                 if (ep->type != DWC_OTG_EP_TYPE_ISOC)
3811                                         deptsiz.b.mc = 1;
3812                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
3813                                                 deptsiz.d32);
3814                                 DWC_WRITE_REG32(&(in_regs->diepdma),
3815                                                 (uint32_t) ep->dma_addr);
3816                         } else {
3817 #ifdef DWC_UTE_CFI
3818                                 /* The descriptor chain should be already initialized by now */
3819                                 if (ep->buff_mode != BM_STANDARD) {
3820                                         DWC_WRITE_REG32(&in_regs->diepdma,
3821                                                         ep->descs_dma_addr);
3822                                 } else {
3823 #endif
3824                                         init_dma_desc_chain(core_if, ep);
3825                                 /** DIEPDMAn Register write */
3826                                         DWC_WRITE_REG32(&in_regs->diepdma,
3827                                                         ep->dma_desc_addr);
3828 #ifdef DWC_UTE_CFI
3829                                 }
3830 #endif
3831                         }
3832                 } else {
3833                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
3834                         if (ep->type != DWC_OTG_EP_TYPE_ISOC) {
3835                                 /**
3836                                  * Enable the Non-Periodic Tx FIFO empty interrupt,
3837                                  * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
3838                                  * the data will be written into the fifo by the ISR.
3839                                  */
3840                                 if (core_if->en_multiple_tx_fifo == 0) {
3841                                         intr_mask.b.nptxfempty = 1;
3842                                         DWC_MODIFY_REG32
3843                                             (&core_if->core_global_regs->gintmsk,
3844                                              intr_mask.d32, intr_mask.d32);
3845                                 } else {
3846                                         /* Enable the Tx FIFO Empty Interrupt for this EP */
3847                                         if (ep->xfer_len > 0) {
3848                                                 uint32_t fifoemptymsk = 0;
3849                                                 fifoemptymsk = 1 << ep->num;
3850                                                 DWC_MODIFY_REG32
3851                                                     (&core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
3852                                                      0, fifoemptymsk);
3853
3854                                         }
3855                                 }
3856                         } else {
3857                                 write_isoc_tx_fifo(core_if, ep);
3858                         }
3859                 }
3860                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
3861                         depctl.b.nextep = core_if->nextep_seq[ep->num];
3862
3863                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3864                         dsts_data_t dsts = {.d32 = 0 };
3865                         if (ep->bInterval == 1) {
3866                                 dsts.d32 =
3867                                     DWC_READ_REG32(&core_if->dev_if->
3868                                                    dev_global_regs->dsts);
3869                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
3870                                 if (ep->frame_num > 0x3FFF) {
3871                                         ep->frm_overrun = 1;
3872                                         ep->frame_num &= 0x3FFF;
3873                                 } else
3874                                         ep->frm_overrun = 0;
3875                                 if (ep->frame_num & 0x1) {
3876                                         depctl.b.setd1pid = 1;
3877                                 } else {
3878                                         depctl.b.setd0pid = 1;
3879                                 }
3880                         }
3881                 }
3882                 /* EP enable, IN data in FIFO */
3883                 depctl.b.cnak = 1;
3884                 depctl.b.epena = 1;
3885                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
3886
3887         } else {
3888                 /* OUT endpoint */
3889                 dwc_otg_dev_out_ep_regs_t *out_regs =
3890                     core_if->dev_if->out_ep_regs[ep->num];
3891
3892                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
3893                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
3894
3895                 if (!core_if->dma_desc_enable) {
3896                         if (ep->maxpacket > ep->maxxfer / MAX_PKT_CNT)
3897                                 ep->xfer_len += (ep->maxxfer < (ep->total_len - ep->xfer_len)) ?
3898                                 ep->maxxfer : (ep->total_len - ep->xfer_len);
3899                 else
3900                                         ep->xfer_len += (MAX_PKT_CNT * ep->maxpacket < (ep->total_len
3901                                         - ep->xfer_len)) ? MAX_PKT_CNT * ep->maxpacket : (ep->total_len - ep->xfer_len);
3902                 }
3903
3904                 /* Program the transfer size and packet count as follows:
3905                  *
3906                  *      pktcnt = N
3907                  *      xfersize = N * maxpacket
3908                  */
3909                 if ((ep->xfer_len - ep->xfer_count) == 0) {
3910                         /* Zero Length Packet */
3911                         deptsiz.b.xfersize = ep->maxpacket;
3912                         deptsiz.b.pktcnt = 1;
3913                 } else {
3914                         deptsiz.b.pktcnt =
3915                             (ep->xfer_len - ep->xfer_count +
3916                              (ep->maxpacket - 1)) / ep->maxpacket;
3917                         if (deptsiz.b.pktcnt > MAX_PKT_CNT) {
3918                                 deptsiz.b.pktcnt = MAX_PKT_CNT;
3919                         }
3920                         if (!core_if->dma_desc_enable) {
3921                                 ep->xfer_len =
3922                                         deptsiz.b.pktcnt * ep->maxpacket + ep->xfer_count;
3923                         }
3924                         deptsiz.b.xfersize = ep->xfer_len - ep->xfer_count;
3925                 }
3926
3927                 DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n",
3928                             ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt);
3929
3930                 if (core_if->dma_enable) {
3931                         if (!core_if->dma_desc_enable) {
3932                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
3933                                                 deptsiz.d32);
3934
3935                                 DWC_WRITE_REG32(&(out_regs->doepdma),
3936                                                 (uint32_t) ep->dma_addr);
3937                         } else {
3938 #ifdef DWC_UTE_CFI
3939                                 /* The descriptor chain should be already initialized by now */
3940                                 if (ep->buff_mode != BM_STANDARD) {
3941                                         DWC_WRITE_REG32(&out_regs->doepdma,
3942                                                         ep->descs_dma_addr);
3943                                 } else {
3944 #endif
3945                                         /** This is used for interrupt out transfers*/
3946                                         if (!ep->xfer_len)
3947                                                 ep->xfer_len = ep->total_len;
3948                                         init_dma_desc_chain(core_if, ep);
3949
3950                                         if (core_if->core_params->dev_out_nak) {
3951                                                 if (ep->type == DWC_OTG_EP_TYPE_BULK) {
3952                                                         deptsiz.b.pktcnt = (ep->total_len +
3953                                                                 (ep->maxpacket - 1)) / ep->maxpacket;
3954                                                         deptsiz.b.xfersize = ep->total_len;
3955                                                         /* Remember initial value of doeptsiz */
3956                                                         core_if->start_doeptsiz_val[ep->num] = deptsiz.d32;
3957                                                         DWC_WRITE_REG32(&out_regs->doeptsiz,
3958                                                                 deptsiz.d32);
3959                                                 }
3960                                         }
3961                                 /** DOEPDMAn Register write */
3962                                         DWC_WRITE_REG32(&out_regs->doepdma,
3963                                                         ep->dma_desc_addr);
3964 #ifdef DWC_UTE_CFI
3965                                 }
3966 #endif
3967                         }
3968                 } else {
3969                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
3970                 }
3971
3972                 if (ep->type == DWC_OTG_EP_TYPE_ISOC) {
3973                         dsts_data_t dsts = {.d32 = 0 };
3974                         if (ep->bInterval == 1) {
3975                                 dsts.d32 =
3976                                     DWC_READ_REG32(&core_if->dev_if->
3977                                                    dev_global_regs->dsts);
3978                                 ep->frame_num = dsts.b.soffn + ep->bInterval;
3979                                 if (ep->frame_num > 0x3FFF) {
3980                                         ep->frm_overrun = 1;
3981                                         ep->frame_num &= 0x3FFF;
3982                                 } else
3983                                         ep->frm_overrun = 0;
3984
3985                                 if (ep->frame_num & 0x1) {
3986                                         depctl.b.setd1pid = 1;
3987                                 } else {
3988                                         depctl.b.setd0pid = 1;
3989                                 }
3990                         }
3991                 }
3992
3993                 /* EP enable */
3994                 depctl.b.cnak = 1;
3995                 depctl.b.epena = 1;
3996
3997                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
3998
3999                 DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n",
4000                             DWC_READ_REG32(&out_regs->doepctl),
4001                             DWC_READ_REG32(&out_regs->doeptsiz));
4002                 DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n",
4003                             DWC_READ_REG32(&core_if->dev_if->dev_global_regs->
4004                                            daintmsk),
4005                             DWC_READ_REG32(&core_if->core_global_regs->
4006                                            gintmsk));
4007
4008                 /* Timer is scheduling only for out bulk transfers for
4009                  * "Device DDMA OUT NAK Enhancement" feature to inform user
4010                  * about received data payload in case of timeout
4011                  */
4012                 if (core_if->core_params->dev_out_nak) {
4013                         if (ep->type == DWC_OTG_EP_TYPE_BULK) {
4014                                 core_if->ep_xfer_info[ep->num].core_if = core_if;
4015                                 core_if->ep_xfer_info[ep->num].ep = ep;
4016                                 core_if->ep_xfer_info[ep->num].state = 1;
4017
4018                                 /* Start a timer for this transfer. */
4019                                 DWC_TIMER_SCHEDULE(core_if->ep_xfer_timer[ep->num], 10000);
4020                         }
4021                 }
4022         }
4023 }
4024
4025 /**
4026  * This function setup a zero length transfer in Buffer DMA and
4027  * Slave modes for usb requests with zero field set
4028  *
4029  * @param core_if Programming view of DWC_otg controller.
4030  * @param ep The EP to start the transfer on.
4031  *
4032  */
4033 void dwc_otg_ep_start_zl_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4034 {
4035
4036         depctl_data_t depctl;
4037         deptsiz_data_t deptsiz;
4038         gintmsk_data_t intr_mask = {.d32 = 0 };
4039
4040         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__);
4041         DWC_PRINTF("zero length transfer is called\n");
4042
4043         /* IN endpoint */
4044         if (ep->is_in == 1) {
4045                 dwc_otg_dev_in_ep_regs_t *in_regs =
4046                     core_if->dev_if->in_ep_regs[ep->num];
4047
4048                 depctl.d32 = DWC_READ_REG32(&(in_regs->diepctl));
4049                 deptsiz.d32 = DWC_READ_REG32(&(in_regs->dieptsiz));
4050
4051                 deptsiz.b.xfersize = 0;
4052                 deptsiz.b.pktcnt = 1;
4053
4054                 /* Write the DMA register */
4055                 if (core_if->dma_enable) {
4056                         if (core_if->dma_desc_enable == 0) {
4057                                 deptsiz.b.mc = 1;
4058                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4059                                                 deptsiz.d32);
4060                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4061                                                 (uint32_t) ep->dma_addr);
4062                         }
4063                 } else {
4064                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4065                         /**
4066                          * Enable the Non-Periodic Tx FIFO empty interrupt,
4067                          * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode,
4068                          * the data will be written into the fifo by the ISR.
4069                          */
4070                         if (core_if->en_multiple_tx_fifo == 0) {
4071                                 intr_mask.b.nptxfempty = 1;
4072                                 DWC_MODIFY_REG32(&core_if->
4073                                                  core_global_regs->gintmsk,
4074                                                  intr_mask.d32, intr_mask.d32);
4075                         } else {
4076                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4077                                 if (ep->xfer_len > 0) {
4078                                         uint32_t fifoemptymsk = 0;
4079                                         fifoemptymsk = 1 << ep->num;
4080                                         DWC_MODIFY_REG32(&core_if->
4081                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4082                                                          0, fifoemptymsk);
4083                                 }
4084                         }
4085                 }
4086
4087                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4088                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4089                 /* EP enable, IN data in FIFO */
4090                 depctl.b.cnak = 1;
4091                 depctl.b.epena = 1;
4092                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4093
4094         } else {
4095                 /* OUT endpoint */
4096                 dwc_otg_dev_out_ep_regs_t *out_regs =
4097                     core_if->dev_if->out_ep_regs[ep->num];
4098
4099                 depctl.d32 = DWC_READ_REG32(&(out_regs->doepctl));
4100                 deptsiz.d32 = DWC_READ_REG32(&(out_regs->doeptsiz));
4101
4102                 /* Zero Length Packet */
4103                 deptsiz.b.xfersize = ep->maxpacket;
4104                 deptsiz.b.pktcnt = 1;
4105
4106                 if (core_if->dma_enable) {
4107                         if (!core_if->dma_desc_enable) {
4108                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4109                                                 deptsiz.d32);
4110
4111                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4112                                                 (uint32_t) ep->dma_addr);
4113                         }
4114                 } else {
4115                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4116                 }
4117
4118                 /* EP enable */
4119                 depctl.b.cnak = 1;
4120                 depctl.b.epena = 1;
4121
4122                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4123
4124         }
4125 }
4126
4127 /**
4128  * This function does the setup for a data transfer for EP0 and starts
4129  * the transfer.  For an IN transfer, the packets will be loaded into
4130  * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are
4131  * unloaded from the Rx FIFO in the ISR.
4132  *
4133  * @param core_if Programming view of DWC_otg controller.
4134  * @param ep The EP0 data.
4135  */
4136 void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4137 {
4138         depctl_data_t depctl;
4139         deptsiz0_data_t deptsiz;
4140         gintmsk_data_t intr_mask = {.d32 = 0 };
4141         dwc_otg_dev_dma_desc_t *dma_desc;
4142
4143         DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d "
4144                     "xfer_buff=%p start_xfer_buff=%p \n",
4145                     ep->num, (ep->is_in ? "IN" : "OUT"), ep->xfer_len,
4146                     ep->xfer_count, ep->xfer_buff, ep->start_xfer_buff);
4147
4148         ep->total_len = ep->xfer_len;
4149
4150         /* IN endpoint */
4151         if (ep->is_in == 1) {
4152                 dwc_otg_dev_in_ep_regs_t *in_regs =
4153                     core_if->dev_if->in_ep_regs[0];
4154
4155                 gnptxsts_data_t gtxstatus;
4156
4157                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4158                         depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4159                         if (depctl.b.epena)
4160                                 return;
4161                 }
4162
4163                 gtxstatus.d32 =
4164                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4165
4166                 /* If dedicated FIFO every time flush fifo before enable ep*/
4167                 if (core_if->en_multiple_tx_fifo && core_if->snpsid >= OTG_CORE_REV_3_00a)
4168                         dwc_otg_flush_tx_fifo(core_if, ep->tx_fifo_num);
4169
4170                 if (core_if->en_multiple_tx_fifo == 0
4171                     && gtxstatus.b.nptxqspcavail == 0
4172                     && !core_if->dma_enable) {
4173 #ifdef DEBUG
4174                         deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4175                         DWC_DEBUGPL(DBG_PCD, "DIEPCTL0=%0x\n",
4176                                     DWC_READ_REG32(&in_regs->diepctl));
4177                         DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n",
4178                                     deptsiz.d32,
4179                                     deptsiz.b.xfersize, deptsiz.b.pktcnt);
4180                         DWC_PRINTF("TX Queue or FIFO Full (0x%0x)\n",
4181                                    gtxstatus.d32);
4182 #endif
4183                         return;
4184                 }
4185
4186                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4187                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4188
4189                 /* Zero Length Packet? */
4190                 if (ep->xfer_len == 0) {
4191                         deptsiz.b.xfersize = 0;
4192                         deptsiz.b.pktcnt = 1;
4193                 } else {
4194                         /* Program the transfer size and packet count
4195                          *      as follows: xfersize = N * maxpacket +
4196                          *      short_packet pktcnt = N + (short_packet
4197                          *      exist ? 1 : 0)
4198                          */
4199                         if (ep->xfer_len > ep->maxpacket) {
4200                                 ep->xfer_len = ep->maxpacket;
4201                                 deptsiz.b.xfersize = ep->maxpacket;
4202                         } else {
4203                                 deptsiz.b.xfersize = ep->xfer_len;
4204                         }
4205                         deptsiz.b.pktcnt = 1;
4206
4207                 }
4208                 DWC_DEBUGPL(DBG_PCDV,
4209                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4210                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4211                             deptsiz.d32);
4212
4213                 /* Write the DMA register */
4214                 if (core_if->dma_enable) {
4215                         if (core_if->dma_desc_enable == 0) {
4216                                 DWC_WRITE_REG32(&in_regs->dieptsiz,
4217                                                 deptsiz.d32);
4218
4219                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4220                                                 (uint32_t) ep->dma_addr);
4221                         } else {
4222                                 dma_desc = core_if->dev_if->in_desc_addr;
4223
4224                                 /** DMA Descriptor Setup */
4225                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4226                                 dma_desc->status.b.l = 1;
4227                                 dma_desc->status.b.ioc = 1;
4228                                 dma_desc->status.b.sp =
4229                                     (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4230                                 dma_desc->status.b.bytes = ep->xfer_len;
4231                                 dma_desc->buf = ep->dma_addr;
4232                                 dma_desc->status.b.sts = 0;
4233                                 dma_desc->status.b.bs = BS_HOST_READY;
4234
4235                                 /** DIEPDMA0 Register write */
4236                                 DWC_WRITE_REG32(&in_regs->diepdma,
4237                                                 core_if->
4238                                                 dev_if->dma_in_desc_addr);
4239                         }
4240                 } else {
4241                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4242                 }
4243
4244                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4245                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4246                 /* EP enable, IN data in FIFO */
4247                 depctl.b.cnak = 1;
4248                 depctl.b.epena = 1;
4249                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4250
4251                 /**
4252                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4253                  * data will be written into the fifo by the ISR.
4254                  */
4255                 if (!core_if->dma_enable) {
4256                         if (core_if->en_multiple_tx_fifo == 0) {
4257                                 intr_mask.b.nptxfempty = 1;
4258                                 DWC_MODIFY_REG32(&core_if->
4259                                                  core_global_regs->gintmsk,
4260                                                  intr_mask.d32, intr_mask.d32);
4261                         } else {
4262                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4263                                 if (ep->xfer_len > 0) {
4264                                         uint32_t fifoemptymsk = 0;
4265                                         fifoemptymsk |= 1 << ep->num;
4266                                         DWC_MODIFY_REG32(&core_if->
4267                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4268                                                          0, fifoemptymsk);
4269                                 }
4270                         }
4271                 }
4272         } else {
4273                 /* OUT endpoint */
4274                 dwc_otg_dev_out_ep_regs_t *out_regs =
4275                     core_if->dev_if->out_ep_regs[0];
4276
4277                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4278                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4279
4280                 /* Program the transfer size and packet count as follows:
4281                  *      xfersize = N * (maxpacket + 4 - (maxpacket % 4))
4282                  *      pktcnt = N                                                                                      */
4283                 /* Zero Length Packet */
4284                 deptsiz.b.xfersize = ep->maxpacket;
4285                 deptsiz.b.pktcnt = 1;
4286                 if (core_if->snpsid >= OTG_CORE_REV_3_00a)
4287                         deptsiz.b.supcnt = 3;
4288
4289                 DWC_DEBUGPL(DBG_PCDV, "len=%d  xfersize=%d pktcnt=%d\n",
4290                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt);
4291
4292                 if (core_if->dma_enable) {
4293                         if (!core_if->dma_desc_enable) {
4294                                 DWC_WRITE_REG32(&out_regs->doeptsiz,
4295                                                 deptsiz.d32);
4296
4297                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4298                                                 (uint32_t) ep->dma_addr);
4299                         } else {
4300                                 dma_desc = core_if->dev_if->out_desc_addr;
4301
4302                                 /** DMA Descriptor Setup */
4303                                 dma_desc->status.b.bs = BS_HOST_BUSY;
4304                                 if (core_if->snpsid >= OTG_CORE_REV_3_00a) {
4305                                         dma_desc->status.b.mtrf = 0;
4306                                         dma_desc->status.b.sr = 0;
4307                                 }
4308                                 dma_desc->status.b.l = 1;
4309                                 dma_desc->status.b.ioc = 1;
4310                                 dma_desc->status.b.bytes = ep->maxpacket;
4311                                 dma_desc->buf = ep->dma_addr;
4312                                 dma_desc->status.b.sts = 0;
4313                                 dma_desc->status.b.bs = BS_HOST_READY;
4314
4315                                 /** DOEPDMA0 Register write */
4316                                 DWC_WRITE_REG32(&out_regs->doepdma,
4317                                                 core_if->dev_if->
4318                                                 dma_out_desc_addr);
4319                         }
4320                 } else {
4321                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4322                 }
4323
4324                 /* EP enable */
4325                 depctl.b.cnak = 1;
4326                 depctl.b.epena = 1;
4327                 DWC_WRITE_REG32(&(out_regs->doepctl), depctl.d32);
4328         }
4329 }
4330
4331 /**
4332  * This function continues control IN transfers started by
4333  * dwc_otg_ep0_start_transfer, when the transfer does not fit in a
4334  * single packet.  NOTE: The DIEPCTL0/DOEPCTL0 registers only have one
4335  * bit for the packet count.
4336  *
4337  * @param core_if Programming view of DWC_otg controller.
4338  * @param ep The EP0 data.
4339  */
4340 void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4341 {
4342         depctl_data_t depctl;
4343         deptsiz0_data_t deptsiz;
4344         gintmsk_data_t intr_mask = {.d32 = 0 };
4345         dwc_otg_dev_dma_desc_t *dma_desc;
4346
4347         if (ep->is_in == 1) {
4348                 dwc_otg_dev_in_ep_regs_t *in_regs =
4349                     core_if->dev_if->in_ep_regs[0];
4350                 gnptxsts_data_t tx_status = {.d32 = 0 };
4351
4352                 tx_status.d32 =
4353                     DWC_READ_REG32(&core_if->core_global_regs->gnptxsts);
4354                 /** @todo Should there be check for room in the Tx
4355                  * Status Queue.  If not remove the code above this comment. */
4356
4357                 depctl.d32 = DWC_READ_REG32(&in_regs->diepctl);
4358                 deptsiz.d32 = DWC_READ_REG32(&in_regs->dieptsiz);
4359
4360                 /* Program the transfer size and packet count
4361                  *      as follows: xfersize = N * maxpacket +
4362                  *      short_packet pktcnt = N + (short_packet
4363                  *      exist ? 1 : 0)
4364                  */
4365
4366                 if (core_if->dma_desc_enable == 0) {
4367                         deptsiz.b.xfersize =
4368                             (ep->total_len - ep->xfer_count) >
4369                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4370                                                              ep->xfer_count);
4371                         deptsiz.b.pktcnt = 1;
4372                         if (core_if->dma_enable == 0) {
4373                                 ep->xfer_len += deptsiz.b.xfersize;
4374                         } else {
4375                                 ep->xfer_len = deptsiz.b.xfersize;
4376                         }
4377                         DWC_WRITE_REG32(&in_regs->dieptsiz, deptsiz.d32);
4378                 } else {
4379                         ep->xfer_len =
4380                             (ep->total_len - ep->xfer_count) >
4381                             ep->maxpacket ? ep->maxpacket : (ep->total_len -
4382                                                              ep->xfer_count);
4383
4384                         dma_desc = core_if->dev_if->in_desc_addr;
4385
4386                         /** DMA Descriptor Setup */
4387                         dma_desc->status.b.bs = BS_HOST_BUSY;
4388                         dma_desc->status.b.l = 1;
4389                         dma_desc->status.b.ioc = 1;
4390                         dma_desc->status.b.sp =
4391                             (ep->xfer_len == ep->maxpacket) ? 0 : 1;
4392                         dma_desc->status.b.bytes = ep->xfer_len;
4393                         dma_desc->buf = ep->dma_addr;
4394                         dma_desc->status.b.sts = 0;
4395                         dma_desc->status.b.bs = BS_HOST_READY;
4396
4397                         /** DIEPDMA0 Register write */
4398                         DWC_WRITE_REG32(&in_regs->diepdma,
4399                                         core_if->dev_if->dma_in_desc_addr);
4400                 }
4401
4402                 DWC_DEBUGPL(DBG_PCDV,
4403                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4404                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4405                             deptsiz.d32);
4406
4407                 /* Write the DMA register */
4408                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4409                         if (core_if->dma_desc_enable == 0)
4410                                 DWC_WRITE_REG32(&(in_regs->diepdma),
4411                                                 (uint32_t) ep->dma_addr);
4412                 }
4413                 if (!core_if->core_params->en_multiple_tx_fifo && core_if->dma_enable)
4414                         depctl.b.nextep = core_if->nextep_seq[ep->num];
4415                 /* EP enable, IN data in FIFO */
4416                 depctl.b.cnak = 1;
4417                 depctl.b.epena = 1;
4418                 DWC_WRITE_REG32(&in_regs->diepctl, depctl.d32);
4419
4420                 /**
4421                  * Enable the Non-Periodic Tx FIFO empty interrupt, the
4422                  * data will be written into the fifo by the ISR.
4423                  */
4424                 if (!core_if->dma_enable) {
4425                         if (core_if->en_multiple_tx_fifo == 0) {
4426                                 /* First clear it from GINTSTS */
4427                                 intr_mask.b.nptxfempty = 1;
4428                                 DWC_MODIFY_REG32(&core_if->
4429                                                  core_global_regs->gintmsk,
4430                                                  intr_mask.d32, intr_mask.d32);
4431
4432                         } else {
4433                                 /* Enable the Tx FIFO Empty Interrupt for this EP */
4434                                 if (ep->xfer_len > 0) {
4435                                         uint32_t fifoemptymsk = 0;
4436                                         fifoemptymsk |= 1 << ep->num;
4437                                         DWC_MODIFY_REG32(&core_if->
4438                                                          dev_if->dev_global_regs->dtknqr4_fifoemptymsk,
4439                                                          0, fifoemptymsk);
4440                                 }
4441                         }
4442                 }
4443         } else {
4444                 dwc_otg_dev_out_ep_regs_t *out_regs =
4445                     core_if->dev_if->out_ep_regs[0];
4446
4447                 depctl.d32 = DWC_READ_REG32(&out_regs->doepctl);
4448                 deptsiz.d32 = DWC_READ_REG32(&out_regs->doeptsiz);
4449
4450                 /* Program the transfer size and packet count
4451                  *      as follows: xfersize = N * maxpacket +
4452                  *      short_packet pktcnt = N + (short_packet
4453                  *      exist ? 1 : 0)
4454                  */
4455                 deptsiz.b.xfersize = ep->maxpacket;
4456                 deptsiz.b.pktcnt = 1;
4457
4458                 if (core_if->dma_desc_enable == 0) {
4459                         DWC_WRITE_REG32(&out_regs->doeptsiz, deptsiz.d32);
4460                 } else {
4461                         dma_desc = core_if->dev_if->out_desc_addr;
4462
4463                         /** DMA Descriptor Setup */
4464                         dma_desc->status.b.bs = BS_HOST_BUSY;
4465                         dma_desc->status.b.l = 1;
4466                         dma_desc->status.b.ioc = 1;
4467                         dma_desc->status.b.bytes = ep->maxpacket;
4468                         dma_desc->buf = ep->dma_addr;
4469                         dma_desc->status.b.sts = 0;
4470                         dma_desc->status.b.bs = BS_HOST_READY;
4471
4472                         /** DOEPDMA0 Register write */
4473                         DWC_WRITE_REG32(&out_regs->doepdma,
4474                                         core_if->dev_if->dma_out_desc_addr);
4475                 }
4476
4477                 DWC_DEBUGPL(DBG_PCDV,
4478                             "IN len=%d  xfersize=%d pktcnt=%d [%08x]\n",
4479                             ep->xfer_len, deptsiz.b.xfersize, deptsiz.b.pktcnt,
4480                             deptsiz.d32);
4481
4482                 /* Write the DMA register */
4483                 if (core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) {
4484                         if (core_if->dma_desc_enable == 0)
4485                                 DWC_WRITE_REG32(&(out_regs->doepdma),
4486                                                 (uint32_t) ep->dma_addr);
4487
4488                 }
4489
4490                 /* EP enable, IN data in FIFO */
4491                 depctl.b.cnak = 1;
4492                 depctl.b.epena = 1;
4493                 DWC_WRITE_REG32(&out_regs->doepctl, depctl.d32);
4494
4495         }
4496 }
4497
4498 #ifdef DEBUG
4499 void dump_msg(const u8 * buf, unsigned int length)
4500 {
4501         unsigned int start, num, i;
4502         char line[52], *p;
4503
4504         if (length >= 512)
4505                 return;
4506         start = 0;
4507         while (length > 0) {
4508                 num = length < 16u ? length : 16u;
4509                 p = line;
4510                 for (i = 0; i < num; ++i) {
4511                         if (i == 8)
4512                                 *p++ = ' ';
4513                         DWC_SPRINTF(p, " %02x", buf[i]);
4514                         p += 3;
4515                 }
4516                 *p = 0;
4517                 DWC_PRINTF("%6x: %s\n", start, line);
4518                 buf += num;
4519                 start += num;
4520                 length -= num;
4521         }
4522 }
4523 #else
4524 static inline void dump_msg(const u8 * buf, unsigned int length)
4525 {
4526 }
4527 #endif
4528
4529 /**
4530  * This function writes a packet into the Tx FIFO associated with the
4531  * EP. For non-periodic EPs the non-periodic Tx FIFO is written.  For
4532  * periodic EPs the periodic Tx FIFO associated with the EP is written
4533  * with all packets for the next micro-frame.
4534  *
4535  * @param core_if Programming view of DWC_otg controller.
4536  * @param ep The EP to write packet for.
4537  * @param dma Indicates if DMA is being used.
4538  */
4539 void dwc_otg_ep_write_packet(dwc_otg_core_if_t * core_if, dwc_ep_t * ep,
4540                              int dma)
4541 {
4542         /**
4543          * The buffer is padded to DWORD on a per packet basis in
4544          * slave/dma mode if the MPS is not DWORD aligned. The last
4545          * packet, if short, is also padded to a multiple of DWORD.
4546          *
4547          * ep->xfer_buff always starts DWORD aligned in memory and is a
4548          * multiple of DWORD in length
4549          *
4550          * ep->xfer_len can be any number of bytes
4551          *
4552          * ep->xfer_count is a multiple of ep->maxpacket until the last
4553          *      packet
4554          *
4555          * FIFO access is DWORD */
4556
4557         uint32_t i;
4558         uint32_t byte_count;
4559         uint32_t dword_count;
4560         uint32_t *fifo;
4561         uint32_t *data_buff = (uint32_t *) ep->xfer_buff;
4562
4563         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, core_if,
4564                     ep);
4565         if (ep->xfer_count >= ep->xfer_len) {
4566                 DWC_WARN("%s() No data for EP%d!!!\n", __func__, ep->num);
4567                 return;
4568         }
4569
4570         /* Find the byte length of the packet either short packet or MPS */
4571         if ((ep->xfer_len - ep->xfer_count) < ep->maxpacket) {
4572                 byte_count = ep->xfer_len - ep->xfer_count;
4573         } else {
4574                 byte_count = ep->maxpacket;
4575         }
4576
4577         /* Find the DWORD length, padded by extra bytes as neccessary if MPS
4578          * is not a multiple of DWORD */
4579         dword_count = (byte_count + 3) / 4;
4580
4581 #ifdef VERBOSE
4582         dump_msg(ep->xfer_buff, byte_count);
4583 #endif
4584
4585         /**@todo NGS Where are the Periodic Tx FIFO addresses
4586          * intialized?  What should this be? */
4587
4588         fifo = core_if->data_fifo[ep->num];
4589
4590         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n",
4591                     fifo, data_buff, *data_buff, byte_count);
4592
4593         if (!dma) {
4594                 for (i = 0; i < dword_count; i++, data_buff++) {
4595                         DWC_WRITE_REG32(fifo, *data_buff);
4596                 }
4597         }
4598
4599         ep->xfer_count += byte_count;
4600         ep->xfer_buff += byte_count;
4601         ep->dma_addr += byte_count;
4602 }
4603
4604 /**
4605  * Set the EP STALL.
4606  *
4607  * @param core_if Programming view of DWC_otg controller.
4608  * @param ep The EP to set the stall on.
4609  */
4610 void dwc_otg_ep_set_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4611 {
4612         depctl_data_t depctl;
4613         volatile uint32_t *depctl_addr;
4614
4615         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4616                     (ep->is_in ? "IN" : "OUT"));
4617
4618         if (ep->is_in == 1) {
4619                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4620                 depctl.d32 = DWC_READ_REG32(depctl_addr);
4621
4622                 /* set the disable and stall bits */
4623                 if (depctl.b.epena) {
4624                         depctl.b.epdis = 1;
4625                 }
4626                 depctl.b.stall = 1;
4627                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
4628         } else {
4629                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4630                 depctl.d32 = DWC_READ_REG32(depctl_addr);
4631
4632                 /* set the stall bit */
4633                 depctl.b.stall = 1;
4634                 DWC_WRITE_REG32(depctl_addr, depctl.d32);
4635         }
4636
4637         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
4638
4639         return;
4640 }
4641
4642 /**
4643  * Clear the EP STALL.
4644  *
4645  * @param core_if Programming view of DWC_otg controller.
4646  * @param ep The EP to clear stall from.
4647  */
4648 void dwc_otg_ep_clear_stall(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
4649 {
4650         depctl_data_t depctl;
4651         volatile uint32_t *depctl_addr;
4652
4653         DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, ep->num,
4654                     (ep->is_in ? "IN" : "OUT"));
4655
4656         if (ep->is_in == 1) {
4657                 depctl_addr = &(core_if->dev_if->in_ep_regs[ep->num]->diepctl);
4658         } else {
4659                 depctl_addr = &(core_if->dev_if->out_ep_regs[ep->num]->doepctl);
4660         }
4661
4662         depctl.d32 = DWC_READ_REG32(depctl_addr);
4663
4664         /* clear the stall bits */
4665         depctl.b.stall = 0;
4666
4667         /*
4668          * USB Spec 9.4.5: For endpoints using data toggle, regardless
4669          * of whether an endpoint has the Halt feature set, a
4670          * ClearFeature(ENDPOINT_HALT) request always results in the
4671          * data toggle being reinitialized to DATA0.
4672          */
4673         if (ep->type == DWC_OTG_EP_TYPE_INTR ||
4674             ep->type == DWC_OTG_EP_TYPE_BULK) {
4675                 depctl.b.setd0pid = 1;  /* DATA0 */
4676         }
4677
4678         DWC_WRITE_REG32(depctl_addr, depctl.d32);
4679         DWC_DEBUGPL(DBG_PCD, "DEPCTL=%0x\n", DWC_READ_REG32(depctl_addr));
4680         return;
4681 }
4682
4683 /**
4684  * This function reads a packet from the Rx FIFO into the destination
4685  * buffer. To read SETUP data use dwc_otg_read_setup_packet.
4686  *
4687  * @param core_if Programming view of DWC_otg controller.
4688  * @param dest    Destination buffer for the packet.
4689  * @param bytes  Number of bytes to copy to the destination.
4690  */
4691 void dwc_otg_read_packet(dwc_otg_core_if_t * core_if,
4692                          uint8_t * dest, uint16_t bytes)
4693 {
4694         int i;
4695         int word_count = (bytes + 3) / 4;
4696
4697         volatile uint32_t *fifo = core_if->data_fifo[0];
4698         uint32_t *data_buff = (uint32_t *) dest;
4699
4700         /**
4701          * @todo Account for the case where _dest is not dword aligned. This
4702          * requires reading data from the FIFO into a uint32_t temp buffer,
4703          * then moving it into the data buffer.
4704          */
4705
4706         DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__,
4707                     core_if, dest, bytes);
4708
4709         for (i = 0; i < word_count; i++, data_buff++) {
4710                 *data_buff = DWC_READ_REG32(fifo);
4711         }
4712
4713         return;
4714 }
4715
4716 /**
4717  * This functions reads the device registers and prints them
4718  *
4719  * @param core_if Programming view of DWC_otg controller.
4720  */
4721 void dwc_otg_dump_dev_registers(dwc_otg_core_if_t * core_if)
4722 {
4723         int i;
4724         volatile uint32_t *addr;
4725         uint32_t hwcfg1;
4726
4727         hwcfg1 = ~core_if->core_global_regs->ghwcfg1;
4728
4729         DWC_PRINTF("Device Global Registers\n");
4730         addr = &core_if->dev_if->dev_global_regs->dcfg;
4731         DWC_PRINTF("DCFG                 @0x%08lX : 0x%08X\n",
4732                    (unsigned long)addr, DWC_READ_REG32(addr));
4733         addr = &core_if->dev_if->dev_global_regs->dctl;
4734         DWC_PRINTF("DCTL                 @0x%08lX : 0x%08X\n",
4735                    (unsigned long)addr, DWC_READ_REG32(addr));
4736         addr = &core_if->dev_if->dev_global_regs->dsts;
4737         DWC_PRINTF("DSTS                 @0x%08lX : 0x%08X\n",
4738                    (unsigned long)addr, DWC_READ_REG32(addr));
4739         addr = &core_if->dev_if->dev_global_regs->diepmsk;
4740         DWC_PRINTF("DIEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4741                    DWC_READ_REG32(addr));
4742         addr = &core_if->dev_if->dev_global_regs->doepmsk;
4743         DWC_PRINTF("DOEPMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4744                    DWC_READ_REG32(addr));
4745         addr = &core_if->dev_if->dev_global_regs->daint;
4746         DWC_PRINTF("DAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
4747                    DWC_READ_REG32(addr));
4748         addr = &core_if->dev_if->dev_global_regs->daintmsk;
4749         DWC_PRINTF("DAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
4750                    DWC_READ_REG32(addr));
4751         addr = &core_if->dev_if->dev_global_regs->dtknqr1;
4752         DWC_PRINTF("DTKNQR1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4753                    DWC_READ_REG32(addr));
4754         if (core_if->hwcfg2.b.dev_token_q_depth > 6) {
4755                 addr = &core_if->dev_if->dev_global_regs->dtknqr2;
4756                 DWC_PRINTF("DTKNQR2      @0x%08lX : 0x%08X\n",
4757                            (unsigned long)addr, DWC_READ_REG32(addr));
4758         }
4759
4760         addr = &core_if->dev_if->dev_global_regs->dvbusdis;
4761         DWC_PRINTF("DVBUSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4762                    DWC_READ_REG32(addr));
4763
4764         addr = &core_if->dev_if->dev_global_regs->dvbuspulse;
4765         DWC_PRINTF("DVBUSPULSE  @0x%08lX : 0x%08X\n",
4766                    (unsigned long)addr, DWC_READ_REG32(addr));
4767
4768         addr = &core_if->dev_if->dev_global_regs->dtknqr3_dthrctl;
4769         DWC_PRINTF("DTKNQR3_DTHRCTL      @0x%08lX : 0x%08X\n",
4770                    (unsigned long)addr, DWC_READ_REG32(addr));
4771
4772         if (core_if->hwcfg2.b.dev_token_q_depth > 22) {
4773                 addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4774                 DWC_PRINTF("DTKNQR4      @0x%08lX : 0x%08X\n",
4775                            (unsigned long)addr, DWC_READ_REG32(addr));
4776         }
4777
4778         addr = &core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk;
4779         DWC_PRINTF("FIFOEMPMSK   @0x%08lX : 0x%08X\n", (unsigned long)addr,
4780                    DWC_READ_REG32(addr));
4781
4782         if (core_if->hwcfg2.b.multi_proc_int) {
4783
4784                 addr = &core_if->dev_if->dev_global_regs->deachint;
4785                 DWC_PRINTF("DEACHINT     @0x%08lX : 0x%08X\n",
4786                            (unsigned long)addr, DWC_READ_REG32(addr));
4787                 addr = &core_if->dev_if->dev_global_regs->deachintmsk;
4788                 DWC_PRINTF("DEACHINTMSK  @0x%08lX : 0x%08X\n",
4789                            (unsigned long)addr, DWC_READ_REG32(addr));
4790
4791                 for (i = 0; i <= core_if->dev_if->num_in_eps; i++) {
4792                         addr =
4793                             &core_if->dev_if->
4794                             dev_global_regs->diepeachintmsk[i];
4795                         DWC_PRINTF("DIEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
4796                                    i, (unsigned long)addr,
4797                                    DWC_READ_REG32(addr));
4798                 }
4799
4800                 for (i = 0; i <= core_if->dev_if->num_out_eps; i++) {
4801                         addr =
4802                             &core_if->dev_if->
4803                             dev_global_regs->doepeachintmsk[i];
4804                         DWC_PRINTF("DOEPEACHINTMSK[%d]   @0x%08lX : 0x%08X\n",
4805                                    i, (unsigned long)addr,
4806                                    DWC_READ_REG32(addr));
4807                 }
4808         }
4809
4810         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
4811                 if(hwcfg1 & (2<<(i<<1))){
4812                         DWC_PRINTF("Device IN EP %d Registers\n", i);
4813                         addr = &core_if->dev_if->in_ep_regs[i]->diepctl;
4814                         DWC_PRINTF("DIEPCTL      @0x%08lX : 0x%08X\n",
4815                                    (unsigned long)addr, DWC_READ_REG32(addr));
4816                         addr = &core_if->dev_if->in_ep_regs[i]->diepint;
4817                         DWC_PRINTF("DIEPINT      @0x%08lX : 0x%08X\n",
4818                                    (unsigned long)addr, DWC_READ_REG32(addr));
4819                         addr = &core_if->dev_if->in_ep_regs[i]->dieptsiz;
4820                         DWC_PRINTF("DIETSIZ      @0x%08lX : 0x%08X\n",
4821                                    (unsigned long)addr, DWC_READ_REG32(addr));
4822                         addr = &core_if->dev_if->in_ep_regs[i]->diepdma;
4823                         DWC_PRINTF("DIEPDMA      @0x%08lX : 0x%08X\n",
4824                                    (unsigned long)addr, DWC_READ_REG32(addr));
4825                         addr = &core_if->dev_if->in_ep_regs[i]->dtxfsts;
4826                         DWC_PRINTF("DTXFSTS      @0x%08lX : 0x%08X\n",
4827                                    (unsigned long)addr, DWC_READ_REG32(addr));
4828                         addr = &core_if->dev_if->in_ep_regs[i]->diepdmab;
4829                         DWC_PRINTF("DIEPDMAB     @0x%08lX : 0x%08X\n",
4830                                    (unsigned long)addr, 0 /*DWC_READ_REG32(addr) */ );
4831                 }
4832         }
4833
4834         for (i = 0; i <= core_if->core_params->dev_endpoints; i++) {
4835                 if(hwcfg1 & (1<<(i<<1))){
4836                         DWC_PRINTF("Device OUT EP %d Registers\n", i);
4837                         addr = &core_if->dev_if->out_ep_regs[i]->doepctl;
4838                         DWC_PRINTF("DOEPCTL      @0x%08lX : 0x%08X\n",
4839                                    (unsigned long)addr, DWC_READ_REG32(addr));
4840                         addr = &core_if->dev_if->out_ep_regs[i]->doepint;
4841                         DWC_PRINTF("DOEPINT      @0x%08lX : 0x%08X\n",
4842                                    (unsigned long)addr, DWC_READ_REG32(addr));
4843                         addr = &core_if->dev_if->out_ep_regs[i]->doeptsiz;
4844                         DWC_PRINTF("DOETSIZ      @0x%08lX : 0x%08X\n",
4845                                    (unsigned long)addr, DWC_READ_REG32(addr));
4846                         addr = &core_if->dev_if->out_ep_regs[i]->doepdma;
4847                         DWC_PRINTF("DOEPDMA      @0x%08lX : 0x%08X\n",
4848                                    (unsigned long)addr, DWC_READ_REG32(addr));
4849                         if (core_if->dma_enable) {      /* Don't access this register in SLAVE mode */
4850                                 addr = &core_if->dev_if->out_ep_regs[i]->doepdmab;
4851                                 DWC_PRINTF("DOEPDMAB     @0x%08lX : 0x%08X\n",
4852                                            (unsigned long)addr, DWC_READ_REG32(addr));
4853                         }
4854                 }
4855
4856         }
4857 }
4858
4859 /**
4860  * This functions reads the SPRAM and prints its content
4861  *
4862  * @param core_if Programming view of DWC_otg controller.
4863  */
4864 void dwc_otg_dump_spram(dwc_otg_core_if_t * core_if)
4865 {
4866         volatile uint8_t *addr, *start_addr, *end_addr;
4867
4868         DWC_PRINTF("SPRAM Data:\n");
4869         start_addr = (void *)core_if->core_global_regs;
4870         DWC_PRINTF("Base Address: 0x%8lX\n", (unsigned long)start_addr);
4871         start_addr += 0x00028000;
4872         end_addr = (void *)core_if->core_global_regs;
4873         end_addr += 0x000280e0;
4874
4875         for (addr = start_addr; addr < end_addr; addr += 16) {
4876                 DWC_PRINTF
4877                     ("0x%8lX:\t%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",
4878                      (unsigned long)addr, addr[0], addr[1], addr[2], addr[3],
4879                      addr[4], addr[5], addr[6], addr[7], addr[8], addr[9],
4880                      addr[10], addr[11], addr[12], addr[13], addr[14], addr[15]
4881                     );
4882         }
4883
4884         return;
4885 }
4886
4887 /**
4888  * This function reads the host registers and prints them
4889  *
4890  * @param core_if Programming view of DWC_otg controller.
4891  */
4892 void dwc_otg_dump_host_registers(dwc_otg_core_if_t * core_if)
4893 {
4894         int i;
4895         volatile uint32_t *addr;
4896
4897         DWC_PRINTF("Host Global Registers\n");
4898         addr = &core_if->host_if->host_global_regs->hcfg;
4899         DWC_PRINTF("HCFG                 @0x%08lX : 0x%08X\n",
4900                    (unsigned long)addr, DWC_READ_REG32(addr));
4901         addr = &core_if->host_if->host_global_regs->hfir;
4902         DWC_PRINTF("HFIR                 @0x%08lX : 0x%08X\n",
4903                    (unsigned long)addr, DWC_READ_REG32(addr));
4904         addr = &core_if->host_if->host_global_regs->hfnum;
4905         DWC_PRINTF("HFNUM        @0x%08lX : 0x%08X\n", (unsigned long)addr,
4906                    DWC_READ_REG32(addr));
4907         addr = &core_if->host_if->host_global_regs->hptxsts;
4908         DWC_PRINTF("HPTXSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4909                    DWC_READ_REG32(addr));
4910         addr = &core_if->host_if->host_global_regs->haint;
4911         DWC_PRINTF("HAINT        @0x%08lX : 0x%08X\n", (unsigned long)addr,
4912                    DWC_READ_REG32(addr));
4913         addr = &core_if->host_if->host_global_regs->haintmsk;
4914         DWC_PRINTF("HAINTMSK     @0x%08lX : 0x%08X\n", (unsigned long)addr,
4915                    DWC_READ_REG32(addr));
4916         if (core_if->dma_desc_enable) {
4917                 addr = &core_if->host_if->host_global_regs->hflbaddr;
4918                 DWC_PRINTF("HFLBADDR     @0x%08lX : 0x%08X\n",
4919                            (unsigned long)addr, DWC_READ_REG32(addr));
4920         }
4921
4922         addr = core_if->host_if->hprt0;
4923         DWC_PRINTF("HPRT0        @0x%08lX : 0x%08X\n", (unsigned long)addr,
4924                    DWC_READ_REG32(addr));
4925
4926         for (i = 0; i < core_if->core_params->host_channels; i++) {
4927                 DWC_PRINTF("Host Channel %d Specific Registers\n", i);
4928                 addr = &core_if->host_if->hc_regs[i]->hcchar;
4929                 DWC_PRINTF("HCCHAR       @0x%08lX : 0x%08X\n",
4930                            (unsigned long)addr, DWC_READ_REG32(addr));
4931                 addr = &core_if->host_if->hc_regs[i]->hcsplt;
4932                 DWC_PRINTF("HCSPLT       @0x%08lX : 0x%08X\n",
4933                            (unsigned long)addr, DWC_READ_REG32(addr));
4934                 addr = &core_if->host_if->hc_regs[i]->hcint;
4935                 DWC_PRINTF("HCINT        @0x%08lX : 0x%08X\n",
4936                            (unsigned long)addr, DWC_READ_REG32(addr));
4937                 addr = &core_if->host_if->hc_regs[i]->hcintmsk;
4938                 DWC_PRINTF("HCINTMSK     @0x%08lX : 0x%08X\n",
4939                            (unsigned long)addr, DWC_READ_REG32(addr));
4940                 addr = &core_if->host_if->hc_regs[i]->hctsiz;
4941                 DWC_PRINTF("HCTSIZ       @0x%08lX : 0x%08X\n",
4942                            (unsigned long)addr, DWC_READ_REG32(addr));
4943                 addr = &core_if->host_if->hc_regs[i]->hcdma;
4944                 DWC_PRINTF("HCDMA        @0x%08lX : 0x%08X\n",
4945                            (unsigned long)addr, DWC_READ_REG32(addr));
4946                 if (core_if->dma_desc_enable) {
4947                         addr = &core_if->host_if->hc_regs[i]->hcdmab;
4948                         DWC_PRINTF("HCDMAB       @0x%08lX : 0x%08X\n",
4949                                    (unsigned long)addr, DWC_READ_REG32(addr));
4950                 }
4951
4952         }
4953         return;
4954 }
4955
4956 /**
4957  * This function reads the core global registers and prints them
4958  *
4959  * @param core_if Programming view of DWC_otg controller.
4960  */
4961 void dwc_otg_dump_global_registers(dwc_otg_core_if_t * core_if)
4962 {
4963         int i, ep_num;
4964         volatile uint32_t *addr;
4965         char *txfsiz;
4966
4967         DWC_PRINTF("Core Global Registers\n");
4968         addr = &core_if->core_global_regs->gotgctl;
4969         DWC_PRINTF("GOTGCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4970                    DWC_READ_REG32(addr));
4971         addr = &core_if->core_global_regs->gotgint;
4972         DWC_PRINTF("GOTGINT      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4973                    DWC_READ_REG32(addr));
4974         addr = &core_if->core_global_regs->gahbcfg;
4975         DWC_PRINTF("GAHBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4976                    DWC_READ_REG32(addr));
4977         addr = &core_if->core_global_regs->gusbcfg;
4978         DWC_PRINTF("GUSBCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4979                    DWC_READ_REG32(addr));
4980         addr = &core_if->core_global_regs->grstctl;
4981         DWC_PRINTF("GRSTCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4982                    DWC_READ_REG32(addr));
4983         addr = &core_if->core_global_regs->gintsts;
4984         DWC_PRINTF("GINTSTS      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4985                    DWC_READ_REG32(addr));
4986         addr = &core_if->core_global_regs->gintmsk;
4987         DWC_PRINTF("GINTMSK      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4988                    DWC_READ_REG32(addr));
4989         addr = &core_if->core_global_regs->grxstsr;
4990         DWC_PRINTF("GRXSTSR      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4991                    DWC_READ_REG32(addr));
4992         addr = &core_if->core_global_regs->grxfsiz;
4993         DWC_PRINTF("GRXFSIZ      @0x%08lX : 0x%08X\n", (unsigned long)addr,
4994                    DWC_READ_REG32(addr));
4995         addr = &core_if->core_global_regs->gnptxfsiz;
4996         DWC_PRINTF("GNPTXFSIZ @0x%08lX : 0x%08X\n", (unsigned long)addr,
4997                    DWC_READ_REG32(addr));
4998         addr = &core_if->core_global_regs->gnptxsts;
4999         DWC_PRINTF("GNPTXSTS     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5000                    DWC_READ_REG32(addr));
5001         addr = &core_if->core_global_regs->gi2cctl;
5002         DWC_PRINTF("GI2CCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5003                    DWC_READ_REG32(addr));
5004         addr = &core_if->core_global_regs->gpvndctl;
5005         DWC_PRINTF("GPVNDCTL     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5006                    DWC_READ_REG32(addr));
5007         addr = &core_if->core_global_regs->ggpio;
5008         DWC_PRINTF("GGPIO        @0x%08lX : 0x%08X\n", (unsigned long)addr,
5009                    DWC_READ_REG32(addr));
5010         addr = &core_if->core_global_regs->guid;
5011         DWC_PRINTF("GUID                 @0x%08lX : 0x%08X\n",
5012                    (unsigned long)addr, DWC_READ_REG32(addr));
5013         addr = &core_if->core_global_regs->gsnpsid;
5014         DWC_PRINTF("GSNPSID      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5015                    DWC_READ_REG32(addr));
5016         addr = &core_if->core_global_regs->ghwcfg1;
5017         DWC_PRINTF("GHWCFG1      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5018                    DWC_READ_REG32(addr));
5019         addr = &core_if->core_global_regs->ghwcfg2;
5020         DWC_PRINTF("GHWCFG2      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5021                    DWC_READ_REG32(addr));
5022         addr = &core_if->core_global_regs->ghwcfg3;
5023         DWC_PRINTF("GHWCFG3      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5024                    DWC_READ_REG32(addr));
5025         addr = &core_if->core_global_regs->ghwcfg4;
5026         DWC_PRINTF("GHWCFG4      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5027                    DWC_READ_REG32(addr));
5028         addr = &core_if->core_global_regs->glpmcfg;
5029         DWC_PRINTF("GLPMCFG      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5030                    DWC_READ_REG32(addr));
5031         addr = &core_if->core_global_regs->gpwrdn;
5032         DWC_PRINTF("GPWRDN       @0x%08lX : 0x%08X\n", (unsigned long)addr,
5033                    DWC_READ_REG32(addr));
5034         addr = &core_if->core_global_regs->gdfifocfg;
5035         DWC_PRINTF("GDFIFOCFG    @0x%08lX : 0x%08X\n", (unsigned long)addr,
5036                    DWC_READ_REG32(addr));
5037         addr = &core_if->core_global_regs->adpctl;
5038         DWC_PRINTF("ADPCTL       @0x%08lX : 0x%08X\n", (unsigned long)addr,
5039                    dwc_otg_adp_read_reg(core_if));
5040         addr = &core_if->core_global_regs->hptxfsiz;
5041         DWC_PRINTF("HPTXFSIZ     @0x%08lX : 0x%08X\n", (unsigned long)addr,
5042                    DWC_READ_REG32(addr));
5043
5044         if (core_if->en_multiple_tx_fifo == 0) {
5045                 ep_num = core_if->hwcfg4.b.num_dev_perio_in_ep;
5046                 txfsiz = "DPTXFSIZ";
5047         } else {
5048                 ep_num = core_if->hwcfg4.b.num_in_eps;
5049                 txfsiz = "DIENPTXF";
5050         }
5051         for (i = 0; i < ep_num; i++) {
5052                 addr = &core_if->core_global_regs->dtxfsiz[i];
5053                 DWC_PRINTF("%s[%d] @0x%08lX : 0x%08X\n", txfsiz, i + 1,
5054                            (unsigned long)addr, DWC_READ_REG32(addr));
5055         }
5056         addr = core_if->pcgcctl;
5057         DWC_PRINTF("PCGCCTL      @0x%08lX : 0x%08X\n", (unsigned long)addr,
5058                    DWC_READ_REG32(addr));
5059 }
5060
5061 /**
5062  * Flush a Tx FIFO.
5063  *
5064  * @param core_if Programming view of DWC_otg controller.
5065  * @param num Tx FIFO to flush.
5066  */
5067 void dwc_otg_flush_tx_fifo(dwc_otg_core_if_t * core_if, const int num)
5068 {
5069         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5070         volatile grstctl_t greset = {.d32 = 0 };
5071         int count = 0;
5072
5073         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "Flush Tx FIFO %d\n", num);
5074
5075         greset.b.txfflsh = 1;
5076         greset.b.txfnum = num;
5077         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5078
5079         do {
5080                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5081                 if (++count > 10000) {
5082                         DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
5083                                  __func__, greset.d32,
5084                                  DWC_READ_REG32(&global_regs->gnptxsts));
5085                         break;
5086                 }
5087                 dwc_udelay(1);
5088         } while (greset.b.txfflsh == 1);
5089
5090         /* Wait for 3 PHY Clocks */
5091         dwc_udelay(1);
5092 }
5093
5094 /**
5095  * Flush Rx FIFO.
5096  *
5097  * @param core_if Programming view of DWC_otg controller.
5098  */
5099 void dwc_otg_flush_rx_fifo(dwc_otg_core_if_t * core_if)
5100 {
5101         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5102         volatile grstctl_t greset = {.d32 = 0 };
5103         int count = 0;
5104
5105         DWC_DEBUGPL((DBG_CIL | DBG_PCDV), "%s\n", __func__);
5106         /*
5107          *
5108          */
5109         greset.b.rxfflsh = 1;
5110         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5111
5112         do {
5113                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5114                 if (++count > 10000) {
5115                         DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__,
5116                                  greset.d32);
5117                         break;
5118                 }
5119                 dwc_udelay(1);
5120         } while (greset.b.rxfflsh == 1);
5121
5122         /* Wait for 3 PHY Clocks */
5123         dwc_udelay(1);
5124 }
5125
5126 /**
5127  * Do core a soft reset of the core.  Be careful with this because it
5128  * resets all the internal state machines of the core.
5129  */
5130 void dwc_otg_core_reset(dwc_otg_core_if_t * core_if)
5131 {
5132         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
5133         volatile grstctl_t greset = {.d32 = 0 };
5134         volatile gusbcfg_data_t usbcfg = { .d32 = 0 };
5135         int count = 0;
5136
5137         DWC_DEBUGPL(DBG_CILV, "%s\n", __func__);
5138         /* Wait for AHB master IDLE state. */
5139         do {
5140                 dwc_udelay(10);
5141                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5142                 if (++count > 100000) {
5143                         DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x\n", __func__,
5144                                  greset.d32);
5145                         return;
5146                 }
5147         }
5148         while (greset.b.ahbidle == 0);
5149
5150         /* Core Soft Reset */
5151         count = 0;
5152         greset.b.csftrst = 1;
5153         DWC_WRITE_REG32(&global_regs->grstctl, greset.d32);
5154         do {
5155                 greset.d32 = DWC_READ_REG32(&global_regs->grstctl);
5156                 if (++count > 10000) {
5157                         DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n",
5158                                  __func__, greset.d32);
5159                         break;
5160                 }
5161                 dwc_udelay(1);
5162         }
5163         while (greset.b.csftrst == 1);
5164         usbcfg.d32 = DWC_READ_REG32(&global_regs->gusbcfg);
5165         if(core_if->usb_mode == USB_MODE_FORCE_HOST)
5166         {
5167                 usbcfg.b.force_host_mode = 1;
5168                 usbcfg.b.force_dev_mode = 0;
5169         } else if(core_if->usb_mode == USB_MODE_FORCE_DEVICE)
5170         {
5171                 usbcfg.b.force_host_mode = 0;
5172                 usbcfg.b.force_dev_mode = 1;
5173         } else
5174         {
5175                 usbcfg.b.force_host_mode = 0;
5176                 usbcfg.b.force_dev_mode = 0;
5177         }
5178         DWC_WRITE_REG32( &global_regs->gusbcfg, usbcfg.d32 );
5179
5180         /* Wait for 3 PHY Clocks */
5181         dwc_mdelay(100);
5182
5183 }
5184
5185 uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t * _core_if)
5186 {
5187         return (dwc_otg_mode(_core_if) != DWC_HOST_MODE);
5188 }
5189
5190 uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t * _core_if)
5191 {
5192         return (dwc_otg_mode(_core_if) == DWC_HOST_MODE);
5193 }
5194
5195 /**
5196  * Register HCD callbacks. The callbacks are used to start and stop
5197  * the HCD for interrupt processing.
5198  *
5199  * @param core_if Programming view of DWC_otg controller.
5200  * @param cb the HCD callback structure.
5201  * @param p pointer to be passed to callback function (usb_hcd*).
5202  */
5203 void dwc_otg_cil_register_hcd_callbacks(dwc_otg_core_if_t * core_if,
5204                                         dwc_otg_cil_callbacks_t * cb, void *p)
5205 {
5206         core_if->hcd_cb = cb;
5207         //cb->p = p;
5208         core_if->hcd_cb_p = p;
5209 }
5210
5211 /**
5212  * Register PCD callbacks. The callbacks are used to start and stop
5213  * the PCD for interrupt processing.
5214  *
5215  * @param core_if Programming view of DWC_otg controller.
5216  * @param cb the PCD callback structure.
5217  * @param p pointer to be passed to callback function (pcd*).
5218  */
5219 void dwc_otg_cil_register_pcd_callbacks(dwc_otg_core_if_t * core_if,
5220                                         dwc_otg_cil_callbacks_t * cb, void *p)
5221 {
5222         core_if->pcd_cb = cb;
5223         cb->p = p;
5224 }
5225
5226 #ifdef DWC_EN_ISOC
5227
5228 /**
5229  * This function writes isoc data per 1 (micro)frame into tx fifo
5230  *
5231  * @param core_if Programming view of DWC_otg controller.
5232  * @param ep The EP to start the transfer on.
5233  *
5234  */
5235 void write_isoc_frame_data(dwc_otg_core_if_t * core_if, dwc_ep_t * ep)
5236 {
5237         dwc_otg_dev_in_ep_regs_t *ep_regs;
5238         dtxfsts_data_t txstatus = {.d32 = 0 };
5239         uint32_t len = 0;
5240         uint32_t dwords;
5241
5242         ep->xfer_len = ep->data_per_frame;
5243         ep->xfer_count = 0;
5244
5245         ep_regs = core_if->dev_if->in_ep_regs[ep->num];
5246
5247         len = ep->xfer_len - ep->xfer_count;
5248
5249         if (len > ep->maxpacket) {
5250                 len = ep->maxpacket;
5251         }
5252
5253         dwords = (len + 3) / 4;
5254
5255         /* While there is space in the queue and space in the FIFO and
5256          * More data to tranfer, Write packets to the Tx FIFO */
5257         txstatus.d32 =
5258             DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dtxfsts);
5259         DWC_DEBUGPL(DBG_PCDV, "b4 dtxfsts[%d]=0x%08x\n", ep->num, txstatus.d32);
5260
5261         while (txstatus.b.txfspcavail > dwords &&
5262                ep->xfer_count < ep->xfer_len && ep->xfer_len != 0) {
5263                 /* Write the FIFO */
5264                 dwc_otg_ep_write_packet(core_if, ep, 0);
5265
5266                 len = ep->xfer_len - ep->xfer_count;
5267                 if (len > ep->maxpacket) {
5268                         len = ep->maxpacket;
5269                 }
5270
5271                 dwords = (len + 3) / 4;
5272                 txstatus.d32 =
5273                     DWC_READ_REG32(&core_if->dev_if->in_ep_regs[ep->num]->
5274                                    dtxfsts);
5275                 DWC_DEBUGPL(DBG_PCDV, "dtxfsts[%d]=0x%08x\n", ep->num,
5276                             txstatus.d32);
5277         }
5278 }
5279
5280 /**
5281  * This function initializes a descriptor chain for Isochronous transfer
5282  *
5283  * @param core_if Programming view of DWC_otg controller.
5284  * @param ep The EP to start the transfer on.
5285  *
5286  */
5287 void dwc_otg_iso_ep_start_frm_transfer(dwc_otg_core_if_t * core_if,
5288                                        dwc_ep_t * ep)
5289 {
5290         deptsiz_data_t deptsiz = {.d32 = 0 };
5291         depctl_data_t depctl = {.d32 = 0 };
5292         dsts_data_t dsts = {.d32 = 0 };
5293         volatile uint32_t *addr;
5294
5295         if (ep->is_in) {
5296                 addr = &core_if->dev_if->in_ep_regs[ep->num]->diepctl;
5297         } else {
5298                 addr = &core_if->dev_if->out_ep_regs[ep->num]->doepctl;
5299         }
5300
5301         ep->xfer_len = ep->data_per_frame;
5302         ep->xfer_count = 0;
5303         ep->xfer_buff = ep->cur_pkt_addr;
5304         ep->dma_addr = ep->cur_pkt_dma_addr;
5305
5306         if (ep->is_in) {
5307                 /* Program the transfer size and packet count
5308                  *      as follows: xfersize = N * maxpacket +
5309                  *      short_packet pktcnt = N + (short_packet
5310                  *      exist ? 1 : 0)
5311                  */
5312                 deptsiz.b.xfersize = ep->xfer_len;
5313                 deptsiz.b.pktcnt =
5314                     (ep->xfer_len - 1 + ep->maxpacket) / ep->maxpacket;
5315                 deptsiz.b.mc = deptsiz.b.pktcnt;
5316                 DWC_WRITE_REG32(&core_if->dev_if->in_ep_regs[ep->num]->dieptsiz,
5317                                 deptsiz.d32);
5318
5319                 /* Write the DMA register */
5320                 if (core_if->dma_enable) {
5321                         DWC_WRITE_REG32(&
5322                                         (core_if->dev_if->in_ep_regs[ep->num]->
5323                                          diepdma), (uint32_t) ep->dma_addr);
5324                 }
5325         } else {
5326                 deptsiz.b.pktcnt =
5327                     (ep->xfer_len + (ep->maxpacket - 1)) / ep->maxpacket;
5328                 deptsiz.b.xfersize = deptsiz.b.pktcnt * ep->maxpacket;
5329
5330                 DWC_WRITE_REG32(&core_if->dev_if->
5331                                 out_ep_regs[ep->num]->doeptsiz, deptsiz.d32);
5332
5333                 if (core_if->dma_enable) {
5334                         DWC_WRITE_REG32(&
5335                                         (core_if->dev_if->
5336                                          out_ep_regs[ep->num]->doepdma),
5337                                         (uint32_t) ep->dma_addr);
5338                 }
5339         }
5340
5341         /** Enable endpoint, clear nak  */
5342
5343         depctl.d32 = 0;
5344         if (ep->bInterval == 1) {
5345                 dsts.d32 =
5346                     DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
5347                 ep->next_frame = dsts.b.soffn + ep->bInterval;
5348
5349                 if (ep->next_frame & 0x1) {
5350                         depctl.b.setd1pid = 1;
5351                 } else {
5352                         depctl.b.setd0pid = 1;
5353                 }
5354         } else {
5355                 ep->next_frame += ep->bInterval;
5356
5357                 if (ep->next_frame & 0x1) {
5358                         depctl.b.setd1pid = 1;
5359                 } else {
5360                         depctl.b.setd0pid = 1;
5361                 }
5362         }
5363         depctl.b.epena = 1;
5364         depctl.b.cnak = 1;
5365
5366         DWC_MODIFY_REG32(addr, 0, depctl.d32);
5367         depctl.d32 = DWC_READ_REG32(addr);
5368
5369         if (ep->is_in && core_if->dma_enable == 0) {
5370                 write_isoc_frame_data(core_if, ep);
5371         }
5372
5373 }
5374 #endif /* DWC_EN_ISOC */
5375
5376 static void dwc_otg_set_uninitialized(int32_t * p, int size)
5377 {
5378         int i;
5379         for (i = 0; i < size; i++) {
5380                 p[i] = -1;
5381         }
5382 }
5383
5384 static int dwc_otg_param_initialized(int32_t val)
5385 {
5386         return val != -1;
5387 }
5388
5389 static int dwc_otg_setup_params(dwc_otg_core_if_t * core_if)
5390 {
5391         gintsts_data_t gintsts;
5392         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
5393
5394         core_if->core_params = DWC_ALLOC(sizeof(*core_if->core_params));
5395         if (!core_if->core_params) {
5396                 return -DWC_E_NO_MEMORY;
5397         }
5398         dwc_otg_set_uninitialized((int32_t *) core_if->core_params,
5399                                   sizeof(*core_if->core_params) /
5400                                   sizeof(int32_t));
5401         DWC_PRINTF("Setting default values for core params\n");
5402         dwc_otg_set_param_otg_cap(core_if, dwc_param_otg_cap_default);
5403         dwc_otg_set_param_dma_enable(core_if, dwc_param_dma_enable_default);
5404         dwc_otg_set_param_dma_desc_enable(core_if,
5405                                           dwc_param_dma_desc_enable_default);
5406         dwc_otg_set_param_opt(core_if, dwc_param_opt_default);
5407         dwc_otg_set_param_dma_burst_size(core_if,
5408                                          dwc_param_dma_burst_size_default);
5409         dwc_otg_set_param_host_support_fs_ls_low_power(core_if,
5410                                                        dwc_param_host_support_fs_ls_low_power_default);
5411         dwc_otg_set_param_enable_dynamic_fifo(core_if,
5412                                               dwc_param_enable_dynamic_fifo_default);
5413         dwc_otg_set_param_data_fifo_size(core_if,
5414                                          dwc_param_data_fifo_size_default);
5415         dwc_otg_set_param_dev_rx_fifo_size(core_if,
5416                                            dwc_param_dev_rx_fifo_size_default);
5417         dwc_otg_set_param_dev_nperio_tx_fifo_size(core_if,
5418                                                   dwc_param_dev_nperio_tx_fifo_size_default);
5419         dwc_otg_set_param_host_rx_fifo_size(core_if,
5420                                             dwc_param_host_rx_fifo_size_default);
5421         dwc_otg_set_param_host_nperio_tx_fifo_size(core_if,
5422                                                    dwc_param_host_nperio_tx_fifo_size_default);
5423         dwc_otg_set_param_host_perio_tx_fifo_size(core_if,
5424                                                   dwc_param_host_perio_tx_fifo_size_default);
5425         dwc_otg_set_param_max_transfer_size(core_if,
5426                                             dwc_param_max_transfer_size_default);
5427         dwc_otg_set_param_max_packet_count(core_if,
5428                                            dwc_param_max_packet_count_default);
5429         dwc_otg_set_param_host_channels(core_if,
5430                                         dwc_param_host_channels_default);
5431         dwc_otg_set_param_dev_endpoints(core_if,
5432                                         dwc_param_dev_endpoints_default);
5433         dwc_otg_set_param_phy_type(core_if, dwc_param_phy_type_default);
5434         dwc_otg_set_param_speed(core_if, dwc_param_speed_default);
5435         dwc_otg_set_param_host_ls_low_power_phy_clk(core_if,
5436                                                     dwc_param_host_ls_low_power_phy_clk_default);
5437         dwc_otg_set_param_phy_ulpi_ddr(core_if, dwc_param_phy_ulpi_ddr_default);
5438         dwc_otg_set_param_phy_ulpi_ext_vbus(core_if,
5439                                             dwc_param_phy_ulpi_ext_vbus_default);
5440         dwc_otg_set_param_phy_utmi_width(core_if,
5441                                          dwc_param_phy_utmi_width_default);
5442         dwc_otg_set_param_ts_dline(core_if, dwc_param_ts_dline_default);
5443         dwc_otg_set_param_i2c_enable(core_if, dwc_param_i2c_enable_default);
5444         dwc_otg_set_param_ulpi_fs_ls(core_if, dwc_param_ulpi_fs_ls_default);
5445         dwc_otg_set_param_en_multiple_tx_fifo(core_if,
5446                                               dwc_param_en_multiple_tx_fifo_default);
5447
5448         /* do not set dev_perio_tx_fifo_size and dev_tx_fifo_size here
5449          * set validate parameter values in "set_parameters" later.
5450          */
5451 #if 0
5452         if (gintsts.b.curmode) {
5453                 /* Force device mode to get power-on values of device FIFOs */
5454                 gusbcfg_data_t gusbcfg = {.d32 = 0 };
5455                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5456                 gusbcfg.b.force_dev_mode = 1;
5457                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
5458                 dwc_mdelay(100);
5459                 for (i = 0; i < 15; i++) {
5460                 dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5461                                                          dwc_param_dev_perio_tx_fifo_size_default, i);
5462                 }
5463                 for (i = 0; i < 15; i++) {
5464                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5465                                                            dwc_param_dev_tx_fifo_size_default, i);
5466                 }
5467                 gusbcfg.d32 =  DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
5468                 gusbcfg.b.force_dev_mode = 0;
5469                 DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, gusbcfg.d32);
5470                 dwc_mdelay(100);
5471         } else {
5472                 for (i = 0; i < 15; i++) {
5473                         dwc_otg_set_param_dev_perio_tx_fifo_size(core_if,
5474                                 dwc_param_dev_perio_tx_fifo_size_default, i);
5475                 }
5476                 for (i = 0; i < 15; i++) {
5477                         dwc_otg_set_param_dev_tx_fifo_size(core_if,
5478                                 dwc_param_dev_tx_fifo_size_default, i);
5479                 }
5480         }
5481 #endif
5482         dwc_otg_set_param_thr_ctl(core_if, dwc_param_thr_ctl_default);
5483         dwc_otg_set_param_mpi_enable(core_if, dwc_param_mpi_enable_default);
5484         dwc_otg_set_param_pti_enable(core_if, dwc_param_pti_enable_default);
5485         dwc_otg_set_param_lpm_enable(core_if, dwc_param_lpm_enable_default);
5486
5487         dwc_otg_set_param_besl_enable(core_if, dwc_param_besl_enable_default);
5488         dwc_otg_set_param_baseline_besl(core_if, dwc_param_baseline_besl_default);
5489         dwc_otg_set_param_deep_besl(core_if, dwc_param_deep_besl_default);
5490
5491         dwc_otg_set_param_ic_usb_cap(core_if, dwc_param_ic_usb_cap_default);
5492         dwc_otg_set_param_tx_thr_length(core_if,
5493                                         dwc_param_tx_thr_length_default);
5494         dwc_otg_set_param_rx_thr_length(core_if,
5495                                         dwc_param_rx_thr_length_default);
5496         dwc_otg_set_param_ahb_thr_ratio(core_if,
5497                                         dwc_param_ahb_thr_ratio_default);
5498         dwc_otg_set_param_power_down(core_if, dwc_param_power_down_default);
5499         dwc_otg_set_param_reload_ctl(core_if, dwc_param_reload_ctl_default);
5500         dwc_otg_set_param_dev_out_nak(core_if, dwc_param_dev_out_nak_default);
5501         dwc_otg_set_param_cont_on_bna(core_if, dwc_param_cont_on_bna_default);
5502         dwc_otg_set_param_ahb_single(core_if, dwc_param_ahb_single_default);
5503         dwc_otg_set_param_otg_ver(core_if, dwc_param_otg_ver_default);
5504         dwc_otg_set_param_adp_enable(core_if, dwc_param_adp_enable_default);
5505         return 0;
5506 }
5507
5508 uint8_t dwc_otg_is_dma_enable(dwc_otg_core_if_t * core_if)
5509 {
5510         return core_if->dma_enable;
5511 }
5512
5513 /* Checks if the parameter is outside of its valid range of values */
5514 #define DWC_OTG_PARAM_TEST(_param_, _low_, _high_) \
5515                 (((_param_) < (_low_)) || \
5516                 ((_param_) > (_high_)))
5517
5518 /* Parameter access functions */
5519 int dwc_otg_set_param_otg_cap(dwc_otg_core_if_t * core_if, int32_t val)
5520 {
5521         int valid;
5522         int retval = 0;
5523         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
5524                 DWC_WARN("Wrong value for otg_cap parameter\n");
5525                 DWC_WARN("otg_cap parameter must be 0,1 or 2\n");
5526                 retval = -DWC_E_INVALID;
5527                 goto out;
5528         }
5529
5530         valid = 1;
5531         switch (val) {
5532         case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
5533                 if (core_if->hwcfg2.b.op_mode !=
5534                     DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5535                         valid = 0;
5536                 break;
5537         case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
5538                 if ((core_if->hwcfg2.b.op_mode !=
5539                      DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5540                     && (core_if->hwcfg2.b.op_mode !=
5541                         DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5542                     && (core_if->hwcfg2.b.op_mode !=
5543                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5544                     && (core_if->hwcfg2.b.op_mode !=
5545                         DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) {
5546                         valid = 0;
5547                 }
5548                 break;
5549         case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
5550                 /* always valid */
5551                 break;
5552         }
5553         if (!valid) {
5554                 if (dwc_otg_param_initialized(core_if->core_params->otg_cap)) {
5555                         DWC_ERROR
5556                             ("%d invalid for otg_cap paremter. Check HW configuration.\n",
5557                              val);
5558                 }
5559                 val =
5560                     (((core_if->hwcfg2.b.op_mode ==
5561                        DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG)
5562                       || (core_if->hwcfg2.b.op_mode ==
5563                           DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG)
5564                       || (core_if->hwcfg2.b.op_mode ==
5565                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE)
5566                       || (core_if->hwcfg2.b.op_mode ==
5567                           DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
5568                      DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
5569                      DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE);
5570                 retval = -DWC_E_INVALID;
5571         }
5572
5573         core_if->core_params->otg_cap = val;
5574 out:
5575         return retval;
5576 }
5577
5578 int32_t dwc_otg_get_param_otg_cap(dwc_otg_core_if_t * core_if)
5579 {
5580         return core_if->core_params->otg_cap;
5581 }
5582
5583 int dwc_otg_set_param_opt(dwc_otg_core_if_t * core_if, int32_t val)
5584 {
5585         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5586                 DWC_WARN("Wrong value for opt parameter\n");
5587                 return -DWC_E_INVALID;
5588         }
5589         core_if->core_params->opt = val;
5590         return 0;
5591 }
5592
5593 int32_t dwc_otg_get_param_opt(dwc_otg_core_if_t * core_if)
5594 {
5595         return core_if->core_params->opt;
5596 }
5597
5598 int dwc_otg_set_param_dma_enable(dwc_otg_core_if_t * core_if, int32_t val)
5599 {
5600         int retval = 0;
5601         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5602                 DWC_WARN("Wrong value for dma enable\n");
5603                 return -DWC_E_INVALID;
5604         }
5605
5606         if ((val == 1) && (core_if->hwcfg2.b.architecture == 0)) {
5607                 if (dwc_otg_param_initialized(core_if->core_params->dma_enable)) {
5608                         DWC_ERROR
5609                             ("%d invalid for dma_enable paremter. Check HW configuration.\n",
5610                              val);
5611                 }
5612                 val = 0;
5613                 retval = -DWC_E_INVALID;
5614         }
5615
5616         core_if->core_params->dma_enable = val;
5617         if (val == 0) {
5618                 dwc_otg_set_param_dma_desc_enable(core_if, 0);
5619         }
5620         return retval;
5621 }
5622
5623 int32_t dwc_otg_get_param_dma_enable(dwc_otg_core_if_t * core_if)
5624 {
5625         return core_if->core_params->dma_enable;
5626 }
5627
5628 int dwc_otg_set_param_dma_desc_enable(dwc_otg_core_if_t * core_if, int32_t val)
5629 {
5630         int retval = 0;
5631         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5632                 DWC_WARN("Wrong value for dma_enable\n");
5633                 DWC_WARN("dma_desc_enable must be 0 or 1\n");
5634                 return -DWC_E_INVALID;
5635         }
5636
5637         if ((val == 1)
5638             && ((dwc_otg_get_param_dma_enable(core_if) == 0)
5639                 || (core_if->hwcfg4.b.desc_dma == 0))) {
5640                 if (dwc_otg_param_initialized
5641                     (core_if->core_params->dma_desc_enable)) {
5642                         DWC_ERROR
5643                             ("%d invalid for dma_desc_enable paremter. Check HW configuration.\n",
5644                              val);
5645                 }
5646                 val = 0;
5647                 retval = -DWC_E_INVALID;
5648         }
5649         core_if->core_params->dma_desc_enable = val;
5650         return retval;
5651 }
5652
5653 int32_t dwc_otg_get_param_dma_desc_enable(dwc_otg_core_if_t * core_if)
5654 {
5655         return core_if->core_params->dma_desc_enable;
5656 }
5657
5658 int dwc_otg_set_param_host_support_fs_ls_low_power(dwc_otg_core_if_t * core_if,
5659                                                    int32_t val)
5660 {
5661         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5662                 DWC_WARN("Wrong value for host_support_fs_low_power\n");
5663                 DWC_WARN("host_support_fs_low_power must be 0 or 1\n");
5664                 return -DWC_E_INVALID;
5665         }
5666         core_if->core_params->host_support_fs_ls_low_power = val;
5667         return 0;
5668 }
5669
5670 int32_t dwc_otg_get_param_host_support_fs_ls_low_power(dwc_otg_core_if_t *
5671                                                        core_if)
5672 {
5673         return core_if->core_params->host_support_fs_ls_low_power;
5674 }
5675
5676 int dwc_otg_set_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if,
5677                                           int32_t val)
5678 {
5679         int retval = 0;
5680         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
5681                 DWC_WARN("Wrong value for enable_dynamic_fifo\n");
5682                 DWC_WARN("enable_dynamic_fifo must be 0 or 1\n");
5683                 return -DWC_E_INVALID;
5684         }
5685
5686         if ((val == 1) && (core_if->hwcfg2.b.dynamic_fifo == 0)) {
5687                 if (dwc_otg_param_initialized
5688                     (core_if->core_params->enable_dynamic_fifo)) {
5689                         DWC_ERROR
5690                             ("%d invalid for enable_dynamic_fifo paremter. Check HW configuration.\n",
5691                              val);
5692                 }
5693                 val = 0;
5694                 retval = -DWC_E_INVALID;
5695         }
5696         core_if->core_params->enable_dynamic_fifo = val;
5697         return retval;
5698 }
5699
5700 int32_t dwc_otg_get_param_enable_dynamic_fifo(dwc_otg_core_if_t * core_if)
5701 {
5702         return core_if->core_params->enable_dynamic_fifo;
5703 }
5704
5705 int dwc_otg_set_param_data_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
5706 {
5707         int retval = 0;
5708         if (DWC_OTG_PARAM_TEST(val, 32, 32768)) {
5709                 DWC_WARN("Wrong value for data_fifo_size\n");
5710                 DWC_WARN("data_fifo_size must be 32-32768\n");
5711                 return -DWC_E_INVALID;
5712         }
5713
5714         if (val > core_if->hwcfg3.b.dfifo_depth) {
5715                 if (dwc_otg_param_initialized
5716                     (core_if->core_params->data_fifo_size)) {
5717                         DWC_ERROR
5718                             ("%d invalid for data_fifo_size parameter. Check HW configuration.\n",
5719                              val);
5720                 }
5721                 val = core_if->hwcfg3.b.dfifo_depth;
5722                 retval = -DWC_E_INVALID;
5723         }
5724
5725         core_if->core_params->data_fifo_size = val;
5726         return retval;
5727 }
5728
5729 int32_t dwc_otg_get_param_data_fifo_size(dwc_otg_core_if_t * core_if)
5730 {
5731         return core_if->core_params->data_fifo_size;
5732 }
5733
5734 int dwc_otg_set_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val)
5735 {
5736         int retval = 0;
5737         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5738                 DWC_WARN("Wrong value for dev_rx_fifo_size\n");
5739                 DWC_WARN("dev_rx_fifo_size must be 16-32768\n");
5740                 return -DWC_E_INVALID;
5741         }
5742
5743         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
5744                 if (dwc_otg_param_initialized(core_if->core_params->dev_rx_fifo_size)) {
5745                 DWC_WARN("%d invalid for dev_rx_fifo_size parameter\n", val);
5746                 }
5747                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
5748                 retval = -DWC_E_INVALID;
5749         }
5750
5751         core_if->core_params->dev_rx_fifo_size = val;
5752         return retval;
5753 }
5754
5755 int32_t dwc_otg_get_param_dev_rx_fifo_size(dwc_otg_core_if_t * core_if)
5756 {
5757         return core_if->core_params->dev_rx_fifo_size;
5758 }
5759
5760 int dwc_otg_set_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5761                                               int32_t val)
5762 {
5763         int retval = 0;
5764
5765         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5766                 DWC_WARN("Wrong value for dev_nperio_tx_fifo\n");
5767                 DWC_WARN("dev_nperio_tx_fifo must be 16-32768\n");
5768                 return -DWC_E_INVALID;
5769         }
5770
5771         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
5772                 if (dwc_otg_param_initialized
5773                     (core_if->core_params->dev_nperio_tx_fifo_size)) {
5774                         DWC_ERROR
5775                             ("%d invalid for dev_nperio_tx_fifo_size. Check HW configuration.\n",
5776                              val);
5777                 }
5778                 val =
5779                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
5780                      16);
5781                 retval = -DWC_E_INVALID;
5782         }
5783
5784         core_if->core_params->dev_nperio_tx_fifo_size = val;
5785         return retval;
5786 }
5787
5788 int32_t dwc_otg_get_param_dev_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5789 {
5790         return core_if->core_params->dev_nperio_tx_fifo_size;
5791 }
5792
5793 int dwc_otg_set_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if,
5794                                         int32_t val)
5795 {
5796         int retval = 0;
5797
5798         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5799                 DWC_WARN("Wrong value for host_rx_fifo_size\n");
5800                 DWC_WARN("host_rx_fifo_size must be 16-32768\n");
5801                 return -DWC_E_INVALID;
5802         }
5803
5804         if (val > DWC_READ_REG32(&core_if->core_global_regs->grxfsiz)) {
5805                 if (dwc_otg_param_initialized
5806                     (core_if->core_params->host_rx_fifo_size)) {
5807                         DWC_ERROR
5808                             ("%d invalid for host_rx_fifo_size. Check HW configuration.\n",
5809                              val);
5810                 }
5811                 val = DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
5812                 retval = -DWC_E_INVALID;
5813         }
5814
5815         core_if->core_params->host_rx_fifo_size = val;
5816         return retval;
5817
5818 }
5819
5820 int32_t dwc_otg_get_param_host_rx_fifo_size(dwc_otg_core_if_t * core_if)
5821 {
5822         return core_if->core_params->host_rx_fifo_size;
5823 }
5824
5825 int dwc_otg_set_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5826                                                int32_t val)
5827 {
5828         int retval = 0;
5829
5830         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5831                 DWC_WARN("Wrong value for host_nperio_tx_fifo_size\n");
5832                 DWC_WARN("host_nperio_tx_fifo_size must be 16-32768\n");
5833                 return -DWC_E_INVALID;
5834         }
5835
5836         if (val > (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >> 16)) {
5837                 if (dwc_otg_param_initialized
5838                     (core_if->core_params->host_nperio_tx_fifo_size)) {
5839                         DWC_ERROR
5840                             ("%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
5841                              val);
5842                 }
5843                 val =
5844                     (DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz) >>
5845                      16);
5846                 retval = -DWC_E_INVALID;
5847         }
5848
5849         core_if->core_params->host_nperio_tx_fifo_size = val;
5850         return retval;
5851 }
5852
5853 int32_t dwc_otg_get_param_host_nperio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5854 {
5855         return core_if->core_params->host_nperio_tx_fifo_size;
5856 }
5857
5858 int dwc_otg_set_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
5859                                               int32_t val)
5860 {
5861         int retval = 0;
5862         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
5863                 DWC_WARN("Wrong value for host_perio_tx_fifo_size\n");
5864                 DWC_WARN("host_perio_tx_fifo_size must be 16-32768\n");
5865                 return -DWC_E_INVALID;
5866         }
5867
5868         if (val > ((core_if->hptxfsiz.d32) >> 16)) {
5869                 if (dwc_otg_param_initialized
5870                     (core_if->core_params->host_perio_tx_fifo_size)) {
5871                         DWC_ERROR
5872                             ("%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
5873                              val);
5874                 }
5875                 val = (core_if->hptxfsiz.d32) >> 16;
5876                 retval = -DWC_E_INVALID;
5877         }
5878
5879         core_if->core_params->host_perio_tx_fifo_size = val;
5880         return retval;
5881 }
5882
5883 int32_t dwc_otg_get_param_host_perio_tx_fifo_size(dwc_otg_core_if_t * core_if)
5884 {
5885         return core_if->core_params->host_perio_tx_fifo_size;
5886 }
5887
5888 int dwc_otg_set_param_max_transfer_size(dwc_otg_core_if_t * core_if,
5889                                         int32_t val)
5890 {
5891         int retval = 0;
5892
5893         if (DWC_OTG_PARAM_TEST(val, 2047, 524288)) {
5894                 DWC_WARN("Wrong value for max_transfer_size\n");
5895                 DWC_WARN("max_transfer_size must be 2047-524288\n");
5896                 return -DWC_E_INVALID;
5897         }
5898
5899         if (val >= (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))) {
5900                 if (dwc_otg_param_initialized
5901                     (core_if->core_params->max_transfer_size)) {
5902                         DWC_ERROR
5903                             ("%d invalid for max_transfer_size. Check HW configuration.\n",
5904                              val);
5905                 }
5906                 val =
5907                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 11)) -
5908                      1);
5909                 retval = -DWC_E_INVALID;
5910         }
5911
5912         core_if->core_params->max_transfer_size = val;
5913         return retval;
5914 }
5915
5916 int32_t dwc_otg_get_param_max_transfer_size(dwc_otg_core_if_t * core_if)
5917 {
5918         return core_if->core_params->max_transfer_size;
5919 }
5920
5921 int dwc_otg_set_param_max_packet_count(dwc_otg_core_if_t * core_if, int32_t val)
5922 {
5923         int retval = 0;
5924
5925         if (DWC_OTG_PARAM_TEST(val, 15, 511)) {
5926                 DWC_WARN("Wrong value for max_packet_count\n");
5927                 DWC_WARN("max_packet_count must be 15-511\n");
5928                 return -DWC_E_INVALID;
5929         }
5930
5931         if (val > (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))) {
5932                 if (dwc_otg_param_initialized
5933                     (core_if->core_params->max_packet_count)) {
5934                         DWC_ERROR
5935                             ("%d invalid for max_packet_count. Check HW configuration.\n",
5936                              val);
5937                 }
5938                 val =
5939                     ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1);
5940                 retval = -DWC_E_INVALID;
5941         }
5942
5943         core_if->core_params->max_packet_count = val;
5944         return retval;
5945 }
5946
5947 int32_t dwc_otg_get_param_max_packet_count(dwc_otg_core_if_t * core_if)
5948 {
5949         return core_if->core_params->max_packet_count;
5950 }
5951
5952 int dwc_otg_set_param_host_channels(dwc_otg_core_if_t * core_if, int32_t val)
5953 {
5954         int retval = 0;
5955
5956         if (DWC_OTG_PARAM_TEST(val, 1, 16)) {
5957                 DWC_WARN("Wrong value for host_channels\n");
5958                 DWC_WARN("host_channels must be 1-16\n");
5959                 return -DWC_E_INVALID;
5960         }
5961
5962         if (val > (core_if->hwcfg2.b.num_host_chan + 1)) {
5963                 if (dwc_otg_param_initialized
5964                     (core_if->core_params->host_channels)) {
5965                         DWC_ERROR
5966                             ("%d invalid for host_channels. Check HW configurations.\n",
5967                              val);
5968                 }
5969                 val = (core_if->hwcfg2.b.num_host_chan + 1);
5970                 retval = -DWC_E_INVALID;
5971         }
5972
5973         core_if->core_params->host_channels = val;
5974         return retval;
5975 }
5976
5977 int32_t dwc_otg_get_param_host_channels(dwc_otg_core_if_t * core_if)
5978 {
5979         return core_if->core_params->host_channels;
5980 }
5981
5982 int dwc_otg_set_param_dev_endpoints(dwc_otg_core_if_t * core_if, int32_t val)
5983 {
5984         int retval = 0;
5985
5986         if (DWC_OTG_PARAM_TEST(val, 1, 15)) {
5987                 DWC_WARN("Wrong value for dev_endpoints\n");
5988                 DWC_WARN("dev_endpoints must be 1-15\n");
5989                 return -DWC_E_INVALID;
5990         }
5991
5992         if (val > (core_if->hwcfg2.b.num_dev_ep)) {
5993                 if (dwc_otg_param_initialized
5994                     (core_if->core_params->dev_endpoints)) {
5995                         DWC_ERROR
5996                             ("%d invalid for dev_endpoints. Check HW configurations.\n",
5997                              val);
5998                 }
5999                 val = core_if->hwcfg2.b.num_dev_ep;
6000                 retval = -DWC_E_INVALID;
6001         }
6002
6003         core_if->core_params->dev_endpoints = val;
6004         return retval;
6005 }
6006
6007 int32_t dwc_otg_get_param_dev_endpoints(dwc_otg_core_if_t * core_if)
6008 {
6009         return core_if->core_params->dev_endpoints;
6010 }
6011
6012 int dwc_otg_set_param_phy_type(dwc_otg_core_if_t * core_if, int32_t val)
6013 {
6014         int retval = 0;
6015         int valid = 0;
6016
6017         if (DWC_OTG_PARAM_TEST(val, 0, 2)) {
6018                 DWC_WARN("Wrong value for phy_type\n");
6019                 DWC_WARN("phy_type must be 0,1 or 2\n");
6020                 return -DWC_E_INVALID;
6021         }
6022 #ifndef NO_FS_PHY_HW_CHECKS
6023         if ((val == DWC_PHY_TYPE_PARAM_UTMI) &&
6024             ((core_if->hwcfg2.b.hs_phy_type == 1) ||
6025              (core_if->hwcfg2.b.hs_phy_type == 3))) {
6026                 valid = 1;
6027         } else if ((val == DWC_PHY_TYPE_PARAM_ULPI) &&
6028                    ((core_if->hwcfg2.b.hs_phy_type == 2) ||
6029                     (core_if->hwcfg2.b.hs_phy_type == 3))) {
6030                 valid = 1;
6031         } else if ((val == DWC_PHY_TYPE_PARAM_FS) &&
6032                    (core_if->hwcfg2.b.fs_phy_type == 1)) {
6033                 valid = 1;
6034         }
6035         if (!valid) {
6036                 if (dwc_otg_param_initialized(core_if->core_params->phy_type)) {
6037                         DWC_ERROR
6038                             ("%d invalid for phy_type. Check HW configurations.\n",
6039                              val);
6040                 }
6041                 if (core_if->hwcfg2.b.hs_phy_type) {
6042                         if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
6043                             (core_if->hwcfg2.b.hs_phy_type == 1)) {
6044                                 val = DWC_PHY_TYPE_PARAM_UTMI;
6045                         } else {
6046                                 val = DWC_PHY_TYPE_PARAM_ULPI;
6047                         }
6048                 }
6049                 retval = -DWC_E_INVALID;
6050         }
6051 #endif
6052         core_if->core_params->phy_type = val;
6053         return retval;
6054 }
6055
6056 int32_t dwc_otg_get_param_phy_type(dwc_otg_core_if_t * core_if)
6057 {
6058         return core_if->core_params->phy_type;
6059 }
6060
6061 int dwc_otg_set_param_speed(dwc_otg_core_if_t * core_if, int32_t val)
6062 {
6063         int retval = 0;
6064         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6065                 DWC_WARN("Wrong value for speed parameter\n");
6066                 DWC_WARN("max_speed parameter must be 0 or 1\n");
6067                 return -DWC_E_INVALID;
6068         }
6069         if ((val == 0)
6070             && dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS) {
6071                 if (dwc_otg_param_initialized(core_if->core_params->speed)) {
6072                         DWC_ERROR
6073                             ("%d invalid for speed paremter. Check HW configuration.\n",
6074                              val);
6075                 }
6076                 val =
6077                     (dwc_otg_get_param_phy_type(core_if) ==
6078                      DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
6079                 retval = -DWC_E_INVALID;
6080         }
6081         core_if->core_params->speed = val;
6082         return retval;
6083 }
6084
6085 int32_t dwc_otg_get_param_speed(dwc_otg_core_if_t * core_if)
6086 {
6087         return core_if->core_params->speed;
6088 }
6089
6090 int dwc_otg_set_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if,
6091                                                 int32_t val)
6092 {
6093         int retval = 0;
6094
6095         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6096                 DWC_WARN
6097                     ("Wrong value for host_ls_low_power_phy_clk parameter\n");
6098                 DWC_WARN("host_ls_low_power_phy_clk must be 0 or 1\n");
6099                 return -DWC_E_INVALID;
6100         }
6101
6102         if ((val == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)
6103             && (dwc_otg_get_param_phy_type(core_if) == DWC_PHY_TYPE_PARAM_FS)) {
6104                 if (dwc_otg_param_initialized
6105                     (core_if->core_params->host_ls_low_power_phy_clk)) {
6106                         DWC_ERROR
6107                             ("%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
6108                              val);
6109                 }
6110                 val =
6111                     (dwc_otg_get_param_phy_type(core_if) ==
6112                      DWC_PHY_TYPE_PARAM_FS) ?
6113                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ :
6114                     DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
6115                 retval = -DWC_E_INVALID;
6116         }
6117
6118         core_if->core_params->host_ls_low_power_phy_clk = val;
6119         return retval;
6120 }
6121
6122 int32_t dwc_otg_get_param_host_ls_low_power_phy_clk(dwc_otg_core_if_t * core_if)
6123 {
6124         return core_if->core_params->host_ls_low_power_phy_clk;
6125 }
6126
6127 int dwc_otg_set_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if, int32_t val)
6128 {
6129         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6130                 DWC_WARN("Wrong value for phy_ulpi_ddr\n");
6131                 DWC_WARN("phy_upli_ddr must be 0 or 1\n");
6132                 return -DWC_E_INVALID;
6133         }
6134
6135         core_if->core_params->phy_ulpi_ddr = val;
6136         return 0;
6137 }
6138
6139 int32_t dwc_otg_get_param_phy_ulpi_ddr(dwc_otg_core_if_t * core_if)
6140 {
6141         return core_if->core_params->phy_ulpi_ddr;
6142 }
6143
6144 int dwc_otg_set_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if,
6145                                         int32_t val)
6146 {
6147         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6148                 DWC_WARN("Wrong valaue for phy_ulpi_ext_vbus\n");
6149                 DWC_WARN("phy_ulpi_ext_vbus must be 0 or 1\n");
6150                 return -DWC_E_INVALID;
6151         }
6152
6153         core_if->core_params->phy_ulpi_ext_vbus = val;
6154         return 0;
6155 }
6156
6157 int32_t dwc_otg_get_param_phy_ulpi_ext_vbus(dwc_otg_core_if_t * core_if)
6158 {
6159         return core_if->core_params->phy_ulpi_ext_vbus;
6160 }
6161
6162 int dwc_otg_set_param_phy_utmi_width(dwc_otg_core_if_t * core_if, int32_t val)
6163 {
6164         if (DWC_OTG_PARAM_TEST(val, 8, 8) && DWC_OTG_PARAM_TEST(val, 16, 16)) {
6165                 DWC_WARN("Wrong valaue for phy_utmi_width\n");
6166                 DWC_WARN("phy_utmi_width must be 8 or 16\n");
6167                 return -DWC_E_INVALID;
6168         }
6169
6170         core_if->core_params->phy_utmi_width = val;
6171         return 0;
6172 }
6173
6174 int32_t dwc_otg_get_param_phy_utmi_width(dwc_otg_core_if_t * core_if)
6175 {
6176         return core_if->core_params->phy_utmi_width;
6177 }
6178
6179 int dwc_otg_set_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if, int32_t val)
6180 {
6181         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6182                 DWC_WARN("Wrong valaue for ulpi_fs_ls\n");
6183                 DWC_WARN("ulpi_fs_ls must be 0 or 1\n");
6184                 return -DWC_E_INVALID;
6185         }
6186
6187         core_if->core_params->ulpi_fs_ls = val;
6188         return 0;
6189 }
6190
6191 int32_t dwc_otg_get_param_ulpi_fs_ls(dwc_otg_core_if_t * core_if)
6192 {
6193         return core_if->core_params->ulpi_fs_ls;
6194 }
6195
6196 int dwc_otg_set_param_ts_dline(dwc_otg_core_if_t * core_if, int32_t val)
6197 {
6198         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6199                 DWC_WARN("Wrong valaue for ts_dline\n");
6200                 DWC_WARN("ts_dline must be 0 or 1\n");
6201                 return -DWC_E_INVALID;
6202         }
6203
6204         core_if->core_params->ts_dline = val;
6205         return 0;
6206 }
6207
6208 int32_t dwc_otg_get_param_ts_dline(dwc_otg_core_if_t * core_if)
6209 {
6210         return core_if->core_params->ts_dline;
6211 }
6212
6213 int dwc_otg_set_param_i2c_enable(dwc_otg_core_if_t * core_if, int32_t val)
6214 {
6215         int retval = 0;
6216         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6217                 DWC_WARN("Wrong valaue for i2c_enable\n");
6218                 DWC_WARN("i2c_enable must be 0 or 1\n");
6219                 return -DWC_E_INVALID;
6220         }
6221 #ifndef NO_FS_PHY_HW_CHECK
6222         if (val == 1 && core_if->hwcfg3.b.i2c == 0) {
6223                 if (dwc_otg_param_initialized(core_if->core_params->i2c_enable)) {
6224                         DWC_ERROR
6225                             ("%d invalid for i2c_enable. Check HW configuration.\n",
6226                              val);
6227                 }
6228                 val = 0;
6229                 retval = -DWC_E_INVALID;
6230         }
6231 #endif
6232
6233         core_if->core_params->i2c_enable = val;
6234         return retval;
6235 }
6236
6237 int32_t dwc_otg_get_param_i2c_enable(dwc_otg_core_if_t * core_if)
6238 {
6239         return core_if->core_params->i2c_enable;
6240 }
6241
6242 int dwc_otg_set_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
6243                                              int32_t val, int fifo_num)
6244 {
6245         int retval = 0;
6246         gintsts_data_t gintsts;
6247         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6248
6249         if (core_if->hwcfg4.b.ded_fifo_en == 0){
6250                 if (DWC_OTG_PARAM_TEST(val, 4, 768)) {
6251                         DWC_WARN("Wrong value for dev_perio_tx_fifo_size\n");
6252                         DWC_WARN("dev_perio_tx_fifo_size must be 4-768\n");
6253                         return -DWC_E_INVALID;
6254                 }
6255
6256                 if (val > (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16)) {
6257                         printk("%d   ",DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
6258                         printk("val = %d fifo_num = %d\n",val,fifo_num);
6259                         DWC_WARN("Value is larger then power-on FIFO size\n");
6260                         if (dwc_otg_param_initialized
6261                            (core_if->core_params->dev_perio_tx_fifo_size[fifo_num])) {
6262                                 DWC_ERROR
6263                                 ("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n",
6264                                 val, fifo_num);
6265                         }
6266                         val = (DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]) >> 16);
6267                         retval = -DWC_E_INVALID;
6268                 }
6269
6270                 core_if->core_params->dev_perio_tx_fifo_size[fifo_num] = val;
6271         }
6272         return retval;
6273 }
6274
6275 int32_t dwc_otg_get_param_dev_perio_tx_fifo_size(dwc_otg_core_if_t * core_if,
6276                                                  int fifo_num)
6277 {
6278         return core_if->core_params->dev_perio_tx_fifo_size[fifo_num];
6279 }
6280
6281 int dwc_otg_set_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if,
6282                                           int32_t val)
6283 {
6284         int retval = 0;
6285         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6286                 DWC_WARN("Wrong valaue for en_multiple_tx_fifo,\n");
6287                 DWC_WARN("en_multiple_tx_fifo must be 0 or 1\n");
6288                 return -DWC_E_INVALID;
6289         }
6290
6291         if (val == 1 && core_if->hwcfg4.b.ded_fifo_en == 0) {
6292                 if (dwc_otg_param_initialized
6293                     (core_if->core_params->en_multiple_tx_fifo)) {
6294                         DWC_ERROR
6295                             ("%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
6296                              val);
6297                 }
6298                 val = 0;
6299                 retval = -DWC_E_INVALID;
6300         }
6301
6302         core_if->core_params->en_multiple_tx_fifo = val;
6303         return retval;
6304 }
6305
6306 int32_t dwc_otg_get_param_en_multiple_tx_fifo(dwc_otg_core_if_t * core_if)
6307 {
6308         return core_if->core_params->en_multiple_tx_fifo;
6309 }
6310
6311 int dwc_otg_set_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if, int32_t val,
6312                                        int fifo_num)
6313 {
6314         int retval = 0;
6315         fifosize_data_t txfifosize;
6316         txfifosize.d32 = DWC_READ_REG32(&core_if->core_global_regs->dtxfsiz[fifo_num]);
6317
6318         if (DWC_OTG_PARAM_TEST(val, 16, 32768)) {
6319                 DWC_WARN("Wrong value for dev_tx_fifo_size\n");
6320                 DWC_WARN("dev_tx_fifo_size must be 16-32768\n");
6321                 return -DWC_E_INVALID;
6322         }
6323
6324         core_if->core_params->dev_tx_fifo_size[fifo_num] = val;
6325         return retval;
6326 }
6327
6328 int32_t dwc_otg_get_param_dev_tx_fifo_size(dwc_otg_core_if_t * core_if,
6329                                            int fifo_num)
6330 {
6331         return core_if->core_params->dev_tx_fifo_size[fifo_num];
6332 }
6333
6334 int dwc_otg_set_param_thr_ctl(dwc_otg_core_if_t * core_if, int32_t val)
6335 {
6336         int retval = 0;
6337
6338         if (DWC_OTG_PARAM_TEST(val, 0, 7)) {
6339                 DWC_WARN("Wrong value for thr_ctl\n");
6340                 DWC_WARN("thr_ctl must be 0-7\n");
6341                 return -DWC_E_INVALID;
6342         }
6343
6344         if ((val != 0) &&
6345             (!dwc_otg_get_param_dma_enable(core_if) ||
6346              !core_if->hwcfg4.b.ded_fifo_en)) {
6347                 if (dwc_otg_param_initialized(core_if->core_params->thr_ctl)) {
6348                         DWC_ERROR
6349                             ("%d invalid for parameter thr_ctl. Check HW configuration.\n",
6350                              val);
6351                 }
6352                 val = 0;
6353                 retval = -DWC_E_INVALID;
6354         }
6355
6356         core_if->core_params->thr_ctl = val;
6357         return retval;
6358 }
6359
6360 int32_t dwc_otg_get_param_thr_ctl(dwc_otg_core_if_t * core_if)
6361 {
6362         return core_if->core_params->thr_ctl;
6363 }
6364
6365 int dwc_otg_set_param_lpm_enable(dwc_otg_core_if_t * core_if, int32_t val)
6366 {
6367         int retval = 0;
6368
6369         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6370                 DWC_WARN("Wrong value for lpm_enable\n");
6371                 DWC_WARN("lpm_enable must be 0 or 1\n");
6372                 return -DWC_E_INVALID;
6373         }
6374
6375         if (val && !core_if->hwcfg3.b.otg_lpm_en) {
6376                 if (dwc_otg_param_initialized(core_if->core_params->lpm_enable)) {
6377                         DWC_ERROR
6378                             ("%d invalid for parameter lpm_enable. Check HW configuration.\n",
6379                              val);
6380                 }
6381                 val = 0;
6382                 retval = -DWC_E_INVALID;
6383         }
6384
6385         core_if->core_params->lpm_enable = val;
6386         return retval;
6387 }
6388
6389 int32_t dwc_otg_get_param_lpm_enable(dwc_otg_core_if_t * core_if)
6390 {
6391         return core_if->core_params->lpm_enable;
6392 }
6393
6394 int dwc_otg_set_param_besl_enable(dwc_otg_core_if_t * core_if, int32_t val)
6395 {
6396         int retval = 0;
6397
6398         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6399                 DWC_WARN("Wrong value for besl_enable\n");
6400                 DWC_WARN("besl_enable must be 0 or 1\n");
6401                 return -DWC_E_INVALID;
6402         }
6403
6404         core_if->core_params->besl_enable = val;
6405
6406         if(val)
6407         {
6408                 retval += dwc_otg_set_param_lpm_enable(core_if,val);
6409         }
6410
6411         return retval;
6412 }
6413
6414 int32_t dwc_otg_get_param_besl_enable(dwc_otg_core_if_t * core_if)
6415 {
6416         return core_if->core_params->besl_enable;
6417 }
6418
6419 int dwc_otg_set_param_baseline_besl(dwc_otg_core_if_t * core_if, int32_t val)
6420 {
6421         int retval = 0;
6422
6423         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6424                 DWC_WARN("Wrong value for baseline_besl\n");
6425                 DWC_WARN("baseline_besl must be 0-15\n");
6426                 return -DWC_E_INVALID;
6427         }
6428
6429         core_if->core_params->baseline_besl = val;
6430         return retval;
6431 }
6432
6433 int32_t dwc_otg_get_param_baseline_besl(dwc_otg_core_if_t * core_if)
6434 {
6435         return core_if->core_params->baseline_besl;
6436 }
6437
6438 int dwc_otg_set_param_deep_besl(dwc_otg_core_if_t * core_if, int32_t val)
6439 {
6440         int retval = 0;
6441
6442         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
6443                 DWC_WARN("Wrong value for deep_besl\n");
6444                 DWC_WARN("deep_besl must be 0-15\n");
6445                 return -DWC_E_INVALID;
6446         }
6447
6448         core_if->core_params->deep_besl = val;
6449         return retval;
6450 }
6451
6452 int32_t dwc_otg_get_param_deep_besl(dwc_otg_core_if_t * core_if)
6453 {
6454         return core_if->core_params->deep_besl;
6455 }
6456
6457 int dwc_otg_set_param_tx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
6458 {
6459         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6460                 DWC_WARN("Wrong valaue for tx_thr_length\n");
6461                 DWC_WARN("tx_thr_length must be 8 - 128\n");
6462                 return -DWC_E_INVALID;
6463         }
6464
6465         core_if->core_params->tx_thr_length = val;
6466         return 0;
6467 }
6468
6469 int32_t dwc_otg_get_param_tx_thr_length(dwc_otg_core_if_t * core_if)
6470 {
6471         return core_if->core_params->tx_thr_length;
6472 }
6473
6474 int dwc_otg_set_param_rx_thr_length(dwc_otg_core_if_t * core_if, int32_t val)
6475 {
6476         if (DWC_OTG_PARAM_TEST(val, 8, 128)) {
6477                 DWC_WARN("Wrong valaue for rx_thr_length\n");
6478                 DWC_WARN("rx_thr_length must be 8 - 128\n");
6479                 return -DWC_E_INVALID;
6480         }
6481
6482         core_if->core_params->rx_thr_length = val;
6483         return 0;
6484 }
6485
6486 int32_t dwc_otg_get_param_rx_thr_length(dwc_otg_core_if_t * core_if)
6487 {
6488         return core_if->core_params->rx_thr_length;
6489 }
6490
6491 int dwc_otg_set_param_dma_burst_size(dwc_otg_core_if_t * core_if, int32_t val)
6492 {
6493         if (DWC_OTG_PARAM_TEST(val, 1, 1) &&
6494             DWC_OTG_PARAM_TEST(val, 4, 4) &&
6495             DWC_OTG_PARAM_TEST(val, 8, 8) &&
6496             DWC_OTG_PARAM_TEST(val, 16, 16) &&
6497             DWC_OTG_PARAM_TEST(val, 32, 32) &&
6498             DWC_OTG_PARAM_TEST(val, 64, 64) &&
6499             DWC_OTG_PARAM_TEST(val, 128, 128) &&
6500             DWC_OTG_PARAM_TEST(val, 256, 256)) {
6501                 DWC_WARN("`%d' invalid for parameter `dma_burst_size'\n", val);
6502                 return -DWC_E_INVALID;
6503         }
6504         core_if->core_params->dma_burst_size = val;
6505         return 0;
6506 }
6507
6508 int32_t dwc_otg_get_param_dma_burst_size(dwc_otg_core_if_t * core_if)
6509 {
6510         return core_if->core_params->dma_burst_size;
6511 }
6512
6513 int dwc_otg_set_param_pti_enable(dwc_otg_core_if_t * core_if, int32_t val)
6514 {
6515         int retval = 0;
6516         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6517                 DWC_WARN("`%d' invalid for parameter `pti_enable'\n", val);
6518                 return -DWC_E_INVALID;
6519         }
6520         if (val && (core_if->snpsid < OTG_CORE_REV_2_72a)) {
6521                 if (dwc_otg_param_initialized(core_if->core_params->pti_enable)) {
6522                         DWC_ERROR
6523                             ("%d invalid for parameter pti_enable. Check HW configuration.\n",
6524                              val);
6525                 }
6526                 retval = -DWC_E_INVALID;
6527                 val = 0;
6528         }
6529         core_if->core_params->pti_enable = val;
6530         return retval;
6531 }
6532
6533 int32_t dwc_otg_get_param_pti_enable(dwc_otg_core_if_t * core_if)
6534 {
6535         return core_if->core_params->pti_enable;
6536 }
6537
6538 int dwc_otg_set_param_mpi_enable(dwc_otg_core_if_t * core_if, int32_t val)
6539 {
6540         int retval = 0;
6541         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6542                 DWC_WARN("`%d' invalid for parameter `mpi_enable'\n", val);
6543                 return -DWC_E_INVALID;
6544         }
6545         if (val && (core_if->hwcfg2.b.multi_proc_int == 0)) {
6546                 if (dwc_otg_param_initialized(core_if->core_params->mpi_enable)) {
6547                         DWC_ERROR
6548                             ("%d invalid for parameter mpi_enable. Check HW configuration.\n",
6549                              val);
6550                 }
6551                 retval = -DWC_E_INVALID;
6552                 val = 0;
6553         }
6554         core_if->core_params->mpi_enable = val;
6555         return retval;
6556 }
6557
6558 int32_t dwc_otg_get_param_mpi_enable(dwc_otg_core_if_t * core_if)
6559 {
6560         return core_if->core_params->mpi_enable;
6561 }
6562
6563 int dwc_otg_set_param_adp_enable(dwc_otg_core_if_t * core_if, int32_t val)
6564 {
6565         int retval = 0;
6566         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6567                 DWC_WARN("`%d' invalid for parameter `adp_enable'\n", val);
6568                 return -DWC_E_INVALID;
6569         }
6570         if (val && (core_if->hwcfg3.b.adp_supp == 0)) {
6571                 if (dwc_otg_param_initialized
6572                     (core_if->core_params->adp_supp_enable)) {
6573                         DWC_ERROR
6574                             ("%d invalid for parameter adp_enable. Check HW configuration.\n",
6575                              val);
6576                 }
6577                 retval = -DWC_E_INVALID;
6578                 val = 0;
6579         }
6580         core_if->core_params->adp_supp_enable = val;
6581         /* Set OTG version 2.0 in case of enabling ADP */
6582         if (val)
6583                 dwc_otg_set_param_otg_ver(core_if, 1);
6584
6585         return retval;
6586 }
6587
6588 int32_t dwc_otg_get_param_adp_enable(dwc_otg_core_if_t * core_if)
6589 {
6590         return core_if->core_params->adp_supp_enable;
6591 }
6592
6593 int dwc_otg_set_param_ic_usb_cap(dwc_otg_core_if_t * core_if, int32_t val)
6594 {
6595         int retval = 0;
6596         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6597                 DWC_WARN("`%d' invalid for parameter `ic_usb_cap'\n", val);
6598                 DWC_WARN("ic_usb_cap must be 0 or 1\n");
6599                 return -DWC_E_INVALID;
6600         }
6601
6602         if (val && (core_if->hwcfg2.b.otg_enable_ic_usb == 0)) {
6603                 if (dwc_otg_param_initialized(core_if->core_params->ic_usb_cap)) {
6604                         DWC_ERROR
6605                             ("%d invalid for parameter ic_usb_cap. Check HW configuration.\n",
6606                              val);
6607                 }
6608                 retval = -DWC_E_INVALID;
6609                 val = 0;
6610         }
6611         core_if->core_params->ic_usb_cap = val;
6612         return retval;
6613 }
6614
6615 int32_t dwc_otg_get_param_ic_usb_cap(dwc_otg_core_if_t * core_if)
6616 {
6617         return core_if->core_params->ic_usb_cap;
6618 }
6619
6620 int dwc_otg_set_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if, int32_t val)
6621 {
6622         int retval = 0;
6623         int valid = 1;
6624
6625         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
6626                 DWC_WARN("`%d' invalid for parameter `ahb_thr_ratio'\n", val);
6627                 DWC_WARN("ahb_thr_ratio must be 0 - 3\n");
6628                 return -DWC_E_INVALID;
6629         }
6630
6631         if (val
6632             && (core_if->snpsid < OTG_CORE_REV_2_81a
6633                 || !dwc_otg_get_param_thr_ctl(core_if))) {
6634                 valid = 0;
6635         } else if (val
6636                    && ((dwc_otg_get_param_tx_thr_length(core_if) / (1 << val)) <
6637                        4)) {
6638                 valid = 0;
6639         }
6640         if (valid == 0) {
6641                 if (dwc_otg_param_initialized
6642                     (core_if->core_params->ahb_thr_ratio)) {
6643                         DWC_ERROR
6644                             ("%d invalid for parameter ahb_thr_ratio. Check HW configuration.\n",
6645                              val);
6646                 }
6647                 retval = -DWC_E_INVALID;
6648                 val = 0;
6649         }
6650
6651         core_if->core_params->ahb_thr_ratio = val;
6652         return retval;
6653 }
6654
6655 int32_t dwc_otg_get_param_ahb_thr_ratio(dwc_otg_core_if_t * core_if)
6656 {
6657         return core_if->core_params->ahb_thr_ratio;
6658 }
6659
6660 int dwc_otg_set_param_power_down(dwc_otg_core_if_t * core_if, int32_t val)
6661 {
6662         int retval = 0;
6663         int valid = 1;
6664         hwcfg4_data_t hwcfg4 = {.d32 = 0 };
6665         hwcfg4.d32 = DWC_READ_REG32(&core_if->core_global_regs->ghwcfg4);
6666
6667         if (DWC_OTG_PARAM_TEST(val, 0, 3)) {
6668                 DWC_WARN("`%d' invalid for parameter `power_down'\n", val);
6669                 DWC_WARN("power_down must be 0 - 2\n");
6670                 return -DWC_E_INVALID;
6671         }
6672
6673         if ((val == 2) && (core_if->snpsid < OTG_CORE_REV_2_91a)) {
6674                 valid = 0;
6675         }
6676         if ((val == 3)
6677             && ((core_if->snpsid < OTG_CORE_REV_3_00a)
6678                 || (hwcfg4.b.xhiber == 0))) {
6679                 valid = 0;
6680         }
6681         if (valid == 0) {
6682                 if (dwc_otg_param_initialized(core_if->core_params->power_down)) {
6683                         DWC_ERROR
6684                             ("%d invalid for parameter power_down. Check HW configuration.\n",
6685                              val);
6686                 }
6687                 retval = -DWC_E_INVALID;
6688                 val = 0;
6689         }
6690         core_if->core_params->power_down = val;
6691         return retval;
6692 }
6693
6694 int32_t dwc_otg_get_param_power_down(dwc_otg_core_if_t * core_if)
6695 {
6696         return core_if->core_params->power_down;
6697 }
6698
6699 int dwc_otg_set_param_reload_ctl(dwc_otg_core_if_t * core_if, int32_t val)
6700 {
6701         int retval = 0;
6702         int valid = 1;
6703
6704         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6705                 DWC_WARN("`%d' invalid for parameter `reload_ctl'\n", val);
6706                 DWC_WARN("reload_ctl must be 0 or 1\n");
6707                 return -DWC_E_INVALID;
6708         }
6709
6710         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_92a)) {
6711                 valid = 0;
6712         }
6713         if (valid == 0) {
6714                 if (dwc_otg_param_initialized(core_if->core_params->reload_ctl)) {
6715                         DWC_ERROR("%d invalid for parameter reload_ctl."
6716                                   "Check HW configuration.\n", val);
6717                 }
6718                 retval = -DWC_E_INVALID;
6719                 val = 0;
6720         }
6721         core_if->core_params->reload_ctl = val;
6722         return retval;
6723 }
6724
6725 int32_t dwc_otg_get_param_reload_ctl(dwc_otg_core_if_t * core_if)
6726 {
6727         return core_if->core_params->reload_ctl;
6728 }
6729
6730 int dwc_otg_set_param_dev_out_nak(dwc_otg_core_if_t * core_if, int32_t val)
6731 {
6732         int retval = 0;
6733         int valid = 1;
6734
6735         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6736                 DWC_WARN("`%d' invalid for parameter `dev_out_nak'\n", val);
6737                 DWC_WARN("dev_out_nak must be 0 or 1\n");
6738                 return -DWC_E_INVALID;
6739         }
6740
6741         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_93a) ||
6742                            !(core_if->core_params->dma_desc_enable))) {
6743                 valid = 0;
6744         }
6745         if (valid == 0) {
6746                 if (dwc_otg_param_initialized(core_if->core_params->dev_out_nak)) {
6747                         DWC_ERROR("%d invalid for parameter dev_out_nak."
6748                                   "Check HW configuration.\n", val);
6749                 }
6750                 retval = -DWC_E_INVALID;
6751                 val = 0;
6752         }
6753         core_if->core_params->dev_out_nak = val;
6754         return retval;
6755 }
6756
6757 int32_t dwc_otg_get_param_dev_out_nak(dwc_otg_core_if_t * core_if)
6758 {
6759         return core_if->core_params->dev_out_nak;
6760 }
6761
6762 int dwc_otg_set_param_cont_on_bna(dwc_otg_core_if_t * core_if, int32_t val)
6763 {
6764         int retval = 0;
6765         int valid = 1;
6766
6767         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6768                 DWC_WARN("`%d' invalid for parameter `cont_on_bna'\n", val);
6769                 DWC_WARN("cont_on_bna must be 0 or 1\n");
6770                 return -DWC_E_INVALID;
6771         }
6772
6773         if ((val == 1) && ((core_if->snpsid < OTG_CORE_REV_2_94a) ||
6774                            !(core_if->core_params->dma_desc_enable))) {
6775                 valid = 0;
6776         }
6777         if (valid == 0) {
6778                 if (dwc_otg_param_initialized(core_if->core_params->cont_on_bna)) {
6779                         DWC_ERROR("%d invalid for parameter cont_on_bna."
6780                                 "Check HW configuration.\n", val);
6781                 }
6782                 retval = -DWC_E_INVALID;
6783                 val = 0;
6784         }
6785         core_if->core_params->cont_on_bna = val;
6786         return retval;
6787 }
6788
6789 int32_t dwc_otg_get_param_cont_on_bna(dwc_otg_core_if_t * core_if)
6790 {
6791         return core_if->core_params->cont_on_bna;
6792 }
6793
6794 int dwc_otg_set_param_ahb_single(dwc_otg_core_if_t * core_if, int32_t val)
6795 {
6796         int retval = 0;
6797         int valid = 1;
6798
6799         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6800                 DWC_WARN("`%d' invalid for parameter `ahb_single'\n", val);
6801                 DWC_WARN("ahb_single must be 0 or 1\n");
6802                 return -DWC_E_INVALID;
6803         }
6804
6805         if ((val == 1) && (core_if->snpsid < OTG_CORE_REV_2_94a)) {
6806                 valid = 0;
6807         }
6808         if (valid == 0) {
6809                 if (dwc_otg_param_initialized(core_if->core_params->ahb_single)) {
6810                         DWC_ERROR("%d invalid for parameter ahb_single."
6811                                   "Check HW configuration.\n", val);
6812                 }
6813                 retval = -DWC_E_INVALID;
6814                 val = 0;
6815         }
6816         core_if->core_params->ahb_single = val;
6817         return retval;
6818 }
6819
6820 int32_t dwc_otg_get_param_ahb_single(dwc_otg_core_if_t * core_if)
6821 {
6822         return core_if->core_params->ahb_single;
6823 }
6824
6825 int dwc_otg_set_param_otg_ver(dwc_otg_core_if_t * core_if, int32_t val)
6826 {
6827         int retval = 0;
6828
6829         if (DWC_OTG_PARAM_TEST(val, 0, 1)) {
6830                 DWC_WARN("`%d' invalid for parameter `otg_ver'\n", val);
6831                 DWC_WARN
6832                     ("otg_ver must be 0(for OTG 1.3 support) or 1(for OTG 2.0 support)\n");
6833                 return -DWC_E_INVALID;
6834         }
6835
6836         core_if->core_params->otg_ver = val;
6837         return retval;
6838 }
6839
6840 int32_t dwc_otg_get_param_otg_ver(dwc_otg_core_if_t * core_if)
6841 {
6842         return core_if->core_params->otg_ver;
6843 }
6844
6845 uint32_t dwc_otg_get_hnpstatus(dwc_otg_core_if_t * core_if)
6846 {
6847         gotgctl_data_t otgctl;
6848         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6849         return otgctl.b.hstnegscs;
6850 }
6851
6852 uint32_t dwc_otg_get_srpstatus(dwc_otg_core_if_t * core_if)
6853 {
6854         gotgctl_data_t otgctl;
6855         otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6856         return otgctl.b.sesreqscs;
6857 }
6858
6859 void dwc_otg_set_hnpreq(dwc_otg_core_if_t * core_if, uint32_t val)
6860 {
6861         if(core_if->otg_ver == 0) {
6862                 gotgctl_data_t otgctl;
6863                 otgctl.d32 = DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
6864                 otgctl.b.hnpreq = val;
6865                 DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, otgctl.d32);
6866         } else {
6867                 core_if->otg_sts = val;
6868         }
6869 }
6870
6871 uint32_t dwc_otg_get_gsnpsid(dwc_otg_core_if_t * core_if)
6872 {
6873         return core_if->snpsid;
6874 }
6875
6876 uint32_t dwc_otg_get_mode(dwc_otg_core_if_t * core_if)
6877 {
6878         gintsts_data_t gintsts;
6879         gintsts.d32 = DWC_READ_REG32(&core_if->core_global_regs->gintsts);
6880         return gintsts.b.curmode;
6881 }
6882
6883 uint32_t dwc_otg_get_hnpcapable(dwc_otg_core_if_t * core_if)
6884 {
6885         gusbcfg_data_t usbcfg;
6886         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6887         return usbcfg.b.hnpcap;
6888 }
6889
6890 void dwc_otg_set_hnpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
6891 {
6892         gusbcfg_data_t usbcfg;
6893         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6894         usbcfg.b.hnpcap = val;
6895         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
6896 }
6897
6898 uint32_t dwc_otg_get_srpcapable(dwc_otg_core_if_t * core_if)
6899 {
6900         gusbcfg_data_t usbcfg;
6901         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6902         return usbcfg.b.srpcap;
6903 }
6904
6905 void dwc_otg_set_srpcapable(dwc_otg_core_if_t * core_if, uint32_t val)
6906 {
6907         gusbcfg_data_t usbcfg;
6908         usbcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
6909         usbcfg.b.srpcap = val;
6910         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, usbcfg.d32);
6911 }
6912
6913 uint32_t dwc_otg_get_devspeed(dwc_otg_core_if_t * core_if)
6914 {
6915         dcfg_data_t dcfg;
6916         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
6917         return dcfg.b.devspd;
6918 }
6919
6920 void dwc_otg_set_devspeed(dwc_otg_core_if_t * core_if, uint32_t val)
6921 {
6922         dcfg_data_t dcfg;
6923         dcfg.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dcfg);
6924         dcfg.b.devspd = val;
6925         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dcfg, dcfg.d32);
6926 }
6927
6928 uint32_t dwc_otg_get_busconnected(dwc_otg_core_if_t * core_if)
6929 {
6930         hprt0_data_t hprt0;
6931         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6932         return hprt0.b.prtconnsts;
6933 }
6934
6935 uint32_t dwc_otg_get_enumspeed(dwc_otg_core_if_t * core_if)
6936 {
6937         dsts_data_t dsts;
6938         dsts.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dsts);
6939         return dsts.b.enumspd;
6940 }
6941
6942 uint32_t dwc_otg_get_prtpower(dwc_otg_core_if_t * core_if)
6943 {
6944         hprt0_data_t hprt0;
6945         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6946         return hprt0.b.prtpwr;
6947
6948 }
6949
6950 uint32_t dwc_otg_get_core_state(dwc_otg_core_if_t * core_if)
6951 {
6952         return core_if->hibernation_suspend;
6953 }
6954
6955 void dwc_otg_set_prtpower(dwc_otg_core_if_t * core_if, uint32_t val)
6956 {
6957         hprt0_data_t hprt0;
6958         hprt0.d32 = dwc_otg_read_hprt0(core_if);
6959         hprt0.b.prtpwr = val;
6960         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
6961 }
6962
6963 uint32_t dwc_otg_get_prtsuspend(dwc_otg_core_if_t * core_if)
6964 {
6965         hprt0_data_t hprt0;
6966         hprt0.d32 = DWC_READ_REG32(core_if->host_if->hprt0);
6967         return hprt0.b.prtsusp;
6968
6969 }
6970
6971 void dwc_otg_set_prtsuspend(dwc_otg_core_if_t * core_if, uint32_t val)
6972 {
6973         hprt0_data_t hprt0;
6974         hprt0.d32 = dwc_otg_read_hprt0(core_if);
6975         hprt0.b.prtsusp = val;
6976         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
6977 }
6978
6979 uint32_t dwc_otg_get_fr_interval(dwc_otg_core_if_t * core_if)
6980 {
6981         hfir_data_t hfir;
6982         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
6983         return hfir.b.frint;
6984
6985 }
6986
6987 void dwc_otg_set_fr_interval(dwc_otg_core_if_t * core_if, uint32_t val)
6988 {
6989         hfir_data_t hfir;
6990         uint32_t fram_int;
6991         fram_int = calc_frame_interval(core_if);
6992         hfir.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hfir);
6993         if (!core_if->core_params->reload_ctl) {
6994                 DWC_WARN("\nCannot reload HFIR register.HFIR.HFIRRldCtrl bit is"
6995                          "not set to 1.\nShould load driver with reload_ctl=1"
6996                          " module parameter\n");
6997                 return;
6998         }
6999         switch (fram_int) {
7000         case 3750:
7001                 if ((val < 3350) || (val > 4150)) {
7002                         DWC_WARN("HFIR interval for HS core and 30 MHz"
7003                                  "clock freq should be from 3350 to 4150\n");
7004                         return;
7005                 }
7006                 break;
7007         case 30000:
7008                 if ((val < 26820) || (val > 33180)) {
7009                         DWC_WARN("HFIR interval for FS/LS core and 30 MHz"
7010                                  "clock freq should be from 26820 to 33180\n");
7011                         return;
7012                 }
7013                 break;
7014         case 6000:
7015                 if ((val < 5360) || (val > 6640)) {
7016                         DWC_WARN("HFIR interval for HS core and 48 MHz"
7017                                  "clock freq should be from 5360 to 6640\n");
7018                         return;
7019                 }
7020                 break;
7021         case 48000:
7022                 if ((val < 42912) || (val > 53088)) {
7023                         DWC_WARN("HFIR interval for FS/LS core and 48 MHz"
7024                                  "clock freq should be from 42912 to 53088\n");
7025                         return;
7026                 }
7027                 break;
7028         case 7500:
7029                 if ((val < 6700) || (val > 8300)) {
7030                         DWC_WARN("HFIR interval for HS core and 60 MHz"
7031                                  "clock freq should be from 6700 to 8300\n");
7032                         return;
7033                 }
7034                 break;
7035         case 60000:
7036                 if ((val < 53640) || (val > 65536)) {
7037                         DWC_WARN("HFIR interval for FS/LS core and 60 MHz"
7038                                  "clock freq should be from 53640 to 65536\n");
7039                         return;
7040                 }
7041                 break;
7042         default:
7043                 DWC_WARN("Unknown frame interval\n");
7044                 return;
7045                 break;
7046
7047         }
7048         hfir.b.frint = val;
7049         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hfir, hfir.d32);
7050 }
7051
7052 uint32_t dwc_otg_get_mode_ch_tim(dwc_otg_core_if_t * core_if)
7053 {
7054         hcfg_data_t hcfg;
7055         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7056         return hcfg.b.modechtimen;
7057
7058 }
7059
7060 void dwc_otg_set_mode_ch_tim(dwc_otg_core_if_t * core_if, uint32_t val)
7061 {
7062         hcfg_data_t hcfg;
7063         hcfg.d32 = DWC_READ_REG32(&core_if->host_if->host_global_regs->hcfg);
7064         hcfg.b.modechtimen = val;
7065         DWC_WRITE_REG32(&core_if->host_if->host_global_regs->hcfg, hcfg.d32);
7066 }
7067
7068 void dwc_otg_set_prtresume(dwc_otg_core_if_t * core_if, uint32_t val)
7069 {
7070         hprt0_data_t hprt0;
7071         hprt0.d32 = dwc_otg_read_hprt0(core_if);
7072         hprt0.b.prtres = val;
7073         DWC_WRITE_REG32(core_if->host_if->hprt0, hprt0.d32);
7074 }
7075
7076 uint32_t dwc_otg_get_remotewakesig(dwc_otg_core_if_t * core_if)
7077 {
7078         dctl_data_t dctl;
7079         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7080         return dctl.b.rmtwkupsig;
7081 }
7082
7083 uint32_t dwc_otg_get_beslreject(dwc_otg_core_if_t * core_if)
7084 {
7085         dctl_data_t dctl;
7086         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7087         return dctl.b.besl_reject;
7088 }
7089
7090 void dwc_otg_set_beslreject(dwc_otg_core_if_t * core_if, uint32_t val)
7091 {
7092     dctl_data_t dctl;
7093         dctl.d32 = DWC_READ_REG32(&core_if->dev_if->dev_global_regs->dctl);
7094         dctl.b.besl_reject = val;
7095         DWC_WRITE_REG32(&core_if->dev_if->dev_global_regs->dctl, dctl.d32);
7096 }
7097 uint32_t dwc_otg_get_hirdthresh(dwc_otg_core_if_t * core_if)
7098 {
7099         glpmcfg_data_t lpmcfg;
7100         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7101         return lpmcfg.b.hird_thres;
7102 }
7103
7104 void dwc_otg_set_hirdthresh(dwc_otg_core_if_t * core_if, uint32_t val)
7105 {
7106         glpmcfg_data_t lpmcfg;
7107
7108         if (DWC_OTG_PARAM_TEST(val, 0, 15)) {
7109                 DWC_WARN("Wrong valaue for hird_thres\n");
7110                 DWC_WARN("hird_thres must be 0-f\n");
7111                 return ;
7112         }
7113
7114         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7115         lpmcfg.b.hird_thres |= val;
7116         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7117 }
7118
7119 uint32_t dwc_otg_get_lpm_portsleepstatus(dwc_otg_core_if_t * core_if)
7120 {
7121         glpmcfg_data_t lpmcfg;
7122         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7123
7124         DWC_ASSERT(!
7125                    ((core_if->lx_state == DWC_OTG_L1) ^ lpmcfg.b.prt_sleep_sts),
7126                    "lx_state = %d, lmpcfg.prt_sleep_sts = %d\n",
7127                    core_if->lx_state, lpmcfg.b.prt_sleep_sts);
7128
7129         return lpmcfg.b.prt_sleep_sts;
7130 }
7131
7132 uint32_t dwc_otg_get_lpm_remotewakeenabled(dwc_otg_core_if_t * core_if)
7133 {
7134         glpmcfg_data_t lpmcfg;
7135         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7136         return lpmcfg.b.rem_wkup_en;
7137 }
7138
7139 uint32_t dwc_otg_get_lpmresponse(dwc_otg_core_if_t * core_if)
7140 {
7141         glpmcfg_data_t lpmcfg;
7142         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7143         return lpmcfg.b.appl_resp;
7144 }
7145
7146 void dwc_otg_set_lpmresponse(dwc_otg_core_if_t * core_if, uint32_t val)
7147 {
7148         glpmcfg_data_t lpmcfg;
7149         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7150         lpmcfg.b.appl_resp = val;
7151         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7152 }
7153
7154 uint32_t dwc_otg_get_hsic_connect(dwc_otg_core_if_t * core_if)
7155 {
7156         glpmcfg_data_t lpmcfg;
7157         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7158         return lpmcfg.b.hsic_connect;
7159 }
7160
7161 void dwc_otg_set_hsic_connect(dwc_otg_core_if_t * core_if, uint32_t val)
7162 {
7163         glpmcfg_data_t lpmcfg;
7164         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7165         lpmcfg.b.hsic_connect = val;
7166         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7167 }
7168
7169 uint32_t dwc_otg_get_inv_sel_hsic(dwc_otg_core_if_t * core_if)
7170 {
7171         glpmcfg_data_t lpmcfg;
7172         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7173         return lpmcfg.b.inv_sel_hsic;
7174
7175 }
7176
7177 void dwc_otg_set_inv_sel_hsic(dwc_otg_core_if_t * core_if, uint32_t val)
7178 {
7179         glpmcfg_data_t lpmcfg;
7180         lpmcfg.d32 = DWC_READ_REG32(&core_if->core_global_regs->glpmcfg);
7181         lpmcfg.b.inv_sel_hsic = val;
7182         DWC_WRITE_REG32(&core_if->core_global_regs->glpmcfg, lpmcfg.d32);
7183 }
7184
7185 uint32_t dwc_otg_get_gotgctl(dwc_otg_core_if_t * core_if)
7186 {
7187         return DWC_READ_REG32(&core_if->core_global_regs->gotgctl);
7188 }
7189
7190 void dwc_otg_set_gotgctl(dwc_otg_core_if_t * core_if, uint32_t val)
7191 {
7192         DWC_WRITE_REG32(&core_if->core_global_regs->gotgctl, val);
7193 }
7194
7195 uint32_t dwc_otg_get_gusbcfg(dwc_otg_core_if_t * core_if)
7196 {
7197         return DWC_READ_REG32(&core_if->core_global_regs->gusbcfg);
7198 }
7199
7200 void dwc_otg_set_gusbcfg(dwc_otg_core_if_t * core_if, uint32_t val)
7201 {
7202         DWC_WRITE_REG32(&core_if->core_global_regs->gusbcfg, val);
7203 }
7204
7205 uint32_t dwc_otg_get_grxfsiz(dwc_otg_core_if_t * core_if)
7206 {
7207         return DWC_READ_REG32(&core_if->core_global_regs->grxfsiz);
7208 }
7209
7210 void dwc_otg_set_grxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
7211 {
7212         DWC_WRITE_REG32(&core_if->core_global_regs->grxfsiz, val);
7213 }
7214
7215 uint32_t dwc_otg_get_gnptxfsiz(dwc_otg_core_if_t * core_if)
7216 {
7217         return DWC_READ_REG32(&core_if->core_global_regs->gnptxfsiz);
7218 }
7219
7220 void dwc_otg_set_gnptxfsiz(dwc_otg_core_if_t * core_if, uint32_t val)
7221 {
7222         DWC_WRITE_REG32(&core_if->core_global_regs->gnptxfsiz, val);
7223 }
7224
7225 uint32_t dwc_otg_get_gpvndctl(dwc_otg_core_if_t * core_if)
7226 {
7227         return DWC_READ_REG32(&core_if->core_global_regs->gpvndctl);
7228 }
7229
7230 void dwc_otg_set_gpvndctl(dwc_otg_core_if_t * core_if, uint32_t val)
7231 {
7232         DWC_WRITE_REG32(&core_if->core_global_regs->gpvndctl, val);
7233 }
7234
7235 uint32_t dwc_otg_get_ggpio(dwc_otg_core_if_t * core_if)
7236 {
7237         return DWC_READ_REG32(&core_if->core_global_regs->ggpio);
7238 }
7239
7240 void dwc_otg_set_ggpio(dwc_otg_core_if_t * core_if, uint32_t val)
7241 {
7242         DWC_WRITE_REG32(&core_if->core_global_regs->ggpio, val);
7243 }
7244
7245 uint32_t dwc_otg_get_hprt0(dwc_otg_core_if_t * core_if)
7246 {
7247         return DWC_READ_REG32(core_if->host_if->hprt0);
7248
7249 }
7250
7251 void dwc_otg_set_hprt0(dwc_otg_core_if_t * core_if, uint32_t val)
7252 {
7253         DWC_WRITE_REG32(core_if->host_if->hprt0, val);
7254 }
7255
7256 uint32_t dwc_otg_get_guid(dwc_otg_core_if_t * core_if)
7257 {
7258         return DWC_READ_REG32(&core_if->core_global_regs->guid);
7259 }
7260
7261 void dwc_otg_set_guid(dwc_otg_core_if_t * core_if, uint32_t val)
7262 {
7263         DWC_WRITE_REG32(&core_if->core_global_regs->guid, val);
7264 }
7265
7266 uint32_t dwc_otg_get_hptxfsiz(dwc_otg_core_if_t * core_if)
7267 {
7268         return DWC_READ_REG32(&core_if->core_global_regs->hptxfsiz);
7269 }
7270
7271 uint16_t dwc_otg_get_otg_version(dwc_otg_core_if_t * core_if)
7272 {
7273         return ((core_if->otg_ver == 1) ? (uint16_t)0x0200 : (uint16_t)0x0103);
7274 }
7275
7276 /**
7277  * Start the SRP timer to detect when the SRP does not complete within
7278  * 6 seconds.
7279  *
7280  * @param core_if the pointer to core_if strucure.
7281  */
7282 void dwc_otg_pcd_start_srp_timer(dwc_otg_core_if_t * core_if)
7283 {
7284         core_if->srp_timer_started = 1;
7285         DWC_TIMER_SCHEDULE(core_if->srp_timer, 6000 /* 6 secs */ );
7286 }
7287
7288 void dwc_otg_initiate_srp(void * p)
7289 {
7290         dwc_otg_core_if_t * core_if = p;
7291         uint32_t *addr = (uint32_t *) & (core_if->core_global_regs->gotgctl);
7292         gotgctl_data_t mem;
7293         gotgctl_data_t val;
7294
7295         val.d32 = DWC_READ_REG32(addr);
7296         if (val.b.sesreq) {
7297                 DWC_ERROR("Session Request Already active!\n");
7298                 return;
7299         }
7300
7301         DWC_INFO("Session Request Initated\n"); //NOTICE
7302         mem.d32 = DWC_READ_REG32(addr);
7303         mem.b.sesreq = 1;
7304         DWC_WRITE_REG32(addr, mem.d32);
7305
7306         /* Start the SRP timer */
7307         dwc_otg_pcd_start_srp_timer(core_if);
7308         return;
7309 }
7310
7311 int dwc_otg_check_haps_status(dwc_otg_core_if_t * core_if)
7312 {
7313    int retval = 0;
7314
7315    if(DWC_READ_REG32(&core_if->core_global_regs->gsnpsid) == 0xffffffff)
7316    {
7317                 return -1;
7318    } else {
7319                 return retval;
7320    }
7321
7322 }