drivers/usb/dwc_otg/dwc_otg_hcd_intr.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $
   3  * $Revision: #7 $
   4  * $Date: 2005/11/02 $
   5  * $Change: 553126 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 #include "dwc_otg_driver.h"
  36 #include "dwc_otg_hcd.h"
  37 #include "dwc_otg_regs.h"
  38 int csplit_nak = 0;
  39 /** @file
  40  * This file contains the implementation of the HCD Interrupt handlers.
  41  */
  42
  43 /** This function handles interrupts for the HCD. */
  44 int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
  45 {
  46         int retval = 0;
  47
  48         dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if;
  49         gintsts_data_t gintsts;
  50 #ifdef DEBUG
  51         dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs;
  52 #endif
  53
  54         /* Check if HOST Mode */
  55         if (dwc_otg_is_host_mode(core_if)) {
  56                 gintsts.d32 = dwc_otg_read_core_intr(core_if);
  57                 if (!gintsts.d32) {
  58 //                      DWC_PRINT("%s,GINTSTS = 0\n",__func__);
  59                         return 0;
  60                 }
  61
  62 #ifdef DEBUG
  63                 /* Don't print debug message in the interrupt handler on SOF */
  64 #  ifndef DEBUG_SOF
  65                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  66 #  endif
  67                         DWC_DEBUGPL (DBG_HCD, "\n");
  68 #endif
  69
  70 #ifdef DEBUG
  71 #  ifndef DEBUG_SOF
  72                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
  73 #  endif
  74                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected "
  75                                     "gintsts&gintmsk=0x%08x\n",
  76                                     gintsts.d32);
  77 #endif
  78
  79                 if (gintsts.b.sofintr) {
  80                         retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd);
  81                 }
  82                 if (gintsts.b.rxstsqlvl) {
  83                         retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd);
  84                 }
  85                 if (gintsts.b.nptxfempty) {
  86                         retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd);
  87                 }
  88                 if (gintsts.b.i2cintr) {
  89                         /** @todo Implement i2cintr handler. */
  90                 }
  91                 if (gintsts.b.portintr) {
  92                         retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd);
  93                 }
  94                 if (gintsts.b.hcintr) {
  95                         retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd);
  96                 }
  97                 if (gintsts.b.ptxfempty) {
  98                         retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd);
  99                 }
 100 #ifdef DEBUG
 101 #  ifndef DEBUG_SOF
 102                 if (gintsts.d32 != DWC_SOF_INTR_MASK)
 103 #  endif
 104                 {
 105                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n");
 106                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n",
 107                                     dwc_read_reg32(&global_regs->gintsts));
 108                         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n",
 109                                     dwc_read_reg32(&global_regs->gintmsk));
 110                 }
 111 #endif
 112
 113 #ifdef DEBUG
 114 #  ifndef DEBUG_SOF
 115         if (gintsts.d32 != DWC_SOF_INTR_MASK)
 116 #  endif
 117                 DWC_DEBUGPL (DBG_HCD, "\n");
 118 #endif
 119
 120         }
 121
 122         return retval;
 123 }
 124
 125 #ifdef DWC_TRACK_MISSED_SOFS
 126 #warning Compiling code to track missed SOFs
 127 #define FRAME_NUM_ARRAY_SIZE 1000
 128 /**
 129  * This function is for debug only.
 130  */
 131 static inline void track_missed_sofs(uint16_t _curr_frame_number) {
 132         static uint16_t         frame_num_array[FRAME_NUM_ARRAY_SIZE];
 133         static uint16_t         last_frame_num_array[FRAME_NUM_ARRAY_SIZE];
 134         static int              frame_num_idx = 0;
 135         static uint16_t         last_frame_num = DWC_HFNUM_MAX_FRNUM;
 136         static int              dumped_frame_num_array = 0;
 137
 138         if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
 139                 if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) {
 140                         frame_num_array[frame_num_idx] = _curr_frame_number;
 141                         last_frame_num_array[frame_num_idx++] = last_frame_num;
 142                 }
 143         } else if (!dumped_frame_num_array) {
 144                 int i;
 145                 printk(KERN_EMERG USB_DWC "Frame     Last Frame\n");
 146                 printk(KERN_EMERG USB_DWC "-----     ----------\n");
 147                 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
 148                         printk(KERN_EMERG USB_DWC "0x%04x    0x%04x\n",
 149                                frame_num_array[i], last_frame_num_array[i]);
 150                 }
 151                 dumped_frame_num_array = 1;
 152         }
 153         last_frame_num = _curr_frame_number;
 154 }
 155 #endif
 156
 157 /**
 158  * Handles the start-of-frame interrupt in host mode. Non-periodic
 159  * transactions may be queued to the DWC_otg controller for the current
 160  * (micro)frame. Periodic transactions may be queued to the controller for the
 161  * next (micro)frame.
 162  */
 163 int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd)
 164 {
 165         hfnum_data_t            hfnum;
 166         struct list_head        *qh_entry;
 167         dwc_otg_qh_t            *qh;
 168         dwc_otg_qtd_t           *qtd;
 169         dwc_otg_transaction_type_e tr_type;
 170         gintsts_data_t gintsts = {.d32 = 0};
 171
 172         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
 173
 174 #ifdef DEBUG_SOF
 175         DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n");
 176 #endif
 177
 178         _hcd->frame_number = hfnum.b.frnum;
 179
 180 #ifdef DEBUG
 181         _hcd->frrem_accum += hfnum.b.frrem;
 182         _hcd->frrem_samples++;
 183 #endif
 184
 185 #ifdef DWC_TRACK_MISSED_SOFS
 186         track_missed_sofs(_hcd->frame_number);
 187 #endif
 188
 189         /* Determine whether any periodic QHs should be executed. */
 190         qh_entry = _hcd->periodic_sched_inactive.next;
 191         while (qh_entry != &_hcd->periodic_sched_inactive) {
 192                 qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
 193                 if(qh->qh_state != QH_INACTIVE){
 194                 qh_entry = qh_entry->next;
 195                 continue;
 196                 }
 197                 qh_entry = qh_entry->next;
 198                 if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) {
 199                     #if 1
 200                         /* yk@rk 20100514
 201                          * fix bug for alcro hub
 202                          * do not send csplit after start_split_frame+4
 203                          */
 204                         qtd = list_entry(qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
 205                         if((qh->do_split)&&dwc_frame_num_gt(_hcd->frame_number,
 206                                 dwc_frame_num_inc(qh->start_split_frame, 4))&&(qtd->complete_split))
 207                         {
 208                             DWC_PRINT("frame_number 0x%x, start 0x%x, complete: %x",
 209                                 _hcd->frame_number, qh->start_split_frame, qtd->complete_split);
 210                                 qtd->complete_split = 0;
 211
 212                                 qh->sched_frame = dwc_frame_num_inc(qh->start_split_frame,
 213                                                                      qh->interval);
 214                                 if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) {
 215                                         qh->sched_frame = _hcd->frame_number;
 216                                 }
 217                                 qh->sched_frame |= 0x7;
 218                                 qh->start_split_frame = qh->sched_frame;
 219                         }
 220                         else
 221                         #endif
 222                         {
 223                                 /*
 224                                  * Move QH to the ready list to be executed next
 225                                  * (micro)frame.
 226                                  */
 227                                 //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_ready);
 228                     qh->qh_state = QH_READY;
 229                         }
 230                 }
 231         }
 232
 233         tr_type = dwc_otg_hcd_select_transactions(_hcd);
 234         if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 235                 dwc_otg_hcd_queue_transactions(_hcd, tr_type);
 236 #if 1
 237         } else if (list_empty(&_hcd->periodic_sched_inactive) //&&
 238 //                 list_empty(&_hcd->periodic_sched_ready) &&
 239 //                 list_empty(&_hcd->periodic_sched_assigned) &&
 240 //                 list_empty(&_hcd->periodic_sched_queued)
 241             ) {
 242                 /*
 243                  * We don't have USB data to send. Unfortunately the
 244                  * Synopsis block continues to generate interrupts at
 245                  * about 8k/sec. In order not waste time on these
 246                  * useless interrupts, we're going to disable the SOF
 247                  * interrupt. It will be re-enabled when a new packet
 248                  * is enqueued in dwc_otg_hcd_urb_enqueue()
 249                  */
 250                 dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
 251                                  DWC_SOF_INTR_MASK, 0);
 252 #endif
 253         }
 254
 255         /* Clear interrupt */
 256         gintsts.b.sofintr = 1;
 257         dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32);
 258
 259         return 1;
 260 }
 261
 262 /** Handles the Rx Status Queue Level Interrupt, which indicates that there is at
 263  * least one packet in the Rx FIFO.  The packets are moved from the FIFO to
 264  * memory if the DWC_otg controller is operating in Slave mode. */
 265 int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
 266 {
 267         host_grxsts_data_t grxsts;
 268         dwc_hc_t *hc = NULL;
 269
 270         DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n");
 271
 272         grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp);
 273
 274         hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum];
 275
 276         /* Packet Status */
 277         DWC_DEBUGPL(DBG_HCDV, "    Ch num = %d\n", grxsts.b.chnum);
 278         DWC_DEBUGPL(DBG_HCDV, "    Count = %d\n", grxsts.b.bcnt);
 279         DWC_DEBUGPL(DBG_HCDV, "    DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start);
 280         DWC_DEBUGPL(DBG_HCDV, "    PStatus = %d\n", grxsts.b.pktsts);
 281
 282         switch (grxsts.b.pktsts) {
 283         case DWC_GRXSTS_PKTSTS_IN:
 284                 /* Read the data into the host buffer. */
 285                 if (grxsts.b.bcnt > 0) {
 286                         dwc_otg_read_packet(_dwc_otg_hcd->core_if,
 287                                             hc->xfer_buff,
 288                                             grxsts.b.bcnt);
 289
 290                         /* Update the HC fields for the next packet received. */
 291                         hc->xfer_count += grxsts.b.bcnt;
 292                         hc->xfer_buff += grxsts.b.bcnt;
 293                 }
 294
 295         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
 296         case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR:
 297         case DWC_GRXSTS_PKTSTS_CH_HALTED:
 298                 /* Handled in interrupt, just ignore data */
 299                 break;
 300         default:
 301                 DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts);
 302                 break;
 303         }
 304
 305         return 1;
 306 }
 307
 308 /** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
 309  * data packets may be written to the FIFO for OUT transfers. More requests
 310  * may be written to the non-periodic request queue for IN transfers. This
 311  * interrupt is enabled only in Slave mode. */
 312 int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
 313 {
 314         DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n");
 315         dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
 316                                        DWC_OTG_TRANSACTION_NON_PERIODIC);
 317         return 1;
 318 }
 319
 320 /** This interrupt occurs when the periodic Tx FIFO is half-empty. More data
 321  * packets may be written to the FIFO for OUT transfers. More requests may be
 322  * written to the periodic request queue for IN transfers. This interrupt is
 323  * enabled only in Slave mode. */
 324 int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
 325 {
 326         DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n");
 327         dwc_otg_hcd_queue_transactions(_dwc_otg_hcd,
 328                                        DWC_OTG_TRANSACTION_PERIODIC);
 329         return 1;
 330 }
 331
 332 /** There are multiple conditions that can cause a port interrupt. This function
 333  * determines which interrupt conditions have occurred and handles them
 334  * appropriately. */
 335 int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
 336 {
 337         int retval = 0;
 338         hprt0_data_t hprt0;
 339         hprt0_data_t hprt0_modify;
 340
 341         hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
 342         hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0);
 343
 344         /* Clear appropriate bits in HPRT0 to clear the interrupt bit in
 345          * GINTSTS */
 346
 347         hprt0_modify.b.prtena = 0;
 348         hprt0_modify.b.prtconndet = 0;
 349         hprt0_modify.b.prtenchng = 0;
 350         hprt0_modify.b.prtovrcurrchng = 0;
 351
 352         /* Port Connect Detected
 353          * Set flag and clear if detected */
 354         if (hprt0.b.prtconndet) {
 355                 DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x "
 356                             "Port Connect Detected--\n", hprt0.d32);
 357                 _dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 358                 _dwc_otg_hcd->flags.b.port_connect_status = 1;
 359                 hprt0_modify.b.prtconndet = 1;
 360
 361                 /* B-Device has connected, Delete the connection timer.  */
 362 //                del_timer( &_dwc_otg_hcd->conn_timer );
 363
 364                 /* The Hub driver asserts a reset when it sees port connect
 365                  * status change flag */
 366                 retval |= 1;
 367         }
 368
 369         /* Port Enable Changed
 370          * Clear if detected - Set internal flag if disabled */
 371         if (hprt0.b.prtenchng) {
 372                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 373                             "Port Enable Changed--\n", hprt0.d32);
 374                 hprt0_modify.b.prtenchng = 1;
 375                 if (hprt0.b.prtena == 1) {
 376                         int do_reset = 0;
 377                         dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params;
 378                         dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs;
 379                         dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if;
 380
 381                         /* Check if we need to adjust the PHY clock speed for
 382                          * low power and adjust it */
 383                         /*yk @rk 20110525*/
 384                         /*fix bug usb host 1.1 with low-speed*/
 385                         if (params->host_support_fs_ls_low_power)
 386                         {
 387                                 gusbcfg_data_t usbcfg;
 388
 389                                 usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg);
 390
 391                                 if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ||
 392                                     (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED))
 393                                 {
 394                                         /*
 395                                          * Low power
 396                                          */
 397                                         hcfg_data_t hcfg;
 398                                         #if 0
 399                                         if (usbcfg.b.phylpwrclksel == 0) {
 400                                                 /* Set PHY low power clock select for FS/LS devices */
 401                                                 usbcfg.b.phylpwrclksel = 1;
 402                                                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
 403                                                 do_reset = 1;
 404                                         }
 405                                         #endif
 406
 407                                         hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg);
 408
 409                                         if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) &&
 410                                             (params->host_ls_low_power_phy_clk ==
 411                                              DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ))
 412                                         {
 413                                                 /* 6 MHZ */
 414                                                 DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n");
 415                                                 if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) {
 416                                                         hcfg.b.fslspclksel = DWC_HCFG_6_MHZ;
 417                                                         dwc_write_reg32(&host_if->host_global_regs->hcfg,
 418                                                                         hcfg.d32);
 419                             dwc_write_reg32(&host_if->host_global_regs->hfir, 0x1770);
 420                                                         do_reset = 1;
 421                                                 }
 422                                         }
 423                                         else {
 424                                                 /* 48 MHZ */
 425                                                 DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n");
 426                                                 if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) {
 427                                                         hcfg.b.fslspclksel = DWC_HCFG_48_MHZ;
 428                                                         dwc_write_reg32(&host_if->host_global_regs->hcfg,
 429                                                                         hcfg.d32);
 430                             dwc_write_reg32(&host_if->host_global_regs->hfir, 0xea60);
 431                                                         do_reset = 1;
 432                                                 }
 433                                         }
 434                                 }
 435                                 else {
 436                                         /*
 437                                          * Not low power
 438                                          */
 439                                         if (usbcfg.b.phylpwrclksel == 1) {
 440                                                 usbcfg.b.phylpwrclksel = 0;
 441                                                 dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32);
 442                                                 do_reset = 1;
 443                                         }
 444                                 }
 445
 446                                 if (do_reset) {
 447                                         tasklet_schedule(_dwc_otg_hcd->reset_tasklet);
 448                                 }
 449                         }
 450
 451                         if (!do_reset) {
 452                                 /* Port has been enabled set the reset change flag */
 453                                 _dwc_otg_hcd->flags.b.port_reset_change = 1;
 454                         }
 455
 456                 } else {
 457                         _dwc_otg_hcd->flags.b.port_enable_change = 1;
 458                 }
 459                 retval |= 1;
 460         }
 461
 462         /** Overcurrent Change Interrupt */
 463         if (hprt0.b.prtovrcurrchng) {
 464                 DWC_DEBUGPL(DBG_HCD, "  --Port Interrupt HPRT0=0x%08x "
 465                             "Port Overcurrent Changed--\n", hprt0.d32);
 466                 _dwc_otg_hcd->flags.b.port_over_current_change = 1;
 467                 hprt0_modify.b.prtovrcurrchng = 1;
 468                 retval |= 1;
 469         }
 470
 471         /* Clear Port Interrupts */
 472         dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32);
 473
 474         return retval;
 475 }
 476
 477
 478 /** This interrupt indicates that one or more host channels has a pending
 479  * interrupt. There are multiple conditions that can cause each host channel
 480  * interrupt. This function determines which conditions have occurred for each
 481  * host channel interrupt and handles them appropriately. */
 482 int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd)
 483 {
 484         int retval = 0;
 485         volatile haint_data_t haint;
 486         int hcnum;
 487         struct list_head        *qh_entry;
 488         dwc_otg_qh_t            *qh;
 489         int i;
 490
 491         /* Clear appropriate bits in HCINTn to clear the interrupt bit in
 492          * GINTSTS */
 493
 494         haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
 495 #if 0
 496         for (i = 0; i < _dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 497                 if (haint.b2.chint & (1 << i))
 498                         retval |= dwc_otg_hcd_handle_hc_n_intr(_dwc_otg_hcd, i);
 499         }
 500 #else
 501         /* yk@rk 20100511
 502          * USB Spec2.0 11.18.4
 503          * for all periodic endpoints that have split transactions scheduled within
 504          * a particular microframe, the host must issue complete-split transactions
 505          * in the same relative order as the corresponding start-split transactions
 506          * were issued.
 507          */
 508         qh_entry = _dwc_otg_hcd->periodic_sched_inactive.next;
 509         while (qh_entry != &_dwc_otg_hcd->periodic_sched_inactive) {
 510                 qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
 511                 qh_entry = qh_entry->next;
 512                 if(qh->qh_state != QH_QUEUED)
 513                 continue;
 514                 if(qh->channel == NULL){
 515                     DWC_PRINT("%s channel NULL 1\n", __func__);
 516                     break;
 517                 }
 518                 hcnum = qh->channel->hc_num;
 519                 if (haint.b2.chint & (1 << hcnum)) {
 520                         retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, hcnum);
 521                 }
 522         }
 523
 524         haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
 525         qh_entry = _dwc_otg_hcd->non_periodic_sched_active.next;
 526          while (&_dwc_otg_hcd->non_periodic_sched_active != qh_entry){
 527                 qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry);
 528                 qh_entry = qh_entry->next;
 529                 if(qh->channel == NULL){
 530                     DWC_PRINT("%s channel NULL 2\n", __func__);
 531                     break;
 532                 }
 533                 hcnum = qh->channel->hc_num;
 534                 if (haint.b2.chint & (1 << hcnum)) {
 535                         retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, hcnum);
 536                 }
 537         }
 538         haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if);
 539         for (i = 0; i < _dwc_otg_hcd->core_if->core_params->host_channels; i++) {
 540                 if (haint.b2.chint & (1 << i))
 541                         retval |= dwc_otg_hcd_handle_hc_n_intr(_dwc_otg_hcd, i);
 542         }
 543 #endif
 544         return retval;
 545 }
 546
 547 /* Macro used to clear one channel interrupt */
 548 #define clear_hc_int(_hc_regs_,_intr_) \
 549 do { \
 550         hcint_data_t hcint_clear = {.d32 = 0}; \
 551         hcint_clear.b._intr_ = 1; \
 552         dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \
 553 } while (0)
 554
 555 /*
 556  * Macro used to disable one channel interrupt. Channel interrupts are
 557  * disabled when the channel is halted or released by the interrupt handler.
 558  * There is no need to handle further interrupts of that type until the
 559  * channel is re-assigned. In fact, subsequent handling may cause crashes
 560  * because the channel structures are cleaned up when the channel is released.
 561  */
 562 #define disable_hc_int(_hc_regs_,_intr_) \
 563 do { \
 564         hcintmsk_data_t hcintmsk = {.d32 = 0}; \
 565         hcintmsk.b._intr_ = 1; \
 566         dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \
 567 } while (0)
 568
 569 /**
 570  * Gets the actual length of a transfer after the transfer halts. _halt_status
 571  * holds the reason for the halt.
 572  *
 573  * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE,
 574  * *_short_read is set to 1 upon return if less than the requested
 575  * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon
 576  * return. _short_read may also be NULL on entry, in which case it remains
 577  * unchanged.
 578  */
 579 static uint32_t get_actual_xfer_length(dwc_hc_t *_hc,
 580                                        dwc_otg_hc_regs_t *_hc_regs,
 581                                        dwc_otg_qtd_t *_qtd,
 582                                        dwc_otg_halt_status_e _halt_status,
 583                                        int *_short_read)
 584 {
 585         hctsiz_data_t   hctsiz;
 586         uint32_t        length;
 587
 588         if (_short_read != NULL) {
 589                 *_short_read = 0;
 590         }
 591         hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
 592
 593         if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) {
 594                 if (_hc->ep_is_in) {
 595                         length = _hc->xfer_len - hctsiz.b.xfersize;
 596                         if (_short_read != NULL) {
 597                                 *_short_read = (hctsiz.b.xfersize != 0);
 598                         }
 599                 } else if (_hc->qh->do_split) {
 600                         length = _qtd->ssplit_out_xfer_count;
 601                 } else {
 602                         length = _hc->xfer_len;
 603                 }
 604         } else {
 605                 /*
 606                  * Must use the hctsiz.pktcnt field to determine how much data
 607                  * has been transferred. This field reflects the number of
 608                  * packets that have been transferred via the USB. This is
 609                  * always an integral number of packets if the transfer was
 610                  * halted before its normal completion. (Can't use the
 611                  * hctsiz.xfersize field because that reflects the number of
 612                  * bytes transferred via the AHB, not the USB).
 613                  */
 614                 length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet;
 615         }
 616
 617         return length;
 618 }
 619
 620 /**
 621  * Updates the state of the URB after a Transfer Complete interrupt on the
 622  * host channel. Updates the actual_length field of the URB based on the
 623  * number of bytes transferred via the host channel. Sets the URB status
 624  * if the data transfer is finished.
 625  *
 626  * @return 1 if the data transfer specified by the URB is completely finished,
 627  * 0 otherwise.
 628  */
 629 static int update_urb_state_xfer_comp(dwc_hc_t *_hc,
 630                                       dwc_otg_hc_regs_t *_hc_regs,
 631                                       struct urb *_urb,
 632                                       dwc_otg_qtd_t *_qtd)
 633 {
 634         int             xfer_done = 0;
 635         int             short_read = 0;
 636
 637         _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd,
 638                                                       DWC_OTG_HC_XFER_COMPLETE,
 639                                                       &short_read);
 640
 641         if (short_read || (_urb->actual_length >= _urb->transfer_buffer_length)) {
 642                 xfer_done = 1;
 643                 if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) {
 644                         _urb->status = -EREMOTEIO;
 645                 }
 646                 else {
 647                         _urb->status = 0;
 648                 }
 649         }
 650
 651 #ifdef DEBUG
 652         {
 653                 hctsiz_data_t   hctsiz;
 654                 hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
 655                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
 656                             __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
 657                 DWC_DEBUGPL(DBG_HCDV, "  hc->xfer_len %d\n", _hc->xfer_len);
 658                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.xfersize %d\n", hctsiz.b.xfersize);
 659                 DWC_DEBUGPL(DBG_HCDV, "  urb->transfer_buffer_length %d\n",
 660                             _urb->transfer_buffer_length);
 661                 DWC_DEBUGPL(DBG_HCDV, "  urb->actual_length %d\n", _urb->actual_length);
 662                 DWC_DEBUGPL(DBG_HCDV, "  short_read %d, xfer_done %d\n",
 663                             short_read, xfer_done);
 664         }
 665 #endif
 666
 667         return xfer_done;
 668 }
 669
 670 /*
 671  * Save the starting data toggle for the next transfer. The data toggle is
 672  * saved in the QH for non-control transfers and it's saved in the QTD for
 673  * control transfers.
 674  */
 675 static void save_data_toggle(dwc_hc_t *_hc,
 676                              dwc_otg_hc_regs_t *_hc_regs,
 677                              dwc_otg_qtd_t *_qtd)
 678 {
 679         hctsiz_data_t hctsiz;
 680         hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
 681
 682         if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) {
 683                 dwc_otg_qh_t *qh = _hc->qh;
 684                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 685                         qh->data_toggle = DWC_OTG_HC_PID_DATA0;
 686                 } else {
 687                         qh->data_toggle = DWC_OTG_HC_PID_DATA1;
 688                 }
 689         } else {
 690                 if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) {
 691                         _qtd->data_toggle = DWC_OTG_HC_PID_DATA0;
 692                 } else {
 693                         _qtd->data_toggle = DWC_OTG_HC_PID_DATA1;
 694                 }
 695         }
 696 }
 697
 698 /**
 699  * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
 700  * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
 701  * still linked to the QH, the QH is added to the end of the inactive
 702  * non-periodic schedule. For periodic QHs, removes the QH from the periodic
 703  * schedule if no more QTDs are linked to the QH.
 704  */
 705 static void deactivate_qh(dwc_otg_hcd_t *_hcd,
 706                           dwc_otg_qh_t *_qh,
 707                           int free_qtd)
 708 {
 709         int continue_split = 0;
 710         dwc_otg_qtd_t *qtd;
 711
 712         DWC_DEBUGPL(DBG_HCDV, "  %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd);
 713
 714         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
 715
 716         if (qtd->complete_split) {
 717                 continue_split = 1;
 718         }
 719         else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) ||
 720                  (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END))
 721         {
 722                 continue_split = 1;
 723         }
 724
 725         if (free_qtd) {
 726                 dwc_otg_hcd_qtd_remove_and_free(qtd);
 727                 continue_split = 0;
 728         }
 729
 730         _qh->channel = NULL;
 731         _qh->qtd_in_process = NULL;
 732         dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split);
 733 }
 734
 735 /**
 736  * Updates the state of an Isochronous URB when the transfer is stopped for
 737  * any reason. The fields of the current entry in the frame descriptor array
 738  * are set based on the transfer state and the input _halt_status. Completes
 739  * the Isochronous URB if all the URB frames have been completed.
 740  *
 741  * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be
 742  * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE.
 743  */
 744 static dwc_otg_halt_status_e
 745 update_isoc_urb_state(dwc_otg_hcd_t *_hcd,
 746                       dwc_hc_t *_hc,
 747                       dwc_otg_hc_regs_t *_hc_regs,
 748                       dwc_otg_qtd_t *_qtd,
 749                       dwc_otg_halt_status_e _halt_status)
 750 {
 751         struct urb *urb = _qtd->urb;
 752         dwc_otg_halt_status_e ret_val = _halt_status;
 753         struct usb_iso_packet_descriptor *frame_desc;
 754
 755         frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index];
 756         switch (_halt_status) {
 757         case DWC_OTG_HC_XFER_COMPLETE:
 758                 frame_desc->status = 0;
 759                 frame_desc->actual_length =
 760                         get_actual_xfer_length(_hc, _hc_regs, _qtd,
 761                                                _halt_status, NULL);
 762                 break;
 763         case DWC_OTG_HC_XFER_FRAME_OVERRUN:
 764                 urb->error_count++;
 765                 if (_hc->ep_is_in) {
 766                         frame_desc->status = -ENOSR;
 767                 } else {
 768                         frame_desc->status = -ECOMM;
 769                 }
 770                 frame_desc->actual_length = 0;
 771                 break;
 772         case DWC_OTG_HC_XFER_BABBLE_ERR:
 773                 urb->error_count++;
 774                 frame_desc->status = -EOVERFLOW;
 775                 /* Don't need to update actual_length in this case. */
 776                 break;
 777         case DWC_OTG_HC_XFER_XACT_ERR:
 778                 urb->error_count++;
 779                 frame_desc->status = -EPROTO;
 780                 frame_desc->actual_length =
 781                         get_actual_xfer_length(_hc, _hc_regs, _qtd,
 782                                                _halt_status, NULL);
 783             break;
 784         default:
 785                 DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__,
 786                           _halt_status);
 787                 BUG();
 788                 break;
 789         }
 790
 791         if (++_qtd->isoc_frame_index == urb->number_of_packets) {
 792                 /*
 793                  * urb->status is not used for isoc transfers.
 794                  * The individual frame_desc statuses are used instead.
 795                  */
 796                 dwc_otg_hcd_complete_urb(_hcd, urb, 0);
 797                 ret_val = DWC_OTG_HC_XFER_URB_COMPLETE;
 798         } else {
 799                 ret_val = DWC_OTG_HC_XFER_COMPLETE;
 800         }
 801
 802         return ret_val;
 803 }
 804
 805 /**
 806  * Releases a host channel for use by other transfers. Attempts to select and
 807  * queue more transactions since at least one host channel is available.
 808  *
 809  * @param _hcd The HCD state structure.
 810  * @param _hc The host channel to release.
 811  * @param _qtd The QTD associated with the host channel. This QTD may be freed
 812  * if the transfer is complete or an error has occurred.
 813  * @param _halt_status Reason the channel is being released. This status
 814  * determines the actions taken by this function.
 815  */
 816 /*static */
 817 void release_channel(dwc_otg_hcd_t *_hcd,
 818                             dwc_hc_t *_hc,
 819                             dwc_otg_qtd_t *_qtd,
 820                             dwc_otg_halt_status_e _halt_status)
 821 {
 822         dwc_otg_transaction_type_e tr_type;
 823         int free_qtd;
 824         int continue_trans = 1;
 825     if(_halt_status != DWC_OTG_HC_XFER_URB_DEQUEUE){
 826         if(((uint32_t) _qtd & 0xf0000000)==0){
 827             DWC_PRINT("%s qtd %p, status %d\n", __func__, _qtd, _halt_status);
 828             goto cleanup;
 829         }
 830         if(((uint32_t) _qtd & 0x80000000)==0){
 831             DWC_PRINT("%s qtd %p, status %d 1\n", __func__, _qtd, _halt_status);
 832             goto cleanup;
 833         }
 834         if(((uint32_t) _qtd->urb & 0xf0000000)==0){
 835             DWC_PRINT("%s qtd %p urb %p, status %d\n", __func__, _qtd, _qtd->urb, _halt_status);
 836             goto cleanup;
 837         }
 838     }
 839
 840         DWC_DEBUGPL(DBG_HCDV, "  %s: channel %d, halt_status %d\n",
 841                     __func__, _hc->hc_num, _halt_status);
 842         switch (_halt_status) {
 843         case DWC_OTG_HC_XFER_URB_COMPLETE:
 844                 free_qtd = 1;
 845                 break;
 846         case DWC_OTG_HC_XFER_AHB_ERR:
 847         case DWC_OTG_HC_XFER_STALL:
 848         case DWC_OTG_HC_XFER_BABBLE_ERR:
 849                 free_qtd = 1;
 850                 break;
 851         case DWC_OTG_HC_XFER_XACT_ERR:
 852                 if (_qtd->error_count >= 3) {
 853                         DWC_DEBUGPL(DBG_HCDV, "  Complete URB with transaction error\n");
 854                         free_qtd = 1;
 855                         _qtd->urb->status = -EPROTO;
 856                         dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO);
 857                 } else {
 858                         free_qtd = 0;
 859                 }
 860                 break;
 861         case DWC_OTG_HC_XFER_URB_DEQUEUE:
 862                 /*
 863                  * The QTD has already been removed and the QH has been
 864                  * deactivated. Don't want to do anything except release the
 865                  * host channel and try to queue more transfers.
 866                  */
 867                 continue_trans = 0;
 868                 goto cleanup;
 869         case DWC_OTG_HC_XFER_NO_HALT_STATUS:
 870                 DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num);
 871                 free_qtd = 0;
 872                 break;
 873         default:
 874                 free_qtd = 0;
 875                 break;
 876         }
 877         if(csplit_nak)
 878         {
 879                 continue_trans = 0;
 880                 csplit_nak = 0;
 881         }
 882
 883
 884         deactivate_qh(_hcd, _hc->qh, free_qtd);
 885
 886  cleanup:
 887         /*
 888          * Release the host channel for use by other transfers. The cleanup
 889          * function clears the channel interrupt enables and conditions, so
 890          * there's no need to clear the Channel Halted interrupt separately.
 891          */
 892         dwc_otg_hc_cleanup(_hcd->core_if, _hc);
 893         list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list);
 894
 895         switch (_hc->ep_type) {
 896         case DWC_OTG_EP_TYPE_CONTROL:
 897         case DWC_OTG_EP_TYPE_BULK:
 898                 _hcd->non_periodic_channels--;
 899                 break;
 900
 901         default:
 902                 /*
 903                  * Don't release reservations for periodic channels here.
 904                  * That's done when a periodic transfer is descheduled (i.e.
 905                  * when the QH is removed from the periodic schedule).
 906                  */
 907                 break;
 908         }
 909         if(continue_trans)
 910         {
 911                 /* Try to queue more transfers now that there's a free channel. */
 912                 tr_type = dwc_otg_hcd_select_transactions(_hcd);
 913                 if (tr_type != DWC_OTG_TRANSACTION_NONE) {
 914                         dwc_otg_hcd_queue_transactions(_hcd, tr_type);
 915                 }
 916         }
 917         /*
 918          * Make sure the start of frame interrupt is enabled now that
 919          * we know we should have queued data. The SOF interrupt
 920          * handler automatically disables itself when idle to reduce
 921          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
 922          * for the disable
 923          */
 924         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, 0,
 925                          DWC_SOF_INTR_MASK);
 926 }
 927
 928 /**
 929  * Halts a host channel. If the channel cannot be halted immediately because
 930  * the request queue is full, this function ensures that the FIFO empty
 931  * interrupt for the appropriate queue is enabled so that the halt request can
 932  * be queued when there is space in the request queue.
 933  *
 934  * This function may also be called in DMA mode. In that case, the channel is
 935  * simply released since the core always halts the channel automatically in
 936  * DMA mode.
 937  */
 938 static void halt_channel(dwc_otg_hcd_t *_hcd,
 939                          dwc_hc_t *_hc,
 940                          dwc_otg_qtd_t *_qtd,
 941                          dwc_otg_halt_status_e _halt_status)
 942 {
 943         if (_hcd->core_if->dma_enable) {
 944                 release_channel(_hcd, _hc, _qtd, _halt_status);
 945                 return;
 946         }
 947
 948         /* Slave mode processing... */
 949         dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status);
 950
 951         if (_hc->halt_on_queue) {
 952                 gintmsk_data_t gintmsk = {.d32 = 0};
 953                 dwc_otg_core_global_regs_t *global_regs;
 954                 global_regs = _hcd->core_if->core_global_regs;
 955
 956                 if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL ||
 957                     _hc->ep_type == DWC_OTG_EP_TYPE_BULK) {
 958                         /*
 959                          * Make sure the Non-periodic Tx FIFO empty interrupt
 960                          * is enabled so that the non-periodic schedule will
 961                          * be processed.
 962                          */
 963                         gintmsk.b.nptxfempty = 1;
 964                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
 965                 } else {
 966                         /*
 967                          * Move the QH from the periodic queued schedule to
 968                          * the periodic assigned schedule. This allows the
 969                          * halt to be queued when the periodic schedule is
 970                          * processed.
 971                          */
 972                         //list_move_tail(&_hc->qh->qh_list_entry,
 973                         //        &_hcd->periodic_sched_assigned);
 974
 975                         /*
 976                          * Make sure the Periodic Tx FIFO Empty interrupt is
 977                          * enabled so that the periodic schedule will be
 978                          * processed.
 979                          */
 980                         gintmsk.b.ptxfempty = 1;
 981                         dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32);
 982                 }
 983         }
 984 }
 985
 986 /**
 987  * Performs common cleanup for non-periodic transfers after a Transfer
 988  * Complete interrupt. This function should be called after any endpoint type
 989  * specific handling is finished to release the host channel.
 990  */
 991 static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd,
 992                                        dwc_hc_t *_hc,
 993                                        dwc_otg_hc_regs_t *_hc_regs,
 994                                        dwc_otg_qtd_t *_qtd,
 995                                        dwc_otg_halt_status_e _halt_status)
 996 {
 997         hcint_data_t hcint;
 998
 999         _qtd->error_count = 0;
1000
1001         hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
1002         if (hcint.b.nyet) {
1003                 /*
1004                  * Got a NYET on the last transaction of the transfer. This
1005                  * means that the endpoint should be in the PING state at the
1006                  * beginning of the next transfer.
1007                  */
1008                 _hc->qh->ping_state = 1;
1009                 clear_hc_int(_hc_regs,nyet);
1010         }
1011
1012         /*
1013          * Always halt and release the host channel to make it available for
1014          * more transfers. There may still be more phases for a control
1015          * transfer or more data packets for a bulk transfer at this point,
1016          * but the host channel is still halted. A channel will be reassigned
1017          * to the transfer when the non-periodic schedule is processed after
1018          * the channel is released. This allows transactions to be queued
1019          * properly via dwc_otg_hcd_queue_transactions, which also enables the
1020          * Tx FIFO Empty interrupt if necessary.
1021          */
1022         if (_hc->ep_is_in) {
1023                 /*
1024                  * IN transfers in Slave mode require an explicit disable to
1025                  * halt the channel. (In DMA mode, this call simply releases
1026                  * the channel.)
1027                  */
1028                 halt_channel(_hcd, _hc, _qtd, _halt_status);
1029         } else {
1030                 /*
1031                  * The channel is automatically disabled by the core for OUT
1032                  * transfers in Slave mode.
1033                  */
1034                 release_channel(_hcd, _hc, _qtd, _halt_status);
1035         }
1036 }
1037
1038 /**
1039  * Performs common cleanup for periodic transfers after a Transfer Complete
1040  * interrupt. This function should be called after any endpoint type specific
1041  * handling is finished to release the host channel.
1042  */
1043 static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd,
1044                                    dwc_hc_t *_hc,
1045                                    dwc_otg_hc_regs_t *_hc_regs,
1046                                    dwc_otg_qtd_t *_qtd,
1047                                    dwc_otg_halt_status_e _halt_status)
1048 {
1049         hctsiz_data_t hctsiz;
1050         _qtd->error_count = 0;
1051
1052         hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
1053         if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) {
1054                 /* Core halts channel in these cases. */
1055                 release_channel(_hcd, _hc, _qtd, _halt_status);
1056         } else {
1057                 /* Flush any outstanding requests from the Tx queue. */
1058                 halt_channel(_hcd, _hc, _qtd, _halt_status);
1059         }
1060 }
1061
1062 /**
1063  * Handles a host channel Transfer Complete interrupt. This handler may be
1064  * called in either DMA mode or Slave mode.
1065  */
1066 static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd,
1067                                        dwc_hc_t *_hc,
1068                                        dwc_otg_hc_regs_t *_hc_regs,
1069                                        dwc_otg_qtd_t *_qtd)
1070 {
1071         int                     urb_xfer_done;
1072         dwc_otg_halt_status_e   halt_status = DWC_OTG_HC_XFER_COMPLETE;
1073         struct urb              *urb;
1074         int                     pipe_type;
1075
1076         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1077                     "Transfer Complete--\n", _hc->hc_num);
1078
1079         if(((uint32_t) _qtd & 0xf0000000)==0){
1080                 DWC_PRINT("%s qtd %p\n", __func__, _qtd);
1081                 release_channel(_hcd, _hc, _qtd, _hc->halt_status);
1082                 return 1;
1083         }
1084
1085         urb = _qtd->urb;
1086         if(((uint32_t)urb & 0xf0000000)==0){
1087                 DWC_PRINT("%s qtd %p, urb %p\n", __func__, _qtd, urb);
1088                 release_channel(_hcd, _hc, _qtd, _hc->halt_status);
1089                 return 1;
1090         }
1091
1092         /*
1093          * Handle xfer complete on CSPLIT.
1094          */
1095         if (_hc->qh->do_split) {
1096                 _qtd->complete_split = 0;
1097         }
1098
1099         pipe_type = usb_pipetype(urb->pipe);
1100         /* Update the QTD and URB states. */
1101         switch (pipe_type) {
1102         case PIPE_CONTROL:
1103                 switch (_qtd->control_phase) {
1104                 case DWC_OTG_CONTROL_SETUP:
1105                         if (urb->transfer_buffer_length > 0) {
1106                                 _qtd->control_phase = DWC_OTG_CONTROL_DATA;
1107                         } else {
1108                                 _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1109                         }
1110                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction done\n");
1111                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1112                         break;
1113                 case DWC_OTG_CONTROL_DATA: {
1114                         urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd);
1115                         if (urb_xfer_done) {
1116                                 _qtd->control_phase = DWC_OTG_CONTROL_STATUS;
1117                                 DWC_DEBUGPL(DBG_HCDV, "  Control data transfer done\n");
1118                         } else {
1119                                 save_data_toggle(_hc, _hc_regs, _qtd);
1120                         }
1121                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1122                         break;
1123                 }
1124                 case DWC_OTG_CONTROL_STATUS:
1125                         DWC_DEBUGPL(DBG_HCDV, "  Control transfer complete\n");
1126                         if (urb->status == -EINPROGRESS) {
1127                                 urb->status = 0;
1128                         }
1129                         dwc_otg_hcd_complete_urb(_hcd, urb, urb->status);
1130                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1131                         break;
1132                 }
1133
1134                 complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status);
1135                 break;
1136         case PIPE_BULK:
1137                 DWC_DEBUGPL(DBG_HCDV, "  Bulk transfer complete\n");
1138                 urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd);
1139                 if (urb_xfer_done) {
1140                         dwc_otg_hcd_complete_urb(_hcd, urb, urb->status);
1141                         halt_status = DWC_OTG_HC_XFER_URB_COMPLETE;
1142                 } else {
1143                         halt_status = DWC_OTG_HC_XFER_COMPLETE;
1144                 }
1145
1146                 save_data_toggle(_hc, _hc_regs, _qtd);
1147                 complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status);
1148                 break;
1149         case PIPE_INTERRUPT:
1150                 DWC_DEBUGPL(DBG_HCDV, "  Interrupt transfer complete\n");
1151                 urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd);
1152                 if(!urb_xfer_done){
1153                     save_data_toggle(_hc, _hc_regs, _qtd);
1154                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK);
1155                 break;
1156                 }
1157                 /*
1158                  * Interrupt URB is done on the first transfer complete
1159                  * interrupt.
1160                  */
1161                 dwc_otg_hcd_complete_urb(_hcd, urb, urb->status);
1162                 save_data_toggle(_hc, _hc_regs, _qtd);
1163                 complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,
1164                                        DWC_OTG_HC_XFER_URB_COMPLETE);
1165                 break;
1166         case PIPE_ISOCHRONOUS:
1167                 DWC_DEBUGPL(DBG_HCDV,  "  Isochronous transfer complete\n");
1168                 if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL)
1169                 {
1170                         halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
1171                                                             DWC_OTG_HC_XFER_COMPLETE);
1172                 }
1173                 complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status);
1174                 break;
1175         }
1176
1177         disable_hc_int(_hc_regs,xfercompl);
1178
1179         return 1;
1180 }
1181
1182 /**
1183  * Handles a host channel STALL interrupt. This handler may be called in
1184  * either DMA mode or Slave mode.
1185  */
1186 static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd,
1187                                     dwc_hc_t *_hc,
1188                                     dwc_otg_hc_regs_t *_hc_regs,
1189                                     dwc_otg_qtd_t *_qtd)
1190 {
1191         struct urb *urb = _qtd->urb;
1192         int pipe_type = usb_pipetype(urb->pipe);
1193
1194         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1195                     "STALL Received--\n", _hc->hc_num);
1196
1197         if (pipe_type == PIPE_CONTROL) {
1198                 dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
1199         }
1200
1201         if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) {
1202                 dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE);
1203                 /*
1204                  * USB protocol requires resetting the data toggle for bulk
1205                  * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1206                  * setup command is issued to the endpoint. Anticipate the
1207                  * CLEAR_FEATURE command since a STALL has occurred and reset
1208                  * the data toggle now.
1209                  */
1210                 _hc->qh->data_toggle = 0;
1211         }
1212
1213         halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL);
1214
1215         disable_hc_int(_hc_regs,stall);
1216
1217         return 1;
1218 }
1219
1220 /*
1221  * Updates the state of the URB when a transfer has been stopped due to an
1222  * abnormal condition before the transfer completes. Modifies the
1223  * actual_length field of the URB to reflect the number of bytes that have
1224  * actually been transferred via the host channel.
1225  */
1226 static void update_urb_state_xfer_intr(dwc_hc_t *_hc,
1227                                        dwc_otg_hc_regs_t *_hc_regs,
1228                                        struct urb *_urb,
1229                                        dwc_otg_qtd_t *_qtd,
1230                                        dwc_otg_halt_status_e _halt_status)
1231 {
1232         uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd,
1233                                                             _halt_status, NULL);
1234         _urb->actual_length += bytes_transferred;
1235
1236 #ifdef DEBUG
1237         {
1238                 hctsiz_data_t   hctsiz;
1239                 hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
1240                 DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n",
1241                             __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num);
1242                 DWC_DEBUGPL(DBG_HCDV, "  _hc->start_pkt_count %d\n", _hc->start_pkt_count);
1243                 DWC_DEBUGPL(DBG_HCDV, "  hctsiz.pktcnt %d\n", hctsiz.b.pktcnt);
1244                 DWC_DEBUGPL(DBG_HCDV, "  _hc->max_packet %d\n", _hc->max_packet);
1245                 DWC_DEBUGPL(DBG_HCDV, "  bytes_transferred %d\n", bytes_transferred);
1246                 DWC_DEBUGPL(DBG_HCDV, "  _urb->actual_length %d\n", _urb->actual_length);
1247                 DWC_DEBUGPL(DBG_HCDV, "  _urb->transfer_buffer_length %d\n",
1248                             _urb->transfer_buffer_length);
1249         }
1250 #endif
1251 }
1252
1253 /**
1254  * Handles a host channel NAK interrupt. This handler may be called in either
1255  * DMA mode or Slave mode.
1256  */
1257 static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd,
1258                                   dwc_hc_t *_hc,
1259                                   dwc_otg_hc_regs_t *_hc_regs,
1260                                   dwc_otg_qtd_t *_qtd)
1261 {
1262         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1263                     "NAK Received--\n", _hc->hc_num);
1264
1265         /*
1266          * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1267          * interrupt.  Re-start the SSPLIT transfer.
1268          */
1269         if (_hc->do_split) {
1270                 if (_hc->complete_split) {
1271                         _qtd->error_count = 0;
1272                 }
1273                 csplit_nak = 1;
1274                 _qtd->complete_split = 0;
1275                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK);
1276                 goto handle_nak_done;
1277         }
1278
1279         switch (usb_pipetype(_qtd->urb->pipe)) {
1280         case PIPE_CONTROL:
1281         case PIPE_BULK:
1282                 if (_hcd->core_if->dma_enable && _hc->ep_is_in) {
1283                         /*
1284                          * NAK interrupts are enabled on bulk/control IN
1285                          * transfers in DMA mode for the sole purpose of
1286                          * resetting the error count after a transaction error
1287                          * occurs. The core will continue transferring data.
1288                          */
1289                         _qtd->error_count = 0;
1290                         goto handle_nak_done;
1291                 }
1292
1293                 /*
1294                  * NAK interrupts normally occur during OUT transfers in DMA
1295                  * or Slave mode. For IN transfers, more requests will be
1296                  * queued as request queue space is available.
1297                  */
1298                 _qtd->error_count = 0;
1299
1300                 if (!_hc->qh->ping_state) {
1301                         update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
1302                                                    _qtd, DWC_OTG_HC_XFER_NAK);
1303                         save_data_toggle(_hc, _hc_regs, _qtd);
1304                         if (_qtd->urb->dev->speed == USB_SPEED_HIGH) {
1305                                 _hc->qh->ping_state = 1;
1306                         }
1307                 }
1308
1309                 /*
1310                  * Halt the channel so the transfer can be re-started from
1311                  * the appropriate point or the PING protocol will
1312                  * start/continue.
1313                  */
1314                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK);
1315                 break;
1316         case PIPE_INTERRUPT:
1317                 _qtd->error_count = 0;
1318         update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,_qtd, DWC_OTG_HC_XFER_NAK);
1319         save_data_toggle(_hc, _hc_regs, _qtd);
1320                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK);
1321                 break;
1322         case PIPE_ISOCHRONOUS:
1323                 /* Should never get called for isochronous transfers. */
1324                 BUG();
1325                 break;
1326         }
1327
1328  handle_nak_done:
1329         clear_hc_int(_hc_regs,nak);
1330         disable_hc_int(_hc_regs,nak);
1331
1332         return 1;
1333 }
1334
1335 /**
1336  * Handles a host channel ACK interrupt. This interrupt is enabled when
1337  * performing the PING protocol in Slave mode, when errors occur during
1338  * either Slave mode or DMA mode, and during Start Split transactions.
1339  */
1340 static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd,
1341                                   dwc_hc_t *_hc,
1342                                   dwc_otg_hc_regs_t *_hc_regs,
1343                                   dwc_otg_qtd_t *_qtd)
1344 {
1345         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1346                     "ACK Received--\n", _hc->hc_num);
1347
1348         if (_hc->do_split) {
1349                 /*
1350                  * Handle ACK on SSPLIT.
1351                  * ACK should not occur in CSPLIT.
1352                  */
1353                 if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) {
1354                         _qtd->ssplit_out_xfer_count = _hc->xfer_len;
1355                 }
1356                 if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) {
1357                         /* Don't need complete for isochronous out transfers. */
1358                         _qtd->complete_split = 1;
1359                 }
1360
1361                 /* ISOC OUT */
1362                 if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) {
1363                         switch (_hc->xact_pos) {
1364                         case DWC_HCSPLIT_XACTPOS_ALL:
1365                                 break;
1366                         case DWC_HCSPLIT_XACTPOS_END:
1367                                 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL;
1368                                 _qtd->isoc_split_offset = 0;
1369                                 break;
1370                         case DWC_HCSPLIT_XACTPOS_BEGIN:
1371                         case DWC_HCSPLIT_XACTPOS_MID:
1372                                 /*
1373                                  * For BEGIN or MID, calculate the length for
1374                                  * the next microframe to determine the correct
1375                                  * SSPLIT token, either MID or END.
1376                                  */
1377                                 do {
1378                                         struct usb_iso_packet_descriptor *frame_desc;
1379
1380                                         frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index];
1381                                         _qtd->isoc_split_offset += 188;
1382
1383                                         if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) {
1384                                                 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END;
1385                                         }
1386                                         else {
1387                                                 _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID;
1388                                         }
1389
1390                                 } while(0);
1391                                 break;
1392                         }
1393                 }
1394                 else {
1395                         halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK);
1396                 }
1397         } else {
1398                 _qtd->error_count = 0;
1399
1400                 if (_hc->qh->ping_state) {
1401                         _hc->qh->ping_state = 0;
1402                         /*
1403                          * Halt the channel so the transfer can be re-started
1404                          * from the appropriate point. This only happens in
1405                          * Slave mode. In DMA mode, the ping_state is cleared
1406                          * when the transfer is started because the core
1407                          * automatically executes the PING, then the transfer.
1408                          */
1409                         halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK);
1410                 }
1411         }
1412
1413         /*
1414          * If the ACK occurred when _not_ in the PING state, let the channel
1415          * continue transferring data after clearing the error count.
1416          */
1417
1418         disable_hc_int(_hc_regs,ack);
1419
1420         return 1;
1421 }
1422
1423 /**
1424  * Handles a host channel NYET interrupt. This interrupt should only occur on
1425  * Bulk and Control OUT endpoints and for complete split transactions. If a
1426  * NYET occurs at the same time as a Transfer Complete interrupt, it is
1427  * handled in the xfercomp interrupt handler, not here. This handler may be
1428  * called in either DMA mode or Slave mode.
1429  */
1430 static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd,
1431                                    dwc_hc_t *_hc,
1432                                    dwc_otg_hc_regs_t *_hc_regs,
1433                                    dwc_otg_qtd_t *_qtd)
1434 {
1435         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1436                     "NYET Received--\n", _hc->hc_num);
1437
1438         /*
1439          * NYET on CSPLIT
1440          * re-do the CSPLIT immediately on non-periodic
1441          */
1442         if ((_hc->do_split) && (_hc->complete_split)) {
1443                 if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) ||
1444                     (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) {
1445                         int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd));
1446
1447                         if (dwc_full_frame_num(frnum) !=
1448                             dwc_full_frame_num(_hc->qh->sched_frame)) {
1449                                 /*
1450                                  * No longer in the same full speed frame.
1451                                  * Treat this as a transaction error.
1452                                  */
1453 #if 0
1454                                 /** @todo Fix system performance so this can
1455                                  * be treated as an error. Right now complete
1456                                  * splits cannot be scheduled precisely enough
1457                                  * due to other system activity, so this error
1458                                  * occurs regularly in Slave mode.
1459                                  */
1460                                 _qtd->error_count++;
1461 #endif
1462                                 _qtd->complete_split = 0;
1463                                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR);
1464                                 /** @todo add support for isoc release */
1465                                 goto handle_nyet_done;
1466                         }
1467                 }
1468
1469                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET);
1470                 goto handle_nyet_done;
1471         }
1472
1473         _hc->qh->ping_state = 1;
1474         _qtd->error_count = 0;
1475
1476         update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd,
1477                                    DWC_OTG_HC_XFER_NYET);
1478         save_data_toggle(_hc, _hc_regs, _qtd);
1479
1480         /*
1481          * Halt the channel and re-start the transfer so the PING
1482          * protocol will start.
1483          */
1484         halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET);
1485
1486 handle_nyet_done:
1487         disable_hc_int(_hc_regs,nyet);
1488         return 1;
1489 }
1490
1491 /**
1492  * Handles a host channel babble interrupt. This handler may be called in
1493  * either DMA mode or Slave mode.
1494  */
1495 static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd,
1496                                      dwc_hc_t *_hc,
1497                                      dwc_otg_hc_regs_t *_hc_regs,
1498                                      dwc_otg_qtd_t *_qtd)
1499 {
1500         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1501                     "Babble Error--\n", _hc->hc_num);
1502     DWC_PRINT("%s \n", __func__);
1503         if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) {
1504                 dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW);
1505                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR);
1506         } else {
1507                 dwc_otg_halt_status_e halt_status;
1508                 halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
1509                                                     DWC_OTG_HC_XFER_BABBLE_ERR);
1510                 halt_channel(_hcd, _hc, _qtd, halt_status);
1511         }
1512         disable_hc_int(_hc_regs,bblerr);
1513         return 1;
1514 }
1515
1516 /**
1517  * Handles a host channel AHB error interrupt. This handler is only called in
1518  * DMA mode.
1519  */
1520 static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd,
1521                                      dwc_hc_t *_hc,
1522                                      dwc_otg_hc_regs_t *_hc_regs,
1523                                      dwc_otg_qtd_t *_qtd)
1524 {
1525         hcchar_data_t   hcchar;
1526         hcsplt_data_t   hcsplt;
1527         hctsiz_data_t   hctsiz;
1528         uint32_t        hcdma;
1529         struct urb      *urb = _qtd->urb;
1530
1531         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1532                     "AHB Error--\n", _hc->hc_num);
1533
1534         hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
1535         hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
1536         hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
1537         hcdma = dwc_read_reg32(&_hc_regs->hcdma);
1538
1539         DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num);
1540         DWC_ERROR("  hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1541         DWC_ERROR("  hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1542                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n");
1543         DWC_ERROR("  Device address: %d\n", usb_pipedevice(urb->pipe));
1544         DWC_ERROR("  Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe),
1545                     (usb_pipein(urb->pipe) ? "IN" : "OUT"));
1546         DWC_ERROR("  Endpoint type: %s\n",
1547                     ({char *pipetype;
1548                     switch (usb_pipetype(urb->pipe)) {
1549                     case PIPE_CONTROL: pipetype = "CONTROL"; break;
1550                     case PIPE_BULK: pipetype = "BULK"; break;
1551                     case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1552                     case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1553                     default: pipetype = "UNKNOWN"; break;
1554                     }; pipetype;}));
1555         DWC_ERROR("  Speed: %s\n",
1556                     ({char *speed;
1557                     switch (urb->dev->speed) {
1558                     case USB_SPEED_HIGH: speed = "HIGH"; break;
1559                     case USB_SPEED_FULL: speed = "FULL"; break;
1560                     case USB_SPEED_LOW: speed = "LOW"; break;
1561                     default: speed = "UNKNOWN"; break;
1562                     }; speed;}));
1563         DWC_ERROR("  Max packet size: %d\n",
1564                     usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
1565         DWC_ERROR("  Data buffer length: %d\n", urb->transfer_buffer_length);
1566         DWC_ERROR("  Transfer buffer: %p, Transfer DMA: %p\n",
1567                     urb->transfer_buffer, (void *)urb->transfer_dma);
1568         DWC_ERROR("  Setup buffer: %p, Setup DMA: %p\n",
1569                     urb->setup_packet, (void *)urb->setup_dma);
1570         DWC_ERROR("  Interval: %d\n", urb->interval);
1571
1572         dwc_otg_hcd_complete_urb(_hcd, urb, -EIO);
1573
1574         /*
1575          * Force a channel halt. Don't call halt_channel because that won't
1576          * write to the HCCHARn register in DMA mode to force the halt.
1577          */
1578         dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR);
1579
1580         disable_hc_int(_hc_regs,ahberr);
1581         return 1;
1582 }
1583
1584 /**
1585  * Handles a host channel transaction error interrupt. This handler may be
1586  * called in either DMA mode or Slave mode.
1587  */
1588 static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd,
1589                                       dwc_hc_t *_hc,
1590                                       dwc_otg_hc_regs_t *_hc_regs,
1591                                       dwc_otg_qtd_t *_qtd)
1592 {
1593     dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
1594         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1595                     "Transaction Error--\n", _hc->hc_num);
1596     if (list_empty(&_hc->qh->qh_list_entry)){
1597         DWC_PRINT("%s qh empty\n", __func__);
1598         goto out;
1599     }
1600
1601     if(((uint32_t) _qtd & 0xf0000000)==0){
1602         DWC_PRINT("%s qtd %p\n", __func__, _qtd);
1603         goto out;
1604     }
1605     if(((uint32_t) _qtd & 0xf0000000)==0xf0000000){
1606         DWC_PRINT("%s qtd %p 1\n", __func__, _qtd);
1607         goto out;
1608     }
1609     if(((uint32_t) _qtd->urb & 0xf0000000)==0){
1610         DWC_PRINT("%s qtd %p urb %p\n", __func__,_qtd, _qtd->urb);
1611         goto out;
1612     }
1613         switch (usb_pipetype(_qtd->urb->pipe)) {
1614         case PIPE_CONTROL:
1615         case PIPE_BULK:
1616                 _qtd->error_count++;
1617                 if (!_hc->qh->ping_state) {
1618                         update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb,
1619                                                    _qtd, DWC_OTG_HC_XFER_XACT_ERR);
1620                         save_data_toggle(_hc, _hc_regs, _qtd);
1621                         if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) {
1622                                 _hc->qh->ping_state = 1;
1623                         }
1624                 }
1625
1626                 /*
1627                  * Halt the channel so the transfer can be re-started from
1628                  * the appropriate point or the PING protocol will start.
1629                  */
1630                 halt_status = DWC_OTG_HC_XFER_XACT_ERR;
1631                 break;
1632         case PIPE_INTERRUPT:
1633                 _qtd->error_count++;
1634                 if ((_hc->do_split) && (_hc->complete_split)) {
1635                         _qtd->complete_split = 0;
1636                 }
1637                 halt_status = DWC_OTG_HC_XFER_XACT_ERR;
1638                 break;
1639         case PIPE_ISOCHRONOUS:
1640                 {
1641                         halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
1642                                                             DWC_OTG_HC_XFER_XACT_ERR);
1643
1644                 }
1645                 break;
1646         }
1647
1648 out:
1649     halt_channel(_hcd, _hc, _qtd, halt_status);
1650         disable_hc_int(_hc_regs,xacterr);
1651
1652         return 1;
1653 }
1654
1655 /**
1656  * Handles a host channel frame overrun interrupt. This handler may be called
1657  * in either DMA mode or Slave mode.
1658  */
1659 static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd,
1660                                        dwc_hc_t *_hc,
1661                                        dwc_otg_hc_regs_t *_hc_regs,
1662                                        dwc_otg_qtd_t *_qtd)
1663 {
1664         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1665                     "Frame Overrun--\n", _hc->hc_num);
1666
1667         switch (usb_pipetype(_qtd->urb->pipe)) {
1668         case PIPE_CONTROL:
1669         case PIPE_BULK:
1670                 break;
1671         case PIPE_INTERRUPT:
1672                 halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN);
1673                 break;
1674         case PIPE_ISOCHRONOUS:
1675                 {
1676                         dwc_otg_halt_status_e halt_status;
1677                         halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd,
1678                                                             DWC_OTG_HC_XFER_FRAME_OVERRUN);
1679
1680                         halt_channel(_hcd, _hc, _qtd, halt_status);
1681                 }
1682                 break;
1683         }
1684
1685         disable_hc_int(_hc_regs,frmovrun);
1686
1687         return 1;
1688 }
1689
1690 /**
1691  * Handles a host channel data toggle error interrupt. This handler may be
1692  * called in either DMA mode or Slave mode.
1693  */
1694 static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd,
1695                                          dwc_hc_t *_hc,
1696                                          dwc_otg_hc_regs_t *_hc_regs,
1697                                          dwc_otg_qtd_t *_qtd)
1698 {
1699         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1700                     "Data Toggle Error--\n", _hc->hc_num);
1701
1702         if (_hc->ep_is_in) {
1703                 _qtd->error_count = 0;
1704         } else {
1705                 DWC_ERROR("Data Toggle Error on OUT transfer,"
1706                           "channel %d\n", _hc->hc_num);
1707         }
1708
1709         disable_hc_int(_hc_regs,datatglerr);
1710
1711         return 1;
1712 }
1713
1714 #ifdef DEBUG
1715 /**
1716  * This function is for debug only. It checks that a valid halt status is set
1717  * and that HCCHARn.chdis is clear. If there's a problem, corrective action is
1718  * taken and a warning is issued.
1719  * @return 1 if halt status is ok, 0 otherwise.
1720  */
1721 static inline int halt_status_ok(dwc_otg_hcd_t *_hcd,
1722                                  dwc_hc_t *_hc,
1723                                  dwc_otg_hc_regs_t *_hc_regs,
1724                                  dwc_otg_qtd_t *_qtd)
1725 {
1726         hcchar_data_t hcchar;
1727         hctsiz_data_t hctsiz;
1728         hcint_data_t hcint;
1729         hcintmsk_data_t hcintmsk;
1730         hcsplt_data_t hcsplt;
1731
1732         if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) {
1733                 /*
1734                  * This code is here only as a check. This condition should
1735                  * never happen. Ignore the halt if it does occur.
1736                  */
1737                 hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
1738                 hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz);
1739                 hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
1740                 hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
1741                 hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt);
1742                 DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, "
1743                          "channel %d, hcchar 0x%08x, hctsiz 0x%08x, "
1744                          "hcint 0x%08x, hcintmsk 0x%08x, "
1745                          "hcsplt 0x%08x, qtd->complete_split %d\n",
1746                          __func__, _hc->hc_num, hcchar.d32, hctsiz.d32,
1747                          hcint.d32, hcintmsk.d32,
1748                          hcsplt.d32, _qtd->complete_split);
1749
1750                 DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n",
1751                          __func__, _hc->hc_num);
1752                 DWC_WARN("\n");
1753                 clear_hc_int(_hc_regs,chhltd);
1754                 return 0;
1755         }
1756
1757         /*
1758          * This code is here only as a check. hcchar.chdis should
1759          * never be set when the halt interrupt occurs. Halt the
1760          * channel again if it does occur.
1761          */
1762         hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar);
1763         if (hcchar.b.chdis) {
1764                 DWC_WARN("%s: hcchar.chdis set unexpectedly, "
1765                          "hcchar 0x%08x, trying to halt again\n",
1766                          __func__, hcchar.d32);
1767                 clear_hc_int(_hc_regs,chhltd);
1768                 _hc->halt_pending = 0;
1769                 halt_channel(_hcd, _hc, _qtd, _hc->halt_status);
1770                 return 0;
1771         }
1772
1773         return 1;
1774 }
1775 #endif
1776
1777 /**
1778  * Handles a host Channel Halted interrupt in DMA mode. This handler
1779  * determines the reason the channel halted and proceeds accordingly.
1780  */
1781 static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd,
1782                                       dwc_hc_t *_hc,
1783                                       dwc_otg_hc_regs_t *_hc_regs,
1784                                       dwc_otg_qtd_t *_qtd)
1785 {
1786         hcint_data_t hcint;
1787         hcintmsk_data_t hcintmsk;
1788
1789         if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE ||
1790             _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) {
1791                 /*
1792                  * Just release the channel. A dequeue can happen on a
1793                  * transfer timeout. In the case of an AHB Error, the channel
1794                  * was forced to halt because there's no way to gracefully
1795                  * recover.
1796                  */
1797                 release_channel(_hcd, _hc, _qtd, _hc->halt_status);
1798                 return;
1799         }
1800
1801         /* Read the HCINTn register to determine the cause for the halt. */
1802         hcint.d32 = dwc_read_reg32(&_hc_regs->hcint);
1803         hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk);
1804
1805         if (hcint.b.xfercomp) {
1806                 /** @todo This is here because of a possible hardware bug.  Spec
1807                  * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1808                  * interrupt w/ACK bit set should occur, but I only see the
1809                  * XFERCOMP bit, even with it masked out.  This is a workaround
1810                  * for that behavior.  Should fix this when hardware is fixed.
1811                  */
1812                 if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) {
1813                         handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd);
1814                 }
1815                 handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd);
1816         } else if (hcint.b.stall) {
1817                 handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd);
1818         } else if (hcint.b.xacterr) {
1819                 /*
1820                  * Must handle xacterr before nak or ack. Could get a xacterr
1821                  * at the same time as either of these on a BULK/CONTROL OUT
1822                  * that started with a PING. The xacterr takes precedence.
1823                  */
1824                 handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd);
1825         } else if (hcint.b.nyet) {
1826                 /*
1827                  * Must handle nyet before nak or ack. Could get a nyet at the
1828                  * same time as either of those on a BULK/CONTROL OUT that
1829                  * started with a PING. The nyet takes precedence.
1830                  */
1831                 handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd);
1832         } else if (hcint.b.bblerr) {
1833                 handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd);
1834         } else if (hcint.b.frmovrun) {
1835                 handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd);
1836         } else if (hcint.b.nak && !hcintmsk.b.nak) {
1837                 /*
1838                  * If nak is not masked, it's because a non-split IN transfer
1839                  * is in an error state. In that case, the nak is handled by
1840                  * the nak interrupt handler, not here. Handle nak here for
1841                  * BULK/CONTROL OUT transfers, which halt on a NAK to allow
1842                  * rewinding the buffer pointer.
1843                  */
1844                 handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd);
1845         } else if (hcint.b.ack && !hcintmsk.b.ack) {
1846                 /*
1847                  * If ack is not masked, it's because a non-split IN transfer
1848                  * is in an error state. In that case, the ack is handled by
1849                  * the ack interrupt handler, not here. Handle ack here for
1850                  * split transfers. Start splits halt on ACK.
1851                  */
1852                 handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd);
1853         } else if(hcint.b.datatglerr){
1854          DWC_PRINT("%s, DATA toggle error, Channel %d\n",__func__, _hc->hc_num);
1855          _qtd->error_count++;
1856          save_data_toggle(_hc, _hc_regs, _qtd);
1857          halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR);
1858          clear_hc_int(_hc_regs,chhltd);
1859         } else {
1860                 if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
1861                     _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
1862                         /*
1863                          * A periodic transfer halted with no other channel
1864                          * interrupts set. Assume it was halted by the core
1865                          * because it could not be completed in its scheduled
1866                          * (micro)frame.
1867                          */
1868 #ifdef DEBUG
1869                         DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n",
1870                                   __func__, _hc->hc_num);
1871 #endif
1872                         halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE);
1873                 } else {
1874                         DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason "
1875                                   "for halting is unknown, hcint 0x%08x, intsts 0x%08x\n",
1876                                   __func__, _hc->hc_num, hcint.d32,
1877                                   dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts));
1878                                 clear_hc_int(_hc_regs,chhltd);
1879                 }
1880         }
1881 }
1882
1883 /**
1884  * Handles a host channel Channel Halted interrupt.
1885  *
1886  * In slave mode, this handler is called only when the driver specifically
1887  * requests a halt. This occurs during handling other host channel interrupts
1888  * (e.g. nak, xacterr, stall, nyet, etc.).
1889  *
1890  * In DMA mode, this is the interrupt that occurs when the core has finished
1891  * processing a transfer on a channel. Other host channel interrupts (except
1892  * ahberr) are disabled in DMA mode.
1893  */
1894 static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd,
1895                                      dwc_hc_t *_hc,
1896                                      dwc_otg_hc_regs_t *_hc_regs,
1897                                      dwc_otg_qtd_t *_qtd)
1898 {
1899         DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: "
1900                     "Channel Halted--\n", _hc->hc_num);
1901
1902         if (_hcd->core_if->dma_enable) {
1903                 handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd);
1904         } else {
1905 #ifdef DEBUG
1906                 if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd)) {
1907                         return 1;
1908                 }
1909 #endif
1910                 release_channel(_hcd, _hc, _qtd, _hc->halt_status);
1911         }
1912
1913         return 1;
1914 }
1915
1916 /** Handles interrupt for a specific Host Channel */
1917 int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num)
1918 {
1919         int retval = 0;
1920         hcint_data_t hcint;
1921         hcintmsk_data_t hcintmsk;
1922         dwc_hc_t *hc;
1923         dwc_otg_hc_regs_t *hc_regs;
1924         dwc_otg_qtd_t *qtd;
1925
1926         DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num);
1927
1928         hc = _dwc_otg_hcd->hc_ptr_array[_num];
1929         hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num];
1930         qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
1931         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1932         hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk);
1933         DWC_DEBUGPL(DBG_HCDV, "  hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1934                     hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32));
1935         hcint.d32 = hcint.d32 & hcintmsk.d32;
1936
1937         if (!_dwc_otg_hcd->core_if->dma_enable) {
1938                 if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) {
1939                         hcint.b.chhltd = 0;
1940                 }
1941         }
1942
1943         if (hcint.b.chhltd) {
1944                 retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1945         }
1946         if (hcint.b.xfercomp) {
1947                 retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1948                 /*
1949                  * If NYET occurred at same time as Xfer Complete, the NYET is
1950                  * handled by the Xfer Complete interrupt handler. Don't want
1951                  * to call the NYET interrupt handler in this case.
1952                  */
1953                 hcint.b.nyet = 0;
1954         }
1955         if (hcint.b.ahberr) {
1956                 retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1957         }
1958         if (hcint.b.stall) {
1959                 retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1960         }
1961         if (hcint.b.nak) {
1962                 retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1963         }
1964         if (hcint.b.ack) {
1965                 if(!hcint.b.chhltd)
1966                         retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1967         }
1968         if (hcint.b.nyet) {
1969                 retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1970         }
1971         if (hcint.b.xacterr) {
1972                 retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1973         }
1974         if (hcint.b.bblerr) {
1975                 retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1976         }
1977         if (hcint.b.frmovrun) {
1978                 retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1979         }
1980         if (hcint.b.datatglerr) {
1981                 retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd);
1982         }
1983         return retval;
1984 }
1985
1986 #endif /* DWC_DEVICE_ONLY */