drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/clk.h>
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/init.h>
  46 #include <linux/device.h>
  47 #include <linux/errno.h>
  48 #include <linux/list.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/string.h>
  51 #include <linux/dma-mapping.h>
  52 #include <linux/irq.h>
  53 #include <linux/platform_device.h>
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65
  66     if(core_if->op_state == B_PERIPHERAL)
  67     {
  68         DWC_PRINT("%s, usb device mode\n", __func__);
  69         return 0;
  70     }
  71     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  72     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  73     if(hprt0.b.prtconnsts)  // usb device connected
  74     {
  75         //partial power-down
  76         if(!hprt0.b.prtsusp)
  77         {
  78             //hprt0.d32 = 0;
  79             hprt0.b.prtsusp = 1;
  80             hprt0.b.prtena = 0;
  81             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  82         }
  83         udelay(10);
  84         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  85         if(!hprt0.b.prtsusp)
  86         {
  87             //hprt0.d32 = 0;
  88             hprt0.b.prtsusp = 1;
  89             hprt0.b.prtena = 0;
  90             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  91         }
  92         mdelay(5);
  93         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  94         pcgcctl.b.pwrclmp = 1;//power clamp
  95         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  96         udelay(1);
  97         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
  98         pcgcctl.b.stoppclk = 1;//stop phy clk
  99         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 100     }
 101     else    //no device connect
 102     {
 103         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 104                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 0);
 105         }
 106     }
 107     udelay(3);
 108     clk_disable(core_if->otg_dev->phyclk);
 109     clk_disable(core_if->otg_dev->ahbclk);
 110     //power off
 111     return 0;
 112 }
 113
 114 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 115 {
 116     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 117     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 118     hprt0_data_t hprt0;
 119     pcgcctl_data_t pcgcctl;
 120     gintmsk_data_t gintmsk;
 121
 122     if(core_if->op_state == B_PERIPHERAL)
 123     {
 124         DWC_PRINT("%s, usb device mode\n", __func__);
 125         return 0;
 126     }
 127     clk_enable(core_if->otg_dev->phyclk);
 128     clk_enable(core_if->otg_dev->ahbclk);
 129
 130     //partial power-down
 131     //power on
 132     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 133     pcgcctl.b.stoppclk = 0;//stop phy clk
 134     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 135     udelay(1);
 136     pcgcctl.b.pwrclmp = 0;//power clamp
 137     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 138     udelay(2);
 139
 140     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 141     gintmsk.b.portintr = 0;
 142     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 143
 144     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 145     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 146     if(hprt0.b.prtconnsts)
 147     {
 148         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 149         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 150         hprt0.b.prtpwr = 1;
 151         hprt0.b.prtres = 1;
 152         hprt0.b.prtena = 0;
 153         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 154         mdelay(20);
 155         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 156         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 157         //hprt0.d32 = 0;
 158         hprt0.b.prtpwr = 1;
 159         hprt0.b.prtres = 0;
 160         hprt0.b.prtena = 0;
 161         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 162         hprt0.d32 = 0;
 163         hprt0.b.prtpwr = 1;
 164         hprt0.b.prtena = 0;
 165         hprt0.b.prtconndet = 1;
 166         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 167
 168         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 169         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 170
 171         mdelay(10);
 172     }
 173     else
 174     {
 175         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 176                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 1);
 177         }
 178     }
 179     gintmsk.b.portintr = 1;
 180     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 181
 182         return 0;
 183 }
 184
 185 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 186
 187 static const struct hc_driver dwc_otg_hc_driver = {
 188
 189         .description =          dwc_otg_hcd_name,
 190         .product_desc =         "DWC OTG Controller",
 191         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 192
 193         .irq =                  dwc_otg_hcd_irq,
 194
 195         .flags =                HCD_MEMORY | HCD_USB2,
 196
 197         //.reset =
 198         .start =                dwc_otg_hcd_start,
 199         //.suspend =
 200         //.resume =
 201
 202         /* yk@rk 20100625
 203          * core/hcd.c call hcd->driver->bus_suspend
 204          * otherwise system can not be suspended
 205          */
 206 #ifdef CONFIG_PM
 207         .bus_suspend =          dwc_otg_hcd_suspend,
 208         .bus_resume =           dwc_otg_hcd_resume,
 209 #endif
 210         .stop =                 dwc_otg_hcd_stop,
 211
 212         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 213         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 214         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 215
 216         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 217
 218         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 219         .hub_control =          dwc_otg_hcd_hub_control,
 220         //.hub_suspend =
 221         //.hub_resume =
 222 };
 223
 224 #ifdef CONFIG_USB11_HOST
 225 static const struct hc_driver host11_hc_driver = {
 226
 227         .description =          "host11_hcd",
 228         .product_desc =         "DWC OTG Controller",
 229         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 230
 231         .irq =                  dwc_otg_hcd_irq,
 232
 233         .flags =                HCD_MEMORY | HCD_USB2,
 234
 235         //.reset =
 236         .start =                dwc_otg_hcd_start,
 237         //.suspend =
 238         //.resume =
 239
 240         /* yk@rk 20100625
 241          * core/hcd.c call hcd->driver->bus_suspend
 242          * otherwise system can not be suspended
 243          */
 244 #ifdef CONFIG_PM
 245         .bus_suspend =          dwc_otg_hcd_suspend,
 246         .bus_resume =           dwc_otg_hcd_resume,
 247 #endif
 248         .stop =                 dwc_otg_hcd_stop,
 249
 250         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 251         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 252         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 253
 254         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 255
 256         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 257         .hub_control =          dwc_otg_hcd_hub_control,
 258         //.hub_suspend =
 259         //.hub_resume =
 260 };
 261 #endif
 262 #ifdef CONFIG_USB20_HOST
 263 static const struct hc_driver host20_hc_driver = {
 264
 265         .description =          "host20_hcd",
 266         .product_desc =         "DWC OTG Controller",
 267         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 268
 269         .irq =                  dwc_otg_hcd_irq,
 270
 271         .flags =                HCD_MEMORY | HCD_USB2,
 272
 273         //.reset =
 274         .start =                dwc_otg_hcd_start,
 275         //.suspend =
 276         //.resume =
 277
 278         /* yk@rk 20100625
 279          * core/hcd.c call hcd->driver->bus_suspend
 280          * otherwise system can not be suspended
 281          */
 282 #ifdef CONFIG_PM
 283         .bus_suspend =          dwc_otg_hcd_suspend,
 284         .bus_resume =           dwc_otg_hcd_resume,
 285 #endif
 286         .stop =                 dwc_otg_hcd_stop,
 287
 288         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 289         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 290         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 291
 292         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 293
 294         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 295         .hub_control =          dwc_otg_hcd_hub_control,
 296         //.hub_suspend =
 297         //.hub_resume =
 298 };
 299 #endif
 300
 301 /**
 302  * Work queue function for starting the HCD when A-Cable is connected.
 303  * The dwc_otg_hcd_start() must be called in a process context.
 304  */
 305 static void hcd_start_func(struct work_struct *work)
 306 {
 307     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 308     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 309
 310     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 311     if (hcd) {
 312             dwc_otg_hcd_start(hcd);
 313     }
 314 }
 315
 316 /**
 317  * HCD Callback function for starting the HCD when A-Cable is
 318  * connected.
 319  *
 320  * @param _p void pointer to the <code>struct usb_hcd</code>
 321  */
 322 static int32_t dwc_otg_hcd_start_cb(void *_p)
 323 {
 324         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 325         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 326         hprt0_data_t hprt0;
 327
 328         if (core_if->op_state == B_HOST) {
 329                 /*
 330                  * Reset the port.  During a HNP mode switch the reset
 331                  * needs to occur within 1ms and have a duration of at
 332                  * least 50ms.
 333                  */
 334                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 335                 hprt0.b.prtrst = 1;
 336                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 337                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 338         } else {
 339                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 340         }
 341
 342         /* Need to start the HCD in a non-interrupt context. */
 343 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 344         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 345         schedule_work(&dwc_otg_hcd->start_work);
 346
 347         return 1;
 348 }
 349
 350
 351 /**
 352  * HCD Callback function for stopping the HCD.
 353  *
 354  * @param _p void pointer to the <code>struct usb_hcd</code>
 355  */
 356 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 357 {
 358         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 359         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 360         dwc_otg_hcd_stop( usb_hcd );
 361         return 1;
 362 }
 363
 364 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 365 {
 366 #ifdef DEBUG
 367         int i;
 368         int num_channels = _hcd->core_if->core_params->host_channels;
 369         for (i = 0; i < num_channels; i++) {
 370                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 371         }
 372 #endif
 373 }
 374
 375 static void del_timers(dwc_otg_hcd_t *_hcd)
 376 {
 377         del_xfer_timers(_hcd);
 378         del_timer(&_hcd->conn_timer);
 379 }
 380
 381 /**
 382  * Processes all the URBs in a single list of QHs. Completes them with
 383  * -ETIMEDOUT and frees the QTD.
 384  */
 385 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 386 {
 387         struct list_head        *qh_item;
 388         dwc_otg_qh_t            *qh;
 389         struct list_head        *qtd_item;
 390         dwc_otg_qtd_t           *qtd;
 391         struct urb              *urb;
 392         struct usb_host_endpoint *ep;
 393
 394         list_for_each(qh_item, _qh_list) {
 395                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 396                 for (qtd_item = qh->qtd_list.next;
 397                      qtd_item != &qh->qtd_list;
 398                      qtd_item = qh->qtd_list.next) {
 399                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 400                         if (qtd->urb != NULL) {
 401                         urb = qtd->urb;
 402                         ep = qtd->urb->ep;
 403                             // 20110415 yk
 404                             // urb will be re entry to ep->urb_list if use ETIMEOUT
 405                                 dwc_otg_hcd_complete_urb(_hcd, qtd->urb,
 406                                                          -ETIMEDOUT);//ESHUTDOWN
 407
 408                         //if(!list_empty(&ep->urb_list))
 409                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
 410                           __func__, urb, usb_pipedevice(urb->pipe),
 411                           usb_pipeendpoint(urb->pipe),
 412                           usb_pipein(urb->pipe) ? "IN" : "OUT", urb->unlinked);
 413
 414                 if (!urb->unlinked)
 415                     urb->unlinked = -ESHUTDOWN;
 416
 417                         }
 418                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 419                 }
 420         }
 421 }
 422
 423 /**
 424  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 425  * and periodic schedules. The QTD associated with each URB is removed from
 426  * the schedule and freed. This function may be called when a disconnect is
 427  * detected or when the HCD is being stopped.
 428  */
 429 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 430 {
 431         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 432         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 433         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 434         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 435         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 436         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 437 }
 438
 439 /**
 440  * HCD Callback function for disconnect of the HCD.
 441  *
 442  * @param _p void pointer to the <code>struct usb_hcd</code>
 443  */
 444 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 445 {
 446         gintsts_data_t  intr;
 447     dwc_otg_hcd_t       *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 448
 449     //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 450
 451     /*
 452      * Set status flags for the hub driver.
 453      */
 454     dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 455         dwc_otg_hcd->flags.b.port_connect_status = 0;
 456
 457     /*
 458      * Shutdown any transfers in process by clearing the Tx FIFO Empty
 459      * interrupt mask and status bits and disabling subsequent host
 460      * channel interrupts.
 461      */
 462     intr.d32 = 0;
 463     intr.b.nptxfempty = 1;
 464     intr.b.ptxfempty = 1;
 465         intr.b.hcintr = 1;
 466     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 467     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 468
 469         del_timers(dwc_otg_hcd);
 470
 471         /*
 472          * Turn off the vbus power only if the core has transitioned to device
 473          * mode. If still in host mode, need to keep power on to detect a
 474          * reconnection.
 475          */
 476         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 477                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 478                         hprt0_data_t hprt0 = { .d32=0 };
 479                         DWC_PRINT("Disconnect: PortPower off\n");
 480                         hprt0.b.prtpwr = 0;
 481                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 482                 }
 483
 484                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 485         }
 486
 487         /* Respond with an error status to all URBs in the schedule. */
 488         kill_all_urbs(dwc_otg_hcd);
 489
 490         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 491                 /* Clean up any host channels that were in use. */
 492                 int                     num_channels;
 493                 int                     i;
 494                 dwc_hc_t                *channel;
 495                 dwc_otg_hc_regs_t       *hc_regs;
 496                 hcchar_data_t           hcchar;
 497
 498                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 499
 500                 if (!dwc_otg_hcd->core_if->dma_enable) {
 501                         /* Flush out any channel requests in slave mode. */
 502                         for (i = 0; i < num_channels; i++) {
 503                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 504                                 if (list_empty(&channel->hc_list_entry)) {
 505                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 506                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 507                                         if (hcchar.b.chen) {
 508                                                 hcchar.b.chen = 0;
 509                                                 hcchar.b.chdis = 1;
 510                                                 hcchar.b.epdir = 0;
 511                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 512                                         }
 513                                 }
 514                         }
 515                 }
 516
 517                 for (i = 0; i < num_channels; i++) {
 518                         channel = dwc_otg_hcd->hc_ptr_array[i];
 519                         if (list_empty(&channel->hc_list_entry)) {
 520                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 521                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 522                                 if (hcchar.b.chen) {
 523                                         /* Halt the channel. */
 524                                         hcchar.b.chdis = 1;
 525                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 526                                 }
 527
 528                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 529                                 list_add_tail(&channel->hc_list_entry,
 530                                               &dwc_otg_hcd->free_hc_list);
 531                         }
 532                 }
 533         }
 534
 535     /* A disconnect will end the session so the B-Device is no
 536      * longer a B-host. */
 537     ((struct usb_hcd *)_p)->self.is_b_host = 0;
 538     return 1;
 539 }
 540
 541 /**
 542  * Connection timeout function.  An OTG host is required to display a
 543  * message if the device does not connect within 10 seconds.
 544  */
 545 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 546 {
 547         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 548         DWC_PRINT( "Connect Timeout\n");
 549         DWC_ERROR( "Device Not Connected/Responding\n" );
 550 }
 551
 552 /**
 553  * Start the connection timer.  An OTG host is required to display a
 554  * message if the device does not connect within 10 seconds.  The
 555  * timer is deleted if a port connect interrupt occurs before the
 556  * timer expires.
 557  */
 558 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 559 {
 560         init_timer( &_hcd->conn_timer );
 561         _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 562         _hcd->conn_timer.data = (unsigned long)0;
 563         _hcd->conn_timer.expires = jiffies + (HZ*10);
 564         add_timer( &_hcd->conn_timer );
 565 }
 566
 567 /**
 568  * HCD Callback function for disconnect of the HCD.
 569  *
 570  * @param _p void pointer to the <code>struct usb_hcd</code>
 571  */
 572 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 573 {
 574         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 575         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 576         dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 577         return 1;
 578 }
 579
 580 /*
 581  * suspend: 0 usb phy enable
 582  *          1 usb phy suspend
 583  */
 584 static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
 585 {
 586     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 587
 588     if(suspend) {
 589         *otg_phy_con1 |= (0x01<<2);
 590         *otg_phy_con1 |= (0x01<<3);    // exit suspend.
 591         *otg_phy_con1 &= ~(0x01<<2);
 592
 593         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 594     }
 595     else
 596     {
 597         *otg_phy_con1 |= (0x01<<2);
 598         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
 599         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 600     }
 601
 602     return suspend;
 603 }
 604
 605 /**
 606  * HCD Callback structure for handling mode switching.
 607  */
 608 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 609         .start = dwc_otg_hcd_start_cb,
 610         .stop = dwc_otg_hcd_stop_cb,
 611         .disconnect = dwc_otg_hcd_disconnect_cb,
 612         .session_start = dwc_otg_hcd_session_start_cb,
 613         .suspend = dwc_otg_phy_suspend_cb,
 614         .p = 0,//hcd
 615 };
 616
 617 /**
 618  * Reset tasklet function
 619  */
 620 static void reset_tasklet_func (unsigned long data)
 621 {
 622         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 623         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 624         hprt0_data_t hprt0;
 625
 626         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 627
 628         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 629         hprt0.b.prtrst = 1;
 630         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 631         mdelay (60);
 632
 633         hprt0.b.prtrst = 0;
 634         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 635         dwc_otg_hcd->flags.b.port_reset_change = 1;
 636
 637         return;
 638 }
 639
 640 static struct tasklet_struct reset_tasklet = {
 641         .next = NULL,
 642         .state = 0,
 643         .count = ATOMIC_INIT(0),
 644         .func = reset_tasklet_func,
 645         .data = 0,
 646 };
 647
 648 /**
 649  * Initializes the HCD. This function allocates memory for and initializes the
 650  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 651  * USB bus with the core and calls the hc_driver->start() function. It returns
 652  * a negative error on failure.
 653  */
 654 extern uint32_t g_dbg_lvl;
 655 int __devinit dwc_otg_hcd_init(struct device *dev)
 656 {
 657         struct usb_hcd *hcd = NULL;
 658         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 659     dwc_otg_device_t *otg_dev = dev->platform_data;
 660
 661         int             num_channels;
 662         int             i;
 663         dwc_hc_t        *channel;
 664
 665         int retval = 0;
 666 #if 1  //kaiker .these code must execute before usb_create_hcd
 667         /* Set device flags indicating whether the HCD supports DMA. */
 668         static u64 usb_dmamask = 0xffffffffUL;
 669         if (otg_dev->core_if->dma_enable) {
 670                 dev->dma_mask = &usb_dmamask;
 671                 dev->coherent_dma_mask = ~0;
 672         } else {
 673                 dev->dma_mask = (void *)0;
 674                 dev->coherent_dma_mask = 0;
 675         }
 676 #endif
 677 //      g_dbg_lvl = 0xff;
 678
 679         /*
 680          * Allocate memory for the base HCD plus the DWC OTG HCD.
 681          * Initialize the base HCD.
 682          */
 683         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 684         if (hcd == NULL) {
 685                 retval = -ENOMEM;
 686                 goto error1;
 687         }
 688         hcd->regs = otg_dev->base;
 689         hcd->self.otg_port = 1;
 690
 691         /* Initialize the DWC OTG HCD. */
 692         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 693
 694         spin_lock_init(&dwc_otg_hcd->global_lock);
 695
 696         dwc_otg_hcd->core_if = otg_dev->core_if;
 697         otg_dev->hcd = dwc_otg_hcd;
 698
 699 #ifdef CONFIG_USB20_OTG_EN
 700     dwc_otg_hcd->host_enabled = 1;
 701 #else
 702     dwc_otg_hcd->host_enabled = 0;
 703 #endif
 704
 705         /* Register the HCD CIL Callbacks */
 706         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 707                                            &hcd_cil_callbacks, hcd);
 708
 709         /* Initialize the non-periodic schedule. */
 710         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 711         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 712
 713         /* Initialize the periodic schedule. */
 714         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 715         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 716         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 717         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 718
 719         /*
 720          * Create a host channel descriptor for each host channel implemented
 721          * in the controller. Initialize the channel descriptor array.
 722          */
 723         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 724         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 725         for (i = 0; i < num_channels; i++) {
 726                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 727                 if (channel == NULL) {
 728                         retval = -ENOMEM;
 729                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 730                         goto error2;
 731                 }
 732                 memset(channel, 0, sizeof(dwc_hc_t));
 733                 channel->hc_num = i;
 734                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 735 #ifdef DEBUG
 736                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 737 #endif
 738
 739                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 740         }
 741
 742         /* Initialize the Connection timeout timer. */
 743         init_timer( &dwc_otg_hcd->conn_timer );
 744
 745         /* Initialize reset tasklet. */
 746         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 747         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 748         /*
 749          * Finish generic HCD initialization and start the HCD. This function
 750          * allocates the DMA buffer pool, registers the USB bus, requests the
 751          * IRQ line, and calls dwc_otg_hcd_start method.
 752          */
 753         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 754                                         IRQF_SHARED);
 755         if (retval < 0) {
 756                 DWC_ERROR("usb_add_hcd fail,everest\n");
 757                 goto error2;
 758         }
 759         /*
 760          * Allocate space for storing data on status transactions. Normally no
 761          * data is sent, but this space acts as a bit bucket. This must be
 762          * done after usb_add_hcd since that function allocates the DMA buffer
 763          * pool.
 764          */
 765         if (otg_dev->core_if->dma_enable) {
 766                 dwc_otg_hcd->status_buf =
 767                         dma_alloc_coherent(dev,
 768                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 769                                            &dwc_otg_hcd->status_buf_dma,
 770                                            GFP_KERNEL | GFP_DMA);
 771         } else {
 772                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 773                                                   GFP_KERNEL);
 774         }
 775         if (dwc_otg_hcd->status_buf == NULL) {
 776                 retval = -ENOMEM;
 777                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 778                 goto error3;
 779         }
 780
 781 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 782 //                  dev->bus_id, hcd->self.busnum);
 783
 784         return 0;
 785
 786         /* Error conditions */
 787  error3:
 788         usb_remove_hcd(hcd);
 789  error2:
 790         dwc_otg_hcd_free(hcd);
 791         usb_put_hcd(hcd);
 792
 793  error1:
 794         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 795         return retval;
 796 }
 797
 798 #ifdef CONFIG_USB11_HOST
 799 /*
 800  * suspend: 0 usb phy enable
 801  *          1 usb phy suspend
 802  */
 803 static int32_t host11_phy_suspend_cb( void *_p, int suspend)
 804 {
 805     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 806
 807     if(suspend) {
 808         *otg_phy_con1 &= ~(0x01<<28);
 809         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 810     }
 811     else
 812     {
 813         *otg_phy_con1 |= (0x01<<28);
 814         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 815     }
 816
 817     return suspend;
 818 }
 819 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 820         .start = dwc_otg_hcd_start_cb,
 821         .stop = dwc_otg_hcd_stop_cb,
 822         .disconnect = dwc_otg_hcd_disconnect_cb,
 823         .session_start = dwc_otg_hcd_session_start_cb,
 824         .suspend = host11_phy_suspend_cb,
 825         .p = 0,//hcd
 826 };
 827
 828 static struct tasklet_struct host11_reset_tasklet = {
 829         .next = NULL,
 830         .state = 0,
 831         .count = ATOMIC_INIT(0),
 832         .func = reset_tasklet_func,
 833         .data = 0,
 834 };
 835
 836 int __devinit host11_hcd_init(struct device *dev)
 837 {
 838         struct usb_hcd *hcd = NULL;
 839         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 840     dwc_otg_device_t *otg_dev = dev->platform_data;
 841
 842         int             num_channels;
 843         int             i;
 844         dwc_hc_t        *channel;
 845
 846         int retval = 0;
 847 #if 1  //kaiker .these code must execute before usb_create_hcd
 848         /* Set device flags indicating whether the HCD supports DMA. */
 849         static u64 usb_dmamask = 0xffffffffUL;
 850         if (otg_dev->core_if->dma_enable) {
 851 //              DWC_PRINT("Using DMA mode\n");
 852                 dev->dma_mask = &usb_dmamask;
 853                 dev->coherent_dma_mask = ~0;
 854         } else {
 855 //              DWC_PRINT("Using Slave mode\n");
 856                 dev->dma_mask = (void *)0;
 857                 dev->coherent_dma_mask = 0;
 858         }
 859 #endif
 860 //      g_dbg_lvl = 0xff;
 861
 862         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 863
 864         /*
 865          * Allocate memory for the base HCD plus the DWC OTG HCD.
 866          * Initialize the base HCD.
 867          */
 868         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 869         if (hcd == NULL) {
 870                 retval = -ENOMEM;
 871                 goto error1;
 872         }
 873         hcd->regs = otg_dev->base;
 874         hcd->self.otg_port = 1;
 875
 876         /* Initialize the DWC OTG HCD. */
 877         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 878         dwc_otg_hcd->core_if = otg_dev->core_if;
 879         otg_dev->hcd = dwc_otg_hcd;
 880
 881 #ifdef CONFIG_USB11_HOST_EN
 882         dwc_otg_hcd->host_enabled = 1;
 883 #else
 884         dwc_otg_hcd->host_enabled = 0;
 885 #endif
 886
 887         spin_lock_init(&dwc_otg_hcd->global_lock);
 888
 889
 890         /* Register the HCD CIL Callbacks */
 891         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 892                                            &host11_cil_callbacks, hcd);
 893
 894         /* Initialize the non-periodic schedule. */
 895         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 896         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 897
 898         /* Initialize the periodic schedule. */
 899         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 900         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 901         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 902         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 903
 904         /*
 905          * Create a host channel descriptor for each host channel implemented
 906          * in the controller. Initialize the channel descriptor array.
 907          */
 908         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 909         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 910         for (i = 0; i < num_channels; i++) {
 911                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 912                 if (channel == NULL) {
 913                         retval = -ENOMEM;
 914                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 915                         goto error2;
 916                 }
 917                 memset(channel, 0, sizeof(dwc_hc_t));
 918                 channel->hc_num = i;
 919                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 920 #ifdef DEBUG
 921                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 922 #endif
 923
 924                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 925         }
 926
 927         /* Initialize the Connection timeout timer. */
 928         init_timer( &dwc_otg_hcd->conn_timer );
 929
 930         /* Initialize reset tasklet. */
 931         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 932         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 933         /*
 934          * Finish generic HCD initialization and start the HCD. This function
 935          * allocates the DMA buffer pool, registers the USB bus, requests the
 936          * IRQ line, and calls dwc_otg_hcd_start method.
 937          */
 938         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 939                                         IRQF_SHARED);
 940         if (retval < 0) {
 941                 DWC_ERROR("usb_add_hcd fail,everest\n");
 942                 goto error2;
 943         }
 944         /*
 945          * Allocate space for storing data on status transactions. Normally no
 946          * data is sent, but this space acts as a bit bucket. This must be
 947          * done after usb_add_hcd since that function allocates the DMA buffer
 948          * pool.
 949          */
 950         if (otg_dev->core_if->dma_enable) {
 951                 dwc_otg_hcd->status_buf =
 952                         dma_alloc_coherent(dev,
 953                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 954                                            &dwc_otg_hcd->status_buf_dma,
 955                                            GFP_KERNEL | GFP_DMA);
 956         } else {
 957                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 958                                                   GFP_KERNEL);
 959         }
 960         if (dwc_otg_hcd->status_buf == NULL) {
 961                 retval = -ENOMEM;
 962                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 963                 goto error3;
 964         }
 965
 966 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 967 //                  dev->bus_id, hcd->self.busnum);
 968
 969         return 0;
 970
 971         /* Error conditions */
 972  error3:
 973         usb_remove_hcd(hcd);
 974  error2:
 975         dwc_otg_hcd_free(hcd);
 976         usb_put_hcd(hcd);
 977
 978  error1:
 979         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 980         return retval;
 981 }
 982 #endif
 983 #ifdef CONFIG_USB20_HOST
 984
 985 /*
 986  * suspend: 0 usb phy enable
 987  *          1 usb phy suspend
 988  */
 989 static int32_t host20_phy_suspend_cb( void *_p, int suspend)
 990 {
 991     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 992     uint32_t regval;
 993
 994     regval = *otg_phy_con1;
 995
 996     if(suspend) {
 997         regval |= (0x01<<14);    // exit suspend.
 998         regval &= ~(0x01<<13);
 999
1000         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
1001     }
1002     else
1003     {
1004         regval &= ~(0x01<<14);    // exit suspend.
1005         regval |= (0x01<<13);    // software control
1006         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
1007     }
1008     *otg_phy_con1 = regval;
1009
1010     return suspend;
1011 }
1012
1013 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1014         .start = dwc_otg_hcd_start_cb,
1015         .stop = dwc_otg_hcd_stop_cb,
1016         .disconnect = dwc_otg_hcd_disconnect_cb,
1017         .session_start = dwc_otg_hcd_session_start_cb,
1018         .suspend = host20_phy_suspend_cb,
1019         .p = 0,//hcd
1020 };
1021
1022 static struct tasklet_struct host20_reset_tasklet = {
1023         .next = NULL,
1024         .state = 0,
1025         .count = ATOMIC_INIT(0),
1026         .func = reset_tasklet_func,
1027         .data = 0,
1028 };
1029
1030 int __devinit host20_hcd_init(struct device *dev)
1031 {
1032         struct usb_hcd *hcd = NULL;
1033         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1034     dwc_otg_device_t *otg_dev = dev->platform_data;
1035
1036         int             num_channels;
1037         int             i;
1038         dwc_hc_t        *channel;
1039
1040         int retval = 0;
1041 #if 1  //kaiker .these code must execute before usb_create_hcd
1042         /* Set device flags indicating whether the HCD supports DMA. */
1043         static u64 usb_dmamask = 0xffffffffUL;
1044         if (otg_dev->core_if->dma_enable) {
1045 //              DWC_PRINT("Using DMA mode\n");
1046                 dev->dma_mask = &usb_dmamask;
1047                 dev->coherent_dma_mask = ~0;
1048         } else {
1049 //              DWC_PRINT("Using Slave mode\n");
1050                 dev->dma_mask = (void *)0;
1051                 dev->coherent_dma_mask = 0;
1052         }
1053 #endif
1054 //      g_dbg_lvl = 0xff;
1055
1056         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1057
1058         /*
1059          * Allocate memory for the base HCD plus the DWC OTG HCD.
1060          * Initialize the base HCD.
1061          */
1062         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1063         if (hcd == NULL) {
1064                 retval = -ENOMEM;
1065                 goto error1;
1066         }
1067         hcd->regs = otg_dev->base;
1068         hcd->self.otg_port = 1;
1069
1070         /* Initialize the DWC OTG HCD. */
1071         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1072         dwc_otg_hcd->core_if = otg_dev->core_if;
1073         otg_dev->hcd = dwc_otg_hcd;
1074
1075 #ifdef CONFIG_USB20_HOST_EN
1076         dwc_otg_hcd->host_enabled = 1;
1077 #else
1078         dwc_otg_hcd->host_enabled = 0;
1079 #endif
1080
1081         spin_lock_init(&dwc_otg_hcd->global_lock);
1082
1083
1084         /* Register the HCD CIL Callbacks */
1085         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1086                                            &host20_cil_callbacks, hcd);
1087
1088         /* Initialize the non-periodic schedule. */
1089         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1090         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1091
1092         /* Initialize the periodic schedule. */
1093         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1094         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1095         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1096         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1097
1098         /*
1099          * Create a host channel descriptor for each host channel implemented
1100          * in the controller. Initialize the channel descriptor array.
1101          */
1102         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1103         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1104         for (i = 0; i < num_channels; i++) {
1105                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1106                 if (channel == NULL) {
1107                         retval = -ENOMEM;
1108                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1109                         goto error2;
1110                 }
1111                 memset(channel, 0, sizeof(dwc_hc_t));
1112                 channel->hc_num = i;
1113                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1114 #ifdef DEBUG
1115                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1116 #endif
1117
1118                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1119         }
1120
1121         /* Initialize the Connection timeout timer. */
1122         init_timer( &dwc_otg_hcd->conn_timer );
1123
1124         /* Initialize reset tasklet. */
1125         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1126         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1127         /*
1128          * Finish generic HCD initialization and start the HCD. This function
1129          * allocates the DMA buffer pool, registers the USB bus, requests the
1130          * IRQ line, and calls dwc_otg_hcd_start method.
1131          */
1132         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1133                                         IRQF_SHARED);
1134         if (retval < 0) {
1135                 DWC_ERROR("usb_add_hcd fail,everest\n");
1136                 goto error2;
1137         }
1138         /*
1139          * Allocate space for storing data on status transactions. Normally no
1140          * data is sent, but this space acts as a bit bucket. This must be
1141          * done after usb_add_hcd since that function allocates the DMA buffer
1142          * pool.
1143          */
1144         if (otg_dev->core_if->dma_enable) {
1145                 dwc_otg_hcd->status_buf =
1146                         dma_alloc_coherent(dev,
1147                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1148                                            &dwc_otg_hcd->status_buf_dma,
1149                                            GFP_KERNEL | GFP_DMA);
1150         } else {
1151                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1152                                                   GFP_KERNEL);
1153         }
1154         if (dwc_otg_hcd->status_buf == NULL) {
1155                 retval = -ENOMEM;
1156                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1157                 goto error3;
1158         }
1159
1160
1161         return 0;
1162
1163         /* Error conditions */
1164  error3:
1165         usb_remove_hcd(hcd);
1166  error2:
1167         dwc_otg_hcd_free(hcd);
1168         usb_put_hcd(hcd);
1169
1170  error1:
1171         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1172         return retval;
1173 }
1174 #endif
1175
1176 /**
1177  * Removes the HCD.
1178  * Frees memory and resources associated with the HCD and deregisters the bus.
1179  */
1180 void dwc_otg_hcd_remove(struct device *dev)
1181 {
1182         dwc_otg_device_t *otg_dev = dev->platform_data;
1183     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1184         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1185
1186         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1187
1188         /* Turn off all interrupts */
1189         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1190         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1191
1192         usb_remove_hcd(hcd);
1193         dwc_otg_hcd_free(hcd);
1194         usb_put_hcd(hcd);
1195
1196         return;
1197 }
1198
1199
1200 /* =========================================================================
1201  *  Linux HC Driver Functions
1202  * ========================================================================= */
1203
1204 /**
1205  * Initializes dynamic portions of the DWC_otg HCD state.
1206  */
1207 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1208 {
1209         struct list_head        *item;
1210         int                     num_channels;
1211         int                     i;
1212         dwc_hc_t                *channel;
1213         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1214
1215         _hcd->flags.d32 = 0;
1216
1217         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1218         _hcd->non_periodic_channels = 0;
1219         _hcd->periodic_channels = 0;
1220
1221         /*
1222          * Put all channels in the free channel list and clean up channel
1223          * states.
1224          */
1225         item = _hcd->free_hc_list.next;
1226         while (item != &_hcd->free_hc_list) {
1227                 list_del(item);
1228                 item = _hcd->free_hc_list.next;
1229         }
1230         num_channels = _hcd->core_if->core_params->host_channels;
1231         for (i = 0; i < num_channels; i++) {
1232                 channel = _hcd->hc_ptr_array[i];
1233                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1234                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1235         }
1236
1237         /* Initialize the DWC core for host mode operation. */
1238         dwc_otg_core_host_init(_hcd->core_if);
1239 }
1240
1241 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1242  * mode operation. Activates the root port. Returns 0 on success and a negative
1243  * error code on failure. */
1244 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1245 {
1246     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1247     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1248         unsigned long flags;
1249
1250         struct usb_bus *bus;
1251
1252         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1253         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1254
1255         bus = hcd_to_bus(_hcd);
1256         _hcd->state = HC_STATE_RUNNING;
1257
1258         /* Initialize and connect root hub if one is not already attached */
1259         if (bus->root_hub) {
1260                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1261                 /* Inform the HUB driver to resume. */
1262                 usb_hcd_resume_root_hub(_hcd);
1263         }
1264         else {
1265             /*
1266              * no use
1267              * yk@rk 2010121
1268             struct usb_device *udev;6
1269                 udev = usb_alloc_dev(NULL, bus, 0);
1270                 udev->speed = USB_SPEED_HIGH;
1271                 if (!udev) {
1272                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1273                         return -ENODEV;
1274                 }
1275         */
1276             /* Not needed - VJ
1277                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1278                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1279                return -ENODEV;
1280                }
1281              */
1282         }
1283         /* Initialize the bus state.  If the core is in Device Mode
1284          * HALT the USB bus and return. */
1285         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1286                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1287                 //_hcd->state = HC_STATE_HALT;
1288                 goto out;
1289         }
1290         hcd_reinit(dwc_otg_hcd);
1291 out:
1292         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1293
1294         return 0;
1295 }
1296
1297 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1298 {
1299         struct list_head        *item;
1300         dwc_otg_qh_t            *qh;
1301
1302         if (_qh_list->next == NULL) {
1303                 /* The list hasn't been initialized yet. */
1304                 return;
1305         }
1306
1307         /* Ensure there are no QTDs or URBs left. */
1308         kill_urbs_in_qh_list(_hcd, _qh_list);
1309
1310         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1311                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1312                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1313         }
1314 }
1315
1316 /**
1317  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1318  * stopped.
1319  */
1320 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1321 {
1322         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1323         hprt0_data_t hprt0 = { .d32=0 };
1324
1325         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1326
1327         /* Turn off all host-specific interrupts. */
1328         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1329
1330         /*
1331          * The root hub should be disconnected before this function is called.
1332          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1333          * and the QH lists (via ..._hcd_endpoint_disable).
1334          */
1335
1336         /* Turn off the vbus power */
1337         DWC_PRINT("PortPower off\n");
1338         hprt0.b.prtpwr = 0;
1339         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1340
1341         return;
1342 }
1343
1344
1345 /** Returns the current frame number. */
1346 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1347 {
1348         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1349         hfnum_data_t hfnum;
1350
1351         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1352                                    host_if->host_global_regs->hfnum);
1353
1354 #ifdef DEBUG_SOF
1355         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1356 #endif
1357         return hfnum.b.frnum;
1358 }
1359
1360 /**
1361  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1362  * in the struct usb_hcd field.
1363  */
1364 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1365 {
1366         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1367         int             i;
1368
1369         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1370
1371         del_timers(dwc_otg_hcd);
1372
1373         /* Free memory for QH/QTD lists */
1374         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1375         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1376         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1377         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1378         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1379         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1380
1381         /* Free memory for the host channels. */
1382         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1383                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1384                 if (hc != NULL) {
1385                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1386                         kfree(hc);
1387                 }
1388         }
1389
1390         if (dwc_otg_hcd->core_if->dma_enable) {
1391                 if (dwc_otg_hcd->status_buf_dma) {
1392                         dma_free_coherent(_hcd->self.controller,
1393                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1394                                           dwc_otg_hcd->status_buf,
1395                                           dwc_otg_hcd->status_buf_dma);
1396                 }
1397         } else if (dwc_otg_hcd->status_buf != NULL) {
1398                 kfree(dwc_otg_hcd->status_buf);
1399         }
1400
1401         return;
1402 }
1403
1404
1405 #ifdef DEBUG
1406 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1407 {
1408         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1409         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1410                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1411         DWC_PRINT("  Endpoint type: %s\n",
1412                   ({char *pipetype;
1413                   switch (usb_pipetype(_urb->pipe)) {
1414                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1415                   case PIPE_BULK: pipetype = "BULK"; break;
1416                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1417                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1418                   default: pipetype = "UNKNOWN"; break;
1419                   }; pipetype;}));
1420         DWC_PRINT("  Speed: %s\n",
1421                   ({char *speed;
1422                   switch (_urb->dev->speed) {
1423                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1424                   case USB_SPEED_FULL: speed = "FULL"; break;
1425                   case USB_SPEED_LOW: speed = "LOW"; break;
1426                   default: speed = "UNKNOWN"; break;
1427                   }; speed;}));
1428         DWC_PRINT("  Max packet size: %d\n",
1429                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1430         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1431         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1432                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1433         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1434                   _urb->setup_packet, (void *)_urb->setup_dma);
1435         DWC_PRINT("  Interval: %d\n", _urb->interval);
1436         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1437                 int i;
1438                 for (i = 0; i < _urb->number_of_packets;  i++) {
1439                         DWC_PRINT("  ISO Desc %d:\n", i);
1440                         DWC_PRINT("    offset: %d, length %d\n",
1441                                   _urb->iso_frame_desc[i].offset,
1442                                   _urb->iso_frame_desc[i].length);
1443                 }
1444         }
1445 }
1446
1447 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1448                               dwc_otg_qh_t *qh)
1449 {
1450         if (qh->channel != NULL) {
1451                 dwc_hc_t *hc = qh->channel;
1452                 struct list_head *item;
1453                 dwc_otg_qh_t *qh_item;
1454                 int num_channels = _hcd->core_if->core_params->host_channels;
1455                 int i;
1456
1457                 dwc_otg_hc_regs_t *hc_regs;
1458                 hcchar_data_t   hcchar;
1459                 hcsplt_data_t   hcsplt;
1460                 hctsiz_data_t   hctsiz;
1461                 uint32_t        hcdma;
1462
1463                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1464                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1465                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1466                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1467                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1468
1469                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1470                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1471                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1472                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1473                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1474                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1475                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1476                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1477                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1478                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1479                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1480                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1481                 DWC_PRINT("    qh: %p\n", hc->qh);
1482                 DWC_PRINT("  NP inactive sched:\n");
1483                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1484                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1485                         DWC_PRINT("    %p\n", qh_item);
1486                 }
1487                 DWC_PRINT("  NP active sched:\n");
1488                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1489                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1490                         DWC_PRINT("    %p\n", qh_item);
1491                 }
1492                 DWC_PRINT("  Channels: \n");
1493                 for (i = 0; i < num_channels; i++) {
1494                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1495                         DWC_PRINT("    %2d: %p\n", i, hc);
1496                 }
1497         }
1498 }
1499 #endif
1500
1501 /** Starts processing a USB transfer request specified by a USB Request Block
1502  * (URB). mem_flags indicates the type of memory allocation to use while
1503  * processing this URB. */
1504 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1505                             struct urb *_urb,
1506                             gfp_t _mem_flags)
1507 {
1508         int retval;
1509         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1510         dwc_otg_qtd_t * qtd;
1511         unsigned long flags;
1512 #if 0
1513         retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
1514         if (retval)
1515         {
1516                 DWC_PRINT("%s, usb_hcd_link_urb_to_ep error\n", __func__);
1517                 return retval;
1518         }
1519 #endif
1520         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1521 #if 1
1522         /*
1523          * Make sure the start of frame interrupt is enabled now that
1524          * we know we should have queued data. The SOF interrupt
1525          * handler automatically disables itself when idle to reduce
1526          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1527          * for the disable
1528          */
1529         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1530                          DWC_SOF_INTR_MASK);
1531 #endif
1532 #ifdef DEBUG
1533             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1534                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1535         }
1536 #endif  /*  */
1537     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1538             /* No longer connected. */
1539                 retval =  -ENODEV;
1540                 goto out;
1541         }
1542         qtd = dwc_otg_hcd_qtd_create(_urb);
1543         if (qtd == NULL) {
1544                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1545                 retval = -ENOMEM;
1546                 goto out;
1547         }
1548         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1549         if (retval < 0) {
1550                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1551                            "Error status %d\n", retval);
1552                 dwc_otg_hcd_qtd_free(qtd);
1553         }
1554 out:
1555         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1556
1557         return retval;
1558 }
1559
1560 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1561  * success.  */
1562 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1563 {
1564         unsigned long flags;
1565         dwc_otg_hcd_t * dwc_otg_hcd;
1566         dwc_otg_qtd_t * urb_qtd;
1567         dwc_otg_qh_t * qh;
1568         struct usb_host_endpoint *_ep = _urb->ep;//dwc_urb_to_endpoint(_urb);
1569         //int retval;
1570
1571         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1572         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1573         if(_ep==NULL)
1574         {
1575                 DWC_PRINT("%s=====================================================\n",__func__);
1576                 DWC_PRINT("urb->ep is null\n");
1577                 return -1;
1578         }
1579         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1580         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1581         #if 0
1582         retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
1583         if (retval) {
1584                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1585                 return retval;
1586         }
1587         #endif
1588         if(urb_qtd == NULL)
1589         {
1590                 DWC_PRINT("%s,urb_qtd is null\n",__func__);
1591                 goto urb_qtd_null;
1592                 //return -1;
1593         }
1594         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1595
1596 #ifdef DEBUG
1597     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1598                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1599                 if (urb_qtd == qh->qtd_in_process) {
1600                         dump_channel_info(dwc_otg_hcd, qh);
1601                 }
1602         }
1603
1604 #endif  /*  */
1605 #if 1
1606     if (urb_qtd == qh->qtd_in_process) {
1607             /* The QTD is in process (it has been assigned to a channel). */
1608             if (dwc_otg_hcd->flags.b.port_connect_status) {
1609
1610                     /*
1611                      * If still connected (i.e. in host mode), halt the
1612                      * channel so it can be used for other transfers. If
1613                      * no longer connected, the host registers can't be
1614                      * written to halt the channel since the core is in
1615                      * device mode.
1616                      */
1617                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1618                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1619                 }
1620         }
1621
1622     /*
1623      * Free the QTD and clean up the associated QH. Leave the QH in the
1624      * schedule if it has any remaining QTDs.
1625      */
1626     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1627         if (urb_qtd == qh->qtd_in_process) {
1628                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1629                 qh->channel = NULL;
1630                 qh->qtd_in_process = NULL;
1631         } else if (list_empty(&qh->qtd_list)) {
1632                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1633         }
1634 #endif
1635
1636 urb_qtd_null:
1637         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1638         _urb->hcpriv = NULL;
1639         //usb_hcd_unlink_urb_from_ep(_hcd, _urb);
1640     /* Higher layer software sets URB status. */
1641         usb_hcd_giveback_urb(_hcd, _urb, _status);
1642         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1643                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1644                 DWC_PRINT("  urb->status = %d\n", _status);
1645         }
1646         return 0;
1647 }
1648
1649
1650 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1651  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1652  * must already be dequeued. */
1653 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1654                                   struct usb_host_endpoint *_ep)
1655
1656 {
1657         unsigned long flags;
1658         dwc_otg_qh_t *qh;
1659         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1660
1661         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1662
1663         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1664                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1665                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1666
1667         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1668         if (qh != NULL) {
1669 #ifdef DEBUG
1670                 /** Check that the QTD list is really empty */
1671                 if (!list_empty(&qh->qtd_list)) {
1672                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1673                                  " QTD List for this endpoint is not empty\n");
1674                 }
1675 #endif
1676
1677                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1678                 _ep->hcpriv = NULL;
1679         }
1680
1681         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1682
1683         return;
1684 }
1685
1686 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1687  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1688  * interrupt.
1689  *
1690  * This function is called by the USB core when an interrupt occurs */
1691 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1692 {
1693         irqreturn_t result;
1694         unsigned long flags;
1695         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1696
1697         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1698
1699         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1700
1701         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1702
1703         return result;
1704 }
1705
1706 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1707  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1708  * is the status change indicator for the single root port. Returns 1 if either
1709  * change indicator is 1, otherwise returns 0. */
1710 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1711                                 char *_buf)
1712 {
1713         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1714
1715         _buf[0] = 0;
1716         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1717                     dwc_otg_hcd->flags.b.port_reset_change ||
1718                     dwc_otg_hcd->flags.b.port_enable_change ||
1719                     dwc_otg_hcd->flags.b.port_suspend_change ||
1720                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1721
1722 #ifdef DEBUG
1723         if (_buf[0]) {
1724                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1725                             " Root port status changed\n");
1726                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1727                             dwc_otg_hcd->flags.b.port_connect_status_change);
1728                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1729                             dwc_otg_hcd->flags.b.port_reset_change);
1730                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1731                             dwc_otg_hcd->flags.b.port_enable_change);
1732                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1733                             dwc_otg_hcd->flags.b.port_suspend_change);
1734                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1735                             dwc_otg_hcd->flags.b.port_over_current_change);
1736         }
1737 #endif
1738         return (_buf[0] != 0);
1739 }
1740
1741 #ifdef DWC_HS_ELECT_TST
1742 /*
1743  * Quick and dirty hack to implement the HS Electrical Test
1744  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1745  *
1746  * This code was copied from our userspace app "hset". It sends a
1747  * Get Device Descriptor control sequence in two parts, first the
1748  * Setup packet by itself, followed some time later by the In and
1749  * Ack packets. Rather than trying to figure out how to add this
1750  * functionality to the normal driver code, we just hijack the
1751  * hardware, using these two function to drive the hardware
1752  * directly.
1753  */
1754
1755 dwc_otg_core_global_regs_t *global_regs;
1756 dwc_otg_host_global_regs_t *hc_global_regs;
1757 dwc_otg_hc_regs_t *hc_regs;
1758 uint32_t *data_fifo;
1759
1760 static void do_setup(void)
1761 {
1762         gintsts_data_t gintsts;
1763         hctsiz_data_t hctsiz;
1764         hcchar_data_t hcchar;
1765         haint_data_t haint;
1766         hcint_data_t hcint;
1767
1768         /* Enable HAINTs */
1769         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1770
1771         /* Enable HCINTs */
1772         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1773
1774         /* Read GINTSTS */
1775         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1776         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1777
1778         /* Read HAINT */
1779         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1780         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1781
1782         /* Read HCINT */
1783         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1784         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1785
1786         /* Read HCCHAR */
1787         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1788         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1789
1790         /* Clear HCINT */
1791         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1792
1793         /* Clear HAINT */
1794         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1795
1796         /* Clear GINTSTS */
1797         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1798
1799         /* Read GINTSTS */
1800         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1801         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1802
1803         /*
1804          * Send Setup packet (Get Device Descriptor)
1805          */
1806
1807         /* Make sure channel is disabled */
1808         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1809         if (hcchar.b.chen) {
1810                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1811                 hcchar.b.chdis = 1;
1812 //              hcchar.b.chen = 1;
1813                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1814                 //sleep(1);
1815                 mdelay(1000);
1816
1817                 /* Read GINTSTS */
1818                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1819                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1820
1821                 /* Read HAINT */
1822                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1823                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1824
1825                 /* Read HCINT */
1826                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1827                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1828
1829                 /* Read HCCHAR */
1830                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1831                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1832
1833                 /* Clear HCINT */
1834                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1835
1836                 /* Clear HAINT */
1837                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1838
1839                 /* Clear GINTSTS */
1840                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1841
1842                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1843                 //if (hcchar.b.chen) {
1844                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1845                 //}
1846         }
1847
1848         /* Set HCTSIZ */
1849         hctsiz.d32 = 0;
1850         hctsiz.b.xfersize = 8;
1851         hctsiz.b.pktcnt = 1;
1852         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1853         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1854
1855         /* Set HCCHAR */
1856         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1857         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1858         hcchar.b.epdir = 0;
1859         hcchar.b.epnum = 0;
1860         hcchar.b.mps = 8;
1861         hcchar.b.chen = 1;
1862         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1863
1864         /* Fill FIFO with Setup data for Get Device Descriptor */
1865         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1866         dwc_write_reg32(data_fifo++, 0x01000680);
1867         dwc_write_reg32(data_fifo++, 0x00080000);
1868
1869         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1870         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1871
1872         /* Wait for host channel interrupt */
1873         do {
1874                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1875         } while (gintsts.b.hcintr == 0);
1876
1877         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1878
1879         /* Disable HCINTs */
1880         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1881
1882         /* Disable HAINTs */
1883         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1884
1885         /* Read HAINT */
1886         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1887         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1888
1889         /* Read HCINT */
1890         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1891         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1892
1893         /* Read HCCHAR */
1894         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1895         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1896
1897         /* Clear HCINT */
1898         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1899
1900         /* Clear HAINT */
1901         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1902
1903         /* Clear GINTSTS */
1904         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1905
1906         /* Read GINTSTS */
1907         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1908         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1909 }
1910
1911 static void do_in_ack(void)
1912 {
1913         gintsts_data_t gintsts;
1914         hctsiz_data_t hctsiz;
1915         hcchar_data_t hcchar;
1916         haint_data_t haint;
1917         hcint_data_t hcint;
1918         host_grxsts_data_t grxsts;
1919
1920         /* Enable HAINTs */
1921         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1922
1923         /* Enable HCINTs */
1924         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1925
1926         /* Read GINTSTS */
1927         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1928         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1929
1930         /* Read HAINT */
1931         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1932         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1933
1934         /* Read HCINT */
1935         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1936         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1937
1938         /* Read HCCHAR */
1939         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1940         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1941
1942         /* Clear HCINT */
1943         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1944
1945         /* Clear HAINT */
1946         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1947
1948         /* Clear GINTSTS */
1949         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1950
1951         /* Read GINTSTS */
1952         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1953         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1954
1955         /*
1956          * Receive Control In packet
1957          */
1958
1959         /* Make sure channel is disabled */
1960         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1961         if (hcchar.b.chen) {
1962                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1963                 hcchar.b.chdis = 1;
1964                 hcchar.b.chen = 1;
1965                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1966                 //sleep(1);
1967                 mdelay(1000);
1968
1969                 /* Read GINTSTS */
1970                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1971                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1972
1973                 /* Read HAINT */
1974                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1975                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1976
1977                 /* Read HCINT */
1978                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1979                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1980
1981                 /* Read HCCHAR */
1982                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1983                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1984
1985                 /* Clear HCINT */
1986                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1987
1988                 /* Clear HAINT */
1989                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1990
1991                 /* Clear GINTSTS */
1992                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1993
1994                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1995                 //if (hcchar.b.chen) {
1996                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
1997                 //}
1998         }
1999
2000         /* Set HCTSIZ */
2001         hctsiz.d32 = 0;
2002         hctsiz.b.xfersize = 8;
2003         hctsiz.b.pktcnt = 1;
2004         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2005         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2006
2007         /* Set HCCHAR */
2008         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2009         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2010         hcchar.b.epdir = 1;
2011         hcchar.b.epnum = 0;
2012         hcchar.b.mps = 8;
2013         hcchar.b.chen = 1;
2014         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2015
2016         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2017         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2018
2019         /* Wait for receive status queue interrupt */
2020         do {
2021                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2022         } while (gintsts.b.rxstsqlvl == 0);
2023
2024         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2025
2026         /* Read RXSTS */
2027         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2028         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2029
2030         /* Clear RXSTSQLVL in GINTSTS */
2031         gintsts.d32 = 0;
2032         gintsts.b.rxstsqlvl = 1;
2033         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2034
2035         switch (grxsts.b.pktsts) {
2036         case DWC_GRXSTS_PKTSTS_IN:
2037                 /* Read the data into the host buffer */
2038                 if (grxsts.b.bcnt > 0) {
2039                         int i;
2040                         int word_count = (grxsts.b.bcnt + 3) / 4;
2041
2042                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2043
2044                         for (i = 0; i < word_count; i++) {
2045                                 (void)dwc_read_reg32(data_fifo++);
2046                         }
2047                 }
2048
2049                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2050         break;
2051
2052         default:
2053                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2054         break;
2055         }
2056
2057         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2058         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2059
2060         /* Wait for receive status queue interrupt */
2061         do {
2062                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2063         } while (gintsts.b.rxstsqlvl == 0);
2064
2065         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2066
2067         /* Read RXSTS */
2068         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2069         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2070
2071         /* Clear RXSTSQLVL in GINTSTS */
2072         gintsts.d32 = 0;
2073         gintsts.b.rxstsqlvl = 1;
2074         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2075
2076         switch (grxsts.b.pktsts) {
2077         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2078         break;
2079
2080         default:
2081                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2082         break;
2083         }
2084
2085         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2086         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2087
2088         /* Wait for host channel interrupt */
2089         do {
2090                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2091         } while (gintsts.b.hcintr == 0);
2092
2093         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2094
2095         /* Read HAINT */
2096         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2097         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2098
2099         /* Read HCINT */
2100         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2101         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2102
2103         /* Read HCCHAR */
2104         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2105         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2106
2107         /* Clear HCINT */
2108         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2109
2110         /* Clear HAINT */
2111         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2112
2113         /* Clear GINTSTS */
2114         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2115
2116         /* Read GINTSTS */
2117         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2118         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2119
2120 //      usleep(100000);
2121 //      mdelay(100);
2122         mdelay(1);
2123
2124         /*
2125          * Send handshake packet
2126          */
2127
2128         /* Read HAINT */
2129         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2130         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2131
2132         /* Read HCINT */
2133         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2134         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2135
2136         /* Read HCCHAR */
2137         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2138         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2139
2140         /* Clear HCINT */
2141         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2142
2143         /* Clear HAINT */
2144         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2145
2146         /* Clear GINTSTS */
2147         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2148
2149         /* Read GINTSTS */
2150         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2151         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2152
2153         /* Make sure channel is disabled */
2154         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2155         if (hcchar.b.chen) {
2156                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2157                 hcchar.b.chdis = 1;
2158                 hcchar.b.chen = 1;
2159                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2160                 //sleep(1);
2161                 mdelay(1000);
2162
2163                 /* Read GINTSTS */
2164                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2165                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2166
2167                 /* Read HAINT */
2168                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2169                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2170
2171                 /* Read HCINT */
2172                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2173                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2174
2175                 /* Read HCCHAR */
2176                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2177                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2178
2179                 /* Clear HCINT */
2180                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2181
2182                 /* Clear HAINT */
2183                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2184
2185                 /* Clear GINTSTS */
2186                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2187
2188                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2189                 //if (hcchar.b.chen) {
2190                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2191                 //}
2192         }
2193
2194         /* Set HCTSIZ */
2195         hctsiz.d32 = 0;
2196         hctsiz.b.xfersize = 0;
2197         hctsiz.b.pktcnt = 1;
2198         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2199         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2200
2201         /* Set HCCHAR */
2202         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2203         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2204         hcchar.b.epdir = 0;
2205         hcchar.b.epnum = 0;
2206         hcchar.b.mps = 8;
2207         hcchar.b.chen = 1;
2208         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2209
2210         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2211         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2212
2213         /* Wait for host channel interrupt */
2214         do {
2215                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2216         } while (gintsts.b.hcintr == 0);
2217
2218         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2219
2220         /* Disable HCINTs */
2221         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2222
2223         /* Disable HAINTs */
2224         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2225
2226         /* Read HAINT */
2227         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2228         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2229
2230         /* Read HCINT */
2231         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2232         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2233
2234         /* Read HCCHAR */
2235         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2236         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2237
2238         /* Clear HCINT */
2239         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2240
2241         /* Clear HAINT */
2242         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2243
2244         /* Clear GINTSTS */
2245         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2246
2247         /* Read GINTSTS */
2248         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2249         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2250 }
2251 #endif /* DWC_HS_ELECT_TST */
2252
2253 /** Handles hub class-specific requests.*/
2254 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2255                             u16 _typeReq,
2256                             u16 _wValue,
2257                             u16 _wIndex,
2258                             char *_buf,
2259                             u16 _wLength)
2260 {
2261         int retval = 0;
2262         unsigned long flags;
2263
2264         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2265         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2266         struct usb_hub_descriptor *desc;
2267         hprt0_data_t hprt0 = {.d32 = 0};
2268
2269         uint32_t port_status;
2270         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2271
2272         switch (_typeReq) {
2273         case ClearHubFeature:
2274                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2275                             "ClearHubFeature 0x%x\n", _wValue);
2276                 switch (_wValue) {
2277                 case C_HUB_LOCAL_POWER:
2278                 case C_HUB_OVER_CURRENT:
2279                         /* Nothing required here */
2280                         break;
2281                 default:
2282                         retval = -EINVAL;
2283                         DWC_ERROR ("DWC OTG HCD - "
2284                                    "ClearHubFeature request %xh unknown\n", _wValue);
2285                 }
2286                 break;
2287         case ClearPortFeature:
2288                 if (!_wIndex || _wIndex > 1)
2289                         goto error;
2290
2291                 switch (_wValue) {
2292                 case USB_PORT_FEAT_ENABLE:
2293                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2294                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2295                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2296                         hprt0.b.prtena = 1;
2297                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2298                         break;
2299                 case USB_PORT_FEAT_SUSPEND:
2300                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2301                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2302                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2303                         hprt0.b.prtres = 1;
2304                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2305                         /* Clear Resume bit */
2306                         mdelay (100);
2307                         hprt0.b.prtres = 0;
2308                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2309                         break;
2310                 case USB_PORT_FEAT_POWER:
2311                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2312                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2313                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2314                         hprt0.b.prtpwr = 0;
2315                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2316                         break;
2317                 case USB_PORT_FEAT_INDICATOR:
2318                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2319                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2320                         /* Port inidicator not supported */
2321                         break;
2322                 case USB_PORT_FEAT_C_CONNECTION:
2323                         /* Clears drivers internal connect status change
2324                          * flag */
2325                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2326                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2327                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2328                         break;
2329                 case USB_PORT_FEAT_C_RESET:
2330                         /* Clears the driver's internal Port Reset Change
2331                          * flag */
2332                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2333                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2334                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2335                         break;
2336                 case USB_PORT_FEAT_C_ENABLE:
2337                         /* Clears the driver's internal Port
2338                          * Enable/Disable Change flag */
2339                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2340                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2341                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2342                         break;
2343                 case USB_PORT_FEAT_C_SUSPEND:
2344                         /* Clears the driver's internal Port Suspend
2345                          * Change flag, which is set when resume signaling on
2346                          * the host port is complete */
2347                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2348                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2349                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2350                         break;
2351                 case USB_PORT_FEAT_C_OVER_CURRENT:
2352                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2353                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2354                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2355                         break;
2356                 default:
2357                         retval = -EINVAL;
2358                         DWC_ERROR ("DWC OTG HCD - "
2359                                    "ClearPortFeature request %xh "
2360                                    "unknown or unsupported\n", _wValue);
2361                 }
2362                 break;
2363         case GetHubDescriptor:
2364                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2365                              "GetHubDescriptor\n");
2366                 desc = (struct usb_hub_descriptor *)_buf;
2367                 desc->bDescLength = 9;
2368                 desc->bDescriptorType = 0x29;
2369                 desc->bNbrPorts = 1;
2370                 desc->wHubCharacteristics = 0x08;
2371                 desc->bPwrOn2PwrGood = 1;
2372                 desc->bHubContrCurrent = 0;
2373                 desc->bitmap[0] = 0;
2374                 desc->bitmap[1] = 0xff;
2375                 break;
2376         case GetHubStatus:
2377                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2378                              "GetHubStatus\n");
2379                 memset (_buf, 0, 4);
2380                 break;
2381         case GetPortStatus:
2382                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2383                              "GetPortStatus\n");
2384
2385                 if (!_wIndex || _wIndex > 1)
2386                         goto error;
2387
2388                 port_status = 0;
2389
2390                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2391                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2392
2393                 if (dwc_otg_hcd->flags.b.port_enable_change)
2394                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2395
2396                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2397                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2398
2399                 if (dwc_otg_hcd->flags.b.port_reset_change)
2400                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2401
2402                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2403                         DWC_ERROR("Device Not Supported\n");
2404                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2405                 }
2406
2407                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2408                         /*
2409                          * The port is disconnected, which means the core is
2410                          * either in device mode or it soon will be. Just
2411                          * return 0's for the remainder of the port status
2412                          * since the port register can't be read if the core
2413                          * is in device mode.
2414                          */
2415                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2416                         break;
2417                 }
2418
2419                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2420                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2421
2422                 if (hprt0.b.prtconnsts)
2423                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2424
2425                 if (hprt0.b.prtena)
2426                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2427
2428                 if (hprt0.b.prtsusp)
2429                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2430
2431                 if (hprt0.b.prtovrcurract)
2432                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2433
2434                 if (hprt0.b.prtrst)
2435                         port_status |= (1 << USB_PORT_FEAT_RESET);
2436
2437                 if (hprt0.b.prtpwr)
2438                         port_status |= (1 << USB_PORT_FEAT_POWER);
2439
2440                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2441                         port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
2442
2443                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2444                         port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
2445
2446                 if (hprt0.b.prttstctl)
2447                         port_status |= (1 << USB_PORT_FEAT_TEST);
2448
2449                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2450
2451                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2452
2453                 break;
2454         case SetHubFeature:
2455                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2456                              "SetHubFeature\n");
2457                 /* No HUB features supported */
2458                 break;
2459         case SetPortFeature:
2460                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2461                         goto error;
2462
2463                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2464                         /*
2465                          * The port is disconnected, which means the core is
2466                          * either in device mode or it soon will be. Just
2467                          * return without doing anything since the port
2468                          * register can't be written if the core is in device
2469                          * mode.
2470                          */
2471                         break;
2472                 }
2473
2474                 switch (_wValue) {
2475                 case USB_PORT_FEAT_SUSPEND:
2476                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2477                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2478                         if (_hcd->self.otg_port == _wIndex &&
2479                             _hcd->self.b_hnp_enable) {
2480                                 gotgctl_data_t  gotgctl = {.d32=0};
2481                                 gotgctl.b.hstsethnpen = 1;
2482                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2483                                                   0, gotgctl.d32);
2484                                 core_if->op_state = A_SUSPEND;
2485                         }
2486                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2487                         hprt0.b.prtsusp = 1;
2488                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2489                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2490                         /* Suspend the Phy Clock */
2491                         {
2492                                 pcgcctl_data_t pcgcctl = {.d32=0};
2493                                 pcgcctl.b.stoppclk = 1;
2494                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2495                         }
2496
2497                         /* For HNP the bus must be suspended for at least 200ms.*/
2498                         if (_hcd->self.b_hnp_enable) {
2499                                 mdelay(200);
2500                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2501                         }
2502                         break;
2503                 case USB_PORT_FEAT_POWER:
2504                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2505                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2506                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2507                         hprt0.b.prtpwr = 1;
2508                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2509                         break;
2510                 case USB_PORT_FEAT_RESET:
2511                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2512                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2513                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2514                         /* When B-Host the Port reset bit is set in
2515                          * the Start HCD Callback function, so that
2516                          * the reset is started within 1ms of the HNP
2517                          * success interrupt. */
2518                         if (!_hcd->self.is_b_host) {
2519                                 hprt0.b.prtrst = 1;
2520                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2521                         }
2522                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2523                         MDELAY (60);
2524                         hprt0.b.prtrst = 0;
2525                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2526                         break;
2527
2528 #ifdef DWC_HS_ELECT_TST
2529                 case USB_PORT_FEAT_TEST:
2530                 {
2531                         uint32_t t;
2532                         gintmsk_data_t gintmsk;
2533
2534                         t = (_wIndex >> 8); /* MSB wIndex USB */
2535                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2536                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2537                         warn("USB_PORT_FEAT_TEST %d\n", t);
2538                         if (t < 6) {
2539                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2540                                 hprt0.b.prttstctl = t;
2541                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2542                         } else {
2543                                 /* Setup global vars with reg addresses (quick and
2544                                  * dirty hack, should be cleaned up)
2545                                  */
2546                                 global_regs = core_if->core_global_regs;
2547                                 hc_global_regs = core_if->host_if->host_global_regs;
2548                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2549                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2550
2551                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2552                                         /* Save current interrupt mask */
2553                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2554
2555                                         /* Disable all interrupts while we muck with
2556                                          * the hardware directly
2557                                          */
2558                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2559
2560                                         /* 15 second delay per the test spec */
2561                                         mdelay(15000);
2562
2563                                         /* Drive suspend on the root port */
2564                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2565                                         hprt0.b.prtsusp = 1;
2566                                         hprt0.b.prtres = 0;
2567                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2568
2569                                         /* 15 second delay per the test spec */
2570                                         mdelay(15000);
2571
2572                                         /* Drive resume on the root port */
2573                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2574                                         hprt0.b.prtsusp = 0;
2575                                         hprt0.b.prtres = 1;
2576                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2577                                         mdelay(100);
2578
2579                                         /* Clear the resume bit */
2580                                         hprt0.b.prtres = 0;
2581                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2582
2583                                         /* Restore interrupts */
2584                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2585                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2586                                         /* Save current interrupt mask */
2587                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2588
2589                                         /* Disable all interrupts while we muck with
2590                                          * the hardware directly
2591                                          */
2592                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2593
2594                                         /* 15 second delay per the test spec */
2595                                         mdelay(15000);
2596
2597                                         /* Send the Setup packet */
2598                                         do_setup();
2599
2600                                         /* 15 second delay so nothing else happens for awhile */
2601                                         mdelay(15000);
2602
2603                                         /* Restore interrupts */
2604                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2605                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2606                                         /* Save current interrupt mask */
2607                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2608
2609                                         /* Disable all interrupts while we muck with
2610                                          * the hardware directly
2611                                          */
2612                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2613
2614                                         /* Send the Setup packet */
2615                                         do_setup();
2616
2617                                         /* 15 second delay so nothing else happens for awhile */
2618                                         mdelay(15000);
2619
2620                                         /* Send the In and Ack packets */
2621                                         do_in_ack();
2622
2623                                         /* 15 second delay so nothing else happens for awhile */
2624                                         mdelay(15000);
2625
2626                                         /* Restore interrupts */
2627                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2628                                 }
2629                         }
2630                         break;
2631                 }
2632 #endif /* DWC_HS_ELECT_TST */
2633
2634                 case USB_PORT_FEAT_INDICATOR:
2635                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2636                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2637                         /* Not supported */
2638                         break;
2639                 default:
2640                         retval = -EINVAL;
2641                         DWC_ERROR ("DWC OTG HCD - "
2642                                    "SetPortFeature request %xh "
2643                                    "unknown or unsupported\n", _wValue);
2644                         break;
2645                 }
2646                 break;
2647         default:
2648         error:
2649                 retval = -EINVAL;
2650                 DWC_WARN ("DWC OTG HCD - "
2651                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2652                           _typeReq, _wIndex, _wValue);
2653                 break;
2654         }
2655
2656         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2657         return retval;
2658 }
2659
2660
2661 /**
2662  * Assigns transactions from a QTD to a free host channel and initializes the
2663  * host channel to perform the transactions. The host channel is removed from
2664  * the free list.
2665  *
2666  * @param _hcd The HCD state structure.
2667  * @param _qh Transactions from the first QTD for this QH are selected and
2668  * assigned to a free host channel.
2669  */
2670 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2671 {
2672         dwc_hc_t        *hc;
2673         dwc_otg_qtd_t   *qtd;
2674         struct urb      *urb;
2675
2676         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2677         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2678
2679         /* Remove the host channel from the free list. */
2680         list_del_init(&hc->hc_list_entry);
2681
2682         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2683         urb = qtd->urb;
2684         _qh->channel = hc;
2685         _qh->qtd_in_process = qtd;
2686
2687         /*
2688          * Use usb_pipedevice to determine device address. This address is
2689          * 0 before the SET_ADDRESS command and the correct address afterward.
2690          */
2691         hc->dev_addr = usb_pipedevice(urb->pipe);
2692         hc->ep_num = usb_pipeendpoint(urb->pipe);
2693
2694         if (urb->dev->speed == USB_SPEED_LOW) {
2695                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2696                 /*
2697                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2698                  * device connected.
2699                  */
2700         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2701         } else if (urb->dev->speed == USB_SPEED_FULL) {
2702                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2703                 /*
2704                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2705                  * device connected. warning: only support 1 device at root hub.
2706                  */
2707         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2708         } else {
2709                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2710         }
2711
2712         hc->max_packet = dwc_max_packet(_qh->maxp);
2713
2714         hc->xfer_started = 0;
2715         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2716         hc->error_state = (qtd->error_count > 0);
2717         hc->halt_on_queue = 0;
2718         hc->halt_pending = 0;
2719         hc->requests = 0;
2720
2721         /*
2722          * The following values may be modified in the transfer type section
2723          * below. The xfer_len value may be reduced when the transfer is
2724          * started to accommodate the max widths of the XferSize and PktCnt
2725          * fields in the HCTSIZn register.
2726          */
2727         hc->do_ping = _qh->ping_state;
2728         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2729         hc->data_pid_start = _qh->data_toggle;
2730         hc->multi_count = 1;
2731
2732         if (_hcd->core_if->dma_enable) {
2733                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2734         } else {
2735                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2736         }
2737         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2738         hc->xfer_count = 0;
2739
2740         /*
2741          * Set the split attributes
2742          */
2743         hc->do_split = 0;
2744         if (_qh->do_split) {
2745                 hc->do_split = 1;
2746                 hc->xact_pos = qtd->isoc_split_pos;
2747                 hc->complete_split = qtd->complete_split;
2748                 hc->hub_addr = urb->dev->tt->hub->devnum;
2749                 hc->port_addr = urb->dev->ttport;
2750         }
2751
2752         switch (usb_pipetype(urb->pipe)) {
2753         case PIPE_CONTROL:
2754                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2755                 switch (qtd->control_phase) {
2756                 case DWC_OTG_CONTROL_SETUP:
2757                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2758                         hc->do_ping = 0;
2759                         hc->ep_is_in = 0;
2760                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2761                         if (_hcd->core_if->dma_enable) {
2762                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2763                         } else {
2764                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2765                         }
2766                         hc->xfer_len = 8;
2767                         break;
2768                 case DWC_OTG_CONTROL_DATA:
2769                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2770                         hc->data_pid_start = qtd->data_toggle;
2771                         break;
2772                 case DWC_OTG_CONTROL_STATUS:
2773                         /*
2774                          * Direction is opposite of data direction or IN if no
2775                          * data.
2776                          */
2777                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2778                         if (urb->transfer_buffer_length == 0) {
2779                                 hc->ep_is_in = 1;
2780                         } else {
2781                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2782                         }
2783                         if (hc->ep_is_in) {
2784                                 hc->do_ping = 0;
2785                         }
2786                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2787                         hc->xfer_len = 0;
2788                         if (_hcd->core_if->dma_enable) {
2789                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2790                         } else {
2791                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2792                         }
2793                         break;
2794                 }
2795                 break;
2796         case PIPE_BULK:
2797                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2798                 break;
2799         case PIPE_INTERRUPT:
2800                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2801                 break;
2802         case PIPE_ISOCHRONOUS:
2803                 {
2804                         struct usb_iso_packet_descriptor *frame_desc;
2805                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2806                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2807                         if (_hcd->core_if->dma_enable) {
2808                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2809                         } else {
2810                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2811                         }
2812                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2813                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2814
2815                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2816                                 if (hc->xfer_len <= 188) {
2817                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2818                                 }
2819                                 else {
2820                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2821                                 }
2822                         }
2823                 }
2824                 break;
2825         }
2826
2827         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2828             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2829                 /*
2830                  * This value may be modified when the transfer is started to
2831                  * reflect the actual transfer length.
2832                  */
2833                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2834         }
2835
2836         dwc_otg_hc_init(_hcd->core_if, hc);
2837         hc->qh = _qh;
2838 }
2839
2840 /**
2841  * This function selects transactions from the HCD transfer schedule and
2842  * assigns them to available host channels. It is called from HCD interrupt
2843  * handler functions.
2844  *
2845  * @param _hcd The HCD state structure.
2846  *
2847  * @return The types of new transactions that were assigned to host channels.
2848  */
2849 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2850 {
2851         struct list_head                *qh_ptr;
2852         dwc_otg_qh_t                    *qh;
2853         int                             num_channels;
2854         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2855
2856 #ifdef DEBUG_SOF
2857         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2858 #endif
2859
2860         /* Process entries in the periodic ready list. */
2861         qh_ptr = _hcd->periodic_sched_ready.next;
2862         while (qh_ptr != &_hcd->periodic_sched_ready &&
2863                !list_empty(&_hcd->free_hc_list)) {
2864
2865                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2866                 assign_and_init_hc(_hcd, qh);
2867
2868                 /*
2869                  * Move the QH from the periodic ready schedule to the
2870                  * periodic assigned schedule.
2871                  */
2872                 qh_ptr = qh_ptr->next;
2873                 list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2874
2875                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2876         }
2877
2878         /*
2879          * Process entries in the inactive portion of the non-periodic
2880          * schedule. Some free host channels may not be used if they are
2881          * reserved for periodic transfers.
2882          */
2883         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2884         num_channels = _hcd->core_if->core_params->host_channels;
2885         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2886                 /*yk@rk 20100714
2887                (_hcd->non_periodic_channels <
2888                 num_channels - _hcd->periodic_channels) &&
2889                 */
2890                !list_empty(&_hcd->free_hc_list)) {
2891
2892                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2893                 assign_and_init_hc(_hcd, qh);
2894
2895                 /*
2896                  * Move the QH from the non-periodic inactive schedule to the
2897                  * non-periodic active schedule.
2898                  */
2899                 qh_ptr = qh_ptr->next;
2900                 list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2901
2902                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2903                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2904                 } else {
2905                         ret_val = DWC_OTG_TRANSACTION_ALL;
2906                 }
2907
2908                 _hcd->non_periodic_channels++;
2909         }
2910
2911         return ret_val;
2912 }
2913
2914 /**
2915  * Attempts to queue a single transaction request for a host channel
2916  * associated with either a periodic or non-periodic transfer. This function
2917  * assumes that there is space available in the appropriate request queue. For
2918  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2919  * is available in the appropriate Tx FIFO.
2920  *
2921  * @param _hcd The HCD state structure.
2922  * @param _hc Host channel descriptor associated with either a periodic or
2923  * non-periodic transfer.
2924  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2925  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2926  * transfers.
2927  *
2928  * @return 1 if a request is queued and more requests may be needed to
2929  * complete the transfer, 0 if no more requests are required for this
2930  * transfer, -1 if there is insufficient space in the Tx FIFO.
2931  */
2932 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2933                              dwc_hc_t *_hc,
2934                              uint16_t _fifo_dwords_avail)
2935 {
2936         int retval;
2937
2938         if (_hcd->core_if->dma_enable) {
2939                 if (!_hc->xfer_started) {
2940                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2941                         _hc->qh->ping_state = 0;
2942                 }
2943                 retval = 0;
2944         } else  if (_hc->halt_pending) {
2945                 /* Don't queue a request if the channel has been halted. */
2946                 retval = 0;
2947         } else if (_hc->halt_on_queue) {
2948                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
2949                 retval = 0;
2950         } else if (_hc->do_ping) {
2951                 if (!_hc->xfer_started) {
2952                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2953                 }
2954                 retval = 0;
2955         } else if (!_hc->ep_is_in ||
2956                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2957                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
2958                         if (!_hc->xfer_started) {
2959                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2960                                 retval = 1;
2961                         } else {
2962                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2963                         }
2964                 } else {
2965                         retval = -1;
2966                 }
2967         } else {
2968                 if (!_hc->xfer_started) {
2969                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2970                         retval = 1;
2971                 } else {
2972                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2973                 }
2974         }
2975
2976         return retval;
2977 }
2978
2979 /**
2980  * Processes active non-periodic channels and queues transactions for these
2981  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2982  * FIFO Empty interrupt is enabled if there are more transactions to queue as
2983  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2984  * FIFO Empty interrupt is disabled.
2985  */
2986 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
2987 {
2988         gnptxsts_data_t         tx_status;
2989         struct list_head        *orig_qh_ptr;
2990         dwc_otg_qh_t            *qh;
2991         int                     status;
2992         int                     no_queue_space = 0;
2993         int                     no_fifo_space = 0;
2994         int                     more_to_do = 0;
2995
2996         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
2997
2998         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
2999 #ifdef DEBUG
3000         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3001         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3002                     tx_status.b.nptxqspcavail);
3003         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
3004                     tx_status.b.nptxfspcavail);
3005 #endif
3006         /*
3007          * Keep track of the starting point. Skip over the start-of-list
3008          * entry.
3009          */
3010         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3011                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3012         }
3013         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3014
3015         /*
3016          * Process once through the active list or until no more space is
3017          * available in the request queue or the Tx FIFO.
3018          */
3019         do {
3020                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3021                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3022                         no_queue_space = 1;
3023                         break;
3024                 }
3025
3026                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3027                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3028
3029                 if (status > 0) {
3030                         more_to_do = 1;
3031                 } else if (status < 0) {
3032                         no_fifo_space = 1;
3033                         break;
3034                 }
3035
3036                 /* Advance to next QH, skipping start-of-list entry. */
3037                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3038                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3039                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3040                 }
3041
3042         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3043
3044         if (!_hcd->core_if->dma_enable) {
3045                 gintmsk_data_t intr_mask = {.d32 = 0};
3046                 intr_mask.b.nptxfempty = 1;
3047
3048 #ifdef DEBUG
3049                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3050                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3051                             tx_status.b.nptxqspcavail);
3052                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3053                             tx_status.b.nptxfspcavail);
3054 #endif
3055                 if (more_to_do || no_queue_space || no_fifo_space) {
3056                         /*
3057                          * May need to queue more transactions as the request
3058                          * queue or Tx FIFO empties. Enable the non-periodic
3059                          * Tx FIFO empty interrupt. (Always use the half-empty
3060                          * level to ensure that new requests are loaded as
3061                          * soon as possible.)
3062                          */
3063                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3064                 } else {
3065                         /*
3066                          * Disable the Tx FIFO empty interrupt since there are
3067                          * no more transactions that need to be queued right
3068                          * now. This function is called from interrupt
3069                          * handlers to queue more transactions as transfer
3070                          * states change.
3071                          */
3072                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3073                 }
3074         }
3075 }
3076
3077 /**
3078  * Processes periodic channels for the next frame and queues transactions for
3079  * these channels to the DWC_otg controller. After queueing transactions, the
3080  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3081  * to queue as Periodic Tx FIFO or request queue space becomes available.
3082  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3083  */
3084 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3085 {
3086         hptxsts_data_t          tx_status;
3087         struct list_head        *qh_ptr;
3088         dwc_otg_qh_t            *qh;
3089         int                     status;
3090         int                     no_queue_space = 0;
3091         int                     no_fifo_space = 0;
3092
3093         dwc_otg_host_global_regs_t *host_regs;
3094         host_regs = _hcd->core_if->host_if->host_global_regs;
3095
3096         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3097 #ifdef DEBUG
3098         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3099         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3100                     tx_status.b.ptxqspcavail);
3101         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3102                     tx_status.b.ptxfspcavail);
3103 #endif
3104
3105         qh_ptr = _hcd->periodic_sched_assigned.next;
3106         while (qh_ptr != &_hcd->periodic_sched_assigned) {
3107                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3108                 if (tx_status.b.ptxqspcavail == 0) {
3109                         no_queue_space = 1;
3110                         break;
3111                 }
3112
3113                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3114
3115                 /*
3116                  * Set a flag if we're queuing high-bandwidth in slave mode.
3117                  * The flag prevents any halts to get into the request queue in
3118                  * the middle of multiple high-bandwidth packets getting queued.
3119                  */
3120                 if ((!_hcd->core_if->dma_enable) &&
3121                     (qh->channel->multi_count > 1))
3122                 {
3123                         _hcd->core_if->queuing_high_bandwidth = 1;
3124                 }
3125
3126                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3127                 if (status < 0) {
3128                         no_fifo_space = 1;
3129                         break;
3130                 }
3131
3132                 /*
3133                  * In Slave mode, stay on the current transfer until there is
3134                  * nothing more to do or the high-bandwidth request count is
3135                  * reached. In DMA mode, only need to queue one request. The
3136                  * controller automatically handles multiple packets for
3137                  * high-bandwidth transfers.
3138                  */
3139                 if (_hcd->core_if->dma_enable ||
3140                     (status == 0 ||
3141                      qh->channel->requests == qh->channel->multi_count)) {
3142                         qh_ptr = qh_ptr->next;
3143                         /*
3144                          * Move the QH from the periodic assigned schedule to
3145                          * the periodic queued schedule.
3146                          */
3147                         list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3148
3149                         /* done queuing high bandwidth */
3150                         _hcd->core_if->queuing_high_bandwidth = 0;
3151                 }
3152         }
3153
3154         if (!_hcd->core_if->dma_enable) {
3155                 dwc_otg_core_global_regs_t *global_regs;
3156                 gintmsk_data_t intr_mask = {.d32 = 0};
3157
3158                 global_regs = _hcd->core_if->core_global_regs;
3159                 intr_mask.b.ptxfempty = 1;
3160 #ifdef DEBUG
3161                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3162                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3163                             tx_status.b.ptxqspcavail);
3164                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3165                             tx_status.b.ptxfspcavail);
3166 #endif
3167                 if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
3168                     no_queue_space || no_fifo_space) {
3169                         /*
3170                          * May need to queue more transactions as the request
3171                          * queue or Tx FIFO empties. Enable the periodic Tx
3172                          * FIFO empty interrupt. (Always use the half-empty
3173                          * level to ensure that new requests are loaded as
3174                          * soon as possible.)
3175                          */
3176                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3177                 } else {
3178                         /*
3179                          * Disable the Tx FIFO empty interrupt since there are
3180                          * no more transactions that need to be queued right
3181                          * now. This function is called from interrupt
3182                          * handlers to queue more transactions as transfer
3183                          * states change.
3184                          */
3185                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3186                 }
3187         }
3188 }
3189
3190 /**
3191  * This function processes the currently active host channels and queues
3192  * transactions for these channels to the DWC_otg controller. It is called
3193  * from HCD interrupt handler functions.
3194  *
3195  * @param _hcd The HCD state structure.
3196  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3197  * periodic, or both).
3198  */
3199 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3200                                     dwc_otg_transaction_type_e _tr_type)
3201 {
3202 #ifdef DEBUG_SOF
3203         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3204 #endif
3205         /* Process host channels associated with periodic transfers. */
3206         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3207              _tr_type == DWC_OTG_TRANSACTION_ALL) &&
3208             !list_empty(&_hcd->periodic_sched_assigned)) {
3209
3210                 process_periodic_channels(_hcd);
3211         }
3212
3213         /* Process host channels associated with non-periodic transfers. */
3214         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3215              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3216                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3217                         process_non_periodic_channels(_hcd);
3218                 } else {
3219                         /*
3220                          * Ensure NP Tx FIFO empty interrupt is disabled when
3221                          * there are no non-periodic transfers to process.
3222                          */
3223                         gintmsk_data_t gintmsk = {.d32 = 0};
3224                         gintmsk.b.nptxfempty = 1;
3225                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3226                                          gintmsk.d32, 0);
3227                 }
3228         }
3229 }
3230
3231 /**
3232  * Sets the final status of an URB and returns it to the device driver. Any
3233  * required cleanup of the URB is performed.
3234  */
3235 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3236                               int _status)
3237 __releases(_hcd->lock)
3238 __acquires(_hcd->lock)
3239 {
3240
3241 #ifdef DEBUG
3242         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3243                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3244                           __func__, _urb, usb_pipedevice(_urb->pipe),
3245                           usb_pipeendpoint(_urb->pipe),
3246                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3247                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3248                         int i;
3249                         for (i = 0; i < _urb->number_of_packets; i++) {
3250                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3251                                           i, _urb->iso_frame_desc[i].status);
3252                         }
3253                 }
3254         }
3255 #endif
3256
3257
3258         _urb->hcpriv = NULL;
3259         //usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
3260         spin_unlock(&_hcd->lock);
3261         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3262         spin_lock(&_hcd->lock);
3263 }
3264
3265 void dwc_otg_clear_halt(struct urb *_urb)
3266 {
3267         struct dwc_otg_qh *_qh;
3268         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3269         if((ep)&&(ep->hcpriv))
3270         {
3271                 _qh =  (dwc_otg_qh_t *) ep->hcpriv;
3272                 _qh->data_toggle = 0;
3273         }
3274 }
3275 /*
3276  * Returns the Queue Head for an URB.
3277  */
3278 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3279 {
3280         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3281         return (dwc_otg_qh_t *) ep->hcpriv;
3282 }
3283
3284 #ifdef DEBUG
3285 void dwc_print_setup_data (uint8_t *setup)
3286 {
3287         int i;
3288         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3289                 DWC_PRINT("Setup Data = MSB ");
3290                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3291                 DWC_PRINT("\n");
3292                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3293                 DWC_PRINT("  bmRequestType Type = ");
3294                 switch ((setup[0]&0x60) >> 5) {
3295                 case 0: DWC_PRINT("Standard\n"); break;
3296                 case 1: DWC_PRINT("Class\n"); break;
3297                 case 2: DWC_PRINT("Vendor\n"); break;
3298                 case 3: DWC_PRINT("Reserved\n"); break;
3299                 }
3300                 DWC_PRINT("  bmRequestType Recipient = ");
3301                 switch (setup[0]&0x1f) {
3302                 case 0: DWC_PRINT("Device\n"); break;
3303                 case 1: DWC_PRINT("Interface\n"); break;
3304                 case 2: DWC_PRINT("Endpoint\n"); break;
3305                 case 3: DWC_PRINT("Other\n"); break;
3306                 default: DWC_PRINT("Reserved\n"); break;
3307                 }
3308                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3309                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3310                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3311                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3312         }
3313 }
3314 #endif
3315
3316 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3317 #if 0
3318         DWC_PRINT("Frame remaining at SOF:\n");
3319         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3320                   _hcd->frrem_samples, _hcd->frrem_accum,
3321                   (_hcd->frrem_samples > 0) ?
3322                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3323
3324         DWC_PRINT("\n");
3325         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3326         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3327                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3328                   (_hcd->core_if->hfnum_7_samples > 0) ?
3329                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3330         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3331         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3332                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3333                   (_hcd->core_if->hfnum_0_samples > 0) ?
3334                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3335         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3336         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3337                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3338                   (_hcd->core_if->hfnum_other_samples > 0) ?
3339                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3340
3341         DWC_PRINT("\n");
3342         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3343         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3344                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3345                   (_hcd->hfnum_7_samples_a > 0) ?
3346                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3347         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3348         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3349                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3350                   (_hcd->hfnum_0_samples_a > 0) ?
3351                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3352         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3353         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3354                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3355                   (_hcd->hfnum_other_samples_a > 0) ?
3356                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3357
3358         DWC_PRINT("\n");
3359         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3360         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3361                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3362                   (_hcd->hfnum_7_samples_b > 0) ?
3363                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3364         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3365         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3366                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3367                   (_hcd->hfnum_0_samples_b > 0) ?
3368                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3369         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3370         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3371                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3372                   (_hcd->hfnum_other_samples_b > 0) ?
3373                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3374 #endif
3375 }
3376
3377 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3378 {
3379 #ifdef DEBUG
3380         int num_channels;
3381         int i;
3382         gnptxsts_data_t np_tx_status;
3383         hptxsts_data_t p_tx_status;
3384
3385         num_channels = _hcd->core_if->core_params->host_channels;
3386         DWC_PRINT("\n");
3387         DWC_PRINT("************************************************************\n");
3388         DWC_PRINT("HCD State:\n");
3389         DWC_PRINT("  Num channels: %d\n", num_channels);
3390         for (i = 0; i < num_channels; i++) {
3391                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3392                 DWC_PRINT("  Channel %d:\n", i);
3393                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3394                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3395                 DWC_PRINT("    speed: %d\n", hc->speed);
3396                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3397                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3398                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3399                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3400                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3401                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3402                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3403                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3404                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3405                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3406                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3407                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3408                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3409                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3410                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3411                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3412                 DWC_PRINT("    requests: %d\n", hc->requests);
3413                 DWC_PRINT("    qh: %p\n", hc->qh);
3414                 if (hc->xfer_started) {
3415                         hfnum_data_t hfnum;
3416                         hcchar_data_t hcchar;
3417                         hctsiz_data_t hctsiz;
3418                         hcint_data_t hcint;
3419                         hcintmsk_data_t hcintmsk;
3420                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3421                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3422                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3423                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3424                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3425                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3426                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3427                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3428                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3429                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3430                 }
3431                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3432                         dwc_otg_qtd_t *qtd;
3433                         struct urb *urb;
3434                         qtd = hc->qh->qtd_in_process;
3435                         urb = qtd->urb;
3436                         DWC_PRINT("    URB Info:\n");
3437                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3438                         if (urb != NULL) {
3439                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3440                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3441                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3442                                 DWC_PRINT("      Max packet size: %d\n",
3443                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3444                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3445                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3446                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3447                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3448                         }
3449                 }
3450         }
3451         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3452         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3453         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3454         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3455         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3456         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3457         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3458         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3459         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3460         dwc_otg_hcd_dump_frrem(_hcd);
3461         dwc_otg_dump_global_registers(_hcd->core_if);
3462         dwc_otg_dump_host_registers(_hcd->core_if);
3463         DWC_PRINT("************************************************************\n");
3464         DWC_PRINT("\n");
3465 #endif
3466 }
3467 #endif /* DWC_DEVICE_ONLY */