drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/clk.h>
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/init.h>
  46 #include <linux/device.h>
  47 #include <linux/errno.h>
  48 #include <linux/list.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/string.h>
  51 #include <linux/dma-mapping.h>
  52 #include <linux/irq.h>
  53 #include <linux/platform_device.h>
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65
  66     if(core_if->op_state == B_PERIPHERAL)
  67     {
  68         DWC_PRINT("%s, usb device mode\n", __func__);
  69         return 0;
  70     }
  71     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  72     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  73     if(hprt0.b.prtconnsts)  // usb device connected
  74     {
  75         //partial power-down
  76         if(!hprt0.b.prtsusp)
  77         {
  78             //hprt0.d32 = 0;
  79             hprt0.b.prtsusp = 1;
  80             hprt0.b.prtena = 0;
  81             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  82         }
  83         udelay(10);
  84         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  85         if(!hprt0.b.prtsusp)
  86         {
  87             //hprt0.d32 = 0;
  88             hprt0.b.prtsusp = 1;
  89             hprt0.b.prtena = 0;
  90             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  91         }
  92         mdelay(5);
  93         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  94         pcgcctl.b.pwrclmp = 1;//power clamp
  95         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  96         udelay(1);
  97         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
  98         pcgcctl.b.stoppclk = 1;//stop phy clk
  99         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 100     }
 101     else    //no device connect
 102     {
 103         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 104                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 0);
 105         }
 106     }
 107     clk_disable(core_if->otg_dev->phyclk);
 108     clk_disable(core_if->otg_dev->ahbclk);
 109     //power off
 110     return 0;
 111 }
 112
 113 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 114 {
 115     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 116     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 117     hprt0_data_t hprt0;
 118     pcgcctl_data_t pcgcctl;
 119     gintmsk_data_t gintmsk;
 120
 121     if(core_if->op_state == B_PERIPHERAL)
 122     {
 123         DWC_PRINT("%s, usb device mode\n", __func__);
 124         return 0;
 125     }
 126     clk_enable(core_if->otg_dev->phyclk);
 127     clk_enable(core_if->otg_dev->ahbclk);
 128
 129     //partial power-down
 130     //power on
 131     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 132     pcgcctl.b.stoppclk = 0;//stop phy clk
 133     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 134     udelay(1);
 135     pcgcctl.b.pwrclmp = 0;//power clamp
 136     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 137     udelay(2);
 138
 139     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 140     gintmsk.b.portintr = 0;
 141     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 142
 143     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 144     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 145     if(hprt0.b.prtconnsts)
 146     {
 147         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 148         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 149         hprt0.b.prtpwr = 1;
 150         hprt0.b.prtres = 1;
 151         hprt0.b.prtena = 0;
 152         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 153         mdelay(20);
 154         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 155         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 156         //hprt0.d32 = 0;
 157         hprt0.b.prtpwr = 1;
 158         hprt0.b.prtres = 0;
 159         hprt0.b.prtena = 0;
 160         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 161         hprt0.d32 = 0;
 162         hprt0.b.prtpwr = 1;
 163         hprt0.b.prtena = 0;
 164         hprt0.b.prtconndet = 1;
 165         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 166
 167         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 168         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 169
 170         gintmsk.b.portintr = 1;
 171         dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 172         mdelay(10);
 173     }
 174     else
 175     {
 176         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 177                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 1);
 178         }
 179     }
 180
 181         return 0;
 182 }
 183
 184 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 185
 186 static const struct hc_driver dwc_otg_hc_driver = {
 187
 188         .description =          dwc_otg_hcd_name,
 189         .product_desc =         "DWC OTG Controller",
 190         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 191
 192         .irq =                  dwc_otg_hcd_irq,
 193
 194         .flags =                HCD_MEMORY | HCD_USB2,
 195
 196         //.reset =
 197         .start =                dwc_otg_hcd_start,
 198         //.suspend =
 199         //.resume =
 200
 201         /* yk@rk 20100625
 202          * core/hcd.c call hcd->driver->bus_suspend
 203          * otherwise system can not be suspended
 204          */
 205 #ifdef CONFIG_PM
 206         .bus_suspend =          dwc_otg_hcd_suspend,
 207         .bus_resume =           dwc_otg_hcd_resume,
 208 #endif
 209         .stop =                 dwc_otg_hcd_stop,
 210
 211         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 212         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 213         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 214
 215         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 216
 217         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 218         .hub_control =          dwc_otg_hcd_hub_control,
 219         //.hub_suspend =
 220         //.hub_resume =
 221 };
 222
 223 #ifdef CONFIG_USB11_HOST
 224 static const struct hc_driver host11_hc_driver = {
 225
 226         .description =          "host11_hcd",
 227         .product_desc =         "DWC OTG Controller",
 228         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 229
 230         .irq =                  dwc_otg_hcd_irq,
 231
 232         .flags =                HCD_MEMORY | HCD_USB2,
 233
 234         //.reset =
 235         .start =                dwc_otg_hcd_start,
 236         //.suspend =
 237         //.resume =
 238
 239         /* yk@rk 20100625
 240          * core/hcd.c call hcd->driver->bus_suspend
 241          * otherwise system can not be suspended
 242          */
 243 #ifdef CONFIG_PM
 244         .bus_suspend =          dwc_otg_hcd_suspend,
 245         .bus_resume =           dwc_otg_hcd_resume,
 246 #endif
 247         .stop =                 dwc_otg_hcd_stop,
 248
 249         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 250         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 251         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 252
 253         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 254
 255         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 256         .hub_control =          dwc_otg_hcd_hub_control,
 257         //.hub_suspend =
 258         //.hub_resume =
 259 };
 260 #endif
 261 #ifdef CONFIG_USB20_HOST
 262 static const struct hc_driver host20_hc_driver = {
 263
 264         .description =          "host20_hcd",
 265         .product_desc =         "DWC OTG Controller",
 266         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 267
 268         .irq =                  dwc_otg_hcd_irq,
 269
 270         .flags =                HCD_MEMORY | HCD_USB2,
 271
 272         //.reset =
 273         .start =                dwc_otg_hcd_start,
 274         //.suspend =
 275         //.resume =
 276
 277         /* yk@rk 20100625
 278          * core/hcd.c call hcd->driver->bus_suspend
 279          * otherwise system can not be suspended
 280          */
 281 #ifdef CONFIG_PM
 282         .bus_suspend =          dwc_otg_hcd_suspend,
 283         .bus_resume =           dwc_otg_hcd_resume,
 284 #endif
 285         .stop =                 dwc_otg_hcd_stop,
 286
 287         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 288         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 289         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 290
 291         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 292
 293         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 294         .hub_control =          dwc_otg_hcd_hub_control,
 295         //.hub_suspend =
 296         //.hub_resume =
 297 };
 298 #endif
 299
 300 /**
 301  * Work queue function for starting the HCD when A-Cable is connected.
 302  * The dwc_otg_hcd_start() must be called in a process context.
 303  */
 304 static void hcd_start_func(struct work_struct *work)
 305 {
 306     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 307     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 308
 309     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 310     if (hcd) {
 311             dwc_otg_hcd_start(hcd);
 312     }
 313 }
 314
 315 /**
 316  * HCD Callback function for starting the HCD when A-Cable is
 317  * connected.
 318  *
 319  * @param _p void pointer to the <code>struct usb_hcd</code>
 320  */
 321 static int32_t dwc_otg_hcd_start_cb(void *_p)
 322 {
 323         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 324         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 325         hprt0_data_t hprt0;
 326
 327         if (core_if->op_state == B_HOST) {
 328                 /*
 329                  * Reset the port.  During a HNP mode switch the reset
 330                  * needs to occur within 1ms and have a duration of at
 331                  * least 50ms.
 332                  */
 333                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 334                 hprt0.b.prtrst = 1;
 335                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 336                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 337         } else {
 338                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 339         }
 340
 341         /* Need to start the HCD in a non-interrupt context. */
 342 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 343         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 344         schedule_work(&dwc_otg_hcd->start_work);
 345
 346         return 1;
 347 }
 348
 349
 350 /**
 351  * HCD Callback function for stopping the HCD.
 352  *
 353  * @param _p void pointer to the <code>struct usb_hcd</code>
 354  */
 355 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 356 {
 357         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 358         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 359         dwc_otg_hcd_stop( usb_hcd );
 360         return 1;
 361 }
 362
 363 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 364 {
 365 #ifdef DEBUG
 366         int i;
 367         int num_channels = _hcd->core_if->core_params->host_channels;
 368         for (i = 0; i < num_channels; i++) {
 369                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 370         }
 371 #endif
 372 }
 373
 374 static void del_timers(dwc_otg_hcd_t *_hcd)
 375 {
 376         del_xfer_timers(_hcd);
 377         del_timer(&_hcd->conn_timer);
 378 }
 379
 380 /**
 381  * Processes all the URBs in a single list of QHs. Completes them with
 382  * -ETIMEDOUT and frees the QTD.
 383  */
 384 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 385 {
 386         struct list_head        *qh_item;
 387         dwc_otg_qh_t            *qh;
 388         struct list_head        *qtd_item;
 389         dwc_otg_qtd_t           *qtd;
 390
 391         list_for_each(qh_item, _qh_list) {
 392                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 393                 for (qtd_item = qh->qtd_list.next;
 394                      qtd_item != &qh->qtd_list;
 395                      qtd_item = qh->qtd_list.next) {
 396                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 397                         if (qtd->urb != NULL) {
 398                                 dwc_otg_hcd_complete_urb(_hcd, qtd->urb,
 399                                                          -ETIMEDOUT);
 400                         }
 401                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 402                 }
 403         }
 404 }
 405 #if 0
 406 /**
 407  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 408  * and periodic schedules. The QTD associated with each URB is removed from
 409  * the schedule and freed. This function may be called when a disconnect is
 410  * detected or when the HCD is being stopped.
 411  */
 412 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 413 {
 414         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 415         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 416         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 417         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 418         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 419         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 420 }
 421 #endif
 422 /**
 423  * HCD Callback function for disconnect of the HCD.
 424  *
 425  * @param _p void pointer to the <code>struct usb_hcd</code>
 426  */
 427 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 428 {
 429         gintsts_data_t  intr;
 430         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 431
 432         //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 433
 434         /*
 435          * Set status flags for the hub driver.
 436          */
 437 //     DWC_PRINT("dwc_otg_hcd_disconnect_cb");
 438         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 439         dwc_otg_hcd->flags.b.port_connect_status = 0;
 440
 441         /*
 442          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 443          * interrupt mask and status bits and disabling subsequent host
 444          * channel interrupts.
 445          */
 446         intr.d32 = 0;
 447         intr.b.nptxfempty = 1;
 448         intr.b.ptxfempty = 1;
 449         intr.b.hcintr = 1;
 450         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 451         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 452
 453         del_timers(dwc_otg_hcd);
 454
 455         /*
 456          * Turn off the vbus power only if the core has transitioned to device
 457          * mode. If still in host mode, need to keep power on to detect a
 458          * reconnection.
 459          */
 460         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 461                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 462                         hprt0_data_t hprt0 = { .d32=0 };
 463                         DWC_PRINT("Disconnect: PortPower off\n");
 464                         hprt0.b.prtpwr = 0;
 465                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 466                 }
 467
 468                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 469         }
 470
 471         /* Respond with an error status to all URBs in the schedule. */
 472         // yk@20101227 handle kernel panic bug when disconnect
 473         //kill_all_urbs(dwc_otg_hcd);
 474
 475         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 476                 /* Clean up any host channels that were in use. */
 477                 int                     num_channels;
 478                 int                     i;
 479                 dwc_hc_t                *channel;
 480                 dwc_otg_hc_regs_t       *hc_regs;
 481                 hcchar_data_t           hcchar;
 482
 483                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 484
 485                 if (!dwc_otg_hcd->core_if->dma_enable) {
 486                         /* Flush out any channel requests in slave mode. */
 487                         for (i = 0; i < num_channels; i++) {
 488                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 489                                 if (list_empty(&channel->hc_list_entry)) {
 490                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 491                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 492                                         if (hcchar.b.chen) {
 493                                                 hcchar.b.chen = 0;
 494                                                 hcchar.b.chdis = 1;
 495                                                 hcchar.b.epdir = 0;
 496                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 497                                         }
 498                                 }
 499                         }
 500                 }
 501
 502                 for (i = 0; i < num_channels; i++) {
 503                         channel = dwc_otg_hcd->hc_ptr_array[i];
 504                         if (list_empty(&channel->hc_list_entry)) {
 505                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 506                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 507                                 if (hcchar.b.chen) {
 508                                         /* Halt the channel. */
 509                                         hcchar.b.chdis = 1;
 510                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 511                                 }
 512
 513                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 514                                 list_add_tail(&channel->hc_list_entry,
 515                                               &dwc_otg_hcd->free_hc_list);
 516                         }
 517                 }
 518         }
 519
 520         /* A disconnect will end the session so the B-Device is no
 521          * longer a B-host. */
 522         ((struct usb_hcd *)_p)->self.is_b_host = 0;
 523         return 1;
 524 }
 525
 526 /**
 527  * Connection timeout function.  An OTG host is required to display a
 528  * message if the device does not connect within 10 seconds.
 529  */
 530 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 531 {
 532         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 533         DWC_PRINT( "Connect Timeout\n");
 534         DWC_ERROR( "Device Not Connected/Responding\n" );
 535 }
 536
 537 /**
 538  * Start the connection timer.  An OTG host is required to display a
 539  * message if the device does not connect within 10 seconds.  The
 540  * timer is deleted if a port connect interrupt occurs before the
 541  * timer expires.
 542  */
 543 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 544 {
 545         init_timer( &_hcd->conn_timer );
 546         _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 547         _hcd->conn_timer.data = (unsigned long)0;
 548         _hcd->conn_timer.expires = jiffies + (HZ*10);
 549         add_timer( &_hcd->conn_timer );
 550 }
 551
 552 /**
 553  * HCD Callback function for disconnect of the HCD.
 554  *
 555  * @param _p void pointer to the <code>struct usb_hcd</code>
 556  */
 557 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 558 {
 559         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 560         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 561         dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 562         return 1;
 563 }
 564
 565 /*
 566  * suspend: 0 usb phy enable
 567  *          1 usb phy suspend
 568  */
 569 static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
 570 {
 571     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 572
 573     if(suspend) {
 574         *otg_phy_con1 |= (0x01<<2);
 575         *otg_phy_con1 |= (0x01<<3);    // exit suspend.
 576         *otg_phy_con1 &= ~(0x01<<2);
 577
 578         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 579     }
 580     else
 581     {
 582         *otg_phy_con1 |= (0x01<<2);
 583         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
 584         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 585     }
 586
 587     return suspend;
 588 }
 589
 590 /**
 591  * HCD Callback structure for handling mode switching.
 592  */
 593 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 594         .start = dwc_otg_hcd_start_cb,
 595         .stop = dwc_otg_hcd_stop_cb,
 596         .disconnect = dwc_otg_hcd_disconnect_cb,
 597         .session_start = dwc_otg_hcd_session_start_cb,
 598         .suspend = dwc_otg_phy_suspend_cb,
 599         .p = 0,//hcd
 600 };
 601
 602 /**
 603  * Reset tasklet function
 604  */
 605 static void reset_tasklet_func (unsigned long data)
 606 {
 607         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 608         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 609         hprt0_data_t hprt0;
 610
 611         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 612
 613         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 614         hprt0.b.prtrst = 1;
 615         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 616         mdelay (60);
 617
 618         hprt0.b.prtrst = 0;
 619         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 620         dwc_otg_hcd->flags.b.port_reset_change = 1;
 621
 622         return;
 623 }
 624
 625 static struct tasklet_struct reset_tasklet = {
 626         .next = NULL,
 627         .state = 0,
 628         .count = ATOMIC_INIT(0),
 629         .func = reset_tasklet_func,
 630         .data = 0,
 631 };
 632
 633 /**
 634  * Initializes the HCD. This function allocates memory for and initializes the
 635  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 636  * USB bus with the core and calls the hc_driver->start() function. It returns
 637  * a negative error on failure.
 638  */
 639 extern uint32_t g_dbg_lvl;
 640 int __devinit dwc_otg_hcd_init(struct device *dev)
 641 {
 642         struct usb_hcd *hcd = NULL;
 643         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 644     dwc_otg_device_t *otg_dev = dev->platform_data;
 645
 646         int             num_channels;
 647         int             i;
 648         dwc_hc_t        *channel;
 649
 650         int retval = 0;
 651 #if 1  //kaiker .these code must execute before usb_create_hcd
 652         /* Set device flags indicating whether the HCD supports DMA. */
 653         static u64 usb_dmamask = 0xffffffffUL;
 654         if (otg_dev->core_if->dma_enable) {
 655                 dev->dma_mask = &usb_dmamask;
 656                 dev->coherent_dma_mask = ~0;
 657         } else {
 658                 dev->dma_mask = (void *)0;
 659                 dev->coherent_dma_mask = 0;
 660         }
 661 #endif
 662         DWC_PRINT("dwc_otg_hcd_init everest\n");
 663 //      g_dbg_lvl = 0xff;
 664
 665         /*
 666          * Allocate memory for the base HCD plus the DWC OTG HCD.
 667          * Initialize the base HCD.
 668          */
 669         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 670         if (hcd == NULL) {
 671                 retval = -ENOMEM;
 672                 goto error1;
 673         }
 674         hcd->regs = otg_dev->base;
 675         hcd->self.otg_port = 1;
 676
 677         /* Initialize the DWC OTG HCD. */
 678         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 679
 680         spin_lock_init(&dwc_otg_hcd->global_lock);
 681
 682         dwc_otg_hcd->core_if = otg_dev->core_if;
 683         otg_dev->hcd = dwc_otg_hcd;
 684
 685 #ifdef CONFIG_USB20_OTG_EN
 686     dwc_otg_hcd->host_enabled = 1;
 687 #else
 688     dwc_otg_hcd->host_enabled = 0;
 689 #endif
 690
 691         /* Register the HCD CIL Callbacks */
 692         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 693                                            &hcd_cil_callbacks, hcd);
 694
 695         /* Initialize the non-periodic schedule. */
 696         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 697         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 698
 699         /* Initialize the periodic schedule. */
 700         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 701         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 702         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 703         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 704
 705         /*
 706          * Create a host channel descriptor for each host channel implemented
 707          * in the controller. Initialize the channel descriptor array.
 708          */
 709         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 710         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 711         for (i = 0; i < num_channels; i++) {
 712                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 713                 if (channel == NULL) {
 714                         retval = -ENOMEM;
 715                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 716                         goto error2;
 717                 }
 718                 memset(channel, 0, sizeof(dwc_hc_t));
 719                 channel->hc_num = i;
 720                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 721 #ifdef DEBUG
 722                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 723 #endif
 724
 725                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 726         }
 727
 728         /* Initialize the Connection timeout timer. */
 729         init_timer( &dwc_otg_hcd->conn_timer );
 730
 731         /* Initialize reset tasklet. */
 732         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 733         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 734         /*
 735          * Finish generic HCD initialization and start the HCD. This function
 736          * allocates the DMA buffer pool, registers the USB bus, requests the
 737          * IRQ line, and calls dwc_otg_hcd_start method.
 738          */
 739         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 740                                         IRQF_SHARED);
 741         if (retval < 0) {
 742                 DWC_ERROR("usb_add_hcd fail,everest\n");
 743                 goto error2;
 744         }
 745         /*
 746          * Allocate space for storing data on status transactions. Normally no
 747          * data is sent, but this space acts as a bit bucket. This must be
 748          * done after usb_add_hcd since that function allocates the DMA buffer
 749          * pool.
 750          */
 751         if (otg_dev->core_if->dma_enable) {
 752                 dwc_otg_hcd->status_buf =
 753                         dma_alloc_coherent(dev,
 754                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 755                                            &dwc_otg_hcd->status_buf_dma,
 756                                            GFP_KERNEL | GFP_DMA);
 757         } else {
 758                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 759                                                   GFP_KERNEL);
 760         }
 761         if (dwc_otg_hcd->status_buf == NULL) {
 762                 retval = -ENOMEM;
 763                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 764                 goto error3;
 765         }
 766
 767         DWC_PRINT("%s end,everest\n",__func__);
 768 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 769 //                  dev->bus_id, hcd->self.busnum);
 770
 771         return 0;
 772
 773         /* Error conditions */
 774  error3:
 775         usb_remove_hcd(hcd);
 776  error2:
 777         dwc_otg_hcd_free(hcd);
 778         usb_put_hcd(hcd);
 779
 780  error1:
 781         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 782         return retval;
 783 }
 784
 785 #ifdef CONFIG_USB11_HOST
 786 /*
 787  * suspend: 0 usb phy enable
 788  *          1 usb phy suspend
 789  */
 790 static int32_t host11_phy_suspend_cb( void *_p, int suspend)
 791 {
 792     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 793
 794     if(suspend) {
 795         *otg_phy_con1 &= ~(0x01<<28);
 796         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 797     }
 798     else
 799     {
 800         *otg_phy_con1 |= (0x01<<28);
 801         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 802     }
 803
 804     return suspend;
 805 }
 806 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 807         .start = dwc_otg_hcd_start_cb,
 808         .stop = dwc_otg_hcd_stop_cb,
 809         .disconnect = dwc_otg_hcd_disconnect_cb,
 810         .session_start = dwc_otg_hcd_session_start_cb,
 811         .suspend = host11_phy_suspend_cb,
 812         .p = 0,//hcd
 813 };
 814
 815 static struct tasklet_struct host11_reset_tasklet = {
 816         .next = NULL,
 817         .state = 0,
 818         .count = ATOMIC_INIT(0),
 819         .func = reset_tasklet_func,
 820         .data = 0,
 821 };
 822
 823 int __devinit host11_hcd_init(struct device *dev)
 824 {
 825         struct usb_hcd *hcd = NULL;
 826         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 827     dwc_otg_device_t *otg_dev = dev->platform_data;
 828
 829         int             num_channels;
 830         int             i;
 831         dwc_hc_t        *channel;
 832
 833         int retval = 0;
 834 #if 1  //kaiker .these code must execute before usb_create_hcd
 835         /* Set device flags indicating whether the HCD supports DMA. */
 836         static u64 usb_dmamask = 0xffffffffUL;
 837         if (otg_dev->core_if->dma_enable) {
 838 //              DWC_PRINT("Using DMA mode\n");
 839                 dev->dma_mask = &usb_dmamask;
 840                 dev->coherent_dma_mask = ~0;
 841         } else {
 842 //              DWC_PRINT("Using Slave mode\n");
 843                 dev->dma_mask = (void *)0;
 844                 dev->coherent_dma_mask = 0;
 845         }
 846 #endif
 847         DWC_PRINT("%s everest\n",__func__);
 848 //      g_dbg_lvl = 0xff;
 849
 850         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 851
 852         /*
 853          * Allocate memory for the base HCD plus the DWC OTG HCD.
 854          * Initialize the base HCD.
 855          */
 856         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 857         if (hcd == NULL) {
 858                 retval = -ENOMEM;
 859                 goto error1;
 860         }
 861         hcd->regs = otg_dev->base;
 862         hcd->self.otg_port = 1;
 863
 864         /* Initialize the DWC OTG HCD. */
 865         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 866         dwc_otg_hcd->core_if = otg_dev->core_if;
 867         otg_dev->hcd = dwc_otg_hcd;
 868
 869 #ifdef CONFIG_USB11_HOST_EN
 870         dwc_otg_hcd->host_enabled = 1;
 871 #else
 872         dwc_otg_hcd->host_enabled = 0;
 873 #endif
 874
 875         spin_lock_init(&dwc_otg_hcd->global_lock);
 876
 877
 878         /* Register the HCD CIL Callbacks */
 879         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 880                                            &host11_cil_callbacks, hcd);
 881
 882         /* Initialize the non-periodic schedule. */
 883         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 884         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 885
 886         /* Initialize the periodic schedule. */
 887         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 888         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 889         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 890         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 891
 892         /*
 893          * Create a host channel descriptor for each host channel implemented
 894          * in the controller. Initialize the channel descriptor array.
 895          */
 896         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 897         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 898         for (i = 0; i < num_channels; i++) {
 899                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 900                 if (channel == NULL) {
 901                         retval = -ENOMEM;
 902                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 903                         goto error2;
 904                 }
 905                 memset(channel, 0, sizeof(dwc_hc_t));
 906                 channel->hc_num = i;
 907                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 908 #ifdef DEBUG
 909                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 910 #endif
 911
 912                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 913         }
 914
 915         /* Initialize the Connection timeout timer. */
 916         init_timer( &dwc_otg_hcd->conn_timer );
 917
 918         /* Initialize reset tasklet. */
 919         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 920         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 921         /*
 922          * Finish generic HCD initialization and start the HCD. This function
 923          * allocates the DMA buffer pool, registers the USB bus, requests the
 924          * IRQ line, and calls dwc_otg_hcd_start method.
 925          */
 926         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 927                                         IRQF_SHARED);
 928         if (retval < 0) {
 929                 DWC_ERROR("usb_add_hcd fail,everest\n");
 930                 goto error2;
 931         }
 932         /*
 933          * Allocate space for storing data on status transactions. Normally no
 934          * data is sent, but this space acts as a bit bucket. This must be
 935          * done after usb_add_hcd since that function allocates the DMA buffer
 936          * pool.
 937          */
 938         if (otg_dev->core_if->dma_enable) {
 939                 dwc_otg_hcd->status_buf =
 940                         dma_alloc_coherent(dev,
 941                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 942                                            &dwc_otg_hcd->status_buf_dma,
 943                                            GFP_KERNEL | GFP_DMA);
 944         } else {
 945                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 946                                                   GFP_KERNEL);
 947         }
 948         if (dwc_otg_hcd->status_buf == NULL) {
 949                 retval = -ENOMEM;
 950                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 951                 goto error3;
 952         }
 953
 954         DWC_PRINT("%s end,everest\n",__func__);
 955 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 956 //                  dev->bus_id, hcd->self.busnum);
 957
 958         return 0;
 959
 960         /* Error conditions */
 961  error3:
 962         usb_remove_hcd(hcd);
 963  error2:
 964         dwc_otg_hcd_free(hcd);
 965         usb_put_hcd(hcd);
 966
 967  error1:
 968         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 969         return retval;
 970 }
 971 #endif
 972 #ifdef CONFIG_USB20_HOST
 973
 974 /*
 975  * suspend: 0 usb phy enable
 976  *          1 usb phy suspend
 977  */
 978 static int32_t host20_phy_suspend_cb( void *_p, int suspend)
 979 {
 980     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 981     uint32_t regval;
 982
 983     regval = *otg_phy_con1;
 984
 985     if(suspend) {
 986         regval |= (0x01<<14);    // exit suspend.
 987         regval &= ~(0x01<<13);
 988
 989         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 990     }
 991     else
 992     {
 993         regval &= ~(0x01<<14);    // exit suspend.
 994         regval |= (0x01<<13);    // software control
 995         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 996     }
 997     *otg_phy_con1 = regval;
 998
 999     return suspend;
1000 }
1001
1002 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1003         .start = dwc_otg_hcd_start_cb,
1004         .stop = dwc_otg_hcd_stop_cb,
1005         .disconnect = dwc_otg_hcd_disconnect_cb,
1006         .session_start = dwc_otg_hcd_session_start_cb,
1007         .suspend = host20_phy_suspend_cb,
1008         .p = 0,//hcd
1009 };
1010
1011 static struct tasklet_struct host20_reset_tasklet = {
1012         .next = NULL,
1013         .state = 0,
1014         .count = ATOMIC_INIT(0),
1015         .func = reset_tasklet_func,
1016         .data = 0,
1017 };
1018
1019 int __devinit host20_hcd_init(struct device *dev)
1020 {
1021         struct usb_hcd *hcd = NULL;
1022         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1023     dwc_otg_device_t *otg_dev = dev->platform_data;
1024
1025         int             num_channels;
1026         int             i;
1027         dwc_hc_t        *channel;
1028
1029         int retval = 0;
1030 #if 1  //kaiker .these code must execute before usb_create_hcd
1031         /* Set device flags indicating whether the HCD supports DMA. */
1032         static u64 usb_dmamask = 0xffffffffUL;
1033         if (otg_dev->core_if->dma_enable) {
1034 //              DWC_PRINT("Using DMA mode\n");
1035                 dev->dma_mask = &usb_dmamask;
1036                 dev->coherent_dma_mask = ~0;
1037         } else {
1038 //              DWC_PRINT("Using Slave mode\n");
1039                 dev->dma_mask = (void *)0;
1040                 dev->coherent_dma_mask = 0;
1041         }
1042 #endif
1043         DWC_PRINT("%s everest\n",__func__);
1044 //      g_dbg_lvl = 0xff;
1045
1046         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1047
1048         /*
1049          * Allocate memory for the base HCD plus the DWC OTG HCD.
1050          * Initialize the base HCD.
1051          */
1052         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1053         if (hcd == NULL) {
1054                 retval = -ENOMEM;
1055                 goto error1;
1056         }
1057         hcd->regs = otg_dev->base;
1058         hcd->self.otg_port = 1;
1059
1060         /* Initialize the DWC OTG HCD. */
1061         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1062         dwc_otg_hcd->core_if = otg_dev->core_if;
1063         otg_dev->hcd = dwc_otg_hcd;
1064
1065 #ifdef CONFIG_USB20_HOST_EN
1066         dwc_otg_hcd->host_enabled = 1;
1067 #else
1068         dwc_otg_hcd->host_enabled = 0;
1069 #endif
1070
1071         spin_lock_init(&dwc_otg_hcd->global_lock);
1072
1073
1074         /* Register the HCD CIL Callbacks */
1075         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1076                                            &host20_cil_callbacks, hcd);
1077
1078         /* Initialize the non-periodic schedule. */
1079         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1080         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1081
1082         /* Initialize the periodic schedule. */
1083         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1084         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1085         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1086         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1087
1088         /*
1089          * Create a host channel descriptor for each host channel implemented
1090          * in the controller. Initialize the channel descriptor array.
1091          */
1092         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1093         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1094         for (i = 0; i < num_channels; i++) {
1095                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1096                 if (channel == NULL) {
1097                         retval = -ENOMEM;
1098                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1099                         goto error2;
1100                 }
1101                 memset(channel, 0, sizeof(dwc_hc_t));
1102                 channel->hc_num = i;
1103                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1104 #ifdef DEBUG
1105                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1106 #endif
1107
1108                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1109         }
1110
1111         /* Initialize the Connection timeout timer. */
1112         init_timer( &dwc_otg_hcd->conn_timer );
1113
1114         /* Initialize reset tasklet. */
1115         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1116         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1117         /*
1118          * Finish generic HCD initialization and start the HCD. This function
1119          * allocates the DMA buffer pool, registers the USB bus, requests the
1120          * IRQ line, and calls dwc_otg_hcd_start method.
1121          */
1122         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1123                                         IRQF_SHARED);
1124         if (retval < 0) {
1125                 DWC_ERROR("usb_add_hcd fail,everest\n");
1126                 goto error2;
1127         }
1128         /*
1129          * Allocate space for storing data on status transactions. Normally no
1130          * data is sent, but this space acts as a bit bucket. This must be
1131          * done after usb_add_hcd since that function allocates the DMA buffer
1132          * pool.
1133          */
1134         if (otg_dev->core_if->dma_enable) {
1135                 dwc_otg_hcd->status_buf =
1136                         dma_alloc_coherent(dev,
1137                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1138                                            &dwc_otg_hcd->status_buf_dma,
1139                                            GFP_KERNEL | GFP_DMA);
1140         } else {
1141                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1142                                                   GFP_KERNEL);
1143         }
1144         if (dwc_otg_hcd->status_buf == NULL) {
1145                 retval = -ENOMEM;
1146                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1147                 goto error3;
1148         }
1149
1150         DWC_PRINT("%s end,everest\n",__func__);
1151
1152         return 0;
1153
1154         /* Error conditions */
1155  error3:
1156         usb_remove_hcd(hcd);
1157  error2:
1158         dwc_otg_hcd_free(hcd);
1159         usb_put_hcd(hcd);
1160
1161  error1:
1162         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1163         return retval;
1164 }
1165 #endif
1166
1167 /**
1168  * Removes the HCD.
1169  * Frees memory and resources associated with the HCD and deregisters the bus.
1170  */
1171 void dwc_otg_hcd_remove(struct device *dev)
1172 {
1173         dwc_otg_device_t *otg_dev = dev->platform_data;
1174     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1175         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1176
1177         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1178
1179         /* Turn off all interrupts */
1180         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1181         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1182
1183         usb_remove_hcd(hcd);
1184         dwc_otg_hcd_free(hcd);
1185         usb_put_hcd(hcd);
1186
1187         return;
1188 }
1189
1190
1191 /* =========================================================================
1192  *  Linux HC Driver Functions
1193  * ========================================================================= */
1194
1195 /**
1196  * Initializes dynamic portions of the DWC_otg HCD state.
1197  */
1198 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1199 {
1200         struct list_head        *item;
1201         int                     num_channels;
1202         int                     i;
1203         dwc_hc_t                *channel;
1204         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1205
1206         _hcd->flags.d32 = 0;
1207
1208         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1209         _hcd->non_periodic_channels = 0;
1210         _hcd->periodic_channels = 0;
1211
1212         /*
1213          * Put all channels in the free channel list and clean up channel
1214          * states.
1215          */
1216         item = _hcd->free_hc_list.next;
1217         while (item != &_hcd->free_hc_list) {
1218                 list_del(item);
1219                 item = _hcd->free_hc_list.next;
1220         }
1221         num_channels = _hcd->core_if->core_params->host_channels;
1222         for (i = 0; i < num_channels; i++) {
1223                 channel = _hcd->hc_ptr_array[i];
1224                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1225                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1226         }
1227
1228         /* Initialize the DWC core for host mode operation. */
1229         dwc_otg_core_host_init(_hcd->core_if);
1230 }
1231
1232 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1233  * mode operation. Activates the root port. Returns 0 on success and a negative
1234  * error code on failure. */
1235 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1236 {
1237     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1238     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1239         unsigned long flags;
1240
1241         struct usb_bus *bus;
1242
1243         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1244         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1245
1246         DWC_PRINT("dwc_otg_hcd_start! everest\n");
1247         bus = hcd_to_bus(_hcd);
1248         _hcd->state = HC_STATE_RUNNING;
1249
1250         /* Initialize and connect root hub if one is not already attached */
1251         if (bus->root_hub) {
1252                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1253                 /* Inform the HUB driver to resume. */
1254                 usb_hcd_resume_root_hub(_hcd);
1255         }
1256         else {
1257             /*
1258              * no use
1259              * yk@rk 2010121
1260             struct usb_device *udev;6
1261                 udev = usb_alloc_dev(NULL, bus, 0);
1262                 udev->speed = USB_SPEED_HIGH;
1263                 if (!udev) {
1264                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1265                         return -ENODEV;
1266                 }
1267         */
1268             /* Not needed - VJ
1269                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1270                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1271                return -ENODEV;
1272                }
1273              */
1274         }
1275         /* Initialize the bus state.  If the core is in Device Mode
1276          * HALT the USB bus and return. */
1277         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1278                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1279                 //_hcd->state = HC_STATE_HALT;
1280                 goto out;
1281         }
1282         hcd_reinit(dwc_otg_hcd);
1283 out:
1284         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1285
1286         return 0;
1287 }
1288
1289 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1290 {
1291         struct list_head        *item;
1292         dwc_otg_qh_t            *qh;
1293
1294         if (_qh_list->next == NULL) {
1295                 /* The list hasn't been initialized yet. */
1296                 return;
1297         }
1298
1299         /* Ensure there are no QTDs or URBs left. */
1300         kill_urbs_in_qh_list(_hcd, _qh_list);
1301
1302         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1303                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1304                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1305         }
1306 }
1307
1308 /**
1309  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1310  * stopped.
1311  */
1312 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1313 {
1314         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1315         hprt0_data_t hprt0 = { .d32=0 };
1316
1317         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1318
1319         /* Turn off all host-specific interrupts. */
1320         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1321
1322         /*
1323          * The root hub should be disconnected before this function is called.
1324          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1325          * and the QH lists (via ..._hcd_endpoint_disable).
1326          */
1327
1328         /* Turn off the vbus power */
1329         DWC_PRINT("PortPower off\n");
1330         hprt0.b.prtpwr = 0;
1331         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1332
1333         return;
1334 }
1335
1336
1337 /** Returns the current frame number. */
1338 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1339 {
1340         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1341         hfnum_data_t hfnum;
1342
1343         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1344                                    host_if->host_global_regs->hfnum);
1345
1346 #ifdef DEBUG_SOF
1347         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1348 #endif
1349         return hfnum.b.frnum;
1350 }
1351
1352 /**
1353  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1354  * in the struct usb_hcd field.
1355  */
1356 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1357 {
1358         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1359         int             i;
1360
1361         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1362
1363         del_timers(dwc_otg_hcd);
1364
1365         /* Free memory for QH/QTD lists */
1366         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1367         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1368         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1369         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1370         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1371         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1372
1373         /* Free memory for the host channels. */
1374         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1375                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1376                 if (hc != NULL) {
1377                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1378                         kfree(hc);
1379                 }
1380         }
1381
1382         if (dwc_otg_hcd->core_if->dma_enable) {
1383                 if (dwc_otg_hcd->status_buf_dma) {
1384                         dma_free_coherent(_hcd->self.controller,
1385                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1386                                           dwc_otg_hcd->status_buf,
1387                                           dwc_otg_hcd->status_buf_dma);
1388                 }
1389         } else if (dwc_otg_hcd->status_buf != NULL) {
1390                 kfree(dwc_otg_hcd->status_buf);
1391         }
1392
1393         return;
1394 }
1395
1396
1397 #ifdef DEBUG
1398 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1399 {
1400         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1401         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1402                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1403         DWC_PRINT("  Endpoint type: %s\n",
1404                   ({char *pipetype;
1405                   switch (usb_pipetype(_urb->pipe)) {
1406                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1407                   case PIPE_BULK: pipetype = "BULK"; break;
1408                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1409                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1410                   default: pipetype = "UNKNOWN"; break;
1411                   }; pipetype;}));
1412         DWC_PRINT("  Speed: %s\n",
1413                   ({char *speed;
1414                   switch (_urb->dev->speed) {
1415                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1416                   case USB_SPEED_FULL: speed = "FULL"; break;
1417                   case USB_SPEED_LOW: speed = "LOW"; break;
1418                   default: speed = "UNKNOWN"; break;
1419                   }; speed;}));
1420         DWC_PRINT("  Max packet size: %d\n",
1421                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1422         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1423         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1424                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1425         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1426                   _urb->setup_packet, (void *)_urb->setup_dma);
1427         DWC_PRINT("  Interval: %d\n", _urb->interval);
1428         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1429                 int i;
1430                 for (i = 0; i < _urb->number_of_packets;  i++) {
1431                         DWC_PRINT("  ISO Desc %d:\n", i);
1432                         DWC_PRINT("    offset: %d, length %d\n",
1433                                   _urb->iso_frame_desc[i].offset,
1434                                   _urb->iso_frame_desc[i].length);
1435                 }
1436         }
1437 }
1438
1439 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1440                               dwc_otg_qh_t *qh)
1441 {
1442         if (qh->channel != NULL) {
1443                 dwc_hc_t *hc = qh->channel;
1444                 struct list_head *item;
1445                 dwc_otg_qh_t *qh_item;
1446                 int num_channels = _hcd->core_if->core_params->host_channels;
1447                 int i;
1448
1449                 dwc_otg_hc_regs_t *hc_regs;
1450                 hcchar_data_t   hcchar;
1451                 hcsplt_data_t   hcsplt;
1452                 hctsiz_data_t   hctsiz;
1453                 uint32_t        hcdma;
1454
1455                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1456                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1457                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1458                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1459                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1460
1461                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1462                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1463                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1464                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1465                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1466                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1467                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1468                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1469                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1470                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1471                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1472                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1473                 DWC_PRINT("    qh: %p\n", hc->qh);
1474                 DWC_PRINT("  NP inactive sched:\n");
1475                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1476                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1477                         DWC_PRINT("    %p\n", qh_item);
1478                 }
1479                 DWC_PRINT("  NP active sched:\n");
1480                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1481                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1482                         DWC_PRINT("    %p\n", qh_item);
1483                 }
1484                 DWC_PRINT("  Channels: \n");
1485                 for (i = 0; i < num_channels; i++) {
1486                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1487                         DWC_PRINT("    %2d: %p\n", i, hc);
1488                 }
1489         }
1490 }
1491 #endif
1492
1493 /** Starts processing a USB transfer request specified by a USB Request Block
1494  * (URB). mem_flags indicates the type of memory allocation to use while
1495  * processing this URB. */
1496 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1497                             struct urb *_urb,
1498                             gfp_t _mem_flags)
1499 {
1500         int retval;
1501         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1502         dwc_otg_qtd_t * qtd;
1503         unsigned long flags;
1504
1505         retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
1506         if (retval)
1507         {
1508                 DWC_PRINT("%s, usb_hcd_link_urb_to_ep error\n", __func__);
1509                 return retval;
1510         }
1511         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1512 #if 1
1513         /*
1514          * Make sure the start of frame interrupt is enabled now that
1515          * we know we should have queued data. The SOF interrupt
1516          * handler automatically disables itself when idle to reduce
1517          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1518          * for the disable
1519          */
1520         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1521                          DWC_SOF_INTR_MASK);
1522 #endif
1523 #ifdef DEBUG
1524             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1525                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1526         }
1527 #endif  /*  */
1528     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1529             /* No longer connected. */
1530                 retval =  -ENODEV;
1531                 goto out;
1532         }
1533         qtd = dwc_otg_hcd_qtd_create(_urb);
1534         if (qtd == NULL) {
1535                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1536                 retval = -ENOMEM;
1537                 goto out;
1538         }
1539         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1540         if (retval < 0) {
1541                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1542                            "Error status %d\n", retval);
1543                 dwc_otg_hcd_qtd_free(qtd);
1544         }
1545 out:
1546         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1547
1548         return retval;
1549 }
1550
1551 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1552  * success.  */
1553 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1554 {
1555         unsigned long flags;
1556         dwc_otg_hcd_t * dwc_otg_hcd;
1557         dwc_otg_qtd_t * urb_qtd;
1558         dwc_otg_qh_t * qh;
1559         struct usb_host_endpoint *_ep = _urb->ep;//dwc_urb_to_endpoint(_urb);
1560         int retval;
1561
1562         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1563         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1564         if(_ep==NULL)
1565         {
1566                 DWC_PRINT("%s=====================================================\n",__func__);
1567                 DWC_PRINT("urb->ep is null\n");
1568                 return -1;
1569         }
1570         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1571         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1572         retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
1573         if (retval) {
1574                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1575                 return retval;
1576         }
1577         if(urb_qtd == NULL)
1578         {
1579                 DWC_PRINT("%s,urb_qtd is null\n",__func__);
1580                 goto urb_qtd_null;
1581                 //return -1;
1582         }
1583         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1584
1585 #ifdef DEBUG
1586     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1587                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1588                 if (urb_qtd == qh->qtd_in_process) {
1589                         dump_channel_info(dwc_otg_hcd, qh);
1590                 }
1591         }
1592
1593 #endif  /*  */
1594 #if 1
1595     if (urb_qtd == qh->qtd_in_process) {
1596             /* The QTD is in process (it has been assigned to a channel). */
1597             if (dwc_otg_hcd->flags.b.port_connect_status) {
1598
1599                     /*
1600                      * If still connected (i.e. in host mode), halt the
1601                      * channel so it can be used for other transfers. If
1602                      * no longer connected, the host registers can't be
1603                      * written to halt the channel since the core is in
1604                      * device mode.
1605                      */
1606                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1607                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1608                 }
1609         }
1610
1611     /*
1612      * Free the QTD and clean up the associated QH. Leave the QH in the
1613      * schedule if it has any remaining QTDs.
1614      */
1615     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1616         if (urb_qtd == qh->qtd_in_process) {
1617                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1618                 qh->channel = NULL;
1619                 qh->qtd_in_process = NULL;
1620         } else if (list_empty(&qh->qtd_list)) {
1621                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1622         }
1623 #endif
1624
1625 urb_qtd_null:
1626         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1627         _urb->hcpriv = NULL;
1628         usb_hcd_unlink_urb_from_ep(_hcd, _urb);
1629     /* Higher layer software sets URB status. */
1630         usb_hcd_giveback_urb(_hcd, _urb, _status);
1631         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1632                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1633                 DWC_PRINT("  urb->status = %d\n", _status);
1634         }
1635         return 0;
1636 }
1637
1638
1639 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1640  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1641  * must already be dequeued. */
1642 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1643                                   struct usb_host_endpoint *_ep)
1644
1645 {
1646         unsigned long flags;
1647         dwc_otg_qh_t *qh;
1648         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1649
1650         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1651
1652         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1653                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1654                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1655
1656         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1657         if (qh != NULL) {
1658 #ifdef DEBUG
1659                 /** Check that the QTD list is really empty */
1660                 if (!list_empty(&qh->qtd_list)) {
1661                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1662                                  " QTD List for this endpoint is not empty\n");
1663                 }
1664 #endif
1665
1666                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1667                 _ep->hcpriv = NULL;
1668         }
1669
1670         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1671
1672         return;
1673 }
1674
1675 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1676  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1677  * interrupt.
1678  *
1679  * This function is called by the USB core when an interrupt occurs */
1680 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1681 {
1682         irqreturn_t result;
1683         unsigned long flags;
1684         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1685
1686         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1687
1688         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1689
1690         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1691
1692         return result;
1693 }
1694
1695 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1696  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1697  * is the status change indicator for the single root port. Returns 1 if either
1698  * change indicator is 1, otherwise returns 0. */
1699 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1700                                 char *_buf)
1701 {
1702         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1703
1704         _buf[0] = 0;
1705         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1706                     dwc_otg_hcd->flags.b.port_reset_change ||
1707                     dwc_otg_hcd->flags.b.port_enable_change ||
1708                     dwc_otg_hcd->flags.b.port_suspend_change ||
1709                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1710
1711 #ifdef DEBUG
1712         if (_buf[0]) {
1713                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1714                             " Root port status changed\n");
1715                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1716                             dwc_otg_hcd->flags.b.port_connect_status_change);
1717                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1718                             dwc_otg_hcd->flags.b.port_reset_change);
1719                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1720                             dwc_otg_hcd->flags.b.port_enable_change);
1721                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1722                             dwc_otg_hcd->flags.b.port_suspend_change);
1723                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1724                             dwc_otg_hcd->flags.b.port_over_current_change);
1725         }
1726 #endif
1727         return (_buf[0] != 0);
1728 }
1729
1730 #ifdef DWC_HS_ELECT_TST
1731 /*
1732  * Quick and dirty hack to implement the HS Electrical Test
1733  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1734  *
1735  * This code was copied from our userspace app "hset". It sends a
1736  * Get Device Descriptor control sequence in two parts, first the
1737  * Setup packet by itself, followed some time later by the In and
1738  * Ack packets. Rather than trying to figure out how to add this
1739  * functionality to the normal driver code, we just hijack the
1740  * hardware, using these two function to drive the hardware
1741  * directly.
1742  */
1743
1744 dwc_otg_core_global_regs_t *global_regs;
1745 dwc_otg_host_global_regs_t *hc_global_regs;
1746 dwc_otg_hc_regs_t *hc_regs;
1747 uint32_t *data_fifo;
1748
1749 static void do_setup(void)
1750 {
1751         gintsts_data_t gintsts;
1752         hctsiz_data_t hctsiz;
1753         hcchar_data_t hcchar;
1754         haint_data_t haint;
1755         hcint_data_t hcint;
1756
1757         /* Enable HAINTs */
1758         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1759
1760         /* Enable HCINTs */
1761         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1762
1763         /* Read GINTSTS */
1764         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1765         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1766
1767         /* Read HAINT */
1768         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1769         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1770
1771         /* Read HCINT */
1772         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1773         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1774
1775         /* Read HCCHAR */
1776         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1777         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1778
1779         /* Clear HCINT */
1780         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1781
1782         /* Clear HAINT */
1783         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1784
1785         /* Clear GINTSTS */
1786         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1787
1788         /* Read GINTSTS */
1789         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1790         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1791
1792         /*
1793          * Send Setup packet (Get Device Descriptor)
1794          */
1795
1796         /* Make sure channel is disabled */
1797         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1798         if (hcchar.b.chen) {
1799                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1800                 hcchar.b.chdis = 1;
1801 //              hcchar.b.chen = 1;
1802                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1803                 //sleep(1);
1804                 mdelay(1000);
1805
1806                 /* Read GINTSTS */
1807                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1808                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1809
1810                 /* Read HAINT */
1811                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1812                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1813
1814                 /* Read HCINT */
1815                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1816                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1817
1818                 /* Read HCCHAR */
1819                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1820                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1821
1822                 /* Clear HCINT */
1823                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1824
1825                 /* Clear HAINT */
1826                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1827
1828                 /* Clear GINTSTS */
1829                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1830
1831                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1832                 //if (hcchar.b.chen) {
1833                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1834                 //}
1835         }
1836
1837         /* Set HCTSIZ */
1838         hctsiz.d32 = 0;
1839         hctsiz.b.xfersize = 8;
1840         hctsiz.b.pktcnt = 1;
1841         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1842         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1843
1844         /* Set HCCHAR */
1845         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1846         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1847         hcchar.b.epdir = 0;
1848         hcchar.b.epnum = 0;
1849         hcchar.b.mps = 8;
1850         hcchar.b.chen = 1;
1851         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1852
1853         /* Fill FIFO with Setup data for Get Device Descriptor */
1854         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1855         dwc_write_reg32(data_fifo++, 0x01000680);
1856         dwc_write_reg32(data_fifo++, 0x00080000);
1857
1858         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1859         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1860
1861         /* Wait for host channel interrupt */
1862         do {
1863                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1864         } while (gintsts.b.hcintr == 0);
1865
1866         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1867
1868         /* Disable HCINTs */
1869         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1870
1871         /* Disable HAINTs */
1872         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1873
1874         /* Read HAINT */
1875         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1876         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1877
1878         /* Read HCINT */
1879         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1880         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1881
1882         /* Read HCCHAR */
1883         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1884         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1885
1886         /* Clear HCINT */
1887         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1888
1889         /* Clear HAINT */
1890         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1891
1892         /* Clear GINTSTS */
1893         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1894
1895         /* Read GINTSTS */
1896         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1897         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1898 }
1899
1900 static void do_in_ack(void)
1901 {
1902         gintsts_data_t gintsts;
1903         hctsiz_data_t hctsiz;
1904         hcchar_data_t hcchar;
1905         haint_data_t haint;
1906         hcint_data_t hcint;
1907         host_grxsts_data_t grxsts;
1908
1909         /* Enable HAINTs */
1910         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1911
1912         /* Enable HCINTs */
1913         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1914
1915         /* Read GINTSTS */
1916         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1917         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1918
1919         /* Read HAINT */
1920         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1921         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1922
1923         /* Read HCINT */
1924         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1925         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1926
1927         /* Read HCCHAR */
1928         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1929         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1930
1931         /* Clear HCINT */
1932         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1933
1934         /* Clear HAINT */
1935         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1936
1937         /* Clear GINTSTS */
1938         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1939
1940         /* Read GINTSTS */
1941         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1942         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1943
1944         /*
1945          * Receive Control In packet
1946          */
1947
1948         /* Make sure channel is disabled */
1949         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1950         if (hcchar.b.chen) {
1951                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1952                 hcchar.b.chdis = 1;
1953                 hcchar.b.chen = 1;
1954                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1955                 //sleep(1);
1956                 mdelay(1000);
1957
1958                 /* Read GINTSTS */
1959                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1960                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1961
1962                 /* Read HAINT */
1963                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1964                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1965
1966                 /* Read HCINT */
1967                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1968                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1969
1970                 /* Read HCCHAR */
1971                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1972                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1973
1974                 /* Clear HCINT */
1975                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1976
1977                 /* Clear HAINT */
1978                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1979
1980                 /* Clear GINTSTS */
1981                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1982
1983                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1984                 //if (hcchar.b.chen) {
1985                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
1986                 //}
1987         }
1988
1989         /* Set HCTSIZ */
1990         hctsiz.d32 = 0;
1991         hctsiz.b.xfersize = 8;
1992         hctsiz.b.pktcnt = 1;
1993         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1994         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1995
1996         /* Set HCCHAR */
1997         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1998         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1999         hcchar.b.epdir = 1;
2000         hcchar.b.epnum = 0;
2001         hcchar.b.mps = 8;
2002         hcchar.b.chen = 1;
2003         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2004
2005         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2006         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2007
2008         /* Wait for receive status queue interrupt */
2009         do {
2010                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2011         } while (gintsts.b.rxstsqlvl == 0);
2012
2013         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2014
2015         /* Read RXSTS */
2016         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2017         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2018
2019         /* Clear RXSTSQLVL in GINTSTS */
2020         gintsts.d32 = 0;
2021         gintsts.b.rxstsqlvl = 1;
2022         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2023
2024         switch (grxsts.b.pktsts) {
2025         case DWC_GRXSTS_PKTSTS_IN:
2026                 /* Read the data into the host buffer */
2027                 if (grxsts.b.bcnt > 0) {
2028                         int i;
2029                         int word_count = (grxsts.b.bcnt + 3) / 4;
2030
2031                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2032
2033                         for (i = 0; i < word_count; i++) {
2034                                 (void)dwc_read_reg32(data_fifo++);
2035                         }
2036                 }
2037
2038                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2039         break;
2040
2041         default:
2042                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2043         break;
2044         }
2045
2046         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2047         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2048
2049         /* Wait for receive status queue interrupt */
2050         do {
2051                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2052         } while (gintsts.b.rxstsqlvl == 0);
2053
2054         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2055
2056         /* Read RXSTS */
2057         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2058         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2059
2060         /* Clear RXSTSQLVL in GINTSTS */
2061         gintsts.d32 = 0;
2062         gintsts.b.rxstsqlvl = 1;
2063         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2064
2065         switch (grxsts.b.pktsts) {
2066         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2067         break;
2068
2069         default:
2070                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2071         break;
2072         }
2073
2074         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2075         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2076
2077         /* Wait for host channel interrupt */
2078         do {
2079                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2080         } while (gintsts.b.hcintr == 0);
2081
2082         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2083
2084         /* Read HAINT */
2085         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2086         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2087
2088         /* Read HCINT */
2089         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2090         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2091
2092         /* Read HCCHAR */
2093         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2094         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2095
2096         /* Clear HCINT */
2097         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2098
2099         /* Clear HAINT */
2100         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2101
2102         /* Clear GINTSTS */
2103         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2104
2105         /* Read GINTSTS */
2106         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2107         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2108
2109 //      usleep(100000);
2110 //      mdelay(100);
2111         mdelay(1);
2112
2113         /*
2114          * Send handshake packet
2115          */
2116
2117         /* Read HAINT */
2118         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2119         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2120
2121         /* Read HCINT */
2122         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2123         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2124
2125         /* Read HCCHAR */
2126         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2127         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2128
2129         /* Clear HCINT */
2130         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2131
2132         /* Clear HAINT */
2133         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2134
2135         /* Clear GINTSTS */
2136         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2137
2138         /* Read GINTSTS */
2139         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2140         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2141
2142         /* Make sure channel is disabled */
2143         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2144         if (hcchar.b.chen) {
2145                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2146                 hcchar.b.chdis = 1;
2147                 hcchar.b.chen = 1;
2148                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2149                 //sleep(1);
2150                 mdelay(1000);
2151
2152                 /* Read GINTSTS */
2153                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2154                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2155
2156                 /* Read HAINT */
2157                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2158                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2159
2160                 /* Read HCINT */
2161                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2162                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2163
2164                 /* Read HCCHAR */
2165                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2166                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2167
2168                 /* Clear HCINT */
2169                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2170
2171                 /* Clear HAINT */
2172                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2173
2174                 /* Clear GINTSTS */
2175                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2176
2177                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2178                 //if (hcchar.b.chen) {
2179                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2180                 //}
2181         }
2182
2183         /* Set HCTSIZ */
2184         hctsiz.d32 = 0;
2185         hctsiz.b.xfersize = 0;
2186         hctsiz.b.pktcnt = 1;
2187         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2188         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2189
2190         /* Set HCCHAR */
2191         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2192         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2193         hcchar.b.epdir = 0;
2194         hcchar.b.epnum = 0;
2195         hcchar.b.mps = 8;
2196         hcchar.b.chen = 1;
2197         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2198
2199         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2200         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2201
2202         /* Wait for host channel interrupt */
2203         do {
2204                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2205         } while (gintsts.b.hcintr == 0);
2206
2207         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2208
2209         /* Disable HCINTs */
2210         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2211
2212         /* Disable HAINTs */
2213         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2214
2215         /* Read HAINT */
2216         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2217         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2218
2219         /* Read HCINT */
2220         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2221         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2222
2223         /* Read HCCHAR */
2224         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2225         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2226
2227         /* Clear HCINT */
2228         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2229
2230         /* Clear HAINT */
2231         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2232
2233         /* Clear GINTSTS */
2234         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2235
2236         /* Read GINTSTS */
2237         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2238         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2239 }
2240 #endif /* DWC_HS_ELECT_TST */
2241
2242 /** Handles hub class-specific requests.*/
2243 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2244                             u16 _typeReq,
2245                             u16 _wValue,
2246                             u16 _wIndex,
2247                             char *_buf,
2248                             u16 _wLength)
2249 {
2250         int retval = 0;
2251         unsigned long flags;
2252
2253         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2254         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2255         struct usb_hub_descriptor *desc;
2256         hprt0_data_t hprt0 = {.d32 = 0};
2257
2258         uint32_t port_status;
2259         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2260
2261         switch (_typeReq) {
2262         case ClearHubFeature:
2263                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2264                             "ClearHubFeature 0x%x\n", _wValue);
2265                 switch (_wValue) {
2266                 case C_HUB_LOCAL_POWER:
2267                 case C_HUB_OVER_CURRENT:
2268                         /* Nothing required here */
2269                         break;
2270                 default:
2271                         retval = -EINVAL;
2272                         DWC_ERROR ("DWC OTG HCD - "
2273                                    "ClearHubFeature request %xh unknown\n", _wValue);
2274                 }
2275                 break;
2276         case ClearPortFeature:
2277                 if (!_wIndex || _wIndex > 1)
2278                         goto error;
2279
2280                 switch (_wValue) {
2281                 case USB_PORT_FEAT_ENABLE:
2282                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2283                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2284                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2285                         hprt0.b.prtena = 1;
2286                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2287                         break;
2288                 case USB_PORT_FEAT_SUSPEND:
2289                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2290                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2291                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2292                         hprt0.b.prtres = 1;
2293                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2294                         /* Clear Resume bit */
2295                         mdelay (100);
2296                         hprt0.b.prtres = 0;
2297                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2298                         break;
2299                 case USB_PORT_FEAT_POWER:
2300                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2301                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2302                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2303                         hprt0.b.prtpwr = 0;
2304                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2305                         break;
2306                 case USB_PORT_FEAT_INDICATOR:
2307                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2308                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2309                         /* Port inidicator not supported */
2310                         break;
2311                 case USB_PORT_FEAT_C_CONNECTION:
2312                         /* Clears drivers internal connect status change
2313                          * flag */
2314                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2315                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2316                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2317                         break;
2318                 case USB_PORT_FEAT_C_RESET:
2319                         /* Clears the driver's internal Port Reset Change
2320                          * flag */
2321                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2322                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2323                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2324                         break;
2325                 case USB_PORT_FEAT_C_ENABLE:
2326                         /* Clears the driver's internal Port
2327                          * Enable/Disable Change flag */
2328                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2329                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2330                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2331                         break;
2332                 case USB_PORT_FEAT_C_SUSPEND:
2333                         /* Clears the driver's internal Port Suspend
2334                          * Change flag, which is set when resume signaling on
2335                          * the host port is complete */
2336                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2337                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2338                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2339                         break;
2340                 case USB_PORT_FEAT_C_OVER_CURRENT:
2341                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2342                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2343                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2344                         break;
2345                 default:
2346                         retval = -EINVAL;
2347                         DWC_ERROR ("DWC OTG HCD - "
2348                                    "ClearPortFeature request %xh "
2349                                    "unknown or unsupported\n", _wValue);
2350                 }
2351                 break;
2352         case GetHubDescriptor:
2353                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2354                              "GetHubDescriptor\n");
2355                 desc = (struct usb_hub_descriptor *)_buf;
2356                 desc->bDescLength = 9;
2357                 desc->bDescriptorType = 0x29;
2358                 desc->bNbrPorts = 1;
2359                 desc->wHubCharacteristics = 0x08;
2360                 desc->bPwrOn2PwrGood = 1;
2361                 desc->bHubContrCurrent = 0;
2362                 desc->bitmap[0] = 0;
2363                 desc->bitmap[1] = 0xff;
2364                 break;
2365         case GetHubStatus:
2366                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2367                              "GetHubStatus\n");
2368                 memset (_buf, 0, 4);
2369                 break;
2370         case GetPortStatus:
2371                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2372                              "GetPortStatus\n");
2373
2374                 if (!_wIndex || _wIndex > 1)
2375                         goto error;
2376
2377                 port_status = 0;
2378
2379                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2380                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2381
2382                 if (dwc_otg_hcd->flags.b.port_enable_change)
2383                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2384
2385                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2386                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2387
2388                 if (dwc_otg_hcd->flags.b.port_reset_change)
2389                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2390
2391                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2392                         DWC_ERROR("Device Not Supported\n");
2393                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2394                 }
2395
2396                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2397                         /*
2398                          * The port is disconnected, which means the core is
2399                          * either in device mode or it soon will be. Just
2400                          * return 0's for the remainder of the port status
2401                          * since the port register can't be read if the core
2402                          * is in device mode.
2403                          */
2404                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2405                         break;
2406                 }
2407
2408                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2409                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2410
2411                 if (hprt0.b.prtconnsts)
2412                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2413
2414                 if (hprt0.b.prtena)
2415                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2416
2417                 if (hprt0.b.prtsusp)
2418                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2419
2420                 if (hprt0.b.prtovrcurract)
2421                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2422
2423                 if (hprt0.b.prtrst)
2424                         port_status |= (1 << USB_PORT_FEAT_RESET);
2425
2426                 if (hprt0.b.prtpwr)
2427                         port_status |= (1 << USB_PORT_FEAT_POWER);
2428
2429                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2430                         port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
2431
2432                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2433                         port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
2434
2435                 if (hprt0.b.prttstctl)
2436                         port_status |= (1 << USB_PORT_FEAT_TEST);
2437
2438                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2439
2440                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2441
2442                 break;
2443         case SetHubFeature:
2444                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2445                              "SetHubFeature\n");
2446                 /* No HUB features supported */
2447                 break;
2448         case SetPortFeature:
2449                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2450                         goto error;
2451
2452                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2453                         /*
2454                          * The port is disconnected, which means the core is
2455                          * either in device mode or it soon will be. Just
2456                          * return without doing anything since the port
2457                          * register can't be written if the core is in device
2458                          * mode.
2459                          */
2460                         break;
2461                 }
2462
2463                 switch (_wValue) {
2464                 case USB_PORT_FEAT_SUSPEND:
2465                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2466                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2467                         if (_hcd->self.otg_port == _wIndex &&
2468                             _hcd->self.b_hnp_enable) {
2469                                 gotgctl_data_t  gotgctl = {.d32=0};
2470                                 gotgctl.b.hstsethnpen = 1;
2471                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2472                                                   0, gotgctl.d32);
2473                                 core_if->op_state = A_SUSPEND;
2474                         }
2475                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2476                         hprt0.b.prtsusp = 1;
2477                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2478                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2479                         /* Suspend the Phy Clock */
2480                         {
2481                                 pcgcctl_data_t pcgcctl = {.d32=0};
2482                                 pcgcctl.b.stoppclk = 1;
2483                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2484                         }
2485
2486                         /* For HNP the bus must be suspended for at least 200ms.*/
2487                         if (_hcd->self.b_hnp_enable) {
2488                                 mdelay(200);
2489                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2490                         }
2491                         break;
2492                 case USB_PORT_FEAT_POWER:
2493                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2494                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2495                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2496                         hprt0.b.prtpwr = 1;
2497                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2498                         break;
2499                 case USB_PORT_FEAT_RESET:
2500                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2501                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2502                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2503                         /* When B-Host the Port reset bit is set in
2504                          * the Start HCD Callback function, so that
2505                          * the reset is started within 1ms of the HNP
2506                          * success interrupt. */
2507                         if (!_hcd->self.is_b_host) {
2508                                 hprt0.b.prtrst = 1;
2509                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2510                         }
2511                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2512                         MDELAY (60);
2513                         hprt0.b.prtrst = 0;
2514                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2515                         break;
2516
2517 #ifdef DWC_HS_ELECT_TST
2518                 case USB_PORT_FEAT_TEST:
2519                 {
2520                         uint32_t t;
2521                         gintmsk_data_t gintmsk;
2522
2523                         t = (_wIndex >> 8); /* MSB wIndex USB */
2524                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2525                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2526                         warn("USB_PORT_FEAT_TEST %d\n", t);
2527                         if (t < 6) {
2528                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2529                                 hprt0.b.prttstctl = t;
2530                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2531                         } else {
2532                                 /* Setup global vars with reg addresses (quick and
2533                                  * dirty hack, should be cleaned up)
2534                                  */
2535                                 global_regs = core_if->core_global_regs;
2536                                 hc_global_regs = core_if->host_if->host_global_regs;
2537                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2538                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2539
2540                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2541                                         /* Save current interrupt mask */
2542                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2543
2544                                         /* Disable all interrupts while we muck with
2545                                          * the hardware directly
2546                                          */
2547                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2548
2549                                         /* 15 second delay per the test spec */
2550                                         mdelay(15000);
2551
2552                                         /* Drive suspend on the root port */
2553                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2554                                         hprt0.b.prtsusp = 1;
2555                                         hprt0.b.prtres = 0;
2556                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2557
2558                                         /* 15 second delay per the test spec */
2559                                         mdelay(15000);
2560
2561                                         /* Drive resume on the root port */
2562                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2563                                         hprt0.b.prtsusp = 0;
2564                                         hprt0.b.prtres = 1;
2565                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2566                                         mdelay(100);
2567
2568                                         /* Clear the resume bit */
2569                                         hprt0.b.prtres = 0;
2570                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2571
2572                                         /* Restore interrupts */
2573                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2574                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2575                                         /* Save current interrupt mask */
2576                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2577
2578                                         /* Disable all interrupts while we muck with
2579                                          * the hardware directly
2580                                          */
2581                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2582
2583                                         /* 15 second delay per the test spec */
2584                                         mdelay(15000);
2585
2586                                         /* Send the Setup packet */
2587                                         do_setup();
2588
2589                                         /* 15 second delay so nothing else happens for awhile */
2590                                         mdelay(15000);
2591
2592                                         /* Restore interrupts */
2593                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2594                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2595                                         /* Save current interrupt mask */
2596                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2597
2598                                         /* Disable all interrupts while we muck with
2599                                          * the hardware directly
2600                                          */
2601                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2602
2603                                         /* Send the Setup packet */
2604                                         do_setup();
2605
2606                                         /* 15 second delay so nothing else happens for awhile */
2607                                         mdelay(15000);
2608
2609                                         /* Send the In and Ack packets */
2610                                         do_in_ack();
2611
2612                                         /* 15 second delay so nothing else happens for awhile */
2613                                         mdelay(15000);
2614
2615                                         /* Restore interrupts */
2616                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2617                                 }
2618                         }
2619                         break;
2620                 }
2621 #endif /* DWC_HS_ELECT_TST */
2622
2623                 case USB_PORT_FEAT_INDICATOR:
2624                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2625                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2626                         /* Not supported */
2627                         break;
2628                 default:
2629                         retval = -EINVAL;
2630                         DWC_ERROR ("DWC OTG HCD - "
2631                                    "SetPortFeature request %xh "
2632                                    "unknown or unsupported\n", _wValue);
2633                         break;
2634                 }
2635                 break;
2636         default:
2637         error:
2638                 retval = -EINVAL;
2639                 DWC_WARN ("DWC OTG HCD - "
2640                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2641                           _typeReq, _wIndex, _wValue);
2642                 break;
2643         }
2644
2645         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2646         return retval;
2647 }
2648
2649
2650 /**
2651  * Assigns transactions from a QTD to a free host channel and initializes the
2652  * host channel to perform the transactions. The host channel is removed from
2653  * the free list.
2654  *
2655  * @param _hcd The HCD state structure.
2656  * @param _qh Transactions from the first QTD for this QH are selected and
2657  * assigned to a free host channel.
2658  */
2659 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2660 {
2661         dwc_hc_t        *hc;
2662         dwc_otg_qtd_t   *qtd;
2663         struct urb      *urb;
2664
2665         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2666         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2667
2668         /* Remove the host channel from the free list. */
2669         list_del_init(&hc->hc_list_entry);
2670
2671         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2672         urb = qtd->urb;
2673         _qh->channel = hc;
2674         _qh->qtd_in_process = qtd;
2675
2676         /*
2677          * Use usb_pipedevice to determine device address. This address is
2678          * 0 before the SET_ADDRESS command and the correct address afterward.
2679          */
2680         hc->dev_addr = usb_pipedevice(urb->pipe);
2681         hc->ep_num = usb_pipeendpoint(urb->pipe);
2682
2683         if (urb->dev->speed == USB_SPEED_LOW) {
2684                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2685                 /*
2686                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2687                  * device connected.
2688                  */
2689         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2690         } else if (urb->dev->speed == USB_SPEED_FULL) {
2691                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2692                 /*
2693                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2694                  * device connected. warning: only support 1 device at root hub.
2695                  */
2696         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2697         } else {
2698                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2699         }
2700
2701         hc->max_packet = dwc_max_packet(_qh->maxp);
2702
2703         hc->xfer_started = 0;
2704         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2705         hc->error_state = (qtd->error_count > 0);
2706         hc->halt_on_queue = 0;
2707         hc->halt_pending = 0;
2708         hc->requests = 0;
2709
2710         /*
2711          * The following values may be modified in the transfer type section
2712          * below. The xfer_len value may be reduced when the transfer is
2713          * started to accommodate the max widths of the XferSize and PktCnt
2714          * fields in the HCTSIZn register.
2715          */
2716         hc->do_ping = _qh->ping_state;
2717         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2718         hc->data_pid_start = _qh->data_toggle;
2719         hc->multi_count = 1;
2720
2721         if (_hcd->core_if->dma_enable) {
2722                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2723         } else {
2724                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2725         }
2726         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2727         hc->xfer_count = 0;
2728
2729         /*
2730          * Set the split attributes
2731          */
2732         hc->do_split = 0;
2733         if (_qh->do_split) {
2734                 hc->do_split = 1;
2735                 hc->xact_pos = qtd->isoc_split_pos;
2736                 hc->complete_split = qtd->complete_split;
2737                 hc->hub_addr = urb->dev->tt->hub->devnum;
2738                 hc->port_addr = urb->dev->ttport;
2739         }
2740
2741         switch (usb_pipetype(urb->pipe)) {
2742         case PIPE_CONTROL:
2743                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2744                 switch (qtd->control_phase) {
2745                 case DWC_OTG_CONTROL_SETUP:
2746                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2747                         hc->do_ping = 0;
2748                         hc->ep_is_in = 0;
2749                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2750                         if (_hcd->core_if->dma_enable) {
2751                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2752                         } else {
2753                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2754                         }
2755                         hc->xfer_len = 8;
2756                         break;
2757                 case DWC_OTG_CONTROL_DATA:
2758                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2759                         hc->data_pid_start = qtd->data_toggle;
2760                         break;
2761                 case DWC_OTG_CONTROL_STATUS:
2762                         /*
2763                          * Direction is opposite of data direction or IN if no
2764                          * data.
2765                          */
2766                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2767                         if (urb->transfer_buffer_length == 0) {
2768                                 hc->ep_is_in = 1;
2769                         } else {
2770                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2771                         }
2772                         if (hc->ep_is_in) {
2773                                 hc->do_ping = 0;
2774                         }
2775                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2776                         hc->xfer_len = 0;
2777                         if (_hcd->core_if->dma_enable) {
2778                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2779                         } else {
2780                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2781                         }
2782                         break;
2783                 }
2784                 break;
2785         case PIPE_BULK:
2786                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2787                 break;
2788         case PIPE_INTERRUPT:
2789                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2790                 break;
2791         case PIPE_ISOCHRONOUS:
2792                 {
2793                         struct usb_iso_packet_descriptor *frame_desc;
2794                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2795                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2796                         if (_hcd->core_if->dma_enable) {
2797                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2798                         } else {
2799                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2800                         }
2801                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2802                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2803
2804                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2805                                 if (hc->xfer_len <= 188) {
2806                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2807                                 }
2808                                 else {
2809                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2810                                 }
2811                         }
2812                 }
2813                 break;
2814         }
2815
2816         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2817             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2818                 /*
2819                  * This value may be modified when the transfer is started to
2820                  * reflect the actual transfer length.
2821                  */
2822                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2823         }
2824
2825         dwc_otg_hc_init(_hcd->core_if, hc);
2826         hc->qh = _qh;
2827 }
2828
2829 /**
2830  * This function selects transactions from the HCD transfer schedule and
2831  * assigns them to available host channels. It is called from HCD interrupt
2832  * handler functions.
2833  *
2834  * @param _hcd The HCD state structure.
2835  *
2836  * @return The types of new transactions that were assigned to host channels.
2837  */
2838 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2839 {
2840         struct list_head                *qh_ptr;
2841         dwc_otg_qh_t                    *qh;
2842         int                             num_channels;
2843         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2844
2845 #ifdef DEBUG_SOF
2846         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2847 #endif
2848
2849         /* Process entries in the periodic ready list. */
2850         qh_ptr = _hcd->periodic_sched_ready.next;
2851         while (qh_ptr != &_hcd->periodic_sched_ready &&
2852                !list_empty(&_hcd->free_hc_list)) {
2853
2854                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2855                 assign_and_init_hc(_hcd, qh);
2856
2857                 /*
2858                  * Move the QH from the periodic ready schedule to the
2859                  * periodic assigned schedule.
2860                  */
2861                 qh_ptr = qh_ptr->next;
2862                 list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2863
2864                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2865         }
2866
2867         /*
2868          * Process entries in the inactive portion of the non-periodic
2869          * schedule. Some free host channels may not be used if they are
2870          * reserved for periodic transfers.
2871          */
2872         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2873         num_channels = _hcd->core_if->core_params->host_channels;
2874         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2875                 /*yk@rk 20100714
2876                (_hcd->non_periodic_channels <
2877                 num_channels - _hcd->periodic_channels) &&
2878                 */
2879                !list_empty(&_hcd->free_hc_list)) {
2880
2881                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2882                 assign_and_init_hc(_hcd, qh);
2883
2884                 /*
2885                  * Move the QH from the non-periodic inactive schedule to the
2886                  * non-periodic active schedule.
2887                  */
2888                 qh_ptr = qh_ptr->next;
2889                 list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2890
2891                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2892                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2893                 } else {
2894                         ret_val = DWC_OTG_TRANSACTION_ALL;
2895                 }
2896
2897                 _hcd->non_periodic_channels++;
2898         }
2899
2900         return ret_val;
2901 }
2902
2903 /**
2904  * Attempts to queue a single transaction request for a host channel
2905  * associated with either a periodic or non-periodic transfer. This function
2906  * assumes that there is space available in the appropriate request queue. For
2907  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2908  * is available in the appropriate Tx FIFO.
2909  *
2910  * @param _hcd The HCD state structure.
2911  * @param _hc Host channel descriptor associated with either a periodic or
2912  * non-periodic transfer.
2913  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2914  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2915  * transfers.
2916  *
2917  * @return 1 if a request is queued and more requests may be needed to
2918  * complete the transfer, 0 if no more requests are required for this
2919  * transfer, -1 if there is insufficient space in the Tx FIFO.
2920  */
2921 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2922                              dwc_hc_t *_hc,
2923                              uint16_t _fifo_dwords_avail)
2924 {
2925         int retval;
2926
2927         if (_hcd->core_if->dma_enable) {
2928                 if (!_hc->xfer_started) {
2929                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2930                         _hc->qh->ping_state = 0;
2931                 }
2932                 retval = 0;
2933         } else  if (_hc->halt_pending) {
2934                 /* Don't queue a request if the channel has been halted. */
2935                 retval = 0;
2936         } else if (_hc->halt_on_queue) {
2937                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
2938                 retval = 0;
2939         } else if (_hc->do_ping) {
2940                 if (!_hc->xfer_started) {
2941                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2942                 }
2943                 retval = 0;
2944         } else if (!_hc->ep_is_in ||
2945                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2946                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
2947                         if (!_hc->xfer_started) {
2948                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2949                                 retval = 1;
2950                         } else {
2951                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2952                         }
2953                 } else {
2954                         retval = -1;
2955                 }
2956         } else {
2957                 if (!_hc->xfer_started) {
2958                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2959                         retval = 1;
2960                 } else {
2961                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2962                 }
2963         }
2964
2965         return retval;
2966 }
2967
2968 /**
2969  * Processes active non-periodic channels and queues transactions for these
2970  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2971  * FIFO Empty interrupt is enabled if there are more transactions to queue as
2972  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2973  * FIFO Empty interrupt is disabled.
2974  */
2975 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
2976 {
2977         gnptxsts_data_t         tx_status;
2978         struct list_head        *orig_qh_ptr;
2979         dwc_otg_qh_t            *qh;
2980         int                     status;
2981         int                     no_queue_space = 0;
2982         int                     no_fifo_space = 0;
2983         int                     more_to_do = 0;
2984
2985         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
2986
2987         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
2988 #ifdef DEBUG
2989         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2990         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
2991                     tx_status.b.nptxqspcavail);
2992         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
2993                     tx_status.b.nptxfspcavail);
2994 #endif
2995         /*
2996          * Keep track of the starting point. Skip over the start-of-list
2997          * entry.
2998          */
2999         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3000                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3001         }
3002         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3003
3004         /*
3005          * Process once through the active list or until no more space is
3006          * available in the request queue or the Tx FIFO.
3007          */
3008         do {
3009                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3010                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3011                         no_queue_space = 1;
3012                         break;
3013                 }
3014
3015                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3016                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3017
3018                 if (status > 0) {
3019                         more_to_do = 1;
3020                 } else if (status < 0) {
3021                         no_fifo_space = 1;
3022                         break;
3023                 }
3024
3025                 /* Advance to next QH, skipping start-of-list entry. */
3026                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3027                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3028                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3029                 }
3030
3031         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3032
3033         if (!_hcd->core_if->dma_enable) {
3034                 gintmsk_data_t intr_mask = {.d32 = 0};
3035                 intr_mask.b.nptxfempty = 1;
3036
3037 #ifdef DEBUG
3038                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3039                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3040                             tx_status.b.nptxqspcavail);
3041                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3042                             tx_status.b.nptxfspcavail);
3043 #endif
3044                 if (more_to_do || no_queue_space || no_fifo_space) {
3045                         /*
3046                          * May need to queue more transactions as the request
3047                          * queue or Tx FIFO empties. Enable the non-periodic
3048                          * Tx FIFO empty interrupt. (Always use the half-empty
3049                          * level to ensure that new requests are loaded as
3050                          * soon as possible.)
3051                          */
3052                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3053                 } else {
3054                         /*
3055                          * Disable the Tx FIFO empty interrupt since there are
3056                          * no more transactions that need to be queued right
3057                          * now. This function is called from interrupt
3058                          * handlers to queue more transactions as transfer
3059                          * states change.
3060                          */
3061                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3062                 }
3063         }
3064 }
3065
3066 /**
3067  * Processes periodic channels for the next frame and queues transactions for
3068  * these channels to the DWC_otg controller. After queueing transactions, the
3069  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3070  * to queue as Periodic Tx FIFO or request queue space becomes available.
3071  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3072  */
3073 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3074 {
3075         hptxsts_data_t          tx_status;
3076         struct list_head        *qh_ptr;
3077         dwc_otg_qh_t            *qh;
3078         int                     status;
3079         int                     no_queue_space = 0;
3080         int                     no_fifo_space = 0;
3081
3082         dwc_otg_host_global_regs_t *host_regs;
3083         host_regs = _hcd->core_if->host_if->host_global_regs;
3084
3085         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3086 #ifdef DEBUG
3087         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3088         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3089                     tx_status.b.ptxqspcavail);
3090         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3091                     tx_status.b.ptxfspcavail);
3092 #endif
3093
3094         qh_ptr = _hcd->periodic_sched_assigned.next;
3095         while (qh_ptr != &_hcd->periodic_sched_assigned) {
3096                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3097                 if (tx_status.b.ptxqspcavail == 0) {
3098                         no_queue_space = 1;
3099                         break;
3100                 }
3101
3102                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3103
3104                 /*
3105                  * Set a flag if we're queuing high-bandwidth in slave mode.
3106                  * The flag prevents any halts to get into the request queue in
3107                  * the middle of multiple high-bandwidth packets getting queued.
3108                  */
3109                 if ((!_hcd->core_if->dma_enable) &&
3110                     (qh->channel->multi_count > 1))
3111                 {
3112                         _hcd->core_if->queuing_high_bandwidth = 1;
3113                 }
3114
3115                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3116                 if (status < 0) {
3117                         no_fifo_space = 1;
3118                         break;
3119                 }
3120
3121                 /*
3122                  * In Slave mode, stay on the current transfer until there is
3123                  * nothing more to do or the high-bandwidth request count is
3124                  * reached. In DMA mode, only need to queue one request. The
3125                  * controller automatically handles multiple packets for
3126                  * high-bandwidth transfers.
3127                  */
3128                 if (_hcd->core_if->dma_enable ||
3129                     (status == 0 ||
3130                      qh->channel->requests == qh->channel->multi_count)) {
3131                         qh_ptr = qh_ptr->next;
3132                         /*
3133                          * Move the QH from the periodic assigned schedule to
3134                          * the periodic queued schedule.
3135                          */
3136                         list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3137
3138                         /* done queuing high bandwidth */
3139                         _hcd->core_if->queuing_high_bandwidth = 0;
3140                 }
3141         }
3142
3143         if (!_hcd->core_if->dma_enable) {
3144                 dwc_otg_core_global_regs_t *global_regs;
3145                 gintmsk_data_t intr_mask = {.d32 = 0};
3146
3147                 global_regs = _hcd->core_if->core_global_regs;
3148                 intr_mask.b.ptxfempty = 1;
3149 #ifdef DEBUG
3150                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3151                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3152                             tx_status.b.ptxqspcavail);
3153                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3154                             tx_status.b.ptxfspcavail);
3155 #endif
3156                 if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
3157                     no_queue_space || no_fifo_space) {
3158                         /*
3159                          * May need to queue more transactions as the request
3160                          * queue or Tx FIFO empties. Enable the periodic Tx
3161                          * FIFO empty interrupt. (Always use the half-empty
3162                          * level to ensure that new requests are loaded as
3163                          * soon as possible.)
3164                          */
3165                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3166                 } else {
3167                         /*
3168                          * Disable the Tx FIFO empty interrupt since there are
3169                          * no more transactions that need to be queued right
3170                          * now. This function is called from interrupt
3171                          * handlers to queue more transactions as transfer
3172                          * states change.
3173                          */
3174                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3175                 }
3176         }
3177 }
3178
3179 /**
3180  * This function processes the currently active host channels and queues
3181  * transactions for these channels to the DWC_otg controller. It is called
3182  * from HCD interrupt handler functions.
3183  *
3184  * @param _hcd The HCD state structure.
3185  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3186  * periodic, or both).
3187  */
3188 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3189                                     dwc_otg_transaction_type_e _tr_type)
3190 {
3191 #ifdef DEBUG_SOF
3192         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3193 #endif
3194         /* Process host channels associated with periodic transfers. */
3195         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3196              _tr_type == DWC_OTG_TRANSACTION_ALL) &&
3197             !list_empty(&_hcd->periodic_sched_assigned)) {
3198
3199                 process_periodic_channels(_hcd);
3200         }
3201
3202         /* Process host channels associated with non-periodic transfers. */
3203         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3204              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3205                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3206                         process_non_periodic_channels(_hcd);
3207                 } else {
3208                         /*
3209                          * Ensure NP Tx FIFO empty interrupt is disabled when
3210                          * there are no non-periodic transfers to process.
3211                          */
3212                         gintmsk_data_t gintmsk = {.d32 = 0};
3213                         gintmsk.b.nptxfempty = 1;
3214                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3215                                          gintmsk.d32, 0);
3216                 }
3217         }
3218 }
3219
3220 /**
3221  * Sets the final status of an URB and returns it to the device driver. Any
3222  * required cleanup of the URB is performed.
3223  */
3224 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3225                               int _status)
3226 __releases(_hcd->lock)
3227 __acquires(_hcd->lock)
3228 {
3229
3230 #ifdef DEBUG
3231         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3232                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3233                           __func__, _urb, usb_pipedevice(_urb->pipe),
3234                           usb_pipeendpoint(_urb->pipe),
3235                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3236                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3237                         int i;
3238                         for (i = 0; i < _urb->number_of_packets; i++) {
3239                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3240                                           i, _urb->iso_frame_desc[i].status);
3241                         }
3242                 }
3243         }
3244 #endif
3245
3246
3247         _urb->hcpriv = NULL;
3248         usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
3249         spin_unlock(&_hcd->lock);
3250         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3251         spin_lock(&_hcd->lock);
3252 }
3253
3254
3255 /*
3256  * Returns the Queue Head for an URB.
3257  */
3258 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3259 {
3260         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3261         return (dwc_otg_qh_t *) ep->hcpriv;
3262 }
3263
3264 #ifdef DEBUG
3265 void dwc_print_setup_data (uint8_t *setup)
3266 {
3267         int i;
3268         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3269                 DWC_PRINT("Setup Data = MSB ");
3270                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3271                 DWC_PRINT("\n");
3272                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3273                 DWC_PRINT("  bmRequestType Type = ");
3274                 switch ((setup[0]&0x60) >> 5) {
3275                 case 0: DWC_PRINT("Standard\n"); break;
3276                 case 1: DWC_PRINT("Class\n"); break;
3277                 case 2: DWC_PRINT("Vendor\n"); break;
3278                 case 3: DWC_PRINT("Reserved\n"); break;
3279                 }
3280                 DWC_PRINT("  bmRequestType Recipient = ");
3281                 switch (setup[0]&0x1f) {
3282                 case 0: DWC_PRINT("Device\n"); break;
3283                 case 1: DWC_PRINT("Interface\n"); break;
3284                 case 2: DWC_PRINT("Endpoint\n"); break;
3285                 case 3: DWC_PRINT("Other\n"); break;
3286                 default: DWC_PRINT("Reserved\n"); break;
3287                 }
3288                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3289                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3290                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3291                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3292         }
3293 }
3294 #endif
3295
3296 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3297 #if 0
3298         DWC_PRINT("Frame remaining at SOF:\n");
3299         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3300                   _hcd->frrem_samples, _hcd->frrem_accum,
3301                   (_hcd->frrem_samples > 0) ?
3302                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3303
3304         DWC_PRINT("\n");
3305         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3306         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3307                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3308                   (_hcd->core_if->hfnum_7_samples > 0) ?
3309                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3310         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3311         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3312                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3313                   (_hcd->core_if->hfnum_0_samples > 0) ?
3314                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3315         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3316         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3317                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3318                   (_hcd->core_if->hfnum_other_samples > 0) ?
3319                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3320
3321         DWC_PRINT("\n");
3322         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3323         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3324                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3325                   (_hcd->hfnum_7_samples_a > 0) ?
3326                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3327         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3328         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3329                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3330                   (_hcd->hfnum_0_samples_a > 0) ?
3331                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3332         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3333         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3334                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3335                   (_hcd->hfnum_other_samples_a > 0) ?
3336                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3337
3338         DWC_PRINT("\n");
3339         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3340         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3341                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3342                   (_hcd->hfnum_7_samples_b > 0) ?
3343                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3344         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3345         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3346                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3347                   (_hcd->hfnum_0_samples_b > 0) ?
3348                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3349         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3350         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3351                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3352                   (_hcd->hfnum_other_samples_b > 0) ?
3353                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3354 #endif
3355 }
3356
3357 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3358 {
3359 #ifdef DEBUG
3360         int num_channels;
3361         int i;
3362         gnptxsts_data_t np_tx_status;
3363         hptxsts_data_t p_tx_status;
3364
3365         num_channels = _hcd->core_if->core_params->host_channels;
3366         DWC_PRINT("\n");
3367         DWC_PRINT("************************************************************\n");
3368         DWC_PRINT("HCD State:\n");
3369         DWC_PRINT("  Num channels: %d\n", num_channels);
3370         for (i = 0; i < num_channels; i++) {
3371                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3372                 DWC_PRINT("  Channel %d:\n", i);
3373                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3374                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3375                 DWC_PRINT("    speed: %d\n", hc->speed);
3376                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3377                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3378                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3379                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3380                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3381                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3382                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3383                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3384                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3385                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3386                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3387                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3388                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3389                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3390                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3391                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3392                 DWC_PRINT("    requests: %d\n", hc->requests);
3393                 DWC_PRINT("    qh: %p\n", hc->qh);
3394                 if (hc->xfer_started) {
3395                         hfnum_data_t hfnum;
3396                         hcchar_data_t hcchar;
3397                         hctsiz_data_t hctsiz;
3398                         hcint_data_t hcint;
3399                         hcintmsk_data_t hcintmsk;
3400                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3401                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3402                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3403                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3404                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3405                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3406                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3407                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3408                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3409                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3410                 }
3411                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3412                         dwc_otg_qtd_t *qtd;
3413                         struct urb *urb;
3414                         qtd = hc->qh->qtd_in_process;
3415                         urb = qtd->urb;
3416                         DWC_PRINT("    URB Info:\n");
3417                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3418                         if (urb != NULL) {
3419                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3420                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3421                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3422                                 DWC_PRINT("      Max packet size: %d\n",
3423                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3424                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3425                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3426                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3427                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3428                         }
3429                 }
3430         }
3431         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3432         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3433         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3434         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3435         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3436         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3437         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3438         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3439         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3440         dwc_otg_hcd_dump_frrem(_hcd);
3441         dwc_otg_dump_global_registers(_hcd->core_if);
3442         dwc_otg_dump_host_registers(_hcd->core_if);
3443         DWC_PRINT("************************************************************\n");
3444         DWC_PRINT("\n");
3445 #endif
3446 }
3447 #endif /* DWC_DEVICE_ONLY */