drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/clk.h>
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/init.h>
  46 #include <linux/device.h>
  47 #include <linux/errno.h>
  48 #include <linux/list.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/string.h>
  51 #include <linux/dma-mapping.h>
  52 #include <linux/irq.h>
  53 #include <linux/platform_device.h>
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65
  66     if(core_if->op_state == B_PERIPHERAL)
  67     {
  68         DWC_PRINT("%s, usb device mode\n", __func__);
  69         return 0;
  70     }
  71     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  72     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  73     if(hprt0.b.prtconnsts)  // usb device connected
  74     {
  75         //partial power-down
  76         if(!hprt0.b.prtsusp)
  77         {
  78             //hprt0.d32 = 0;
  79             hprt0.b.prtsusp = 1;
  80             hprt0.b.prtena = 0;
  81             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  82         }
  83         udelay(10);
  84         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  85         if(!hprt0.b.prtsusp)
  86         {
  87             //hprt0.d32 = 0;
  88             hprt0.b.prtsusp = 1;
  89             hprt0.b.prtena = 0;
  90             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  91         }
  92         mdelay(5);
  93         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  94         pcgcctl.b.pwrclmp = 1;//power clamp
  95         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  96         udelay(1);
  97         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
  98         pcgcctl.b.stoppclk = 1;//stop phy clk
  99         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 100     }
 101     else    //no device connect
 102     {
 103         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 104                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 0);
 105         }
 106     }
 107     udelay(3);
 108     clk_disable(core_if->otg_dev->phyclk);
 109     clk_disable(core_if->otg_dev->ahbclk);
 110     //power off
 111     return 0;
 112 }
 113
 114 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 115 {
 116     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 117     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 118     hprt0_data_t hprt0;
 119     pcgcctl_data_t pcgcctl;
 120     gintmsk_data_t gintmsk;
 121
 122     if(core_if->op_state == B_PERIPHERAL)
 123     {
 124         DWC_PRINT("%s, usb device mode\n", __func__);
 125         return 0;
 126     }
 127     clk_enable(core_if->otg_dev->phyclk);
 128     clk_enable(core_if->otg_dev->ahbclk);
 129
 130     //partial power-down
 131     //power on
 132     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 133     pcgcctl.b.stoppclk = 0;//stop phy clk
 134     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 135     udelay(1);
 136     pcgcctl.b.pwrclmp = 0;//power clamp
 137     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 138     udelay(2);
 139
 140     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 141     gintmsk.b.portintr = 0;
 142     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 143
 144     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 145     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 146     if(hprt0.b.prtconnsts)
 147     {
 148         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 149         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 150         hprt0.b.prtpwr = 1;
 151         hprt0.b.prtres = 1;
 152         hprt0.b.prtena = 0;
 153         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 154         mdelay(20);
 155         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 156         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 157         //hprt0.d32 = 0;
 158         hprt0.b.prtpwr = 1;
 159         hprt0.b.prtres = 0;
 160         hprt0.b.prtena = 0;
 161         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 162         hprt0.d32 = 0;
 163         hprt0.b.prtpwr = 1;
 164         hprt0.b.prtena = 0;
 165         hprt0.b.prtconndet = 1;
 166         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 167
 168         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 169         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 170
 171         mdelay(10);
 172     }
 173     else
 174     {
 175         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 176                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 1);
 177         }
 178     }
 179     gintmsk.b.portintr = 1;
 180     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 181
 182         return 0;
 183 }
 184
 185 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 186
 187 static const struct hc_driver dwc_otg_hc_driver = {
 188
 189         .description =          dwc_otg_hcd_name,
 190         .product_desc =         "DWC OTG Controller",
 191         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 192
 193         .irq =                  dwc_otg_hcd_irq,
 194
 195         .flags =                HCD_MEMORY | HCD_USB2,
 196
 197         //.reset =
 198         .start =                dwc_otg_hcd_start,
 199         //.suspend =
 200         //.resume =
 201
 202         /* yk@rk 20100625
 203          * core/hcd.c call hcd->driver->bus_suspend
 204          * otherwise system can not be suspended
 205          */
 206 #ifdef CONFIG_PM
 207         .bus_suspend =          dwc_otg_hcd_suspend,
 208         .bus_resume =           dwc_otg_hcd_resume,
 209 #endif
 210         .stop =                 dwc_otg_hcd_stop,
 211
 212         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 213         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 214         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 215
 216         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 217
 218         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 219         .hub_control =          dwc_otg_hcd_hub_control,
 220         //.hub_suspend =
 221         //.hub_resume =
 222 };
 223
 224 #ifdef CONFIG_USB11_HOST
 225 static const struct hc_driver host11_hc_driver = {
 226
 227         .description =          "host11_hcd",
 228         .product_desc =         "DWC OTG Controller",
 229         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 230
 231         .irq =                  dwc_otg_hcd_irq,
 232
 233         .flags =                HCD_MEMORY | HCD_USB2,
 234
 235         //.reset =
 236         .start =                dwc_otg_hcd_start,
 237         //.suspend =
 238         //.resume =
 239
 240         /* yk@rk 20100625
 241          * core/hcd.c call hcd->driver->bus_suspend
 242          * otherwise system can not be suspended
 243          */
 244 #ifdef CONFIG_PM
 245         .bus_suspend =          dwc_otg_hcd_suspend,
 246         .bus_resume =           dwc_otg_hcd_resume,
 247 #endif
 248         .stop =                 dwc_otg_hcd_stop,
 249
 250         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 251         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 252         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 253
 254         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 255
 256         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 257         .hub_control =          dwc_otg_hcd_hub_control,
 258         //.hub_suspend =
 259         //.hub_resume =
 260 };
 261 #endif
 262 #ifdef CONFIG_USB20_HOST
 263 static const struct hc_driver host20_hc_driver = {
 264
 265         .description =          "host20_hcd",
 266         .product_desc =         "DWC OTG Controller",
 267         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 268
 269         .irq =                  dwc_otg_hcd_irq,
 270
 271         .flags =                HCD_MEMORY | HCD_USB2,
 272
 273         //.reset =
 274         .start =                dwc_otg_hcd_start,
 275         //.suspend =
 276         //.resume =
 277
 278         /* yk@rk 20100625
 279          * core/hcd.c call hcd->driver->bus_suspend
 280          * otherwise system can not be suspended
 281          */
 282 #ifdef CONFIG_PM
 283         .bus_suspend =          dwc_otg_hcd_suspend,
 284         .bus_resume =           dwc_otg_hcd_resume,
 285 #endif
 286         .stop =                 dwc_otg_hcd_stop,
 287
 288         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 289         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 290         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 291
 292         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 293
 294         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 295         .hub_control =          dwc_otg_hcd_hub_control,
 296         //.hub_suspend =
 297         //.hub_resume =
 298 };
 299 #endif
 300
 301 /**
 302  * Work queue function for starting the HCD when A-Cable is connected.
 303  * The dwc_otg_hcd_start() must be called in a process context.
 304  */
 305 static void hcd_start_func(struct work_struct *work)
 306 {
 307     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 308     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 309
 310     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 311     if (hcd) {
 312             dwc_otg_hcd_start(hcd);
 313     }
 314 }
 315
 316 /**
 317  * HCD Callback function for starting the HCD when A-Cable is
 318  * connected.
 319  *
 320  * @param _p void pointer to the <code>struct usb_hcd</code>
 321  */
 322 static int32_t dwc_otg_hcd_start_cb(void *_p)
 323 {
 324         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 325         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 326         hprt0_data_t hprt0;
 327
 328         if (core_if->op_state == B_HOST) {
 329                 /*
 330                  * Reset the port.  During a HNP mode switch the reset
 331                  * needs to occur within 1ms and have a duration of at
 332                  * least 50ms.
 333                  */
 334                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 335                 hprt0.b.prtrst = 1;
 336                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 337                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 338         } else {
 339                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 340         }
 341
 342         /* Need to start the HCD in a non-interrupt context. */
 343 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 344         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 345         schedule_work(&dwc_otg_hcd->start_work);
 346
 347         return 1;
 348 }
 349
 350
 351 /**
 352  * HCD Callback function for stopping the HCD.
 353  *
 354  * @param _p void pointer to the <code>struct usb_hcd</code>
 355  */
 356 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 357 {
 358         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 359         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 360         dwc_otg_hcd_stop( usb_hcd );
 361         return 1;
 362 }
 363
 364 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 365 {
 366 #ifdef DEBUG
 367         int i;
 368         int num_channels = _hcd->core_if->core_params->host_channels;
 369         for (i = 0; i < num_channels; i++) {
 370                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 371         }
 372 #endif
 373 }
 374
 375 static void del_timers(dwc_otg_hcd_t *_hcd)
 376 {
 377         del_xfer_timers(_hcd);
 378         del_timer(&_hcd->conn_timer);
 379 }
 380
 381 /**
 382  * Processes all the URBs in a single list of QHs. Completes them with
 383  * -ETIMEDOUT and frees the QTD.
 384  */
 385 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 386 {
 387         struct list_head        *qh_item;
 388         dwc_otg_qh_t            *qh;
 389         struct list_head        *qtd_item;
 390         dwc_otg_qtd_t           *qtd;
 391
 392         list_for_each(qh_item, _qh_list) {
 393                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 394                 for (qtd_item = qh->qtd_list.next;
 395                      qtd_item != &qh->qtd_list;
 396                      qtd_item = qh->qtd_list.next) {
 397                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 398                         if (qtd->urb != NULL) {
 399                                 dwc_otg_hcd_complete_urb(_hcd, qtd->urb,
 400                                                          -ETIMEDOUT);
 401                         }
 402                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 403                 }
 404         }
 405 }
 406 #if 0
 407 /**
 408  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 409  * and periodic schedules. The QTD associated with each URB is removed from
 410  * the schedule and freed. This function may be called when a disconnect is
 411  * detected or when the HCD is being stopped.
 412  */
 413 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 414 {
 415         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 416         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 417         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 418         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 419         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 420         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 421 }
 422 #endif
 423 /**
 424  * HCD Callback function for disconnect of the HCD.
 425  *
 426  * @param _p void pointer to the <code>struct usb_hcd</code>
 427  */
 428 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 429 {
 430         gintsts_data_t  intr;
 431         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 432
 433         //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 434
 435         /*
 436          * Set status flags for the hub driver.
 437          */
 438 //     DWC_PRINT("dwc_otg_hcd_disconnect_cb");
 439         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 440         dwc_otg_hcd->flags.b.port_connect_status = 0;
 441
 442         /*
 443          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 444          * interrupt mask and status bits and disabling subsequent host
 445          * channel interrupts.
 446          */
 447         intr.d32 = 0;
 448         intr.b.nptxfempty = 1;
 449         intr.b.ptxfempty = 1;
 450         intr.b.hcintr = 1;
 451         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 452         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 453
 454         del_timers(dwc_otg_hcd);
 455
 456         /*
 457          * Turn off the vbus power only if the core has transitioned to device
 458          * mode. If still in host mode, need to keep power on to detect a
 459          * reconnection.
 460          */
 461         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 462                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 463                         hprt0_data_t hprt0 = { .d32=0 };
 464                         DWC_PRINT("Disconnect: PortPower off\n");
 465                         hprt0.b.prtpwr = 0;
 466                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 467                 }
 468
 469                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 470         }
 471
 472         /* Respond with an error status to all URBs in the schedule. */
 473         // yk@20101227 handle kernel panic bug when disconnect
 474         //kill_all_urbs(dwc_otg_hcd);
 475
 476         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 477                 /* Clean up any host channels that were in use. */
 478                 int                     num_channels;
 479                 int                     i;
 480                 dwc_hc_t                *channel;
 481                 dwc_otg_hc_regs_t       *hc_regs;
 482                 hcchar_data_t           hcchar;
 483
 484                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 485
 486                 if (!dwc_otg_hcd->core_if->dma_enable) {
 487                         /* Flush out any channel requests in slave mode. */
 488                         for (i = 0; i < num_channels; i++) {
 489                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 490                                 if (list_empty(&channel->hc_list_entry)) {
 491                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 492                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 493                                         if (hcchar.b.chen) {
 494                                                 hcchar.b.chen = 0;
 495                                                 hcchar.b.chdis = 1;
 496                                                 hcchar.b.epdir = 0;
 497                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 498                                         }
 499                                 }
 500                         }
 501                 }
 502
 503                 for (i = 0; i < num_channels; i++) {
 504                         channel = dwc_otg_hcd->hc_ptr_array[i];
 505                         if (list_empty(&channel->hc_list_entry)) {
 506                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 507                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 508                                 if (hcchar.b.chen) {
 509                                         /* Halt the channel. */
 510                                         hcchar.b.chdis = 1;
 511                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 512                                 }
 513
 514                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 515                                 list_add_tail(&channel->hc_list_entry,
 516                                               &dwc_otg_hcd->free_hc_list);
 517                         }
 518                 }
 519         }
 520
 521         /* A disconnect will end the session so the B-Device is no
 522          * longer a B-host. */
 523         ((struct usb_hcd *)_p)->self.is_b_host = 0;
 524         return 1;
 525 }
 526
 527 /**
 528  * Connection timeout function.  An OTG host is required to display a
 529  * message if the device does not connect within 10 seconds.
 530  */
 531 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 532 {
 533         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 534         DWC_PRINT( "Connect Timeout\n");
 535         DWC_ERROR( "Device Not Connected/Responding\n" );
 536 }
 537
 538 /**
 539  * Start the connection timer.  An OTG host is required to display a
 540  * message if the device does not connect within 10 seconds.  The
 541  * timer is deleted if a port connect interrupt occurs before the
 542  * timer expires.
 543  */
 544 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 545 {
 546         init_timer( &_hcd->conn_timer );
 547         _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 548         _hcd->conn_timer.data = (unsigned long)0;
 549         _hcd->conn_timer.expires = jiffies + (HZ*10);
 550         add_timer( &_hcd->conn_timer );
 551 }
 552
 553 /**
 554  * HCD Callback function for disconnect of the HCD.
 555  *
 556  * @param _p void pointer to the <code>struct usb_hcd</code>
 557  */
 558 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 559 {
 560         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 561         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 562         dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 563         return 1;
 564 }
 565
 566 /*
 567  * suspend: 0 usb phy enable
 568  *          1 usb phy suspend
 569  */
 570 static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
 571 {
 572     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 573
 574     if(suspend) {
 575         *otg_phy_con1 |= (0x01<<2);
 576         *otg_phy_con1 |= (0x01<<3);    // exit suspend.
 577         *otg_phy_con1 &= ~(0x01<<2);
 578
 579         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 580     }
 581     else
 582     {
 583         *otg_phy_con1 |= (0x01<<2);
 584         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
 585         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 586     }
 587
 588     return suspend;
 589 }
 590
 591 /**
 592  * HCD Callback structure for handling mode switching.
 593  */
 594 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 595         .start = dwc_otg_hcd_start_cb,
 596         .stop = dwc_otg_hcd_stop_cb,
 597         .disconnect = dwc_otg_hcd_disconnect_cb,
 598         .session_start = dwc_otg_hcd_session_start_cb,
 599         .suspend = dwc_otg_phy_suspend_cb,
 600         .p = 0,//hcd
 601 };
 602
 603 /**
 604  * Reset tasklet function
 605  */
 606 static void reset_tasklet_func (unsigned long data)
 607 {
 608         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 609         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 610         hprt0_data_t hprt0;
 611
 612         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 613
 614         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 615         hprt0.b.prtrst = 1;
 616         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 617         mdelay (60);
 618
 619         hprt0.b.prtrst = 0;
 620         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 621         dwc_otg_hcd->flags.b.port_reset_change = 1;
 622
 623         return;
 624 }
 625
 626 static struct tasklet_struct reset_tasklet = {
 627         .next = NULL,
 628         .state = 0,
 629         .count = ATOMIC_INIT(0),
 630         .func = reset_tasklet_func,
 631         .data = 0,
 632 };
 633
 634 /**
 635  * Initializes the HCD. This function allocates memory for and initializes the
 636  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 637  * USB bus with the core and calls the hc_driver->start() function. It returns
 638  * a negative error on failure.
 639  */
 640 extern uint32_t g_dbg_lvl;
 641 int __devinit dwc_otg_hcd_init(struct device *dev)
 642 {
 643         struct usb_hcd *hcd = NULL;
 644         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 645     dwc_otg_device_t *otg_dev = dev->platform_data;
 646
 647         int             num_channels;
 648         int             i;
 649         dwc_hc_t        *channel;
 650
 651         int retval = 0;
 652 #if 1  //kaiker .these code must execute before usb_create_hcd
 653         /* Set device flags indicating whether the HCD supports DMA. */
 654         static u64 usb_dmamask = 0xffffffffUL;
 655         if (otg_dev->core_if->dma_enable) {
 656                 dev->dma_mask = &usb_dmamask;
 657                 dev->coherent_dma_mask = ~0;
 658         } else {
 659                 dev->dma_mask = (void *)0;
 660                 dev->coherent_dma_mask = 0;
 661         }
 662 #endif
 663         DWC_PRINT("dwc_otg_hcd_init everest\n");
 664 //      g_dbg_lvl = 0xff;
 665
 666         /*
 667          * Allocate memory for the base HCD plus the DWC OTG HCD.
 668          * Initialize the base HCD.
 669          */
 670         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 671         if (hcd == NULL) {
 672                 retval = -ENOMEM;
 673                 goto error1;
 674         }
 675         hcd->regs = otg_dev->base;
 676         hcd->self.otg_port = 1;
 677
 678         /* Initialize the DWC OTG HCD. */
 679         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 680
 681         spin_lock_init(&dwc_otg_hcd->global_lock);
 682
 683         dwc_otg_hcd->core_if = otg_dev->core_if;
 684         otg_dev->hcd = dwc_otg_hcd;
 685
 686 #ifdef CONFIG_USB20_OTG_EN
 687     dwc_otg_hcd->host_enabled = 1;
 688 #else
 689     dwc_otg_hcd->host_enabled = 0;
 690 #endif
 691
 692         /* Register the HCD CIL Callbacks */
 693         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 694                                            &hcd_cil_callbacks, hcd);
 695
 696         /* Initialize the non-periodic schedule. */
 697         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 698         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 699
 700         /* Initialize the periodic schedule. */
 701         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 702         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 703         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 704         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 705
 706         /*
 707          * Create a host channel descriptor for each host channel implemented
 708          * in the controller. Initialize the channel descriptor array.
 709          */
 710         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 711         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 712         for (i = 0; i < num_channels; i++) {
 713                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 714                 if (channel == NULL) {
 715                         retval = -ENOMEM;
 716                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 717                         goto error2;
 718                 }
 719                 memset(channel, 0, sizeof(dwc_hc_t));
 720                 channel->hc_num = i;
 721                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 722 #ifdef DEBUG
 723                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 724 #endif
 725
 726                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 727         }
 728
 729         /* Initialize the Connection timeout timer. */
 730         init_timer( &dwc_otg_hcd->conn_timer );
 731
 732         /* Initialize reset tasklet. */
 733         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 734         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 735         /*
 736          * Finish generic HCD initialization and start the HCD. This function
 737          * allocates the DMA buffer pool, registers the USB bus, requests the
 738          * IRQ line, and calls dwc_otg_hcd_start method.
 739          */
 740         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 741                                         IRQF_SHARED);
 742         if (retval < 0) {
 743                 DWC_ERROR("usb_add_hcd fail,everest\n");
 744                 goto error2;
 745         }
 746         /*
 747          * Allocate space for storing data on status transactions. Normally no
 748          * data is sent, but this space acts as a bit bucket. This must be
 749          * done after usb_add_hcd since that function allocates the DMA buffer
 750          * pool.
 751          */
 752         if (otg_dev->core_if->dma_enable) {
 753                 dwc_otg_hcd->status_buf =
 754                         dma_alloc_coherent(dev,
 755                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 756                                            &dwc_otg_hcd->status_buf_dma,
 757                                            GFP_KERNEL | GFP_DMA);
 758         } else {
 759                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 760                                                   GFP_KERNEL);
 761         }
 762         if (dwc_otg_hcd->status_buf == NULL) {
 763                 retval = -ENOMEM;
 764                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 765                 goto error3;
 766         }
 767
 768         DWC_PRINT("%s end,everest\n",__func__);
 769 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 770 //                  dev->bus_id, hcd->self.busnum);
 771
 772         return 0;
 773
 774         /* Error conditions */
 775  error3:
 776         usb_remove_hcd(hcd);
 777  error2:
 778         dwc_otg_hcd_free(hcd);
 779         usb_put_hcd(hcd);
 780
 781  error1:
 782         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 783         return retval;
 784 }
 785
 786 #ifdef CONFIG_USB11_HOST
 787 /*
 788  * suspend: 0 usb phy enable
 789  *          1 usb phy suspend
 790  */
 791 static int32_t host11_phy_suspend_cb( void *_p, int suspend)
 792 {
 793     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 794
 795     if(suspend) {
 796         *otg_phy_con1 &= ~(0x01<<28);
 797         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 798     }
 799     else
 800     {
 801         *otg_phy_con1 |= (0x01<<28);
 802         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 803     }
 804
 805     return suspend;
 806 }
 807 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 808         .start = dwc_otg_hcd_start_cb,
 809         .stop = dwc_otg_hcd_stop_cb,
 810         .disconnect = dwc_otg_hcd_disconnect_cb,
 811         .session_start = dwc_otg_hcd_session_start_cb,
 812         .suspend = host11_phy_suspend_cb,
 813         .p = 0,//hcd
 814 };
 815
 816 static struct tasklet_struct host11_reset_tasklet = {
 817         .next = NULL,
 818         .state = 0,
 819         .count = ATOMIC_INIT(0),
 820         .func = reset_tasklet_func,
 821         .data = 0,
 822 };
 823
 824 int __devinit host11_hcd_init(struct device *dev)
 825 {
 826         struct usb_hcd *hcd = NULL;
 827         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 828     dwc_otg_device_t *otg_dev = dev->platform_data;
 829
 830         int             num_channels;
 831         int             i;
 832         dwc_hc_t        *channel;
 833
 834         int retval = 0;
 835 #if 1  //kaiker .these code must execute before usb_create_hcd
 836         /* Set device flags indicating whether the HCD supports DMA. */
 837         static u64 usb_dmamask = 0xffffffffUL;
 838         if (otg_dev->core_if->dma_enable) {
 839 //              DWC_PRINT("Using DMA mode\n");
 840                 dev->dma_mask = &usb_dmamask;
 841                 dev->coherent_dma_mask = ~0;
 842         } else {
 843 //              DWC_PRINT("Using Slave mode\n");
 844                 dev->dma_mask = (void *)0;
 845                 dev->coherent_dma_mask = 0;
 846         }
 847 #endif
 848         DWC_PRINT("%s everest\n",__func__);
 849 //      g_dbg_lvl = 0xff;
 850
 851         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 852
 853         /*
 854          * Allocate memory for the base HCD plus the DWC OTG HCD.
 855          * Initialize the base HCD.
 856          */
 857         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 858         if (hcd == NULL) {
 859                 retval = -ENOMEM;
 860                 goto error1;
 861         }
 862         hcd->regs = otg_dev->base;
 863         hcd->self.otg_port = 1;
 864
 865         /* Initialize the DWC OTG HCD. */
 866         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 867         dwc_otg_hcd->core_if = otg_dev->core_if;
 868         otg_dev->hcd = dwc_otg_hcd;
 869
 870 #ifdef CONFIG_USB11_HOST_EN
 871         dwc_otg_hcd->host_enabled = 1;
 872 #else
 873         dwc_otg_hcd->host_enabled = 0;
 874 #endif
 875
 876         spin_lock_init(&dwc_otg_hcd->global_lock);
 877
 878
 879         /* Register the HCD CIL Callbacks */
 880         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 881                                            &host11_cil_callbacks, hcd);
 882
 883         /* Initialize the non-periodic schedule. */
 884         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 885         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 886
 887         /* Initialize the periodic schedule. */
 888         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 889         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 890         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 891         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 892
 893         /*
 894          * Create a host channel descriptor for each host channel implemented
 895          * in the controller. Initialize the channel descriptor array.
 896          */
 897         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 898         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 899         for (i = 0; i < num_channels; i++) {
 900                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 901                 if (channel == NULL) {
 902                         retval = -ENOMEM;
 903                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 904                         goto error2;
 905                 }
 906                 memset(channel, 0, sizeof(dwc_hc_t));
 907                 channel->hc_num = i;
 908                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 909 #ifdef DEBUG
 910                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 911 #endif
 912
 913                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 914         }
 915
 916         /* Initialize the Connection timeout timer. */
 917         init_timer( &dwc_otg_hcd->conn_timer );
 918
 919         /* Initialize reset tasklet. */
 920         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 921         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 922         /*
 923          * Finish generic HCD initialization and start the HCD. This function
 924          * allocates the DMA buffer pool, registers the USB bus, requests the
 925          * IRQ line, and calls dwc_otg_hcd_start method.
 926          */
 927         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 928                                         IRQF_SHARED);
 929         if (retval < 0) {
 930                 DWC_ERROR("usb_add_hcd fail,everest\n");
 931                 goto error2;
 932         }
 933         /*
 934          * Allocate space for storing data on status transactions. Normally no
 935          * data is sent, but this space acts as a bit bucket. This must be
 936          * done after usb_add_hcd since that function allocates the DMA buffer
 937          * pool.
 938          */
 939         if (otg_dev->core_if->dma_enable) {
 940                 dwc_otg_hcd->status_buf =
 941                         dma_alloc_coherent(dev,
 942                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 943                                            &dwc_otg_hcd->status_buf_dma,
 944                                            GFP_KERNEL | GFP_DMA);
 945         } else {
 946                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 947                                                   GFP_KERNEL);
 948         }
 949         if (dwc_otg_hcd->status_buf == NULL) {
 950                 retval = -ENOMEM;
 951                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 952                 goto error3;
 953         }
 954
 955         DWC_PRINT("%s end,everest\n",__func__);
 956 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 957 //                  dev->bus_id, hcd->self.busnum);
 958
 959         return 0;
 960
 961         /* Error conditions */
 962  error3:
 963         usb_remove_hcd(hcd);
 964  error2:
 965         dwc_otg_hcd_free(hcd);
 966         usb_put_hcd(hcd);
 967
 968  error1:
 969         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 970         return retval;
 971 }
 972 #endif
 973 #ifdef CONFIG_USB20_HOST
 974
 975 /*
 976  * suspend: 0 usb phy enable
 977  *          1 usb phy suspend
 978  */
 979 static int32_t host20_phy_suspend_cb( void *_p, int suspend)
 980 {
 981     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 982     uint32_t regval;
 983
 984     regval = *otg_phy_con1;
 985
 986     if(suspend) {
 987         regval |= (0x01<<14);    // exit suspend.
 988         regval &= ~(0x01<<13);
 989
 990         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 991     }
 992     else
 993     {
 994         regval &= ~(0x01<<14);    // exit suspend.
 995         regval |= (0x01<<13);    // software control
 996         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 997     }
 998     *otg_phy_con1 = regval;
 999
1000     return suspend;
1001 }
1002
1003 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1004         .start = dwc_otg_hcd_start_cb,
1005         .stop = dwc_otg_hcd_stop_cb,
1006         .disconnect = dwc_otg_hcd_disconnect_cb,
1007         .session_start = dwc_otg_hcd_session_start_cb,
1008         .suspend = host20_phy_suspend_cb,
1009         .p = 0,//hcd
1010 };
1011
1012 static struct tasklet_struct host20_reset_tasklet = {
1013         .next = NULL,
1014         .state = 0,
1015         .count = ATOMIC_INIT(0),
1016         .func = reset_tasklet_func,
1017         .data = 0,
1018 };
1019
1020 int __devinit host20_hcd_init(struct device *dev)
1021 {
1022         struct usb_hcd *hcd = NULL;
1023         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1024     dwc_otg_device_t *otg_dev = dev->platform_data;
1025
1026         int             num_channels;
1027         int             i;
1028         dwc_hc_t        *channel;
1029
1030         int retval = 0;
1031 #if 1  //kaiker .these code must execute before usb_create_hcd
1032         /* Set device flags indicating whether the HCD supports DMA. */
1033         static u64 usb_dmamask = 0xffffffffUL;
1034         if (otg_dev->core_if->dma_enable) {
1035 //              DWC_PRINT("Using DMA mode\n");
1036                 dev->dma_mask = &usb_dmamask;
1037                 dev->coherent_dma_mask = ~0;
1038         } else {
1039 //              DWC_PRINT("Using Slave mode\n");
1040                 dev->dma_mask = (void *)0;
1041                 dev->coherent_dma_mask = 0;
1042         }
1043 #endif
1044         DWC_PRINT("%s everest\n",__func__);
1045 //      g_dbg_lvl = 0xff;
1046
1047         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1048
1049         /*
1050          * Allocate memory for the base HCD plus the DWC OTG HCD.
1051          * Initialize the base HCD.
1052          */
1053         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1054         if (hcd == NULL) {
1055                 retval = -ENOMEM;
1056                 goto error1;
1057         }
1058         hcd->regs = otg_dev->base;
1059         hcd->self.otg_port = 1;
1060
1061         /* Initialize the DWC OTG HCD. */
1062         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1063         dwc_otg_hcd->core_if = otg_dev->core_if;
1064         otg_dev->hcd = dwc_otg_hcd;
1065
1066 #ifdef CONFIG_USB20_HOST_EN
1067         dwc_otg_hcd->host_enabled = 1;
1068 #else
1069         dwc_otg_hcd->host_enabled = 0;
1070 #endif
1071
1072         spin_lock_init(&dwc_otg_hcd->global_lock);
1073
1074
1075         /* Register the HCD CIL Callbacks */
1076         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1077                                            &host20_cil_callbacks, hcd);
1078
1079         /* Initialize the non-periodic schedule. */
1080         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1081         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1082
1083         /* Initialize the periodic schedule. */
1084         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1085         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1086         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1087         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1088
1089         /*
1090          * Create a host channel descriptor for each host channel implemented
1091          * in the controller. Initialize the channel descriptor array.
1092          */
1093         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1094         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1095         for (i = 0; i < num_channels; i++) {
1096                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1097                 if (channel == NULL) {
1098                         retval = -ENOMEM;
1099                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1100                         goto error2;
1101                 }
1102                 memset(channel, 0, sizeof(dwc_hc_t));
1103                 channel->hc_num = i;
1104                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1105 #ifdef DEBUG
1106                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1107 #endif
1108
1109                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1110         }
1111
1112         /* Initialize the Connection timeout timer. */
1113         init_timer( &dwc_otg_hcd->conn_timer );
1114
1115         /* Initialize reset tasklet. */
1116         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1117         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1118         /*
1119          * Finish generic HCD initialization and start the HCD. This function
1120          * allocates the DMA buffer pool, registers the USB bus, requests the
1121          * IRQ line, and calls dwc_otg_hcd_start method.
1122          */
1123         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1124                                         IRQF_SHARED);
1125         if (retval < 0) {
1126                 DWC_ERROR("usb_add_hcd fail,everest\n");
1127                 goto error2;
1128         }
1129         /*
1130          * Allocate space for storing data on status transactions. Normally no
1131          * data is sent, but this space acts as a bit bucket. This must be
1132          * done after usb_add_hcd since that function allocates the DMA buffer
1133          * pool.
1134          */
1135         if (otg_dev->core_if->dma_enable) {
1136                 dwc_otg_hcd->status_buf =
1137                         dma_alloc_coherent(dev,
1138                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1139                                            &dwc_otg_hcd->status_buf_dma,
1140                                            GFP_KERNEL | GFP_DMA);
1141         } else {
1142                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1143                                                   GFP_KERNEL);
1144         }
1145         if (dwc_otg_hcd->status_buf == NULL) {
1146                 retval = -ENOMEM;
1147                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1148                 goto error3;
1149         }
1150
1151         DWC_PRINT("%s end,everest\n",__func__);
1152
1153         return 0;
1154
1155         /* Error conditions */
1156  error3:
1157         usb_remove_hcd(hcd);
1158  error2:
1159         dwc_otg_hcd_free(hcd);
1160         usb_put_hcd(hcd);
1161
1162  error1:
1163         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1164         return retval;
1165 }
1166 #endif
1167
1168 /**
1169  * Removes the HCD.
1170  * Frees memory and resources associated with the HCD and deregisters the bus.
1171  */
1172 void dwc_otg_hcd_remove(struct device *dev)
1173 {
1174         dwc_otg_device_t *otg_dev = dev->platform_data;
1175     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1176         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1177
1178         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1179
1180         /* Turn off all interrupts */
1181         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1182         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1183
1184         usb_remove_hcd(hcd);
1185         dwc_otg_hcd_free(hcd);
1186         usb_put_hcd(hcd);
1187
1188         return;
1189 }
1190
1191
1192 /* =========================================================================
1193  *  Linux HC Driver Functions
1194  * ========================================================================= */
1195
1196 /**
1197  * Initializes dynamic portions of the DWC_otg HCD state.
1198  */
1199 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1200 {
1201         struct list_head        *item;
1202         int                     num_channels;
1203         int                     i;
1204         dwc_hc_t                *channel;
1205         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1206
1207         _hcd->flags.d32 = 0;
1208
1209         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1210         _hcd->non_periodic_channels = 0;
1211         _hcd->periodic_channels = 0;
1212
1213         /*
1214          * Put all channels in the free channel list and clean up channel
1215          * states.
1216          */
1217         item = _hcd->free_hc_list.next;
1218         while (item != &_hcd->free_hc_list) {
1219                 list_del(item);
1220                 item = _hcd->free_hc_list.next;
1221         }
1222         num_channels = _hcd->core_if->core_params->host_channels;
1223         for (i = 0; i < num_channels; i++) {
1224                 channel = _hcd->hc_ptr_array[i];
1225                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1226                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1227         }
1228
1229         /* Initialize the DWC core for host mode operation. */
1230         dwc_otg_core_host_init(_hcd->core_if);
1231 }
1232
1233 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1234  * mode operation. Activates the root port. Returns 0 on success and a negative
1235  * error code on failure. */
1236 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1237 {
1238     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1239     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1240         unsigned long flags;
1241
1242         struct usb_bus *bus;
1243
1244         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1245         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1246
1247         DWC_PRINT("dwc_otg_hcd_start! everest\n");
1248         bus = hcd_to_bus(_hcd);
1249         _hcd->state = HC_STATE_RUNNING;
1250
1251         /* Initialize and connect root hub if one is not already attached */
1252         if (bus->root_hub) {
1253                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1254                 /* Inform the HUB driver to resume. */
1255                 usb_hcd_resume_root_hub(_hcd);
1256         }
1257         else {
1258             /*
1259              * no use
1260              * yk@rk 2010121
1261             struct usb_device *udev;6
1262                 udev = usb_alloc_dev(NULL, bus, 0);
1263                 udev->speed = USB_SPEED_HIGH;
1264                 if (!udev) {
1265                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1266                         return -ENODEV;
1267                 }
1268         */
1269             /* Not needed - VJ
1270                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1271                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1272                return -ENODEV;
1273                }
1274              */
1275         }
1276         /* Initialize the bus state.  If the core is in Device Mode
1277          * HALT the USB bus and return. */
1278         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1279                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1280                 //_hcd->state = HC_STATE_HALT;
1281                 goto out;
1282         }
1283         hcd_reinit(dwc_otg_hcd);
1284 out:
1285         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1286
1287         return 0;
1288 }
1289
1290 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1291 {
1292         struct list_head        *item;
1293         dwc_otg_qh_t            *qh;
1294
1295         if (_qh_list->next == NULL) {
1296                 /* The list hasn't been initialized yet. */
1297                 return;
1298         }
1299
1300         /* Ensure there are no QTDs or URBs left. */
1301         kill_urbs_in_qh_list(_hcd, _qh_list);
1302
1303         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1304                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1305                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1306         }
1307 }
1308
1309 /**
1310  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1311  * stopped.
1312  */
1313 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1314 {
1315         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1316         hprt0_data_t hprt0 = { .d32=0 };
1317
1318         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1319
1320         /* Turn off all host-specific interrupts. */
1321         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1322
1323         /*
1324          * The root hub should be disconnected before this function is called.
1325          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1326          * and the QH lists (via ..._hcd_endpoint_disable).
1327          */
1328
1329         /* Turn off the vbus power */
1330         DWC_PRINT("PortPower off\n");
1331         hprt0.b.prtpwr = 0;
1332         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1333
1334         return;
1335 }
1336
1337
1338 /** Returns the current frame number. */
1339 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1340 {
1341         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1342         hfnum_data_t hfnum;
1343
1344         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1345                                    host_if->host_global_regs->hfnum);
1346
1347 #ifdef DEBUG_SOF
1348         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1349 #endif
1350         return hfnum.b.frnum;
1351 }
1352
1353 /**
1354  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1355  * in the struct usb_hcd field.
1356  */
1357 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1358 {
1359         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1360         int             i;
1361
1362         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1363
1364         del_timers(dwc_otg_hcd);
1365
1366         /* Free memory for QH/QTD lists */
1367         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1368         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1369         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1370         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1371         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1372         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1373
1374         /* Free memory for the host channels. */
1375         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1376                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1377                 if (hc != NULL) {
1378                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1379                         kfree(hc);
1380                 }
1381         }
1382
1383         if (dwc_otg_hcd->core_if->dma_enable) {
1384                 if (dwc_otg_hcd->status_buf_dma) {
1385                         dma_free_coherent(_hcd->self.controller,
1386                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1387                                           dwc_otg_hcd->status_buf,
1388                                           dwc_otg_hcd->status_buf_dma);
1389                 }
1390         } else if (dwc_otg_hcd->status_buf != NULL) {
1391                 kfree(dwc_otg_hcd->status_buf);
1392         }
1393
1394         return;
1395 }
1396
1397
1398 #ifdef DEBUG
1399 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1400 {
1401         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1402         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1403                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1404         DWC_PRINT("  Endpoint type: %s\n",
1405                   ({char *pipetype;
1406                   switch (usb_pipetype(_urb->pipe)) {
1407                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1408                   case PIPE_BULK: pipetype = "BULK"; break;
1409                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1410                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1411                   default: pipetype = "UNKNOWN"; break;
1412                   }; pipetype;}));
1413         DWC_PRINT("  Speed: %s\n",
1414                   ({char *speed;
1415                   switch (_urb->dev->speed) {
1416                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1417                   case USB_SPEED_FULL: speed = "FULL"; break;
1418                   case USB_SPEED_LOW: speed = "LOW"; break;
1419                   default: speed = "UNKNOWN"; break;
1420                   }; speed;}));
1421         DWC_PRINT("  Max packet size: %d\n",
1422                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1423         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1424         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1425                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1426         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1427                   _urb->setup_packet, (void *)_urb->setup_dma);
1428         DWC_PRINT("  Interval: %d\n", _urb->interval);
1429         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1430                 int i;
1431                 for (i = 0; i < _urb->number_of_packets;  i++) {
1432                         DWC_PRINT("  ISO Desc %d:\n", i);
1433                         DWC_PRINT("    offset: %d, length %d\n",
1434                                   _urb->iso_frame_desc[i].offset,
1435                                   _urb->iso_frame_desc[i].length);
1436                 }
1437         }
1438 }
1439
1440 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1441                               dwc_otg_qh_t *qh)
1442 {
1443         if (qh->channel != NULL) {
1444                 dwc_hc_t *hc = qh->channel;
1445                 struct list_head *item;
1446                 dwc_otg_qh_t *qh_item;
1447                 int num_channels = _hcd->core_if->core_params->host_channels;
1448                 int i;
1449
1450                 dwc_otg_hc_regs_t *hc_regs;
1451                 hcchar_data_t   hcchar;
1452                 hcsplt_data_t   hcsplt;
1453                 hctsiz_data_t   hctsiz;
1454                 uint32_t        hcdma;
1455
1456                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1457                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1458                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1459                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1460                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1461
1462                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1463                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1464                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1465                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1466                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1467                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1468                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1469                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1470                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1471                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1472                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1473                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1474                 DWC_PRINT("    qh: %p\n", hc->qh);
1475                 DWC_PRINT("  NP inactive sched:\n");
1476                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1477                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1478                         DWC_PRINT("    %p\n", qh_item);
1479                 }
1480                 DWC_PRINT("  NP active sched:\n");
1481                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1482                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1483                         DWC_PRINT("    %p\n", qh_item);
1484                 }
1485                 DWC_PRINT("  Channels: \n");
1486                 for (i = 0; i < num_channels; i++) {
1487                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1488                         DWC_PRINT("    %2d: %p\n", i, hc);
1489                 }
1490         }
1491 }
1492 #endif
1493
1494 /** Starts processing a USB transfer request specified by a USB Request Block
1495  * (URB). mem_flags indicates the type of memory allocation to use while
1496  * processing this URB. */
1497 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1498                             struct urb *_urb,
1499                             gfp_t _mem_flags)
1500 {
1501         int retval;
1502         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1503         dwc_otg_qtd_t * qtd;
1504         unsigned long flags;
1505
1506         retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
1507         if (retval)
1508         {
1509                 DWC_PRINT("%s, usb_hcd_link_urb_to_ep error\n", __func__);
1510                 return retval;
1511         }
1512         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1513 #if 1
1514         /*
1515          * Make sure the start of frame interrupt is enabled now that
1516          * we know we should have queued data. The SOF interrupt
1517          * handler automatically disables itself when idle to reduce
1518          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1519          * for the disable
1520          */
1521         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1522                          DWC_SOF_INTR_MASK);
1523 #endif
1524 #ifdef DEBUG
1525             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1526                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1527         }
1528 #endif  /*  */
1529     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1530             /* No longer connected. */
1531                 retval =  -ENODEV;
1532                 goto out;
1533         }
1534         qtd = dwc_otg_hcd_qtd_create(_urb);
1535         if (qtd == NULL) {
1536                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1537                 retval = -ENOMEM;
1538                 goto out;
1539         }
1540         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1541         if (retval < 0) {
1542                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1543                            "Error status %d\n", retval);
1544                 dwc_otg_hcd_qtd_free(qtd);
1545         }
1546 out:
1547         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1548
1549         return retval;
1550 }
1551
1552 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1553  * success.  */
1554 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1555 {
1556         unsigned long flags;
1557         dwc_otg_hcd_t * dwc_otg_hcd;
1558         dwc_otg_qtd_t * urb_qtd;
1559         dwc_otg_qh_t * qh;
1560         struct usb_host_endpoint *_ep = _urb->ep;//dwc_urb_to_endpoint(_urb);
1561         int retval;
1562
1563         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1564         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1565         if(_ep==NULL)
1566         {
1567                 DWC_PRINT("%s=====================================================\n",__func__);
1568                 DWC_PRINT("urb->ep is null\n");
1569                 return -1;
1570         }
1571         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1572         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1573         retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
1574         if (retval) {
1575                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1576                 return retval;
1577         }
1578         if(urb_qtd == NULL)
1579         {
1580                 DWC_PRINT("%s,urb_qtd is null\n",__func__);
1581                 goto urb_qtd_null;
1582                 //return -1;
1583         }
1584         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1585
1586 #ifdef DEBUG
1587     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1588                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1589                 if (urb_qtd == qh->qtd_in_process) {
1590                         dump_channel_info(dwc_otg_hcd, qh);
1591                 }
1592         }
1593
1594 #endif  /*  */
1595 #if 1
1596     if (urb_qtd == qh->qtd_in_process) {
1597             /* The QTD is in process (it has been assigned to a channel). */
1598             if (dwc_otg_hcd->flags.b.port_connect_status) {
1599
1600                     /*
1601                      * If still connected (i.e. in host mode), halt the
1602                      * channel so it can be used for other transfers. If
1603                      * no longer connected, the host registers can't be
1604                      * written to halt the channel since the core is in
1605                      * device mode.
1606                      */
1607                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1608                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1609                 }
1610         }
1611
1612     /*
1613      * Free the QTD and clean up the associated QH. Leave the QH in the
1614      * schedule if it has any remaining QTDs.
1615      */
1616     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1617         if (urb_qtd == qh->qtd_in_process) {
1618                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1619                 qh->channel = NULL;
1620                 qh->qtd_in_process = NULL;
1621         } else if (list_empty(&qh->qtd_list)) {
1622                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1623         }
1624 #endif
1625
1626 urb_qtd_null:
1627         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1628         _urb->hcpriv = NULL;
1629         usb_hcd_unlink_urb_from_ep(_hcd, _urb);
1630     /* Higher layer software sets URB status. */
1631         usb_hcd_giveback_urb(_hcd, _urb, _status);
1632         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1633                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1634                 DWC_PRINT("  urb->status = %d\n", _status);
1635         }
1636         return 0;
1637 }
1638
1639
1640 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1641  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1642  * must already be dequeued. */
1643 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1644                                   struct usb_host_endpoint *_ep)
1645
1646 {
1647         unsigned long flags;
1648         dwc_otg_qh_t *qh;
1649         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1650
1651         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1652
1653         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1654                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1655                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1656
1657         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1658         if (qh != NULL) {
1659 #ifdef DEBUG
1660                 /** Check that the QTD list is really empty */
1661                 if (!list_empty(&qh->qtd_list)) {
1662                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1663                                  " QTD List for this endpoint is not empty\n");
1664                 }
1665 #endif
1666
1667                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1668                 _ep->hcpriv = NULL;
1669         }
1670
1671         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1672
1673         return;
1674 }
1675
1676 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1677  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1678  * interrupt.
1679  *
1680  * This function is called by the USB core when an interrupt occurs */
1681 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1682 {
1683         irqreturn_t result;
1684         unsigned long flags;
1685         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1686
1687         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1688
1689         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1690
1691         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1692
1693         return result;
1694 }
1695
1696 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1697  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1698  * is the status change indicator for the single root port. Returns 1 if either
1699  * change indicator is 1, otherwise returns 0. */
1700 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1701                                 char *_buf)
1702 {
1703         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1704
1705         _buf[0] = 0;
1706         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1707                     dwc_otg_hcd->flags.b.port_reset_change ||
1708                     dwc_otg_hcd->flags.b.port_enable_change ||
1709                     dwc_otg_hcd->flags.b.port_suspend_change ||
1710                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1711
1712 #ifdef DEBUG
1713         if (_buf[0]) {
1714                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1715                             " Root port status changed\n");
1716                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1717                             dwc_otg_hcd->flags.b.port_connect_status_change);
1718                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1719                             dwc_otg_hcd->flags.b.port_reset_change);
1720                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1721                             dwc_otg_hcd->flags.b.port_enable_change);
1722                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1723                             dwc_otg_hcd->flags.b.port_suspend_change);
1724                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1725                             dwc_otg_hcd->flags.b.port_over_current_change);
1726         }
1727 #endif
1728         return (_buf[0] != 0);
1729 }
1730
1731 #ifdef DWC_HS_ELECT_TST
1732 /*
1733  * Quick and dirty hack to implement the HS Electrical Test
1734  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1735  *
1736  * This code was copied from our userspace app "hset". It sends a
1737  * Get Device Descriptor control sequence in two parts, first the
1738  * Setup packet by itself, followed some time later by the In and
1739  * Ack packets. Rather than trying to figure out how to add this
1740  * functionality to the normal driver code, we just hijack the
1741  * hardware, using these two function to drive the hardware
1742  * directly.
1743  */
1744
1745 dwc_otg_core_global_regs_t *global_regs;
1746 dwc_otg_host_global_regs_t *hc_global_regs;
1747 dwc_otg_hc_regs_t *hc_regs;
1748 uint32_t *data_fifo;
1749
1750 static void do_setup(void)
1751 {
1752         gintsts_data_t gintsts;
1753         hctsiz_data_t hctsiz;
1754         hcchar_data_t hcchar;
1755         haint_data_t haint;
1756         hcint_data_t hcint;
1757
1758         /* Enable HAINTs */
1759         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1760
1761         /* Enable HCINTs */
1762         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1763
1764         /* Read GINTSTS */
1765         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1766         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1767
1768         /* Read HAINT */
1769         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1770         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1771
1772         /* Read HCINT */
1773         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1774         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1775
1776         /* Read HCCHAR */
1777         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1778         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1779
1780         /* Clear HCINT */
1781         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1782
1783         /* Clear HAINT */
1784         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1785
1786         /* Clear GINTSTS */
1787         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1788
1789         /* Read GINTSTS */
1790         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1791         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1792
1793         /*
1794          * Send Setup packet (Get Device Descriptor)
1795          */
1796
1797         /* Make sure channel is disabled */
1798         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1799         if (hcchar.b.chen) {
1800                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1801                 hcchar.b.chdis = 1;
1802 //              hcchar.b.chen = 1;
1803                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1804                 //sleep(1);
1805                 mdelay(1000);
1806
1807                 /* Read GINTSTS */
1808                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1809                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1810
1811                 /* Read HAINT */
1812                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1813                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1814
1815                 /* Read HCINT */
1816                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1817                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1818
1819                 /* Read HCCHAR */
1820                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1821                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1822
1823                 /* Clear HCINT */
1824                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1825
1826                 /* Clear HAINT */
1827                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1828
1829                 /* Clear GINTSTS */
1830                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1831
1832                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1833                 //if (hcchar.b.chen) {
1834                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1835                 //}
1836         }
1837
1838         /* Set HCTSIZ */
1839         hctsiz.d32 = 0;
1840         hctsiz.b.xfersize = 8;
1841         hctsiz.b.pktcnt = 1;
1842         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1843         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1844
1845         /* Set HCCHAR */
1846         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1847         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1848         hcchar.b.epdir = 0;
1849         hcchar.b.epnum = 0;
1850         hcchar.b.mps = 8;
1851         hcchar.b.chen = 1;
1852         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1853
1854         /* Fill FIFO with Setup data for Get Device Descriptor */
1855         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1856         dwc_write_reg32(data_fifo++, 0x01000680);
1857         dwc_write_reg32(data_fifo++, 0x00080000);
1858
1859         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1860         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1861
1862         /* Wait for host channel interrupt */
1863         do {
1864                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1865         } while (gintsts.b.hcintr == 0);
1866
1867         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1868
1869         /* Disable HCINTs */
1870         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1871
1872         /* Disable HAINTs */
1873         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1874
1875         /* Read HAINT */
1876         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1877         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1878
1879         /* Read HCINT */
1880         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1881         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1882
1883         /* Read HCCHAR */
1884         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1885         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1886
1887         /* Clear HCINT */
1888         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1889
1890         /* Clear HAINT */
1891         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1892
1893         /* Clear GINTSTS */
1894         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1895
1896         /* Read GINTSTS */
1897         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1898         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1899 }
1900
1901 static void do_in_ack(void)
1902 {
1903         gintsts_data_t gintsts;
1904         hctsiz_data_t hctsiz;
1905         hcchar_data_t hcchar;
1906         haint_data_t haint;
1907         hcint_data_t hcint;
1908         host_grxsts_data_t grxsts;
1909
1910         /* Enable HAINTs */
1911         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1912
1913         /* Enable HCINTs */
1914         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1915
1916         /* Read GINTSTS */
1917         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1918         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1919
1920         /* Read HAINT */
1921         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1922         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1923
1924         /* Read HCINT */
1925         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1926         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1927
1928         /* Read HCCHAR */
1929         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1930         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1931
1932         /* Clear HCINT */
1933         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1934
1935         /* Clear HAINT */
1936         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1937
1938         /* Clear GINTSTS */
1939         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1940
1941         /* Read GINTSTS */
1942         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1943         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1944
1945         /*
1946          * Receive Control In packet
1947          */
1948
1949         /* Make sure channel is disabled */
1950         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1951         if (hcchar.b.chen) {
1952                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1953                 hcchar.b.chdis = 1;
1954                 hcchar.b.chen = 1;
1955                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1956                 //sleep(1);
1957                 mdelay(1000);
1958
1959                 /* Read GINTSTS */
1960                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1961                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1962
1963                 /* Read HAINT */
1964                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1965                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1966
1967                 /* Read HCINT */
1968                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1969                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1970
1971                 /* Read HCCHAR */
1972                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1973                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1974
1975                 /* Clear HCINT */
1976                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1977
1978                 /* Clear HAINT */
1979                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1980
1981                 /* Clear GINTSTS */
1982                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1983
1984                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1985                 //if (hcchar.b.chen) {
1986                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
1987                 //}
1988         }
1989
1990         /* Set HCTSIZ */
1991         hctsiz.d32 = 0;
1992         hctsiz.b.xfersize = 8;
1993         hctsiz.b.pktcnt = 1;
1994         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1995         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1996
1997         /* Set HCCHAR */
1998         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1999         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2000         hcchar.b.epdir = 1;
2001         hcchar.b.epnum = 0;
2002         hcchar.b.mps = 8;
2003         hcchar.b.chen = 1;
2004         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2005
2006         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2007         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2008
2009         /* Wait for receive status queue interrupt */
2010         do {
2011                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2012         } while (gintsts.b.rxstsqlvl == 0);
2013
2014         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2015
2016         /* Read RXSTS */
2017         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2018         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2019
2020         /* Clear RXSTSQLVL in GINTSTS */
2021         gintsts.d32 = 0;
2022         gintsts.b.rxstsqlvl = 1;
2023         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2024
2025         switch (grxsts.b.pktsts) {
2026         case DWC_GRXSTS_PKTSTS_IN:
2027                 /* Read the data into the host buffer */
2028                 if (grxsts.b.bcnt > 0) {
2029                         int i;
2030                         int word_count = (grxsts.b.bcnt + 3) / 4;
2031
2032                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2033
2034                         for (i = 0; i < word_count; i++) {
2035                                 (void)dwc_read_reg32(data_fifo++);
2036                         }
2037                 }
2038
2039                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2040         break;
2041
2042         default:
2043                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2044         break;
2045         }
2046
2047         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2048         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2049
2050         /* Wait for receive status queue interrupt */
2051         do {
2052                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2053         } while (gintsts.b.rxstsqlvl == 0);
2054
2055         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2056
2057         /* Read RXSTS */
2058         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2059         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2060
2061         /* Clear RXSTSQLVL in GINTSTS */
2062         gintsts.d32 = 0;
2063         gintsts.b.rxstsqlvl = 1;
2064         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2065
2066         switch (grxsts.b.pktsts) {
2067         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2068         break;
2069
2070         default:
2071                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2072         break;
2073         }
2074
2075         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2076         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2077
2078         /* Wait for host channel interrupt */
2079         do {
2080                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2081         } while (gintsts.b.hcintr == 0);
2082
2083         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2084
2085         /* Read HAINT */
2086         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2087         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2088
2089         /* Read HCINT */
2090         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2091         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2092
2093         /* Read HCCHAR */
2094         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2095         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2096
2097         /* Clear HCINT */
2098         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2099
2100         /* Clear HAINT */
2101         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2102
2103         /* Clear GINTSTS */
2104         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2105
2106         /* Read GINTSTS */
2107         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2108         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2109
2110 //      usleep(100000);
2111 //      mdelay(100);
2112         mdelay(1);
2113
2114         /*
2115          * Send handshake packet
2116          */
2117
2118         /* Read HAINT */
2119         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2120         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2121
2122         /* Read HCINT */
2123         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2124         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2125
2126         /* Read HCCHAR */
2127         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2128         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2129
2130         /* Clear HCINT */
2131         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2132
2133         /* Clear HAINT */
2134         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2135
2136         /* Clear GINTSTS */
2137         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2138
2139         /* Read GINTSTS */
2140         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2141         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2142
2143         /* Make sure channel is disabled */
2144         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2145         if (hcchar.b.chen) {
2146                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2147                 hcchar.b.chdis = 1;
2148                 hcchar.b.chen = 1;
2149                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2150                 //sleep(1);
2151                 mdelay(1000);
2152
2153                 /* Read GINTSTS */
2154                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2155                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2156
2157                 /* Read HAINT */
2158                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2159                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2160
2161                 /* Read HCINT */
2162                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2163                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2164
2165                 /* Read HCCHAR */
2166                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2167                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2168
2169                 /* Clear HCINT */
2170                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2171
2172                 /* Clear HAINT */
2173                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2174
2175                 /* Clear GINTSTS */
2176                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2177
2178                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2179                 //if (hcchar.b.chen) {
2180                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2181                 //}
2182         }
2183
2184         /* Set HCTSIZ */
2185         hctsiz.d32 = 0;
2186         hctsiz.b.xfersize = 0;
2187         hctsiz.b.pktcnt = 1;
2188         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2189         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2190
2191         /* Set HCCHAR */
2192         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2193         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2194         hcchar.b.epdir = 0;
2195         hcchar.b.epnum = 0;
2196         hcchar.b.mps = 8;
2197         hcchar.b.chen = 1;
2198         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2199
2200         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2201         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2202
2203         /* Wait for host channel interrupt */
2204         do {
2205                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2206         } while (gintsts.b.hcintr == 0);
2207
2208         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2209
2210         /* Disable HCINTs */
2211         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2212
2213         /* Disable HAINTs */
2214         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2215
2216         /* Read HAINT */
2217         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2218         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2219
2220         /* Read HCINT */
2221         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2222         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2223
2224         /* Read HCCHAR */
2225         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2226         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2227
2228         /* Clear HCINT */
2229         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2230
2231         /* Clear HAINT */
2232         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2233
2234         /* Clear GINTSTS */
2235         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2236
2237         /* Read GINTSTS */
2238         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2239         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2240 }
2241 #endif /* DWC_HS_ELECT_TST */
2242
2243 /** Handles hub class-specific requests.*/
2244 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2245                             u16 _typeReq,
2246                             u16 _wValue,
2247                             u16 _wIndex,
2248                             char *_buf,
2249                             u16 _wLength)
2250 {
2251         int retval = 0;
2252         unsigned long flags;
2253
2254         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2255         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2256         struct usb_hub_descriptor *desc;
2257         hprt0_data_t hprt0 = {.d32 = 0};
2258
2259         uint32_t port_status;
2260         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2261
2262         switch (_typeReq) {
2263         case ClearHubFeature:
2264                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2265                             "ClearHubFeature 0x%x\n", _wValue);
2266                 switch (_wValue) {
2267                 case C_HUB_LOCAL_POWER:
2268                 case C_HUB_OVER_CURRENT:
2269                         /* Nothing required here */
2270                         break;
2271                 default:
2272                         retval = -EINVAL;
2273                         DWC_ERROR ("DWC OTG HCD - "
2274                                    "ClearHubFeature request %xh unknown\n", _wValue);
2275                 }
2276                 break;
2277         case ClearPortFeature:
2278                 if (!_wIndex || _wIndex > 1)
2279                         goto error;
2280
2281                 switch (_wValue) {
2282                 case USB_PORT_FEAT_ENABLE:
2283                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2284                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2285                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2286                         hprt0.b.prtena = 1;
2287                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2288                         break;
2289                 case USB_PORT_FEAT_SUSPEND:
2290                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2291                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2292                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2293                         hprt0.b.prtres = 1;
2294                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2295                         /* Clear Resume bit */
2296                         mdelay (100);
2297                         hprt0.b.prtres = 0;
2298                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2299                         break;
2300                 case USB_PORT_FEAT_POWER:
2301                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2302                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2303                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2304                         hprt0.b.prtpwr = 0;
2305                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2306                         break;
2307                 case USB_PORT_FEAT_INDICATOR:
2308                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2309                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2310                         /* Port inidicator not supported */
2311                         break;
2312                 case USB_PORT_FEAT_C_CONNECTION:
2313                         /* Clears drivers internal connect status change
2314                          * flag */
2315                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2316                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2317                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2318                         break;
2319                 case USB_PORT_FEAT_C_RESET:
2320                         /* Clears the driver's internal Port Reset Change
2321                          * flag */
2322                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2323                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2324                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2325                         break;
2326                 case USB_PORT_FEAT_C_ENABLE:
2327                         /* Clears the driver's internal Port
2328                          * Enable/Disable Change flag */
2329                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2330                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2331                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2332                         break;
2333                 case USB_PORT_FEAT_C_SUSPEND:
2334                         /* Clears the driver's internal Port Suspend
2335                          * Change flag, which is set when resume signaling on
2336                          * the host port is complete */
2337                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2338                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2339                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2340                         break;
2341                 case USB_PORT_FEAT_C_OVER_CURRENT:
2342                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2343                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2344                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2345                         break;
2346                 default:
2347                         retval = -EINVAL;
2348                         DWC_ERROR ("DWC OTG HCD - "
2349                                    "ClearPortFeature request %xh "
2350                                    "unknown or unsupported\n", _wValue);
2351                 }
2352                 break;
2353         case GetHubDescriptor:
2354                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2355                              "GetHubDescriptor\n");
2356                 desc = (struct usb_hub_descriptor *)_buf;
2357                 desc->bDescLength = 9;
2358                 desc->bDescriptorType = 0x29;
2359                 desc->bNbrPorts = 1;
2360                 desc->wHubCharacteristics = 0x08;
2361                 desc->bPwrOn2PwrGood = 1;
2362                 desc->bHubContrCurrent = 0;
2363                 desc->bitmap[0] = 0;
2364                 desc->bitmap[1] = 0xff;
2365                 break;
2366         case GetHubStatus:
2367                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2368                              "GetHubStatus\n");
2369                 memset (_buf, 0, 4);
2370                 break;
2371         case GetPortStatus:
2372                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2373                              "GetPortStatus\n");
2374
2375                 if (!_wIndex || _wIndex > 1)
2376                         goto error;
2377
2378                 port_status = 0;
2379
2380                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2381                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2382
2383                 if (dwc_otg_hcd->flags.b.port_enable_change)
2384                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2385
2386                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2387                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2388
2389                 if (dwc_otg_hcd->flags.b.port_reset_change)
2390                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2391
2392                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2393                         DWC_ERROR("Device Not Supported\n");
2394                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2395                 }
2396
2397                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2398                         /*
2399                          * The port is disconnected, which means the core is
2400                          * either in device mode or it soon will be. Just
2401                          * return 0's for the remainder of the port status
2402                          * since the port register can't be read if the core
2403                          * is in device mode.
2404                          */
2405                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2406                         break;
2407                 }
2408
2409                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2410                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2411
2412                 if (hprt0.b.prtconnsts)
2413                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2414
2415                 if (hprt0.b.prtena)
2416                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2417
2418                 if (hprt0.b.prtsusp)
2419                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2420
2421                 if (hprt0.b.prtovrcurract)
2422                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2423
2424                 if (hprt0.b.prtrst)
2425                         port_status |= (1 << USB_PORT_FEAT_RESET);
2426
2427                 if (hprt0.b.prtpwr)
2428                         port_status |= (1 << USB_PORT_FEAT_POWER);
2429
2430                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2431                         port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
2432
2433                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2434                         port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
2435
2436                 if (hprt0.b.prttstctl)
2437                         port_status |= (1 << USB_PORT_FEAT_TEST);
2438
2439                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2440
2441                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2442
2443                 break;
2444         case SetHubFeature:
2445                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2446                              "SetHubFeature\n");
2447                 /* No HUB features supported */
2448                 break;
2449         case SetPortFeature:
2450                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2451                         goto error;
2452
2453                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2454                         /*
2455                          * The port is disconnected, which means the core is
2456                          * either in device mode or it soon will be. Just
2457                          * return without doing anything since the port
2458                          * register can't be written if the core is in device
2459                          * mode.
2460                          */
2461                         break;
2462                 }
2463
2464                 switch (_wValue) {
2465                 case USB_PORT_FEAT_SUSPEND:
2466                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2467                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2468                         if (_hcd->self.otg_port == _wIndex &&
2469                             _hcd->self.b_hnp_enable) {
2470                                 gotgctl_data_t  gotgctl = {.d32=0};
2471                                 gotgctl.b.hstsethnpen = 1;
2472                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2473                                                   0, gotgctl.d32);
2474                                 core_if->op_state = A_SUSPEND;
2475                         }
2476                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2477                         hprt0.b.prtsusp = 1;
2478                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2479                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2480                         /* Suspend the Phy Clock */
2481                         {
2482                                 pcgcctl_data_t pcgcctl = {.d32=0};
2483                                 pcgcctl.b.stoppclk = 1;
2484                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2485                         }
2486
2487                         /* For HNP the bus must be suspended for at least 200ms.*/
2488                         if (_hcd->self.b_hnp_enable) {
2489                                 mdelay(200);
2490                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2491                         }
2492                         break;
2493                 case USB_PORT_FEAT_POWER:
2494                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2495                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2496                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2497                         hprt0.b.prtpwr = 1;
2498                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2499                         break;
2500                 case USB_PORT_FEAT_RESET:
2501                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2502                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2503                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2504                         /* When B-Host the Port reset bit is set in
2505                          * the Start HCD Callback function, so that
2506                          * the reset is started within 1ms of the HNP
2507                          * success interrupt. */
2508                         if (!_hcd->self.is_b_host) {
2509                                 hprt0.b.prtrst = 1;
2510                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2511                         }
2512                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2513                         MDELAY (60);
2514                         hprt0.b.prtrst = 0;
2515                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2516                         break;
2517
2518 #ifdef DWC_HS_ELECT_TST
2519                 case USB_PORT_FEAT_TEST:
2520                 {
2521                         uint32_t t;
2522                         gintmsk_data_t gintmsk;
2523
2524                         t = (_wIndex >> 8); /* MSB wIndex USB */
2525                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2526                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2527                         warn("USB_PORT_FEAT_TEST %d\n", t);
2528                         if (t < 6) {
2529                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2530                                 hprt0.b.prttstctl = t;
2531                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2532                         } else {
2533                                 /* Setup global vars with reg addresses (quick and
2534                                  * dirty hack, should be cleaned up)
2535                                  */
2536                                 global_regs = core_if->core_global_regs;
2537                                 hc_global_regs = core_if->host_if->host_global_regs;
2538                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2539                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2540
2541                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2542                                         /* Save current interrupt mask */
2543                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2544
2545                                         /* Disable all interrupts while we muck with
2546                                          * the hardware directly
2547                                          */
2548                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2549
2550                                         /* 15 second delay per the test spec */
2551                                         mdelay(15000);
2552
2553                                         /* Drive suspend on the root port */
2554                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2555                                         hprt0.b.prtsusp = 1;
2556                                         hprt0.b.prtres = 0;
2557                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2558
2559                                         /* 15 second delay per the test spec */
2560                                         mdelay(15000);
2561
2562                                         /* Drive resume on the root port */
2563                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2564                                         hprt0.b.prtsusp = 0;
2565                                         hprt0.b.prtres = 1;
2566                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2567                                         mdelay(100);
2568
2569                                         /* Clear the resume bit */
2570                                         hprt0.b.prtres = 0;
2571                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2572
2573                                         /* Restore interrupts */
2574                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2575                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2576                                         /* Save current interrupt mask */
2577                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2578
2579                                         /* Disable all interrupts while we muck with
2580                                          * the hardware directly
2581                                          */
2582                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2583
2584                                         /* 15 second delay per the test spec */
2585                                         mdelay(15000);
2586
2587                                         /* Send the Setup packet */
2588                                         do_setup();
2589
2590                                         /* 15 second delay so nothing else happens for awhile */
2591                                         mdelay(15000);
2592
2593                                         /* Restore interrupts */
2594                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2595                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2596                                         /* Save current interrupt mask */
2597                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2598
2599                                         /* Disable all interrupts while we muck with
2600                                          * the hardware directly
2601                                          */
2602                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2603
2604                                         /* Send the Setup packet */
2605                                         do_setup();
2606
2607                                         /* 15 second delay so nothing else happens for awhile */
2608                                         mdelay(15000);
2609
2610                                         /* Send the In and Ack packets */
2611                                         do_in_ack();
2612
2613                                         /* 15 second delay so nothing else happens for awhile */
2614                                         mdelay(15000);
2615
2616                                         /* Restore interrupts */
2617                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2618                                 }
2619                         }
2620                         break;
2621                 }
2622 #endif /* DWC_HS_ELECT_TST */
2623
2624                 case USB_PORT_FEAT_INDICATOR:
2625                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2626                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2627                         /* Not supported */
2628                         break;
2629                 default:
2630                         retval = -EINVAL;
2631                         DWC_ERROR ("DWC OTG HCD - "
2632                                    "SetPortFeature request %xh "
2633                                    "unknown or unsupported\n", _wValue);
2634                         break;
2635                 }
2636                 break;
2637         default:
2638         error:
2639                 retval = -EINVAL;
2640                 DWC_WARN ("DWC OTG HCD - "
2641                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2642                           _typeReq, _wIndex, _wValue);
2643                 break;
2644         }
2645
2646         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2647         return retval;
2648 }
2649
2650
2651 /**
2652  * Assigns transactions from a QTD to a free host channel and initializes the
2653  * host channel to perform the transactions. The host channel is removed from
2654  * the free list.
2655  *
2656  * @param _hcd The HCD state structure.
2657  * @param _qh Transactions from the first QTD for this QH are selected and
2658  * assigned to a free host channel.
2659  */
2660 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2661 {
2662         dwc_hc_t        *hc;
2663         dwc_otg_qtd_t   *qtd;
2664         struct urb      *urb;
2665
2666         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2667         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2668
2669         /* Remove the host channel from the free list. */
2670         list_del_init(&hc->hc_list_entry);
2671
2672         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2673         urb = qtd->urb;
2674         _qh->channel = hc;
2675         _qh->qtd_in_process = qtd;
2676
2677         /*
2678          * Use usb_pipedevice to determine device address. This address is
2679          * 0 before the SET_ADDRESS command and the correct address afterward.
2680          */
2681         hc->dev_addr = usb_pipedevice(urb->pipe);
2682         hc->ep_num = usb_pipeendpoint(urb->pipe);
2683
2684         if (urb->dev->speed == USB_SPEED_LOW) {
2685                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2686                 /*
2687                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2688                  * device connected.
2689                  */
2690         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2691         } else if (urb->dev->speed == USB_SPEED_FULL) {
2692                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2693                 /*
2694                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2695                  * device connected. warning: only support 1 device at root hub.
2696                  */
2697         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2698         } else {
2699                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2700         }
2701
2702         hc->max_packet = dwc_max_packet(_qh->maxp);
2703
2704         hc->xfer_started = 0;
2705         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2706         hc->error_state = (qtd->error_count > 0);
2707         hc->halt_on_queue = 0;
2708         hc->halt_pending = 0;
2709         hc->requests = 0;
2710
2711         /*
2712          * The following values may be modified in the transfer type section
2713          * below. The xfer_len value may be reduced when the transfer is
2714          * started to accommodate the max widths of the XferSize and PktCnt
2715          * fields in the HCTSIZn register.
2716          */
2717         hc->do_ping = _qh->ping_state;
2718         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2719         hc->data_pid_start = _qh->data_toggle;
2720         hc->multi_count = 1;
2721
2722         if (_hcd->core_if->dma_enable) {
2723                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2724         } else {
2725                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2726         }
2727         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2728         hc->xfer_count = 0;
2729
2730         /*
2731          * Set the split attributes
2732          */
2733         hc->do_split = 0;
2734         if (_qh->do_split) {
2735                 hc->do_split = 1;
2736                 hc->xact_pos = qtd->isoc_split_pos;
2737                 hc->complete_split = qtd->complete_split;
2738                 hc->hub_addr = urb->dev->tt->hub->devnum;
2739                 hc->port_addr = urb->dev->ttport;
2740         }
2741
2742         switch (usb_pipetype(urb->pipe)) {
2743         case PIPE_CONTROL:
2744                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2745                 switch (qtd->control_phase) {
2746                 case DWC_OTG_CONTROL_SETUP:
2747                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2748                         hc->do_ping = 0;
2749                         hc->ep_is_in = 0;
2750                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2751                         if (_hcd->core_if->dma_enable) {
2752                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2753                         } else {
2754                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2755                         }
2756                         hc->xfer_len = 8;
2757                         break;
2758                 case DWC_OTG_CONTROL_DATA:
2759                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2760                         hc->data_pid_start = qtd->data_toggle;
2761                         break;
2762                 case DWC_OTG_CONTROL_STATUS:
2763                         /*
2764                          * Direction is opposite of data direction or IN if no
2765                          * data.
2766                          */
2767                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2768                         if (urb->transfer_buffer_length == 0) {
2769                                 hc->ep_is_in = 1;
2770                         } else {
2771                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2772                         }
2773                         if (hc->ep_is_in) {
2774                                 hc->do_ping = 0;
2775                         }
2776                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2777                         hc->xfer_len = 0;
2778                         if (_hcd->core_if->dma_enable) {
2779                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2780                         } else {
2781                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2782                         }
2783                         break;
2784                 }
2785                 break;
2786         case PIPE_BULK:
2787                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2788                 break;
2789         case PIPE_INTERRUPT:
2790                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2791                 break;
2792         case PIPE_ISOCHRONOUS:
2793                 {
2794                         struct usb_iso_packet_descriptor *frame_desc;
2795                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2796                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2797                         if (_hcd->core_if->dma_enable) {
2798                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2799                         } else {
2800                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2801                         }
2802                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2803                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2804
2805                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2806                                 if (hc->xfer_len <= 188) {
2807                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2808                                 }
2809                                 else {
2810                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2811                                 }
2812                         }
2813                 }
2814                 break;
2815         }
2816
2817         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2818             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2819                 /*
2820                  * This value may be modified when the transfer is started to
2821                  * reflect the actual transfer length.
2822                  */
2823                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2824         }
2825
2826         dwc_otg_hc_init(_hcd->core_if, hc);
2827         hc->qh = _qh;
2828 }
2829
2830 /**
2831  * This function selects transactions from the HCD transfer schedule and
2832  * assigns them to available host channels. It is called from HCD interrupt
2833  * handler functions.
2834  *
2835  * @param _hcd The HCD state structure.
2836  *
2837  * @return The types of new transactions that were assigned to host channels.
2838  */
2839 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2840 {
2841         struct list_head                *qh_ptr;
2842         dwc_otg_qh_t                    *qh;
2843         int                             num_channels;
2844         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2845
2846 #ifdef DEBUG_SOF
2847         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2848 #endif
2849
2850         /* Process entries in the periodic ready list. */
2851         qh_ptr = _hcd->periodic_sched_ready.next;
2852         while (qh_ptr != &_hcd->periodic_sched_ready &&
2853                !list_empty(&_hcd->free_hc_list)) {
2854
2855                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2856                 assign_and_init_hc(_hcd, qh);
2857
2858                 /*
2859                  * Move the QH from the periodic ready schedule to the
2860                  * periodic assigned schedule.
2861                  */
2862                 qh_ptr = qh_ptr->next;
2863                 list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2864
2865                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2866         }
2867
2868         /*
2869          * Process entries in the inactive portion of the non-periodic
2870          * schedule. Some free host channels may not be used if they are
2871          * reserved for periodic transfers.
2872          */
2873         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2874         num_channels = _hcd->core_if->core_params->host_channels;
2875         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2876                 /*yk@rk 20100714
2877                (_hcd->non_periodic_channels <
2878                 num_channels - _hcd->periodic_channels) &&
2879                 */
2880                !list_empty(&_hcd->free_hc_list)) {
2881
2882                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2883                 assign_and_init_hc(_hcd, qh);
2884
2885                 /*
2886                  * Move the QH from the non-periodic inactive schedule to the
2887                  * non-periodic active schedule.
2888                  */
2889                 qh_ptr = qh_ptr->next;
2890                 list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2891
2892                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2893                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2894                 } else {
2895                         ret_val = DWC_OTG_TRANSACTION_ALL;
2896                 }
2897
2898                 _hcd->non_periodic_channels++;
2899         }
2900
2901         return ret_val;
2902 }
2903
2904 /**
2905  * Attempts to queue a single transaction request for a host channel
2906  * associated with either a periodic or non-periodic transfer. This function
2907  * assumes that there is space available in the appropriate request queue. For
2908  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2909  * is available in the appropriate Tx FIFO.
2910  *
2911  * @param _hcd The HCD state structure.
2912  * @param _hc Host channel descriptor associated with either a periodic or
2913  * non-periodic transfer.
2914  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2915  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2916  * transfers.
2917  *
2918  * @return 1 if a request is queued and more requests may be needed to
2919  * complete the transfer, 0 if no more requests are required for this
2920  * transfer, -1 if there is insufficient space in the Tx FIFO.
2921  */
2922 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2923                              dwc_hc_t *_hc,
2924                              uint16_t _fifo_dwords_avail)
2925 {
2926         int retval;
2927
2928         if (_hcd->core_if->dma_enable) {
2929                 if (!_hc->xfer_started) {
2930                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2931                         _hc->qh->ping_state = 0;
2932                 }
2933                 retval = 0;
2934         } else  if (_hc->halt_pending) {
2935                 /* Don't queue a request if the channel has been halted. */
2936                 retval = 0;
2937         } else if (_hc->halt_on_queue) {
2938                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
2939                 retval = 0;
2940         } else if (_hc->do_ping) {
2941                 if (!_hc->xfer_started) {
2942                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2943                 }
2944                 retval = 0;
2945         } else if (!_hc->ep_is_in ||
2946                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2947                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
2948                         if (!_hc->xfer_started) {
2949                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2950                                 retval = 1;
2951                         } else {
2952                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2953                         }
2954                 } else {
2955                         retval = -1;
2956                 }
2957         } else {
2958                 if (!_hc->xfer_started) {
2959                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2960                         retval = 1;
2961                 } else {
2962                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2963                 }
2964         }
2965
2966         return retval;
2967 }
2968
2969 /**
2970  * Processes active non-periodic channels and queues transactions for these
2971  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2972  * FIFO Empty interrupt is enabled if there are more transactions to queue as
2973  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2974  * FIFO Empty interrupt is disabled.
2975  */
2976 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
2977 {
2978         gnptxsts_data_t         tx_status;
2979         struct list_head        *orig_qh_ptr;
2980         dwc_otg_qh_t            *qh;
2981         int                     status;
2982         int                     no_queue_space = 0;
2983         int                     no_fifo_space = 0;
2984         int                     more_to_do = 0;
2985
2986         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
2987
2988         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
2989 #ifdef DEBUG
2990         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2991         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
2992                     tx_status.b.nptxqspcavail);
2993         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
2994                     tx_status.b.nptxfspcavail);
2995 #endif
2996         /*
2997          * Keep track of the starting point. Skip over the start-of-list
2998          * entry.
2999          */
3000         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3001                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3002         }
3003         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3004
3005         /*
3006          * Process once through the active list or until no more space is
3007          * available in the request queue or the Tx FIFO.
3008          */
3009         do {
3010                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3011                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3012                         no_queue_space = 1;
3013                         break;
3014                 }
3015
3016                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3017                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3018
3019                 if (status > 0) {
3020                         more_to_do = 1;
3021                 } else if (status < 0) {
3022                         no_fifo_space = 1;
3023                         break;
3024                 }
3025
3026                 /* Advance to next QH, skipping start-of-list entry. */
3027                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3028                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3029                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3030                 }
3031
3032         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3033
3034         if (!_hcd->core_if->dma_enable) {
3035                 gintmsk_data_t intr_mask = {.d32 = 0};
3036                 intr_mask.b.nptxfempty = 1;
3037
3038 #ifdef DEBUG
3039                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3040                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3041                             tx_status.b.nptxqspcavail);
3042                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3043                             tx_status.b.nptxfspcavail);
3044 #endif
3045                 if (more_to_do || no_queue_space || no_fifo_space) {
3046                         /*
3047                          * May need to queue more transactions as the request
3048                          * queue or Tx FIFO empties. Enable the non-periodic
3049                          * Tx FIFO empty interrupt. (Always use the half-empty
3050                          * level to ensure that new requests are loaded as
3051                          * soon as possible.)
3052                          */
3053                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3054                 } else {
3055                         /*
3056                          * Disable the Tx FIFO empty interrupt since there are
3057                          * no more transactions that need to be queued right
3058                          * now. This function is called from interrupt
3059                          * handlers to queue more transactions as transfer
3060                          * states change.
3061                          */
3062                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3063                 }
3064         }
3065 }
3066
3067 /**
3068  * Processes periodic channels for the next frame and queues transactions for
3069  * these channels to the DWC_otg controller. After queueing transactions, the
3070  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3071  * to queue as Periodic Tx FIFO or request queue space becomes available.
3072  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3073  */
3074 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3075 {
3076         hptxsts_data_t          tx_status;
3077         struct list_head        *qh_ptr;
3078         dwc_otg_qh_t            *qh;
3079         int                     status;
3080         int                     no_queue_space = 0;
3081         int                     no_fifo_space = 0;
3082
3083         dwc_otg_host_global_regs_t *host_regs;
3084         host_regs = _hcd->core_if->host_if->host_global_regs;
3085
3086         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3087 #ifdef DEBUG
3088         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3089         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3090                     tx_status.b.ptxqspcavail);
3091         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3092                     tx_status.b.ptxfspcavail);
3093 #endif
3094
3095         qh_ptr = _hcd->periodic_sched_assigned.next;
3096         while (qh_ptr != &_hcd->periodic_sched_assigned) {
3097                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3098                 if (tx_status.b.ptxqspcavail == 0) {
3099                         no_queue_space = 1;
3100                         break;
3101                 }
3102
3103                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3104
3105                 /*
3106                  * Set a flag if we're queuing high-bandwidth in slave mode.
3107                  * The flag prevents any halts to get into the request queue in
3108                  * the middle of multiple high-bandwidth packets getting queued.
3109                  */
3110                 if ((!_hcd->core_if->dma_enable) &&
3111                     (qh->channel->multi_count > 1))
3112                 {
3113                         _hcd->core_if->queuing_high_bandwidth = 1;
3114                 }
3115
3116                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3117                 if (status < 0) {
3118                         no_fifo_space = 1;
3119                         break;
3120                 }
3121
3122                 /*
3123                  * In Slave mode, stay on the current transfer until there is
3124                  * nothing more to do or the high-bandwidth request count is
3125                  * reached. In DMA mode, only need to queue one request. The
3126                  * controller automatically handles multiple packets for
3127                  * high-bandwidth transfers.
3128                  */
3129                 if (_hcd->core_if->dma_enable ||
3130                     (status == 0 ||
3131                      qh->channel->requests == qh->channel->multi_count)) {
3132                         qh_ptr = qh_ptr->next;
3133                         /*
3134                          * Move the QH from the periodic assigned schedule to
3135                          * the periodic queued schedule.
3136                          */
3137                         list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3138
3139                         /* done queuing high bandwidth */
3140                         _hcd->core_if->queuing_high_bandwidth = 0;
3141                 }
3142         }
3143
3144         if (!_hcd->core_if->dma_enable) {
3145                 dwc_otg_core_global_regs_t *global_regs;
3146                 gintmsk_data_t intr_mask = {.d32 = 0};
3147
3148                 global_regs = _hcd->core_if->core_global_regs;
3149                 intr_mask.b.ptxfempty = 1;
3150 #ifdef DEBUG
3151                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3152                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3153                             tx_status.b.ptxqspcavail);
3154                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3155                             tx_status.b.ptxfspcavail);
3156 #endif
3157                 if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
3158                     no_queue_space || no_fifo_space) {
3159                         /*
3160                          * May need to queue more transactions as the request
3161                          * queue or Tx FIFO empties. Enable the periodic Tx
3162                          * FIFO empty interrupt. (Always use the half-empty
3163                          * level to ensure that new requests are loaded as
3164                          * soon as possible.)
3165                          */
3166                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3167                 } else {
3168                         /*
3169                          * Disable the Tx FIFO empty interrupt since there are
3170                          * no more transactions that need to be queued right
3171                          * now. This function is called from interrupt
3172                          * handlers to queue more transactions as transfer
3173                          * states change.
3174                          */
3175                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3176                 }
3177         }
3178 }
3179
3180 /**
3181  * This function processes the currently active host channels and queues
3182  * transactions for these channels to the DWC_otg controller. It is called
3183  * from HCD interrupt handler functions.
3184  *
3185  * @param _hcd The HCD state structure.
3186  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3187  * periodic, or both).
3188  */
3189 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3190                                     dwc_otg_transaction_type_e _tr_type)
3191 {
3192 #ifdef DEBUG_SOF
3193         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3194 #endif
3195         /* Process host channels associated with periodic transfers. */
3196         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3197              _tr_type == DWC_OTG_TRANSACTION_ALL) &&
3198             !list_empty(&_hcd->periodic_sched_assigned)) {
3199
3200                 process_periodic_channels(_hcd);
3201         }
3202
3203         /* Process host channels associated with non-periodic transfers. */
3204         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3205              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3206                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3207                         process_non_periodic_channels(_hcd);
3208                 } else {
3209                         /*
3210                          * Ensure NP Tx FIFO empty interrupt is disabled when
3211                          * there are no non-periodic transfers to process.
3212                          */
3213                         gintmsk_data_t gintmsk = {.d32 = 0};
3214                         gintmsk.b.nptxfempty = 1;
3215                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3216                                          gintmsk.d32, 0);
3217                 }
3218         }
3219 }
3220
3221 /**
3222  * Sets the final status of an URB and returns it to the device driver. Any
3223  * required cleanup of the URB is performed.
3224  */
3225 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3226                               int _status)
3227 __releases(_hcd->lock)
3228 __acquires(_hcd->lock)
3229 {
3230
3231 #ifdef DEBUG
3232         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3233                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3234                           __func__, _urb, usb_pipedevice(_urb->pipe),
3235                           usb_pipeendpoint(_urb->pipe),
3236                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3237                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3238                         int i;
3239                         for (i = 0; i < _urb->number_of_packets; i++) {
3240                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3241                                           i, _urb->iso_frame_desc[i].status);
3242                         }
3243                 }
3244         }
3245 #endif
3246
3247
3248         _urb->hcpriv = NULL;
3249         usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
3250         spin_unlock(&_hcd->lock);
3251         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3252         spin_lock(&_hcd->lock);
3253 }
3254
3255
3256 /*
3257  * Returns the Queue Head for an URB.
3258  */
3259 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3260 {
3261         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3262         return (dwc_otg_qh_t *) ep->hcpriv;
3263 }
3264
3265 #ifdef DEBUG
3266 void dwc_print_setup_data (uint8_t *setup)
3267 {
3268         int i;
3269         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3270                 DWC_PRINT("Setup Data = MSB ");
3271                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3272                 DWC_PRINT("\n");
3273                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3274                 DWC_PRINT("  bmRequestType Type = ");
3275                 switch ((setup[0]&0x60) >> 5) {
3276                 case 0: DWC_PRINT("Standard\n"); break;
3277                 case 1: DWC_PRINT("Class\n"); break;
3278                 case 2: DWC_PRINT("Vendor\n"); break;
3279                 case 3: DWC_PRINT("Reserved\n"); break;
3280                 }
3281                 DWC_PRINT("  bmRequestType Recipient = ");
3282                 switch (setup[0]&0x1f) {
3283                 case 0: DWC_PRINT("Device\n"); break;
3284                 case 1: DWC_PRINT("Interface\n"); break;
3285                 case 2: DWC_PRINT("Endpoint\n"); break;
3286                 case 3: DWC_PRINT("Other\n"); break;
3287                 default: DWC_PRINT("Reserved\n"); break;
3288                 }
3289                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3290                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3291                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3292                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3293         }
3294 }
3295 #endif
3296
3297 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3298 #if 0
3299         DWC_PRINT("Frame remaining at SOF:\n");
3300         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3301                   _hcd->frrem_samples, _hcd->frrem_accum,
3302                   (_hcd->frrem_samples > 0) ?
3303                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3304
3305         DWC_PRINT("\n");
3306         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3307         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3308                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3309                   (_hcd->core_if->hfnum_7_samples > 0) ?
3310                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3311         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3312         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3313                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3314                   (_hcd->core_if->hfnum_0_samples > 0) ?
3315                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3316         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3317         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3318                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3319                   (_hcd->core_if->hfnum_other_samples > 0) ?
3320                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3321
3322         DWC_PRINT("\n");
3323         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3324         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3325                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3326                   (_hcd->hfnum_7_samples_a > 0) ?
3327                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3328         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3329         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3330                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3331                   (_hcd->hfnum_0_samples_a > 0) ?
3332                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3333         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3334         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3335                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3336                   (_hcd->hfnum_other_samples_a > 0) ?
3337                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3338
3339         DWC_PRINT("\n");
3340         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3341         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3342                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3343                   (_hcd->hfnum_7_samples_b > 0) ?
3344                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3345         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3346         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3347                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3348                   (_hcd->hfnum_0_samples_b > 0) ?
3349                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3350         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3351         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3352                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3353                   (_hcd->hfnum_other_samples_b > 0) ?
3354                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3355 #endif
3356 }
3357
3358 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3359 {
3360 #ifdef DEBUG
3361         int num_channels;
3362         int i;
3363         gnptxsts_data_t np_tx_status;
3364         hptxsts_data_t p_tx_status;
3365
3366         num_channels = _hcd->core_if->core_params->host_channels;
3367         DWC_PRINT("\n");
3368         DWC_PRINT("************************************************************\n");
3369         DWC_PRINT("HCD State:\n");
3370         DWC_PRINT("  Num channels: %d\n", num_channels);
3371         for (i = 0; i < num_channels; i++) {
3372                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3373                 DWC_PRINT("  Channel %d:\n", i);
3374                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3375                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3376                 DWC_PRINT("    speed: %d\n", hc->speed);
3377                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3378                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3379                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3380                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3381                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3382                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3383                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3384                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3385                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3386                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3387                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3388                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3389                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3390                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3391                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3392                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3393                 DWC_PRINT("    requests: %d\n", hc->requests);
3394                 DWC_PRINT("    qh: %p\n", hc->qh);
3395                 if (hc->xfer_started) {
3396                         hfnum_data_t hfnum;
3397                         hcchar_data_t hcchar;
3398                         hctsiz_data_t hctsiz;
3399                         hcint_data_t hcint;
3400                         hcintmsk_data_t hcintmsk;
3401                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3402                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3403                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3404                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3405                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3406                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3407                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3408                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3409                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3410                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3411                 }
3412                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3413                         dwc_otg_qtd_t *qtd;
3414                         struct urb *urb;
3415                         qtd = hc->qh->qtd_in_process;
3416                         urb = qtd->urb;
3417                         DWC_PRINT("    URB Info:\n");
3418                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3419                         if (urb != NULL) {
3420                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3421                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3422                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3423                                 DWC_PRINT("      Max packet size: %d\n",
3424                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3425                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3426                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3427                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3428                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3429                         }
3430                 }
3431         }
3432         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3433         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3434         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3435         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3436         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3437         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3438         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3439         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3440         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3441         dwc_otg_hcd_dump_frrem(_hcd);
3442         dwc_otg_dump_global_registers(_hcd->core_if);
3443         dwc_otg_dump_host_registers(_hcd->core_if);
3444         DWC_PRINT("************************************************************\n");
3445         DWC_PRINT("\n");
3446 #endif
3447 }
3448 #endif /* DWC_DEVICE_ONLY */