drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/clk.h>
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/init.h>
  46 #include <linux/device.h>
  47 #include <linux/errno.h>
  48 #include <linux/list.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/string.h>
  51 #include <linux/dma-mapping.h>
  52 #include <linux/irq.h>
  53 #include <linux/platform_device.h>
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65
  66     if(core_if->op_state == B_PERIPHERAL)
  67     {
  68         DWC_PRINT("%s, usb device mode\n", __func__);
  69         return 0;
  70     }
  71     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  72     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  73     if(hprt0.b.prtconnsts)  // usb device connected
  74     {
  75         //partial power-down
  76         if(!hprt0.b.prtsusp)
  77         {
  78             //hprt0.d32 = 0;
  79             hprt0.b.prtsusp = 1;
  80             hprt0.b.prtena = 0;
  81             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  82         }
  83         udelay(10);
  84         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  85         if(!hprt0.b.prtsusp)
  86         {
  87             //hprt0.d32 = 0;
  88             hprt0.b.prtsusp = 1;
  89             hprt0.b.prtena = 0;
  90             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  91         }
  92         mdelay(5);
  93         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  94         pcgcctl.b.pwrclmp = 1;//power clamp
  95         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  96         udelay(1);
  97         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
  98         pcgcctl.b.stoppclk = 1;//stop phy clk
  99         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 100     }
 101     else    //no device connect
 102     {
 103         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 104                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 0);
 105         }
 106     }
 107     udelay(3);
 108     #ifndef CONFIG_DWC_REMOTE_WAKEUP
 109     clk_disable(core_if->otg_dev->phyclk);
 110     clk_disable(core_if->otg_dev->ahbclk);
 111     #endif
 112     //power off
 113     return 0;
 114 }
 115
 116 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 117 {
 118     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 119     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 120     hprt0_data_t hprt0;
 121     pcgcctl_data_t pcgcctl;
 122     gintmsk_data_t gintmsk;
 123
 124     if(core_if->op_state == B_PERIPHERAL)
 125     {
 126         DWC_PRINT("%s, usb device mode\n", __func__);
 127         return 0;
 128     }
 129     #ifndef CONFIG_DWC_REMOTE_WAKEUP
 130     clk_enable(core_if->otg_dev->phyclk);
 131     clk_enable(core_if->otg_dev->ahbclk);
 132     #endif
 133     //partial power-down
 134     //power on
 135     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 136     pcgcctl.b.stoppclk = 0;//stop phy clk
 137     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 138     udelay(1);
 139     pcgcctl.b.pwrclmp = 0;//power clamp
 140     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 141     udelay(2);
 142
 143     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 144     gintmsk.b.portintr = 0;
 145     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 146
 147     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 148     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 149     if(hprt0.b.prtconnsts)
 150     {
 151         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 152         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 153         hprt0.b.prtpwr = 1;
 154         hprt0.b.prtres = 1;
 155         hprt0.b.prtena = 0;
 156         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 157         mdelay(20);
 158         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 159         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 160         //hprt0.d32 = 0;
 161         hprt0.b.prtpwr = 1;
 162         hprt0.b.prtres = 0;
 163         hprt0.b.prtena = 0;
 164         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 165         hprt0.d32 = 0;
 166         hprt0.b.prtpwr = 1;
 167         hprt0.b.prtena = 0;
 168         hprt0.b.prtconndet = 1;
 169         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 170
 171         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 172         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 173
 174         mdelay(10);
 175     }
 176     else
 177     {
 178         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 179                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 1);
 180         }
 181     }
 182     gintmsk.b.portintr = 1;
 183     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 184
 185         return 0;
 186 }
 187
 188 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 189
 190 static const struct hc_driver dwc_otg_hc_driver = {
 191
 192         .description =          dwc_otg_hcd_name,
 193         .product_desc =         "DWC OTG Controller",
 194         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 195
 196         .irq =                  dwc_otg_hcd_irq,
 197
 198         .flags =                HCD_MEMORY | HCD_USB2,
 199
 200         //.reset =
 201         .start =                dwc_otg_hcd_start,
 202         //.suspend =
 203         //.resume =
 204
 205         /* yk@rk 20100625
 206          * core/hcd.c call hcd->driver->bus_suspend
 207          * otherwise system can not be suspended
 208          */
 209 #ifdef CONFIG_PM
 210         .bus_suspend =          dwc_otg_hcd_suspend,
 211         .bus_resume =           dwc_otg_hcd_resume,
 212 #endif
 213         .stop =                 dwc_otg_hcd_stop,
 214
 215         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 216         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 217         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 218
 219         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 220
 221         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 222         .hub_control =          dwc_otg_hcd_hub_control,
 223         //.hub_suspend =
 224         //.hub_resume =
 225 };
 226
 227 #ifdef CONFIG_USB11_HOST
 228 static const struct hc_driver host11_hc_driver = {
 229
 230         .description =          "host11_hcd",
 231         .product_desc =         "DWC OTG Controller",
 232         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 233
 234         .irq =                  dwc_otg_hcd_irq,
 235
 236         .flags =                HCD_MEMORY | HCD_USB2,
 237
 238         //.reset =
 239         .start =                dwc_otg_hcd_start,
 240         //.suspend =
 241         //.resume =
 242
 243         /* yk@rk 20100625
 244          * core/hcd.c call hcd->driver->bus_suspend
 245          * otherwise system can not be suspended
 246          */
 247 #ifdef CONFIG_PM
 248         .bus_suspend =          dwc_otg_hcd_suspend,
 249         .bus_resume =           dwc_otg_hcd_resume,
 250 #endif
 251         .stop =                 dwc_otg_hcd_stop,
 252
 253         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 254         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 255         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 256
 257         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 258
 259         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 260         .hub_control =          dwc_otg_hcd_hub_control,
 261         //.hub_suspend =
 262         //.hub_resume =
 263 };
 264 #endif
 265 #ifdef CONFIG_USB20_HOST
 266 static const struct hc_driver host20_hc_driver = {
 267
 268         .description =          "host20_hcd",
 269         .product_desc =         "DWC OTG Controller",
 270         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 271
 272         .irq =                  dwc_otg_hcd_irq,
 273
 274         .flags =                HCD_MEMORY | HCD_USB2,
 275
 276         //.reset =
 277         .start =                dwc_otg_hcd_start,
 278         //.suspend =
 279         //.resume =
 280
 281         /* yk@rk 20100625
 282          * core/hcd.c call hcd->driver->bus_suspend
 283          * otherwise system can not be suspended
 284          */
 285 #ifdef CONFIG_PM
 286         .bus_suspend =          dwc_otg_hcd_suspend,
 287         .bus_resume =           dwc_otg_hcd_resume,
 288 #endif
 289         .stop =                 dwc_otg_hcd_stop,
 290
 291         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 292         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 293         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 294
 295         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 296
 297         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 298         .hub_control =          dwc_otg_hcd_hub_control,
 299         //.hub_suspend =
 300         //.hub_resume =
 301 };
 302 #endif
 303
 304 /**
 305  * Work queue function for starting the HCD when A-Cable is connected.
 306  * The dwc_otg_hcd_start() must be called in a process context.
 307  */
 308 static void hcd_start_func(struct work_struct *work)
 309 {
 310     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 311     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 312
 313     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 314     if (hcd) {
 315             dwc_otg_hcd_start(hcd);
 316     }
 317 }
 318
 319 /**
 320  * HCD Callback function for starting the HCD when A-Cable is
 321  * connected.
 322  *
 323  * @param _p void pointer to the <code>struct usb_hcd</code>
 324  */
 325 static int32_t dwc_otg_hcd_start_cb(void *_p)
 326 {
 327         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 328         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 329         hprt0_data_t hprt0;
 330
 331         if (core_if->op_state == B_HOST) {
 332                 /*
 333                  * Reset the port.  During a HNP mode switch the reset
 334                  * needs to occur within 1ms and have a duration of at
 335                  * least 50ms.
 336                  */
 337                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 338                 hprt0.b.prtrst = 1;
 339                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 340                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 341         } else {
 342                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 343         }
 344
 345         /* Need to start the HCD in a non-interrupt context. */
 346 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 347         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 348         schedule_work(&dwc_otg_hcd->start_work);
 349
 350         return 1;
 351 }
 352
 353
 354 /**
 355  * HCD Callback function for stopping the HCD.
 356  *
 357  * @param _p void pointer to the <code>struct usb_hcd</code>
 358  */
 359 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 360 {
 361         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 362         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 363         dwc_otg_hcd_stop( usb_hcd );
 364         return 1;
 365 }
 366
 367 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 368 {
 369 #ifdef DEBUG
 370         int i;
 371         int num_channels = _hcd->core_if->core_params->host_channels;
 372         for (i = 0; i < num_channels; i++) {
 373                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 374         }
 375 #endif
 376 }
 377
 378 static void del_timers(dwc_otg_hcd_t *_hcd)
 379 {
 380         del_xfer_timers(_hcd);
 381         del_timer(&_hcd->conn_timer);
 382 }
 383
 384 /**
 385  * Processes all the URBs in a single list of QHs. Completes them with
 386  * -ETIMEDOUT and frees the QTD.
 387  */
 388 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 389 {
 390         struct list_head        *qh_item;
 391         dwc_otg_qh_t            *qh;
 392         struct list_head        *qtd_item;
 393         dwc_otg_qtd_t           *qtd;
 394         struct urb              *urb;
 395         struct usb_host_endpoint *ep;
 396
 397         list_for_each(qh_item, _qh_list) {
 398                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 399                 for (qtd_item = qh->qtd_list.next;
 400                      qtd_item != &qh->qtd_list;
 401                      qtd_item = qh->qtd_list.next) {
 402                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 403                         if (qtd->urb != NULL) {
 404                         urb = qtd->urb;
 405                         ep = qtd->urb->ep;
 406                             // 20110415 yk
 407                             // urb will be re entry to ep->urb_list if use ETIMEOUT
 408                                 dwc_otg_hcd_complete_urb(_hcd, qtd->urb,
 409                                                          -ETIMEDOUT);//ESHUTDOWN
 410
 411                         //if(!list_empty(&ep->urb_list))
 412                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
 413                           __func__, urb, usb_pipedevice(urb->pipe),
 414                           usb_pipeendpoint(urb->pipe),
 415                           usb_pipein(urb->pipe) ? "IN" : "OUT", urb->unlinked);
 416
 417                 if (!urb->unlinked)
 418                     urb->unlinked = -ESHUTDOWN;
 419
 420                         }
 421                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 422                 }
 423         }
 424 }
 425
 426 /**
 427  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 428  * and periodic schedules. The QTD associated with each URB is removed from
 429  * the schedule and freed. This function may be called when a disconnect is
 430  * detected or when the HCD is being stopped.
 431  */
 432 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 433 {
 434         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 435         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 436         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 437         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 438         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 439         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 440 }
 441
 442 /**
 443  * HCD Callback function for disconnect of the HCD.
 444  *
 445  * @param _p void pointer to the <code>struct usb_hcd</code>
 446  */
 447 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 448 {
 449         gintsts_data_t  intr;
 450     dwc_otg_hcd_t       *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 451
 452     //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 453
 454     /*
 455      * Set status flags for the hub driver.
 456      */
 457     dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 458         dwc_otg_hcd->flags.b.port_connect_status = 0;
 459
 460     /*
 461      * Shutdown any transfers in process by clearing the Tx FIFO Empty
 462      * interrupt mask and status bits and disabling subsequent host
 463      * channel interrupts.
 464      */
 465     intr.d32 = 0;
 466     intr.b.nptxfempty = 1;
 467     intr.b.ptxfempty = 1;
 468         intr.b.hcintr = 1;
 469     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 470     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 471
 472         del_timers(dwc_otg_hcd);
 473
 474         /*
 475          * Turn off the vbus power only if the core has transitioned to device
 476          * mode. If still in host mode, need to keep power on to detect a
 477          * reconnection.
 478          */
 479         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 480                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 481                         hprt0_data_t hprt0 = { .d32=0 };
 482                         DWC_PRINT("Disconnect: PortPower off\n");
 483                         hprt0.b.prtpwr = 0;
 484                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 485                 }
 486
 487                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 488         }
 489
 490         /* Respond with an error status to all URBs in the schedule. */
 491         kill_all_urbs(dwc_otg_hcd);
 492
 493         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 494                 /* Clean up any host channels that were in use. */
 495                 int                     num_channels;
 496                 int                     i;
 497                 dwc_hc_t                *channel;
 498                 dwc_otg_hc_regs_t       *hc_regs;
 499                 hcchar_data_t           hcchar;
 500
 501                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 502
 503                 if (!dwc_otg_hcd->core_if->dma_enable) {
 504                         /* Flush out any channel requests in slave mode. */
 505                         for (i = 0; i < num_channels; i++) {
 506                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 507                                 if (list_empty(&channel->hc_list_entry)) {
 508                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 509                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 510                                         if (hcchar.b.chen) {
 511                                                 hcchar.b.chen = 0;
 512                                                 hcchar.b.chdis = 1;
 513                                                 hcchar.b.epdir = 0;
 514                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 515                                         }
 516                                 }
 517                         }
 518                 }
 519
 520                 for (i = 0; i < num_channels; i++) {
 521                         channel = dwc_otg_hcd->hc_ptr_array[i];
 522                         if (list_empty(&channel->hc_list_entry)) {
 523                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 524                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 525                                 if (hcchar.b.chen) {
 526                                         /* Halt the channel. */
 527                                         hcchar.b.chdis = 1;
 528                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 529                                 }
 530
 531                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 532                                 list_add_tail(&channel->hc_list_entry,
 533                                               &dwc_otg_hcd->free_hc_list);
 534                         }
 535                 }
 536         }
 537
 538     /* A disconnect will end the session so the B-Device is no
 539      * longer a B-host. */
 540     ((struct usb_hcd *)_p)->self.is_b_host = 0;
 541     return 1;
 542 }
 543
 544 /**
 545  * Connection timeout function.  An OTG host is required to display a
 546  * message if the device does not connect within 10 seconds.
 547  */
 548 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 549 {
 550         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 551         DWC_PRINT( "Connect Timeout\n");
 552         DWC_ERROR( "Device Not Connected/Responding\n" );
 553 }
 554
 555 /**
 556  * Start the connection timer.  An OTG host is required to display a
 557  * message if the device does not connect within 10 seconds.  The
 558  * timer is deleted if a port connect interrupt occurs before the
 559  * timer expires.
 560  */
 561 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 562 {
 563         init_timer( &_hcd->conn_timer );
 564         _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 565         _hcd->conn_timer.data = (unsigned long)0;
 566         _hcd->conn_timer.expires = jiffies + (HZ*10);
 567         add_timer( &_hcd->conn_timer );
 568 }
 569
 570 /**
 571  * HCD Callback function for disconnect of the HCD.
 572  *
 573  * @param _p void pointer to the <code>struct usb_hcd</code>
 574  */
 575 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 576 {
 577         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 578         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 579         dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 580         return 1;
 581 }
 582
 583 /*
 584  * suspend: 0 usb phy enable
 585  *          1 usb phy suspend
 586  */
 587 static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
 588 {
 589     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 590
 591     if(suspend) {
 592         *otg_phy_con1 |= (0x01<<2);
 593         *otg_phy_con1 |= (0x01<<3);    // exit suspend.
 594         *otg_phy_con1 &= ~(0x01<<2);
 595
 596         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 597     }
 598     else
 599     {
 600         *otg_phy_con1 |= (0x01<<2);
 601         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
 602         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 603     }
 604
 605     return suspend;
 606 }
 607
 608 /**
 609  * HCD Callback structure for handling mode switching.
 610  */
 611 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 612         .start = dwc_otg_hcd_start_cb,
 613         .stop = dwc_otg_hcd_stop_cb,
 614         .disconnect = dwc_otg_hcd_disconnect_cb,
 615         .session_start = dwc_otg_hcd_session_start_cb,
 616         .suspend = dwc_otg_phy_suspend_cb,
 617         .p = 0,//hcd
 618 };
 619
 620 /**
 621  * Reset tasklet function
 622  */
 623 static void reset_tasklet_func (unsigned long data)
 624 {
 625         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 626         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 627         hprt0_data_t hprt0;
 628
 629         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 630
 631         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 632         hprt0.b.prtrst = 1;
 633         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 634         mdelay (60);
 635
 636         hprt0.b.prtrst = 0;
 637         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 638         dwc_otg_hcd->flags.b.port_reset_change = 1;
 639
 640         return;
 641 }
 642
 643 static struct tasklet_struct reset_tasklet = {
 644         .next = NULL,
 645         .state = 0,
 646         .count = ATOMIC_INIT(0),
 647         .func = reset_tasklet_func,
 648         .data = 0,
 649 };
 650
 651 /**
 652  * Initializes the HCD. This function allocates memory for and initializes the
 653  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 654  * USB bus with the core and calls the hc_driver->start() function. It returns
 655  * a negative error on failure.
 656  */
 657 extern uint32_t g_dbg_lvl;
 658 int __devinit dwc_otg_hcd_init(struct device *dev)
 659 {
 660         struct usb_hcd *hcd = NULL;
 661         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 662     dwc_otg_device_t *otg_dev = dev->platform_data;
 663
 664         int             num_channels;
 665         int             i;
 666         dwc_hc_t        *channel;
 667
 668         int retval = 0;
 669 #if 1  //kaiker .these code must execute before usb_create_hcd
 670         /* Set device flags indicating whether the HCD supports DMA. */
 671         static u64 usb_dmamask = 0xffffffffUL;
 672         if (otg_dev->core_if->dma_enable) {
 673                 dev->dma_mask = &usb_dmamask;
 674                 dev->coherent_dma_mask = ~0;
 675         } else {
 676                 dev->dma_mask = (void *)0;
 677                 dev->coherent_dma_mask = 0;
 678         }
 679 #endif
 680 //      g_dbg_lvl = 0xff;
 681
 682         /*
 683          * Allocate memory for the base HCD plus the DWC OTG HCD.
 684          * Initialize the base HCD.
 685          */
 686         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 687         if (hcd == NULL) {
 688                 retval = -ENOMEM;
 689                 goto error1;
 690         }
 691         hcd->regs = otg_dev->base;
 692         hcd->self.otg_port = 1;
 693
 694         /* Initialize the DWC OTG HCD. */
 695         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 696
 697         spin_lock_init(&dwc_otg_hcd->global_lock);
 698
 699         dwc_otg_hcd->core_if = otg_dev->core_if;
 700         otg_dev->hcd = dwc_otg_hcd;
 701
 702 #ifdef CONFIG_USB20_OTG_EN
 703     dwc_otg_hcd->host_enabled = 1;
 704 #else
 705     dwc_otg_hcd->host_enabled = 0;
 706 #endif
 707
 708         /* Register the HCD CIL Callbacks */
 709         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 710                                            &hcd_cil_callbacks, hcd);
 711
 712         /* Initialize the non-periodic schedule. */
 713         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 714         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 715
 716         /* Initialize the periodic schedule. */
 717         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 718         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 719         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 720         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 721
 722         /*
 723          * Create a host channel descriptor for each host channel implemented
 724          * in the controller. Initialize the channel descriptor array.
 725          */
 726         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 727         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 728         for (i = 0; i < num_channels; i++) {
 729                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 730                 if (channel == NULL) {
 731                         retval = -ENOMEM;
 732                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 733                         goto error2;
 734                 }
 735                 memset(channel, 0, sizeof(dwc_hc_t));
 736                 channel->hc_num = i;
 737                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 738 #ifdef DEBUG
 739                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 740 #endif
 741
 742                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 743         }
 744
 745         /* Initialize the Connection timeout timer. */
 746         init_timer( &dwc_otg_hcd->conn_timer );
 747
 748         /* Initialize reset tasklet. */
 749         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 750         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 751         /*
 752          * Finish generic HCD initialization and start the HCD. This function
 753          * allocates the DMA buffer pool, registers the USB bus, requests the
 754          * IRQ line, and calls dwc_otg_hcd_start method.
 755          */
 756         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 757                                         IRQF_SHARED);
 758         if (retval < 0) {
 759                 DWC_ERROR("usb_add_hcd fail,everest\n");
 760                 goto error2;
 761         }
 762         /*
 763          * Allocate space for storing data on status transactions. Normally no
 764          * data is sent, but this space acts as a bit bucket. This must be
 765          * done after usb_add_hcd since that function allocates the DMA buffer
 766          * pool.
 767          */
 768         if (otg_dev->core_if->dma_enable) {
 769                 dwc_otg_hcd->status_buf =
 770                         dma_alloc_coherent(dev,
 771                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 772                                            &dwc_otg_hcd->status_buf_dma,
 773                                            GFP_KERNEL | GFP_DMA);
 774         } else {
 775                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 776                                                   GFP_KERNEL);
 777         }
 778         if (dwc_otg_hcd->status_buf == NULL) {
 779                 retval = -ENOMEM;
 780                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 781                 goto error3;
 782         }
 783
 784 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 785 //                  dev->bus_id, hcd->self.busnum);
 786
 787         return 0;
 788
 789         /* Error conditions */
 790  error3:
 791         usb_remove_hcd(hcd);
 792  error2:
 793         dwc_otg_hcd_free(hcd);
 794         usb_put_hcd(hcd);
 795
 796  error1:
 797         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 798         return retval;
 799 }
 800
 801 #ifdef CONFIG_USB11_HOST
 802 /*
 803  * suspend: 0 usb phy enable
 804  *          1 usb phy suspend
 805  */
 806 static int32_t host11_phy_suspend_cb( void *_p, int suspend)
 807 {
 808     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 809
 810     if(suspend) {
 811         *otg_phy_con1 &= ~(0x01<<28);
 812         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 813     }
 814     else
 815     {
 816         *otg_phy_con1 |= (0x01<<28);
 817         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 818     }
 819
 820     return suspend;
 821 }
 822 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 823         .start = dwc_otg_hcd_start_cb,
 824         .stop = dwc_otg_hcd_stop_cb,
 825         .disconnect = dwc_otg_hcd_disconnect_cb,
 826         .session_start = dwc_otg_hcd_session_start_cb,
 827         .suspend = host11_phy_suspend_cb,
 828         .p = 0,//hcd
 829 };
 830
 831 static struct tasklet_struct host11_reset_tasklet = {
 832         .next = NULL,
 833         .state = 0,
 834         .count = ATOMIC_INIT(0),
 835         .func = reset_tasklet_func,
 836         .data = 0,
 837 };
 838
 839 int __devinit host11_hcd_init(struct device *dev)
 840 {
 841         struct usb_hcd *hcd = NULL;
 842         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 843     dwc_otg_device_t *otg_dev = dev->platform_data;
 844
 845         int             num_channels;
 846         int             i;
 847         dwc_hc_t        *channel;
 848
 849         int retval = 0;
 850 #if 1  //kaiker .these code must execute before usb_create_hcd
 851         /* Set device flags indicating whether the HCD supports DMA. */
 852         static u64 usb_dmamask = 0xffffffffUL;
 853         if (otg_dev->core_if->dma_enable) {
 854 //              DWC_PRINT("Using DMA mode\n");
 855                 dev->dma_mask = &usb_dmamask;
 856                 dev->coherent_dma_mask = ~0;
 857         } else {
 858 //              DWC_PRINT("Using Slave mode\n");
 859                 dev->dma_mask = (void *)0;
 860                 dev->coherent_dma_mask = 0;
 861         }
 862 #endif
 863 //      g_dbg_lvl = 0xff;
 864
 865         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 866
 867         /*
 868          * Allocate memory for the base HCD plus the DWC OTG HCD.
 869          * Initialize the base HCD.
 870          */
 871         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 872         if (hcd == NULL) {
 873                 retval = -ENOMEM;
 874                 goto error1;
 875         }
 876         hcd->regs = otg_dev->base;
 877         hcd->self.otg_port = 1;
 878
 879         /* Initialize the DWC OTG HCD. */
 880         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 881         dwc_otg_hcd->core_if = otg_dev->core_if;
 882         otg_dev->hcd = dwc_otg_hcd;
 883
 884 #ifdef CONFIG_USB11_HOST_EN
 885         dwc_otg_hcd->host_enabled = 1;
 886 #else
 887         dwc_otg_hcd->host_enabled = 0;
 888 #endif
 889
 890         spin_lock_init(&dwc_otg_hcd->global_lock);
 891
 892
 893         /* Register the HCD CIL Callbacks */
 894         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 895                                            &host11_cil_callbacks, hcd);
 896
 897         /* Initialize the non-periodic schedule. */
 898         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 899         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 900
 901         /* Initialize the periodic schedule. */
 902         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 903         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 904         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 905         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 906
 907         /*
 908          * Create a host channel descriptor for each host channel implemented
 909          * in the controller. Initialize the channel descriptor array.
 910          */
 911         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 912         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 913         for (i = 0; i < num_channels; i++) {
 914                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 915                 if (channel == NULL) {
 916                         retval = -ENOMEM;
 917                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 918                         goto error2;
 919                 }
 920                 memset(channel, 0, sizeof(dwc_hc_t));
 921                 channel->hc_num = i;
 922                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 923 #ifdef DEBUG
 924                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 925 #endif
 926
 927                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 928         }
 929
 930         /* Initialize the Connection timeout timer. */
 931         init_timer( &dwc_otg_hcd->conn_timer );
 932
 933         /* Initialize reset tasklet. */
 934         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 935         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 936         /*
 937          * Finish generic HCD initialization and start the HCD. This function
 938          * allocates the DMA buffer pool, registers the USB bus, requests the
 939          * IRQ line, and calls dwc_otg_hcd_start method.
 940          */
 941         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 942                                         IRQF_SHARED);
 943         if (retval < 0) {
 944                 DWC_ERROR("usb_add_hcd fail,everest\n");
 945                 goto error2;
 946         }
 947         /*
 948          * Allocate space for storing data on status transactions. Normally no
 949          * data is sent, but this space acts as a bit bucket. This must be
 950          * done after usb_add_hcd since that function allocates the DMA buffer
 951          * pool.
 952          */
 953         if (otg_dev->core_if->dma_enable) {
 954                 dwc_otg_hcd->status_buf =
 955                         dma_alloc_coherent(dev,
 956                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 957                                            &dwc_otg_hcd->status_buf_dma,
 958                                            GFP_KERNEL | GFP_DMA);
 959         } else {
 960                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 961                                                   GFP_KERNEL);
 962         }
 963         if (dwc_otg_hcd->status_buf == NULL) {
 964                 retval = -ENOMEM;
 965                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 966                 goto error3;
 967         }
 968
 969 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 970 //                  dev->bus_id, hcd->self.busnum);
 971
 972         return 0;
 973
 974         /* Error conditions */
 975  error3:
 976         usb_remove_hcd(hcd);
 977  error2:
 978         dwc_otg_hcd_free(hcd);
 979         usb_put_hcd(hcd);
 980
 981  error1:
 982         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 983         return retval;
 984 }
 985 #endif
 986 #ifdef CONFIG_USB20_HOST
 987
 988 /*
 989  * suspend: 0 usb phy enable
 990  *          1 usb phy suspend
 991  */
 992 static int32_t host20_phy_suspend_cb( void *_p, int suspend)
 993 {
 994     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 995     uint32_t regval;
 996
 997     regval = *otg_phy_con1;
 998
 999     if(suspend) {
1000         regval |= (0x01<<14);    // exit suspend.
1001         regval &= ~(0x01<<13);
1002
1003         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
1004     }
1005     else
1006     {
1007         regval &= ~(0x01<<14);    // exit suspend.
1008         regval |= (0x01<<13);    // software control
1009         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
1010     }
1011     *otg_phy_con1 = regval;
1012
1013     return suspend;
1014 }
1015
1016 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1017         .start = dwc_otg_hcd_start_cb,
1018         .stop = dwc_otg_hcd_stop_cb,
1019         .disconnect = dwc_otg_hcd_disconnect_cb,
1020         .session_start = dwc_otg_hcd_session_start_cb,
1021         .suspend = host20_phy_suspend_cb,
1022         .p = 0,//hcd
1023 };
1024
1025 static struct tasklet_struct host20_reset_tasklet = {
1026         .next = NULL,
1027         .state = 0,
1028         .count = ATOMIC_INIT(0),
1029         .func = reset_tasklet_func,
1030         .data = 0,
1031 };
1032
1033 int __devinit host20_hcd_init(struct device *dev)
1034 {
1035         struct usb_hcd *hcd = NULL;
1036         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1037     dwc_otg_device_t *otg_dev = dev->platform_data;
1038
1039         int             num_channels;
1040         int             i;
1041         dwc_hc_t        *channel;
1042
1043         int retval = 0;
1044 #if 1  //kaiker .these code must execute before usb_create_hcd
1045         /* Set device flags indicating whether the HCD supports DMA. */
1046         static u64 usb_dmamask = 0xffffffffUL;
1047         if (otg_dev->core_if->dma_enable) {
1048 //              DWC_PRINT("Using DMA mode\n");
1049                 dev->dma_mask = &usb_dmamask;
1050                 dev->coherent_dma_mask = ~0;
1051         } else {
1052 //              DWC_PRINT("Using Slave mode\n");
1053                 dev->dma_mask = (void *)0;
1054                 dev->coherent_dma_mask = 0;
1055         }
1056 #endif
1057 //      g_dbg_lvl = 0xff;
1058
1059         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1060
1061         /*
1062          * Allocate memory for the base HCD plus the DWC OTG HCD.
1063          * Initialize the base HCD.
1064          */
1065         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1066         if (hcd == NULL) {
1067                 retval = -ENOMEM;
1068                 goto error1;
1069         }
1070         hcd->regs = otg_dev->base;
1071         hcd->self.otg_port = 1;
1072
1073         /* Initialize the DWC OTG HCD. */
1074         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1075         dwc_otg_hcd->core_if = otg_dev->core_if;
1076         otg_dev->hcd = dwc_otg_hcd;
1077
1078 #ifdef CONFIG_USB20_HOST_EN
1079         dwc_otg_hcd->host_enabled = 1;
1080 #else
1081         dwc_otg_hcd->host_enabled = 0;
1082 #endif
1083
1084         spin_lock_init(&dwc_otg_hcd->global_lock);
1085
1086
1087         /* Register the HCD CIL Callbacks */
1088         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1089                                            &host20_cil_callbacks, hcd);
1090
1091         /* Initialize the non-periodic schedule. */
1092         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1093         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1094
1095         /* Initialize the periodic schedule. */
1096         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1097         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1098         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1099         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1100
1101         /*
1102          * Create a host channel descriptor for each host channel implemented
1103          * in the controller. Initialize the channel descriptor array.
1104          */
1105         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1106         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1107         for (i = 0; i < num_channels; i++) {
1108                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1109                 if (channel == NULL) {
1110                         retval = -ENOMEM;
1111                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1112                         goto error2;
1113                 }
1114                 memset(channel, 0, sizeof(dwc_hc_t));
1115                 channel->hc_num = i;
1116                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1117 #ifdef DEBUG
1118                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1119 #endif
1120
1121                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1122         }
1123
1124         /* Initialize the Connection timeout timer. */
1125         init_timer( &dwc_otg_hcd->conn_timer );
1126
1127         /* Initialize reset tasklet. */
1128         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1129         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1130         /*
1131          * Finish generic HCD initialization and start the HCD. This function
1132          * allocates the DMA buffer pool, registers the USB bus, requests the
1133          * IRQ line, and calls dwc_otg_hcd_start method.
1134          */
1135         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1136                                         IRQF_SHARED);
1137         if (retval < 0) {
1138                 DWC_ERROR("usb_add_hcd fail,everest\n");
1139                 goto error2;
1140         }
1141         /*
1142          * Allocate space for storing data on status transactions. Normally no
1143          * data is sent, but this space acts as a bit bucket. This must be
1144          * done after usb_add_hcd since that function allocates the DMA buffer
1145          * pool.
1146          */
1147         if (otg_dev->core_if->dma_enable) {
1148                 dwc_otg_hcd->status_buf =
1149                         dma_alloc_coherent(dev,
1150                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1151                                            &dwc_otg_hcd->status_buf_dma,
1152                                            GFP_KERNEL | GFP_DMA);
1153         } else {
1154                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1155                                                   GFP_KERNEL);
1156         }
1157         if (dwc_otg_hcd->status_buf == NULL) {
1158                 retval = -ENOMEM;
1159                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1160                 goto error3;
1161         }
1162
1163
1164         return 0;
1165
1166         /* Error conditions */
1167  error3:
1168         usb_remove_hcd(hcd);
1169  error2:
1170         dwc_otg_hcd_free(hcd);
1171         usb_put_hcd(hcd);
1172
1173  error1:
1174         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1175         return retval;
1176 }
1177 #endif
1178
1179 /**
1180  * Removes the HCD.
1181  * Frees memory and resources associated with the HCD and deregisters the bus.
1182  */
1183 void dwc_otg_hcd_remove(struct device *dev)
1184 {
1185         dwc_otg_device_t *otg_dev = dev->platform_data;
1186     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1187         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1188
1189         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1190
1191         /* Turn off all interrupts */
1192         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1193         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1194
1195         usb_remove_hcd(hcd);
1196         dwc_otg_hcd_free(hcd);
1197         usb_put_hcd(hcd);
1198
1199         return;
1200 }
1201
1202
1203 /* =========================================================================
1204  *  Linux HC Driver Functions
1205  * ========================================================================= */
1206
1207 /**
1208  * Initializes dynamic portions of the DWC_otg HCD state.
1209  */
1210 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1211 {
1212         struct list_head        *item;
1213         int                     num_channels;
1214         int                     i;
1215         dwc_hc_t                *channel;
1216         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1217
1218         _hcd->flags.d32 = 0;
1219
1220         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1221         _hcd->non_periodic_channels = 0;
1222         _hcd->periodic_channels = 0;
1223
1224         /*
1225          * Put all channels in the free channel list and clean up channel
1226          * states.
1227          */
1228         item = _hcd->free_hc_list.next;
1229         while (item != &_hcd->free_hc_list) {
1230                 list_del(item);
1231                 item = _hcd->free_hc_list.next;
1232         }
1233         num_channels = _hcd->core_if->core_params->host_channels;
1234         for (i = 0; i < num_channels; i++) {
1235                 channel = _hcd->hc_ptr_array[i];
1236                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1237                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1238         }
1239
1240         /* Initialize the DWC core for host mode operation. */
1241         dwc_otg_core_host_init(_hcd->core_if);
1242 }
1243
1244 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1245  * mode operation. Activates the root port. Returns 0 on success and a negative
1246  * error code on failure. */
1247 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1248 {
1249     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1250     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1251         unsigned long flags;
1252
1253         struct usb_bus *bus;
1254
1255         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1256         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1257
1258         bus = hcd_to_bus(_hcd);
1259         _hcd->state = HC_STATE_RUNNING;
1260
1261         /* Initialize and connect root hub if one is not already attached */
1262         if (bus->root_hub) {
1263                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1264                 /* Inform the HUB driver to resume. */
1265                 usb_hcd_resume_root_hub(_hcd);
1266         }
1267         else {
1268             /*
1269              * no use
1270              * yk@rk 2010121
1271             struct usb_device *udev;6
1272                 udev = usb_alloc_dev(NULL, bus, 0);
1273                 udev->speed = USB_SPEED_HIGH;
1274                 if (!udev) {
1275                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1276                         return -ENODEV;
1277                 }
1278         */
1279             /* Not needed - VJ
1280                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1281                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1282                return -ENODEV;
1283                }
1284              */
1285         }
1286         /* Initialize the bus state.  If the core is in Device Mode
1287          * HALT the USB bus and return. */
1288         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1289                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1290                 //_hcd->state = HC_STATE_HALT;
1291                 goto out;
1292         }
1293         hcd_reinit(dwc_otg_hcd);
1294 out:
1295         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1296
1297         return 0;
1298 }
1299
1300 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1301 {
1302         struct list_head        *item;
1303         dwc_otg_qh_t            *qh;
1304
1305         if (_qh_list->next == NULL) {
1306                 /* The list hasn't been initialized yet. */
1307                 return;
1308         }
1309
1310         /* Ensure there are no QTDs or URBs left. */
1311         kill_urbs_in_qh_list(_hcd, _qh_list);
1312
1313         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1314                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1315                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1316         }
1317 }
1318
1319 /**
1320  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1321  * stopped.
1322  */
1323 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1324 {
1325         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1326         hprt0_data_t hprt0 = { .d32=0 };
1327
1328         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1329
1330         /* Turn off all host-specific interrupts. */
1331         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1332
1333         /*
1334          * The root hub should be disconnected before this function is called.
1335          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1336          * and the QH lists (via ..._hcd_endpoint_disable).
1337          */
1338
1339         /* Turn off the vbus power */
1340         DWC_PRINT("PortPower off\n");
1341         hprt0.b.prtpwr = 0;
1342         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1343
1344         return;
1345 }
1346
1347
1348 /** Returns the current frame number. */
1349 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1350 {
1351         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1352         hfnum_data_t hfnum;
1353
1354         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1355                                    host_if->host_global_regs->hfnum);
1356
1357 #ifdef DEBUG_SOF
1358         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1359 #endif
1360         return hfnum.b.frnum;
1361 }
1362
1363 /**
1364  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1365  * in the struct usb_hcd field.
1366  */
1367 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1368 {
1369         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1370         int             i;
1371
1372         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1373
1374         del_timers(dwc_otg_hcd);
1375
1376         /* Free memory for QH/QTD lists */
1377         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1378         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1379         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1380         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1381         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1382         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1383
1384         /* Free memory for the host channels. */
1385         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1386                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1387                 if (hc != NULL) {
1388                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1389                         kfree(hc);
1390                 }
1391         }
1392
1393         if (dwc_otg_hcd->core_if->dma_enable) {
1394                 if (dwc_otg_hcd->status_buf_dma) {
1395                         dma_free_coherent(_hcd->self.controller,
1396                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1397                                           dwc_otg_hcd->status_buf,
1398                                           dwc_otg_hcd->status_buf_dma);
1399                 }
1400         } else if (dwc_otg_hcd->status_buf != NULL) {
1401                 kfree(dwc_otg_hcd->status_buf);
1402         }
1403
1404         return;
1405 }
1406
1407
1408 #ifdef DEBUG
1409 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1410 {
1411         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1412         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1413                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1414         DWC_PRINT("  Endpoint type: %s\n",
1415                   ({char *pipetype;
1416                   switch (usb_pipetype(_urb->pipe)) {
1417                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1418                   case PIPE_BULK: pipetype = "BULK"; break;
1419                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1420                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1421                   default: pipetype = "UNKNOWN"; break;
1422                   }; pipetype;}));
1423         DWC_PRINT("  Speed: %s\n",
1424                   ({char *speed;
1425                   switch (_urb->dev->speed) {
1426                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1427                   case USB_SPEED_FULL: speed = "FULL"; break;
1428                   case USB_SPEED_LOW: speed = "LOW"; break;
1429                   default: speed = "UNKNOWN"; break;
1430                   }; speed;}));
1431         DWC_PRINT("  Max packet size: %d\n",
1432                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1433         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1434         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1435                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1436         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1437                   _urb->setup_packet, (void *)_urb->setup_dma);
1438         DWC_PRINT("  Interval: %d\n", _urb->interval);
1439         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1440                 int i;
1441                 for (i = 0; i < _urb->number_of_packets;  i++) {
1442                         DWC_PRINT("  ISO Desc %d:\n", i);
1443                         DWC_PRINT("    offset: %d, length %d\n",
1444                                   _urb->iso_frame_desc[i].offset,
1445                                   _urb->iso_frame_desc[i].length);
1446                 }
1447         }
1448 }
1449
1450 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1451                               dwc_otg_qh_t *qh)
1452 {
1453         if (qh->channel != NULL) {
1454                 dwc_hc_t *hc = qh->channel;
1455                 struct list_head *item;
1456                 dwc_otg_qh_t *qh_item;
1457                 int num_channels = _hcd->core_if->core_params->host_channels;
1458                 int i;
1459
1460                 dwc_otg_hc_regs_t *hc_regs;
1461                 hcchar_data_t   hcchar;
1462                 hcsplt_data_t   hcsplt;
1463                 hctsiz_data_t   hctsiz;
1464                 uint32_t        hcdma;
1465
1466                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1467                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1468                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1469                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1470                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1471
1472                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1473                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1474                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1475                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1476                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1477                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1478                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1479                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1480                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1481                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1482                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1483                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1484                 DWC_PRINT("    qh: %p\n", hc->qh);
1485                 DWC_PRINT("  NP inactive sched:\n");
1486                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1487                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1488                         DWC_PRINT("    %p\n", qh_item);
1489                 }
1490                 DWC_PRINT("  NP active sched:\n");
1491                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1492                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1493                         DWC_PRINT("    %p\n", qh_item);
1494                 }
1495                 DWC_PRINT("  Channels: \n");
1496                 for (i = 0; i < num_channels; i++) {
1497                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1498                         DWC_PRINT("    %2d: %p\n", i, hc);
1499                 }
1500         }
1501 }
1502 #endif
1503
1504 /** Starts processing a USB transfer request specified by a USB Request Block
1505  * (URB). mem_flags indicates the type of memory allocation to use while
1506  * processing this URB. */
1507 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1508                             struct urb *_urb,
1509                             gfp_t _mem_flags)
1510 {
1511         int retval;
1512         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1513         dwc_otg_qtd_t * qtd;
1514         unsigned long flags;
1515 #if 0
1516         retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
1517         if (retval)
1518         {
1519                 DWC_PRINT("%s, usb_hcd_link_urb_to_ep error\n", __func__);
1520                 return retval;
1521         }
1522 #endif
1523         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1524 #if 1
1525         /*
1526          * Make sure the start of frame interrupt is enabled now that
1527          * we know we should have queued data. The SOF interrupt
1528          * handler automatically disables itself when idle to reduce
1529          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1530          * for the disable
1531          */
1532         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1533                          DWC_SOF_INTR_MASK);
1534 #endif
1535 #ifdef DEBUG
1536             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1537                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1538         }
1539 #endif  /*  */
1540     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1541             /* No longer connected. */
1542                 retval =  -ENODEV;
1543                 goto out;
1544         }
1545         qtd = dwc_otg_hcd_qtd_create(_urb);
1546         if (qtd == NULL) {
1547                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1548                 retval = -ENOMEM;
1549                 goto out;
1550         }
1551         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1552         if (retval < 0) {
1553                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1554                            "Error status %d\n", retval);
1555                 dwc_otg_hcd_qtd_free(qtd);
1556         }
1557 out:
1558         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1559
1560         return retval;
1561 }
1562
1563 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1564  * success.  */
1565 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1566 {
1567         unsigned long flags;
1568         dwc_otg_hcd_t * dwc_otg_hcd;
1569         dwc_otg_qtd_t * urb_qtd;
1570         dwc_otg_qh_t * qh;
1571         struct usb_host_endpoint *_ep = _urb->ep;//dwc_urb_to_endpoint(_urb);
1572         //int retval;
1573
1574         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1575         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1576         if(_ep==NULL)
1577         {
1578                 DWC_PRINT("%s=====================================================\n",__func__);
1579                 DWC_PRINT("urb->ep is null\n");
1580                 return -1;
1581         }
1582         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1583         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1584         #if 0
1585         retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
1586         if (retval) {
1587                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1588                 return retval;
1589         }
1590         #endif
1591         if(urb_qtd == NULL)
1592         {
1593                 DWC_PRINT("%s,urb_qtd is null\n",__func__);
1594                 goto urb_qtd_null;
1595                 //return -1;
1596         }
1597         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1598
1599 #ifdef DEBUG
1600     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1601                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1602                 if (urb_qtd == qh->qtd_in_process) {
1603                         dump_channel_info(dwc_otg_hcd, qh);
1604                 }
1605         }
1606
1607 #endif  /*  */
1608 #if 1
1609     if (urb_qtd == qh->qtd_in_process) {
1610             /* The QTD is in process (it has been assigned to a channel). */
1611             if (dwc_otg_hcd->flags.b.port_connect_status) {
1612
1613                     /*
1614                      * If still connected (i.e. in host mode), halt the
1615                      * channel so it can be used for other transfers. If
1616                      * no longer connected, the host registers can't be
1617                      * written to halt the channel since the core is in
1618                      * device mode.
1619                      */
1620                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1621                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1622                 }
1623         }
1624
1625     /*
1626      * Free the QTD and clean up the associated QH. Leave the QH in the
1627      * schedule if it has any remaining QTDs.
1628      */
1629     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1630         if (urb_qtd == qh->qtd_in_process) {
1631                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1632                 qh->channel = NULL;
1633                 qh->qtd_in_process = NULL;
1634         } else if (list_empty(&qh->qtd_list)) {
1635                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1636         }
1637 #endif
1638
1639 urb_qtd_null:
1640         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1641         _urb->hcpriv = NULL;
1642         //usb_hcd_unlink_urb_from_ep(_hcd, _urb);
1643     /* Higher layer software sets URB status. */
1644         usb_hcd_giveback_urb(_hcd, _urb, _status);
1645         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1646                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1647                 DWC_PRINT("  urb->status = %d\n", _status);
1648         }
1649         return 0;
1650 }
1651
1652
1653 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1654  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1655  * must already be dequeued. */
1656 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1657                                   struct usb_host_endpoint *_ep)
1658
1659 {
1660         unsigned long flags;
1661         dwc_otg_qh_t *qh;
1662         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1663
1664         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1665
1666         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1667                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1668                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1669
1670         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1671         if (qh != NULL) {
1672 #ifdef DEBUG
1673                 /** Check that the QTD list is really empty */
1674                 if (!list_empty(&qh->qtd_list)) {
1675                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1676                                  " QTD List for this endpoint is not empty\n");
1677                 }
1678 #endif
1679
1680                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1681                 _ep->hcpriv = NULL;
1682         }
1683
1684         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1685
1686         return;
1687 }
1688
1689 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1690  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1691  * interrupt.
1692  *
1693  * This function is called by the USB core when an interrupt occurs */
1694 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1695 {
1696         irqreturn_t result;
1697         unsigned long flags;
1698         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1699
1700         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1701
1702         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1703
1704         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1705
1706         return result;
1707 }
1708
1709 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1710  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1711  * is the status change indicator for the single root port. Returns 1 if either
1712  * change indicator is 1, otherwise returns 0. */
1713 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1714                                 char *_buf)
1715 {
1716         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1717
1718         _buf[0] = 0;
1719         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1720                     dwc_otg_hcd->flags.b.port_reset_change ||
1721                     dwc_otg_hcd->flags.b.port_enable_change ||
1722                     dwc_otg_hcd->flags.b.port_suspend_change ||
1723                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1724
1725 #ifdef DEBUG
1726         if (_buf[0]) {
1727                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1728                             " Root port status changed\n");
1729                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1730                             dwc_otg_hcd->flags.b.port_connect_status_change);
1731                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1732                             dwc_otg_hcd->flags.b.port_reset_change);
1733                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1734                             dwc_otg_hcd->flags.b.port_enable_change);
1735                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1736                             dwc_otg_hcd->flags.b.port_suspend_change);
1737                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1738                             dwc_otg_hcd->flags.b.port_over_current_change);
1739         }
1740 #endif
1741         return (_buf[0] != 0);
1742 }
1743
1744 #ifdef DWC_HS_ELECT_TST
1745 /*
1746  * Quick and dirty hack to implement the HS Electrical Test
1747  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1748  *
1749  * This code was copied from our userspace app "hset". It sends a
1750  * Get Device Descriptor control sequence in two parts, first the
1751  * Setup packet by itself, followed some time later by the In and
1752  * Ack packets. Rather than trying to figure out how to add this
1753  * functionality to the normal driver code, we just hijack the
1754  * hardware, using these two function to drive the hardware
1755  * directly.
1756  */
1757
1758 dwc_otg_core_global_regs_t *global_regs;
1759 dwc_otg_host_global_regs_t *hc_global_regs;
1760 dwc_otg_hc_regs_t *hc_regs;
1761 uint32_t *data_fifo;
1762
1763 static void do_setup(void)
1764 {
1765         gintsts_data_t gintsts;
1766         hctsiz_data_t hctsiz;
1767         hcchar_data_t hcchar;
1768         haint_data_t haint;
1769         hcint_data_t hcint;
1770
1771         /* Enable HAINTs */
1772         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1773
1774         /* Enable HCINTs */
1775         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1776
1777         /* Read GINTSTS */
1778         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1779         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1780
1781         /* Read HAINT */
1782         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1783         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1784
1785         /* Read HCINT */
1786         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1787         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1788
1789         /* Read HCCHAR */
1790         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1791         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1792
1793         /* Clear HCINT */
1794         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1795
1796         /* Clear HAINT */
1797         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1798
1799         /* Clear GINTSTS */
1800         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1801
1802         /* Read GINTSTS */
1803         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1804         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1805
1806         /*
1807          * Send Setup packet (Get Device Descriptor)
1808          */
1809
1810         /* Make sure channel is disabled */
1811         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1812         if (hcchar.b.chen) {
1813                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1814                 hcchar.b.chdis = 1;
1815 //              hcchar.b.chen = 1;
1816                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1817                 //sleep(1);
1818                 mdelay(1000);
1819
1820                 /* Read GINTSTS */
1821                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1822                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1823
1824                 /* Read HAINT */
1825                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1826                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1827
1828                 /* Read HCINT */
1829                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1830                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1831
1832                 /* Read HCCHAR */
1833                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1834                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1835
1836                 /* Clear HCINT */
1837                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1838
1839                 /* Clear HAINT */
1840                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1841
1842                 /* Clear GINTSTS */
1843                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1844
1845                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1846                 //if (hcchar.b.chen) {
1847                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1848                 //}
1849         }
1850
1851         /* Set HCTSIZ */
1852         hctsiz.d32 = 0;
1853         hctsiz.b.xfersize = 8;
1854         hctsiz.b.pktcnt = 1;
1855         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1856         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1857
1858         /* Set HCCHAR */
1859         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1860         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1861         hcchar.b.epdir = 0;
1862         hcchar.b.epnum = 0;
1863         hcchar.b.mps = 8;
1864         hcchar.b.chen = 1;
1865         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1866
1867         /* Fill FIFO with Setup data for Get Device Descriptor */
1868         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1869         dwc_write_reg32(data_fifo++, 0x01000680);
1870         dwc_write_reg32(data_fifo++, 0x00080000);
1871
1872         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1873         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1874
1875         /* Wait for host channel interrupt */
1876         do {
1877                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1878         } while (gintsts.b.hcintr == 0);
1879
1880         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1881
1882         /* Disable HCINTs */
1883         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1884
1885         /* Disable HAINTs */
1886         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1887
1888         /* Read HAINT */
1889         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1890         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1891
1892         /* Read HCINT */
1893         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1894         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1895
1896         /* Read HCCHAR */
1897         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1898         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1899
1900         /* Clear HCINT */
1901         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1902
1903         /* Clear HAINT */
1904         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1905
1906         /* Clear GINTSTS */
1907         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1908
1909         /* Read GINTSTS */
1910         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1911         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1912 }
1913
1914 static void do_in_ack(void)
1915 {
1916         gintsts_data_t gintsts;
1917         hctsiz_data_t hctsiz;
1918         hcchar_data_t hcchar;
1919         haint_data_t haint;
1920         hcint_data_t hcint;
1921         host_grxsts_data_t grxsts;
1922
1923         /* Enable HAINTs */
1924         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1925
1926         /* Enable HCINTs */
1927         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1928
1929         /* Read GINTSTS */
1930         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1931         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1932
1933         /* Read HAINT */
1934         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1935         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1936
1937         /* Read HCINT */
1938         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1939         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1940
1941         /* Read HCCHAR */
1942         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1943         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1944
1945         /* Clear HCINT */
1946         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1947
1948         /* Clear HAINT */
1949         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1950
1951         /* Clear GINTSTS */
1952         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1953
1954         /* Read GINTSTS */
1955         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1956         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1957
1958         /*
1959          * Receive Control In packet
1960          */
1961
1962         /* Make sure channel is disabled */
1963         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1964         if (hcchar.b.chen) {
1965                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1966                 hcchar.b.chdis = 1;
1967                 hcchar.b.chen = 1;
1968                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1969                 //sleep(1);
1970                 mdelay(1000);
1971
1972                 /* Read GINTSTS */
1973                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1974                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1975
1976                 /* Read HAINT */
1977                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1978                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1979
1980                 /* Read HCINT */
1981                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1982                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1983
1984                 /* Read HCCHAR */
1985                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1986                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1987
1988                 /* Clear HCINT */
1989                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1990
1991                 /* Clear HAINT */
1992                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1993
1994                 /* Clear GINTSTS */
1995                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1996
1997                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1998                 //if (hcchar.b.chen) {
1999                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
2000                 //}
2001         }
2002
2003         /* Set HCTSIZ */
2004         hctsiz.d32 = 0;
2005         hctsiz.b.xfersize = 8;
2006         hctsiz.b.pktcnt = 1;
2007         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2008         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2009
2010         /* Set HCCHAR */
2011         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2012         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2013         hcchar.b.epdir = 1;
2014         hcchar.b.epnum = 0;
2015         hcchar.b.mps = 8;
2016         hcchar.b.chen = 1;
2017         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2018
2019         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2020         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2021
2022         /* Wait for receive status queue interrupt */
2023         do {
2024                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2025         } while (gintsts.b.rxstsqlvl == 0);
2026
2027         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2028
2029         /* Read RXSTS */
2030         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2031         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2032
2033         /* Clear RXSTSQLVL in GINTSTS */
2034         gintsts.d32 = 0;
2035         gintsts.b.rxstsqlvl = 1;
2036         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2037
2038         switch (grxsts.b.pktsts) {
2039         case DWC_GRXSTS_PKTSTS_IN:
2040                 /* Read the data into the host buffer */
2041                 if (grxsts.b.bcnt > 0) {
2042                         int i;
2043                         int word_count = (grxsts.b.bcnt + 3) / 4;
2044
2045                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2046
2047                         for (i = 0; i < word_count; i++) {
2048                                 (void)dwc_read_reg32(data_fifo++);
2049                         }
2050                 }
2051
2052                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2053         break;
2054
2055         default:
2056                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2057         break;
2058         }
2059
2060         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2061         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2062
2063         /* Wait for receive status queue interrupt */
2064         do {
2065                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2066         } while (gintsts.b.rxstsqlvl == 0);
2067
2068         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2069
2070         /* Read RXSTS */
2071         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2072         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2073
2074         /* Clear RXSTSQLVL in GINTSTS */
2075         gintsts.d32 = 0;
2076         gintsts.b.rxstsqlvl = 1;
2077         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2078
2079         switch (grxsts.b.pktsts) {
2080         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2081         break;
2082
2083         default:
2084                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2085         break;
2086         }
2087
2088         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2089         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2090
2091         /* Wait for host channel interrupt */
2092         do {
2093                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2094         } while (gintsts.b.hcintr == 0);
2095
2096         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2097
2098         /* Read HAINT */
2099         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2100         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2101
2102         /* Read HCINT */
2103         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2104         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2105
2106         /* Read HCCHAR */
2107         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2108         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2109
2110         /* Clear HCINT */
2111         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2112
2113         /* Clear HAINT */
2114         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2115
2116         /* Clear GINTSTS */
2117         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2118
2119         /* Read GINTSTS */
2120         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2121         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2122
2123 //      usleep(100000);
2124 //      mdelay(100);
2125         mdelay(1);
2126
2127         /*
2128          * Send handshake packet
2129          */
2130
2131         /* Read HAINT */
2132         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2133         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2134
2135         /* Read HCINT */
2136         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2137         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2138
2139         /* Read HCCHAR */
2140         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2141         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2142
2143         /* Clear HCINT */
2144         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2145
2146         /* Clear HAINT */
2147         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2148
2149         /* Clear GINTSTS */
2150         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2151
2152         /* Read GINTSTS */
2153         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2154         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2155
2156         /* Make sure channel is disabled */
2157         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2158         if (hcchar.b.chen) {
2159                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2160                 hcchar.b.chdis = 1;
2161                 hcchar.b.chen = 1;
2162                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2163                 //sleep(1);
2164                 mdelay(1000);
2165
2166                 /* Read GINTSTS */
2167                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2168                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2169
2170                 /* Read HAINT */
2171                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2172                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2173
2174                 /* Read HCINT */
2175                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2176                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2177
2178                 /* Read HCCHAR */
2179                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2180                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2181
2182                 /* Clear HCINT */
2183                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2184
2185                 /* Clear HAINT */
2186                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2187
2188                 /* Clear GINTSTS */
2189                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2190
2191                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2192                 //if (hcchar.b.chen) {
2193                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2194                 //}
2195         }
2196
2197         /* Set HCTSIZ */
2198         hctsiz.d32 = 0;
2199         hctsiz.b.xfersize = 0;
2200         hctsiz.b.pktcnt = 1;
2201         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2202         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2203
2204         /* Set HCCHAR */
2205         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2206         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2207         hcchar.b.epdir = 0;
2208         hcchar.b.epnum = 0;
2209         hcchar.b.mps = 8;
2210         hcchar.b.chen = 1;
2211         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2212
2213         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2214         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2215
2216         /* Wait for host channel interrupt */
2217         do {
2218                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2219         } while (gintsts.b.hcintr == 0);
2220
2221         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2222
2223         /* Disable HCINTs */
2224         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2225
2226         /* Disable HAINTs */
2227         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2228
2229         /* Read HAINT */
2230         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2231         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2232
2233         /* Read HCINT */
2234         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2235         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2236
2237         /* Read HCCHAR */
2238         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2239         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2240
2241         /* Clear HCINT */
2242         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2243
2244         /* Clear HAINT */
2245         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2246
2247         /* Clear GINTSTS */
2248         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2249
2250         /* Read GINTSTS */
2251         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2252         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2253 }
2254 #endif /* DWC_HS_ELECT_TST */
2255
2256 /** Handles hub class-specific requests.*/
2257 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2258                             u16 _typeReq,
2259                             u16 _wValue,
2260                             u16 _wIndex,
2261                             char *_buf,
2262                             u16 _wLength)
2263 {
2264         int retval = 0;
2265         unsigned long flags;
2266
2267         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2268         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2269         struct usb_hub_descriptor *desc;
2270         hprt0_data_t hprt0 = {.d32 = 0};
2271
2272         uint32_t port_status;
2273         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2274
2275         switch (_typeReq) {
2276         case ClearHubFeature:
2277                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2278                             "ClearHubFeature 0x%x\n", _wValue);
2279                 switch (_wValue) {
2280                 case C_HUB_LOCAL_POWER:
2281                 case C_HUB_OVER_CURRENT:
2282                         /* Nothing required here */
2283                         break;
2284                 default:
2285                         retval = -EINVAL;
2286                         DWC_ERROR ("DWC OTG HCD - "
2287                                    "ClearHubFeature request %xh unknown\n", _wValue);
2288                 }
2289                 break;
2290         case ClearPortFeature:
2291                 if (!_wIndex || _wIndex > 1)
2292                         goto error;
2293
2294                 switch (_wValue) {
2295                 case USB_PORT_FEAT_ENABLE:
2296                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2297                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2298                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2299                         hprt0.b.prtena = 1;
2300                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2301                         break;
2302                 case USB_PORT_FEAT_SUSPEND:
2303                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2304                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2305                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2306                         hprt0.b.prtres = 1;
2307                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2308                         /* Clear Resume bit */
2309                         mdelay (100);
2310                         hprt0.b.prtres = 0;
2311                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2312                         break;
2313                 case USB_PORT_FEAT_POWER:
2314                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2315                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2316                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2317                         hprt0.b.prtpwr = 0;
2318                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2319                         break;
2320                 case USB_PORT_FEAT_INDICATOR:
2321                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2322                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2323                         /* Port inidicator not supported */
2324                         break;
2325                 case USB_PORT_FEAT_C_CONNECTION:
2326                         /* Clears drivers internal connect status change
2327                          * flag */
2328                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2329                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2330                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2331                         break;
2332                 case USB_PORT_FEAT_C_RESET:
2333                         /* Clears the driver's internal Port Reset Change
2334                          * flag */
2335                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2336                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2337                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2338                         break;
2339                 case USB_PORT_FEAT_C_ENABLE:
2340                         /* Clears the driver's internal Port
2341                          * Enable/Disable Change flag */
2342                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2343                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2344                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2345                         break;
2346                 case USB_PORT_FEAT_C_SUSPEND:
2347                         /* Clears the driver's internal Port Suspend
2348                          * Change flag, which is set when resume signaling on
2349                          * the host port is complete */
2350                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2351                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2352                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2353                         break;
2354                 case USB_PORT_FEAT_C_OVER_CURRENT:
2355                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2356                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2357                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2358                         break;
2359                 default:
2360                         retval = -EINVAL;
2361                         DWC_ERROR ("DWC OTG HCD - "
2362                                    "ClearPortFeature request %xh "
2363                                    "unknown or unsupported\n", _wValue);
2364                 }
2365                 break;
2366         case GetHubDescriptor:
2367                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2368                              "GetHubDescriptor\n");
2369                 desc = (struct usb_hub_descriptor *)_buf;
2370                 desc->bDescLength = 9;
2371                 desc->bDescriptorType = 0x29;
2372                 desc->bNbrPorts = 1;
2373                 desc->wHubCharacteristics = 0x08;
2374                 desc->bPwrOn2PwrGood = 1;
2375                 desc->bHubContrCurrent = 0;
2376                 desc->bitmap[0] = 0;
2377                 desc->bitmap[1] = 0xff;
2378                 break;
2379         case GetHubStatus:
2380                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2381                              "GetHubStatus\n");
2382                 memset (_buf, 0, 4);
2383                 break;
2384         case GetPortStatus:
2385                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2386                              "GetPortStatus\n");
2387
2388                 if (!_wIndex || _wIndex > 1)
2389                         goto error;
2390
2391                 port_status = 0;
2392
2393                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2394                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2395
2396                 if (dwc_otg_hcd->flags.b.port_enable_change)
2397                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2398
2399                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2400                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2401
2402                 if (dwc_otg_hcd->flags.b.port_reset_change)
2403                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2404
2405                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2406                         DWC_ERROR("Device Not Supported\n");
2407                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2408                 }
2409
2410                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2411                         /*
2412                          * The port is disconnected, which means the core is
2413                          * either in device mode or it soon will be. Just
2414                          * return 0's for the remainder of the port status
2415                          * since the port register can't be read if the core
2416                          * is in device mode.
2417                          */
2418                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2419                         break;
2420                 }
2421
2422                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2423                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2424
2425                 if (hprt0.b.prtconnsts)
2426                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2427
2428                 if (hprt0.b.prtena)
2429                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2430
2431                 if (hprt0.b.prtsusp)
2432                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2433
2434                 if (hprt0.b.prtovrcurract)
2435                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2436
2437                 if (hprt0.b.prtrst)
2438                         port_status |= (1 << USB_PORT_FEAT_RESET);
2439
2440                 if (hprt0.b.prtpwr)
2441                         port_status |= (1 << USB_PORT_FEAT_POWER);
2442
2443                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2444                         port_status |= USB_PORT_STAT_HIGH_SPEED;
2445
2446                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2447                         port_status |= USB_PORT_STAT_LOW_SPEED;
2448
2449                 if (hprt0.b.prttstctl)
2450                         port_status |= (1 << USB_PORT_FEAT_TEST);
2451
2452                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2453
2454                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2455
2456                 break;
2457         case SetHubFeature:
2458                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2459                              "SetHubFeature\n");
2460                 /* No HUB features supported */
2461                 break;
2462         case SetPortFeature:
2463                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2464                         goto error;
2465
2466                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2467                         /*
2468                          * The port is disconnected, which means the core is
2469                          * either in device mode or it soon will be. Just
2470                          * return without doing anything since the port
2471                          * register can't be written if the core is in device
2472                          * mode.
2473                          */
2474                         break;
2475                 }
2476
2477                 switch (_wValue) {
2478                 case USB_PORT_FEAT_SUSPEND:
2479                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2480                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2481                         if (_hcd->self.otg_port == _wIndex &&
2482                             _hcd->self.b_hnp_enable) {
2483                                 gotgctl_data_t  gotgctl = {.d32=0};
2484                                 gotgctl.b.hstsethnpen = 1;
2485                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2486                                                   0, gotgctl.d32);
2487                                 core_if->op_state = A_SUSPEND;
2488                         }
2489                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2490                         hprt0.b.prtsusp = 1;
2491                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2492                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2493                         /* Suspend the Phy Clock */
2494                         {
2495                                 pcgcctl_data_t pcgcctl = {.d32=0};
2496                                 pcgcctl.b.stoppclk = 1;
2497                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2498                         }
2499
2500                         /* For HNP the bus must be suspended for at least 200ms.*/
2501                         if (_hcd->self.b_hnp_enable) {
2502                                 mdelay(200);
2503                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2504                         }
2505                         break;
2506                 case USB_PORT_FEAT_POWER:
2507                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2508                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2509                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2510                         hprt0.b.prtpwr = 1;
2511                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2512                         break;
2513                 case USB_PORT_FEAT_RESET:
2514                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2515                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2516                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2517                         /* When B-Host the Port reset bit is set in
2518                          * the Start HCD Callback function, so that
2519                          * the reset is started within 1ms of the HNP
2520                          * success interrupt. */
2521                         if (!_hcd->self.is_b_host) {
2522                                 hprt0.b.prtrst = 1;
2523                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2524                         }
2525             spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2526                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2527                         // kever @rk 20110712
2528                         // can not use mdelay(60) while irq disable
2529                         //MDELAY (60);
2530                         msleep(60);
2531             spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2532                         hprt0.b.prtrst = 0;
2533                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2534                         break;
2535
2536 #ifdef DWC_HS_ELECT_TST
2537                 case USB_PORT_FEAT_TEST:
2538                 {
2539                         uint32_t t;
2540                         gintmsk_data_t gintmsk;
2541
2542                         t = (_wIndex >> 8); /* MSB wIndex USB */
2543                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2544                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2545                         warn("USB_PORT_FEAT_TEST %d\n", t);
2546                         if (t < 6) {
2547                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2548                                 hprt0.b.prttstctl = t;
2549                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2550                         } else {
2551                                 /* Setup global vars with reg addresses (quick and
2552                                  * dirty hack, should be cleaned up)
2553                                  */
2554                                 global_regs = core_if->core_global_regs;
2555                                 hc_global_regs = core_if->host_if->host_global_regs;
2556                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2557                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2558
2559                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2560                                         /* Save current interrupt mask */
2561                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2562
2563                                         /* Disable all interrupts while we muck with
2564                                          * the hardware directly
2565                                          */
2566                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2567
2568                                         /* 15 second delay per the test spec */
2569                                         mdelay(15000);
2570
2571                                         /* Drive suspend on the root port */
2572                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2573                                         hprt0.b.prtsusp = 1;
2574                                         hprt0.b.prtres = 0;
2575                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2576
2577                                         /* 15 second delay per the test spec */
2578                                         mdelay(15000);
2579
2580                                         /* Drive resume on the root port */
2581                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2582                                         hprt0.b.prtsusp = 0;
2583                                         hprt0.b.prtres = 1;
2584                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2585                                         mdelay(100);
2586
2587                                         /* Clear the resume bit */
2588                                         hprt0.b.prtres = 0;
2589                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2590
2591                                         /* Restore interrupts */
2592                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2593                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2594                                         /* Save current interrupt mask */
2595                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2596
2597                                         /* Disable all interrupts while we muck with
2598                                          * the hardware directly
2599                                          */
2600                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2601
2602                                         /* 15 second delay per the test spec */
2603                                         mdelay(15000);
2604
2605                                         /* Send the Setup packet */
2606                                         do_setup();
2607
2608                                         /* 15 second delay so nothing else happens for awhile */
2609                                         mdelay(15000);
2610
2611                                         /* Restore interrupts */
2612                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2613                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2614                                         /* Save current interrupt mask */
2615                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2616
2617                                         /* Disable all interrupts while we muck with
2618                                          * the hardware directly
2619                                          */
2620                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2621
2622                                         /* Send the Setup packet */
2623                                         do_setup();
2624
2625                                         /* 15 second delay so nothing else happens for awhile */
2626                                         mdelay(15000);
2627
2628                                         /* Send the In and Ack packets */
2629                                         do_in_ack();
2630
2631                                         /* 15 second delay so nothing else happens for awhile */
2632                                         mdelay(15000);
2633
2634                                         /* Restore interrupts */
2635                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2636                                 }
2637                         }
2638                         break;
2639                 }
2640 #endif /* DWC_HS_ELECT_TST */
2641
2642                 case USB_PORT_FEAT_INDICATOR:
2643                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2644                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2645                         /* Not supported */
2646                         break;
2647                 default:
2648                         retval = -EINVAL;
2649                         DWC_ERROR ("DWC OTG HCD - "
2650                                    "SetPortFeature request %xh "
2651                                    "unknown or unsupported\n", _wValue);
2652                         break;
2653                 }
2654                 break;
2655         default:
2656         error:
2657                 retval = -EINVAL;
2658                 DWC_WARN ("DWC OTG HCD - "
2659                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2660                           _typeReq, _wIndex, _wValue);
2661                 break;
2662         }
2663
2664         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2665         return retval;
2666 }
2667
2668
2669 /**
2670  * Assigns transactions from a QTD to a free host channel and initializes the
2671  * host channel to perform the transactions. The host channel is removed from
2672  * the free list.
2673  *
2674  * @param _hcd The HCD state structure.
2675  * @param _qh Transactions from the first QTD for this QH are selected and
2676  * assigned to a free host channel.
2677  */
2678 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2679 {
2680         dwc_hc_t        *hc;
2681         dwc_otg_qtd_t   *qtd;
2682         struct urb      *urb;
2683
2684         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2685         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2686
2687         /* Remove the host channel from the free list. */
2688         list_del_init(&hc->hc_list_entry);
2689
2690         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2691         urb = qtd->urb;
2692         _qh->channel = hc;
2693         _qh->qtd_in_process = qtd;
2694
2695         /*
2696          * Use usb_pipedevice to determine device address. This address is
2697          * 0 before the SET_ADDRESS command and the correct address afterward.
2698          */
2699         hc->dev_addr = usb_pipedevice(urb->pipe);
2700         hc->ep_num = usb_pipeendpoint(urb->pipe);
2701
2702         if (urb->dev->speed == USB_SPEED_LOW) {
2703                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2704                 /*
2705                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2706                  * device connected.
2707                  */
2708         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2709         } else if (urb->dev->speed == USB_SPEED_FULL) {
2710                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2711                 /*
2712                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2713                  * device connected. warning: only support 1 device at root hub.
2714                  */
2715         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2716         } else {
2717                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2718         }
2719
2720         hc->max_packet = dwc_max_packet(_qh->maxp);
2721
2722         hc->xfer_started = 0;
2723         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2724         hc->error_state = (qtd->error_count > 0);
2725         hc->halt_on_queue = 0;
2726         hc->halt_pending = 0;
2727         hc->requests = 0;
2728
2729         /*
2730          * The following values may be modified in the transfer type section
2731          * below. The xfer_len value may be reduced when the transfer is
2732          * started to accommodate the max widths of the XferSize and PktCnt
2733          * fields in the HCTSIZn register.
2734          */
2735         hc->do_ping = _qh->ping_state;
2736         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2737         hc->data_pid_start = _qh->data_toggle;
2738         hc->multi_count = 1;
2739
2740         if (_hcd->core_if->dma_enable) {
2741                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2742         } else {
2743                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2744         }
2745         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2746         hc->xfer_count = 0;
2747
2748         /*
2749          * Set the split attributes
2750          */
2751         hc->do_split = 0;
2752         if (_qh->do_split) {
2753                 hc->do_split = 1;
2754                 hc->xact_pos = qtd->isoc_split_pos;
2755                 hc->complete_split = qtd->complete_split;
2756                 hc->hub_addr = urb->dev->tt->hub->devnum;
2757                 hc->port_addr = urb->dev->ttport;
2758         }
2759
2760         switch (usb_pipetype(urb->pipe)) {
2761         case PIPE_CONTROL:
2762                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2763                 switch (qtd->control_phase) {
2764                 case DWC_OTG_CONTROL_SETUP:
2765                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2766                         hc->do_ping = 0;
2767                         hc->ep_is_in = 0;
2768                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2769                         if (_hcd->core_if->dma_enable) {
2770                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2771                         } else {
2772                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2773                         }
2774                         hc->xfer_len = 8;
2775                         break;
2776                 case DWC_OTG_CONTROL_DATA:
2777                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2778                         hc->data_pid_start = qtd->data_toggle;
2779                         break;
2780                 case DWC_OTG_CONTROL_STATUS:
2781                         /*
2782                          * Direction is opposite of data direction or IN if no
2783                          * data.
2784                          */
2785                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2786                         if (urb->transfer_buffer_length == 0) {
2787                                 hc->ep_is_in = 1;
2788                         } else {
2789                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2790                         }
2791                         if (hc->ep_is_in) {
2792                                 hc->do_ping = 0;
2793                         }
2794                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2795                         hc->xfer_len = 0;
2796                         if (_hcd->core_if->dma_enable) {
2797                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2798                         } else {
2799                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2800                         }
2801                         break;
2802                 }
2803                 break;
2804         case PIPE_BULK:
2805                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2806                 break;
2807         case PIPE_INTERRUPT:
2808                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2809                 break;
2810         case PIPE_ISOCHRONOUS:
2811                 {
2812                         struct usb_iso_packet_descriptor *frame_desc;
2813                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2814                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2815                         if (_hcd->core_if->dma_enable) {
2816                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2817                         } else {
2818                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2819                         }
2820                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2821                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2822
2823                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2824                                 if (hc->xfer_len <= 188) {
2825                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2826                                 }
2827                                 else {
2828                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2829                                 }
2830                         }
2831                 }
2832                 break;
2833         }
2834
2835         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2836             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2837                 /*
2838                  * This value may be modified when the transfer is started to
2839                  * reflect the actual transfer length.
2840                  */
2841                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2842         }
2843
2844         dwc_otg_hc_init(_hcd->core_if, hc);
2845         hc->qh = _qh;
2846 }
2847
2848 /**
2849  * This function selects transactions from the HCD transfer schedule and
2850  * assigns them to available host channels. It is called from HCD interrupt
2851  * handler functions.
2852  *
2853  * @param _hcd The HCD state structure.
2854  *
2855  * @return The types of new transactions that were assigned to host channels.
2856  */
2857 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2858 {
2859         struct list_head                *qh_ptr;
2860         dwc_otg_qh_t                    *qh;
2861         int                             num_channels;
2862         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2863
2864 #ifdef DEBUG_SOF
2865         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2866 #endif
2867
2868         /* Process entries in the periodic ready list. */
2869         qh_ptr = _hcd->periodic_sched_ready.next;
2870         while (qh_ptr != &_hcd->periodic_sched_ready &&
2871                !list_empty(&_hcd->free_hc_list)) {
2872
2873                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2874                 assign_and_init_hc(_hcd, qh);
2875
2876                 /*
2877                  * Move the QH from the periodic ready schedule to the
2878                  * periodic assigned schedule.
2879                  */
2880                 qh_ptr = qh_ptr->next;
2881                 list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2882
2883                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2884         }
2885
2886         /*
2887          * Process entries in the inactive portion of the non-periodic
2888          * schedule. Some free host channels may not be used if they are
2889          * reserved for periodic transfers.
2890          */
2891         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2892         num_channels = _hcd->core_if->core_params->host_channels;
2893         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2894                 /*yk@rk 20100714
2895                (_hcd->non_periodic_channels <
2896                 num_channels - _hcd->periodic_channels) &&
2897                 */
2898                !list_empty(&_hcd->free_hc_list)) {
2899
2900                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2901                 assign_and_init_hc(_hcd, qh);
2902
2903                 /*
2904                  * Move the QH from the non-periodic inactive schedule to the
2905                  * non-periodic active schedule.
2906                  */
2907                 qh_ptr = qh_ptr->next;
2908                 list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2909
2910                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2911                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2912                 } else {
2913                         ret_val = DWC_OTG_TRANSACTION_ALL;
2914                 }
2915
2916                 _hcd->non_periodic_channels++;
2917         }
2918
2919         return ret_val;
2920 }
2921
2922 /**
2923  * Attempts to queue a single transaction request for a host channel
2924  * associated with either a periodic or non-periodic transfer. This function
2925  * assumes that there is space available in the appropriate request queue. For
2926  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2927  * is available in the appropriate Tx FIFO.
2928  *
2929  * @param _hcd The HCD state structure.
2930  * @param _hc Host channel descriptor associated with either a periodic or
2931  * non-periodic transfer.
2932  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2933  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2934  * transfers.
2935  *
2936  * @return 1 if a request is queued and more requests may be needed to
2937  * complete the transfer, 0 if no more requests are required for this
2938  * transfer, -1 if there is insufficient space in the Tx FIFO.
2939  */
2940 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2941                              dwc_hc_t *_hc,
2942                              uint16_t _fifo_dwords_avail)
2943 {
2944         int retval;
2945
2946         if (_hcd->core_if->dma_enable) {
2947                 if (!_hc->xfer_started) {
2948                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2949                         _hc->qh->ping_state = 0;
2950                 }
2951                 retval = 0;
2952         } else  if (_hc->halt_pending) {
2953                 /* Don't queue a request if the channel has been halted. */
2954                 retval = 0;
2955         } else if (_hc->halt_on_queue) {
2956                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
2957                 retval = 0;
2958         } else if (_hc->do_ping) {
2959                 if (!_hc->xfer_started) {
2960                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2961                 }
2962                 retval = 0;
2963         } else if (!_hc->ep_is_in ||
2964                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2965                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
2966                         if (!_hc->xfer_started) {
2967                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2968                                 retval = 1;
2969                         } else {
2970                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2971                         }
2972                 } else {
2973                         retval = -1;
2974                 }
2975         } else {
2976                 if (!_hc->xfer_started) {
2977                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2978                         retval = 1;
2979                 } else {
2980                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2981                 }
2982         }
2983
2984         return retval;
2985 }
2986
2987 /**
2988  * Processes active non-periodic channels and queues transactions for these
2989  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2990  * FIFO Empty interrupt is enabled if there are more transactions to queue as
2991  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2992  * FIFO Empty interrupt is disabled.
2993  */
2994 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
2995 {
2996         gnptxsts_data_t         tx_status;
2997         struct list_head        *orig_qh_ptr;
2998         dwc_otg_qh_t            *qh;
2999         int                     status;
3000         int                     no_queue_space = 0;
3001         int                     no_fifo_space = 0;
3002         int                     more_to_do = 0;
3003
3004         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
3005
3006         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
3007 #ifdef DEBUG
3008         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3009         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3010                     tx_status.b.nptxqspcavail);
3011         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
3012                     tx_status.b.nptxfspcavail);
3013 #endif
3014         /*
3015          * Keep track of the starting point. Skip over the start-of-list
3016          * entry.
3017          */
3018         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3019                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3020         }
3021         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3022
3023         /*
3024          * Process once through the active list or until no more space is
3025          * available in the request queue or the Tx FIFO.
3026          */
3027         do {
3028                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3029                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3030                         no_queue_space = 1;
3031                         break;
3032                 }
3033
3034                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3035                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3036
3037                 if (status > 0) {
3038                         more_to_do = 1;
3039                 } else if (status < 0) {
3040                         no_fifo_space = 1;
3041                         break;
3042                 }
3043
3044                 /* Advance to next QH, skipping start-of-list entry. */
3045                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3046                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3047                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3048                 }
3049
3050         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3051
3052         if (!_hcd->core_if->dma_enable) {
3053                 gintmsk_data_t intr_mask = {.d32 = 0};
3054                 intr_mask.b.nptxfempty = 1;
3055
3056 #ifdef DEBUG
3057                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3058                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3059                             tx_status.b.nptxqspcavail);
3060                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3061                             tx_status.b.nptxfspcavail);
3062 #endif
3063                 if (more_to_do || no_queue_space || no_fifo_space) {
3064                         /*
3065                          * May need to queue more transactions as the request
3066                          * queue or Tx FIFO empties. Enable the non-periodic
3067                          * Tx FIFO empty interrupt. (Always use the half-empty
3068                          * level to ensure that new requests are loaded as
3069                          * soon as possible.)
3070                          */
3071                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3072                 } else {
3073                         /*
3074                          * Disable the Tx FIFO empty interrupt since there are
3075                          * no more transactions that need to be queued right
3076                          * now. This function is called from interrupt
3077                          * handlers to queue more transactions as transfer
3078                          * states change.
3079                          */
3080                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3081                 }
3082         }
3083 }
3084
3085 /**
3086  * Processes periodic channels for the next frame and queues transactions for
3087  * these channels to the DWC_otg controller. After queueing transactions, the
3088  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3089  * to queue as Periodic Tx FIFO or request queue space becomes available.
3090  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3091  */
3092 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3093 {
3094         hptxsts_data_t          tx_status;
3095         struct list_head        *qh_ptr;
3096         dwc_otg_qh_t            *qh;
3097         int                     status;
3098         int                     no_queue_space = 0;
3099         int                     no_fifo_space = 0;
3100
3101         dwc_otg_host_global_regs_t *host_regs;
3102         host_regs = _hcd->core_if->host_if->host_global_regs;
3103
3104         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3105 #ifdef DEBUG
3106         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3107         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3108                     tx_status.b.ptxqspcavail);
3109         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3110                     tx_status.b.ptxfspcavail);
3111 #endif
3112
3113         qh_ptr = _hcd->periodic_sched_assigned.next;
3114         while (qh_ptr != &_hcd->periodic_sched_assigned) {
3115                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3116                 if (tx_status.b.ptxqspcavail == 0) {
3117                         no_queue_space = 1;
3118                         break;
3119                 }
3120
3121                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3122
3123                 /*
3124                  * Set a flag if we're queuing high-bandwidth in slave mode.
3125                  * The flag prevents any halts to get into the request queue in
3126                  * the middle of multiple high-bandwidth packets getting queued.
3127                  */
3128                 if ((!_hcd->core_if->dma_enable) &&
3129                     (qh->channel->multi_count > 1))
3130                 {
3131                         _hcd->core_if->queuing_high_bandwidth = 1;
3132                 }
3133
3134                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3135                 if (status < 0) {
3136                         no_fifo_space = 1;
3137                         break;
3138                 }
3139
3140                 /*
3141                  * In Slave mode, stay on the current transfer until there is
3142                  * nothing more to do or the high-bandwidth request count is
3143                  * reached. In DMA mode, only need to queue one request. The
3144                  * controller automatically handles multiple packets for
3145                  * high-bandwidth transfers.
3146                  */
3147                 if (_hcd->core_if->dma_enable ||
3148                     (status == 0 ||
3149                      qh->channel->requests == qh->channel->multi_count)) {
3150                         qh_ptr = qh_ptr->next;
3151                         /*
3152                          * Move the QH from the periodic assigned schedule to
3153                          * the periodic queued schedule.
3154                          */
3155                         list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3156
3157                         /* done queuing high bandwidth */
3158                         _hcd->core_if->queuing_high_bandwidth = 0;
3159                 }
3160         }
3161
3162         if (!_hcd->core_if->dma_enable) {
3163                 dwc_otg_core_global_regs_t *global_regs;
3164                 gintmsk_data_t intr_mask = {.d32 = 0};
3165
3166                 global_regs = _hcd->core_if->core_global_regs;
3167                 intr_mask.b.ptxfempty = 1;
3168 #ifdef DEBUG
3169                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3170                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3171                             tx_status.b.ptxqspcavail);
3172                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3173                             tx_status.b.ptxfspcavail);
3174 #endif
3175                 if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
3176                     no_queue_space || no_fifo_space) {
3177                         /*
3178                          * May need to queue more transactions as the request
3179                          * queue or Tx FIFO empties. Enable the periodic Tx
3180                          * FIFO empty interrupt. (Always use the half-empty
3181                          * level to ensure that new requests are loaded as
3182                          * soon as possible.)
3183                          */
3184                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3185                 } else {
3186                         /*
3187                          * Disable the Tx FIFO empty interrupt since there are
3188                          * no more transactions that need to be queued right
3189                          * now. This function is called from interrupt
3190                          * handlers to queue more transactions as transfer
3191                          * states change.
3192                          */
3193                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3194                 }
3195         }
3196 }
3197
3198 /**
3199  * This function processes the currently active host channels and queues
3200  * transactions for these channels to the DWC_otg controller. It is called
3201  * from HCD interrupt handler functions.
3202  *
3203  * @param _hcd The HCD state structure.
3204  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3205  * periodic, or both).
3206  */
3207 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3208                                     dwc_otg_transaction_type_e _tr_type)
3209 {
3210 #ifdef DEBUG_SOF
3211         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3212 #endif
3213         /* Process host channels associated with periodic transfers. */
3214         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3215              _tr_type == DWC_OTG_TRANSACTION_ALL) &&
3216             !list_empty(&_hcd->periodic_sched_assigned)) {
3217
3218                 process_periodic_channels(_hcd);
3219         }
3220
3221         /* Process host channels associated with non-periodic transfers. */
3222         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3223              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3224                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3225                         process_non_periodic_channels(_hcd);
3226                 } else {
3227                         /*
3228                          * Ensure NP Tx FIFO empty interrupt is disabled when
3229                          * there are no non-periodic transfers to process.
3230                          */
3231                         gintmsk_data_t gintmsk = {.d32 = 0};
3232                         gintmsk.b.nptxfempty = 1;
3233                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3234                                          gintmsk.d32, 0);
3235                 }
3236         }
3237 }
3238
3239 /**
3240  * Sets the final status of an URB and returns it to the device driver. Any
3241  * required cleanup of the URB is performed.
3242  */
3243 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3244                               int _status)
3245 __releases(_hcd->lock)
3246 __acquires(_hcd->lock)
3247 {
3248
3249 #ifdef DEBUG
3250         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3251                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3252                           __func__, _urb, usb_pipedevice(_urb->pipe),
3253                           usb_pipeendpoint(_urb->pipe),
3254                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3255                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3256                         int i;
3257                         for (i = 0; i < _urb->number_of_packets; i++) {
3258                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3259                                           i, _urb->iso_frame_desc[i].status);
3260                         }
3261                 }
3262         }
3263 #endif
3264
3265
3266         _urb->hcpriv = NULL;
3267         //usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
3268         spin_unlock(&_hcd->lock);
3269         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3270         spin_lock(&_hcd->lock);
3271 }
3272
3273 void dwc_otg_clear_halt(struct urb *_urb)
3274 {
3275         struct dwc_otg_qh *_qh;
3276         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3277         if((ep)&&(ep->hcpriv))
3278         {
3279                 _qh =  (dwc_otg_qh_t *) ep->hcpriv;
3280                 _qh->data_toggle = 0;
3281         }
3282 }
3283 /*
3284  * Returns the Queue Head for an URB.
3285  */
3286 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3287 {
3288         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3289         return (dwc_otg_qh_t *) ep->hcpriv;
3290 }
3291
3292 #ifdef DEBUG
3293 void dwc_print_setup_data (uint8_t *setup)
3294 {
3295         int i;
3296         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3297                 DWC_PRINT("Setup Data = MSB ");
3298                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3299                 DWC_PRINT("\n");
3300                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3301                 DWC_PRINT("  bmRequestType Type = ");
3302                 switch ((setup[0]&0x60) >> 5) {
3303                 case 0: DWC_PRINT("Standard\n"); break;
3304                 case 1: DWC_PRINT("Class\n"); break;
3305                 case 2: DWC_PRINT("Vendor\n"); break;
3306                 case 3: DWC_PRINT("Reserved\n"); break;
3307                 }
3308                 DWC_PRINT("  bmRequestType Recipient = ");
3309                 switch (setup[0]&0x1f) {
3310                 case 0: DWC_PRINT("Device\n"); break;
3311                 case 1: DWC_PRINT("Interface\n"); break;
3312                 case 2: DWC_PRINT("Endpoint\n"); break;
3313                 case 3: DWC_PRINT("Other\n"); break;
3314                 default: DWC_PRINT("Reserved\n"); break;
3315                 }
3316                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3317                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3318                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3319                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3320         }
3321 }
3322 #endif
3323
3324 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3325 #if 0
3326         DWC_PRINT("Frame remaining at SOF:\n");
3327         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3328                   _hcd->frrem_samples, _hcd->frrem_accum,
3329                   (_hcd->frrem_samples > 0) ?
3330                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3331
3332         DWC_PRINT("\n");
3333         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3334         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3335                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3336                   (_hcd->core_if->hfnum_7_samples > 0) ?
3337                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3338         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3339         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3340                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3341                   (_hcd->core_if->hfnum_0_samples > 0) ?
3342                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3343         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3344         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3345                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3346                   (_hcd->core_if->hfnum_other_samples > 0) ?
3347                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3348
3349         DWC_PRINT("\n");
3350         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3351         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3352                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3353                   (_hcd->hfnum_7_samples_a > 0) ?
3354                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3355         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3356         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3357                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3358                   (_hcd->hfnum_0_samples_a > 0) ?
3359                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3360         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3361         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3362                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3363                   (_hcd->hfnum_other_samples_a > 0) ?
3364                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3365
3366         DWC_PRINT("\n");
3367         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3368         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3369                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3370                   (_hcd->hfnum_7_samples_b > 0) ?
3371                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3372         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3373         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3374                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3375                   (_hcd->hfnum_0_samples_b > 0) ?
3376                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3377         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3378         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3379                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3380                   (_hcd->hfnum_other_samples_b > 0) ?
3381                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3382 #endif
3383 }
3384
3385 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3386 {
3387 #ifdef DEBUG
3388         int num_channels;
3389         int i;
3390         gnptxsts_data_t np_tx_status;
3391         hptxsts_data_t p_tx_status;
3392
3393         num_channels = _hcd->core_if->core_params->host_channels;
3394         DWC_PRINT("\n");
3395         DWC_PRINT("************************************************************\n");
3396         DWC_PRINT("HCD State:\n");
3397         DWC_PRINT("  Num channels: %d\n", num_channels);
3398         for (i = 0; i < num_channels; i++) {
3399                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3400                 DWC_PRINT("  Channel %d:\n", i);
3401                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3402                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3403                 DWC_PRINT("    speed: %d\n", hc->speed);
3404                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3405                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3406                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3407                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3408                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3409                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3410                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3411                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3412                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3413                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3414                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3415                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3416                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3417                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3418                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3419                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3420                 DWC_PRINT("    requests: %d\n", hc->requests);
3421                 DWC_PRINT("    qh: %p\n", hc->qh);
3422                 if (hc->xfer_started) {
3423                         hfnum_data_t hfnum;
3424                         hcchar_data_t hcchar;
3425                         hctsiz_data_t hctsiz;
3426                         hcint_data_t hcint;
3427                         hcintmsk_data_t hcintmsk;
3428                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3429                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3430                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3431                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3432                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3433                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3434                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3435                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3436                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3437                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3438                 }
3439                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3440                         dwc_otg_qtd_t *qtd;
3441                         struct urb *urb;
3442                         qtd = hc->qh->qtd_in_process;
3443                         urb = qtd->urb;
3444                         DWC_PRINT("    URB Info:\n");
3445                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3446                         if (urb != NULL) {
3447                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3448                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3449                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3450                                 DWC_PRINT("      Max packet size: %d\n",
3451                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3452                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3453                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3454                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3455                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3456                         }
3457                 }
3458         }
3459         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3460         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3461         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3462         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3463         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3464         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3465         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3466         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3467         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3468         dwc_otg_hcd_dump_frrem(_hcd);
3469         dwc_otg_dump_global_registers(_hcd->core_if);
3470         dwc_otg_dump_host_registers(_hcd->core_if);
3471         DWC_PRINT("************************************************************\n");
3472         DWC_PRINT("\n");
3473 #endif
3474 }
3475 #endif /* DWC_DEVICE_ONLY */