drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/device.h>
  46 #include <linux/errno.h>
  47 #include <linux/list.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/string.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/irq.h>
  52 #include <linux/platform_device.h>
  53
  54 #include "dwc_otg_driver.h"
  55 #include "dwc_otg_hcd.h"
  56 #include "dwc_otg_regs.h"
  57
  58 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  59 {
  60 #if 1
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65     //dwc_debug(1);
  66
  67     if(core_if->op_state == B_PERIPHERAL)
  68     {
  69         DWC_PRINT("%s, usb device mode\n", __func__);
  70         return 0;
  71     }
  72     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  73     DWC_PRINT("%s, HPRT0:0x%x\n",__func__,hprt0.d32);
  74     //partial power-down
  75     if(!hprt0.b.prtsusp)
  76     {
  77         //hprt0.d32 = 0;
  78         hprt0.b.prtsusp = 1;
  79         hprt0.b.prtena = 0;
  80         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  81     }
  82     udelay(10);
  83     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  84     DWC_PRINT("%s, HPRT0:0x%x\n",__func__,hprt0.d32);
  85     if(!hprt0.b.prtsusp)
  86     {
  87         //hprt0.d32 = 0;
  88         hprt0.b.prtsusp = 1;
  89         hprt0.b.prtena = 0;
  90         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  91     }
  92     mdelay(5);
  93 #if 1
  94     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  95     pcgcctl.b.pwrclmp = 1;//power clamp
  96     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  97     udelay(1);
  98     //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
  99     pcgcctl.b.stoppclk = 1;//stop phy clk
 100     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 101 #endif
 102 #endif
 103     //power off
 104     return 0;
 105 }
 106
 107 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 108 {
 109 #if 1
 110     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 111     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 112     hprt0_data_t hprt0;
 113     pcgcctl_data_t pcgcctl;
 114     gintmsk_data_t gintmsk;
 115
 116     if(core_if->op_state == B_PERIPHERAL)
 117     {
 118         DWC_PRINT("%s, usb device mode\n", __func__);
 119         return 0;
 120     }
 121 #if 1
 122     //partial power-down
 123     //power on
 124     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 125     pcgcctl.b.stoppclk = 0;//stop phy clk
 126     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 127     udelay(1);
 128     pcgcctl.b.pwrclmp = 0;//power clamp
 129     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 130     udelay(2);
 131 #endif
 132     //dwc_debug(3);
 133     //dwc_debug(1);
 134     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 135     gintmsk.b.portintr = 0;
 136     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 137
 138     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 139     DWC_PRINT("%s, HPRT0:0x%x\n",__func__,hprt0.d32);
 140     hprt0.b.prtpwr = 1;
 141     hprt0.b.prtres = 1;
 142     hprt0.b.prtena = 0;
 143     dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 144     mdelay(20);
 145     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 146     DWC_PRINT("%s, HPRT0:0x%x\n",__func__,hprt0.d32);
 147     //hprt0.d32 = 0;
 148     hprt0.b.prtpwr = 1;
 149     hprt0.b.prtres = 0;
 150     hprt0.b.prtena = 0;
 151     dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 152     hprt0.d32 = 0;
 153     hprt0.b.prtpwr = 1;
 154     hprt0.b.prtena = 0;
 155     hprt0.b.prtconndet = 1;
 156     dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 157
 158     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 159     DWC_PRINT("%s, HPRT0:0x%x\n",__func__,hprt0.d32);
 160
 161     gintmsk.b.portintr = 1;
 162     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 163     mdelay(10);
 164 #endif
 165         return 0;
 166 }
 167
 168 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 169
 170 static const struct hc_driver dwc_otg_hc_driver = {
 171
 172         .description =          dwc_otg_hcd_name,
 173         .product_desc =         "DWC OTG Controller",
 174         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 175
 176         .irq =                  dwc_otg_hcd_irq,
 177
 178         .flags =                HCD_MEMORY | HCD_USB2,
 179
 180         //.reset =
 181         .start =                dwc_otg_hcd_start,
 182         //.suspend =
 183         //.resume =
 184
 185         /* yk@rk 20100625
 186          * core/hcd.c call hcd->driver->bus_suspend
 187          * otherwise system can not be suspended
 188          */
 189 #ifdef CONFIG_PM
 190         .bus_suspend =          dwc_otg_hcd_suspend,
 191         .bus_resume =           dwc_otg_hcd_resume,
 192 #endif
 193         .stop =                 dwc_otg_hcd_stop,
 194
 195         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 196         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 197         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 198
 199         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 200
 201         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 202         .hub_control =          dwc_otg_hcd_hub_control,
 203         //.hub_suspend =
 204         //.hub_resume =
 205 };
 206
 207 #ifdef CONFIG_USB11_HOST
 208 static const struct hc_driver host11_hc_driver = {
 209
 210         .description =          "host11_hcd",
 211         .product_desc =         "DWC OTG Controller",
 212         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 213
 214         .irq =                  dwc_otg_hcd_irq,
 215
 216         .flags =                HCD_MEMORY | HCD_USB2,
 217
 218         //.reset =
 219         .start =                dwc_otg_hcd_start,
 220         //.suspend =
 221         //.resume =
 222
 223         /* yk@rk 20100625
 224          * core/hcd.c call hcd->driver->bus_suspend
 225          * otherwise system can not be suspended
 226          */
 227 #ifdef CONFIG_PM
 228         .bus_suspend =          dwc_otg_hcd_suspend,
 229         .bus_resume =           dwc_otg_hcd_resume,
 230 #endif
 231         .stop =                 dwc_otg_hcd_stop,
 232
 233         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 234         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 235         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 236
 237         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 238
 239         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 240         .hub_control =          dwc_otg_hcd_hub_control,
 241         //.hub_suspend =
 242         //.hub_resume =
 243 };
 244 #endif
 245 #ifdef CONFIG_USB20_HOST
 246 static const struct hc_driver host20_hc_driver = {
 247
 248         .description =          "host20_hcd",
 249         .product_desc =         "DWC OTG Controller",
 250         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 251
 252         .irq =                  dwc_otg_hcd_irq,
 253
 254         .flags =                HCD_MEMORY | HCD_USB2,
 255
 256         //.reset =
 257         .start =                dwc_otg_hcd_start,
 258         //.suspend =
 259         //.resume =
 260
 261         /* yk@rk 20100625
 262          * core/hcd.c call hcd->driver->bus_suspend
 263          * otherwise system can not be suspended
 264          */
 265 #ifdef CONFIG_PM
 266         .bus_suspend =          dwc_otg_hcd_suspend,
 267         .bus_resume =           dwc_otg_hcd_resume,
 268 #endif
 269         .stop =                 dwc_otg_hcd_stop,
 270
 271         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 272         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 273         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 274
 275         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 276
 277         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 278         .hub_control =          dwc_otg_hcd_hub_control,
 279         //.hub_suspend =
 280         //.hub_resume =
 281 };
 282 #endif
 283
 284 /**
 285  * Work queue function for starting the HCD when A-Cable is connected.
 286  * The dwc_otg_hcd_start() must be called in a process context.
 287  */
 288 static void hcd_start_func(struct work_struct *work)
 289 {
 290     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 291     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 292
 293     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 294     if (hcd) {
 295             dwc_otg_hcd_start(hcd);
 296     }
 297 }
 298
 299 /**
 300  * HCD Callback function for starting the HCD when A-Cable is
 301  * connected.
 302  *
 303  * @param _p void pointer to the <code>struct usb_hcd</code>
 304  */
 305 static int32_t dwc_otg_hcd_start_cb(void *_p)
 306 {
 307         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 308         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 309         hprt0_data_t hprt0;
 310
 311         if (core_if->op_state == B_HOST) {
 312                 /*
 313                  * Reset the port.  During a HNP mode switch the reset
 314                  * needs to occur within 1ms and have a duration of at
 315                  * least 50ms.
 316                  */
 317                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 318                 hprt0.b.prtrst = 1;
 319                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 320                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 321         } else {
 322                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 323         }
 324
 325         /* Need to start the HCD in a non-interrupt context. */
 326 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 327         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 328         schedule_work(&dwc_otg_hcd->start_work);
 329
 330         return 1;
 331 }
 332
 333
 334 /**
 335  * HCD Callback function for stopping the HCD.
 336  *
 337  * @param _p void pointer to the <code>struct usb_hcd</code>
 338  */
 339 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 340 {
 341         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 342         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 343         dwc_otg_hcd_stop( usb_hcd );
 344         return 1;
 345 }
 346
 347 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 348 {
 349 #ifdef DEBUG
 350         int i;
 351         int num_channels = _hcd->core_if->core_params->host_channels;
 352         for (i = 0; i < num_channels; i++) {
 353                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 354         }
 355 #endif
 356 }
 357
 358 static void del_timers(dwc_otg_hcd_t *_hcd)
 359 {
 360         del_xfer_timers(_hcd);
 361         del_timer(&_hcd->conn_timer);
 362 }
 363
 364 /**
 365  * Processes all the URBs in a single list of QHs. Completes them with
 366  * -ETIMEDOUT and frees the QTD.
 367  */
 368 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 369 {
 370         struct list_head        *qh_item;
 371         dwc_otg_qh_t            *qh;
 372         struct list_head        *qtd_item;
 373         dwc_otg_qtd_t           *qtd;
 374
 375         list_for_each(qh_item, _qh_list) {
 376                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 377                 for (qtd_item = qh->qtd_list.next;
 378                      qtd_item != &qh->qtd_list;
 379                      qtd_item = qh->qtd_list.next) {
 380                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 381                         if (qtd->urb != NULL) {
 382                                 dwc_otg_hcd_complete_urb(_hcd, qtd->urb,
 383                                                          -ETIMEDOUT);
 384                         }
 385                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 386                 }
 387         }
 388 }
 389
 390 /**
 391  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 392  * and periodic schedules. The QTD associated with each URB is removed from
 393  * the schedule and freed. This function may be called when a disconnect is
 394  * detected or when the HCD is being stopped.
 395  */
 396 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 397 {
 398         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 399         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 400         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 401         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 402         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 403         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 404 }
 405
 406 /**
 407  * HCD Callback function for disconnect of the HCD.
 408  *
 409  * @param _p void pointer to the <code>struct usb_hcd</code>
 410  */
 411 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 412 {
 413         gintsts_data_t  intr;
 414         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 415
 416         //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 417
 418         /*
 419          * Set status flags for the hub driver.
 420          */
 421 //     DWC_PRINT("dwc_otg_hcd_disconnect_cb");
 422         dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 423         dwc_otg_hcd->flags.b.port_connect_status = 0;
 424
 425         /*
 426          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 427          * interrupt mask and status bits and disabling subsequent host
 428          * channel interrupts.
 429          */
 430         intr.d32 = 0;
 431         intr.b.nptxfempty = 1;
 432         intr.b.ptxfempty = 1;
 433         intr.b.hcintr = 1;
 434         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 435         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 436
 437         del_timers(dwc_otg_hcd);
 438
 439         /*
 440          * Turn off the vbus power only if the core has transitioned to device
 441          * mode. If still in host mode, need to keep power on to detect a
 442          * reconnection.
 443          */
 444         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 445                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 446                         hprt0_data_t hprt0 = { .d32=0 };
 447                         DWC_PRINT("Disconnect: PortPower off\n");
 448                         hprt0.b.prtpwr = 0;
 449                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 450                 }
 451
 452                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 453         }
 454
 455         /* Respond with an error status to all URBs in the schedule. */
 456         kill_all_urbs(dwc_otg_hcd);
 457
 458         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 459                 /* Clean up any host channels that were in use. */
 460                 int                     num_channels;
 461                 int                     i;
 462                 dwc_hc_t                *channel;
 463                 dwc_otg_hc_regs_t       *hc_regs;
 464                 hcchar_data_t           hcchar;
 465
 466                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 467
 468                 if (!dwc_otg_hcd->core_if->dma_enable) {
 469                         /* Flush out any channel requests in slave mode. */
 470                         for (i = 0; i < num_channels; i++) {
 471                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 472                                 if (list_empty(&channel->hc_list_entry)) {
 473                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 474                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 475                                         if (hcchar.b.chen) {
 476                                                 hcchar.b.chen = 0;
 477                                                 hcchar.b.chdis = 1;
 478                                                 hcchar.b.epdir = 0;
 479                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 480                                         }
 481                                 }
 482                         }
 483                 }
 484
 485                 for (i = 0; i < num_channels; i++) {
 486                         channel = dwc_otg_hcd->hc_ptr_array[i];
 487                         if (list_empty(&channel->hc_list_entry)) {
 488                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 489                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 490                                 if (hcchar.b.chen) {
 491                                         /* Halt the channel. */
 492                                         hcchar.b.chdis = 1;
 493                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 494                                 }
 495
 496                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 497                                 list_add_tail(&channel->hc_list_entry,
 498                                               &dwc_otg_hcd->free_hc_list);
 499                         }
 500                 }
 501         }
 502
 503         /* A disconnect will end the session so the B-Device is no
 504          * longer a B-host. */
 505         ((struct usb_hcd *)_p)->self.is_b_host = 0;
 506         return 1;
 507 }
 508
 509 /**
 510  * Connection timeout function.  An OTG host is required to display a
 511  * message if the device does not connect within 10 seconds.
 512  */
 513 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 514 {
 515         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 516         DWC_PRINT( "Connect Timeout\n");
 517         DWC_ERROR( "Device Not Connected/Responding\n" );
 518 }
 519
 520 /**
 521  * Start the connection timer.  An OTG host is required to display a
 522  * message if the device does not connect within 10 seconds.  The
 523  * timer is deleted if a port connect interrupt occurs before the
 524  * timer expires.
 525  */
 526 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 527 {
 528         init_timer( &_hcd->conn_timer );
 529         _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 530         _hcd->conn_timer.data = (unsigned long)0;
 531         _hcd->conn_timer.expires = jiffies + (HZ*10);
 532         add_timer( &_hcd->conn_timer );
 533 }
 534
 535 /**
 536  * HCD Callback function for disconnect of the HCD.
 537  *
 538  * @param _p void pointer to the <code>struct usb_hcd</code>
 539  */
 540 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 541 {
 542         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 543         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 544         dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 545         return 1;
 546 }
 547
 548 /**
 549  * HCD Callback structure for handling mode switching.
 550  */
 551 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 552         .start = dwc_otg_hcd_start_cb,
 553         .stop = dwc_otg_hcd_stop_cb,
 554         .disconnect = dwc_otg_hcd_disconnect_cb,
 555         .session_start = dwc_otg_hcd_session_start_cb,
 556         .p = 0,//hcd
 557 };
 558
 559 /**
 560  * Reset tasklet function
 561  */
 562 static void reset_tasklet_func (unsigned long data)
 563 {
 564         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 565         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 566         hprt0_data_t hprt0;
 567
 568         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 569
 570         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 571         hprt0.b.prtrst = 1;
 572         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 573         mdelay (60);
 574
 575         hprt0.b.prtrst = 0;
 576         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 577         dwc_otg_hcd->flags.b.port_reset_change = 1;
 578
 579         return;
 580 }
 581
 582 static struct tasklet_struct reset_tasklet = {
 583         .next = NULL,
 584         .state = 0,
 585         .count = ATOMIC_INIT(0),
 586         .func = reset_tasklet_func,
 587         .data = 0,
 588 };
 589
 590 /**
 591  * Initializes the HCD. This function allocates memory for and initializes the
 592  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 593  * USB bus with the core and calls the hc_driver->start() function. It returns
 594  * a negative error on failure.
 595  */
 596 extern uint32_t g_dbg_lvl;
 597 int __devinit dwc_otg_hcd_init(struct device *dev)
 598 {
 599         struct usb_hcd *hcd = NULL;
 600         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 601     dwc_otg_device_t *otg_dev = dev->platform_data;
 602
 603         int             num_channels;
 604         int             i;
 605         dwc_hc_t        *channel;
 606
 607         int retval = 0;
 608 #if 1  //kaiker .these code must execute before usb_create_hcd
 609         /* Set device flags indicating whether the HCD supports DMA. */
 610         static u64 usb_dmamask = 0xffffffffUL;
 611         if (otg_dev->core_if->dma_enable) {
 612                 dev->dma_mask = &usb_dmamask;
 613                 dev->coherent_dma_mask = ~0;
 614         } else {
 615                 dev->dma_mask = (void *)0;
 616                 dev->coherent_dma_mask = 0;
 617         }
 618 #endif
 619         DWC_PRINT("dwc_otg_hcd_init everest\n");
 620 //      g_dbg_lvl = 0xff;
 621
 622         /*
 623          * Allocate memory for the base HCD plus the DWC OTG HCD.
 624          * Initialize the base HCD.
 625          */
 626         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 627         if (hcd == NULL) {
 628                 retval = -ENOMEM;
 629                 goto error1;
 630         }
 631         hcd->regs = otg_dev->base;
 632         hcd->self.otg_port = 1;
 633
 634         /* Initialize the DWC OTG HCD. */
 635         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 636
 637         spin_lock_init(&dwc_otg_hcd->global_lock);
 638
 639         dwc_otg_hcd->core_if = otg_dev->core_if;
 640         otg_dev->hcd = dwc_otg_hcd;
 641
 642         /* Register the HCD CIL Callbacks */
 643         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 644                                            &hcd_cil_callbacks, hcd);
 645
 646         /* Initialize the non-periodic schedule. */
 647         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 648         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 649
 650         /* Initialize the periodic schedule. */
 651         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 652         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 653         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 654         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 655
 656         /*
 657          * Create a host channel descriptor for each host channel implemented
 658          * in the controller. Initialize the channel descriptor array.
 659          */
 660         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 661         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 662         for (i = 0; i < num_channels; i++) {
 663                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 664                 if (channel == NULL) {
 665                         retval = -ENOMEM;
 666                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 667                         goto error2;
 668                 }
 669                 memset(channel, 0, sizeof(dwc_hc_t));
 670                 channel->hc_num = i;
 671                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 672 #ifdef DEBUG
 673                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 674 #endif
 675
 676                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 677         }
 678
 679         /* Initialize the Connection timeout timer. */
 680         init_timer( &dwc_otg_hcd->conn_timer );
 681
 682         /* Initialize reset tasklet. */
 683         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 684         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 685         /*
 686          * Finish generic HCD initialization and start the HCD. This function
 687          * allocates the DMA buffer pool, registers the USB bus, requests the
 688          * IRQ line, and calls dwc_otg_hcd_start method.
 689          */
 690         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 691                                         IRQF_SHARED);
 692         if (retval < 0) {
 693                 DWC_ERROR("usb_add_hcd fail,everest\n");
 694                 goto error2;
 695         }
 696         /*
 697          * Allocate space for storing data on status transactions. Normally no
 698          * data is sent, but this space acts as a bit bucket. This must be
 699          * done after usb_add_hcd since that function allocates the DMA buffer
 700          * pool.
 701          */
 702         if (otg_dev->core_if->dma_enable) {
 703                 dwc_otg_hcd->status_buf =
 704                         dma_alloc_coherent(dev,
 705                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 706                                            &dwc_otg_hcd->status_buf_dma,
 707                                            GFP_KERNEL | GFP_DMA);
 708         } else {
 709                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 710                                                   GFP_KERNEL);
 711         }
 712         if (dwc_otg_hcd->status_buf == NULL) {
 713                 retval = -ENOMEM;
 714                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 715                 goto error3;
 716         }
 717
 718         DWC_PRINT("%s end,everest\n",__func__);
 719 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 720 //                  dev->bus_id, hcd->self.busnum);
 721
 722         return 0;
 723
 724         /* Error conditions */
 725  error3:
 726         usb_remove_hcd(hcd);
 727  error2:
 728         dwc_otg_hcd_free(hcd);
 729         usb_put_hcd(hcd);
 730
 731  error1:
 732         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 733         return retval;
 734 }
 735
 736 #ifdef CONFIG_USB11_HOST
 737 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 738         .start = dwc_otg_hcd_start_cb,
 739         .stop = dwc_otg_hcd_stop_cb,
 740         .disconnect = dwc_otg_hcd_disconnect_cb,
 741         .session_start = dwc_otg_hcd_session_start_cb,
 742         .p = 0,//hcd
 743 };
 744
 745 static struct tasklet_struct host11_reset_tasklet = {
 746         .next = NULL,
 747         .state = 0,
 748         .count = ATOMIC_INIT(0),
 749         .func = reset_tasklet_func,
 750         .data = 0,
 751 };
 752
 753 int __devinit host11_hcd_init(struct device *dev)
 754 {
 755         struct usb_hcd *hcd = NULL;
 756         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 757     dwc_otg_device_t *otg_dev = dev->platform_data;
 758
 759         int             num_channels;
 760         int             i;
 761         dwc_hc_t        *channel;
 762
 763         int retval = 0;
 764 #if 1  //kaiker .these code must execute before usb_create_hcd
 765         /* Set device flags indicating whether the HCD supports DMA. */
 766         static u64 usb_dmamask = 0xffffffffUL;
 767         if (otg_dev->core_if->dma_enable) {
 768 //              DWC_PRINT("Using DMA mode\n");
 769                 dev->dma_mask = &usb_dmamask;
 770                 dev->coherent_dma_mask = ~0;
 771         } else {
 772 //              DWC_PRINT("Using Slave mode\n");
 773                 dev->dma_mask = (void *)0;
 774                 dev->coherent_dma_mask = 0;
 775         }
 776 #endif
 777         DWC_PRINT("%s everest\n",__func__);
 778 //      g_dbg_lvl = 0xff;
 779
 780         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 781
 782         /*
 783          * Allocate memory for the base HCD plus the DWC OTG HCD.
 784          * Initialize the base HCD.
 785          */
 786         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 787         if (hcd == NULL) {
 788                 retval = -ENOMEM;
 789                 goto error1;
 790         }
 791         hcd->regs = otg_dev->base;
 792         hcd->self.otg_port = 1;
 793
 794         /* Initialize the DWC OTG HCD. */
 795         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 796         dwc_otg_hcd->core_if = otg_dev->core_if;
 797         otg_dev->hcd = dwc_otg_hcd;
 798
 799         spin_lock_init(&dwc_otg_hcd->global_lock);
 800
 801
 802         /* Register the HCD CIL Callbacks */
 803         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 804                                            &host11_cil_callbacks, hcd);
 805
 806         /* Initialize the non-periodic schedule. */
 807         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 808         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 809
 810         /* Initialize the periodic schedule. */
 811         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 812         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 813         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 814         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 815
 816         /*
 817          * Create a host channel descriptor for each host channel implemented
 818          * in the controller. Initialize the channel descriptor array.
 819          */
 820         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 821         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 822         for (i = 0; i < num_channels; i++) {
 823                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 824                 if (channel == NULL) {
 825                         retval = -ENOMEM;
 826                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 827                         goto error2;
 828                 }
 829                 memset(channel, 0, sizeof(dwc_hc_t));
 830                 channel->hc_num = i;
 831                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 832 #ifdef DEBUG
 833                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 834 #endif
 835
 836                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 837         }
 838
 839         /* Initialize the Connection timeout timer. */
 840         init_timer( &dwc_otg_hcd->conn_timer );
 841
 842         /* Initialize reset tasklet. */
 843         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 844         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 845         /*
 846          * Finish generic HCD initialization and start the HCD. This function
 847          * allocates the DMA buffer pool, registers the USB bus, requests the
 848          * IRQ line, and calls dwc_otg_hcd_start method.
 849          */
 850         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 851                                         IRQF_SHARED);
 852         if (retval < 0) {
 853                 DWC_ERROR("usb_add_hcd fail,everest\n");
 854                 goto error2;
 855         }
 856         /*
 857          * Allocate space for storing data on status transactions. Normally no
 858          * data is sent, but this space acts as a bit bucket. This must be
 859          * done after usb_add_hcd since that function allocates the DMA buffer
 860          * pool.
 861          */
 862         if (otg_dev->core_if->dma_enable) {
 863                 dwc_otg_hcd->status_buf =
 864                         dma_alloc_coherent(dev,
 865                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 866                                            &dwc_otg_hcd->status_buf_dma,
 867                                            GFP_KERNEL | GFP_DMA);
 868         } else {
 869                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 870                                                   GFP_KERNEL);
 871         }
 872         if (dwc_otg_hcd->status_buf == NULL) {
 873                 retval = -ENOMEM;
 874                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 875                 goto error3;
 876         }
 877
 878         DWC_PRINT("%s end,everest\n",__func__);
 879 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 880 //                  dev->bus_id, hcd->self.busnum);
 881
 882         return 0;
 883
 884         /* Error conditions */
 885  error3:
 886         usb_remove_hcd(hcd);
 887  error2:
 888         dwc_otg_hcd_free(hcd);
 889         usb_put_hcd(hcd);
 890
 891  error1:
 892         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 893         return retval;
 894 }
 895 #endif
 896 #ifdef CONFIG_USB20_HOST
 897 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
 898         .start = dwc_otg_hcd_start_cb,
 899         .stop = dwc_otg_hcd_stop_cb,
 900         .disconnect = dwc_otg_hcd_disconnect_cb,
 901         .session_start = dwc_otg_hcd_session_start_cb,
 902         .p = 0,//hcd
 903 };
 904
 905 static struct tasklet_struct host20_reset_tasklet = {
 906         .next = NULL,
 907         .state = 0,
 908         .count = ATOMIC_INIT(0),
 909         .func = reset_tasklet_func,
 910         .data = 0,
 911 };
 912
 913 int __devinit host20_hcd_init(struct device *dev)
 914 {
 915         struct usb_hcd *hcd = NULL;
 916         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 917     dwc_otg_device_t *otg_dev = dev->platform_data;
 918
 919         int             num_channels;
 920         int             i;
 921         dwc_hc_t        *channel;
 922
 923         int retval = 0;
 924 #if 1  //kaiker .these code must execute before usb_create_hcd
 925         /* Set device flags indicating whether the HCD supports DMA. */
 926         static u64 usb_dmamask = 0xffffffffUL;
 927         if (otg_dev->core_if->dma_enable) {
 928 //              DWC_PRINT("Using DMA mode\n");
 929                 dev->dma_mask = &usb_dmamask;
 930                 dev->coherent_dma_mask = ~0;
 931         } else {
 932 //              DWC_PRINT("Using Slave mode\n");
 933                 dev->dma_mask = (void *)0;
 934                 dev->coherent_dma_mask = 0;
 935         }
 936 #endif
 937         DWC_PRINT("%s everest\n",__func__);
 938 //      g_dbg_lvl = 0xff;
 939
 940         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 941
 942         /*
 943          * Allocate memory for the base HCD plus the DWC OTG HCD.
 944          * Initialize the base HCD.
 945          */
 946         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
 947         if (hcd == NULL) {
 948                 retval = -ENOMEM;
 949                 goto error1;
 950         }
 951         hcd->regs = otg_dev->base;
 952         hcd->self.otg_port = 1;
 953
 954         /* Initialize the DWC OTG HCD. */
 955         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 956         dwc_otg_hcd->core_if = otg_dev->core_if;
 957         otg_dev->hcd = dwc_otg_hcd;
 958
 959         spin_lock_init(&dwc_otg_hcd->global_lock);
 960
 961
 962         /* Register the HCD CIL Callbacks */
 963         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 964                                            &host20_cil_callbacks, hcd);
 965
 966         /* Initialize the non-periodic schedule. */
 967         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 968         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 969
 970         /* Initialize the periodic schedule. */
 971         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 972         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 973         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 974         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 975
 976         /*
 977          * Create a host channel descriptor for each host channel implemented
 978          * in the controller. Initialize the channel descriptor array.
 979          */
 980         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 981         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 982         for (i = 0; i < num_channels; i++) {
 983                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 984                 if (channel == NULL) {
 985                         retval = -ENOMEM;
 986                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 987                         goto error2;
 988                 }
 989                 memset(channel, 0, sizeof(dwc_hc_t));
 990                 channel->hc_num = i;
 991                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 992 #ifdef DEBUG
 993                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 994 #endif
 995
 996                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 997         }
 998
 999         /* Initialize the Connection timeout timer. */
1000         init_timer( &dwc_otg_hcd->conn_timer );
1001
1002         /* Initialize reset tasklet. */
1003         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1004         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1005         /*
1006          * Finish generic HCD initialization and start the HCD. This function
1007          * allocates the DMA buffer pool, registers the USB bus, requests the
1008          * IRQ line, and calls dwc_otg_hcd_start method.
1009          */
1010         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1011                                         IRQF_SHARED);
1012         if (retval < 0) {
1013                 DWC_ERROR("usb_add_hcd fail,everest\n");
1014                 goto error2;
1015         }
1016         /*
1017          * Allocate space for storing data on status transactions. Normally no
1018          * data is sent, but this space acts as a bit bucket. This must be
1019          * done after usb_add_hcd since that function allocates the DMA buffer
1020          * pool.
1021          */
1022         if (otg_dev->core_if->dma_enable) {
1023                 dwc_otg_hcd->status_buf =
1024                         dma_alloc_coherent(dev,
1025                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1026                                            &dwc_otg_hcd->status_buf_dma,
1027                                            GFP_KERNEL | GFP_DMA);
1028         } else {
1029                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1030                                                   GFP_KERNEL);
1031         }
1032         if (dwc_otg_hcd->status_buf == NULL) {
1033                 retval = -ENOMEM;
1034                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1035                 goto error3;
1036         }
1037
1038         DWC_PRINT("%s end,everest\n",__func__);
1039 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
1040 //                  dev->bus_id, hcd->self.busnum);
1041
1042         return 0;
1043
1044         /* Error conditions */
1045  error3:
1046         usb_remove_hcd(hcd);
1047  error2:
1048         dwc_otg_hcd_free(hcd);
1049         usb_put_hcd(hcd);
1050
1051  error1:
1052         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1053         return retval;
1054 }
1055 #endif
1056
1057 /**
1058  * Removes the HCD.
1059  * Frees memory and resources associated with the HCD and deregisters the bus.
1060  */
1061 void dwc_otg_hcd_remove(struct device *dev)
1062 {
1063         dwc_otg_device_t *otg_dev = dev->platform_data;
1064     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1065         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1066
1067         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1068
1069         /* Turn off all interrupts */
1070         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1071         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1072
1073         usb_remove_hcd(hcd);
1074         dwc_otg_hcd_free(hcd);
1075         usb_put_hcd(hcd);
1076
1077         return;
1078 }
1079
1080
1081 /* =========================================================================
1082  *  Linux HC Driver Functions
1083  * ========================================================================= */
1084
1085 /**
1086  * Initializes dynamic portions of the DWC_otg HCD state.
1087  */
1088 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1089 {
1090         struct list_head        *item;
1091         int                     num_channels;
1092         int                     i;
1093         dwc_hc_t                *channel;
1094         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1095
1096         _hcd->flags.d32 = 0;
1097
1098         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1099         _hcd->non_periodic_channels = 0;
1100         _hcd->periodic_channels = 0;
1101
1102         /*
1103          * Put all channels in the free channel list and clean up channel
1104          * states.
1105          */
1106         item = _hcd->free_hc_list.next;
1107         while (item != &_hcd->free_hc_list) {
1108                 list_del(item);
1109                 item = _hcd->free_hc_list.next;
1110         }
1111         num_channels = _hcd->core_if->core_params->host_channels;
1112         for (i = 0; i < num_channels; i++) {
1113                 channel = _hcd->hc_ptr_array[i];
1114                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1115                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1116         }
1117
1118         /* Initialize the DWC core for host mode operation. */
1119         dwc_otg_core_host_init(_hcd->core_if);
1120 }
1121
1122 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1123  * mode operation. Activates the root port. Returns 0 on success and a negative
1124  * error code on failure. */
1125 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1126 {
1127     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1128     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1129         unsigned long flags;
1130
1131         struct usb_bus *bus;
1132
1133         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1134         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1135
1136         DWC_PRINT("dwc_otg_hcd_start! everest\n");
1137         bus = hcd_to_bus(_hcd);
1138         _hcd->state = HC_STATE_RUNNING;
1139
1140         /* Initialize and connect root hub if one is not already attached */
1141         if (bus->root_hub) {
1142                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1143                 /* Inform the HUB driver to resume. */
1144                 usb_hcd_resume_root_hub(_hcd);
1145         }
1146         else {
1147             /*
1148              * no use
1149              * yk@rk 2010121
1150             struct usb_device *udev;6
1151                 udev = usb_alloc_dev(NULL, bus, 0);
1152                 udev->speed = USB_SPEED_HIGH;
1153                 if (!udev) {
1154                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1155                         return -ENODEV;
1156                 }
1157         */
1158             /* Not needed - VJ
1159                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1160                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1161                return -ENODEV;
1162                }
1163              */
1164         }
1165         /* Initialize the bus state.  If the core is in Device Mode
1166          * HALT the USB bus and return. */
1167         if (dwc_otg_is_device_mode (core_if)) {
1168                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1169                 //_hcd->state = HC_STATE_HALT;
1170                 goto out;
1171         }
1172         hcd_reinit(dwc_otg_hcd);
1173 out:
1174         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1175
1176         return 0;
1177 }
1178
1179 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1180 {
1181         struct list_head        *item;
1182         dwc_otg_qh_t            *qh;
1183
1184         if (_qh_list->next == NULL) {
1185                 /* The list hasn't been initialized yet. */
1186                 return;
1187         }
1188
1189         /* Ensure there are no QTDs or URBs left. */
1190         kill_urbs_in_qh_list(_hcd, _qh_list);
1191
1192         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1193                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1194                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1195         }
1196 }
1197
1198 /**
1199  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1200  * stopped.
1201  */
1202 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1203 {
1204         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1205         hprt0_data_t hprt0 = { .d32=0 };
1206
1207         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1208
1209         /* Turn off all host-specific interrupts. */
1210         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1211
1212         /*
1213          * The root hub should be disconnected before this function is called.
1214          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1215          * and the QH lists (via ..._hcd_endpoint_disable).
1216          */
1217
1218         /* Turn off the vbus power */
1219         DWC_PRINT("PortPower off\n");
1220         hprt0.b.prtpwr = 0;
1221         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1222
1223         return;
1224 }
1225
1226
1227 /** Returns the current frame number. */
1228 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1229 {
1230         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1231         hfnum_data_t hfnum;
1232
1233         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1234                                    host_if->host_global_regs->hfnum);
1235
1236 #ifdef DEBUG_SOF
1237         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1238 #endif
1239         return hfnum.b.frnum;
1240 }
1241
1242 /**
1243  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1244  * in the struct usb_hcd field.
1245  */
1246 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1247 {
1248         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1249         int             i;
1250
1251         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1252
1253         del_timers(dwc_otg_hcd);
1254
1255         /* Free memory for QH/QTD lists */
1256         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1257         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1258         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1259         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1260         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1261         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1262
1263         /* Free memory for the host channels. */
1264         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1265                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1266                 if (hc != NULL) {
1267                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1268                         kfree(hc);
1269                 }
1270         }
1271
1272         if (dwc_otg_hcd->core_if->dma_enable) {
1273                 if (dwc_otg_hcd->status_buf_dma) {
1274                         dma_free_coherent(_hcd->self.controller,
1275                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1276                                           dwc_otg_hcd->status_buf,
1277                                           dwc_otg_hcd->status_buf_dma);
1278                 }
1279         } else if (dwc_otg_hcd->status_buf != NULL) {
1280                 kfree(dwc_otg_hcd->status_buf);
1281         }
1282
1283         return;
1284 }
1285
1286
1287 #ifdef DEBUG
1288 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1289 {
1290         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1291         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1292                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1293         DWC_PRINT("  Endpoint type: %s\n",
1294                   ({char *pipetype;
1295                   switch (usb_pipetype(_urb->pipe)) {
1296                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1297                   case PIPE_BULK: pipetype = "BULK"; break;
1298                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1299                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1300                   default: pipetype = "UNKNOWN"; break;
1301                   }; pipetype;}));
1302         DWC_PRINT("  Speed: %s\n",
1303                   ({char *speed;
1304                   switch (_urb->dev->speed) {
1305                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1306                   case USB_SPEED_FULL: speed = "FULL"; break;
1307                   case USB_SPEED_LOW: speed = "LOW"; break;
1308                   default: speed = "UNKNOWN"; break;
1309                   }; speed;}));
1310         DWC_PRINT("  Max packet size: %d\n",
1311                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1312         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1313         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1314                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1315         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1316                   _urb->setup_packet, (void *)_urb->setup_dma);
1317         DWC_PRINT("  Interval: %d\n", _urb->interval);
1318         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1319                 int i;
1320                 for (i = 0; i < _urb->number_of_packets;  i++) {
1321                         DWC_PRINT("  ISO Desc %d:\n", i);
1322                         DWC_PRINT("    offset: %d, length %d\n",
1323                                   _urb->iso_frame_desc[i].offset,
1324                                   _urb->iso_frame_desc[i].length);
1325                 }
1326         }
1327 }
1328
1329 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1330                               dwc_otg_qh_t *qh)
1331 {
1332         if (qh->channel != NULL) {
1333                 dwc_hc_t *hc = qh->channel;
1334                 struct list_head *item;
1335                 dwc_otg_qh_t *qh_item;
1336                 int num_channels = _hcd->core_if->core_params->host_channels;
1337                 int i;
1338
1339                 dwc_otg_hc_regs_t *hc_regs;
1340                 hcchar_data_t   hcchar;
1341                 hcsplt_data_t   hcsplt;
1342                 hctsiz_data_t   hctsiz;
1343                 uint32_t        hcdma;
1344
1345                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1346                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1347                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1348                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1349                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1350
1351                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1352                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1353                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1354                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1355                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1356                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1357                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1358                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1359                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1360                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1361                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1362                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1363                 DWC_PRINT("    qh: %p\n", hc->qh);
1364                 DWC_PRINT("  NP inactive sched:\n");
1365                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1366                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1367                         DWC_PRINT("    %p\n", qh_item);
1368                 }
1369                 DWC_PRINT("  NP active sched:\n");
1370                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1371                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1372                         DWC_PRINT("    %p\n", qh_item);
1373                 }
1374                 DWC_PRINT("  Channels: \n");
1375                 for (i = 0; i < num_channels; i++) {
1376                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1377                         DWC_PRINT("    %2d: %p\n", i, hc);
1378                 }
1379         }
1380 }
1381 #endif
1382
1383 /** Starts processing a USB transfer request specified by a USB Request Block
1384  * (URB). mem_flags indicates the type of memory allocation to use while
1385  * processing this URB. */
1386 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1387                             struct urb *_urb,
1388                             gfp_t _mem_flags)
1389 {
1390         int retval;
1391         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1392         dwc_otg_qtd_t * qtd;
1393         unsigned long flags;
1394
1395         retval = usb_hcd_link_urb_to_ep(_hcd, _urb);
1396         if (retval)
1397         {
1398                 DWC_PRINT("%s, usb_hcd_link_urb_to_ep error\n", __func__);
1399                 return retval;
1400         }
1401         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1402 #if 1
1403         /*
1404          * Make sure the start of frame interrupt is enabled now that
1405          * we know we should have queued data. The SOF interrupt
1406          * handler automatically disables itself when idle to reduce
1407          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1408          * for the disable
1409          */
1410         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1411                          DWC_SOF_INTR_MASK);
1412 #endif
1413 #ifdef DEBUG
1414             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1415                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1416         }
1417 #endif  /*  */
1418     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1419             /* No longer connected. */
1420                 retval =  -ENODEV;
1421                 goto out;
1422         }
1423         qtd = dwc_otg_hcd_qtd_create(_urb);
1424         if (qtd == NULL) {
1425                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1426                 retval = -ENOMEM;
1427                 goto out;
1428         }
1429         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1430         if (retval < 0) {
1431                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1432                            "Error status %d\n", retval);
1433                 dwc_otg_hcd_qtd_free(qtd);
1434         }
1435 out:
1436         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1437
1438         return retval;
1439 }
1440
1441 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1442  * success.  */
1443 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1444 {
1445         unsigned long flags;
1446         dwc_otg_hcd_t * dwc_otg_hcd;
1447         dwc_otg_qtd_t * urb_qtd;
1448         dwc_otg_qh_t * qh;
1449         struct usb_host_endpoint *_ep = _urb->ep;//dwc_urb_to_endpoint(_urb);
1450         int retval;
1451
1452         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1453         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1454         if(_ep==NULL)
1455         {
1456                 DWC_PRINT("%s=====================================================\n",__func__);
1457                 DWC_PRINT("urb->ep is null\n");
1458                 return -1;
1459         }
1460         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1461         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1462         retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status);
1463         if (retval) {
1464                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1465                 return retval;
1466         }
1467         if(urb_qtd == NULL)
1468         {
1469                 DWC_PRINT("%s,urb_qtd is null\n",__func__);
1470                 //return -1;
1471         }
1472         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1473
1474 #ifdef DEBUG
1475     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1476                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1477                 if (urb_qtd == qh->qtd_in_process) {
1478                         dump_channel_info(dwc_otg_hcd, qh);
1479                 }
1480         }
1481
1482 #endif  /*  */
1483 #if 1
1484     if (urb_qtd == qh->qtd_in_process) {
1485             /* The QTD is in process (it has been assigned to a channel). */
1486             if (dwc_otg_hcd->flags.b.port_connect_status) {
1487
1488                     /*
1489                      * If still connected (i.e. in host mode), halt the
1490                      * channel so it can be used for other transfers. If
1491                      * no longer connected, the host registers can't be
1492                      * written to halt the channel since the core is in
1493                      * device mode.
1494                      */
1495                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1496                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1497                 }
1498         }
1499
1500     /*
1501      * Free the QTD and clean up the associated QH. Leave the QH in the
1502      * schedule if it has any remaining QTDs.
1503      */
1504     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1505         if (urb_qtd == qh->qtd_in_process) {
1506                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1507                 qh->channel = NULL;
1508                 qh->qtd_in_process = NULL;
1509         } else if (list_empty(&qh->qtd_list)) {
1510                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1511         }
1512 #endif
1513         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1514         _urb->hcpriv = NULL;
1515         usb_hcd_unlink_urb_from_ep(_hcd, _urb);
1516     /* Higher layer software sets URB status. */
1517         usb_hcd_giveback_urb(_hcd, _urb, _status);
1518         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1519                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1520                 DWC_PRINT("  urb->status = %d\n", _status);
1521         }
1522         return 0;
1523 }
1524
1525
1526 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1527  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1528  * must already be dequeued. */
1529 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1530                                   struct usb_host_endpoint *_ep)
1531
1532 {
1533         unsigned long flags;
1534         dwc_otg_qh_t *qh;
1535         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1536
1537         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1538
1539         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1540                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1541                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1542
1543         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1544         if (qh != NULL) {
1545 #ifdef DEBUG
1546                 /** Check that the QTD list is really empty */
1547                 if (!list_empty(&qh->qtd_list)) {
1548                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1549                                  " QTD List for this endpoint is not empty\n");
1550                 }
1551 #endif
1552
1553                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1554                 _ep->hcpriv = NULL;
1555         }
1556
1557         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1558
1559         return;
1560 }
1561
1562 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1563  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1564  * interrupt.
1565  *
1566  * This function is called by the USB core when an interrupt occurs */
1567 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1568 {
1569         irqreturn_t result;
1570         unsigned long flags;
1571         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1572
1573         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1574
1575         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1576
1577         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1578
1579         return result;
1580 }
1581
1582 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1583  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1584  * is the status change indicator for the single root port. Returns 1 if either
1585  * change indicator is 1, otherwise returns 0. */
1586 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1587                                 char *_buf)
1588 {
1589         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1590
1591         _buf[0] = 0;
1592         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1593                     dwc_otg_hcd->flags.b.port_reset_change ||
1594                     dwc_otg_hcd->flags.b.port_enable_change ||
1595                     dwc_otg_hcd->flags.b.port_suspend_change ||
1596                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1597
1598 #ifdef DEBUG
1599         if (_buf[0]) {
1600                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1601                             " Root port status changed\n");
1602                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1603                             dwc_otg_hcd->flags.b.port_connect_status_change);
1604                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1605                             dwc_otg_hcd->flags.b.port_reset_change);
1606                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1607                             dwc_otg_hcd->flags.b.port_enable_change);
1608                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1609                             dwc_otg_hcd->flags.b.port_suspend_change);
1610                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1611                             dwc_otg_hcd->flags.b.port_over_current_change);
1612         }
1613 #endif
1614         return (_buf[0] != 0);
1615 }
1616
1617 #ifdef DWC_HS_ELECT_TST
1618 /*
1619  * Quick and dirty hack to implement the HS Electrical Test
1620  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1621  *
1622  * This code was copied from our userspace app "hset". It sends a
1623  * Get Device Descriptor control sequence in two parts, first the
1624  * Setup packet by itself, followed some time later by the In and
1625  * Ack packets. Rather than trying to figure out how to add this
1626  * functionality to the normal driver code, we just hijack the
1627  * hardware, using these two function to drive the hardware
1628  * directly.
1629  */
1630
1631 dwc_otg_core_global_regs_t *global_regs;
1632 dwc_otg_host_global_regs_t *hc_global_regs;
1633 dwc_otg_hc_regs_t *hc_regs;
1634 uint32_t *data_fifo;
1635
1636 static void do_setup(void)
1637 {
1638         gintsts_data_t gintsts;
1639         hctsiz_data_t hctsiz;
1640         hcchar_data_t hcchar;
1641         haint_data_t haint;
1642         hcint_data_t hcint;
1643
1644         /* Enable HAINTs */
1645         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1646
1647         /* Enable HCINTs */
1648         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1649
1650         /* Read GINTSTS */
1651         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1652         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1653
1654         /* Read HAINT */
1655         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1656         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1657
1658         /* Read HCINT */
1659         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1660         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1661
1662         /* Read HCCHAR */
1663         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1664         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1665
1666         /* Clear HCINT */
1667         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1668
1669         /* Clear HAINT */
1670         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1671
1672         /* Clear GINTSTS */
1673         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1674
1675         /* Read GINTSTS */
1676         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1677         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1678
1679         /*
1680          * Send Setup packet (Get Device Descriptor)
1681          */
1682
1683         /* Make sure channel is disabled */
1684         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1685         if (hcchar.b.chen) {
1686                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1687                 hcchar.b.chdis = 1;
1688 //              hcchar.b.chen = 1;
1689                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1690                 //sleep(1);
1691                 mdelay(1000);
1692
1693                 /* Read GINTSTS */
1694                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1695                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1696
1697                 /* Read HAINT */
1698                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1699                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1700
1701                 /* Read HCINT */
1702                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1703                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1704
1705                 /* Read HCCHAR */
1706                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1707                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1708
1709                 /* Clear HCINT */
1710                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1711
1712                 /* Clear HAINT */
1713                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1714
1715                 /* Clear GINTSTS */
1716                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1717
1718                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1719                 //if (hcchar.b.chen) {
1720                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1721                 //}
1722         }
1723
1724         /* Set HCTSIZ */
1725         hctsiz.d32 = 0;
1726         hctsiz.b.xfersize = 8;
1727         hctsiz.b.pktcnt = 1;
1728         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1729         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1730
1731         /* Set HCCHAR */
1732         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1733         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1734         hcchar.b.epdir = 0;
1735         hcchar.b.epnum = 0;
1736         hcchar.b.mps = 8;
1737         hcchar.b.chen = 1;
1738         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1739
1740         /* Fill FIFO with Setup data for Get Device Descriptor */
1741         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1742         dwc_write_reg32(data_fifo++, 0x01000680);
1743         dwc_write_reg32(data_fifo++, 0x00080000);
1744
1745         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1746         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1747
1748         /* Wait for host channel interrupt */
1749         do {
1750                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1751         } while (gintsts.b.hcintr == 0);
1752
1753         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1754
1755         /* Disable HCINTs */
1756         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1757
1758         /* Disable HAINTs */
1759         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1760
1761         /* Read HAINT */
1762         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1763         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1764
1765         /* Read HCINT */
1766         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1767         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1768
1769         /* Read HCCHAR */
1770         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1771         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1772
1773         /* Clear HCINT */
1774         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1775
1776         /* Clear HAINT */
1777         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1778
1779         /* Clear GINTSTS */
1780         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1781
1782         /* Read GINTSTS */
1783         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1784         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1785 }
1786
1787 static void do_in_ack(void)
1788 {
1789         gintsts_data_t gintsts;
1790         hctsiz_data_t hctsiz;
1791         hcchar_data_t hcchar;
1792         haint_data_t haint;
1793         hcint_data_t hcint;
1794         host_grxsts_data_t grxsts;
1795
1796         /* Enable HAINTs */
1797         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1798
1799         /* Enable HCINTs */
1800         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1801
1802         /* Read GINTSTS */
1803         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1804         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1805
1806         /* Read HAINT */
1807         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1808         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1809
1810         /* Read HCINT */
1811         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1812         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1813
1814         /* Read HCCHAR */
1815         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1816         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1817
1818         /* Clear HCINT */
1819         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1820
1821         /* Clear HAINT */
1822         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1823
1824         /* Clear GINTSTS */
1825         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1826
1827         /* Read GINTSTS */
1828         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1829         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1830
1831         /*
1832          * Receive Control In packet
1833          */
1834
1835         /* Make sure channel is disabled */
1836         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1837         if (hcchar.b.chen) {
1838                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1839                 hcchar.b.chdis = 1;
1840                 hcchar.b.chen = 1;
1841                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1842                 //sleep(1);
1843                 mdelay(1000);
1844
1845                 /* Read GINTSTS */
1846                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1847                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1848
1849                 /* Read HAINT */
1850                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1851                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1852
1853                 /* Read HCINT */
1854                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1855                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1856
1857                 /* Read HCCHAR */
1858                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1859                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1860
1861                 /* Clear HCINT */
1862                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1863
1864                 /* Clear HAINT */
1865                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1866
1867                 /* Clear GINTSTS */
1868                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1869
1870                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1871                 //if (hcchar.b.chen) {
1872                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
1873                 //}
1874         }
1875
1876         /* Set HCTSIZ */
1877         hctsiz.d32 = 0;
1878         hctsiz.b.xfersize = 8;
1879         hctsiz.b.pktcnt = 1;
1880         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
1881         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1882
1883         /* Set HCCHAR */
1884         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1885         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1886         hcchar.b.epdir = 1;
1887         hcchar.b.epnum = 0;
1888         hcchar.b.mps = 8;
1889         hcchar.b.chen = 1;
1890         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1891
1892         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1893         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
1894
1895         /* Wait for receive status queue interrupt */
1896         do {
1897                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1898         } while (gintsts.b.rxstsqlvl == 0);
1899
1900         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
1901
1902         /* Read RXSTS */
1903         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
1904         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
1905
1906         /* Clear RXSTSQLVL in GINTSTS */
1907         gintsts.d32 = 0;
1908         gintsts.b.rxstsqlvl = 1;
1909         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1910
1911         switch (grxsts.b.pktsts) {
1912         case DWC_GRXSTS_PKTSTS_IN:
1913                 /* Read the data into the host buffer */
1914                 if (grxsts.b.bcnt > 0) {
1915                         int i;
1916                         int word_count = (grxsts.b.bcnt + 3) / 4;
1917
1918                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1919
1920                         for (i = 0; i < word_count; i++) {
1921                                 (void)dwc_read_reg32(data_fifo++);
1922                         }
1923                 }
1924
1925                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
1926         break;
1927
1928         default:
1929                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
1930         break;
1931         }
1932
1933         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1934         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
1935
1936         /* Wait for receive status queue interrupt */
1937         do {
1938                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1939         } while (gintsts.b.rxstsqlvl == 0);
1940
1941         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
1942
1943         /* Read RXSTS */
1944         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
1945         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
1946
1947         /* Clear RXSTSQLVL in GINTSTS */
1948         gintsts.d32 = 0;
1949         gintsts.b.rxstsqlvl = 1;
1950         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1951
1952         switch (grxsts.b.pktsts) {
1953         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
1954         break;
1955
1956         default:
1957                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
1958         break;
1959         }
1960
1961         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1962         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
1963
1964         /* Wait for host channel interrupt */
1965         do {
1966                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1967         } while (gintsts.b.hcintr == 0);
1968
1969         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
1970
1971         /* Read HAINT */
1972         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1973         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1974
1975         /* Read HCINT */
1976         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1977         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1978
1979         /* Read HCCHAR */
1980         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1981         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1982
1983         /* Clear HCINT */
1984         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1985
1986         /* Clear HAINT */
1987         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1988
1989         /* Clear GINTSTS */
1990         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1991
1992         /* Read GINTSTS */
1993         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1994         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1995
1996 //      usleep(100000);
1997 //      mdelay(100);
1998         mdelay(1);
1999
2000         /*
2001          * Send handshake packet
2002          */
2003
2004         /* Read HAINT */
2005         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2006         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2007
2008         /* Read HCINT */
2009         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2010         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2011
2012         /* Read HCCHAR */
2013         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2014         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2015
2016         /* Clear HCINT */
2017         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2018
2019         /* Clear HAINT */
2020         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2021
2022         /* Clear GINTSTS */
2023         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2024
2025         /* Read GINTSTS */
2026         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2027         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2028
2029         /* Make sure channel is disabled */
2030         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2031         if (hcchar.b.chen) {
2032                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2033                 hcchar.b.chdis = 1;
2034                 hcchar.b.chen = 1;
2035                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2036                 //sleep(1);
2037                 mdelay(1000);
2038
2039                 /* Read GINTSTS */
2040                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2041                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2042
2043                 /* Read HAINT */
2044                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2045                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2046
2047                 /* Read HCINT */
2048                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2049                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2050
2051                 /* Read HCCHAR */
2052                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2053                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2054
2055                 /* Clear HCINT */
2056                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2057
2058                 /* Clear HAINT */
2059                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2060
2061                 /* Clear GINTSTS */
2062                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2063
2064                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2065                 //if (hcchar.b.chen) {
2066                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2067                 //}
2068         }
2069
2070         /* Set HCTSIZ */
2071         hctsiz.d32 = 0;
2072         hctsiz.b.xfersize = 0;
2073         hctsiz.b.pktcnt = 1;
2074         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2075         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2076
2077         /* Set HCCHAR */
2078         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2079         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2080         hcchar.b.epdir = 0;
2081         hcchar.b.epnum = 0;
2082         hcchar.b.mps = 8;
2083         hcchar.b.chen = 1;
2084         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2085
2086         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2087         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2088
2089         /* Wait for host channel interrupt */
2090         do {
2091                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2092         } while (gintsts.b.hcintr == 0);
2093
2094         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2095
2096         /* Disable HCINTs */
2097         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2098
2099         /* Disable HAINTs */
2100         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2101
2102         /* Read HAINT */
2103         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2104         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2105
2106         /* Read HCINT */
2107         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2108         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2109
2110         /* Read HCCHAR */
2111         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2112         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2113
2114         /* Clear HCINT */
2115         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2116
2117         /* Clear HAINT */
2118         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2119
2120         /* Clear GINTSTS */
2121         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2122
2123         /* Read GINTSTS */
2124         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2125         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2126 }
2127 #endif /* DWC_HS_ELECT_TST */
2128
2129 /** Handles hub class-specific requests.*/
2130 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2131                             u16 _typeReq,
2132                             u16 _wValue,
2133                             u16 _wIndex,
2134                             char *_buf,
2135                             u16 _wLength)
2136 {
2137         int retval = 0;
2138         unsigned long flags;
2139
2140         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2141         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2142         struct usb_hub_descriptor *desc;
2143         hprt0_data_t hprt0 = {.d32 = 0};
2144
2145         uint32_t port_status;
2146         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2147
2148         switch (_typeReq) {
2149         case ClearHubFeature:
2150                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2151                             "ClearHubFeature 0x%x\n", _wValue);
2152                 switch (_wValue) {
2153                 case C_HUB_LOCAL_POWER:
2154                 case C_HUB_OVER_CURRENT:
2155                         /* Nothing required here */
2156                         break;
2157                 default:
2158                         retval = -EINVAL;
2159                         DWC_ERROR ("DWC OTG HCD - "
2160                                    "ClearHubFeature request %xh unknown\n", _wValue);
2161                 }
2162                 break;
2163         case ClearPortFeature:
2164                 if (!_wIndex || _wIndex > 1)
2165                         goto error;
2166
2167                 switch (_wValue) {
2168                 case USB_PORT_FEAT_ENABLE:
2169                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2170                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2171                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2172                         hprt0.b.prtena = 1;
2173                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2174                         break;
2175                 case USB_PORT_FEAT_SUSPEND:
2176                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2177                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2178                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2179                         hprt0.b.prtres = 1;
2180                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2181                         /* Clear Resume bit */
2182                         mdelay (100);
2183                         hprt0.b.prtres = 0;
2184                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2185                         break;
2186                 case USB_PORT_FEAT_POWER:
2187                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2188                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2189                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2190                         hprt0.b.prtpwr = 0;
2191                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2192                         break;
2193                 case USB_PORT_FEAT_INDICATOR:
2194                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2195                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2196                         /* Port inidicator not supported */
2197                         break;
2198                 case USB_PORT_FEAT_C_CONNECTION:
2199                         /* Clears drivers internal connect status change
2200                          * flag */
2201                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2202                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2203                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2204                         break;
2205                 case USB_PORT_FEAT_C_RESET:
2206                         /* Clears the driver's internal Port Reset Change
2207                          * flag */
2208                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2209                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2210                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2211                         break;
2212                 case USB_PORT_FEAT_C_ENABLE:
2213                         /* Clears the driver's internal Port
2214                          * Enable/Disable Change flag */
2215                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2216                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2217                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2218                         break;
2219                 case USB_PORT_FEAT_C_SUSPEND:
2220                         /* Clears the driver's internal Port Suspend
2221                          * Change flag, which is set when resume signaling on
2222                          * the host port is complete */
2223                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2224                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2225                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2226                         break;
2227                 case USB_PORT_FEAT_C_OVER_CURRENT:
2228                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2229                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2230                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2231                         break;
2232                 default:
2233                         retval = -EINVAL;
2234                         DWC_ERROR ("DWC OTG HCD - "
2235                                    "ClearPortFeature request %xh "
2236                                    "unknown or unsupported\n", _wValue);
2237                 }
2238                 break;
2239         case GetHubDescriptor:
2240                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2241                              "GetHubDescriptor\n");
2242                 desc = (struct usb_hub_descriptor *)_buf;
2243                 desc->bDescLength = 9;
2244                 desc->bDescriptorType = 0x29;
2245                 desc->bNbrPorts = 1;
2246                 desc->wHubCharacteristics = 0x08;
2247                 desc->bPwrOn2PwrGood = 1;
2248                 desc->bHubContrCurrent = 0;
2249                 desc->bitmap[0] = 0;
2250                 desc->bitmap[1] = 0xff;
2251                 break;
2252         case GetHubStatus:
2253                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2254                              "GetHubStatus\n");
2255                 memset (_buf, 0, 4);
2256                 break;
2257         case GetPortStatus:
2258                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2259                              "GetPortStatus\n");
2260
2261                 if (!_wIndex || _wIndex > 1)
2262                         goto error;
2263
2264                 port_status = 0;
2265
2266                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2267                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2268
2269                 if (dwc_otg_hcd->flags.b.port_enable_change)
2270                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2271
2272                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2273                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2274
2275                 if (dwc_otg_hcd->flags.b.port_reset_change)
2276                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2277
2278                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2279                         DWC_ERROR("Device Not Supported\n");
2280                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2281                 }
2282
2283                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2284                         /*
2285                          * The port is disconnected, which means the core is
2286                          * either in device mode or it soon will be. Just
2287                          * return 0's for the remainder of the port status
2288                          * since the port register can't be read if the core
2289                          * is in device mode.
2290                          */
2291                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2292                         break;
2293                 }
2294
2295                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2296                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2297
2298                 if (hprt0.b.prtconnsts)
2299                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2300
2301                 if (hprt0.b.prtena)
2302                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2303
2304                 if (hprt0.b.prtsusp)
2305                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2306
2307                 if (hprt0.b.prtovrcurract)
2308                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2309
2310                 if (hprt0.b.prtrst)
2311                         port_status |= (1 << USB_PORT_FEAT_RESET);
2312
2313                 if (hprt0.b.prtpwr)
2314                         port_status |= (1 << USB_PORT_FEAT_POWER);
2315
2316                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2317                         port_status |= (1 << USB_PORT_FEAT_HIGHSPEED);
2318
2319                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2320                         port_status |= (1 << USB_PORT_FEAT_LOWSPEED);
2321
2322                 if (hprt0.b.prttstctl)
2323                         port_status |= (1 << USB_PORT_FEAT_TEST);
2324
2325                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2326
2327                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2328
2329                 break;
2330         case SetHubFeature:
2331                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2332                              "SetHubFeature\n");
2333                 /* No HUB features supported */
2334                 break;
2335         case SetPortFeature:
2336                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2337                         goto error;
2338
2339                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2340                         /*
2341                          * The port is disconnected, which means the core is
2342                          * either in device mode or it soon will be. Just
2343                          * return without doing anything since the port
2344                          * register can't be written if the core is in device
2345                          * mode.
2346                          */
2347                         break;
2348                 }
2349
2350                 switch (_wValue) {
2351                 case USB_PORT_FEAT_SUSPEND:
2352                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2353                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2354                         if (_hcd->self.otg_port == _wIndex &&
2355                             _hcd->self.b_hnp_enable) {
2356                                 gotgctl_data_t  gotgctl = {.d32=0};
2357                                 gotgctl.b.hstsethnpen = 1;
2358                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2359                                                   0, gotgctl.d32);
2360                                 core_if->op_state = A_SUSPEND;
2361                         }
2362                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2363                         hprt0.b.prtsusp = 1;
2364                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2365                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2366                         /* Suspend the Phy Clock */
2367                         {
2368                                 pcgcctl_data_t pcgcctl = {.d32=0};
2369                                 pcgcctl.b.stoppclk = 1;
2370                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2371                         }
2372
2373                         /* For HNP the bus must be suspended for at least 200ms.*/
2374                         if (_hcd->self.b_hnp_enable) {
2375                                 mdelay(200);
2376                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2377                         }
2378                         break;
2379                 case USB_PORT_FEAT_POWER:
2380                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2381                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2382                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2383                         hprt0.b.prtpwr = 1;
2384                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2385                         break;
2386                 case USB_PORT_FEAT_RESET:
2387                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2388                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2389                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2390                         /* When B-Host the Port reset bit is set in
2391                          * the Start HCD Callback function, so that
2392                          * the reset is started within 1ms of the HNP
2393                          * success interrupt. */
2394                         if (!_hcd->self.is_b_host) {
2395                                 hprt0.b.prtrst = 1;
2396                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2397                         }
2398                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2399                         MDELAY (60);
2400                         hprt0.b.prtrst = 0;
2401                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2402                         break;
2403
2404 #ifdef DWC_HS_ELECT_TST
2405                 case USB_PORT_FEAT_TEST:
2406                 {
2407                         uint32_t t;
2408                         gintmsk_data_t gintmsk;
2409
2410                         t = (_wIndex >> 8); /* MSB wIndex USB */
2411                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2412                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2413                         warn("USB_PORT_FEAT_TEST %d\n", t);
2414                         if (t < 6) {
2415                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2416                                 hprt0.b.prttstctl = t;
2417                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2418                         } else {
2419                                 /* Setup global vars with reg addresses (quick and
2420                                  * dirty hack, should be cleaned up)
2421                                  */
2422                                 global_regs = core_if->core_global_regs;
2423                                 hc_global_regs = core_if->host_if->host_global_regs;
2424                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2425                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2426
2427                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2428                                         /* Save current interrupt mask */
2429                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2430
2431                                         /* Disable all interrupts while we muck with
2432                                          * the hardware directly
2433                                          */
2434                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2435
2436                                         /* 15 second delay per the test spec */
2437                                         mdelay(15000);
2438
2439                                         /* Drive suspend on the root port */
2440                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2441                                         hprt0.b.prtsusp = 1;
2442                                         hprt0.b.prtres = 0;
2443                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2444
2445                                         /* 15 second delay per the test spec */
2446                                         mdelay(15000);
2447
2448                                         /* Drive resume on the root port */
2449                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2450                                         hprt0.b.prtsusp = 0;
2451                                         hprt0.b.prtres = 1;
2452                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2453                                         mdelay(100);
2454
2455                                         /* Clear the resume bit */
2456                                         hprt0.b.prtres = 0;
2457                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2458
2459                                         /* Restore interrupts */
2460                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2461                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2462                                         /* Save current interrupt mask */
2463                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2464
2465                                         /* Disable all interrupts while we muck with
2466                                          * the hardware directly
2467                                          */
2468                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2469
2470                                         /* 15 second delay per the test spec */
2471                                         mdelay(15000);
2472
2473                                         /* Send the Setup packet */
2474                                         do_setup();
2475
2476                                         /* 15 second delay so nothing else happens for awhile */
2477                                         mdelay(15000);
2478
2479                                         /* Restore interrupts */
2480                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2481                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2482                                         /* Save current interrupt mask */
2483                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2484
2485                                         /* Disable all interrupts while we muck with
2486                                          * the hardware directly
2487                                          */
2488                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2489
2490                                         /* Send the Setup packet */
2491                                         do_setup();
2492
2493                                         /* 15 second delay so nothing else happens for awhile */
2494                                         mdelay(15000);
2495
2496                                         /* Send the In and Ack packets */
2497                                         do_in_ack();
2498
2499                                         /* 15 second delay so nothing else happens for awhile */
2500                                         mdelay(15000);
2501
2502                                         /* Restore interrupts */
2503                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2504                                 }
2505                         }
2506                         break;
2507                 }
2508 #endif /* DWC_HS_ELECT_TST */
2509
2510                 case USB_PORT_FEAT_INDICATOR:
2511                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2512                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2513                         /* Not supported */
2514                         break;
2515                 default:
2516                         retval = -EINVAL;
2517                         DWC_ERROR ("DWC OTG HCD - "
2518                                    "SetPortFeature request %xh "
2519                                    "unknown or unsupported\n", _wValue);
2520                         break;
2521                 }
2522                 break;
2523         default:
2524         error:
2525                 retval = -EINVAL;
2526                 DWC_WARN ("DWC OTG HCD - "
2527                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2528                           _typeReq, _wIndex, _wValue);
2529                 break;
2530         }
2531
2532         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2533         return retval;
2534 }
2535
2536
2537 /**
2538  * Assigns transactions from a QTD to a free host channel and initializes the
2539  * host channel to perform the transactions. The host channel is removed from
2540  * the free list.
2541  *
2542  * @param _hcd The HCD state structure.
2543  * @param _qh Transactions from the first QTD for this QH are selected and
2544  * assigned to a free host channel.
2545  */
2546 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2547 {
2548         dwc_hc_t        *hc;
2549         dwc_otg_qtd_t   *qtd;
2550         struct urb      *urb;
2551
2552         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2553         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2554
2555         /* Remove the host channel from the free list. */
2556         list_del_init(&hc->hc_list_entry);
2557
2558         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2559         urb = qtd->urb;
2560         _qh->channel = hc;
2561         _qh->qtd_in_process = qtd;
2562
2563         /*
2564          * Use usb_pipedevice to determine device address. This address is
2565          * 0 before the SET_ADDRESS command and the correct address afterward.
2566          */
2567         hc->dev_addr = usb_pipedevice(urb->pipe);
2568         hc->ep_num = usb_pipeendpoint(urb->pipe);
2569
2570         if (urb->dev->speed == USB_SPEED_LOW) {
2571                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2572                 /*
2573                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2574                  * device connected.
2575                  */
2576         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2577         } else if (urb->dev->speed == USB_SPEED_FULL) {
2578                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2579                 /*
2580                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2581                  * device connected. warning: only support 1 device at root hub.
2582                  */
2583         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2584         } else {
2585                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2586         }
2587
2588         hc->max_packet = dwc_max_packet(_qh->maxp);
2589
2590         hc->xfer_started = 0;
2591         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2592         hc->error_state = (qtd->error_count > 0);
2593         hc->halt_on_queue = 0;
2594         hc->halt_pending = 0;
2595         hc->requests = 0;
2596
2597         /*
2598          * The following values may be modified in the transfer type section
2599          * below. The xfer_len value may be reduced when the transfer is
2600          * started to accommodate the max widths of the XferSize and PktCnt
2601          * fields in the HCTSIZn register.
2602          */
2603         hc->do_ping = _qh->ping_state;
2604         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2605         hc->data_pid_start = _qh->data_toggle;
2606         hc->multi_count = 1;
2607
2608         if (_hcd->core_if->dma_enable) {
2609                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2610         } else {
2611                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2612         }
2613         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2614         hc->xfer_count = 0;
2615
2616         /*
2617          * Set the split attributes
2618          */
2619         hc->do_split = 0;
2620         if (_qh->do_split) {
2621                 hc->do_split = 1;
2622                 hc->xact_pos = qtd->isoc_split_pos;
2623                 hc->complete_split = qtd->complete_split;
2624                 hc->hub_addr = urb->dev->tt->hub->devnum;
2625                 hc->port_addr = urb->dev->ttport;
2626         }
2627
2628         switch (usb_pipetype(urb->pipe)) {
2629         case PIPE_CONTROL:
2630                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2631                 switch (qtd->control_phase) {
2632                 case DWC_OTG_CONTROL_SETUP:
2633                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2634                         hc->do_ping = 0;
2635                         hc->ep_is_in = 0;
2636                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2637                         if (_hcd->core_if->dma_enable) {
2638                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2639                         } else {
2640                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2641                         }
2642                         hc->xfer_len = 8;
2643                         break;
2644                 case DWC_OTG_CONTROL_DATA:
2645                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2646                         hc->data_pid_start = qtd->data_toggle;
2647                         break;
2648                 case DWC_OTG_CONTROL_STATUS:
2649                         /*
2650                          * Direction is opposite of data direction or IN if no
2651                          * data.
2652                          */
2653                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2654                         if (urb->transfer_buffer_length == 0) {
2655                                 hc->ep_is_in = 1;
2656                         } else {
2657                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2658                         }
2659                         if (hc->ep_is_in) {
2660                                 hc->do_ping = 0;
2661                         }
2662                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2663                         hc->xfer_len = 0;
2664                         if (_hcd->core_if->dma_enable) {
2665                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2666                         } else {
2667                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2668                         }
2669                         break;
2670                 }
2671                 break;
2672         case PIPE_BULK:
2673                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2674                 break;
2675         case PIPE_INTERRUPT:
2676                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2677                 break;
2678         case PIPE_ISOCHRONOUS:
2679                 {
2680                         struct usb_iso_packet_descriptor *frame_desc;
2681                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2682                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2683                         if (_hcd->core_if->dma_enable) {
2684                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2685                         } else {
2686                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2687                         }
2688                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2689                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2690
2691                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2692                                 if (hc->xfer_len <= 188) {
2693                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2694                                 }
2695                                 else {
2696                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2697                                 }
2698                         }
2699                 }
2700                 break;
2701         }
2702
2703         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2704             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2705                 /*
2706                  * This value may be modified when the transfer is started to
2707                  * reflect the actual transfer length.
2708                  */
2709                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2710         }
2711
2712         dwc_otg_hc_init(_hcd->core_if, hc);
2713         hc->qh = _qh;
2714 }
2715
2716 /**
2717  * This function selects transactions from the HCD transfer schedule and
2718  * assigns them to available host channels. It is called from HCD interrupt
2719  * handler functions.
2720  *
2721  * @param _hcd The HCD state structure.
2722  *
2723  * @return The types of new transactions that were assigned to host channels.
2724  */
2725 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2726 {
2727         struct list_head                *qh_ptr;
2728         dwc_otg_qh_t                    *qh;
2729         int                             num_channels;
2730         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2731
2732 #ifdef DEBUG_SOF
2733         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2734 #endif
2735
2736         /* Process entries in the periodic ready list. */
2737         qh_ptr = _hcd->periodic_sched_ready.next;
2738         while (qh_ptr != &_hcd->periodic_sched_ready &&
2739                !list_empty(&_hcd->free_hc_list)) {
2740
2741                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2742                 assign_and_init_hc(_hcd, qh);
2743
2744                 /*
2745                  * Move the QH from the periodic ready schedule to the
2746                  * periodic assigned schedule.
2747                  */
2748                 qh_ptr = qh_ptr->next;
2749                 list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2750
2751                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2752         }
2753
2754         /*
2755          * Process entries in the inactive portion of the non-periodic
2756          * schedule. Some free host channels may not be used if they are
2757          * reserved for periodic transfers.
2758          */
2759         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2760         num_channels = _hcd->core_if->core_params->host_channels;
2761         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2762                 /*yk@rk 20100714
2763                (_hcd->non_periodic_channels <
2764                 num_channels - _hcd->periodic_channels) &&
2765                 */
2766                !list_empty(&_hcd->free_hc_list)) {
2767
2768                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2769                 assign_and_init_hc(_hcd, qh);
2770
2771                 /*
2772                  * Move the QH from the non-periodic inactive schedule to the
2773                  * non-periodic active schedule.
2774                  */
2775                 qh_ptr = qh_ptr->next;
2776                 list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2777
2778                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2779                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2780                 } else {
2781                         ret_val = DWC_OTG_TRANSACTION_ALL;
2782                 }
2783
2784                 _hcd->non_periodic_channels++;
2785         }
2786
2787         return ret_val;
2788 }
2789
2790 /**
2791  * Attempts to queue a single transaction request for a host channel
2792  * associated with either a periodic or non-periodic transfer. This function
2793  * assumes that there is space available in the appropriate request queue. For
2794  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2795  * is available in the appropriate Tx FIFO.
2796  *
2797  * @param _hcd The HCD state structure.
2798  * @param _hc Host channel descriptor associated with either a periodic or
2799  * non-periodic transfer.
2800  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2801  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2802  * transfers.
2803  *
2804  * @return 1 if a request is queued and more requests may be needed to
2805  * complete the transfer, 0 if no more requests are required for this
2806  * transfer, -1 if there is insufficient space in the Tx FIFO.
2807  */
2808 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2809                              dwc_hc_t *_hc,
2810                              uint16_t _fifo_dwords_avail)
2811 {
2812         int retval;
2813
2814         if (_hcd->core_if->dma_enable) {
2815                 if (!_hc->xfer_started) {
2816                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2817                         _hc->qh->ping_state = 0;
2818                 }
2819                 retval = 0;
2820         } else  if (_hc->halt_pending) {
2821                 /* Don't queue a request if the channel has been halted. */
2822                 retval = 0;
2823         } else if (_hc->halt_on_queue) {
2824                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
2825                 retval = 0;
2826         } else if (_hc->do_ping) {
2827                 if (!_hc->xfer_started) {
2828                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2829                 }
2830                 retval = 0;
2831         } else if (!_hc->ep_is_in ||
2832                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
2833                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
2834                         if (!_hc->xfer_started) {
2835                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2836                                 retval = 1;
2837                         } else {
2838                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2839                         }
2840                 } else {
2841                         retval = -1;
2842                 }
2843         } else {
2844                 if (!_hc->xfer_started) {
2845                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2846                         retval = 1;
2847                 } else {
2848                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
2849                 }
2850         }
2851
2852         return retval;
2853 }
2854
2855 /**
2856  * Processes active non-periodic channels and queues transactions for these
2857  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2858  * FIFO Empty interrupt is enabled if there are more transactions to queue as
2859  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2860  * FIFO Empty interrupt is disabled.
2861  */
2862 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
2863 {
2864         gnptxsts_data_t         tx_status;
2865         struct list_head        *orig_qh_ptr;
2866         dwc_otg_qh_t            *qh;
2867         int                     status;
2868         int                     no_queue_space = 0;
2869         int                     no_fifo_space = 0;
2870         int                     more_to_do = 0;
2871
2872         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
2873
2874         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
2875 #ifdef DEBUG
2876         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2877         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
2878                     tx_status.b.nptxqspcavail);
2879         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
2880                     tx_status.b.nptxfspcavail);
2881 #endif
2882         /*
2883          * Keep track of the starting point. Skip over the start-of-list
2884          * entry.
2885          */
2886         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
2887                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
2888         }
2889         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
2890
2891         /*
2892          * Process once through the active list or until no more space is
2893          * available in the request queue or the Tx FIFO.
2894          */
2895         do {
2896                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2897                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
2898                         no_queue_space = 1;
2899                         break;
2900                 }
2901
2902                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
2903                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
2904
2905                 if (status > 0) {
2906                         more_to_do = 1;
2907                 } else if (status < 0) {
2908                         no_fifo_space = 1;
2909                         break;
2910                 }
2911
2912                 /* Advance to next QH, skipping start-of-list entry. */
2913                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
2914                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
2915                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
2916                 }
2917
2918         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
2919
2920         if (!_hcd->core_if->dma_enable) {
2921                 gintmsk_data_t intr_mask = {.d32 = 0};
2922                 intr_mask.b.nptxfempty = 1;
2923
2924 #ifdef DEBUG
2925                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
2926                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
2927                             tx_status.b.nptxqspcavail);
2928                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
2929                             tx_status.b.nptxfspcavail);
2930 #endif
2931                 if (more_to_do || no_queue_space || no_fifo_space) {
2932                         /*
2933                          * May need to queue more transactions as the request
2934                          * queue or Tx FIFO empties. Enable the non-periodic
2935                          * Tx FIFO empty interrupt. (Always use the half-empty
2936                          * level to ensure that new requests are loaded as
2937                          * soon as possible.)
2938                          */
2939                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
2940                 } else {
2941                         /*
2942                          * Disable the Tx FIFO empty interrupt since there are
2943                          * no more transactions that need to be queued right
2944                          * now. This function is called from interrupt
2945                          * handlers to queue more transactions as transfer
2946                          * states change.
2947                          */
2948                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
2949                 }
2950         }
2951 }
2952
2953 /**
2954  * Processes periodic channels for the next frame and queues transactions for
2955  * these channels to the DWC_otg controller. After queueing transactions, the
2956  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2957  * to queue as Periodic Tx FIFO or request queue space becomes available.
2958  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2959  */
2960 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
2961 {
2962         hptxsts_data_t          tx_status;
2963         struct list_head        *qh_ptr;
2964         dwc_otg_qh_t            *qh;
2965         int                     status;
2966         int                     no_queue_space = 0;
2967         int                     no_fifo_space = 0;
2968
2969         dwc_otg_host_global_regs_t *host_regs;
2970         host_regs = _hcd->core_if->host_if->host_global_regs;
2971
2972         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
2973 #ifdef DEBUG
2974         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
2975         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
2976                     tx_status.b.ptxqspcavail);
2977         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
2978                     tx_status.b.ptxfspcavail);
2979 #endif
2980
2981         qh_ptr = _hcd->periodic_sched_assigned.next;
2982         while (qh_ptr != &_hcd->periodic_sched_assigned) {
2983                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
2984                 if (tx_status.b.ptxqspcavail == 0) {
2985                         no_queue_space = 1;
2986                         break;
2987                 }
2988
2989                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2990
2991                 /*
2992                  * Set a flag if we're queuing high-bandwidth in slave mode.
2993                  * The flag prevents any halts to get into the request queue in
2994                  * the middle of multiple high-bandwidth packets getting queued.
2995                  */
2996                 if ((!_hcd->core_if->dma_enable) &&
2997                     (qh->channel->multi_count > 1))
2998                 {
2999                         _hcd->core_if->queuing_high_bandwidth = 1;
3000                 }
3001
3002                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3003                 if (status < 0) {
3004                         no_fifo_space = 1;
3005                         break;
3006                 }
3007
3008                 /*
3009                  * In Slave mode, stay on the current transfer until there is
3010                  * nothing more to do or the high-bandwidth request count is
3011                  * reached. In DMA mode, only need to queue one request. The
3012                  * controller automatically handles multiple packets for
3013                  * high-bandwidth transfers.
3014                  */
3015                 if (_hcd->core_if->dma_enable ||
3016                     (status == 0 ||
3017                      qh->channel->requests == qh->channel->multi_count)) {
3018                         qh_ptr = qh_ptr->next;
3019                         /*
3020                          * Move the QH from the periodic assigned schedule to
3021                          * the periodic queued schedule.
3022                          */
3023                         list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3024
3025                         /* done queuing high bandwidth */
3026                         _hcd->core_if->queuing_high_bandwidth = 0;
3027                 }
3028         }
3029
3030         if (!_hcd->core_if->dma_enable) {
3031                 dwc_otg_core_global_regs_t *global_regs;
3032                 gintmsk_data_t intr_mask = {.d32 = 0};
3033
3034                 global_regs = _hcd->core_if->core_global_regs;
3035                 intr_mask.b.ptxfempty = 1;
3036 #ifdef DEBUG
3037                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3038                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3039                             tx_status.b.ptxqspcavail);
3040                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3041                             tx_status.b.ptxfspcavail);
3042 #endif
3043                 if (!(list_empty(&_hcd->periodic_sched_assigned)) ||
3044                     no_queue_space || no_fifo_space) {
3045                         /*
3046                          * May need to queue more transactions as the request
3047                          * queue or Tx FIFO empties. Enable the periodic Tx
3048                          * FIFO empty interrupt. (Always use the half-empty
3049                          * level to ensure that new requests are loaded as
3050                          * soon as possible.)
3051                          */
3052                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3053                 } else {
3054                         /*
3055                          * Disable the Tx FIFO empty interrupt since there are
3056                          * no more transactions that need to be queued right
3057                          * now. This function is called from interrupt
3058                          * handlers to queue more transactions as transfer
3059                          * states change.
3060                          */
3061                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3062                 }
3063         }
3064 }
3065
3066 /**
3067  * This function processes the currently active host channels and queues
3068  * transactions for these channels to the DWC_otg controller. It is called
3069  * from HCD interrupt handler functions.
3070  *
3071  * @param _hcd The HCD state structure.
3072  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3073  * periodic, or both).
3074  */
3075 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3076                                     dwc_otg_transaction_type_e _tr_type)
3077 {
3078 #ifdef DEBUG_SOF
3079         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3080 #endif
3081         /* Process host channels associated with periodic transfers. */
3082         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3083              _tr_type == DWC_OTG_TRANSACTION_ALL) &&
3084             !list_empty(&_hcd->periodic_sched_assigned)) {
3085
3086                 process_periodic_channels(_hcd);
3087         }
3088
3089         /* Process host channels associated with non-periodic transfers. */
3090         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3091              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3092                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3093                         process_non_periodic_channels(_hcd);
3094                 } else {
3095                         /*
3096                          * Ensure NP Tx FIFO empty interrupt is disabled when
3097                          * there are no non-periodic transfers to process.
3098                          */
3099                         gintmsk_data_t gintmsk = {.d32 = 0};
3100                         gintmsk.b.nptxfempty = 1;
3101                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3102                                          gintmsk.d32, 0);
3103                 }
3104         }
3105 }
3106
3107 /**
3108  * Sets the final status of an URB and returns it to the device driver. Any
3109  * required cleanup of the URB is performed.
3110  */
3111 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3112                               int _status)
3113 __releases(_hcd->lock)
3114 __acquires(_hcd->lock)
3115 {
3116
3117 #ifdef DEBUG
3118         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3119                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3120                           __func__, _urb, usb_pipedevice(_urb->pipe),
3121                           usb_pipeendpoint(_urb->pipe),
3122                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3123                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3124                         int i;
3125                         for (i = 0; i < _urb->number_of_packets; i++) {
3126                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3127                                           i, _urb->iso_frame_desc[i].status);
3128                         }
3129                 }
3130         }
3131 #endif
3132
3133
3134         _urb->hcpriv = NULL;
3135         usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb);
3136         spin_unlock(&_hcd->lock);
3137         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3138         spin_lock(&_hcd->lock);
3139 }
3140
3141
3142 /*
3143  * Returns the Queue Head for an URB.
3144  */
3145 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3146 {
3147         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3148         return (dwc_otg_qh_t *) ep->hcpriv;
3149 }
3150
3151 #ifdef DEBUG
3152 void dwc_print_setup_data (uint8_t *setup)
3153 {
3154         int i;
3155         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3156                 DWC_PRINT("Setup Data = MSB ");
3157                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3158                 DWC_PRINT("\n");
3159                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3160                 DWC_PRINT("  bmRequestType Type = ");
3161                 switch ((setup[0]&0x60) >> 5) {
3162                 case 0: DWC_PRINT("Standard\n"); break;
3163                 case 1: DWC_PRINT("Class\n"); break;
3164                 case 2: DWC_PRINT("Vendor\n"); break;
3165                 case 3: DWC_PRINT("Reserved\n"); break;
3166                 }
3167                 DWC_PRINT("  bmRequestType Recipient = ");
3168                 switch (setup[0]&0x1f) {
3169                 case 0: DWC_PRINT("Device\n"); break;
3170                 case 1: DWC_PRINT("Interface\n"); break;
3171                 case 2: DWC_PRINT("Endpoint\n"); break;
3172                 case 3: DWC_PRINT("Other\n"); break;
3173                 default: DWC_PRINT("Reserved\n"); break;
3174                 }
3175                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3176                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3177                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3178                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3179         }
3180 }
3181 #endif
3182
3183 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3184 #if 0
3185         DWC_PRINT("Frame remaining at SOF:\n");
3186         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3187                   _hcd->frrem_samples, _hcd->frrem_accum,
3188                   (_hcd->frrem_samples > 0) ?
3189                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3190
3191         DWC_PRINT("\n");
3192         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3193         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3194                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3195                   (_hcd->core_if->hfnum_7_samples > 0) ?
3196                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3197         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3198         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3199                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3200                   (_hcd->core_if->hfnum_0_samples > 0) ?
3201                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3202         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3203         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3204                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3205                   (_hcd->core_if->hfnum_other_samples > 0) ?
3206                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3207
3208         DWC_PRINT("\n");
3209         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3210         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3211                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3212                   (_hcd->hfnum_7_samples_a > 0) ?
3213                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3214         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3215         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3216                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3217                   (_hcd->hfnum_0_samples_a > 0) ?
3218                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3219         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3220         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3221                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3222                   (_hcd->hfnum_other_samples_a > 0) ?
3223                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3224
3225         DWC_PRINT("\n");
3226         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3227         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3228                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3229                   (_hcd->hfnum_7_samples_b > 0) ?
3230                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3231         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3232         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3233                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3234                   (_hcd->hfnum_0_samples_b > 0) ?
3235                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3236         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3237         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3238                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3239                   (_hcd->hfnum_other_samples_b > 0) ?
3240                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3241 #endif
3242 }
3243
3244 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3245 {
3246 #ifdef DEBUG
3247         int num_channels;
3248         int i;
3249         gnptxsts_data_t np_tx_status;
3250         hptxsts_data_t p_tx_status;
3251
3252         num_channels = _hcd->core_if->core_params->host_channels;
3253         DWC_PRINT("\n");
3254         DWC_PRINT("************************************************************\n");
3255         DWC_PRINT("HCD State:\n");
3256         DWC_PRINT("  Num channels: %d\n", num_channels);
3257         for (i = 0; i < num_channels; i++) {
3258                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3259                 DWC_PRINT("  Channel %d:\n", i);
3260                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3261                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3262                 DWC_PRINT("    speed: %d\n", hc->speed);
3263                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3264                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3265                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3266                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3267                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3268                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3269                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3270                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3271                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3272                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3273                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3274                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3275                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3276                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3277                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3278                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3279                 DWC_PRINT("    requests: %d\n", hc->requests);
3280                 DWC_PRINT("    qh: %p\n", hc->qh);
3281                 if (hc->xfer_started) {
3282                         hfnum_data_t hfnum;
3283                         hcchar_data_t hcchar;
3284                         hctsiz_data_t hctsiz;
3285                         hcint_data_t hcint;
3286                         hcintmsk_data_t hcintmsk;
3287                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3288                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3289                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3290                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3291                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3292                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3293                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3294                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3295                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3296                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3297                 }
3298                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3299                         dwc_otg_qtd_t *qtd;
3300                         struct urb *urb;
3301                         qtd = hc->qh->qtd_in_process;
3302                         urb = qtd->urb;
3303                         DWC_PRINT("    URB Info:\n");
3304                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3305                         if (urb != NULL) {
3306                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3307                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3308                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3309                                 DWC_PRINT("      Max packet size: %d\n",
3310                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3311                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3312                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3313                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3314                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3315                         }
3316                 }
3317         }
3318         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3319         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3320         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3321         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3322         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3323         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3324         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3325         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3326         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3327         dwc_otg_hcd_dump_frrem(_hcd);
3328         dwc_otg_dump_global_registers(_hcd->core_if);
3329         dwc_otg_dump_host_registers(_hcd->core_if);
3330         DWC_PRINT("************************************************************\n");
3331         DWC_PRINT("\n");
3332 #endif
3333 }
3334 #endif /* DWC_DEVICE_ONLY */