drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/clk.h>
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/init.h>
  46 #include <linux/device.h>
  47 #include <linux/errno.h>
  48 #include <linux/list.h>
  49 #include <linux/interrupt.h>
  50 #include <linux/string.h>
  51 #include <linux/dma-mapping.h>
  52 #include <linux/irq.h>
  53 #include <linux/platform_device.h>
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65
  66     if(core_if->op_state == B_PERIPHERAL)
  67     {
  68         DWC_PRINT("%s, usb device mode\n", __func__);
  69         return 0;
  70     }
  71     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  72     if((!dwc_otg_hcd->host_enabled)||(!hprt0.b.prtena))
  73         return 0;
  74     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  75     if(hprt0.b.prtconnsts)  // usb device connected
  76     {
  77         //partial power-down
  78         if(!hprt0.b.prtsusp)
  79         {
  80             //hprt0.d32 = 0;
  81             hprt0.b.prtsusp = 1;
  82             hprt0.b.prtena = 0;
  83             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  84         }
  85         udelay(10);
  86         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  87         if(!hprt0.b.prtsusp)
  88         {
  89             //hprt0.d32 = 0;
  90             hprt0.b.prtsusp = 1;
  91             hprt0.b.prtena = 0;
  92             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  93         }
  94         mdelay(5);
  95         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
  96         pcgcctl.b.pwrclmp = 1;//power clamp
  97         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
  98         udelay(1);
  99         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
 100         pcgcctl.b.stoppclk = 1;//stop phy clk
 101         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 102     }
 103     else    //no device connect
 104     {
 105         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 106                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 0);
 107         }
 108     }
 109     udelay(3);
 110     #ifndef CONFIG_DWC_REMOTE_WAKEUP
 111     clk_disable(core_if->otg_dev->phyclk);
 112     clk_disable(core_if->otg_dev->ahbclk);
 113     #endif
 114     //power off
 115     return 0;
 116 }
 117
 118 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 119 {
 120     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 121     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 122     hprt0_data_t hprt0;
 123     pcgcctl_data_t pcgcctl;
 124     gintmsk_data_t gintmsk;
 125
 126     if(core_if->op_state == B_PERIPHERAL)
 127     {
 128         DWC_PRINT("%s, usb device mode\n", __func__);
 129         return 0;
 130     }
 131     if(!dwc_otg_hcd->host_enabled)
 132         return 0;
 133     #ifndef CONFIG_DWC_REMOTE_WAKEUP
 134     clk_enable(core_if->otg_dev->phyclk);
 135     clk_enable(core_if->otg_dev->ahbclk);
 136     #endif
 137     //partial power-down
 138     //power on
 139     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 140     pcgcctl.b.stoppclk = 0;//stop phy clk
 141     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 142     udelay(1);
 143     pcgcctl.b.pwrclmp = 0;//power clamp
 144     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 145     udelay(2);
 146
 147     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 148     gintmsk.b.portintr = 0;
 149     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 150
 151     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 152     if(!hprt0.b.prtena)
 153         return 0;
 154     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 155     if(hprt0.b.prtconnsts)
 156     {
 157         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 158         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 159         hprt0.b.prtpwr = 1;
 160         hprt0.b.prtres = 1;
 161         hprt0.b.prtena = 0;
 162         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 163         mdelay(20);
 164         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 165         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 166         //hprt0.d32 = 0;
 167         hprt0.b.prtpwr = 1;
 168         hprt0.b.prtres = 0;
 169         hprt0.b.prtena = 0;
 170         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 171         hprt0.d32 = 0;
 172         hprt0.b.prtpwr = 1;
 173         hprt0.b.prtena = 0;
 174         hprt0.b.prtconndet = 1;
 175         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 176
 177         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 178         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 179
 180         mdelay(10);
 181     }
 182     else
 183     {
 184         if (core_if->hcd_cb && core_if->hcd_cb->suspend) {
 185                 core_if->hcd_cb->suspend( core_if->hcd_cb->p, 1);
 186         }
 187     }
 188     gintmsk.b.portintr = 1;
 189     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 190
 191         return 0;
 192 }
 193
 194 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 195
 196 static const struct hc_driver dwc_otg_hc_driver = {
 197
 198         .description =          dwc_otg_hcd_name,
 199         .product_desc =         "DWC OTG Controller",
 200         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 201
 202         .irq =                  dwc_otg_hcd_irq,
 203
 204         .flags =                HCD_MEMORY | HCD_USB2,
 205
 206         //.reset =
 207         .start =                dwc_otg_hcd_start,
 208         //.suspend =
 209         //.resume =
 210
 211         /* yk@rk 20100625
 212          * core/hcd.c call hcd->driver->bus_suspend
 213          * otherwise system can not be suspended
 214          */
 215 #ifdef CONFIG_PM
 216         .bus_suspend =          dwc_otg_hcd_suspend,
 217         .bus_resume =           dwc_otg_hcd_resume,
 218 #endif
 219         .stop =                 dwc_otg_hcd_stop,
 220
 221         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 222         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 223         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 224
 225         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 226
 227         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 228         .hub_control =          dwc_otg_hcd_hub_control,
 229         //.hub_suspend =
 230         //.hub_resume =
 231 };
 232
 233 #ifdef CONFIG_USB11_HOST
 234 static const struct hc_driver host11_hc_driver = {
 235
 236         .description =          "host11_hcd",
 237         .product_desc =         "DWC OTG Controller",
 238         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 239
 240         .irq =                  dwc_otg_hcd_irq,
 241
 242         .flags =                HCD_MEMORY | HCD_USB2,
 243
 244         //.reset =
 245         .start =                dwc_otg_hcd_start,
 246         //.suspend =
 247         //.resume =
 248
 249         /* yk@rk 20100625
 250          * core/hcd.c call hcd->driver->bus_suspend
 251          * otherwise system can not be suspended
 252          */
 253 #ifdef CONFIG_PM
 254         .bus_suspend =          dwc_otg_hcd_suspend,
 255         .bus_resume =           dwc_otg_hcd_resume,
 256 #endif
 257         .stop =                 dwc_otg_hcd_stop,
 258
 259         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 260         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 261         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 262
 263         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 264
 265         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 266         .hub_control =          dwc_otg_hcd_hub_control,
 267         //.hub_suspend =
 268         //.hub_resume =
 269 };
 270 #endif
 271 #ifdef CONFIG_USB20_HOST
 272 static const struct hc_driver host20_hc_driver = {
 273
 274         .description =          "host20_hcd",
 275         .product_desc =         "DWC OTG Controller",
 276         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 277
 278         .irq =                  dwc_otg_hcd_irq,
 279
 280         .flags =                HCD_MEMORY | HCD_USB2,
 281
 282         //.reset =
 283         .start =                dwc_otg_hcd_start,
 284         //.suspend =
 285         //.resume =
 286
 287         /* yk@rk 20100625
 288          * core/hcd.c call hcd->driver->bus_suspend
 289          * otherwise system can not be suspended
 290          */
 291 #ifdef CONFIG_PM
 292         .bus_suspend =          dwc_otg_hcd_suspend,
 293         .bus_resume =           dwc_otg_hcd_resume,
 294 #endif
 295         .stop =                 dwc_otg_hcd_stop,
 296
 297         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 298         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 299         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 300
 301         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 302
 303         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 304         .hub_control =          dwc_otg_hcd_hub_control,
 305         //.hub_suspend =
 306         //.hub_resume =
 307 };
 308 #endif
 309
 310 /**
 311  * Work queue function for starting the HCD when A-Cable is connected.
 312  * The dwc_otg_hcd_start() must be called in a process context.
 313  */
 314 static void hcd_start_func(struct work_struct *work)
 315 {
 316     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 317     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 318
 319     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 320     if (hcd) {
 321             dwc_otg_hcd_start(hcd);
 322     }
 323 }
 324
 325 /**
 326  * HCD Callback function for starting the HCD when A-Cable is
 327  * connected.
 328  *
 329  * @param _p void pointer to the <code>struct usb_hcd</code>
 330  */
 331 static int32_t dwc_otg_hcd_start_cb(void *_p)
 332 {
 333         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 334         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 335         hprt0_data_t hprt0;
 336
 337         if (core_if->op_state == B_HOST) {
 338                 /*
 339                  * Reset the port.  During a HNP mode switch the reset
 340                  * needs to occur within 1ms and have a duration of at
 341                  * least 50ms.
 342                  */
 343                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 344                 hprt0.b.prtrst = 1;
 345                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 346                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 347         } else {
 348                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 349         }
 350
 351         /* Need to start the HCD in a non-interrupt context. */
 352 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 353         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 354         schedule_work(&dwc_otg_hcd->start_work);
 355
 356         return 1;
 357 }
 358
 359
 360 /**
 361  * HCD Callback function for stopping the HCD.
 362  *
 363  * @param _p void pointer to the <code>struct usb_hcd</code>
 364  */
 365 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 366 {
 367         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 368         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 369         dwc_otg_hcd_stop( usb_hcd );
 370         return 1;
 371 }
 372
 373 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 374 {
 375 #ifdef DEBUG
 376         int i;
 377         int num_channels = _hcd->core_if->core_params->host_channels;
 378         for (i = 0; i < num_channels; i++) {
 379                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 380         }
 381 #endif
 382 }
 383
 384 static void del_timers(dwc_otg_hcd_t *_hcd)
 385 {
 386         del_xfer_timers(_hcd);
 387         del_timer(&_hcd->conn_timer);
 388 }
 389
 390 /**
 391  * Processes all the URBs in a single list of QHs. Completes them with
 392  * -ETIMEDOUT and frees the QTD.
 393  */
 394 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 395 {
 396         struct list_head        *qh_item;
 397         dwc_otg_qh_t            *qh;
 398         struct list_head        *qtd_item;
 399         dwc_otg_qtd_t           *qtd;
 400         struct urb              *urb;
 401
 402         list_for_each(qh_item, _qh_list) {
 403                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 404                 for (qtd_item = qh->qtd_list.next;
 405                      qtd_item != &qh->qtd_list;
 406                      qtd_item = qh->qtd_list.next) {
 407                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 408                         if (qtd->urb != NULL) {
 409                         urb = qtd->urb;
 410                             // 20110415 yk
 411                             // urb will be re entry to ep->urb_list if use ETIMEOUT
 412                                 dwc_otg_hcd_complete_urb(_hcd, urb,
 413                                                          -ESHUTDOWN);//ETIMEDOUT,ENOENT
 414                         }
 415                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 416                 }
 417         }
 418 }
 419
 420 /**
 421  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 422  * and periodic schedules. The QTD associated with each URB is removed from
 423  * the schedule and freed. This function may be called when a disconnect is
 424  * detected or when the HCD is being stopped.
 425  */
 426 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 427 {
 428         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 429         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 430         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 431 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 432 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 433 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 434 }
 435 extern void release_channel(dwc_otg_hcd_t *_hcd,
 436                             dwc_hc_t *_hc,
 437                             dwc_otg_qtd_t *_qtd,
 438                             dwc_otg_halt_status_e _halt_status);
 439
 440 /**
 441  * HCD Callback function for disconnect of the HCD.
 442  *
 443  * @param _p void pointer to the <code>struct usb_hcd</code>
 444  */
 445 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 446 {
 447         gintsts_data_t  intr;
 448     dwc_otg_hcd_t       *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 449
 450     //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 451
 452     /*
 453      * Set status flags for the hub driver.
 454      */
 455     dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 456         dwc_otg_hcd->flags.b.port_connect_status = 0;
 457
 458     /*
 459      * Shutdown any transfers in process by clearing the Tx FIFO Empty
 460      * interrupt mask and status bits and disabling subsequent host
 461      * channel interrupts.
 462      */
 463     intr.d32 = 0;
 464     intr.b.nptxfempty = 1;
 465     intr.b.ptxfempty = 1;
 466         intr.b.hcintr = 1;
 467     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 468     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 469
 470 //      del_timers(dwc_otg_hcd);
 471
 472         /*
 473          * Turn off the vbus power only if the core has transitioned to device
 474          * mode. If still in host mode, need to keep power on to detect a
 475          * reconnection.
 476          */
 477         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 478                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 479                         hprt0_data_t hprt0 = { .d32=0 };
 480                         DWC_PRINT("Disconnect: PortPower off\n");
 481                         hprt0.b.prtpwr = 0;
 482                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 483                 }
 484
 485                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 486         }
 487
 488         spin_lock(&dwc_otg_hcd->global_lock);
 489         /* Respond with an error status to all URBs in the schedule. */
 490         kill_all_urbs(dwc_otg_hcd);
 491         spin_unlock(&dwc_otg_hcd->global_lock);
 492
 493         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 494                 /* Clean up any host channels that were in use. */
 495                 int                     num_channels;
 496                 int                     i;
 497                 dwc_hc_t                *channel;
 498                 dwc_otg_hc_regs_t       *hc_regs;
 499                 hcchar_data_t           hcchar;
 500
 501                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 502
 503                 if (!dwc_otg_hcd->core_if->dma_enable) {
 504                         /* Flush out any channel requests in slave mode. */
 505                         for (i = 0; i < num_channels; i++) {
 506                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 507                                 if (list_empty(&channel->hc_list_entry)) {
 508                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 509                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 510                                         if (hcchar.b.chen) {
 511                                                 hcchar.b.chen = 0;
 512                                                 hcchar.b.chdis = 1;
 513                                                 hcchar.b.epdir = 0;
 514                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 515                                         }
 516                                 }
 517                         }
 518                 }
 519
 520                 for (i = 0; i < num_channels; i++) {
 521                         channel = dwc_otg_hcd->hc_ptr_array[i];
 522                         if (list_empty(&channel->hc_list_entry)) {
 523                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 524                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 525                                 if (hcchar.b.chen) {
 526                                         /* Halt the channel. */
 527                                         hcchar.b.chdis = 1;
 528                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 529                                 }
 530 #if 1
 531                 release_channel(dwc_otg_hcd, channel, NULL, DWC_OTG_HC_XFER_URB_DEQUEUE);
 532 #else
 533                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 534                                 list_add_tail(&channel->hc_list_entry,
 535                                               &dwc_otg_hcd->free_hc_list);
 536 #endif
 537                         }
 538                 }
 539         }
 540
 541     /* A disconnect will end the session so the B-Device is no
 542      * longer a B-host. */
 543     ((struct usb_hcd *)_p)->self.is_b_host = 0;
 544     return 1;
 545 }
 546
 547 /**
 548  * Connection timeout function.  An OTG host is required to display a
 549  * message if the device does not connect within 10 seconds.
 550  */
 551 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 552 {
 553         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 554         DWC_PRINT( "Connect Timeout\n");
 555         DWC_ERROR( "Device Not Connected/Responding\n" );
 556 }
 557
 558 /**
 559  * Start the connection timer.  An OTG host is required to display a
 560  * message if the device does not connect within 10 seconds.  The
 561  * timer is deleted if a port connect interrupt occurs before the
 562  * timer expires.
 563  */
 564 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 565 {
 566     init_timer( &_hcd->conn_timer );
 567     _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 568     _hcd->conn_timer.data = (unsigned long)0;
 569     _hcd->conn_timer.expires = jiffies + (HZ*10);
 570     add_timer( &_hcd->conn_timer );
 571 }
 572
 573 /**
 574  * HCD Callback function for disconnect of the HCD.
 575  *
 576  * @param _p void pointer to the <code>struct usb_hcd</code>
 577  */
 578 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 579 {
 580         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 581         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 582 //        dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 583         return 1;
 584 }
 585
 586 /*
 587  * suspend: 0 usb phy enable
 588  *          1 usb phy suspend
 589  */
 590 static int32_t dwc_otg_phy_suspend_cb( void *_p, int suspend)
 591 {
 592 #ifdef CONFIG_ARCH_RK29
 593     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 594
 595     if(suspend) {
 596         *otg_phy_con1 |= (0x01<<2);
 597         *otg_phy_con1 |= (0x01<<3);    // exit suspend.
 598         *otg_phy_con1 &= ~(0x01<<2);
 599
 600         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 601     }
 602     else
 603     {
 604         *otg_phy_con1 |= (0x01<<2);
 605         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
 606         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 607     }
 608 #endif
 609 #ifdef CONFIG_ARCH_RK30
 610     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC0_CON2);
 611     if(suspend) {
 612         *otg_phy_con1 = ((0x01<<2)<<16);    // exit suspend.
 613         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 614     }
 615     else{
 616         *otg_phy_con1 = 0x554|(0xfff<<16);   // enter suspend.
 617         udelay(3);
 618         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 619     }
 620 #endif
 621     return suspend;
 622 }
 623
 624 /**
 625  * HCD Callback structure for handling mode switching.
 626  */
 627 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 628         .start = dwc_otg_hcd_start_cb,
 629         .stop = dwc_otg_hcd_stop_cb,
 630         .disconnect = dwc_otg_hcd_disconnect_cb,
 631         .session_start = dwc_otg_hcd_session_start_cb,
 632         .suspend = dwc_otg_phy_suspend_cb,
 633         .p = 0,//hcd
 634 };
 635
 636 /**
 637  * Reset tasklet function
 638  */
 639 static void reset_tasklet_func (unsigned long data)
 640 {
 641         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 642         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 643         hprt0_data_t hprt0;
 644
 645         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 646
 647         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 648         hprt0.b.prtrst = 1;
 649         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 650         mdelay (60);
 651
 652         hprt0.b.prtrst = 0;
 653         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 654         dwc_otg_hcd->flags.b.port_reset_change = 1;
 655
 656         return;
 657 }
 658
 659 static struct tasklet_struct reset_tasklet = {
 660         .next = NULL,
 661         .state = 0,
 662         .count = ATOMIC_INIT(0),
 663         .func = reset_tasklet_func,
 664         .data = 0,
 665 };
 666 #ifdef CONFIG_ARCH_RK30
 667 static void dwc_otg_hcd_enable(struct work_struct *work)
 668 {
 669     dwc_otg_hcd_t *dwc_otg_hcd;
 670     dwc_otg_core_if_t *_core_if;
 671
 672     dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, host_enable_work.work);
 673     _core_if = dwc_otg_hcd->core_if;
 674
 675         if(dwc_otg_hcd->host_enabled == dwc_otg_hcd->host_setenable){
 676 //        DWC_PRINT("%s, enable flag %d\n", __func__, dwc_otg_hcd->host_setenable);
 677             return;
 678         }
 679
 680         dwc_otg_hcd->host_enabled = dwc_otg_hcd->host_setenable;
 681         if(dwc_otg_hcd->host_setenable == 0)    // enable -> disable
 682         {
 683             DWC_PRINT("%s, disable host controller\n", __func__);
 684             #if 1
 685         if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
 686                 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
 687         }
 688         #endif
 689         if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
 690                 _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
 691         }
 692         if (_core_if->hcd_cb && _core_if->hcd_cb->suspend) {
 693                 _core_if->hcd_cb->suspend( _core_if->hcd_cb->p, 0);
 694         }
 695         udelay(3);
 696 //        clk_disable(otg_dev->phyclk);
 697 //        clk_disable(otg_dev->ahbclk);
 698         }
 699         else if(dwc_otg_hcd->host_setenable == 1)
 700         {
 701             DWC_PRINT("%s, enable host controller\n", __func__);
 702 //        clk_enable(otg_dev->phyclk);
 703 //        clk_enable(otg_dev->ahbclk);
 704         if (_core_if->hcd_cb && _core_if->hcd_cb->suspend) {
 705                 _core_if->hcd_cb->suspend( _core_if->hcd_cb->p, 1);
 706         }
 707         mdelay(5);
 708         if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
 709                 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
 710         }
 711         }
 712
 713 }
 714 static void dwc_otg_hcd_connect_detect(unsigned long pdata)
 715 {
 716     dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)pdata;
 717     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 718     unsigned int usbgrf_status = *(unsigned int*)(USBGRF_SOC_STATUS0);
 719         unsigned long flags;
 720
 721         local_irq_save(flags);
 722
 723 //    DWC_PRINT("%s hprt %x, grfstatus 0x%x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
 724     if(usbgrf_status & (7<<22)){
 725     // usb device connected
 726         dwc_otg_hcd->host_setenable = 1;
 727     }
 728     else{
 729     // no device, suspend host
 730         if((dwc_read_reg32(core_if->host_if->hprt0) & 1) == 0)
 731             dwc_otg_hcd->host_setenable = 0;
 732
 733     }
 734     if(dwc_otg_hcd->host_setenable != dwc_otg_hcd->host_enabled){
 735     DWC_PRINT("%s schedule delaywork \n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
 736     schedule_delayed_work(&dwc_otg_hcd->host_enable_work, 8);
 737     }
 738 //    dwc_otg_hcd->connect_detect_timer.expires = jiffies + (HZ<<1); /* 1 s */
 739     mod_timer(&dwc_otg_hcd->connect_detect_timer,jiffies + (HZ<<1));
 740         local_irq_restore(flags);
 741         return;
 742 }
 743 #endif
 744 /**
 745  * Initializes the HCD. This function allocates memory for and initializes the
 746  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 747  * USB bus with the core and calls the hc_driver->start() function. It returns
 748  * a negative error on failure.
 749  */
 750 extern uint32_t g_dbg_lvl;
 751 int __devinit dwc_otg_hcd_init(struct device *dev)
 752 {
 753         struct usb_hcd *hcd = NULL;
 754         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 755     dwc_otg_device_t *otg_dev = dev->platform_data;
 756
 757         int             num_channels;
 758         int             i;
 759         dwc_hc_t        *channel;
 760
 761         int retval = 0;
 762 #if 1  //kaiker .these code must execute before usb_create_hcd
 763         /* Set device flags indicating whether the HCD supports DMA. */
 764         static u64 usb_dmamask = 0xffffffffUL;
 765         if (otg_dev->core_if->dma_enable) {
 766                 dev->dma_mask = &usb_dmamask;
 767                 dev->coherent_dma_mask = ~0;
 768         } else {
 769                 dev->dma_mask = (void *)0;
 770                 dev->coherent_dma_mask = 0;
 771         }
 772 #endif
 773 //      g_dbg_lvl = 0xff;
 774
 775         /*
 776          * Allocate memory for the base HCD plus the DWC OTG HCD.
 777          * Initialize the base HCD.
 778          */
 779         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 780         if (hcd == NULL) {
 781                 retval = -ENOMEM;
 782                 goto error1;
 783         }
 784         hcd->regs = otg_dev->base;
 785         hcd->self.otg_port = 1;
 786
 787         /* Initialize the DWC OTG HCD. */
 788         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 789
 790         spin_lock_init(&dwc_otg_hcd->global_lock);
 791
 792         dwc_otg_hcd->core_if = otg_dev->core_if;
 793         otg_dev->hcd = dwc_otg_hcd;
 794
 795 #ifdef CONFIG_USB20_OTG_EN
 796     dwc_otg_hcd->host_enabled = 1;
 797 #else
 798     dwc_otg_hcd->host_enabled = 0;
 799 #endif
 800
 801         /* Register the HCD CIL Callbacks */
 802         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 803                                            &hcd_cil_callbacks, hcd);
 804
 805         /* Initialize the non-periodic schedule. */
 806         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 807         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 808
 809         /* Initialize the periodic schedule. */
 810         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 811 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 812 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 813 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 814
 815         /*
 816          * Create a host channel descriptor for each host channel implemented
 817          * in the controller. Initialize the channel descriptor array.
 818          */
 819         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 820         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 821         for (i = 0; i < num_channels; i++) {
 822                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 823                 if (channel == NULL) {
 824                         retval = -ENOMEM;
 825                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 826                         goto error2;
 827                 }
 828                 memset(channel, 0, sizeof(dwc_hc_t));
 829                 channel->hc_num = i;
 830                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 831 #ifdef DEBUG
 832                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 833 #endif
 834
 835                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 836         }
 837
 838         /* Initialize the Connection timeout timer. */
 839 //        init_timer( &dwc_otg_hcd->conn_timer );
 840
 841         /* Initialize reset tasklet. */
 842         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 843         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 844         /*
 845          * Finish generic HCD initialization and start the HCD. This function
 846          * allocates the DMA buffer pool, registers the USB bus, requests the
 847          * IRQ line, and calls dwc_otg_hcd_start method.
 848          */
 849         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 850                                         IRQF_SHARED);
 851         if (retval < 0) {
 852                 DWC_ERROR("usb_add_hcd fail,everest\n");
 853                 goto error2;
 854         }
 855         /*
 856          * Allocate space for storing data on status transactions. Normally no
 857          * data is sent, but this space acts as a bit bucket. This must be
 858          * done after usb_add_hcd since that function allocates the DMA buffer
 859          * pool.
 860          */
 861         if (otg_dev->core_if->dma_enable) {
 862                 dwc_otg_hcd->status_buf =
 863                         dma_alloc_coherent(dev,
 864                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 865                                            &dwc_otg_hcd->status_buf_dma,
 866                                            GFP_KERNEL | GFP_DMA);
 867         } else {
 868                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 869                                                   GFP_KERNEL);
 870         }
 871         if (dwc_otg_hcd->status_buf == NULL) {
 872                 retval = -ENOMEM;
 873                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 874                 goto error3;
 875         }
 876
 877 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 878 //                  dev->bus_id, hcd->self.busnum);
 879
 880         return 0;
 881
 882         /* Error conditions */
 883  error3:
 884         usb_remove_hcd(hcd);
 885  error2:
 886         dwc_otg_hcd_free(hcd);
 887         usb_put_hcd(hcd);
 888
 889  error1:
 890         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 891         return retval;
 892 }
 893
 894 #ifdef CONFIG_USB11_HOST
 895 /*
 896  * suspend: 0 usb phy enable
 897  *          1 usb phy suspend
 898  */
 899 static int32_t host11_phy_suspend_cb( void *_p, int suspend)
 900 {
 901     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
 902
 903     if(suspend) {
 904         *otg_phy_con1 &= ~(0x01<<28);
 905         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
 906     }
 907     else
 908     {
 909         *otg_phy_con1 |= (0x01<<28);
 910         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
 911     }
 912
 913     return suspend;
 914 }
 915 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 916         .start = dwc_otg_hcd_start_cb,
 917         .stop = dwc_otg_hcd_stop_cb,
 918         .disconnect = dwc_otg_hcd_disconnect_cb,
 919         .session_start = dwc_otg_hcd_session_start_cb,
 920         .suspend = host11_phy_suspend_cb,
 921         .p = 0,//hcd
 922 };
 923
 924 static struct tasklet_struct host11_reset_tasklet = {
 925         .next = NULL,
 926         .state = 0,
 927         .count = ATOMIC_INIT(0),
 928         .func = reset_tasklet_func,
 929         .data = 0,
 930 };
 931
 932 int __devinit host11_hcd_init(struct device *dev)
 933 {
 934         struct usb_hcd *hcd = NULL;
 935         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 936     dwc_otg_device_t *otg_dev = dev->platform_data;
 937
 938         int             num_channels;
 939         int             i;
 940         dwc_hc_t        *channel;
 941
 942         int retval = 0;
 943 #if 1  //kaiker .these code must execute before usb_create_hcd
 944         /* Set device flags indicating whether the HCD supports DMA. */
 945         static u64 usb_dmamask = 0xffffffffUL;
 946         if (otg_dev->core_if->dma_enable) {
 947 //              DWC_PRINT("Using DMA mode\n");
 948                 dev->dma_mask = &usb_dmamask;
 949                 dev->coherent_dma_mask = ~0;
 950         } else {
 951 //              DWC_PRINT("Using Slave mode\n");
 952                 dev->dma_mask = (void *)0;
 953                 dev->coherent_dma_mask = 0;
 954         }
 955 #endif
 956 //      g_dbg_lvl = 0xff;
 957
 958         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 959
 960         /*
 961          * Allocate memory for the base HCD plus the DWC OTG HCD.
 962          * Initialize the base HCD.
 963          */
 964         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 965         if (hcd == NULL) {
 966                 retval = -ENOMEM;
 967                 goto error1;
 968         }
 969         hcd->regs = otg_dev->base;
 970         hcd->self.otg_port = 1;
 971
 972         /* Initialize the DWC OTG HCD. */
 973         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 974         dwc_otg_hcd->core_if = otg_dev->core_if;
 975         otg_dev->hcd = dwc_otg_hcd;
 976
 977 #ifdef CONFIG_USB11_HOST_EN
 978         dwc_otg_hcd->host_enabled = 1;
 979 #else
 980         dwc_otg_hcd->host_enabled = 0;
 981 #endif
 982
 983         spin_lock_init(&dwc_otg_hcd->global_lock);
 984
 985
 986         /* Register the HCD CIL Callbacks */
 987         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 988                                            &host11_cil_callbacks, hcd);
 989
 990         /* Initialize the non-periodic schedule. */
 991         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 992         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 993
 994         /* Initialize the periodic schedule. */
 995         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 996 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 997 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 998 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 999
1000         /*
1001          * Create a host channel descriptor for each host channel implemented
1002          * in the controller. Initialize the channel descriptor array.
1003          */
1004         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1005         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1006         for (i = 0; i < num_channels; i++) {
1007                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1008                 if (channel == NULL) {
1009                         retval = -ENOMEM;
1010                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1011                         goto error2;
1012                 }
1013                 memset(channel, 0, sizeof(dwc_hc_t));
1014                 channel->hc_num = i;
1015                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1016 #ifdef DEBUG
1017                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1018 #endif
1019
1020                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1021         }
1022
1023         /* Initialize the Connection timeout timer. */
1024 //        init_timer( &dwc_otg_hcd->conn_timer );
1025
1026         /* Initialize reset tasklet. */
1027         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1028         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
1029         /*
1030          * Finish generic HCD initialization and start the HCD. This function
1031          * allocates the DMA buffer pool, registers the USB bus, requests the
1032          * IRQ line, and calls dwc_otg_hcd_start method.
1033          */
1034         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1035                                         IRQF_SHARED);
1036         if (retval < 0) {
1037                 DWC_ERROR("usb_add_hcd fail,everest\n");
1038                 goto error2;
1039         }
1040         /*
1041          * Allocate space for storing data on status transactions. Normally no
1042          * data is sent, but this space acts as a bit bucket. This must be
1043          * done after usb_add_hcd since that function allocates the DMA buffer
1044          * pool.
1045          */
1046         if (otg_dev->core_if->dma_enable) {
1047                 dwc_otg_hcd->status_buf =
1048                         dma_alloc_coherent(dev,
1049                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1050                                            &dwc_otg_hcd->status_buf_dma,
1051                                            GFP_KERNEL | GFP_DMA);
1052         } else {
1053                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1054                                                   GFP_KERNEL);
1055         }
1056         if (dwc_otg_hcd->status_buf == NULL) {
1057                 retval = -ENOMEM;
1058                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1059                 goto error3;
1060         }
1061
1062         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
1063                     _lmdev->dev.bus_id, hcd->self.busnum);
1064
1065         return 0;
1066
1067         /* Error conditions */
1068  error3:
1069         usb_remove_hcd(hcd);
1070  error2:
1071         dwc_otg_hcd_free(hcd);
1072         usb_put_hcd(hcd);
1073
1074  error1:
1075         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1076         return retval;
1077 }
1078 #endif
1079 #ifdef CONFIG_USB20_HOST
1080
1081 /*
1082  * suspend: 0 usb phy enable
1083  *          1 usb phy suspend
1084  */
1085 static int32_t host20_phy_suspend_cb( void *_p, int suspend)
1086 {
1087 #ifdef CONFIG_ARCH_RK29
1088     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
1089     uint32_t regval;
1090
1091     regval = *otg_phy_con1;
1092
1093     if(suspend) {
1094         regval |= (0x01<<14);    // exit suspend.
1095         regval &= ~(0x01<<13);
1096
1097         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
1098     }
1099     else
1100     {
1101         regval &= ~(0x01<<14);    // exit suspend.
1102         regval |= (0x01<<13);    // software control
1103         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
1104     }
1105     *otg_phy_con1 = regval;
1106 #endif
1107
1108 #ifdef CONFIG_ARCH_RK30
1109     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON2);
1110     if(suspend) {
1111         *otg_phy_con1 = ((0x01<<2)<<16);    // exit suspend.
1112         DWC_DEBUGPL(DBG_PCDV, "enable usb phy\n");
1113     }
1114     else{
1115         *otg_phy_con1 = 0x554|(0xfff<<16);   // enter suspend.
1116         udelay(3);
1117         DWC_DEBUGPL(DBG_PCDV, "disable usb phy\n");
1118     }
1119 #endif
1120     return suspend;
1121 }
1122
1123 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1124         .start = dwc_otg_hcd_start_cb,
1125         .stop = dwc_otg_hcd_stop_cb,
1126         .disconnect = dwc_otg_hcd_disconnect_cb,
1127         .session_start = dwc_otg_hcd_session_start_cb,
1128         .suspend = host20_phy_suspend_cb,
1129         .p = 0,//hcd
1130 };
1131
1132 static struct tasklet_struct host20_reset_tasklet = {
1133         .next = NULL,
1134         .state = 0,
1135         .count = ATOMIC_INIT(0),
1136         .func = reset_tasklet_func,
1137         .data = 0,
1138 };
1139
1140 int __devinit host20_hcd_init(struct device *dev)
1141 {
1142         struct usb_hcd *hcd = NULL;
1143         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1144     dwc_otg_device_t *otg_dev = dev->platform_data;
1145
1146         int             num_channels;
1147         int             i;
1148         dwc_hc_t        *channel;
1149
1150         int retval = 0;
1151 #if 1  //kaiker .these code must execute before usb_create_hcd
1152         /* Set device flags indicating whether the HCD supports DMA. */
1153         static u64 usb_dmamask = 0xffffffffUL;
1154         if (otg_dev->core_if->dma_enable) {
1155 //              DWC_PRINT("Using DMA mode\n");
1156                 dev->dma_mask = &usb_dmamask;
1157                 dev->coherent_dma_mask = ~0;
1158         } else {
1159 //              DWC_PRINT("Using Slave mode\n");
1160                 dev->dma_mask = (void *)0;
1161                 dev->coherent_dma_mask = 0;
1162         }
1163 #endif
1164 //      g_dbg_lvl = 0xff;
1165
1166         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1167
1168         /*
1169          * Allocate memory for the base HCD plus the DWC OTG HCD.
1170          * Initialize the base HCD.
1171          */
1172         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1173         if (hcd == NULL) {
1174                 retval = -ENOMEM;
1175                 goto error1;
1176         }
1177         hcd->regs = otg_dev->base;
1178         hcd->self.otg_port = 1;
1179
1180         /* Initialize the DWC OTG HCD. */
1181         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1182         dwc_otg_hcd->core_if = otg_dev->core_if;
1183         otg_dev->hcd = dwc_otg_hcd;
1184
1185 #ifdef CONFIG_USB20_HOST_EN
1186         dwc_otg_hcd->host_enabled = 1;
1187 #else
1188         dwc_otg_hcd->host_enabled = 0;
1189 #endif
1190
1191         spin_lock_init(&dwc_otg_hcd->global_lock);
1192
1193         /* Register the HCD CIL Callbacks */
1194         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1195                                            &host20_cil_callbacks, hcd);
1196
1197         /* Initialize the non-periodic schedule. */
1198         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1199         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1200
1201         /* Initialize the periodic schedule. */
1202         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1203 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1204 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1205 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1206
1207         /*
1208          * Create a host channel descriptor for each host channel implemented
1209          * in the controller. Initialize the channel descriptor array.
1210          */
1211         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1212         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1213         for (i = 0; i < num_channels; i++) {
1214                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1215                 if (channel == NULL) {
1216                         retval = -ENOMEM;
1217                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1218                         goto error2;
1219                 }
1220                 memset(channel, 0, sizeof(dwc_hc_t));
1221                 channel->hc_num = i;
1222                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1223 #ifdef DEBUG
1224                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1225 #endif
1226
1227                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1228         }
1229
1230         /* Initialize the Connection timeout timer. */
1231         //init_timer( &dwc_otg_hcd->conn_timer );
1232
1233         /* Initialize reset tasklet. */
1234         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1235         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1236         /*
1237          * Finish generic HCD initialization and start the HCD. This function
1238          * allocates the DMA buffer pool, registers the USB bus, requests the
1239          * IRQ line, and calls dwc_otg_hcd_start method.
1240          */
1241         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1242                                         IRQF_SHARED);
1243         if (retval < 0) {
1244                 DWC_ERROR("usb_add_hcd fail,everest\n");
1245                 goto error2;
1246         }
1247         /*
1248          * Allocate space for storing data on status transactions. Normally no
1249          * data is sent, but this space acts as a bit bucket. This must be
1250          * done after usb_add_hcd since that function allocates the DMA buffer
1251          * pool.
1252          */
1253         if (otg_dev->core_if->dma_enable) {
1254                 dwc_otg_hcd->status_buf =
1255                         dma_alloc_coherent(dev,
1256                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1257                                            &dwc_otg_hcd->status_buf_dma,
1258                                            GFP_KERNEL | GFP_DMA);
1259         } else {
1260                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1261                                                   GFP_KERNEL);
1262         }
1263         if (dwc_otg_hcd->status_buf == NULL) {
1264                 retval = -ENOMEM;
1265                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1266                 goto error3;
1267         }
1268
1269 #ifdef CONFIG_ARCH_RK30
1270     dwc_otg_hcd->connect_detect_timer.function = dwc_otg_hcd_connect_detect;
1271     dwc_otg_hcd->connect_detect_timer.data = (unsigned long)(dwc_otg_hcd);
1272     init_timer( &dwc_otg_hcd->connect_detect_timer);
1273     mod_timer(&dwc_otg_hcd->connect_detect_timer, jiffies+(HZ<<3));
1274
1275     INIT_DELAYED_WORK(&dwc_otg_hcd->host_enable_work, dwc_otg_hcd_enable);
1276 #endif
1277         return 0;
1278
1279         /* Error conditions */
1280  error3:
1281         usb_remove_hcd(hcd);
1282  error2:
1283         dwc_otg_hcd_free(hcd);
1284         usb_put_hcd(hcd);
1285
1286  error1:
1287         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1288         return retval;
1289 }
1290 #endif
1291
1292
1293 /**
1294  * Removes the HCD.
1295  * Frees memory and resources associated with the HCD and deregisters the bus.
1296  */
1297 void dwc_otg_hcd_remove(struct device *dev)
1298 {
1299         dwc_otg_device_t *otg_dev = dev->platform_data;
1300     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1301         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1302
1303         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1304
1305         /* Turn off all interrupts */
1306         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1307         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1308
1309         usb_remove_hcd(hcd);
1310         dwc_otg_hcd_free(hcd);
1311         usb_put_hcd(hcd);
1312
1313         return;
1314 }
1315
1316
1317 /* =========================================================================
1318  *  Linux HC Driver Functions
1319  * ========================================================================= */
1320
1321 /**
1322  * Initializes dynamic portions of the DWC_otg HCD state.
1323  */
1324 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1325 {
1326         struct list_head        *item;
1327         int                     num_channels;
1328         int                     i;
1329         dwc_hc_t                *channel;
1330         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1331
1332         _hcd->flags.d32 = 0;
1333
1334         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1335         _hcd->non_periodic_channels = 0;
1336         _hcd->periodic_channels = 0;
1337
1338         /*
1339          * Put all channels in the free channel list and clean up channel
1340          * states.
1341          */
1342         item = _hcd->free_hc_list.next;
1343         while (item != &_hcd->free_hc_list) {
1344                 list_del(item);
1345                 item = _hcd->free_hc_list.next;
1346         }
1347         num_channels = _hcd->core_if->core_params->host_channels;
1348         for (i = 0; i < num_channels; i++) {
1349                 channel = _hcd->hc_ptr_array[i];
1350                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1351                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1352         }
1353
1354         /* Initialize the DWC core for host mode operation. */
1355         dwc_otg_core_host_init(_hcd->core_if);
1356 }
1357
1358 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1359  * mode operation. Activates the root port. Returns 0 on success and a negative
1360  * error code on failure. */
1361 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1362 {
1363     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1364     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1365         unsigned long flags;
1366
1367         struct usb_bus *bus;
1368
1369         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1370         local_irq_save(flags);
1371
1372         bus = hcd_to_bus(_hcd);
1373         _hcd->state = HC_STATE_RUNNING;
1374
1375         /* Initialize and connect root hub if one is not already attached */
1376         if (bus->root_hub) {
1377                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1378                 /* Inform the HUB driver to resume. */
1379                 usb_hcd_resume_root_hub(_hcd);
1380         }
1381         else {
1382             /*
1383              * no use
1384              * yk@rk 2010121
1385             struct usb_device *udev;6
1386                 udev = usb_alloc_dev(NULL, bus, 0);
1387                 udev->speed = USB_SPEED_HIGH;
1388                 if (!udev) {
1389                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1390                         return -ENODEV;
1391                 }
1392         */
1393             /* Not needed - VJ
1394                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1395                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1396                return -ENODEV;
1397                }
1398              */
1399         }
1400         /* Initialize the bus state.  If the core is in Device Mode
1401          * HALT the USB bus and return. */
1402         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1403                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1404                 //_hcd->state = HC_STATE_HALT;
1405                 goto out;
1406         }
1407         hcd_reinit(dwc_otg_hcd);
1408 out:
1409     local_irq_restore(flags);
1410
1411         return 0;
1412 }
1413
1414 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1415 {
1416         struct list_head        *item;
1417         dwc_otg_qh_t            *qh;
1418
1419         if (_qh_list->next == NULL) {
1420                 /* The list hasn't been initialized yet. */
1421                 return;
1422         }
1423
1424         /* Ensure there are no QTDs or URBs left. */
1425         kill_urbs_in_qh_list(_hcd, _qh_list);
1426
1427         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1428                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1429                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1430         }
1431 }
1432
1433 /**
1434  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1435  * stopped.
1436  */
1437 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1438 {
1439         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1440         hprt0_data_t hprt0 = { .d32=0 };
1441
1442         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1443
1444         /* Turn off all host-specific interrupts. */
1445         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1446
1447         /*
1448          * The root hub should be disconnected before this function is called.
1449          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1450          * and the QH lists (via ..._hcd_endpoint_disable).
1451          */
1452
1453         /* Turn off the vbus power */
1454         DWC_PRINT("PortPower off\n");
1455         hprt0.b.prtpwr = 0;
1456         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1457
1458         return;
1459 }
1460
1461
1462 /** Returns the current frame number. */
1463 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1464 {
1465         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1466         hfnum_data_t hfnum;
1467
1468         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1469                                    host_if->host_global_regs->hfnum);
1470
1471 #ifdef DEBUG_SOF
1472         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1473 #endif
1474         return hfnum.b.frnum;
1475 }
1476
1477 /**
1478  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1479  * in the struct usb_hcd field.
1480  */
1481 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1482 {
1483         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1484         int             i;
1485
1486         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1487
1488 //      del_timers(dwc_otg_hcd);
1489
1490         /* Free memory for QH/QTD lists */
1491         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1492         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1493         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1494 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1495 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1496 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1497
1498         /* Free memory for the host channels. */
1499         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1500                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1501                 if (hc != NULL) {
1502                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1503                         kfree(hc);
1504                 }
1505         }
1506
1507         if (dwc_otg_hcd->core_if->dma_enable) {
1508                 if (dwc_otg_hcd->status_buf_dma) {
1509                         dma_free_coherent(_hcd->self.controller,
1510                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1511                                           dwc_otg_hcd->status_buf,
1512                                           dwc_otg_hcd->status_buf_dma);
1513                 }
1514         } else if (dwc_otg_hcd->status_buf != NULL) {
1515                 kfree(dwc_otg_hcd->status_buf);
1516         }
1517
1518         return;
1519 }
1520
1521 #ifdef DEBUG
1522 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1523 {
1524         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1525         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1526                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1527         DWC_PRINT("  Endpoint type: %s\n",
1528                   ({char *pipetype;
1529                   switch (usb_pipetype(_urb->pipe)) {
1530                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1531                   case PIPE_BULK: pipetype = "BULK"; break;
1532                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1533                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1534                   default: pipetype = "UNKNOWN"; break;
1535                   }; pipetype;}));
1536         DWC_PRINT("  Speed: %s\n",
1537                   ({char *speed;
1538                   switch (_urb->dev->speed) {
1539                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1540                   case USB_SPEED_FULL: speed = "FULL"; break;
1541                   case USB_SPEED_LOW: speed = "LOW"; break;
1542                   default: speed = "UNKNOWN"; break;
1543                   }; speed;}));
1544         DWC_PRINT("  Max packet size: %d\n",
1545                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1546         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1547         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1548                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1549         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1550                   _urb->setup_packet, (void *)_urb->setup_dma);
1551         DWC_PRINT("  Interval: %d\n", _urb->interval);
1552         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1553                 int i;
1554                 for (i = 0; i < _urb->number_of_packets;  i++) {
1555                         DWC_PRINT("  ISO Desc %d:\n", i);
1556                         DWC_PRINT("    offset: %d, length %d\n",
1557                                   _urb->iso_frame_desc[i].offset,
1558                                   _urb->iso_frame_desc[i].length);
1559                 }
1560         }
1561 }
1562
1563 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1564                               dwc_otg_qh_t *qh)
1565 {
1566         if (qh->channel != NULL) {
1567                 dwc_hc_t *hc = qh->channel;
1568                 struct list_head *item;
1569                 dwc_otg_qh_t *qh_item;
1570                 int num_channels = _hcd->core_if->core_params->host_channels;
1571                 int i;
1572
1573                 dwc_otg_hc_regs_t *hc_regs;
1574                 hcchar_data_t   hcchar;
1575                 hcsplt_data_t   hcsplt;
1576                 hctsiz_data_t   hctsiz;
1577                 uint32_t        hcdma;
1578
1579                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1580                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1581                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1582                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1583                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1584
1585                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1586                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1587                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1588                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1589                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1590                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1591                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1592                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1593                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1594                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1595                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1596                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1597                 DWC_PRINT("    qh: %p\n", hc->qh);
1598                 DWC_PRINT("  NP inactive sched:\n");
1599                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1600                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1601                         DWC_PRINT("    %p\n", qh_item);
1602                 }
1603                 DWC_PRINT("  NP active sched:\n");
1604                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1605                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1606                         DWC_PRINT("    %p\n", qh_item);
1607                 }
1608                 DWC_PRINT("  Channels: \n");
1609                 for (i = 0; i < num_channels; i++) {
1610                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1611                         DWC_PRINT("    %2d: %p\n", i, hc);
1612                 }
1613         }
1614 }
1615 #endif
1616
1617 /** Starts processing a USB transfer request specified by a USB Request Block
1618  * (URB). mem_flags indicates the type of memory allocation to use while
1619  * processing this URB. */
1620 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1621                             struct urb *_urb,
1622                             gfp_t _mem_flags)
1623 {
1624         int retval;
1625         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1626         dwc_otg_qtd_t * qtd;
1627
1628     if(atomic_read(&_urb->use_count)>1){
1629         retval = -EPERM;
1630         dump_stack();
1631         DWC_PRINT("%s urb %p already in queue, qtd %p, count%d\n", __func__, _urb, _urb->hcpriv, atomic_read(&_urb->use_count));
1632         goto out;
1633     }
1634 #ifdef DEBUG
1635             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1636                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1637         }
1638 #endif  /*  */
1639     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1640                 DWC_ERROR("DWC OTG No longer connected\n");
1641             /* No longer connected. */
1642                 retval =  -ENODEV;
1643                 goto out;
1644         }
1645         qtd = dwc_otg_hcd_qtd_create(_urb);
1646         if (qtd == NULL) {
1647                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1648                 retval = -ENOMEM;
1649                 goto out;
1650         }
1651         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1652         if (retval < 0) {
1653                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1654                            "Error status %d\n", retval);
1655                 dwc_otg_hcd_qtd_free(qtd);
1656         }
1657 #if 1
1658         /*
1659          * Make sure the start of frame interrupt is enabled now that
1660          * we know we should have queued data. The SOF interrupt
1661          * handler automatically disables itself when idle to reduce
1662          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1663          * for the disable
1664          */
1665         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1666                          DWC_SOF_INTR_MASK);
1667 #endif
1668 out:
1669         return retval;
1670 }
1671
1672 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1673  * success.  */
1674 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1675 {
1676         unsigned long flags;
1677         dwc_otg_hcd_t * dwc_otg_hcd;
1678         dwc_otg_qtd_t * urb_qtd;
1679         dwc_otg_qh_t * qh;
1680         struct usb_host_endpoint *_ep;
1681
1682         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1683
1684         if(((uint32_t)_urb&0xf0000000)==0)
1685                 DWC_PRINT("%s urb is %p\n", __func__, _urb);
1686
1687     _ep = dwc_urb_to_endpoint(_urb);
1688         if(_ep==NULL)
1689         {
1690                 DWC_PRINT("%s=====================================================\n",__func__);
1691                 DWC_PRINT("urb->ep is null\n");
1692                 return -1;
1693         }
1694
1695         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1696         if(((uint32_t)urb_qtd&0xf0000000) == 0)
1697         {
1698                 DWC_PRINT("%s,urb_qtd is %p urb %p, count %d\n",__func__, urb_qtd, _urb, atomic_read(&_urb->use_count));
1699         if((atomic_read(&_urb->use_count)) == 0)
1700             return 0;
1701         else
1702                     return -1;
1703         }
1704         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1705         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1706         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1707
1708 #ifdef DEBUG
1709     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1710                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1711                 if (urb_qtd == qh->qtd_in_process) {
1712                         dump_channel_info(dwc_otg_hcd, qh);
1713                 }
1714         }
1715
1716 #endif  /*  */
1717
1718     if (urb_qtd == qh->qtd_in_process) {
1719             /* The QTD is in process (it has been assigned to a channel). */
1720             if (dwc_otg_hcd->flags.b.port_connect_status) {
1721                     /*
1722                      * If still connected (i.e. in host mode), halt the
1723                      * channel so it can be used for other transfers. If
1724                      * no longer connected, the host registers can't be
1725                      * written to halt the channel since the core is in
1726                      * device mode.
1727                      */
1728                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1729                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1730                 }
1731         }
1732
1733     /*
1734      * Free the QTD and clean up the associated QH. Leave the QH in the
1735      * schedule if it has any remaining QTDs.
1736      */
1737     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1738         if (urb_qtd == qh->qtd_in_process) {
1739                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1740                 qh->channel = NULL;
1741                 qh->qtd_in_process = NULL;
1742         } else if (list_empty(&qh->qtd_list)) {
1743                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1744         }
1745
1746         _urb->hcpriv = NULL;
1747         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1748     /* Higher layer software sets URB status. */
1749         usb_hcd_giveback_urb(_hcd, _urb, _status);
1750         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1751                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1752                 DWC_PRINT("  urb->status = %d\n", _status);
1753         }
1754         return 0;
1755 }
1756
1757
1758 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1759  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1760  * must already be dequeued. */
1761 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1762                                   struct usb_host_endpoint *_ep)
1763
1764 {
1765         unsigned long flags;
1766         dwc_otg_qh_t *qh;
1767         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1768
1769         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1770
1771         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1772                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1773                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1774
1775         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1776         if (qh != NULL) {
1777 #ifdef DEBUG
1778                 /** Check that the QTD list is really empty */
1779                 if (!list_empty(&qh->qtd_list)) {
1780                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1781                                  " QTD List for this endpoint is not empty\n");
1782                 }
1783 #endif
1784
1785                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1786                 _ep->hcpriv = NULL;
1787         }
1788
1789         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1790
1791         return;
1792 }
1793
1794 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1795  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1796  * interrupt.
1797  *
1798  * This function is called by the USB core when an interrupt occurs */
1799 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1800 {
1801         irqreturn_t result;
1802         unsigned long flags;
1803         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1804
1805         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1806
1807         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1808
1809         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1810
1811         return result;
1812 }
1813
1814 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1815  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1816  * is the status change indicator for the single root port. Returns 1 if either
1817  * change indicator is 1, otherwise returns 0. */
1818 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1819                                 char *_buf)
1820 {
1821         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1822
1823         _buf[0] = 0;
1824         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1825                     dwc_otg_hcd->flags.b.port_reset_change ||
1826                     dwc_otg_hcd->flags.b.port_enable_change ||
1827                     dwc_otg_hcd->flags.b.port_suspend_change ||
1828                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1829
1830 #ifdef DEBUG
1831         if (_buf[0]) {
1832                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1833                             " Root port status changed\n");
1834                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1835                             dwc_otg_hcd->flags.b.port_connect_status_change);
1836                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1837                             dwc_otg_hcd->flags.b.port_reset_change);
1838                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1839                             dwc_otg_hcd->flags.b.port_enable_change);
1840                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1841                             dwc_otg_hcd->flags.b.port_suspend_change);
1842                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1843                             dwc_otg_hcd->flags.b.port_over_current_change);
1844         }
1845 #endif
1846         return (_buf[0] != 0);
1847 }
1848
1849 #ifdef DWC_HS_ELECT_TST
1850 /*
1851  * Quick and dirty hack to implement the HS Electrical Test
1852  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1853  *
1854  * This code was copied from our userspace app "hset". It sends a
1855  * Get Device Descriptor control sequence in two parts, first the
1856  * Setup packet by itself, followed some time later by the In and
1857  * Ack packets. Rather than trying to figure out how to add this
1858  * functionality to the normal driver code, we just hijack the
1859  * hardware, using these two function to drive the hardware
1860  * directly.
1861  */
1862
1863 dwc_otg_core_global_regs_t *global_regs;
1864 dwc_otg_host_global_regs_t *hc_global_regs;
1865 dwc_otg_hc_regs_t *hc_regs;
1866 uint32_t *data_fifo;
1867
1868 static void do_setup(void)
1869 {
1870         gintsts_data_t gintsts;
1871         hctsiz_data_t hctsiz;
1872         hcchar_data_t hcchar;
1873         haint_data_t haint;
1874         hcint_data_t hcint;
1875
1876         /* Enable HAINTs */
1877         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1878
1879         /* Enable HCINTs */
1880         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1881
1882         /* Read GINTSTS */
1883         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1884         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1885
1886         /* Read HAINT */
1887         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1888         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1889
1890         /* Read HCINT */
1891         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1892         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1893
1894         /* Read HCCHAR */
1895         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1896         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1897
1898         /* Clear HCINT */
1899         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1900
1901         /* Clear HAINT */
1902         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1903
1904         /* Clear GINTSTS */
1905         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1906
1907         /* Read GINTSTS */
1908         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1909         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1910
1911         /*
1912          * Send Setup packet (Get Device Descriptor)
1913          */
1914
1915         /* Make sure channel is disabled */
1916         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1917         if (hcchar.b.chen) {
1918                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1919                 hcchar.b.chdis = 1;
1920 //              hcchar.b.chen = 1;
1921                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1922                 //sleep(1);
1923                 mdelay(1000);
1924
1925                 /* Read GINTSTS */
1926                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1927                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1928
1929                 /* Read HAINT */
1930                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1931                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1932
1933                 /* Read HCINT */
1934                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1935                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1936
1937                 /* Read HCCHAR */
1938                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1939                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1940
1941                 /* Clear HCINT */
1942                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1943
1944                 /* Clear HAINT */
1945                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1946
1947                 /* Clear GINTSTS */
1948                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1949
1950                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1951                 //if (hcchar.b.chen) {
1952                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1953                 //}
1954         }
1955
1956         /* Set HCTSIZ */
1957         hctsiz.d32 = 0;
1958         hctsiz.b.xfersize = 8;
1959         hctsiz.b.pktcnt = 1;
1960         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1961         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1962
1963         /* Set HCCHAR */
1964         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1965         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1966         hcchar.b.epdir = 0;
1967         hcchar.b.epnum = 0;
1968         hcchar.b.mps = 8;
1969         hcchar.b.chen = 1;
1970         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1971
1972         /* Fill FIFO with Setup data for Get Device Descriptor */
1973         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1974         dwc_write_reg32(data_fifo++, 0x01000680);
1975         dwc_write_reg32(data_fifo++, 0x00080000);
1976
1977         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1978         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1979
1980         /* Wait for host channel interrupt */
1981         do {
1982                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1983         } while (gintsts.b.hcintr == 0);
1984
1985         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1986
1987         /* Disable HCINTs */
1988         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1989
1990         /* Disable HAINTs */
1991         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1992
1993         /* Read HAINT */
1994         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1995         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1996
1997         /* Read HCINT */
1998         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1999         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2000
2001         /* Read HCCHAR */
2002         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2003         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2004
2005         /* Clear HCINT */
2006         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2007
2008         /* Clear HAINT */
2009         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2010
2011         /* Clear GINTSTS */
2012         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2013
2014         /* Read GINTSTS */
2015         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2016         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2017 }
2018
2019 static void do_in_ack(void)
2020 {
2021         gintsts_data_t gintsts;
2022         hctsiz_data_t hctsiz;
2023         hcchar_data_t hcchar;
2024         haint_data_t haint;
2025         hcint_data_t hcint;
2026         host_grxsts_data_t grxsts;
2027
2028         /* Enable HAINTs */
2029         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
2030
2031         /* Enable HCINTs */
2032         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
2033
2034         /* Read GINTSTS */
2035         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2036         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2037
2038         /* Read HAINT */
2039         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2040         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2041
2042         /* Read HCINT */
2043         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2044         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2045
2046         /* Read HCCHAR */
2047         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2048         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2049
2050         /* Clear HCINT */
2051         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2052
2053         /* Clear HAINT */
2054         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2055
2056         /* Clear GINTSTS */
2057         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2058
2059         /* Read GINTSTS */
2060         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2061         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2062
2063         /*
2064          * Receive Control In packet
2065          */
2066
2067         /* Make sure channel is disabled */
2068         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2069         if (hcchar.b.chen) {
2070                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
2071                 hcchar.b.chdis = 1;
2072                 hcchar.b.chen = 1;
2073                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2074                 //sleep(1);
2075                 mdelay(1000);
2076
2077                 /* Read GINTSTS */
2078                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2079                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2080
2081                 /* Read HAINT */
2082                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2083                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2084
2085                 /* Read HCINT */
2086                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2087                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2088
2089                 /* Read HCCHAR */
2090                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2091                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2092
2093                 /* Clear HCINT */
2094                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2095
2096                 /* Clear HAINT */
2097                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2098
2099                 /* Clear GINTSTS */
2100                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2101
2102                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2103                 //if (hcchar.b.chen) {
2104                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
2105                 //}
2106         }
2107
2108         /* Set HCTSIZ */
2109         hctsiz.d32 = 0;
2110         hctsiz.b.xfersize = 8;
2111         hctsiz.b.pktcnt = 1;
2112         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2113         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2114
2115         /* Set HCCHAR */
2116         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2117         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2118         hcchar.b.epdir = 1;
2119         hcchar.b.epnum = 0;
2120         hcchar.b.mps = 8;
2121         hcchar.b.chen = 1;
2122         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2123
2124         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2125         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2126
2127         /* Wait for receive status queue interrupt */
2128         do {
2129                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2130         } while (gintsts.b.rxstsqlvl == 0);
2131
2132         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2133
2134         /* Read RXSTS */
2135         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2136         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2137
2138         /* Clear RXSTSQLVL in GINTSTS */
2139         gintsts.d32 = 0;
2140         gintsts.b.rxstsqlvl = 1;
2141         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2142
2143         switch (grxsts.b.pktsts) {
2144         case DWC_GRXSTS_PKTSTS_IN:
2145                 /* Read the data into the host buffer */
2146                 if (grxsts.b.bcnt > 0) {
2147                         int i;
2148                         int word_count = (grxsts.b.bcnt + 3) / 4;
2149
2150                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2151
2152                         for (i = 0; i < word_count; i++) {
2153                                 (void)dwc_read_reg32(data_fifo++);
2154                         }
2155                 }
2156
2157                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2158         break;
2159
2160         default:
2161                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2162         break;
2163         }
2164
2165         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2166         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2167
2168         /* Wait for receive status queue interrupt */
2169         do {
2170                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2171         } while (gintsts.b.rxstsqlvl == 0);
2172
2173         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2174
2175         /* Read RXSTS */
2176         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2177         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2178
2179         /* Clear RXSTSQLVL in GINTSTS */
2180         gintsts.d32 = 0;
2181         gintsts.b.rxstsqlvl = 1;
2182         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2183
2184         switch (grxsts.b.pktsts) {
2185         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2186         break;
2187
2188         default:
2189                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2190         break;
2191         }
2192
2193         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2194         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2195
2196         /* Wait for host channel interrupt */
2197         do {
2198                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2199         } while (gintsts.b.hcintr == 0);
2200
2201         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2202
2203         /* Read HAINT */
2204         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2205         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2206
2207         /* Read HCINT */
2208         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2209         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2210
2211         /* Read HCCHAR */
2212         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2213         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2214
2215         /* Clear HCINT */
2216         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2217
2218         /* Clear HAINT */
2219         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2220
2221         /* Clear GINTSTS */
2222         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2223
2224         /* Read GINTSTS */
2225         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2226         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2227
2228 //      usleep(100000);
2229 //      mdelay(100);
2230         mdelay(1);
2231
2232         /*
2233          * Send handshake packet
2234          */
2235
2236         /* Read HAINT */
2237         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2238         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2239
2240         /* Read HCINT */
2241         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2242         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2243
2244         /* Read HCCHAR */
2245         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2246         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2247
2248         /* Clear HCINT */
2249         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2250
2251         /* Clear HAINT */
2252         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2253
2254         /* Clear GINTSTS */
2255         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2256
2257         /* Read GINTSTS */
2258         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2259         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2260
2261         /* Make sure channel is disabled */
2262         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2263         if (hcchar.b.chen) {
2264                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2265                 hcchar.b.chdis = 1;
2266                 hcchar.b.chen = 1;
2267                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2268                 //sleep(1);
2269                 mdelay(1000);
2270
2271                 /* Read GINTSTS */
2272                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2273                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2274
2275                 /* Read HAINT */
2276                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2277                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2278
2279                 /* Read HCINT */
2280                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2281                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2282
2283                 /* Read HCCHAR */
2284                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2285                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2286
2287                 /* Clear HCINT */
2288                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2289
2290                 /* Clear HAINT */
2291                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2292
2293                 /* Clear GINTSTS */
2294                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2295
2296                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2297                 //if (hcchar.b.chen) {
2298                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2299                 //}
2300         }
2301
2302         /* Set HCTSIZ */
2303         hctsiz.d32 = 0;
2304         hctsiz.b.xfersize = 0;
2305         hctsiz.b.pktcnt = 1;
2306         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2307         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2308
2309         /* Set HCCHAR */
2310         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2311         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2312         hcchar.b.epdir = 0;
2313         hcchar.b.epnum = 0;
2314         hcchar.b.mps = 8;
2315         hcchar.b.chen = 1;
2316         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2317
2318         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2319         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2320
2321         /* Wait for host channel interrupt */
2322         do {
2323                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2324         } while (gintsts.b.hcintr == 0);
2325
2326         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2327
2328         /* Disable HCINTs */
2329         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2330
2331         /* Disable HAINTs */
2332         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2333
2334         /* Read HAINT */
2335         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2336         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2337
2338         /* Read HCINT */
2339         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2340         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2341
2342         /* Read HCCHAR */
2343         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2344         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2345
2346         /* Clear HCINT */
2347         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2348
2349         /* Clear HAINT */
2350         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2351
2352         /* Clear GINTSTS */
2353         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2354
2355         /* Read GINTSTS */
2356         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2357         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2358 }
2359 #endif /* DWC_HS_ELECT_TST */
2360
2361 /** Handles hub class-specific requests.*/
2362 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2363                             u16 _typeReq,
2364                             u16 _wValue,
2365                             u16 _wIndex,
2366                             char *_buf,
2367                             u16 _wLength)
2368 {
2369         int retval = 0;
2370         unsigned long flags;
2371
2372         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2373         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2374         struct usb_hub_descriptor *desc;
2375         hprt0_data_t hprt0 = {.d32 = 0};
2376
2377         uint32_t port_status;
2378         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2379
2380         switch (_typeReq) {
2381         case ClearHubFeature:
2382                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2383                             "ClearHubFeature 0x%x\n", _wValue);
2384                 switch (_wValue) {
2385                 case C_HUB_LOCAL_POWER:
2386                 case C_HUB_OVER_CURRENT:
2387                         /* Nothing required here */
2388                         break;
2389                 default:
2390                         retval = -EINVAL;
2391                         DWC_ERROR ("DWC OTG HCD - "
2392                                    "ClearHubFeature request %xh unknown\n", _wValue);
2393                 }
2394                 break;
2395         case ClearPortFeature:
2396                 if (!_wIndex || _wIndex > 1)
2397                         goto error;
2398
2399                 switch (_wValue) {
2400                 case USB_PORT_FEAT_ENABLE:
2401                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2402                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2403                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2404                         hprt0.b.prtena = 1;
2405                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2406                         break;
2407                 case USB_PORT_FEAT_SUSPEND:
2408                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2409                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2410                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2411                         hprt0.b.prtres = 1;
2412                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2413                         /* Clear Resume bit */
2414             spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2415                         mdelay (100);
2416             spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2417                         hprt0.b.prtres = 0;
2418                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2419                         break;
2420                 case USB_PORT_FEAT_POWER:
2421                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2422                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2423                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2424                         hprt0.b.prtpwr = 0;
2425                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2426                         break;
2427                 case USB_PORT_FEAT_INDICATOR:
2428                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2429                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2430                         /* Port inidicator not supported */
2431                         break;
2432                 case USB_PORT_FEAT_C_CONNECTION:
2433                         /* Clears drivers internal connect status change
2434                          * flag */
2435                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2436                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2437                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2438                         break;
2439                 case USB_PORT_FEAT_C_RESET:
2440                         /* Clears the driver's internal Port Reset Change
2441                          * flag */
2442                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2443                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2444                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2445                         break;
2446                 case USB_PORT_FEAT_C_ENABLE:
2447                         /* Clears the driver's internal Port
2448                          * Enable/Disable Change flag */
2449                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2450                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2451                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2452                         break;
2453                 case USB_PORT_FEAT_C_SUSPEND:
2454                         /* Clears the driver's internal Port Suspend
2455                          * Change flag, which is set when resume signaling on
2456                          * the host port is complete */
2457                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2458                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2459                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2460                         break;
2461                 case USB_PORT_FEAT_C_OVER_CURRENT:
2462                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2463                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2464                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2465                         break;
2466                 default:
2467                         retval = -EINVAL;
2468                         DWC_ERROR ("DWC OTG HCD - "
2469                                    "ClearPortFeature request %xh "
2470                                    "unknown or unsupported\n", _wValue);
2471                 }
2472                 break;
2473         case GetHubDescriptor:
2474                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2475                              "GetHubDescriptor\n");
2476                 desc = (struct usb_hub_descriptor *)_buf;
2477                 desc->bDescLength = 9;
2478                 desc->bDescriptorType = 0x29;
2479                 desc->bNbrPorts = 1;
2480                 desc->wHubCharacteristics = 0x08;
2481                 desc->bPwrOn2PwrGood = 1;
2482                 desc->bHubContrCurrent = 0;
2483 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
2484                 desc->u.hs.DeviceRemovable[0] = 0;
2485                 desc->u.hs.DeviceRemovable[1] = 0xff;
2486 #else
2487                 desc->bitmap[0] = 0;
2488                 desc->bitmap[1] = 0xff;
2489 #endif
2490                 break;
2491         case GetHubStatus:
2492                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2493                              "GetHubStatus\n");
2494                 memset (_buf, 0, 4);
2495                 break;
2496         case GetPortStatus:
2497                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2498                              "GetPortStatus\n");
2499
2500                 if (!_wIndex || _wIndex > 1)
2501                         goto error;
2502
2503                 port_status = 0;
2504
2505                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2506                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2507
2508                 if (dwc_otg_hcd->flags.b.port_enable_change)
2509                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2510
2511                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2512                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2513
2514                 if (dwc_otg_hcd->flags.b.port_reset_change)
2515                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2516
2517                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2518                         DWC_ERROR("Device Not Supported\n");
2519                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2520                 }
2521
2522                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2523                         /*
2524                          * The port is disconnected, which means the core is
2525                          * either in device mode or it soon will be. Just
2526                          * return 0's for the remainder of the port status
2527                          * since the port register can't be read if the core
2528                          * is in device mode.
2529                          */
2530                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2531                         break;
2532                 }
2533
2534                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2535                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2536
2537                 if (hprt0.b.prtconnsts)
2538                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2539
2540                 if (hprt0.b.prtena)
2541                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2542
2543                 if (hprt0.b.prtsusp)
2544                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2545
2546                 if (hprt0.b.prtovrcurract)
2547                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2548
2549                 if (hprt0.b.prtrst)
2550                         port_status |= (1 << USB_PORT_FEAT_RESET);
2551
2552                 if (hprt0.b.prtpwr)
2553                         port_status |= (1 << USB_PORT_FEAT_POWER);
2554
2555                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2556                         port_status |= USB_PORT_STAT_HIGH_SPEED;
2557
2558                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2559                         port_status |= USB_PORT_STAT_LOW_SPEED;
2560
2561                 if (hprt0.b.prttstctl)
2562                         port_status |= (1 << USB_PORT_FEAT_TEST);
2563
2564                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2565
2566                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2567
2568                 break;
2569         case SetHubFeature:
2570                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2571                              "SetHubFeature\n");
2572                 /* No HUB features supported */
2573                 break;
2574         case SetPortFeature:
2575                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2576                         goto error;
2577
2578                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2579                         /*
2580                          * The port is disconnected, which means the core is
2581                          * either in device mode or it soon will be. Just
2582                          * return without doing anything since the port
2583                          * register can't be written if the core is in device
2584                          * mode.
2585                          */
2586                         break;
2587                 }
2588
2589                 switch (_wValue) {
2590                 case USB_PORT_FEAT_SUSPEND:
2591                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2592                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2593                         if (_hcd->self.otg_port == _wIndex &&
2594                             _hcd->self.b_hnp_enable) {
2595                                 gotgctl_data_t  gotgctl = {.d32=0};
2596                                 gotgctl.b.hstsethnpen = 1;
2597                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2598                                                   0, gotgctl.d32);
2599                                 core_if->op_state = A_SUSPEND;
2600                         }
2601                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2602                         hprt0.b.prtsusp = 1;
2603                                     dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2604                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2605                         /* Suspend the Phy Clock */
2606                         {
2607                                 pcgcctl_data_t pcgcctl = {.d32=0};
2608                                 pcgcctl.b.stoppclk = 1;
2609                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2610                         }
2611
2612                         /* For HNP the bus must be suspended for at least 200ms.*/
2613                         if (_hcd->self.b_hnp_enable) {
2614                                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2615                                 mdelay(200);
2616                                 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2617                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2618                         }
2619                         break;
2620                 case USB_PORT_FEAT_POWER:
2621                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2622                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2623                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2624                         hprt0.b.prtpwr = 1;
2625                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2626                         break;
2627                 case USB_PORT_FEAT_RESET:
2628                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2629                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2630                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2631                         /* When B-Host the Port reset bit is set in
2632                          * the Start HCD Callback function, so that
2633                          * the reset is started within 1ms of the HNP
2634                          * success interrupt. */
2635                         if (!_hcd->self.is_b_host) {
2636                                 hprt0.b.prtrst = 1;
2637                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2638                         }
2639             spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2640                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2641                         // kever @rk 20110712
2642                         // can not use mdelay(60) while irq disable
2643                         //MDELAY (60);
2644                         msleep(60);
2645             spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2646                         hprt0.b.prtrst = 0;
2647                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2648                         break;
2649
2650 #ifdef DWC_HS_ELECT_TST
2651                 case USB_PORT_FEAT_TEST:
2652                 {
2653                         uint32_t t;
2654                         gintmsk_data_t gintmsk;
2655
2656                         t = (_wIndex >> 8); /* MSB wIndex USB */
2657                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2658                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2659                         warn("USB_PORT_FEAT_TEST %d\n", t);
2660                         if (t < 6) {
2661                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2662                                 hprt0.b.prttstctl = t;
2663                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2664                         } else {
2665                                 /* Setup global vars with reg addresses (quick and
2666                                  * dirty hack, should be cleaned up)
2667                                  */
2668                                 global_regs = core_if->core_global_regs;
2669                                 hc_global_regs = core_if->host_if->host_global_regs;
2670                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2671                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2672
2673                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2674                                         /* Save current interrupt mask */
2675                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2676
2677                                         /* Disable all interrupts while we muck with
2678                                          * the hardware directly
2679                                          */
2680                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2681
2682                                         /* 15 second delay per the test spec */
2683                                         mdelay(15000);
2684
2685                                         /* Drive suspend on the root port */
2686                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2687                                         hprt0.b.prtsusp = 1;
2688                                         hprt0.b.prtres = 0;
2689                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2690
2691                                         /* 15 second delay per the test spec */
2692                                         mdelay(15000);
2693
2694                                         /* Drive resume on the root port */
2695                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2696                                         hprt0.b.prtsusp = 0;
2697                                         hprt0.b.prtres = 1;
2698                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2699                                         mdelay(100);
2700
2701                                         /* Clear the resume bit */
2702                                         hprt0.b.prtres = 0;
2703                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2704
2705                                         /* Restore interrupts */
2706                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2707                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2708                                         /* Save current interrupt mask */
2709                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2710
2711                                         /* Disable all interrupts while we muck with
2712                                          * the hardware directly
2713                                          */
2714                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2715
2716                                         /* 15 second delay per the test spec */
2717                                         mdelay(15000);
2718
2719                                         /* Send the Setup packet */
2720                                         do_setup();
2721
2722                                         /* 15 second delay so nothing else happens for awhile */
2723                                         mdelay(15000);
2724
2725                                         /* Restore interrupts */
2726                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2727                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2728                                         /* Save current interrupt mask */
2729                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2730
2731                                         /* Disable all interrupts while we muck with
2732                                          * the hardware directly
2733                                          */
2734                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2735
2736                                         /* Send the Setup packet */
2737                                         do_setup();
2738
2739                                         /* 15 second delay so nothing else happens for awhile */
2740                                         mdelay(15000);
2741
2742                                         /* Send the In and Ack packets */
2743                                         do_in_ack();
2744
2745                                         /* 15 second delay so nothing else happens for awhile */
2746                                         mdelay(15000);
2747
2748                                         /* Restore interrupts */
2749                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2750                                 }
2751                         }
2752                         break;
2753                 }
2754 #endif /* DWC_HS_ELECT_TST */
2755
2756                 case USB_PORT_FEAT_INDICATOR:
2757                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2758                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2759                         /* Not supported */
2760                         break;
2761                 default:
2762                         retval = -EINVAL;
2763                         DWC_ERROR ("DWC OTG HCD - "
2764                                    "SetPortFeature request %xh "
2765                                    "unknown or unsupported\n", _wValue);
2766                         break;
2767                 }
2768                 break;
2769         default:
2770         error:
2771                 retval = -EINVAL;
2772                 DWC_WARN ("DWC OTG HCD - "
2773                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2774                           _typeReq, _wIndex, _wValue);
2775                 break;
2776         }
2777
2778         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2779         return retval;
2780 }
2781
2782
2783 /**
2784  * Assigns transactions from a QTD to a free host channel and initializes the
2785  * host channel to perform the transactions. The host channel is removed from
2786  * the free list.
2787  *
2788  * @param _hcd The HCD state structure.
2789  * @param _qh Transactions from the first QTD for this QH are selected and
2790  * assigned to a free host channel.
2791  */
2792 static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2793 {
2794         dwc_hc_t        *hc;
2795         dwc_otg_qtd_t   *qtd;
2796         struct urb      *urb;
2797
2798         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2799         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2800
2801         /* Remove the host channel from the free list. */
2802         list_del_init(&hc->hc_list_entry);
2803
2804         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2805         urb = qtd->urb;
2806         _qh->channel = hc;
2807         _qh->qtd_in_process = qtd;
2808
2809         /*
2810          * Use usb_pipedevice to determine device address. This address is
2811          * 0 before the SET_ADDRESS command and the correct address afterward.
2812          */
2813         hc->dev_addr = usb_pipedevice(urb->pipe);
2814         hc->ep_num = usb_pipeendpoint(urb->pipe);
2815
2816         if (urb->dev->speed == USB_SPEED_LOW) {
2817                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2818                 /*
2819                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2820                  * device connected.
2821                  */
2822         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2823         } else if (urb->dev->speed == USB_SPEED_FULL) {
2824                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2825                 /*
2826                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2827                  * device connected. warning: only support 1 device at root hub.
2828                  */
2829         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2830         } else {
2831                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2832         }
2833
2834         hc->max_packet = dwc_max_packet(_qh->maxp);
2835
2836         hc->xfer_started = 0;
2837         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2838         hc->error_state = (qtd->error_count > 0);
2839         hc->halt_on_queue = 0;
2840         hc->halt_pending = 0;
2841         hc->requests = 0;
2842
2843         /*
2844          * The following values may be modified in the transfer type section
2845          * below. The xfer_len value may be reduced when the transfer is
2846          * started to accommodate the max widths of the XferSize and PktCnt
2847          * fields in the HCTSIZn register.
2848          */
2849         hc->do_ping = _qh->ping_state;
2850         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2851         hc->data_pid_start = _qh->data_toggle;
2852         hc->multi_count = 1;
2853
2854         if (_hcd->core_if->dma_enable) {
2855                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2856         } else {
2857                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2858         }
2859         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2860         hc->xfer_count = 0;
2861
2862         /*
2863          * Set the split attributes
2864          */
2865         hc->do_split = 0;
2866         if (_qh->do_split) {
2867                 hc->do_split = 1;
2868                 hc->xact_pos = qtd->isoc_split_pos;
2869                 hc->complete_split = qtd->complete_split;
2870                 hc->hub_addr = urb->dev->tt->hub->devnum;
2871                 hc->port_addr = urb->dev->ttport;
2872         }
2873
2874         switch (usb_pipetype(urb->pipe)) {
2875         case PIPE_CONTROL:
2876                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2877                 switch (qtd->control_phase) {
2878                 case DWC_OTG_CONTROL_SETUP:
2879                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2880                         hc->do_ping = 0;
2881                         hc->ep_is_in = 0;
2882                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2883                         if (_hcd->core_if->dma_enable) {
2884                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2885                         } else {
2886                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2887                         }
2888                         hc->xfer_len = 8;
2889                         break;
2890                 case DWC_OTG_CONTROL_DATA:
2891                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2892                         hc->data_pid_start = qtd->data_toggle;
2893                         break;
2894                 case DWC_OTG_CONTROL_STATUS:
2895                         /*
2896                          * Direction is opposite of data direction or IN if no
2897                          * data.
2898                          */
2899                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2900                         if (urb->transfer_buffer_length == 0) {
2901                                 hc->ep_is_in = 1;
2902                         } else {
2903                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2904                         }
2905                         if (hc->ep_is_in) {
2906                                 hc->do_ping = 0;
2907                         }
2908                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2909                         hc->xfer_len = 0;
2910                         if (_hcd->core_if->dma_enable) {
2911                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2912                         } else {
2913                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2914                         }
2915                         break;
2916                 }
2917                 break;
2918         case PIPE_BULK:
2919                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2920                 break;
2921         case PIPE_INTERRUPT:
2922                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2923                 break;
2924         case PIPE_ISOCHRONOUS:
2925                 {
2926                         struct usb_iso_packet_descriptor *frame_desc;
2927                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2928                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2929                         if (_hcd->core_if->dma_enable) {
2930                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2931                         } else {
2932                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2933                         }
2934                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2935                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2936
2937                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2938                                 if (hc->xfer_len <= 188) {
2939                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2940                                 }
2941                                 else {
2942                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2943                                 }
2944                         }
2945                 }
2946                 break;
2947         }
2948
2949         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2950             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2951                 /*
2952                  * This value may be modified when the transfer is started to
2953                  * reflect the actual transfer length.
2954                  */
2955                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2956         }
2957
2958         dwc_otg_hc_init(_hcd->core_if, hc);
2959         hc->qh = _qh;
2960 }
2961
2962 /**
2963  * This function selects transactions from the HCD transfer schedule and
2964  * assigns them to available host channels. It is called from HCD interrupt
2965  * handler functions.
2966  *
2967  * @param _hcd The HCD state structure.
2968  *
2969  * @return The types of new transactions that were assigned to host channels.
2970  */
2971 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2972 {
2973         struct list_head                *qh_ptr;
2974         dwc_otg_qh_t                    *qh;
2975         int                             num_channels;
2976         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2977
2978 #ifdef DEBUG_SOF
2979         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2980 #endif
2981
2982         /* Process entries in the periodic ready list. */
2983         qh_ptr = _hcd->periodic_sched_inactive.next;
2984         while ((qh_ptr != &_hcd->periodic_sched_inactive)&&
2985                !list_empty(&_hcd->free_hc_list)) {
2986                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2987                 if(qh->qh_state != QH_READY){
2988                 qh_ptr = qh_ptr->next;
2989                 continue;
2990                 }
2991
2992                 assign_and_init_hc(_hcd, qh);
2993
2994                 /*
2995                  * Move the QH from the periodic ready schedule to the
2996                  * periodic assigned schedule.
2997                  */
2998                 qh_ptr = qh_ptr->next;
2999                 //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
3000                 qh->qh_state = QH_ASSIGNED;
3001
3002                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
3003         }
3004
3005         /*
3006          * Process entries in the inactive portion of the non-periodic
3007          * schedule. Some free host channels may not be used if they are
3008          * reserved for periodic transfers.
3009          */
3010         qh_ptr = _hcd->non_periodic_sched_inactive.next;
3011         num_channels = _hcd->core_if->core_params->host_channels;
3012         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
3013                 /*yk@rk 20100714
3014                (_hcd->non_periodic_channels <
3015                 num_channels - _hcd->periodic_channels) &&
3016                 */
3017                !list_empty(&_hcd->free_hc_list)) {
3018
3019                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3020                 assign_and_init_hc(_hcd, qh);
3021
3022                 /*
3023                  * Move the QH from the non-periodic inactive schedule to the
3024                  * non-periodic active schedule.
3025                  */
3026                 qh_ptr = qh_ptr->next;
3027                 list_move_tail(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
3028
3029                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
3030                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
3031                 } else {
3032                         ret_val = DWC_OTG_TRANSACTION_ALL;
3033                 }
3034
3035                 _hcd->non_periodic_channels++;
3036         }
3037
3038         return ret_val;
3039 }
3040
3041 /**
3042  * Attempts to queue a single transaction request for a host channel
3043  * associated with either a periodic or non-periodic transfer. This function
3044  * assumes that there is space available in the appropriate request queue. For
3045  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
3046  * is available in the appropriate Tx FIFO.
3047  *
3048  * @param _hcd The HCD state structure.
3049  * @param _hc Host channel descriptor associated with either a periodic or
3050  * non-periodic transfer.
3051  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
3052  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
3053  * transfers.
3054  *
3055  * @return 1 if a request is queued and more requests may be needed to
3056  * complete the transfer, 0 if no more requests are required for this
3057  * transfer, -1 if there is insufficient space in the Tx FIFO.
3058  */
3059 static int queue_transaction(dwc_otg_hcd_t *_hcd,
3060                              dwc_hc_t *_hc,
3061                              uint16_t _fifo_dwords_avail)
3062 {
3063         int retval;
3064
3065         if (_hcd->core_if->dma_enable) {
3066                 if (!_hc->xfer_started) {
3067                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3068                         _hc->qh->ping_state = 0;
3069                 }
3070                 retval = 0;
3071         } else  if (_hc->halt_pending) {
3072                 /* Don't queue a request if the channel has been halted. */
3073                 retval = 0;
3074         } else if (_hc->halt_on_queue) {
3075                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
3076                 retval = 0;
3077         } else if (_hc->do_ping) {
3078                 if (!_hc->xfer_started) {
3079                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3080                 }
3081                 retval = 0;
3082         } else if (!_hc->ep_is_in ||
3083                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3084                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
3085                         if (!_hc->xfer_started) {
3086                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3087                                 retval = 1;
3088                         } else {
3089                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3090                         }
3091                 } else {
3092                         retval = -1;
3093                 }
3094         } else {
3095                 if (!_hc->xfer_started) {
3096                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3097                         retval = 1;
3098                 } else {
3099                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3100                 }
3101         }
3102
3103         return retval;
3104 }
3105
3106 /**
3107  * Processes active non-periodic channels and queues transactions for these
3108  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3109  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3110  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3111  * FIFO Empty interrupt is disabled.
3112  */
3113 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
3114 {
3115         gnptxsts_data_t         tx_status;
3116         struct list_head        *orig_qh_ptr;
3117         dwc_otg_qh_t            *qh;
3118         int                     status;
3119         int                     no_queue_space = 0;
3120         int                     no_fifo_space = 0;
3121         int                     more_to_do = 0;
3122
3123         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
3124
3125         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
3126 #ifdef DEBUG
3127         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3128         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3129                     tx_status.b.nptxqspcavail);
3130         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
3131                     tx_status.b.nptxfspcavail);
3132 #endif
3133         /*
3134          * Keep track of the starting point. Skip over the start-of-list
3135          * entry.
3136          */
3137         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3138                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3139         }
3140         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3141
3142         /*
3143          * Process once through the active list or until no more space is
3144          * available in the request queue or the Tx FIFO.
3145          */
3146         do {
3147                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3148                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3149                         no_queue_space = 1;
3150                         break;
3151                 }
3152
3153                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3154                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3155
3156                 if (status > 0) {
3157                         more_to_do = 1;
3158                 } else if (status < 0) {
3159                         no_fifo_space = 1;
3160                         break;
3161                 }
3162
3163                 /* Advance to next QH, skipping start-of-list entry. */
3164                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3165                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3166                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3167                 }
3168
3169         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3170
3171         if (!_hcd->core_if->dma_enable) {
3172                 gintmsk_data_t intr_mask = {.d32 = 0};
3173                 intr_mask.b.nptxfempty = 1;
3174
3175 #ifdef DEBUG
3176                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3177                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3178                             tx_status.b.nptxqspcavail);
3179                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3180                             tx_status.b.nptxfspcavail);
3181 #endif
3182                 if (more_to_do || no_queue_space || no_fifo_space) {
3183                         /*
3184                          * May need to queue more transactions as the request
3185                          * queue or Tx FIFO empties. Enable the non-periodic
3186                          * Tx FIFO empty interrupt. (Always use the half-empty
3187                          * level to ensure that new requests are loaded as
3188                          * soon as possible.)
3189                          */
3190                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3191                 } else {
3192                         /*
3193                          * Disable the Tx FIFO empty interrupt since there are
3194                          * no more transactions that need to be queued right
3195                          * now. This function is called from interrupt
3196                          * handlers to queue more transactions as transfer
3197                          * states change.
3198                          */
3199                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3200                 }
3201         }
3202 }
3203
3204 /**
3205  * Processes periodic channels for the next frame and queues transactions for
3206  * these channels to the DWC_otg controller. After queueing transactions, the
3207  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3208  * to queue as Periodic Tx FIFO or request queue space becomes available.
3209  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3210  */
3211 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3212 {
3213         hptxsts_data_t          tx_status;
3214         struct list_head        *qh_ptr;
3215         dwc_otg_qh_t            *qh;
3216         int                     status;
3217         int                     no_queue_space = 0;
3218         int                     no_fifo_space = 0;
3219
3220         dwc_otg_host_global_regs_t *host_regs;
3221         host_regs = _hcd->core_if->host_if->host_global_regs;
3222
3223         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3224 #ifdef DEBUG
3225         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3226         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3227                     tx_status.b.ptxqspcavail);
3228         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3229                     tx_status.b.ptxfspcavail);
3230 #endif
3231
3232         qh_ptr = _hcd->periodic_sched_inactive.next;
3233         while (qh_ptr != &_hcd->periodic_sched_inactive) {
3234                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3235                 if (tx_status.b.ptxqspcavail == 0) {
3236                         no_queue_space = 1;
3237                         break;
3238                 }
3239
3240                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3241                 if(qh->qh_state != QH_ASSIGNED){
3242                 qh_ptr = qh_ptr->next;
3243                 continue;
3244                 }
3245
3246                 /*
3247                  * Set a flag if we're queuing high-bandwidth in slave mode.
3248                  * The flag prevents any halts to get into the request queue in
3249                  * the middle of multiple high-bandwidth packets getting queued.
3250                  */
3251                 if ((!_hcd->core_if->dma_enable) &&
3252                     (qh->channel->multi_count > 1))
3253                 {
3254                         _hcd->core_if->queuing_high_bandwidth = 1;
3255                 }
3256
3257                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3258                 if (status < 0) {
3259                         no_fifo_space = 1;
3260                         break;
3261                 }
3262
3263                 /*
3264                  * In Slave mode, stay on the current transfer until there is
3265                  * nothing more to do or the high-bandwidth request count is
3266                  * reached. In DMA mode, only need to queue one request. The
3267                  * controller automatically handles multiple packets for
3268                  * high-bandwidth transfers.
3269                  */
3270                 if (_hcd->core_if->dma_enable ||
3271                     (status == 0 ||
3272                      qh->channel->requests == qh->channel->multi_count)) {
3273                         qh_ptr = qh_ptr->next;
3274                         /*
3275                          * Move the QH from the periodic assigned schedule to
3276                          * the periodic queued schedule.
3277                          */
3278                         //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3279                         qh->qh_state = QH_QUEUED;
3280
3281                         /* done queuing high bandwidth */
3282                         _hcd->core_if->queuing_high_bandwidth = 0;
3283                 }
3284         }
3285
3286         if (!_hcd->core_if->dma_enable) {
3287                 dwc_otg_core_global_regs_t *global_regs;
3288                 gintmsk_data_t intr_mask = {.d32 = 0};
3289
3290                 global_regs = _hcd->core_if->core_global_regs;
3291                 intr_mask.b.ptxfempty = 1;
3292 #ifdef DEBUG
3293                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3294                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3295                             tx_status.b.ptxqspcavail);
3296                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3297                             tx_status.b.ptxfspcavail);
3298 #endif
3299                 if (//!(list_empty(&_hcd->periodic_sched_assigned)) ||
3300                     no_queue_space || no_fifo_space) {
3301                         /*
3302                          * May need to queue more transactions as the request
3303                          * queue or Tx FIFO empties. Enable the periodic Tx
3304                          * FIFO empty interrupt. (Always use the half-empty
3305                          * level to ensure that new requests are loaded as
3306                          * soon as possible.)
3307                          */
3308                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3309                 } else {
3310                         /*
3311                          * Disable the Tx FIFO empty interrupt since there are
3312                          * no more transactions that need to be queued right
3313                          * now. This function is called from interrupt
3314                          * handlers to queue more transactions as transfer
3315                          * states change.
3316                          */
3317                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3318                 }
3319         }
3320 }
3321
3322 /**
3323  * This function processes the currently active host channels and queues
3324  * transactions for these channels to the DWC_otg controller. It is called
3325  * from HCD interrupt handler functions.
3326  *
3327  * @param _hcd The HCD state structure.
3328  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3329  * periodic, or both).
3330  */
3331 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3332                                     dwc_otg_transaction_type_e _tr_type)
3333 {
3334 #ifdef DEBUG_SOF
3335         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3336 #endif
3337         /* Process host channels associated with periodic transfers. */
3338         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3339              _tr_type == DWC_OTG_TRANSACTION_ALL) //&&
3340             //!list_empty(&_hcd->periodic_sched_assigned)
3341             ) {
3342
3343                 process_periodic_channels(_hcd);
3344         }
3345
3346         /* Process host channels associated with non-periodic transfers. */
3347         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3348              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3349                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3350                         process_non_periodic_channels(_hcd);
3351                 } else {
3352                         /*
3353                          * Ensure NP Tx FIFO empty interrupt is disabled when
3354                          * there are no non-periodic transfers to process.
3355                          */
3356                         gintmsk_data_t gintmsk = {.d32 = 0};
3357                         gintmsk.b.nptxfempty = 1;
3358                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3359                                          gintmsk.d32, 0);
3360                 }
3361         }
3362 }
3363
3364 /**
3365  * Sets the final status of an URB and returns it to the device driver. Any
3366  * required cleanup of the URB is performed.
3367  */
3368 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3369                               int _status)
3370 __releases(_hcd->lock)
3371 __acquires(_hcd->lock)
3372 {
3373
3374 #ifdef DEBUG
3375         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3376                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3377                           __func__, _urb, usb_pipedevice(_urb->pipe),
3378                           usb_pipeendpoint(_urb->pipe),
3379                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3380                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3381                         int i;
3382                         for (i = 0; i < _urb->number_of_packets; i++) {
3383                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3384                                           i, _urb->iso_frame_desc[i].status);
3385                         }
3386                 }
3387         }
3388 #endif
3389
3390         _urb->status = _status;
3391         _urb->hcpriv = NULL;
3392         spin_unlock(&_hcd->global_lock);
3393         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3394         spin_lock(&_hcd->global_lock);
3395 }
3396
3397 void dwc_otg_clear_halt(struct urb *_urb)
3398 {
3399         struct dwc_otg_qh *_qh;
3400         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3401         if((ep)&&(ep->hcpriv))
3402         {
3403                 _qh =  (dwc_otg_qh_t *) ep->hcpriv;
3404                 _qh->data_toggle = 0;
3405         }
3406 }
3407 /*
3408  * Returns the Queue Head for an URB.
3409  */
3410 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3411 {
3412         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3413         return (dwc_otg_qh_t *) ep->hcpriv;
3414 }
3415
3416 #ifdef DEBUG
3417 void dwc_print_setup_data (uint8_t *setup)
3418 {
3419         int i;
3420         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3421                 DWC_PRINT("Setup Data = MSB ");
3422                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3423                 DWC_PRINT("\n");
3424                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3425                 DWC_PRINT("  bmRequestType Type = ");
3426                 switch ((setup[0]&0x60) >> 5) {
3427                 case 0: DWC_PRINT("Standard\n"); break;
3428                 case 1: DWC_PRINT("Class\n"); break;
3429                 case 2: DWC_PRINT("Vendor\n"); break;
3430                 case 3: DWC_PRINT("Reserved\n"); break;
3431                 }
3432                 DWC_PRINT("  bmRequestType Recipient = ");
3433                 switch (setup[0]&0x1f) {
3434                 case 0: DWC_PRINT("Device\n"); break;
3435                 case 1: DWC_PRINT("Interface\n"); break;
3436                 case 2: DWC_PRINT("Endpoint\n"); break;
3437                 case 3: DWC_PRINT("Other\n"); break;
3438                 default: DWC_PRINT("Reserved\n"); break;
3439                 }
3440                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3441                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3442                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3443                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3444         }
3445 }
3446 #endif
3447
3448 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3449 #if 0
3450         DWC_PRINT("Frame remaining at SOF:\n");
3451         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3452                   _hcd->frrem_samples, _hcd->frrem_accum,
3453                   (_hcd->frrem_samples > 0) ?
3454                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3455
3456         DWC_PRINT("\n");
3457         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3458         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3459                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3460                   (_hcd->core_if->hfnum_7_samples > 0) ?
3461                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3462         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3463         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3464                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3465                   (_hcd->core_if->hfnum_0_samples > 0) ?
3466                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3467         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3468         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3469                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3470                   (_hcd->core_if->hfnum_other_samples > 0) ?
3471                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3472
3473         DWC_PRINT("\n");
3474         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3475         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3476                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3477                   (_hcd->hfnum_7_samples_a > 0) ?
3478                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3479         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3480         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3481                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3482                   (_hcd->hfnum_0_samples_a > 0) ?
3483                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3484         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3485         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3486                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3487                   (_hcd->hfnum_other_samples_a > 0) ?
3488                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3489
3490         DWC_PRINT("\n");
3491         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3492         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3493                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3494                   (_hcd->hfnum_7_samples_b > 0) ?
3495                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3496         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3497         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3498                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3499                   (_hcd->hfnum_0_samples_b > 0) ?
3500                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3501         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3502         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3503                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3504                   (_hcd->hfnum_other_samples_b > 0) ?
3505                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3506 #endif
3507 }
3508
3509 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3510 {
3511 #ifdef DEBUG
3512         int num_channels;
3513         int i;
3514         gnptxsts_data_t np_tx_status;
3515         hptxsts_data_t p_tx_status;
3516
3517         num_channels = _hcd->core_if->core_params->host_channels;
3518         DWC_PRINT("\n");
3519         DWC_PRINT("************************************************************\n");
3520         DWC_PRINT("HCD State:\n");
3521         DWC_PRINT("  Num channels: %d\n", num_channels);
3522         for (i = 0; i < num_channels; i++) {
3523                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3524                 DWC_PRINT("  Channel %d:\n", i);
3525                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3526                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3527                 DWC_PRINT("    speed: %d\n", hc->speed);
3528                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3529                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3530                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3531                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3532                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3533                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3534                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3535                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3536                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3537                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3538                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3539                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3540                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3541                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3542                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3543                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3544                 DWC_PRINT("    requests: %d\n", hc->requests);
3545                 DWC_PRINT("    qh: %p\n", hc->qh);
3546                 if (hc->xfer_started) {
3547                         hfnum_data_t hfnum;
3548                         hcchar_data_t hcchar;
3549                         hctsiz_data_t hctsiz;
3550                         hcint_data_t hcint;
3551                         hcintmsk_data_t hcintmsk;
3552                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3553                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3554                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3555                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3556                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3557                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3558                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3559                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3560                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3561                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3562                 }
3563                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3564                         dwc_otg_qtd_t *qtd;
3565                         struct urb *urb;
3566                         qtd = hc->qh->qtd_in_process;
3567                         urb = qtd->urb;
3568                         DWC_PRINT("    URB Info:\n");
3569                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3570                         if (urb != NULL) {
3571                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3572                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3573                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3574                                 DWC_PRINT("      Max packet size: %d\n",
3575                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3576                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3577                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3578                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3579                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3580                         }
3581                 }
3582         }
3583         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3584         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3585         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3586         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3587         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3588         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3589         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3590         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3591         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3592         dwc_otg_hcd_dump_frrem(_hcd);
3593         dwc_otg_dump_global_registers(_hcd->core_if);
3594         dwc_otg_dump_host_registers(_hcd->core_if);
3595         DWC_PRINT("************************************************************\n");
3596         DWC_PRINT("\n");
3597 #endif
3598 }
3599 #endif /* DWC_DEVICE_ONLY */