1 /* ==========================================================================
2 * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
7 * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
8 * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
9 * otherwise expressly agreed to in writing between Synopsys and you.
11 * The Software IS NOT an item of Licensed Software or Licensed Product under
12 * any End User Software License Agreement or Agreement for Licensed Product
13 * with Synopsys or any supplement thereto. You are permitted to use and
14 * redistribute this Software in source and binary forms, with or without
15 * modification, provided that redistributions of source code must retain this
16 * notice. You may not view, use, disclose, copy or distribute this file or
17 * any information contained herein except pursuant to this license grant from
18 * Synopsys. If you do not agree with this notice, including the disclaimer
19 * below, then you are not authorized to use the Software.
21 * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
25 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
27 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
28 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
32 * ========================================================================== */
33 #ifndef DWC_DEVICE_ONLY
38 * This file contains the implementation of the HCD. In Linux, the HCD
39 * implements the hc_driver API.
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/moduleparam.h>
44 #include <linux/init.h>
45 #include <linux/device.h>
46 #include <linux/errno.h>
47 #include <linux/list.h>
48 #include <linux/interrupt.h>
49 #include <linux/string.h>
50 #include <linux/dma-mapping.h>
51 #include <linux/irq.h>
52 #include <linux/platform_device.h>
53 #include "usbdev_rk.h"
55 #include "dwc_otg_driver.h"
56 #include "dwc_otg_hcd.h"
57 #include "dwc_otg_regs.h"
59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
61 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
62 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
64 pcgcctl_data_t pcgcctl;
65 struct dwc_otg_platform_data *pldata;
66 pldata = core_if->otg_dev->pldata;
68 if(core_if->op_state == B_PERIPHERAL)
70 DWC_PRINT("%s, usb device mode\n", __func__);
73 if(!(dwc_otg_hcd->host_enabled&1))
75 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
76 #ifdef CONFIG_USB_SUSPEND
80 DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
81 if(hprt0.b.prtconnsts) // usb device connected
89 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
92 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
98 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
101 pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
102 pcgcctl.b.pwrclmp = 1;//power clamp
103 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
105 //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
106 pcgcctl.b.stoppclk = 1;//stop phy clk
107 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
109 else //no device connect
111 if(pldata->phy_suspend)
112 pldata->phy_suspend( pldata, USB_PHY_SUSPEND);
115 #ifndef CONFIG_DWC_REMOTE_WAKEUP
116 if (pldata->clock_enable)
117 pldata->clock_enable( pldata, 0);
123 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
125 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
126 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
128 pcgcctl_data_t pcgcctl;
129 gintmsk_data_t gintmsk;
130 struct dwc_otg_platform_data *pldata;
131 pldata = core_if->otg_dev->pldata;
133 if(core_if->op_state == B_PERIPHERAL)
135 DWC_PRINT("%s, usb device mode\n", __func__);
138 //#ifdef CONFIG_USB_SUSPEND
139 if(!(dwc_otg_hcd->host_enabled&1))
142 #ifndef CONFIG_DWC_REMOTE_WAKEUP
143 if (pldata->clock_enable)
144 pldata->clock_enable( pldata, 1);
148 pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
149 pcgcctl.b.stoppclk = 0;//stop phy clk
150 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
152 pcgcctl.b.pwrclmp = 0;//power clamp
153 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
156 gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
157 gintmsk.b.portintr = 0;
158 dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
160 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
161 #ifdef CONFIG_USB_SUSPEND
165 DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
166 if(hprt0.b.prtconnsts)
168 //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
169 //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
173 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
175 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
176 //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
181 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
185 hprt0.b.prtconndet = 1;
186 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
188 //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
189 //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
194 if(pldata->phy_suspend)
195 pldata->phy_suspend( pldata, USB_PHY_ENABLED);
197 gintmsk.b.portintr = 1;
198 dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
203 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
205 static const struct hc_driver dwc_otg_hc_driver = {
207 .description = dwc_otg_hcd_name,
208 .product_desc = "DWC OTG Controller",
209 .hcd_priv_size = sizeof(dwc_otg_hcd_t),
211 .irq = dwc_otg_hcd_irq,
213 .flags = HCD_MEMORY | HCD_USB2,
216 .start = dwc_otg_hcd_start,
221 * core/hcd.c call hcd->driver->bus_suspend
222 * otherwise system can not be suspended
225 .bus_suspend = dwc_otg_hcd_suspend,
226 .bus_resume = dwc_otg_hcd_resume,
228 .stop = dwc_otg_hcd_stop,
230 .urb_enqueue = dwc_otg_hcd_urb_enqueue,
231 .urb_dequeue = dwc_otg_hcd_urb_dequeue,
232 .endpoint_disable = dwc_otg_hcd_endpoint_disable,
234 .get_frame_number = dwc_otg_hcd_get_frame_number,
236 .hub_status_data = dwc_otg_hcd_hub_status_data,
237 .hub_control = dwc_otg_hcd_hub_control,
242 #ifdef CONFIG_USB11_HOST
243 static const struct hc_driver host11_hc_driver = {
245 .description = "host11_hcd",
246 .product_desc = "DWC OTG Controller",
247 .hcd_priv_size = sizeof(dwc_otg_hcd_t),
249 .irq = dwc_otg_hcd_irq,
251 .flags = HCD_MEMORY | HCD_USB2,
254 .start = dwc_otg_hcd_start,
259 * core/hcd.c call hcd->driver->bus_suspend
260 * otherwise system can not be suspended
263 .bus_suspend = dwc_otg_hcd_suspend,
264 .bus_resume = dwc_otg_hcd_resume,
266 .stop = dwc_otg_hcd_stop,
268 .urb_enqueue = dwc_otg_hcd_urb_enqueue,
269 .urb_dequeue = dwc_otg_hcd_urb_dequeue,
270 .endpoint_disable = dwc_otg_hcd_endpoint_disable,
272 .get_frame_number = dwc_otg_hcd_get_frame_number,
274 .hub_status_data = dwc_otg_hcd_hub_status_data,
275 .hub_control = dwc_otg_hcd_hub_control,
280 #ifdef CONFIG_USB20_HOST
281 static const struct hc_driver host20_hc_driver = {
283 .description = "host20_hcd",
284 .product_desc = "DWC OTG Controller",
285 .hcd_priv_size = sizeof(dwc_otg_hcd_t),
287 .irq = dwc_otg_hcd_irq,
289 .flags = HCD_MEMORY | HCD_USB2,
292 .start = dwc_otg_hcd_start,
297 * core/hcd.c call hcd->driver->bus_suspend
298 * otherwise system can not be suspended
301 .bus_suspend = dwc_otg_hcd_suspend,
302 .bus_resume = dwc_otg_hcd_resume,
304 .stop = dwc_otg_hcd_stop,
306 .urb_enqueue = dwc_otg_hcd_urb_enqueue,
307 .urb_dequeue = dwc_otg_hcd_urb_dequeue,
308 .endpoint_disable = dwc_otg_hcd_endpoint_disable,
310 .get_frame_number = dwc_otg_hcd_get_frame_number,
312 .hub_status_data = dwc_otg_hcd_hub_status_data,
313 .hub_control = dwc_otg_hcd_hub_control,
320 * Work queue function for starting the HCD when A-Cable is connected.
321 * The dwc_otg_hcd_start() must be called in a process context.
323 static void hcd_start_func(struct work_struct *work)
325 dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
326 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
328 DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
330 dwc_otg_hcd_start(hcd);
335 * HCD Callback function for starting the HCD when A-Cable is
338 * @param _p void pointer to the <code>struct usb_hcd</code>
340 static int32_t dwc_otg_hcd_start_cb(void *_p)
342 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
343 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
346 if (core_if->op_state == B_HOST) {
348 * Reset the port. During a HNP mode switch the reset
349 * needs to occur within 1ms and have a duration of at
352 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
354 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
355 ((struct usb_hcd *)_p)->self.is_b_host = 1;
357 ((struct usb_hcd *)_p)->self.is_b_host = 0;
360 /* Need to start the HCD in a non-interrupt context. */
361 // INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
362 INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
363 schedule_work(&dwc_otg_hcd->start_work);
370 * HCD Callback function for stopping the HCD.
372 * @param _p void pointer to the <code>struct usb_hcd</code>
374 static int32_t dwc_otg_hcd_stop_cb( void *_p )
376 struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
377 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
378 dwc_otg_hcd_stop( usb_hcd );
382 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
386 int num_channels = _hcd->core_if->core_params->host_channels;
387 for (i = 0; i < num_channels; i++) {
388 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
393 static void del_timers(dwc_otg_hcd_t *_hcd)
395 del_xfer_timers(_hcd);
396 del_timer(&_hcd->conn_timer);
400 * Processes all the URBs in a single list of QHs. Completes them with
401 * -ETIMEDOUT and frees the QTD.
403 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
405 struct list_head *qh_item;
407 struct list_head *qtd_item;
411 list_for_each(qh_item, _qh_list) {
412 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
413 for (qtd_item = qh->qtd_list.next;
414 qtd_item != &qh->qtd_list;
415 qtd_item = qh->qtd_list.next) {
416 qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
417 if (qtd->urb != NULL) {
420 // urb will be re entry to ep->urb_list if use ETIMEOUT
421 dwc_otg_hcd_complete_urb(_hcd, urb,
422 -ESHUTDOWN);//ETIMEDOUT,ENOENT
424 dwc_otg_hcd_qtd_remove_and_free(qtd);
430 * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
431 * and periodic schedules. The QTD associated with each URB is removed from
432 * the schedule and freed. This function may be called when a disconnect is
433 * detected or when the HCD is being stopped.
435 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
437 kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
438 kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
439 kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
440 // kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
441 // kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
442 // kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
444 extern void release_channel(dwc_otg_hcd_t *_hcd,
447 dwc_otg_halt_status_e _halt_status);
450 * HCD Callback function for disconnect of the HCD.
452 * @param _p void pointer to the <code>struct usb_hcd</code>
454 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
457 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
459 //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
462 * Set status flags for the hub driver.
464 dwc_otg_hcd->flags.b.port_connect_status_change = 1;
465 dwc_otg_hcd->flags.b.port_connect_status = 0;
468 * Shutdown any transfers in process by clearing the Tx FIFO Empty
469 * interrupt mask and status bits and disabling subsequent host
470 * channel interrupts.
473 intr.b.nptxfempty = 1;
474 intr.b.ptxfempty = 1;
476 dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
477 dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
479 // del_timers(dwc_otg_hcd);
482 * Turn off the vbus power only if the core has transitioned to device
483 * mode. If still in host mode, need to keep power on to detect a
486 if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
487 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
488 hprt0_data_t hprt0 = { .d32=0 };
489 DWC_PRINT("Disconnect: PortPower off\n");
491 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
494 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
497 spin_lock(&dwc_otg_hcd->global_lock);
498 /* Respond with an error status to all URBs in the schedule. */
499 kill_all_urbs(dwc_otg_hcd);
500 spin_unlock(&dwc_otg_hcd->global_lock);
502 if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
503 /* Clean up any host channels that were in use. */
507 dwc_otg_hc_regs_t *hc_regs;
508 hcchar_data_t hcchar;
510 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
512 if (!dwc_otg_hcd->core_if->dma_enable) {
513 /* Flush out any channel requests in slave mode. */
514 for (i = 0; i < num_channels; i++) {
515 channel = dwc_otg_hcd->hc_ptr_array[i];
516 if (list_empty(&channel->hc_list_entry)) {
517 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
518 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
523 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
529 for (i = 0; i < num_channels; i++) {
530 channel = dwc_otg_hcd->hc_ptr_array[i];
531 if (list_empty(&channel->hc_list_entry)) {
532 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
533 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
535 /* Halt the channel. */
537 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
540 release_channel(dwc_otg_hcd, channel, NULL, DWC_OTG_HC_XFER_URB_DEQUEUE);
542 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
543 list_add_tail(&channel->hc_list_entry,
544 &dwc_otg_hcd->free_hc_list);
550 /* A disconnect will end the session so the B-Device is no
551 * longer a B-host. */
552 ((struct usb_hcd *)_p)->self.is_b_host = 0;
557 * Connection timeout function. An OTG host is required to display a
558 * message if the device does not connect within 10 seconds.
560 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
562 DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
563 DWC_PRINT( "Connect Timeout\n");
564 DWC_ERROR( "Device Not Connected/Responding\n" );
568 * Start the connection timer. An OTG host is required to display a
569 * message if the device does not connect within 10 seconds. The
570 * timer is deleted if a port connect interrupt occurs before the
573 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
575 init_timer( &_hcd->conn_timer );
576 _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
577 _hcd->conn_timer.data = (unsigned long)0;
578 _hcd->conn_timer.expires = jiffies + (HZ*10);
579 add_timer( &_hcd->conn_timer );
583 * HCD Callback function for disconnect of the HCD.
585 * @param _p void pointer to the <code>struct usb_hcd</code>
587 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
589 // dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
590 DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
591 // dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
596 * HCD Callback structure for handling mode switching.
598 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
599 .start = dwc_otg_hcd_start_cb,
600 .stop = dwc_otg_hcd_stop_cb,
601 .disconnect = dwc_otg_hcd_disconnect_cb,
602 .session_start = dwc_otg_hcd_session_start_cb,
607 * Reset tasklet function
609 static void reset_tasklet_func (unsigned long data)
611 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
612 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
615 DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
617 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
619 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
623 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
624 dwc_otg_hcd->flags.b.port_reset_change = 1;
629 static struct tasklet_struct reset_tasklet = {
632 .count = ATOMIC_INIT(0),
633 .func = reset_tasklet_func,
636 #ifndef CONFIG_ARCH_RK29
637 static void dwc_otg_hcd_enable(struct work_struct *work)
639 dwc_otg_hcd_t *dwc_otg_hcd;
640 dwc_otg_core_if_t *_core_if;
641 struct dwc_otg_platform_data *pldata;
643 dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, host_enable_work.work);
644 _core_if = dwc_otg_hcd->core_if;
645 pldata = _core_if->otg_dev->pldata;
647 if(dwc_otg_hcd->host_enabled == dwc_otg_hcd->host_setenable){
648 // DWC_PRINT("%s, enable flag %d\n", __func__, dwc_otg_hcd->host_setenable);
652 if(dwc_otg_hcd->host_setenable == 2){// enable -> disable
653 if(pldata->get_status(USB_STATUS_DPDM)){// usb device connected
654 dwc_otg_hcd->host_setenable = 1;
657 DWC_PRINT("%s, disable host controller\n", __func__);
659 if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
660 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
663 pldata->soft_reset();
664 dwc_otg_disable_host_interrupts( _core_if );
665 // if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
666 // _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
668 if(pldata->phy_suspend)
669 pldata->phy_suspend( pldata, USB_PHY_SUSPEND);
671 pldata->clock_enable( pldata, 0);
672 }else if(dwc_otg_hcd->host_setenable == 1){
673 DWC_PRINT("%s, enable host controller\n", __func__);
674 pldata->clock_enable( pldata, 1);
675 if(pldata->phy_suspend)
676 pldata->phy_suspend( pldata, USB_PHY_ENABLED);
678 dwc_otg_core_init(_core_if);
679 dwc_otg_enable_global_interrupts(_core_if);
680 if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
681 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
684 dwc_otg_hcd->host_enabled = dwc_otg_hcd->host_setenable;
688 static void dwc_otg_hcd_connect_detect(unsigned long pdata)
690 dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)pdata;
691 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
693 struct dwc_otg_platform_data *pldata;
694 pldata = core_if->otg_dev->pldata;
696 local_irq_save(flags);
698 // DWC_PRINT("%s hprt %x, grfstatus 0x%x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
699 if(pldata->get_status(USB_STATUS_DPDM)) // usb device connected
700 dwc_otg_hcd->host_setenable = 1;
701 else{ // no device, suspend host
702 if((dwc_read_reg32(core_if->host_if->hprt0) & 1) == 0)
703 dwc_otg_hcd->host_setenable = 2;
705 if((dwc_otg_hcd->host_enabled)&&(dwc_otg_hcd->host_setenable != dwc_otg_hcd->host_enabled)){
706 schedule_delayed_work(&dwc_otg_hcd->host_enable_work, 1);
708 mod_timer(&dwc_otg_hcd->connect_detect_timer,jiffies + (HZ<<1));
709 local_irq_restore(flags);
714 * Initializes the HCD. This function allocates memory for and initializes the
715 * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
716 * USB bus with the core and calls the hc_driver->start() function. It returns
717 * a negative error on failure.
719 extern uint32_t g_dbg_lvl;
720 int __devinit dwc_otg_hcd_init(struct device *dev)
722 struct usb_hcd *hcd = NULL;
723 dwc_otg_hcd_t *dwc_otg_hcd = NULL;
724 dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
731 #if 1 //kaiker .these code must execute before usb_create_hcd
732 /* Set device flags indicating whether the HCD supports DMA. */
733 static u64 usb_dmamask = 0xffffffffUL;
734 if (otg_dev->core_if->dma_enable) {
735 dev->dma_mask = &usb_dmamask;
736 dev->coherent_dma_mask = ~0;
738 dev->dma_mask = (void *)0;
739 dev->coherent_dma_mask = 0;
745 * Allocate memory for the base HCD plus the DWC OTG HCD.
746 * Initialize the base HCD.
748 hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
753 hcd->regs = otg_dev->base;
754 hcd->self.otg_port = 1;
756 /* Initialize the DWC OTG HCD. */
757 dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
759 spin_lock_init(&dwc_otg_hcd->global_lock);
761 dwc_otg_hcd->core_if = otg_dev->core_if;
762 otg_dev->hcd = dwc_otg_hcd;
764 #ifdef CONFIG_USB20_OTG_EN
765 dwc_otg_hcd->host_enabled = 1;
767 dwc_otg_hcd->host_enabled = 0;
770 /* Register the HCD CIL Callbacks */
771 dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
772 &hcd_cil_callbacks, hcd);
774 /* Initialize the non-periodic schedule. */
775 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
776 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
778 /* Initialize the periodic schedule. */
779 INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
780 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
781 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
782 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
785 * Create a host channel descriptor for each host channel implemented
786 * in the controller. Initialize the channel descriptor array.
788 INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
789 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
790 for (i = 0; i < num_channels; i++) {
791 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
792 if (channel == NULL) {
794 DWC_ERROR("%s: host channel allocation failed\n", __func__);
797 memset(channel, 0, sizeof(dwc_hc_t));
799 dwc_otg_hcd->hc_ptr_array[i] = channel;
801 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
804 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
807 /* Initialize the Connection timeout timer. */
808 // init_timer( &dwc_otg_hcd->conn_timer );
810 /* Initialize reset tasklet. */
811 reset_tasklet.data = (unsigned long) dwc_otg_hcd;
812 dwc_otg_hcd->reset_tasklet = &reset_tasklet;
814 * Finish generic HCD initialization and start the HCD. This function
815 * allocates the DMA buffer pool, registers the USB bus, requests the
816 * IRQ line, and calls dwc_otg_hcd_start method.
818 retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
821 DWC_ERROR("usb_add_hcd fail,everest\n");
825 * Allocate space for storing data on status transactions. Normally no
826 * data is sent, but this space acts as a bit bucket. This must be
827 * done after usb_add_hcd since that function allocates the DMA buffer
830 if (otg_dev->core_if->dma_enable) {
831 dwc_otg_hcd->status_buf =
832 dma_alloc_coherent(dev,
833 DWC_OTG_HCD_STATUS_BUF_SIZE,
834 &dwc_otg_hcd->status_buf_dma,
835 GFP_KERNEL | GFP_DMA);
837 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
840 if (dwc_otg_hcd->status_buf == NULL) {
842 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
846 // DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
847 // dev->bus_id, hcd->self.busnum);
851 /* Error conditions */
855 dwc_otg_hcd_free(hcd);
859 DWC_PRINT("dwc_otg_hcd_init error,everest\n");
863 #ifdef CONFIG_USB11_HOST
865 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
866 .start = dwc_otg_hcd_start_cb,
867 .stop = dwc_otg_hcd_stop_cb,
868 .disconnect = dwc_otg_hcd_disconnect_cb,
869 .session_start = dwc_otg_hcd_session_start_cb,
873 static struct tasklet_struct host11_reset_tasklet = {
876 .count = ATOMIC_INIT(0),
877 .func = reset_tasklet_func,
881 int __devinit host11_hcd_init(struct device *dev)
883 struct usb_hcd *hcd = NULL;
884 dwc_otg_hcd_t *dwc_otg_hcd = NULL;
885 dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
892 #if 1 //kaiker .these code must execute before usb_create_hcd
893 /* Set device flags indicating whether the HCD supports DMA. */
894 static u64 usb_dmamask = 0xffffffffUL;
895 if (otg_dev->core_if->dma_enable) {
896 // DWC_PRINT("Using DMA mode\n");
897 dev->dma_mask = &usb_dmamask;
898 dev->coherent_dma_mask = ~0;
900 // DWC_PRINT("Using Slave mode\n");
901 dev->dma_mask = (void *)0;
902 dev->coherent_dma_mask = 0;
907 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
910 * Allocate memory for the base HCD plus the DWC OTG HCD.
911 * Initialize the base HCD.
913 hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
918 hcd->regs = otg_dev->base;
919 hcd->self.otg_port = 1;
921 /* Initialize the DWC OTG HCD. */
922 dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
923 dwc_otg_hcd->core_if = otg_dev->core_if;
924 otg_dev->hcd = dwc_otg_hcd;
926 #ifdef CONFIG_USB11_HOST_EN
927 dwc_otg_hcd->host_enabled = 1;
929 dwc_otg_hcd->host_enabled = 0;
932 spin_lock_init(&dwc_otg_hcd->global_lock);
935 /* Register the HCD CIL Callbacks */
936 dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
937 &host11_cil_callbacks, hcd);
939 /* Initialize the non-periodic schedule. */
940 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
941 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
943 /* Initialize the periodic schedule. */
944 INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
945 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
946 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
947 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
950 * Create a host channel descriptor for each host channel implemented
951 * in the controller. Initialize the channel descriptor array.
953 INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
954 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
955 for (i = 0; i < num_channels; i++) {
956 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
957 if (channel == NULL) {
959 DWC_ERROR("%s: host channel allocation failed\n", __func__);
962 memset(channel, 0, sizeof(dwc_hc_t));
964 dwc_otg_hcd->hc_ptr_array[i] = channel;
966 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
969 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
972 /* Initialize the Connection timeout timer. */
973 // init_timer( &dwc_otg_hcd->conn_timer );
975 /* Initialize reset tasklet. */
976 host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
977 dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
979 * Finish generic HCD initialization and start the HCD. This function
980 * allocates the DMA buffer pool, registers the USB bus, requests the
981 * IRQ line, and calls dwc_otg_hcd_start method.
983 retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
986 DWC_ERROR("usb_add_hcd fail,everest\n");
990 * Allocate space for storing data on status transactions. Normally no
991 * data is sent, but this space acts as a bit bucket. This must be
992 * done after usb_add_hcd since that function allocates the DMA buffer
995 if (otg_dev->core_if->dma_enable) {
996 dwc_otg_hcd->status_buf =
997 dma_alloc_coherent(dev,
998 DWC_OTG_HCD_STATUS_BUF_SIZE,
999 &dwc_otg_hcd->status_buf_dma,
1000 GFP_KERNEL | GFP_DMA);
1002 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1005 if (dwc_otg_hcd->status_buf == NULL) {
1007 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1011 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
1012 _lmdev->dev.bus_id, hcd->self.busnum);
1016 /* Error conditions */
1018 usb_remove_hcd(hcd);
1020 dwc_otg_hcd_free(hcd);
1024 DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1028 #ifdef CONFIG_USB20_HOST
1031 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1032 .start = dwc_otg_hcd_start_cb,
1033 .stop = dwc_otg_hcd_stop_cb,
1034 .disconnect = dwc_otg_hcd_disconnect_cb,
1035 .session_start = dwc_otg_hcd_session_start_cb,
1039 static struct tasklet_struct host20_reset_tasklet = {
1042 .count = ATOMIC_INIT(0),
1043 .func = reset_tasklet_func,
1047 int __devinit host20_hcd_init(struct device *dev)
1049 struct usb_hcd *hcd = NULL;
1050 dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1051 dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1058 #if 1 //kaiker .these code must execute before usb_create_hcd
1059 /* Set device flags indicating whether the HCD supports DMA. */
1060 static u64 usb_dmamask = 0xffffffffUL;
1061 if (otg_dev->core_if->dma_enable) {
1062 // DWC_PRINT("Using DMA mode\n");
1063 dev->dma_mask = &usb_dmamask;
1064 dev->coherent_dma_mask = ~0;
1066 // DWC_PRINT("Using Slave mode\n");
1067 dev->dma_mask = (void *)0;
1068 dev->coherent_dma_mask = 0;
1071 // g_dbg_lvl = 0xff;
1073 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1076 * Allocate memory for the base HCD plus the DWC OTG HCD.
1077 * Initialize the base HCD.
1079 hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1084 hcd->regs = otg_dev->base;
1085 hcd->self.otg_port = 1;
1087 /* Initialize the DWC OTG HCD. */
1088 dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1089 dwc_otg_hcd->core_if = otg_dev->core_if;
1090 otg_dev->hcd = dwc_otg_hcd;
1092 #ifdef CONFIG_USB20_HOST_EN
1093 dwc_otg_hcd->host_enabled = 1;
1095 dwc_otg_hcd->host_enabled = 0;
1098 spin_lock_init(&dwc_otg_hcd->global_lock);
1100 /* Register the HCD CIL Callbacks */
1101 dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1102 &host20_cil_callbacks, hcd);
1104 /* Initialize the non-periodic schedule. */
1105 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1106 INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1108 /* Initialize the periodic schedule. */
1109 INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1110 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1111 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1112 // INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1115 * Create a host channel descriptor for each host channel implemented
1116 * in the controller. Initialize the channel descriptor array.
1118 INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1119 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1120 for (i = 0; i < num_channels; i++) {
1121 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1122 if (channel == NULL) {
1124 DWC_ERROR("%s: host channel allocation failed\n", __func__);
1127 memset(channel, 0, sizeof(dwc_hc_t));
1128 channel->hc_num = i;
1129 dwc_otg_hcd->hc_ptr_array[i] = channel;
1131 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1134 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1137 /* Initialize the Connection timeout timer. */
1138 //init_timer( &dwc_otg_hcd->conn_timer );
1140 /* Initialize reset tasklet. */
1141 host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1142 dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1144 * Finish generic HCD initialization and start the HCD. This function
1145 * allocates the DMA buffer pool, registers the USB bus, requests the
1146 * IRQ line, and calls dwc_otg_hcd_start method.
1148 retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1151 DWC_ERROR("usb_add_hcd fail,everest\n");
1155 * Allocate space for storing data on status transactions. Normally no
1156 * data is sent, but this space acts as a bit bucket. This must be
1157 * done after usb_add_hcd since that function allocates the DMA buffer
1160 if (otg_dev->core_if->dma_enable) {
1161 dwc_otg_hcd->status_buf =
1162 dma_alloc_coherent(dev,
1163 DWC_OTG_HCD_STATUS_BUF_SIZE,
1164 &dwc_otg_hcd->status_buf_dma,
1165 GFP_KERNEL | GFP_DMA);
1167 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1170 if (dwc_otg_hcd->status_buf == NULL) {
1172 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1176 #ifndef CONFIG_ARCH_RK29
1177 dwc_otg_hcd->host_setenable = 1;
1178 dwc_otg_hcd->connect_detect_timer.function = dwc_otg_hcd_connect_detect;
1179 dwc_otg_hcd->connect_detect_timer.data = (unsigned long)(dwc_otg_hcd);
1180 init_timer( &dwc_otg_hcd->connect_detect_timer);
1181 mod_timer(&dwc_otg_hcd->connect_detect_timer, jiffies+(HZ<<3));
1183 INIT_DELAYED_WORK(&dwc_otg_hcd->host_enable_work, dwc_otg_hcd_enable);
1187 /* Error conditions */
1189 usb_remove_hcd(hcd);
1191 dwc_otg_hcd_free(hcd);
1195 DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1203 * Frees memory and resources associated with the HCD and deregisters the bus.
1205 void dwc_otg_hcd_remove(struct device *dev)
1207 dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1208 dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1209 struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1211 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1213 /* Turn off all interrupts */
1214 dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1215 dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1217 usb_remove_hcd(hcd);
1218 dwc_otg_hcd_free(hcd);
1225 /* =========================================================================
1226 * Linux HC Driver Functions
1227 * ========================================================================= */
1230 * Initializes dynamic portions of the DWC_otg HCD state.
1232 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1234 struct list_head *item;
1240 DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1242 _hcd->flags.d32 = 0;
1244 _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1245 _hcd->non_periodic_channels = 0;
1246 _hcd->periodic_channels = 0;
1249 * Put all channels in the free channel list and clean up channel
1252 item = _hcd->free_hc_list.next;
1253 while (item != &_hcd->free_hc_list) {
1255 item = _hcd->free_hc_list.next;
1258 num_channels = _hcd->core_if->core_params->host_channels;
1259 for (i = 0; i < num_channels; i++) {
1260 channel = _hcd->hc_ptr_array[i];
1261 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1262 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1265 /* Initialize the DWC core for host mode operation. */
1266 dwc_otg_core_host_init(_hcd->core_if);
1269 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1270 * mode operation. Activates the root port. Returns 0 on success and a negative
1271 * error code on failure. */
1272 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1274 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1275 dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1276 unsigned long flags;
1278 struct usb_bus *bus;
1280 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1281 local_irq_save(flags);
1283 bus = hcd_to_bus(_hcd);
1284 _hcd->state = HC_STATE_RUNNING;
1286 /* Initialize and connect root hub if one is not already attached */
1287 if (bus->root_hub) {
1288 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1289 /* Inform the HUB driver to resume. */
1290 usb_hcd_resume_root_hub(_hcd);
1296 struct usb_device *udev;6
1297 udev = usb_alloc_dev(NULL, bus, 0);
1298 udev->speed = USB_SPEED_HIGH;
1300 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1305 if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1306 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1311 /* Initialize the bus state. If the core is in Device Mode
1312 * HALT the USB bus and return. */
1313 if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1314 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1315 //_hcd->state = HC_STATE_HALT;
1318 hcd_reinit(dwc_otg_hcd);
1320 local_irq_restore(flags);
1325 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1327 struct list_head *item;
1330 if (_qh_list->next == NULL) {
1331 /* The list hasn't been initialized yet. */
1335 /* Ensure there are no QTDs or URBs left. */
1336 kill_urbs_in_qh_list(_hcd, _qh_list);
1338 for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1339 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1340 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1345 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1348 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1350 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1351 hprt0_data_t hprt0 = { .d32=0 };
1352 struct dwc_otg_platform_data *pldata;
1353 pldata = dwc_otg_hcd->core_if->otg_dev->pldata;
1355 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1357 /* Turn off all host-specific interrupts. */
1358 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1361 * The root hub should be disconnected before this function is called.
1362 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1363 * and the QH lists (via ..._hcd_endpoint_disable).
1366 /* Turn off the vbus power */
1367 DWC_PRINT("PortPower off\n");
1369 dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1371 if(pldata->power_enable)
1372 pldata->power_enable(0);
1377 /** Returns the current frame number. */
1378 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1380 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1383 hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1384 host_if->host_global_regs->hfnum);
1387 DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1389 return hfnum.b.frnum;
1393 * Frees secondary storage associated with the dwc_otg_hcd structure contained
1394 * in the struct usb_hcd field.
1396 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1398 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1401 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1403 // del_timers(dwc_otg_hcd);
1405 /* Free memory for QH/QTD lists */
1406 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1407 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1408 qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1409 // qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1410 // qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1411 // qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1413 /* Free memory for the host channels. */
1414 for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1415 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1417 DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1422 if (dwc_otg_hcd->core_if->dma_enable) {
1423 if (dwc_otg_hcd->status_buf_dma) {
1424 dma_free_coherent(_hcd->self.controller,
1425 DWC_OTG_HCD_STATUS_BUF_SIZE,
1426 dwc_otg_hcd->status_buf,
1427 dwc_otg_hcd->status_buf_dma);
1429 } else if (dwc_otg_hcd->status_buf != NULL) {
1430 kfree(dwc_otg_hcd->status_buf);
1437 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1439 DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe));
1440 DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1441 (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1442 DWC_PRINT(" Endpoint type: %s\n",
1444 switch (usb_pipetype(_urb->pipe)) {
1445 case PIPE_CONTROL: pipetype = "CONTROL"; break;
1446 case PIPE_BULK: pipetype = "BULK"; break;
1447 case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1448 case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1449 default: pipetype = "UNKNOWN"; break;
1451 DWC_PRINT(" Speed: %s\n",
1453 switch (_urb->dev->speed) {
1454 case USB_SPEED_HIGH: speed = "HIGH"; break;
1455 case USB_SPEED_FULL: speed = "FULL"; break;
1456 case USB_SPEED_LOW: speed = "LOW"; break;
1457 default: speed = "UNKNOWN"; break;
1459 DWC_PRINT(" Max packet size: %d\n",
1460 usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1461 DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length);
1462 DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n",
1463 _urb->transfer_buffer, (void *)_urb->transfer_dma);
1464 DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n",
1465 _urb->setup_packet, (void *)_urb->setup_dma);
1466 DWC_PRINT(" Interval: %d\n", _urb->interval);
1467 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1469 for (i = 0; i < _urb->number_of_packets; i++) {
1470 DWC_PRINT(" ISO Desc %d:\n", i);
1471 DWC_PRINT(" offset: %d, length %d\n",
1472 _urb->iso_frame_desc[i].offset,
1473 _urb->iso_frame_desc[i].length);
1478 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1481 if (qh->channel != NULL) {
1482 dwc_hc_t *hc = qh->channel;
1483 struct list_head *item;
1484 dwc_otg_qh_t *qh_item;
1485 int num_channels = _hcd->core_if->core_params->host_channels;
1488 dwc_otg_hc_regs_t *hc_regs;
1489 hcchar_data_t hcchar;
1490 hcsplt_data_t hcsplt;
1491 hctsiz_data_t hctsiz;
1494 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1495 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1496 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1497 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1498 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1500 DWC_PRINT(" Assigned to channel %p:\n", hc);
1501 DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1502 DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1503 DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1504 hc->dev_addr, hc->ep_num, hc->ep_is_in);
1505 DWC_PRINT(" ep_type: %d\n", hc->ep_type);
1506 DWC_PRINT(" max_packet: %d\n", hc->max_packet);
1507 DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
1508 DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
1509 DWC_PRINT(" halt_status: %d\n", hc->halt_status);
1510 DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
1511 DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
1512 DWC_PRINT(" qh: %p\n", hc->qh);
1513 DWC_PRINT(" NP inactive sched:\n");
1514 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1515 qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1516 DWC_PRINT(" %p\n", qh_item);
1518 DWC_PRINT(" NP active sched:\n");
1519 list_for_each(item, &_hcd->non_periodic_sched_active) {
1520 qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1521 DWC_PRINT(" %p\n", qh_item);
1523 DWC_PRINT(" Channels: \n");
1524 for (i = 0; i < num_channels; i++) {
1525 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1526 DWC_PRINT(" %2d: %p\n", i, hc);
1532 /** Starts processing a USB transfer request specified by a USB Request Block
1533 * (URB). mem_flags indicates the type of memory allocation to use while
1534 * processing this URB. */
1535 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1540 dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1541 dwc_otg_qtd_t * qtd;
1543 if(atomic_read(&_urb->use_count)>1){
1546 DWC_PRINT("%s urb %p already in queue, qtd %p, count%d\n", __func__, _urb, _urb->hcpriv, atomic_read(&_urb->use_count));
1549 if((uint32_t)_urb->transfer_buffer & 3){
1551 DWC_PRINT("%s urb->transfer_buffer address not align to 4-byte 0x%x\n", __func__, (uint32_t)_urb->transfer_buffer);
1555 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1556 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1559 if (!dwc_otg_hcd->flags.b.port_connect_status) {
1560 DWC_ERROR("DWC OTG No longer connected\n");
1561 /* No longer connected. */
1565 qtd = dwc_otg_hcd_qtd_create(_urb);
1567 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1571 retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1573 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1574 "Error status %d\n", retval);
1575 dwc_otg_hcd_qtd_free(qtd);
1579 * Make sure the start of frame interrupt is enabled now that
1580 * we know we should have queued data. The SOF interrupt
1581 * handler automatically disables itself when idle to reduce
1582 * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1585 dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1592 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1594 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1596 unsigned long flags;
1597 dwc_otg_hcd_t * dwc_otg_hcd;
1598 dwc_otg_qtd_t * urb_qtd;
1600 struct usb_host_endpoint *_ep;
1602 dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1603 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1605 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1607 if(((uint32_t)_urb&0xf0000000)==0)
1608 DWC_PRINT("%s urb is %p\n", __func__, _urb);
1610 _ep = dwc_urb_to_endpoint(_urb);
1613 DWC_PRINT("%s=====================================================\n",__func__);
1614 DWC_PRINT("urb->ep is null\n");
1618 urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1619 if(((uint32_t)urb_qtd&0xf0000000) == 0)
1621 DWC_PRINT("%s,urb_qtd is %p urb %p, count %d\n",__func__, urb_qtd, _urb, atomic_read(&_urb->use_count));
1622 if((atomic_read(&_urb->use_count)) == 1)
1625 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1629 qh = (dwc_otg_qh_t *) _ep->hcpriv;
1632 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1633 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1634 if (urb_qtd == qh->qtd_in_process) {
1635 dump_channel_info(dwc_otg_hcd, qh);
1641 if (urb_qtd == qh->qtd_in_process) {
1642 /* The QTD is in process (it has been assigned to a channel). */
1643 if (dwc_otg_hcd->flags.b.port_connect_status) {
1645 * If still connected (i.e. in host mode), halt the
1646 * channel so it can be used for other transfers. If
1647 * no longer connected, the host registers can't be
1648 * written to halt the channel since the core is in
1651 dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1652 DWC_OTG_HC_XFER_URB_DEQUEUE);
1657 * Free the QTD and clean up the associated QH. Leave the QH in the
1658 * schedule if it has any remaining QTDs.
1660 dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1661 if (urb_qtd == qh->qtd_in_process) {
1662 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1664 qh->qtd_in_process = NULL;
1665 } else if (list_empty(&qh->qtd_list)) {
1666 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1669 _urb->hcpriv = NULL;
1670 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1671 /* Higher layer software sets URB status. */
1672 usb_hcd_giveback_urb(_hcd, _urb, _status);
1673 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1674 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1675 DWC_PRINT(" urb->status = %d\n", _status);
1681 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1682 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1683 * must already be dequeued. */
1684 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1685 struct usb_host_endpoint *_ep)
1688 unsigned long flags;
1690 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1692 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1694 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1695 "endpoint=%d\n", _ep->desc.bEndpointAddress,
1696 dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1698 qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1701 /** Check that the QTD list is really empty */
1702 if (!list_empty(&qh->qtd_list)) {
1703 DWC_WARN("DWC OTG HCD EP DISABLE:"
1704 " QTD List for this endpoint is not empty\n");
1708 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1712 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1717 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1718 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1721 * This function is called by the USB core when an interrupt occurs */
1722 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1725 unsigned long flags;
1726 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1728 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1730 result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1732 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1737 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1738 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1739 * is the status change indicator for the single root port. Returns 1 if either
1740 * change indicator is 1, otherwise returns 0. */
1741 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1744 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1747 _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1748 dwc_otg_hcd->flags.b.port_reset_change ||
1749 dwc_otg_hcd->flags.b.port_enable_change ||
1750 dwc_otg_hcd->flags.b.port_suspend_change ||
1751 dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1755 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1756 " Root port status changed\n");
1757 DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n",
1758 dwc_otg_hcd->flags.b.port_connect_status_change);
1759 DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n",
1760 dwc_otg_hcd->flags.b.port_reset_change);
1761 DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n",
1762 dwc_otg_hcd->flags.b.port_enable_change);
1763 DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n",
1764 dwc_otg_hcd->flags.b.port_suspend_change);
1765 DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n",
1766 dwc_otg_hcd->flags.b.port_over_current_change);
1769 return (_buf[0] != 0);
1772 #ifdef DWC_HS_ELECT_TST
1774 * Quick and dirty hack to implement the HS Electrical Test
1775 * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1777 * This code was copied from our userspace app "hset". It sends a
1778 * Get Device Descriptor control sequence in two parts, first the
1779 * Setup packet by itself, followed some time later by the In and
1780 * Ack packets. Rather than trying to figure out how to add this
1781 * functionality to the normal driver code, we just hijack the
1782 * hardware, using these two function to drive the hardware
1786 dwc_otg_core_global_regs_t *global_regs;
1787 dwc_otg_host_global_regs_t *hc_global_regs;
1788 dwc_otg_hc_regs_t *hc_regs;
1789 uint32_t *data_fifo;
1791 static void do_setup(void)
1793 gintsts_data_t gintsts;
1794 hctsiz_data_t hctsiz;
1795 hcchar_data_t hcchar;
1800 dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1803 dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1806 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1807 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1810 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1811 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1814 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1815 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1818 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1819 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1822 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1825 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1828 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1831 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1832 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1835 * Send Setup packet (Get Device Descriptor)
1838 /* Make sure channel is disabled */
1839 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1840 if (hcchar.b.chen) {
1841 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1843 // hcchar.b.chen = 1;
1844 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1849 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1850 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1853 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1854 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1857 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1858 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1861 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1862 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1865 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1868 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1871 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1873 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1874 //if (hcchar.b.chen) {
1875 // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1881 hctsiz.b.xfersize = 8;
1882 hctsiz.b.pktcnt = 1;
1883 hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1884 dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1887 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1888 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1893 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1895 /* Fill FIFO with Setup data for Get Device Descriptor */
1896 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1897 dwc_write_reg32(data_fifo++, 0x01000680);
1898 dwc_write_reg32(data_fifo++, 0x00080000);
1900 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1901 //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1903 /* Wait for host channel interrupt */
1905 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1906 } while (gintsts.b.hcintr == 0);
1908 //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1910 /* Disable HCINTs */
1911 dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1913 /* Disable HAINTs */
1914 dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1917 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1918 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1921 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1922 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1925 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1926 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1929 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1932 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1935 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1938 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1939 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1942 static void do_in_ack(void)
1944 gintsts_data_t gintsts;
1945 hctsiz_data_t hctsiz;
1946 hcchar_data_t hcchar;
1949 host_grxsts_data_t grxsts;
1952 dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1955 dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1958 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1959 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1962 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1963 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1966 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1967 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1970 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1971 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1974 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1977 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1980 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1983 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1984 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1987 * Receive Control In packet
1990 /* Make sure channel is disabled */
1991 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1992 if (hcchar.b.chen) {
1993 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1996 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2001 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2002 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2005 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2006 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2009 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2010 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2013 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2014 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2017 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2020 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2023 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2025 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2026 //if (hcchar.b.chen) {
2027 // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
2033 hctsiz.b.xfersize = 8;
2034 hctsiz.b.pktcnt = 1;
2035 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2036 dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2039 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2040 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2045 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2047 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2048 //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2050 /* Wait for receive status queue interrupt */
2052 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2053 } while (gintsts.b.rxstsqlvl == 0);
2055 //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2058 grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2059 //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2061 /* Clear RXSTSQLVL in GINTSTS */
2063 gintsts.b.rxstsqlvl = 1;
2064 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2066 switch (grxsts.b.pktsts) {
2067 case DWC_GRXSTS_PKTSTS_IN:
2068 /* Read the data into the host buffer */
2069 if (grxsts.b.bcnt > 0) {
2071 int word_count = (grxsts.b.bcnt + 3) / 4;
2073 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2075 for (i = 0; i < word_count; i++) {
2076 (void)dwc_read_reg32(data_fifo++);
2080 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2084 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2088 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2089 //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2091 /* Wait for receive status queue interrupt */
2093 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2094 } while (gintsts.b.rxstsqlvl == 0);
2096 //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2099 grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2100 //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2102 /* Clear RXSTSQLVL in GINTSTS */
2104 gintsts.b.rxstsqlvl = 1;
2105 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2107 switch (grxsts.b.pktsts) {
2108 case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2112 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2116 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2117 //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2119 /* Wait for host channel interrupt */
2121 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2122 } while (gintsts.b.hcintr == 0);
2124 //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2127 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2128 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2131 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2132 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2135 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2136 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2139 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2142 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2145 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2148 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2149 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2156 * Send handshake packet
2160 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2161 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2164 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2165 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2168 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2169 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2172 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2175 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2178 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2181 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2182 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2184 /* Make sure channel is disabled */
2185 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2186 if (hcchar.b.chen) {
2187 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2190 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2195 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2196 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2199 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2200 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2203 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2204 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2207 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2208 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2211 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2214 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2217 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2219 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2220 //if (hcchar.b.chen) {
2221 // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2227 hctsiz.b.xfersize = 0;
2228 hctsiz.b.pktcnt = 1;
2229 hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2230 dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2233 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2234 hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2239 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2241 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2242 //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2244 /* Wait for host channel interrupt */
2246 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2247 } while (gintsts.b.hcintr == 0);
2249 //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2251 /* Disable HCINTs */
2252 dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2254 /* Disable HAINTs */
2255 dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2258 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2259 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2262 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2263 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2266 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2267 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2270 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2273 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2276 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2279 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2280 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2282 #endif /* DWC_HS_ELECT_TST */
2284 /** Handles hub class-specific requests.*/
2285 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2293 unsigned long flags;
2295 dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2296 dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2297 struct usb_hub_descriptor *desc;
2298 hprt0_data_t hprt0 = {.d32 = 0};
2300 uint32_t port_status;
2301 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2304 case ClearHubFeature:
2305 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2306 "ClearHubFeature 0x%x\n", _wValue);
2308 case C_HUB_LOCAL_POWER:
2309 case C_HUB_OVER_CURRENT:
2310 /* Nothing required here */
2314 DWC_ERROR ("DWC OTG HCD - "
2315 "ClearHubFeature request %xh unknown\n", _wValue);
2318 case ClearPortFeature:
2319 if (!_wIndex || _wIndex > 1)
2323 case USB_PORT_FEAT_ENABLE:
2324 DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2325 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2326 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2328 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2330 case USB_PORT_FEAT_SUSPEND:
2331 #ifdef CONFIG_USB_SUSPEND
2334 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2335 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2336 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2338 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2339 /* Clear Resume bit */
2340 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2342 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2344 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2346 case USB_PORT_FEAT_POWER:
2347 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2348 "ClearPortFeature USB_PORT_FEAT_POWER\n");
2349 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2351 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2353 case USB_PORT_FEAT_INDICATOR:
2354 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2355 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2356 /* Port inidicator not supported */
2358 case USB_PORT_FEAT_C_CONNECTION:
2359 /* Clears drivers internal connect status change
2361 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2362 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2363 dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2365 case USB_PORT_FEAT_C_RESET:
2366 /* Clears the driver's internal Port Reset Change
2368 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2369 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2370 dwc_otg_hcd->flags.b.port_reset_change = 0;
2372 case USB_PORT_FEAT_C_ENABLE:
2373 /* Clears the driver's internal Port
2374 * Enable/Disable Change flag */
2375 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2376 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2377 dwc_otg_hcd->flags.b.port_enable_change = 0;
2379 case USB_PORT_FEAT_C_SUSPEND:
2380 /* Clears the driver's internal Port Suspend
2381 * Change flag, which is set when resume signaling on
2382 * the host port is complete */
2383 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2384 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2385 dwc_otg_hcd->flags.b.port_suspend_change = 0;
2387 case USB_PORT_FEAT_C_OVER_CURRENT:
2388 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2389 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2390 dwc_otg_hcd->flags.b.port_over_current_change = 0;
2394 DWC_ERROR ("DWC OTG HCD - "
2395 "ClearPortFeature request %xh "
2396 "unknown or unsupported\n", _wValue);
2399 case GetHubDescriptor:
2400 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2401 "GetHubDescriptor\n");
2402 desc = (struct usb_hub_descriptor *)_buf;
2403 desc->bDescLength = 9;
2404 desc->bDescriptorType = 0x29;
2405 desc->bNbrPorts = 1;
2406 desc->wHubCharacteristics = 0x08;
2407 desc->bPwrOn2PwrGood = 1;
2408 desc->bHubContrCurrent = 0;
2409 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
2410 desc->u.hs.DeviceRemovable[0] = 0;
2411 desc->u.hs.DeviceRemovable[1] = 0xff;
2413 desc->bitmap[0] = 0;
2414 desc->bitmap[1] = 0xff;
2418 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2420 memset (_buf, 0, 4);
2423 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2426 if (!_wIndex || _wIndex > 1)
2431 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2432 port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2434 if (dwc_otg_hcd->flags.b.port_enable_change)
2435 port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2437 if (dwc_otg_hcd->flags.b.port_suspend_change)
2438 port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2440 if (dwc_otg_hcd->flags.b.port_reset_change)
2441 port_status |= (1 << USB_PORT_FEAT_C_RESET);
2443 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2444 DWC_ERROR("Device Not Supported\n");
2445 port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2448 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2450 * The port is disconnected, which means the core is
2451 * either in device mode or it soon will be. Just
2452 * return 0's for the remainder of the port status
2453 * since the port register can't be read if the core
2454 * is in device mode.
2456 *((__le32 *) _buf) = cpu_to_le32(port_status);
2460 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2461 DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32);
2463 if (hprt0.b.prtconnsts)
2464 port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2467 port_status |= (1 << USB_PORT_FEAT_ENABLE);
2469 if (hprt0.b.prtsusp)
2470 port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2472 if (hprt0.b.prtovrcurract)
2473 port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2476 port_status |= (1 << USB_PORT_FEAT_RESET);
2479 port_status |= (1 << USB_PORT_FEAT_POWER);
2481 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2482 port_status |= USB_PORT_STAT_HIGH_SPEED;
2484 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2485 port_status |= USB_PORT_STAT_LOW_SPEED;
2487 if (hprt0.b.prttstctl)
2488 port_status |= (1 << USB_PORT_FEAT_TEST);
2490 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2492 *((__le32 *) _buf) = cpu_to_le32(port_status);
2496 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2498 /* No HUB features supported */
2500 case SetPortFeature:
2501 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2504 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2506 * The port is disconnected, which means the core is
2507 * either in device mode or it soon will be. Just
2508 * return without doing anything since the port
2509 * register can't be written if the core is in device
2516 case USB_PORT_FEAT_SUSPEND:
2517 #ifdef CONFIG_USB_SUSPEND
2520 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2521 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2522 if (_hcd->self.otg_port == _wIndex &&
2523 _hcd->self.b_hnp_enable) {
2524 gotgctl_data_t gotgctl = {.d32=0};
2525 gotgctl.b.hstsethnpen = 1;
2526 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2528 core_if->op_state = A_SUSPEND;
2530 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2531 hprt0.b.prtsusp = 1;
2532 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2533 //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2534 /* Suspend the Phy Clock */
2536 pcgcctl_data_t pcgcctl = {.d32=0};
2537 pcgcctl.b.stoppclk = 1;
2538 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2541 /* For HNP the bus must be suspended for at least 200ms.*/
2542 if (_hcd->self.b_hnp_enable) {
2543 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2545 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2546 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2549 case USB_PORT_FEAT_POWER:
2550 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2551 "SetPortFeature - USB_PORT_FEAT_POWER\n");
2552 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2554 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2556 case USB_PORT_FEAT_RESET:
2557 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2558 "SetPortFeature - USB_PORT_FEAT_RESET\n");
2559 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2560 /* When B-Host the Port reset bit is set in
2561 * the Start HCD Callback function, so that
2562 * the reset is started within 1ms of the HNP
2563 * success interrupt. */
2564 if (!_hcd->self.is_b_host) {
2566 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2568 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2569 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2570 // kever @rk 20110712
2571 // can not use mdelay(60) while irq disable
2574 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2576 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2579 #ifdef DWC_HS_ELECT_TST
2580 case USB_PORT_FEAT_TEST:
2583 gintmsk_data_t gintmsk;
2585 t = (_wIndex >> 8); /* MSB wIndex USB */
2586 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2587 "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2588 warn("USB_PORT_FEAT_TEST %d\n", t);
2590 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2591 hprt0.b.prttstctl = t;
2592 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2594 /* Setup global vars with reg addresses (quick and
2595 * dirty hack, should be cleaned up)
2597 global_regs = core_if->core_global_regs;
2598 hc_global_regs = core_if->host_if->host_global_regs;
2599 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2600 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2602 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2603 /* Save current interrupt mask */
2604 gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2606 /* Disable all interrupts while we muck with
2607 * the hardware directly
2609 dwc_write_reg32(&global_regs->gintmsk, 0);
2611 /* 15 second delay per the test spec */
2614 /* Drive suspend on the root port */
2615 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2616 hprt0.b.prtsusp = 1;
2618 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2620 /* 15 second delay per the test spec */
2623 /* Drive resume on the root port */
2624 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2625 hprt0.b.prtsusp = 0;
2627 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2630 /* Clear the resume bit */
2632 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2634 /* Restore interrupts */
2635 dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2636 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2637 /* Save current interrupt mask */
2638 gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2640 /* Disable all interrupts while we muck with
2641 * the hardware directly
2643 dwc_write_reg32(&global_regs->gintmsk, 0);
2645 /* 15 second delay per the test spec */
2648 /* Send the Setup packet */
2651 /* 15 second delay so nothing else happens for awhile */
2654 /* Restore interrupts */
2655 dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2656 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2657 /* Save current interrupt mask */
2658 gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2660 /* Disable all interrupts while we muck with
2661 * the hardware directly
2663 dwc_write_reg32(&global_regs->gintmsk, 0);
2665 /* Send the Setup packet */
2668 /* 15 second delay so nothing else happens for awhile */
2671 /* Send the In and Ack packets */
2674 /* 15 second delay so nothing else happens for awhile */
2677 /* Restore interrupts */
2678 dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2683 #endif /* DWC_HS_ELECT_TST */
2685 case USB_PORT_FEAT_INDICATOR:
2686 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2687 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2692 DWC_ERROR ("DWC OTG HCD - "
2693 "SetPortFeature request %xh "
2694 "unknown or unsupported\n", _wValue);
2701 DWC_WARN ("DWC OTG HCD - "
2702 "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2703 _typeReq, _wIndex, _wValue);
2707 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2713 * Assigns transactions from a QTD to a free host channel and initializes the
2714 * host channel to perform the transactions. The host channel is removed from
2717 * @param _hcd The HCD state structure.
2718 * @param _qh Transactions from the first QTD for this QH are selected and
2719 * assigned to a free host channel.
2721 static int assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2728 DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2729 hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2731 /* Remove the host channel from the free list. */
2732 list_del_init(&hc->hc_list_entry);
2734 qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2737 printk("%s : urb is NULL\n", __func__);
2742 _qh->qtd_in_process = qtd;
2745 * Use usb_pipedevice to determine device address. This address is
2746 * 0 before the SET_ADDRESS command and the correct address afterward.
2748 hc->dev_addr = usb_pipedevice(urb->pipe);
2749 hc->ep_num = usb_pipeendpoint(urb->pipe);
2751 if (urb->dev->speed == USB_SPEED_LOW) {
2752 hc->speed = DWC_OTG_EP_SPEED_LOW;
2754 * yk@rk 20101216 fix bandwidth check error when full/low speed
2757 _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2758 } else if (urb->dev->speed == USB_SPEED_FULL) {
2759 hc->speed = DWC_OTG_EP_SPEED_FULL;
2761 * yk@rk 20101216 fix bandwidth check error when full/low speed
2762 * device connected. warning: only support 1 device at root hub.
2764 _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2766 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2769 hc->max_packet = dwc_max_packet(_qh->maxp);
2771 hc->xfer_started = 0;
2772 hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2773 hc->error_state = (qtd->error_count > 0);
2774 hc->halt_on_queue = 0;
2775 hc->halt_pending = 0;
2779 * The following values may be modified in the transfer type section
2780 * below. The xfer_len value may be reduced when the transfer is
2781 * started to accommodate the max widths of the XferSize and PktCnt
2782 * fields in the HCTSIZn register.
2784 hc->do_ping = _qh->ping_state;
2785 hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2786 hc->data_pid_start = _qh->data_toggle;
2787 hc->multi_count = 1;
2789 if (_hcd->core_if->dma_enable) {
2790 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2792 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2794 hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2798 * Set the split attributes
2801 if (_qh->do_split) {
2803 hc->xact_pos = qtd->isoc_split_pos;
2804 hc->complete_split = qtd->complete_split;
2805 hc->hub_addr = urb->dev->tt->hub->devnum;
2806 hc->port_addr = urb->dev->ttport;
2809 switch (usb_pipetype(urb->pipe)) {
2811 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2812 switch (qtd->control_phase) {
2813 case DWC_OTG_CONTROL_SETUP:
2814 DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n");
2817 hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2818 if (_hcd->core_if->dma_enable) {
2819 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2821 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2825 case DWC_OTG_CONTROL_DATA:
2826 DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n");
2827 hc->data_pid_start = qtd->data_toggle;
2829 case DWC_OTG_CONTROL_STATUS:
2831 * Direction is opposite of data direction or IN if no
2834 DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n");
2835 if (urb->transfer_buffer_length == 0) {
2838 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2843 hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2845 if (_hcd->core_if->dma_enable) {
2846 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2848 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2854 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2856 case PIPE_INTERRUPT:
2857 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2859 case PIPE_ISOCHRONOUS:
2861 struct usb_iso_packet_descriptor *frame_desc;
2862 frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2863 hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2864 if (_hcd->core_if->dma_enable) {
2865 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2867 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2869 hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2870 hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2872 if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2873 if (hc->xfer_len <= 188) {
2874 hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2877 hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2884 if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2885 hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2887 * This value may be modified when the transfer is started to
2888 * reflect the actual transfer length.
2890 hc->multi_count = dwc_hb_mult(_qh->maxp);
2893 dwc_otg_hc_init(_hcd->core_if, hc);
2900 * This function selects transactions from the HCD transfer schedule and
2901 * assigns them to available host channels. It is called from HCD interrupt
2902 * handler functions.
2904 * @param _hcd The HCD state structure.
2906 * @return The types of new transactions that were assigned to host channels.
2908 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2910 struct list_head *qh_ptr;
2913 dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE;
2917 DWC_DEBUGPL(DBG_HCD, " Select Transactions\n");
2920 /* Process entries in the periodic ready list. */
2921 qh_ptr = _hcd->periodic_sched_inactive.next;
2922 while ((qh_ptr != &_hcd->periodic_sched_inactive)&&
2923 !list_empty(&_hcd->free_hc_list)) {
2924 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2925 if(qh->qh_state != QH_READY){
2926 qh_ptr = qh_ptr->next;
2930 assign_and_init_hc(_hcd, qh);
2933 * Move the QH from the periodic ready schedule to the
2934 * periodic assigned schedule.
2936 qh_ptr = qh_ptr->next;
2937 //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2938 qh->qh_state = QH_ASSIGNED;
2940 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2944 * Process entries in the inactive portion of the non-periodic
2945 * schedule. Some free host channels may not be used if they are
2946 * reserved for periodic transfers.
2948 qh_ptr = _hcd->non_periodic_sched_inactive.next;
2949 num_channels = _hcd->core_if->core_params->host_channels;
2950 while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2952 (_hcd->non_periodic_channels <
2953 num_channels - _hcd->periodic_channels) &&
2955 !list_empty(&_hcd->free_hc_list)) {
2957 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2958 err = assign_and_init_hc(_hcd, qh);
2961 * Move the QH from the non-periodic inactive schedule to the
2962 * non-periodic active schedule.
2964 qh_ptr = qh_ptr->next;
2967 list_move_tail(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2969 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2970 ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2972 ret_val = DWC_OTG_TRANSACTION_ALL;
2975 _hcd->non_periodic_channels++;
2982 * Attempts to queue a single transaction request for a host channel
2983 * associated with either a periodic or non-periodic transfer. This function
2984 * assumes that there is space available in the appropriate request queue. For
2985 * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2986 * is available in the appropriate Tx FIFO.
2988 * @param _hcd The HCD state structure.
2989 * @param _hc Host channel descriptor associated with either a periodic or
2990 * non-periodic transfer.
2991 * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2992 * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2995 * @return 1 if a request is queued and more requests may be needed to
2996 * complete the transfer, 0 if no more requests are required for this
2997 * transfer, -1 if there is insufficient space in the Tx FIFO.
2999 static int queue_transaction(dwc_otg_hcd_t *_hcd,
3001 uint16_t _fifo_dwords_avail)
3005 if (_hcd->core_if->dma_enable) {
3006 if (!_hc->xfer_started) {
3007 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3008 _hc->qh->ping_state = 0;
3011 } else if (_hc->halt_pending) {
3012 /* Don't queue a request if the channel has been halted. */
3014 } else if (_hc->halt_on_queue) {
3015 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
3017 } else if (_hc->do_ping) {
3018 if (!_hc->xfer_started) {
3019 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3022 } else if (!_hc->ep_is_in ||
3023 _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3024 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
3025 if (!_hc->xfer_started) {
3026 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3029 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3035 if (!_hc->xfer_started) {
3036 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3039 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3047 * Processes active non-periodic channels and queues transactions for these
3048 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3049 * FIFO Empty interrupt is enabled if there are more transactions to queue as
3050 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3051 * FIFO Empty interrupt is disabled.
3053 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
3055 gnptxsts_data_t tx_status;
3056 struct list_head *orig_qh_ptr;
3059 int no_queue_space = 0;
3060 int no_fifo_space = 0;
3063 dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
3065 DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
3067 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3068 DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n",
3069 tx_status.b.nptxqspcavail);
3070 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n",
3071 tx_status.b.nptxfspcavail);
3074 * Keep track of the starting point. Skip over the start-of-list
3077 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3078 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3080 orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3083 * Process once through the active list or until no more space is
3084 * available in the request queue or the Tx FIFO.
3087 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3088 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3093 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3094 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3098 } else if (status < 0) {
3103 /* Advance to next QH, skipping start-of-list entry. */
3104 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3105 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3106 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3109 } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3111 if (!_hcd->core_if->dma_enable) {
3112 gintmsk_data_t intr_mask = {.d32 = 0};
3113 intr_mask.b.nptxfempty = 1;
3116 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3117 DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n",
3118 tx_status.b.nptxqspcavail);
3119 DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n",
3120 tx_status.b.nptxfspcavail);
3122 if (more_to_do || no_queue_space || no_fifo_space) {
3124 * May need to queue more transactions as the request
3125 * queue or Tx FIFO empties. Enable the non-periodic
3126 * Tx FIFO empty interrupt. (Always use the half-empty
3127 * level to ensure that new requests are loaded as
3128 * soon as possible.)
3130 dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3133 * Disable the Tx FIFO empty interrupt since there are
3134 * no more transactions that need to be queued right
3135 * now. This function is called from interrupt
3136 * handlers to queue more transactions as transfer
3139 dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3145 * Processes periodic channels for the next frame and queues transactions for
3146 * these channels to the DWC_otg controller. After queueing transactions, the
3147 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3148 * to queue as Periodic Tx FIFO or request queue space becomes available.
3149 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3151 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3153 hptxsts_data_t tx_status;
3154 struct list_head *qh_ptr;
3157 int no_queue_space = 0;
3158 int no_fifo_space = 0;
3160 dwc_otg_host_global_regs_t *host_regs;
3161 host_regs = _hcd->core_if->host_if->host_global_regs;
3163 DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3165 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3166 DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n",
3167 tx_status.b.ptxqspcavail);
3168 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n",
3169 tx_status.b.ptxfspcavail);
3172 qh_ptr = _hcd->periodic_sched_inactive.next;
3173 while (qh_ptr != &_hcd->periodic_sched_inactive) {
3174 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3175 if (tx_status.b.ptxqspcavail == 0) {
3180 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3181 if(qh->qh_state != QH_ASSIGNED){
3182 qh_ptr = qh_ptr->next;
3187 * Set a flag if we're queuing high-bandwidth in slave mode.
3188 * The flag prevents any halts to get into the request queue in
3189 * the middle of multiple high-bandwidth packets getting queued.
3191 if ((!_hcd->core_if->dma_enable) &&
3192 (qh->channel->multi_count > 1))
3194 _hcd->core_if->queuing_high_bandwidth = 1;
3197 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3204 * In Slave mode, stay on the current transfer until there is
3205 * nothing more to do or the high-bandwidth request count is
3206 * reached. In DMA mode, only need to queue one request. The
3207 * controller automatically handles multiple packets for
3208 * high-bandwidth transfers.
3210 if (_hcd->core_if->dma_enable ||
3212 qh->channel->requests == qh->channel->multi_count)) {
3213 qh_ptr = qh_ptr->next;
3215 * Move the QH from the periodic assigned schedule to
3216 * the periodic queued schedule.
3218 //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3219 qh->qh_state = QH_QUEUED;
3221 /* done queuing high bandwidth */
3222 _hcd->core_if->queuing_high_bandwidth = 0;
3226 if (!_hcd->core_if->dma_enable) {
3227 dwc_otg_core_global_regs_t *global_regs;
3228 gintmsk_data_t intr_mask = {.d32 = 0};
3230 global_regs = _hcd->core_if->core_global_regs;
3231 intr_mask.b.ptxfempty = 1;
3233 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3234 DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n",
3235 tx_status.b.ptxqspcavail);
3236 DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n",
3237 tx_status.b.ptxfspcavail);
3239 if (//!(list_empty(&_hcd->periodic_sched_assigned)) ||
3240 no_queue_space || no_fifo_space) {
3242 * May need to queue more transactions as the request
3243 * queue or Tx FIFO empties. Enable the periodic Tx
3244 * FIFO empty interrupt. (Always use the half-empty
3245 * level to ensure that new requests are loaded as
3246 * soon as possible.)
3248 dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3251 * Disable the Tx FIFO empty interrupt since there are
3252 * no more transactions that need to be queued right
3253 * now. This function is called from interrupt
3254 * handlers to queue more transactions as transfer
3257 dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3263 * This function processes the currently active host channels and queues
3264 * transactions for these channels to the DWC_otg controller. It is called
3265 * from HCD interrupt handler functions.
3267 * @param _hcd The HCD state structure.
3268 * @param _tr_type The type(s) of transactions to queue (non-periodic,
3269 * periodic, or both).
3271 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3272 dwc_otg_transaction_type_e _tr_type)
3275 DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3277 /* Process host channels associated with periodic transfers. */
3278 if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3279 _tr_type == DWC_OTG_TRANSACTION_ALL) //&&
3280 //!list_empty(&_hcd->periodic_sched_assigned)
3283 process_periodic_channels(_hcd);
3286 /* Process host channels associated with non-periodic transfers. */
3287 if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3288 _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3289 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3290 process_non_periodic_channels(_hcd);
3293 * Ensure NP Tx FIFO empty interrupt is disabled when
3294 * there are no non-periodic transfers to process.
3296 gintmsk_data_t gintmsk = {.d32 = 0};
3297 gintmsk.b.nptxfempty = 1;
3298 dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3305 * Sets the final status of an URB and returns it to the device driver. Any
3306 * required cleanup of the URB is performed.
3308 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3310 __releases(_hcd->lock)
3311 __acquires(_hcd->lock)
3315 if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3316 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3317 __func__, _urb, usb_pipedevice(_urb->pipe),
3318 usb_pipeendpoint(_urb->pipe),
3319 usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3320 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3322 for (i = 0; i < _urb->number_of_packets; i++) {
3323 DWC_PRINT(" ISO Desc %d status: %d\n",
3324 i, _urb->iso_frame_desc[i].status);
3330 _urb->status = _status;
3331 _urb->hcpriv = NULL;
3332 spin_unlock(&_hcd->global_lock);
3333 usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3334 spin_lock(&_hcd->global_lock);
3337 void dwc_otg_clear_halt(struct urb *_urb)
3339 struct dwc_otg_qh *_qh;
3340 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3341 if((ep)&&(ep->hcpriv))
3343 _qh = (dwc_otg_qh_t *) ep->hcpriv;
3344 _qh->data_toggle = 0;
3348 * Returns the Queue Head for an URB.
3350 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3352 struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3353 return (dwc_otg_qh_t *) ep->hcpriv;
3357 void dwc_print_setup_data (uint8_t *setup)
3360 if (CHK_DEBUG_LEVEL(DBG_HCD)){
3361 DWC_PRINT("Setup Data = MSB ");
3362 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3364 DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3365 DWC_PRINT(" bmRequestType Type = ");
3366 switch ((setup[0]&0x60) >> 5) {
3367 case 0: DWC_PRINT("Standard\n"); break;
3368 case 1: DWC_PRINT("Class\n"); break;
3369 case 2: DWC_PRINT("Vendor\n"); break;
3370 case 3: DWC_PRINT("Reserved\n"); break;
3372 DWC_PRINT(" bmRequestType Recipient = ");
3373 switch (setup[0]&0x1f) {
3374 case 0: DWC_PRINT("Device\n"); break;
3375 case 1: DWC_PRINT("Interface\n"); break;
3376 case 2: DWC_PRINT("Endpoint\n"); break;
3377 case 3: DWC_PRINT("Other\n"); break;
3378 default: DWC_PRINT("Reserved\n"); break;
3380 DWC_PRINT(" bRequest = 0x%0x\n", setup[1]);
3381 DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3382 DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3383 DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3388 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3390 DWC_PRINT("Frame remaining at SOF:\n");
3391 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3392 _hcd->frrem_samples, _hcd->frrem_accum,
3393 (_hcd->frrem_samples > 0) ?
3394 _hcd->frrem_accum/_hcd->frrem_samples : 0);
3397 DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3398 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3399 _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3400 (_hcd->core_if->hfnum_7_samples > 0) ?
3401 _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3402 DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3403 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3404 _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3405 (_hcd->core_if->hfnum_0_samples > 0) ?
3406 _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3407 DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3408 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3409 _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3410 (_hcd->core_if->hfnum_other_samples > 0) ?
3411 _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3414 DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3415 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3416 _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3417 (_hcd->hfnum_7_samples_a > 0) ?
3418 _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3419 DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3420 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3421 _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3422 (_hcd->hfnum_0_samples_a > 0) ?
3423 _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3424 DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3425 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3426 _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3427 (_hcd->hfnum_other_samples_a > 0) ?
3428 _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3431 DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3432 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3433 _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3434 (_hcd->hfnum_7_samples_b > 0) ?
3435 _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3436 DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3437 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3438 _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3439 (_hcd->hfnum_0_samples_b > 0) ?
3440 _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3441 DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3442 DWC_PRINT(" samples %u, accum %llu, avg %llu\n",
3443 _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3444 (_hcd->hfnum_other_samples_b > 0) ?
3445 _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3449 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3454 gnptxsts_data_t np_tx_status;
3455 hptxsts_data_t p_tx_status;
3457 num_channels = _hcd->core_if->core_params->host_channels;
3459 DWC_PRINT("************************************************************\n");
3460 DWC_PRINT("HCD State:\n");
3461 DWC_PRINT(" Num channels: %d\n", num_channels);
3462 for (i = 0; i < num_channels; i++) {
3463 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3464 DWC_PRINT(" Channel %d:\n", i);
3465 DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3466 hc->dev_addr, hc->ep_num, hc->ep_is_in);
3467 DWC_PRINT(" speed: %d\n", hc->speed);
3468 DWC_PRINT(" ep_type: %d\n", hc->ep_type);
3469 DWC_PRINT(" max_packet: %d\n", hc->max_packet);
3470 DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start);
3471 DWC_PRINT(" multi_count: %d\n", hc->multi_count);
3472 DWC_PRINT(" xfer_started: %d\n", hc->xfer_started);
3473 DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff);
3474 DWC_PRINT(" xfer_len: %d\n", hc->xfer_len);
3475 DWC_PRINT(" xfer_count: %d\n", hc->xfer_count);
3476 DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue);
3477 DWC_PRINT(" halt_pending: %d\n", hc->halt_pending);
3478 DWC_PRINT(" halt_status: %d\n", hc->halt_status);
3479 DWC_PRINT(" do_split: %d\n", hc->do_split);
3480 DWC_PRINT(" complete_split: %d\n", hc->complete_split);
3481 DWC_PRINT(" hub_addr: %d\n", hc->hub_addr);
3482 DWC_PRINT(" port_addr: %d\n", hc->port_addr);
3483 DWC_PRINT(" xact_pos: %d\n", hc->xact_pos);
3484 DWC_PRINT(" requests: %d\n", hc->requests);
3485 DWC_PRINT(" qh: %p\n", hc->qh);
3486 if (hc->xfer_started) {
3488 hcchar_data_t hcchar;
3489 hctsiz_data_t hctsiz;
3491 hcintmsk_data_t hcintmsk;
3492 hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3493 hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3494 hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3495 hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3496 hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3497 DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32);
3498 DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32);
3499 DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32);
3500 DWC_PRINT(" hcint: 0x%08x\n", hcint.d32);
3501 DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32);
3503 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3506 qtd = hc->qh->qtd_in_process;
3508 DWC_PRINT(" URB Info:\n");
3509 DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb);
3511 DWC_PRINT(" Dev: %d, EP: %d %s\n",
3512 usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3513 usb_pipein(urb->pipe) ? "IN" : "OUT");
3514 DWC_PRINT(" Max packet size: %d\n",
3515 usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3516 DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer);
3517 DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma);
3518 DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3519 DWC_PRINT(" actual_length: %d\n", urb->actual_length);
3523 DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3524 DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels);
3525 DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs);
3526 np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3527 DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3528 DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3529 p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3530 DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3531 DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3532 dwc_otg_hcd_dump_frrem(_hcd);
3533 dwc_otg_dump_global_registers(_hcd->core_if);
3534 dwc_otg_dump_host_registers(_hcd->core_if);
3535 DWC_PRINT("************************************************************\n");
3539 #endif /* DWC_DEVICE_ONLY */