drivers/usb/dwc_otg/dwc_otg_hcd.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $
   3  * $Revision: #16 $
   4  * $Date: 2006/12/05 $
   5  * $Change: 762293 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33 #ifndef DWC_DEVICE_ONLY
  34
  35 /**
  36  * @file
  37  *
  38  * This file contains the implementation of the HCD. In Linux, the HCD
  39  * implements the hc_driver API.
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/device.h>
  46 #include <linux/errno.h>
  47 #include <linux/list.h>
  48 #include <linux/interrupt.h>
  49 #include <linux/string.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/irq.h>
  52 #include <linux/platform_device.h>
  53 #include "usbdev_rk.h"
  54
  55 #include "dwc_otg_driver.h"
  56 #include "dwc_otg_hcd.h"
  57 #include "dwc_otg_regs.h"
  58
  59 static int dwc_otg_hcd_suspend(struct usb_hcd *hcd)
  60 {
  61     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
  62     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
  63     hprt0_data_t hprt0;
  64     pcgcctl_data_t pcgcctl;
  65         struct dwc_otg_platform_data *pldata;
  66     pldata = core_if->otg_dev->pldata;
  67
  68     if(core_if->op_state == B_PERIPHERAL)
  69     {
  70         DWC_PRINT("%s, usb device mode\n", __func__);
  71         return 0;
  72     }
  73     if(!(dwc_otg_hcd->host_enabled&1))
  74         return 0;
  75     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  76 #ifdef CONFIG_USB_SUSPEND
  77     if((!hprt0.b.prtena))
  78         return 0;
  79 #endif
  80     DWC_PRINT("%s suspend, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
  81     if(hprt0.b.prtconnsts)  // usb device connected
  82     {
  83         //partial power-down
  84         if(!hprt0.b.prtsusp)
  85         {
  86             //hprt0.d32 = 0;
  87             hprt0.b.prtsusp = 1;
  88             hprt0.b.prtena = 0;
  89             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  90         }
  91         udelay(10);
  92         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
  93         if(!hprt0.b.prtsusp)
  94         {
  95             //hprt0.d32 = 0;
  96             hprt0.b.prtsusp = 1;
  97             hprt0.b.prtena = 0;
  98             dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
  99         }
 100         mdelay(5);
 101         pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);
 102         pcgcctl.b.pwrclmp = 1;//power clamp
 103         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 104         udelay(1);
 105         //pcgcctl.b.rstpdwnmodule = 1;//reset PDM
 106         pcgcctl.b.stoppclk = 1;//stop phy clk
 107         dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 108     }
 109     else    //no device connect
 110     {
 111         if(pldata->phy_suspend)
 112             pldata->phy_suspend( pldata, USB_PHY_SUSPEND);
 113     }
 114     udelay(3);
 115 #ifndef CONFIG_DWC_REMOTE_WAKEUP
 116     if (pldata->clock_enable)
 117         pldata->clock_enable( pldata, 0);
 118 #endif
 119     //power off
 120     return 0;
 121 }
 122
 123 static int dwc_otg_hcd_resume(struct usb_hcd *hcd)
 124 {
 125     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (hcd);
 126     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 127     hprt0_data_t hprt0;
 128     pcgcctl_data_t pcgcctl;
 129     gintmsk_data_t gintmsk;
 130         struct dwc_otg_platform_data *pldata;
 131     pldata = core_if->otg_dev->pldata;
 132
 133     if(core_if->op_state == B_PERIPHERAL)
 134     {
 135         DWC_PRINT("%s, usb device mode\n", __func__);
 136         return 0;
 137     }
 138 //#ifdef CONFIG_USB_SUSPEND
 139     if(!(dwc_otg_hcd->host_enabled&1))
 140         return 0;
 141 //#endif
 142 #ifndef CONFIG_DWC_REMOTE_WAKEUP
 143     if (pldata->clock_enable)
 144         pldata->clock_enable( pldata, 1);
 145 #endif
 146     //partial power-down
 147     //power on
 148     pcgcctl.d32 = dwc_read_reg32(core_if->pcgcctl);;
 149     pcgcctl.b.stoppclk = 0;//stop phy clk
 150     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 151     udelay(1);
 152     pcgcctl.b.pwrclmp = 0;//power clamp
 153     dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
 154     udelay(2);
 155
 156     gintmsk.d32 = dwc_read_reg32(&core_if->core_global_regs->gintmsk);
 157     gintmsk.b.portintr = 0;
 158     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 159
 160     hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 161 #ifdef CONFIG_USB_SUSPEND
 162     if(!hprt0.b.prtena)
 163         return 0;
 164 #endif
 165     DWC_PRINT("%s resume, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 166     if(hprt0.b.prtconnsts)
 167     {
 168         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 169         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 170         hprt0.b.prtpwr = 1;
 171         hprt0.b.prtres = 1;
 172         hprt0.b.prtena = 0;
 173         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 174         mdelay(20);
 175         hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 176         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 177         //hprt0.d32 = 0;
 178         hprt0.b.prtpwr = 1;
 179         hprt0.b.prtres = 0;
 180         hprt0.b.prtena = 0;
 181         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 182         hprt0.d32 = 0;
 183         hprt0.b.prtpwr = 1;
 184         hprt0.b.prtena = 0;
 185         hprt0.b.prtconndet = 1;
 186         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 187
 188         //hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
 189         //DWC_PRINT("%s, HPRT0:0x%x\n",hcd->self.bus_name,hprt0.d32);
 190
 191         mdelay(10);
 192     }
 193     else{
 194         if(pldata->phy_suspend)
 195             pldata->phy_suspend( pldata, USB_PHY_ENABLED);
 196     }
 197     gintmsk.b.portintr = 1;
 198     dwc_write_reg32(&core_if->core_global_regs->gintmsk, gintmsk.d32);
 199
 200         return 0;
 201 }
 202
 203 static const char dwc_otg_hcd_name [] = "dwc_otg_hcd";
 204
 205 static const struct hc_driver dwc_otg_hc_driver = {
 206
 207         .description =          dwc_otg_hcd_name,
 208         .product_desc =         "DWC OTG Controller",
 209         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 210
 211         .irq =                  dwc_otg_hcd_irq,
 212
 213         .flags =                HCD_MEMORY | HCD_USB2,
 214
 215         //.reset =
 216         .start =                dwc_otg_hcd_start,
 217         //.suspend =
 218         //.resume =
 219
 220         /* yk@rk 20100625
 221          * core/hcd.c call hcd->driver->bus_suspend
 222          * otherwise system can not be suspended
 223          */
 224 #ifdef CONFIG_PM
 225         .bus_suspend =          dwc_otg_hcd_suspend,
 226         .bus_resume =           dwc_otg_hcd_resume,
 227 #endif
 228         .stop =                 dwc_otg_hcd_stop,
 229
 230         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 231         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 232         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 233
 234         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 235
 236         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 237         .hub_control =          dwc_otg_hcd_hub_control,
 238         //.hub_suspend =
 239         //.hub_resume =
 240 };
 241
 242 #ifdef CONFIG_USB11_HOST
 243 static const struct hc_driver host11_hc_driver = {
 244
 245         .description =          "host11_hcd",
 246         .product_desc =         "DWC OTG Controller",
 247         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 248
 249         .irq =                  dwc_otg_hcd_irq,
 250
 251         .flags =                HCD_MEMORY | HCD_USB2,
 252
 253         //.reset =
 254         .start =                dwc_otg_hcd_start,
 255         //.suspend =
 256         //.resume =
 257
 258         /* yk@rk 20100625
 259          * core/hcd.c call hcd->driver->bus_suspend
 260          * otherwise system can not be suspended
 261          */
 262 #ifdef CONFIG_PM
 263         .bus_suspend =          dwc_otg_hcd_suspend,
 264         .bus_resume =           dwc_otg_hcd_resume,
 265 #endif
 266         .stop =                 dwc_otg_hcd_stop,
 267
 268         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 269         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 270         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 271
 272         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 273
 274         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 275         .hub_control =          dwc_otg_hcd_hub_control,
 276         //.hub_suspend =
 277         //.hub_resume =
 278 };
 279 #endif
 280 #ifdef CONFIG_USB20_HOST
 281 static const struct hc_driver host20_hc_driver = {
 282
 283         .description =          "host20_hcd",
 284         .product_desc =         "DWC OTG Controller",
 285         .hcd_priv_size =        sizeof(dwc_otg_hcd_t),
 286
 287         .irq =                  dwc_otg_hcd_irq,
 288
 289         .flags =                HCD_MEMORY | HCD_USB2,
 290
 291         //.reset =
 292         .start =                dwc_otg_hcd_start,
 293         //.suspend =
 294         //.resume =
 295
 296         /* yk@rk 20100625
 297          * core/hcd.c call hcd->driver->bus_suspend
 298          * otherwise system can not be suspended
 299          */
 300 #ifdef CONFIG_PM
 301         .bus_suspend =          dwc_otg_hcd_suspend,
 302         .bus_resume =           dwc_otg_hcd_resume,
 303 #endif
 304         .stop =                 dwc_otg_hcd_stop,
 305
 306         .urb_enqueue =          dwc_otg_hcd_urb_enqueue,
 307         .urb_dequeue =          dwc_otg_hcd_urb_dequeue,
 308         .endpoint_disable =     dwc_otg_hcd_endpoint_disable,
 309
 310         .get_frame_number =     dwc_otg_hcd_get_frame_number,
 311
 312         .hub_status_data =      dwc_otg_hcd_hub_status_data,
 313         .hub_control =          dwc_otg_hcd_hub_control,
 314         //.hub_suspend =
 315         //.hub_resume =
 316 };
 317 #endif
 318
 319 /**
 320  * Work queue function for starting the HCD when A-Cable is connected.
 321  * The dwc_otg_hcd_start() must be called in a process context.
 322  */
 323 static void hcd_start_func(struct work_struct *work)
 324 {
 325     dwc_otg_hcd_t *dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, start_work);
 326     struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
 327
 328     DWC_DEBUGPL(DBG_HCDV, "%s() %p %p\n", __func__, dwc_otg_hcd, hcd);
 329     if (hcd) {
 330             dwc_otg_hcd_start(hcd);
 331     }
 332 }
 333
 334 /**
 335  * HCD Callback function for starting the HCD when A-Cable is
 336  * connected.
 337  *
 338  * @param _p void pointer to the <code>struct usb_hcd</code>
 339  */
 340 static int32_t dwc_otg_hcd_start_cb(void *_p)
 341 {
 342         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p);
 343         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 344         hprt0_data_t hprt0;
 345
 346         if (core_if->op_state == B_HOST) {
 347                 /*
 348                  * Reset the port.  During a HNP mode switch the reset
 349                  * needs to occur within 1ms and have a duration of at
 350                  * least 50ms.
 351                  */
 352                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 353                 hprt0.b.prtrst = 1;
 354                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 355                 ((struct usb_hcd *)_p)->self.is_b_host = 1;
 356         } else {
 357                 ((struct usb_hcd *)_p)->self.is_b_host = 0;
 358         }
 359
 360         /* Need to start the HCD in a non-interrupt context. */
 361 //      INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func, _p);
 362         INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func);
 363         schedule_work(&dwc_otg_hcd->start_work);
 364
 365         return 1;
 366 }
 367
 368
 369 /**
 370  * HCD Callback function for stopping the HCD.
 371  *
 372  * @param _p void pointer to the <code>struct usb_hcd</code>
 373  */
 374 static int32_t dwc_otg_hcd_stop_cb( void *_p )
 375 {
 376         struct usb_hcd *usb_hcd = (struct usb_hcd *)_p;
 377         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 378         dwc_otg_hcd_stop( usb_hcd );
 379         return 1;
 380 }
 381
 382 static void del_xfer_timers(dwc_otg_hcd_t *_hcd)
 383 {
 384 #ifdef DEBUG
 385         int i;
 386         int num_channels = _hcd->core_if->core_params->host_channels;
 387         for (i = 0; i < num_channels; i++) {
 388                 del_timer(&_hcd->core_if->hc_xfer_timer[i]);
 389         }
 390 #endif
 391 }
 392
 393 static void del_timers(dwc_otg_hcd_t *_hcd)
 394 {
 395         del_xfer_timers(_hcd);
 396         del_timer(&_hcd->conn_timer);
 397 }
 398
 399 /**
 400  * Processes all the URBs in a single list of QHs. Completes them with
 401  * -ETIMEDOUT and frees the QTD.
 402  */
 403 static void kill_urbs_in_qh_list(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
 404 {
 405         struct list_head        *qh_item;
 406         dwc_otg_qh_t            *qh;
 407         struct list_head        *qtd_item;
 408         dwc_otg_qtd_t           *qtd;
 409         struct urb              *urb;
 410
 411         list_for_each(qh_item, _qh_list) {
 412                 qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry);
 413                 for (qtd_item = qh->qtd_list.next;
 414                      qtd_item != &qh->qtd_list;
 415                      qtd_item = qh->qtd_list.next) {
 416                         qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry);
 417                         if (qtd->urb != NULL) {
 418                         urb = qtd->urb;
 419                             // 20110415 yk
 420                             // urb will be re entry to ep->urb_list if use ETIMEOUT
 421                                 dwc_otg_hcd_complete_urb(_hcd, urb,
 422                                                          -ESHUTDOWN);//ETIMEDOUT,ENOENT
 423                         }
 424                         dwc_otg_hcd_qtd_remove_and_free(qtd);
 425                 }
 426         }
 427 }
 428
 429 /**
 430  * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic
 431  * and periodic schedules. The QTD associated with each URB is removed from
 432  * the schedule and freed. This function may be called when a disconnect is
 433  * detected or when the HCD is being stopped.
 434  */
 435 static void kill_all_urbs(dwc_otg_hcd_t *_hcd)
 436 {
 437         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive);
 438         kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active);
 439         kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive);
 440 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready);
 441 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned);
 442 //      kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued);
 443 }
 444 extern void release_channel(dwc_otg_hcd_t *_hcd,
 445                             dwc_hc_t *_hc,
 446                             dwc_otg_qtd_t *_qtd,
 447                             dwc_otg_halt_status_e _halt_status);
 448
 449 /**
 450  * HCD Callback function for disconnect of the HCD.
 451  *
 452  * @param _p void pointer to the <code>struct usb_hcd</code>
 453  */
 454 static int32_t dwc_otg_hcd_disconnect_cb( void *_p )
 455 {
 456         gintsts_data_t  intr;
 457     dwc_otg_hcd_t       *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 458
 459     //DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 460
 461     /*
 462      * Set status flags for the hub driver.
 463      */
 464     dwc_otg_hcd->flags.b.port_connect_status_change = 1;
 465         dwc_otg_hcd->flags.b.port_connect_status = 0;
 466
 467     /*
 468      * Shutdown any transfers in process by clearing the Tx FIFO Empty
 469      * interrupt mask and status bits and disabling subsequent host
 470      * channel interrupts.
 471      */
 472     intr.d32 = 0;
 473     intr.b.nptxfempty = 1;
 474     intr.b.ptxfempty = 1;
 475         intr.b.hcintr = 1;
 476     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0);
 477     dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0);
 478
 479 //      del_timers(dwc_otg_hcd);
 480
 481         /*
 482          * Turn off the vbus power only if the core has transitioned to device
 483          * mode. If still in host mode, need to keep power on to detect a
 484          * reconnection.
 485          */
 486         if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) {
 487                 if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) {
 488                         hprt0_data_t hprt0 = { .d32=0 };
 489                         DWC_PRINT("Disconnect: PortPower off\n");
 490                         hprt0.b.prtpwr = 0;
 491                         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
 492                 }
 493
 494                 dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
 495         }
 496
 497         spin_lock(&dwc_otg_hcd->global_lock);
 498         /* Respond with an error status to all URBs in the schedule. */
 499         kill_all_urbs(dwc_otg_hcd);
 500         spin_unlock(&dwc_otg_hcd->global_lock);
 501
 502         if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) {
 503                 /* Clean up any host channels that were in use. */
 504                 int                     num_channels;
 505                 int                     i;
 506                 dwc_hc_t                *channel;
 507                 dwc_otg_hc_regs_t       *hc_regs;
 508                 hcchar_data_t           hcchar;
 509
 510                 num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 511
 512                 if (!dwc_otg_hcd->core_if->dma_enable) {
 513                         /* Flush out any channel requests in slave mode. */
 514                         for (i = 0; i < num_channels; i++) {
 515                                 channel = dwc_otg_hcd->hc_ptr_array[i];
 516                                 if (list_empty(&channel->hc_list_entry)) {
 517                                         hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 518                                         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 519                                         if (hcchar.b.chen) {
 520                                                 hcchar.b.chen = 0;
 521                                                 hcchar.b.chdis = 1;
 522                                                 hcchar.b.epdir = 0;
 523                                                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 524                                         }
 525                                 }
 526                         }
 527                 }
 528
 529                 for (i = 0; i < num_channels; i++) {
 530                         channel = dwc_otg_hcd->hc_ptr_array[i];
 531                         if (list_empty(&channel->hc_list_entry)) {
 532                                 hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i];
 533                                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
 534                                 if (hcchar.b.chen) {
 535                                         /* Halt the channel. */
 536                                         hcchar.b.chdis = 1;
 537                                         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
 538                                 }
 539 #if 1
 540                 release_channel(dwc_otg_hcd, channel, NULL, DWC_OTG_HC_XFER_URB_DEQUEUE);
 541 #else
 542                                 dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel);
 543                                 list_add_tail(&channel->hc_list_entry,
 544                                               &dwc_otg_hcd->free_hc_list);
 545 #endif
 546                         }
 547                 }
 548         }
 549
 550     /* A disconnect will end the session so the B-Device is no
 551      * longer a B-host. */
 552     ((struct usb_hcd *)_p)->self.is_b_host = 0;
 553     return 1;
 554 }
 555
 556 /**
 557  * Connection timeout function.  An OTG host is required to display a
 558  * message if the device does not connect within 10 seconds.
 559  */
 560 void dwc_otg_hcd_connect_timeout( unsigned long _ptr )
 561 {
 562         DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr);
 563         DWC_PRINT( "Connect Timeout\n");
 564         DWC_ERROR( "Device Not Connected/Responding\n" );
 565 }
 566
 567 /**
 568  * Start the connection timer.  An OTG host is required to display a
 569  * message if the device does not connect within 10 seconds.  The
 570  * timer is deleted if a port connect interrupt occurs before the
 571  * timer expires.
 572  */
 573 static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd)
 574 {
 575     init_timer( &_hcd->conn_timer );
 576     _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout;
 577     _hcd->conn_timer.data = (unsigned long)0;
 578     _hcd->conn_timer.expires = jiffies + (HZ*10);
 579     add_timer( &_hcd->conn_timer );
 580 }
 581
 582 /**
 583  * HCD Callback function for disconnect of the HCD.
 584  *
 585  * @param _p void pointer to the <code>struct usb_hcd</code>
 586  */
 587 static int32_t dwc_otg_hcd_session_start_cb( void *_p )
 588 {
 589 //        dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p);
 590         DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p);
 591 //        dwc_otg_hcd_start_connect_timer( dwc_otg_hcd );
 592         return 1;
 593 }
 594
 595 /**
 596  * HCD Callback structure for handling mode switching.
 597  */
 598 static dwc_otg_cil_callbacks_t hcd_cil_callbacks = {
 599         .start = dwc_otg_hcd_start_cb,
 600         .stop = dwc_otg_hcd_stop_cb,
 601         .disconnect = dwc_otg_hcd_disconnect_cb,
 602         .session_start = dwc_otg_hcd_session_start_cb,
 603         .p = 0,//hcd
 604 };
 605
 606 /**
 607  * Reset tasklet function
 608  */
 609 static void reset_tasklet_func (unsigned long data)
 610 {
 611         dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data;
 612         dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 613         hprt0_data_t hprt0;
 614
 615         DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n");
 616
 617         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
 618         hprt0.b.prtrst = 1;
 619         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 620         mdelay (60);
 621
 622         hprt0.b.prtrst = 0;
 623         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
 624         dwc_otg_hcd->flags.b.port_reset_change = 1;
 625
 626         return;
 627 }
 628
 629 static struct tasklet_struct reset_tasklet = {
 630         .next = NULL,
 631         .state = 0,
 632         .count = ATOMIC_INIT(0),
 633         .func = reset_tasklet_func,
 634         .data = 0,
 635 };
 636 #ifndef CONFIG_ARCH_RK29
 637 static void dwc_otg_hcd_enable(struct work_struct *work)
 638 {
 639     dwc_otg_hcd_t *dwc_otg_hcd;
 640     dwc_otg_core_if_t *_core_if;
 641         struct dwc_otg_platform_data *pldata;
 642
 643     dwc_otg_hcd = container_of(work, dwc_otg_hcd_t, host_enable_work.work);
 644     _core_if = dwc_otg_hcd->core_if;
 645     pldata = _core_if->otg_dev->pldata;
 646
 647         if(dwc_otg_hcd->host_enabled == dwc_otg_hcd->host_setenable){
 648 //        DWC_PRINT("%s, enable flag %d\n", __func__, dwc_otg_hcd->host_setenable);
 649             goto out;
 650         }
 651
 652         if(dwc_otg_hcd->host_setenable == 2)    // enable -> disable
 653         {
 654             if(pldata->get_status(USB_STATUS_DPDM)){// usb device connected
 655                 dwc_otg_hcd->host_setenable = 1;
 656                 goto out;
 657             }
 658             DWC_PRINT("%s, disable host controller\n", __func__);
 659             #if 1
 660         if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
 661                 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
 662         }
 663         #endif
 664         dwc_otg_disable_host_interrupts( _core_if );
 665         //if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
 666         //        _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
 667         //}
 668         if(pldata->phy_suspend)
 669             pldata->phy_suspend( pldata, USB_PHY_SUSPEND);
 670         udelay(3);
 671         pldata->clock_enable( pldata, 0);
 672         }
 673         else if(dwc_otg_hcd->host_setenable == 1)
 674         {
 675             DWC_PRINT("%s, enable host controller\n", __func__);
 676         pldata->clock_enable( pldata, 1);
 677         if(pldata->phy_suspend)
 678             pldata->phy_suspend( pldata, USB_PHY_ENABLED);
 679         mdelay(5);
 680         if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
 681                 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
 682         }
 683         }
 684         dwc_otg_hcd->host_enabled = dwc_otg_hcd->host_setenable;
 685 out:
 686     return;
 687 }
 688 static void dwc_otg_hcd_connect_detect(unsigned long pdata)
 689 {
 690     dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t *)pdata;
 691     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
 692         unsigned long flags;
 693         struct dwc_otg_platform_data *pldata;
 694     pldata = core_if->otg_dev->pldata;
 695
 696         local_irq_save(flags);
 697
 698 //    DWC_PRINT("%s hprt %x, grfstatus 0x%x\n", __func__, dwc_read_reg32(core_if->host_if->hprt0), usbgrf_status& (7<<22));
 699     if(pldata->get_status(USB_STATUS_DPDM)) // usb device connected
 700         dwc_otg_hcd->host_setenable = 1;
 701     else{                                   // no device, suspend host
 702         if((dwc_read_reg32(core_if->host_if->hprt0) & 1) == 0)
 703             dwc_otg_hcd->host_setenable = 2;
 704     }
 705     if((dwc_otg_hcd->host_enabled)&&(dwc_otg_hcd->host_setenable != dwc_otg_hcd->host_enabled)){
 706         schedule_delayed_work(&dwc_otg_hcd->host_enable_work, 1);
 707     }
 708     mod_timer(&dwc_otg_hcd->connect_detect_timer,jiffies + (HZ<<1));
 709         local_irq_restore(flags);
 710         return;
 711 }
 712 #endif
 713 /**
 714  * Initializes the HCD. This function allocates memory for and initializes the
 715  * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the
 716  * USB bus with the core and calls the hc_driver->start() function. It returns
 717  * a negative error on failure.
 718  */
 719 extern uint32_t g_dbg_lvl;
 720 int __devinit dwc_otg_hcd_init(struct device *dev)
 721 {
 722         struct usb_hcd *hcd = NULL;
 723         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 724     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
 725
 726         int             num_channels;
 727         int             i;
 728         dwc_hc_t        *channel;
 729
 730         int retval = 0;
 731 #if 1  //kaiker .these code must execute before usb_create_hcd
 732         /* Set device flags indicating whether the HCD supports DMA. */
 733         static u64 usb_dmamask = 0xffffffffUL;
 734         if (otg_dev->core_if->dma_enable) {
 735                 dev->dma_mask = &usb_dmamask;
 736                 dev->coherent_dma_mask = ~0;
 737         } else {
 738                 dev->dma_mask = (void *)0;
 739                 dev->coherent_dma_mask = 0;
 740         }
 741 #endif
 742 //      g_dbg_lvl = 0xff;
 743
 744         /*
 745          * Allocate memory for the base HCD plus the DWC OTG HCD.
 746          * Initialize the base HCD.
 747          */
 748         hcd = usb_create_hcd(&dwc_otg_hc_driver, dev, dev_name(dev));
 749         if (hcd == NULL) {
 750                 retval = -ENOMEM;
 751                 goto error1;
 752         }
 753         hcd->regs = otg_dev->base;
 754         hcd->self.otg_port = 1;
 755
 756         /* Initialize the DWC OTG HCD. */
 757         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 758
 759         spin_lock_init(&dwc_otg_hcd->global_lock);
 760
 761         dwc_otg_hcd->core_if = otg_dev->core_if;
 762         otg_dev->hcd = dwc_otg_hcd;
 763
 764 #ifdef CONFIG_USB20_OTG_EN
 765     dwc_otg_hcd->host_enabled = 1;
 766 #else
 767     dwc_otg_hcd->host_enabled = 0;
 768 #endif
 769
 770         /* Register the HCD CIL Callbacks */
 771         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 772                                            &hcd_cil_callbacks, hcd);
 773
 774         /* Initialize the non-periodic schedule. */
 775         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 776         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 777
 778         /* Initialize the periodic schedule. */
 779         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 780 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 781 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 782 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 783
 784         /*
 785          * Create a host channel descriptor for each host channel implemented
 786          * in the controller. Initialize the channel descriptor array.
 787          */
 788         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 789         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 790         for (i = 0; i < num_channels; i++) {
 791                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 792                 if (channel == NULL) {
 793                         retval = -ENOMEM;
 794                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 795                         goto error2;
 796                 }
 797                 memset(channel, 0, sizeof(dwc_hc_t));
 798                 channel->hc_num = i;
 799                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 800 #ifdef DEBUG
 801                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 802 #endif
 803
 804                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 805         }
 806
 807         /* Initialize the Connection timeout timer. */
 808 //        init_timer( &dwc_otg_hcd->conn_timer );
 809
 810         /* Initialize reset tasklet. */
 811         reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 812         dwc_otg_hcd->reset_tasklet = &reset_tasklet;
 813         /*
 814          * Finish generic HCD initialization and start the HCD. This function
 815          * allocates the DMA buffer pool, registers the USB bus, requests the
 816          * IRQ line, and calls dwc_otg_hcd_start method.
 817          */
 818         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 819                                         IRQF_SHARED);
 820         if (retval < 0) {
 821                 DWC_ERROR("usb_add_hcd fail,everest\n");
 822                 goto error2;
 823         }
 824         /*
 825          * Allocate space for storing data on status transactions. Normally no
 826          * data is sent, but this space acts as a bit bucket. This must be
 827          * done after usb_add_hcd since that function allocates the DMA buffer
 828          * pool.
 829          */
 830         if (otg_dev->core_if->dma_enable) {
 831                 dwc_otg_hcd->status_buf =
 832                         dma_alloc_coherent(dev,
 833                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 834                                            &dwc_otg_hcd->status_buf_dma,
 835                                            GFP_KERNEL | GFP_DMA);
 836         } else {
 837                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
 838                                                   GFP_KERNEL);
 839         }
 840         if (dwc_otg_hcd->status_buf == NULL) {
 841                 retval = -ENOMEM;
 842                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
 843                 goto error3;
 844         }
 845
 846 //      DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
 847 //                  dev->bus_id, hcd->self.busnum);
 848
 849         return 0;
 850
 851         /* Error conditions */
 852  error3:
 853         usb_remove_hcd(hcd);
 854  error2:
 855         dwc_otg_hcd_free(hcd);
 856         usb_put_hcd(hcd);
 857
 858  error1:
 859         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
 860         return retval;
 861 }
 862
 863 #ifdef CONFIG_USB11_HOST
 864
 865 static dwc_otg_cil_callbacks_t host11_cil_callbacks = {
 866         .start = dwc_otg_hcd_start_cb,
 867         .stop = dwc_otg_hcd_stop_cb,
 868         .disconnect = dwc_otg_hcd_disconnect_cb,
 869         .session_start = dwc_otg_hcd_session_start_cb,
 870         .p = 0,//hcd
 871 };
 872
 873 static struct tasklet_struct host11_reset_tasklet = {
 874         .next = NULL,
 875         .state = 0,
 876         .count = ATOMIC_INIT(0),
 877         .func = reset_tasklet_func,
 878         .data = 0,
 879 };
 880
 881 int __devinit host11_hcd_init(struct device *dev)
 882 {
 883         struct usb_hcd *hcd = NULL;
 884         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
 885     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
 886
 887         int             num_channels;
 888         int             i;
 889         dwc_hc_t        *channel;
 890
 891         int retval = 0;
 892 #if 1  //kaiker .these code must execute before usb_create_hcd
 893         /* Set device flags indicating whether the HCD supports DMA. */
 894         static u64 usb_dmamask = 0xffffffffUL;
 895         if (otg_dev->core_if->dma_enable) {
 896 //              DWC_PRINT("Using DMA mode\n");
 897                 dev->dma_mask = &usb_dmamask;
 898                 dev->coherent_dma_mask = ~0;
 899         } else {
 900 //              DWC_PRINT("Using Slave mode\n");
 901                 dev->dma_mask = (void *)0;
 902                 dev->coherent_dma_mask = 0;
 903         }
 904 #endif
 905 //      g_dbg_lvl = 0xff;
 906
 907         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
 908
 909         /*
 910          * Allocate memory for the base HCD plus the DWC OTG HCD.
 911          * Initialize the base HCD.
 912          */
 913         hcd = usb_create_hcd(&host11_hc_driver, dev, dev_name(dev));
 914         if (hcd == NULL) {
 915                 retval = -ENOMEM;
 916                 goto error1;
 917         }
 918         hcd->regs = otg_dev->base;
 919         hcd->self.otg_port = 1;
 920
 921         /* Initialize the DWC OTG HCD. */
 922         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
 923         dwc_otg_hcd->core_if = otg_dev->core_if;
 924         otg_dev->hcd = dwc_otg_hcd;
 925
 926 #ifdef CONFIG_USB11_HOST_EN
 927         dwc_otg_hcd->host_enabled = 1;
 928 #else
 929         dwc_otg_hcd->host_enabled = 0;
 930 #endif
 931
 932         spin_lock_init(&dwc_otg_hcd->global_lock);
 933
 934
 935         /* Register the HCD CIL Callbacks */
 936         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
 937                                            &host11_cil_callbacks, hcd);
 938
 939         /* Initialize the non-periodic schedule. */
 940         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
 941         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
 942
 943         /* Initialize the periodic schedule. */
 944         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
 945 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
 946 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
 947 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
 948
 949         /*
 950          * Create a host channel descriptor for each host channel implemented
 951          * in the controller. Initialize the channel descriptor array.
 952          */
 953         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
 954         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
 955         for (i = 0; i < num_channels; i++) {
 956                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
 957                 if (channel == NULL) {
 958                         retval = -ENOMEM;
 959                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
 960                         goto error2;
 961                 }
 962                 memset(channel, 0, sizeof(dwc_hc_t));
 963                 channel->hc_num = i;
 964                 dwc_otg_hcd->hc_ptr_array[i] = channel;
 965 #ifdef DEBUG
 966                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
 967 #endif
 968
 969                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
 970         }
 971
 972         /* Initialize the Connection timeout timer. */
 973 //        init_timer( &dwc_otg_hcd->conn_timer );
 974
 975         /* Initialize reset tasklet. */
 976         host11_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
 977         dwc_otg_hcd->reset_tasklet = &host11_reset_tasklet;
 978         /*
 979          * Finish generic HCD initialization and start the HCD. This function
 980          * allocates the DMA buffer pool, registers the USB bus, requests the
 981          * IRQ line, and calls dwc_otg_hcd_start method.
 982          */
 983         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
 984                                         IRQF_SHARED);
 985         if (retval < 0) {
 986                 DWC_ERROR("usb_add_hcd fail,everest\n");
 987                 goto error2;
 988         }
 989         /*
 990          * Allocate space for storing data on status transactions. Normally no
 991          * data is sent, but this space acts as a bit bucket. This must be
 992          * done after usb_add_hcd since that function allocates the DMA buffer
 993          * pool.
 994          */
 995         if (otg_dev->core_if->dma_enable) {
 996                 dwc_otg_hcd->status_buf =
 997                         dma_alloc_coherent(dev,
 998                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
 999                                            &dwc_otg_hcd->status_buf_dma,
1000                                            GFP_KERNEL | GFP_DMA);
1001         } else {
1002                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1003                                                   GFP_KERNEL);
1004         }
1005         if (dwc_otg_hcd->status_buf == NULL) {
1006                 retval = -ENOMEM;
1007                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1008                 goto error3;
1009         }
1010
1011         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n",
1012                     _lmdev->dev.bus_id, hcd->self.busnum);
1013
1014         return 0;
1015
1016         /* Error conditions */
1017  error3:
1018         usb_remove_hcd(hcd);
1019  error2:
1020         dwc_otg_hcd_free(hcd);
1021         usb_put_hcd(hcd);
1022
1023  error1:
1024         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1025         return retval;
1026 }
1027 #endif
1028 #ifdef CONFIG_USB20_HOST
1029
1030
1031 static dwc_otg_cil_callbacks_t host20_cil_callbacks = {
1032         .start = dwc_otg_hcd_start_cb,
1033         .stop = dwc_otg_hcd_stop_cb,
1034         .disconnect = dwc_otg_hcd_disconnect_cb,
1035         .session_start = dwc_otg_hcd_session_start_cb,
1036         .p = 0,//hcd
1037 };
1038
1039 static struct tasklet_struct host20_reset_tasklet = {
1040         .next = NULL,
1041         .state = 0,
1042         .count = ATOMIC_INIT(0),
1043         .func = reset_tasklet_func,
1044         .data = 0,
1045 };
1046
1047 int __devinit host20_hcd_init(struct device *dev)
1048 {
1049         struct usb_hcd *hcd = NULL;
1050         dwc_otg_hcd_t *dwc_otg_hcd = NULL;
1051     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1052
1053         int             num_channels;
1054         int             i;
1055         dwc_hc_t        *channel;
1056
1057         int retval = 0;
1058 #if 1  //kaiker .these code must execute before usb_create_hcd
1059         /* Set device flags indicating whether the HCD supports DMA. */
1060         static u64 usb_dmamask = 0xffffffffUL;
1061         if (otg_dev->core_if->dma_enable) {
1062 //              DWC_PRINT("Using DMA mode\n");
1063                 dev->dma_mask = &usb_dmamask;
1064                 dev->coherent_dma_mask = ~0;
1065         } else {
1066 //              DWC_PRINT("Using Slave mode\n");
1067                 dev->dma_mask = (void *)0;
1068                 dev->coherent_dma_mask = 0;
1069         }
1070 #endif
1071 //      g_dbg_lvl = 0xff;
1072
1073         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n");
1074
1075         /*
1076          * Allocate memory for the base HCD plus the DWC OTG HCD.
1077          * Initialize the base HCD.
1078          */
1079         hcd = usb_create_hcd(&host20_hc_driver, dev, dev_name(dev));
1080         if (hcd == NULL) {
1081                 retval = -ENOMEM;
1082                 goto error1;
1083         }
1084         hcd->regs = otg_dev->base;
1085         hcd->self.otg_port = 1;
1086
1087         /* Initialize the DWC OTG HCD. */
1088         dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd);
1089         dwc_otg_hcd->core_if = otg_dev->core_if;
1090         otg_dev->hcd = dwc_otg_hcd;
1091
1092 #ifdef CONFIG_USB20_HOST_EN
1093         dwc_otg_hcd->host_enabled = 1;
1094 #else
1095         dwc_otg_hcd->host_enabled = 0;
1096 #endif
1097
1098         spin_lock_init(&dwc_otg_hcd->global_lock);
1099
1100         /* Register the HCD CIL Callbacks */
1101         dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if,
1102                                            &host20_cil_callbacks, hcd);
1103
1104         /* Initialize the non-periodic schedule. */
1105         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive);
1106         INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active);
1107
1108         /* Initialize the periodic schedule. */
1109         INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive);
1110 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready);
1111 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned);
1112 //      INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued);
1113
1114         /*
1115          * Create a host channel descriptor for each host channel implemented
1116          * in the controller. Initialize the channel descriptor array.
1117          */
1118         INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list);
1119         num_channels = dwc_otg_hcd->core_if->core_params->host_channels;
1120         for (i = 0; i < num_channels; i++) {
1121                 channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL);
1122                 if (channel == NULL) {
1123                         retval = -ENOMEM;
1124                         DWC_ERROR("%s: host channel allocation failed\n", __func__);
1125                         goto error2;
1126                 }
1127                 memset(channel, 0, sizeof(dwc_hc_t));
1128                 channel->hc_num = i;
1129                 dwc_otg_hcd->hc_ptr_array[i] = channel;
1130 #ifdef DEBUG
1131                 init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]);
1132 #endif
1133
1134                 DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel);
1135         }
1136
1137         /* Initialize the Connection timeout timer. */
1138         //init_timer( &dwc_otg_hcd->conn_timer );
1139
1140         /* Initialize reset tasklet. */
1141         host20_reset_tasklet.data = (unsigned long) dwc_otg_hcd;
1142         dwc_otg_hcd->reset_tasklet = &host20_reset_tasklet;
1143         /*
1144          * Finish generic HCD initialization and start the HCD. This function
1145          * allocates the DMA buffer pool, registers the USB bus, requests the
1146          * IRQ line, and calls dwc_otg_hcd_start method.
1147          */
1148         retval = usb_add_hcd(hcd, platform_get_irq(to_platform_device(dev), 0),
1149                                         IRQF_SHARED);
1150         if (retval < 0) {
1151                 DWC_ERROR("usb_add_hcd fail,everest\n");
1152                 goto error2;
1153         }
1154         /*
1155          * Allocate space for storing data on status transactions. Normally no
1156          * data is sent, but this space acts as a bit bucket. This must be
1157          * done after usb_add_hcd since that function allocates the DMA buffer
1158          * pool.
1159          */
1160         if (otg_dev->core_if->dma_enable) {
1161                 dwc_otg_hcd->status_buf =
1162                         dma_alloc_coherent(dev,
1163                                            DWC_OTG_HCD_STATUS_BUF_SIZE,
1164                                            &dwc_otg_hcd->status_buf_dma,
1165                                            GFP_KERNEL | GFP_DMA);
1166         } else {
1167                 dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE,
1168                                                   GFP_KERNEL);
1169         }
1170         if (dwc_otg_hcd->status_buf == NULL) {
1171                 retval = -ENOMEM;
1172                 DWC_ERROR("%s: status_buf allocation failed\n", __func__);
1173                 goto error3;
1174         }
1175
1176 #ifndef CONFIG_ARCH_RK29
1177     dwc_otg_hcd->host_setenable = 1;
1178     dwc_otg_hcd->connect_detect_timer.function = dwc_otg_hcd_connect_detect;
1179     dwc_otg_hcd->connect_detect_timer.data = (unsigned long)(dwc_otg_hcd);
1180     init_timer( &dwc_otg_hcd->connect_detect_timer);
1181     mod_timer(&dwc_otg_hcd->connect_detect_timer, jiffies+(HZ<<3));
1182
1183     INIT_DELAYED_WORK(&dwc_otg_hcd->host_enable_work, dwc_otg_hcd_enable);
1184 #endif
1185         return 0;
1186
1187         /* Error conditions */
1188  error3:
1189         usb_remove_hcd(hcd);
1190  error2:
1191         dwc_otg_hcd_free(hcd);
1192         usb_put_hcd(hcd);
1193
1194  error1:
1195         DWC_PRINT("dwc_otg_hcd_init error,everest\n");
1196         return retval;
1197 }
1198 #endif
1199
1200
1201 /**
1202  * Removes the HCD.
1203  * Frees memory and resources associated with the HCD and deregisters the bus.
1204  */
1205 void dwc_otg_hcd_remove(struct device *dev)
1206 {
1207         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1208     dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd;
1209         struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd);
1210
1211         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n");
1212
1213         /* Turn off all interrupts */
1214         dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0);
1215         dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0);
1216
1217         usb_remove_hcd(hcd);
1218         dwc_otg_hcd_free(hcd);
1219         usb_put_hcd(hcd);
1220
1221         return;
1222 }
1223
1224
1225 /* =========================================================================
1226  *  Linux HC Driver Functions
1227  * ========================================================================= */
1228
1229 /**
1230  * Initializes dynamic portions of the DWC_otg HCD state.
1231  */
1232 static void hcd_reinit(dwc_otg_hcd_t *_hcd)
1233 {
1234         struct list_head        *item;
1235 #if 0
1236         int                     num_channels;
1237         int                     i;
1238         dwc_hc_t                *channel;
1239 #endif
1240         DWC_DEBUGPL(DBG_HCD, "%s: Enter\n", __func__);
1241
1242         _hcd->flags.d32 = 0;
1243
1244         _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active;
1245         _hcd->non_periodic_channels = 0;
1246         _hcd->periodic_channels = 0;
1247
1248         /*
1249          * Put all channels in the free channel list and clean up channel
1250          * states.
1251          */
1252         item = _hcd->free_hc_list.next;
1253         while (item != &_hcd->free_hc_list) {
1254                 list_del(item);
1255                 item = _hcd->free_hc_list.next;
1256         }
1257 #if 0
1258         num_channels = _hcd->core_if->core_params->host_channels;
1259         for (i = 0; i < num_channels; i++) {
1260                 channel = _hcd->hc_ptr_array[i];
1261                 list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list);
1262                 dwc_otg_hc_cleanup(_hcd->core_if, channel);
1263         }
1264 #endif
1265         /* Initialize the DWC core for host mode operation. */
1266         dwc_otg_core_host_init(_hcd->core_if);
1267 }
1268
1269 /** Initializes the DWC_otg controller and its root hub and prepares it for host
1270  * mode operation. Activates the root port. Returns 0 on success and a negative
1271  * error code on failure. */
1272 int dwc_otg_hcd_start(struct usb_hcd *_hcd)
1273 {
1274     dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1275     dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if;
1276         unsigned long flags;
1277
1278         struct usb_bus *bus;
1279
1280         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n");
1281         local_irq_save(flags);
1282
1283         bus = hcd_to_bus(_hcd);
1284         _hcd->state = HC_STATE_RUNNING;
1285
1286         /* Initialize and connect root hub if one is not already attached */
1287         if (bus->root_hub) {
1288                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n");
1289                 /* Inform the HUB driver to resume. */
1290                 usb_hcd_resume_root_hub(_hcd);
1291         }
1292         else {
1293             /*
1294              * no use
1295              * yk@rk 2010121
1296             struct usb_device *udev;6
1297                 udev = usb_alloc_dev(NULL, bus, 0);
1298                 udev->speed = USB_SPEED_HIGH;
1299                 if (!udev) {
1300                         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n");
1301                         return -ENODEV;
1302                 }
1303         */
1304             /* Not needed - VJ
1305                if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) {
1306                    DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval);
1307                return -ENODEV;
1308                }
1309              */
1310         }
1311         /* Initialize the bus state.  If the core is in Device Mode
1312          * HALT the USB bus and return. */
1313         if (!dwc_otg_hcd->host_enabled || dwc_otg_is_device_mode (core_if)) {
1314                 DWC_PRINT("dwc_otg_hcd_start controller in device mode,everest\n");
1315                 //_hcd->state = HC_STATE_HALT;
1316                 goto out;
1317         }
1318         hcd_reinit(dwc_otg_hcd);
1319 out:
1320     local_irq_restore(flags);
1321
1322         return 0;
1323 }
1324
1325 static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list)
1326 {
1327         struct list_head        *item;
1328         dwc_otg_qh_t            *qh;
1329
1330         if (_qh_list->next == NULL) {
1331                 /* The list hasn't been initialized yet. */
1332                 return;
1333         }
1334
1335         /* Ensure there are no QTDs or URBs left. */
1336         kill_urbs_in_qh_list(_hcd, _qh_list);
1337
1338         for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) {
1339                 qh = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1340                 dwc_otg_hcd_qh_remove_and_free(_hcd, qh);
1341         }
1342 }
1343
1344 /**
1345  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
1346  * stopped.
1347  */
1348 void dwc_otg_hcd_stop(struct usb_hcd *_hcd)
1349 {
1350         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1351         hprt0_data_t hprt0 = { .d32=0 };
1352         struct dwc_otg_platform_data *pldata;
1353     pldata = dwc_otg_hcd->core_if->otg_dev->pldata;
1354
1355         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n");
1356
1357         /* Turn off all host-specific interrupts. */
1358         dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if );
1359
1360         /*
1361          * The root hub should be disconnected before this function is called.
1362          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1363          * and the QH lists (via ..._hcd_endpoint_disable).
1364          */
1365
1366         /* Turn off the vbus power */
1367         DWC_PRINT("PortPower off\n");
1368         hprt0.b.prtpwr = 0;
1369         dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32);
1370
1371         if(pldata->power_enable)
1372             pldata->power_enable(0);
1373         return;
1374 }
1375
1376
1377 /** Returns the current frame number. */
1378 int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd)
1379 {
1380         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1381         hfnum_data_t hfnum;
1382
1383         hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if->
1384                                    host_if->host_global_regs->hfnum);
1385
1386 #ifdef DEBUG_SOF
1387         DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum);
1388 #endif
1389         return hfnum.b.frnum;
1390 }
1391
1392 /**
1393  * Frees secondary storage associated with the dwc_otg_hcd structure contained
1394  * in the struct usb_hcd field.
1395  */
1396 void dwc_otg_hcd_free(struct usb_hcd *_hcd)
1397 {
1398         dwc_otg_hcd_t   *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1399         int             i;
1400
1401         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n");
1402
1403 //      del_timers(dwc_otg_hcd);
1404
1405         /* Free memory for QH/QTD lists */
1406         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive);
1407         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active);
1408         qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive);
1409 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready);
1410 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned);
1411 //      qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued);
1412
1413         /* Free memory for the host channels. */
1414         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
1415                 dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i];
1416                 if (hc != NULL) {
1417                         DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc);
1418                         kfree(hc);
1419                 }
1420         }
1421
1422         if (dwc_otg_hcd->core_if->dma_enable) {
1423                 if (dwc_otg_hcd->status_buf_dma) {
1424                         dma_free_coherent(_hcd->self.controller,
1425                                           DWC_OTG_HCD_STATUS_BUF_SIZE,
1426                                           dwc_otg_hcd->status_buf,
1427                                           dwc_otg_hcd->status_buf_dma);
1428                 }
1429         } else if (dwc_otg_hcd->status_buf != NULL) {
1430                 kfree(dwc_otg_hcd->status_buf);
1431         }
1432
1433         return;
1434 }
1435
1436 #ifdef DEBUG
1437 static void dump_urb_info(struct urb *_urb, char* _fn_name)
1438 {
1439         DWC_PRINT("  Device address: %d\n", usb_pipedevice(_urb->pipe));
1440         DWC_PRINT("  Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe),
1441                   (usb_pipein(_urb->pipe) ? "IN" : "OUT"));
1442         DWC_PRINT("  Endpoint type: %s\n",
1443                   ({char *pipetype;
1444                   switch (usb_pipetype(_urb->pipe)) {
1445                   case PIPE_CONTROL: pipetype = "CONTROL"; break;
1446                   case PIPE_BULK: pipetype = "BULK"; break;
1447                   case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break;
1448                   case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break;
1449                   default: pipetype = "UNKNOWN"; break;
1450                   }; pipetype;}));
1451         DWC_PRINT("  Speed: %s\n",
1452                   ({char *speed;
1453                   switch (_urb->dev->speed) {
1454                   case USB_SPEED_HIGH: speed = "HIGH"; break;
1455                   case USB_SPEED_FULL: speed = "FULL"; break;
1456                   case USB_SPEED_LOW: speed = "LOW"; break;
1457                   default: speed = "UNKNOWN"; break;
1458                   }; speed;}));
1459         DWC_PRINT("  Max packet size: %d\n",
1460                   usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe)));
1461         DWC_PRINT("  Data buffer length: %d\n", _urb->transfer_buffer_length);
1462         DWC_PRINT("  Transfer buffer: %p, Transfer DMA: %p\n",
1463                   _urb->transfer_buffer, (void *)_urb->transfer_dma);
1464         DWC_PRINT("  Setup buffer: %p, Setup DMA: %p\n",
1465                   _urb->setup_packet, (void *)_urb->setup_dma);
1466         DWC_PRINT("  Interval: %d\n", _urb->interval);
1467         if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
1468                 int i;
1469                 for (i = 0; i < _urb->number_of_packets;  i++) {
1470                         DWC_PRINT("  ISO Desc %d:\n", i);
1471                         DWC_PRINT("    offset: %d, length %d\n",
1472                                   _urb->iso_frame_desc[i].offset,
1473                                   _urb->iso_frame_desc[i].length);
1474                 }
1475         }
1476 }
1477
1478 static void dump_channel_info(dwc_otg_hcd_t *_hcd,
1479                               dwc_otg_qh_t *qh)
1480 {
1481         if (qh->channel != NULL) {
1482                 dwc_hc_t *hc = qh->channel;
1483                 struct list_head *item;
1484                 dwc_otg_qh_t *qh_item;
1485                 int num_channels = _hcd->core_if->core_params->host_channels;
1486                 int i;
1487
1488                 dwc_otg_hc_regs_t *hc_regs;
1489                 hcchar_data_t   hcchar;
1490                 hcsplt_data_t   hcsplt;
1491                 hctsiz_data_t   hctsiz;
1492                 uint32_t        hcdma;
1493
1494                 hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num];
1495                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1496                 hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt);
1497                 hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz);
1498                 hcdma = dwc_read_reg32(&hc_regs->hcdma);
1499
1500                 DWC_PRINT("  Assigned to channel %p:\n", hc);
1501                 DWC_PRINT("    hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32);
1502                 DWC_PRINT("    hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma);
1503                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1504                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
1505                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
1506                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
1507                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
1508                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
1509                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
1510                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
1511                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
1512                 DWC_PRINT("    qh: %p\n", hc->qh);
1513                 DWC_PRINT("  NP inactive sched:\n");
1514                 list_for_each(item, &_hcd->non_periodic_sched_inactive) {
1515                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1516                         DWC_PRINT("    %p\n", qh_item);
1517                 }
1518                 DWC_PRINT("  NP active sched:\n");
1519                 list_for_each(item, &_hcd->non_periodic_sched_active) {
1520                         qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry);
1521                         DWC_PRINT("    %p\n", qh_item);
1522                 }
1523                 DWC_PRINT("  Channels: \n");
1524                 for (i = 0; i < num_channels; i++) {
1525                         dwc_hc_t *hc = _hcd->hc_ptr_array[i];
1526                         DWC_PRINT("    %2d: %p\n", i, hc);
1527                 }
1528         }
1529 }
1530 #endif
1531
1532 /** Starts processing a USB transfer request specified by a USB Request Block
1533  * (URB). mem_flags indicates the type of memory allocation to use while
1534  * processing this URB. */
1535 int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd,
1536                             struct urb *_urb,
1537                             gfp_t _mem_flags)
1538 {
1539         int retval;
1540         dwc_otg_hcd_t * dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1541         dwc_otg_qtd_t * qtd;
1542
1543     if(atomic_read(&_urb->use_count)>1){
1544         retval = -EPERM;
1545         dump_stack();
1546         DWC_PRINT("%s urb %p already in queue, qtd %p, count%d\n", __func__, _urb, _urb->hcpriv, atomic_read(&_urb->use_count));
1547         goto out;
1548     }
1549     if((uint32_t)_urb->transfer_buffer & 3){
1550         retval = -EPERM;
1551         DWC_PRINT("%s urb->transfer_buffer address not align to 4-byte 0x%x\n", __func__, (uint32_t)_urb->transfer_buffer);
1552         goto out;
1553     }
1554 #ifdef DEBUG
1555             if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1556                 dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue");
1557         }
1558 #endif  /*  */
1559     if (!dwc_otg_hcd->flags.b.port_connect_status) {
1560                 DWC_ERROR("DWC OTG No longer connected\n");
1561             /* No longer connected. */
1562                 retval =  -ENODEV;
1563                 goto out;
1564         }
1565         qtd = dwc_otg_hcd_qtd_create(_urb);
1566         if (qtd == NULL) {
1567                 DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n");
1568                 retval = -ENOMEM;
1569                 goto out;
1570         }
1571         retval = dwc_otg_hcd_qtd_add(qtd, dwc_otg_hcd);
1572         if (retval < 0) {
1573                 DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. "
1574                            "Error status %d\n", retval);
1575                 dwc_otg_hcd_qtd_free(qtd);
1576         }
1577 #if 1
1578         /*
1579          * Make sure the start of frame interrupt is enabled now that
1580          * we know we should have queued data. The SOF interrupt
1581          * handler automatically disables itself when idle to reduce
1582          * the number of interrupts. See dwc_otg_hcd_handle_sof_intr()
1583          * for the disable
1584          */
1585         dwc_modify_reg32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0,
1586                          DWC_SOF_INTR_MASK);
1587 #endif
1588 out:
1589         return retval;
1590 }
1591
1592 /** Aborts/cancels a USB transfer request. Always returns 0 to indicate
1593  * success.  */
1594 int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status)
1595 {
1596         unsigned long flags;
1597         dwc_otg_hcd_t * dwc_otg_hcd;
1598         dwc_otg_qtd_t * urb_qtd;
1599         dwc_otg_qh_t * qh;
1600         struct usb_host_endpoint *_ep;
1601
1602         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n");
1603
1604         if(((uint32_t)_urb&0xf0000000)==0)
1605                 DWC_PRINT("%s urb is %p\n", __func__, _urb);
1606
1607     _ep = dwc_urb_to_endpoint(_urb);
1608         if(_ep==NULL)
1609         {
1610                 DWC_PRINT("%s=====================================================\n",__func__);
1611                 DWC_PRINT("urb->ep is null\n");
1612                 return -1;
1613         }
1614
1615         urb_qtd = (dwc_otg_qtd_t *) _urb->hcpriv;
1616         if(((uint32_t)urb_qtd&0xf0000000) == 0)
1617         {
1618                 DWC_PRINT("%s,urb_qtd is %p urb %p, count %d\n",__func__, urb_qtd, _urb, atomic_read(&_urb->use_count));
1619         if((atomic_read(&_urb->use_count)) == 0)
1620             return 0;
1621         else
1622                     return -1;
1623         }
1624         qh = (dwc_otg_qh_t *) _ep->hcpriv;
1625         dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1626         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1627
1628 #ifdef DEBUG
1629     if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1630                 dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue");
1631                 if (urb_qtd == qh->qtd_in_process) {
1632                         dump_channel_info(dwc_otg_hcd, qh);
1633                 }
1634         }
1635
1636 #endif  /*  */
1637
1638     if (urb_qtd == qh->qtd_in_process) {
1639             /* The QTD is in process (it has been assigned to a channel). */
1640             if (dwc_otg_hcd->flags.b.port_connect_status) {
1641                     /*
1642                      * If still connected (i.e. in host mode), halt the
1643                      * channel so it can be used for other transfers. If
1644                      * no longer connected, the host registers can't be
1645                      * written to halt the channel since the core is in
1646                      * device mode.
1647                      */
1648                     dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel,
1649                                             DWC_OTG_HC_XFER_URB_DEQUEUE);
1650                 }
1651         }
1652
1653     /*
1654      * Free the QTD and clean up the associated QH. Leave the QH in the
1655      * schedule if it has any remaining QTDs.
1656      */
1657     dwc_otg_hcd_qtd_remove_and_free(urb_qtd);
1658         if (urb_qtd == qh->qtd_in_process) {
1659                 dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0);
1660                 qh->channel = NULL;
1661                 qh->qtd_in_process = NULL;
1662         } else if (list_empty(&qh->qtd_list)) {
1663                 dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh);
1664         }
1665
1666         _urb->hcpriv = NULL;
1667         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1668     /* Higher layer software sets URB status. */
1669         usb_hcd_giveback_urb(_hcd, _urb, _status);
1670         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
1671                 DWC_PRINT("Called usb_hcd_giveback_urb()\n");
1672                 DWC_PRINT("  urb->status = %d\n", _status);
1673         }
1674         return 0;
1675 }
1676
1677
1678 /** Frees resources in the DWC_otg controller related to a given endpoint. Also
1679  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
1680  * must already be dequeued. */
1681 void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd,
1682                                   struct usb_host_endpoint *_ep)
1683
1684 {
1685         unsigned long flags;
1686         dwc_otg_qh_t *qh;
1687         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd);
1688
1689         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1690
1691         DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, "
1692                     "endpoint=%d\n", _ep->desc.bEndpointAddress,
1693                     dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress));
1694
1695         qh = (dwc_otg_qh_t *)(_ep->hcpriv);
1696         if (qh != NULL) {
1697 #ifdef DEBUG
1698                 /** Check that the QTD list is really empty */
1699                 if (!list_empty(&qh->qtd_list)) {
1700                         DWC_WARN("DWC OTG HCD EP DISABLE:"
1701                                  " QTD List for this endpoint is not empty\n");
1702                 }
1703 #endif
1704
1705                 dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh);
1706                 _ep->hcpriv = NULL;
1707         }
1708
1709         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1710
1711         return;
1712 }
1713
1714 /** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
1715  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
1716  * interrupt.
1717  *
1718  * This function is called by the USB core when an interrupt occurs */
1719 irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd)
1720 {
1721         irqreturn_t result;
1722         unsigned long flags;
1723         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1724
1725         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
1726
1727         result = IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd));
1728
1729         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
1730
1731         return result;
1732 }
1733
1734 /** Creates Status Change bitmap for the root hub and root port. The bitmap is
1735  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
1736  * is the status change indicator for the single root port. Returns 1 if either
1737  * change indicator is 1, otherwise returns 0. */
1738 int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd,
1739                                 char *_buf)
1740 {
1741         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
1742
1743         _buf[0] = 0;
1744         _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change ||
1745                     dwc_otg_hcd->flags.b.port_reset_change ||
1746                     dwc_otg_hcd->flags.b.port_enable_change ||
1747                     dwc_otg_hcd->flags.b.port_suspend_change ||
1748                     dwc_otg_hcd->flags.b.port_over_current_change) << 1;
1749
1750 #ifdef DEBUG
1751         if (_buf[0]) {
1752                 DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:"
1753                             " Root port status changed\n");
1754                 DWC_DEBUGPL(DBG_HCDV, "  port_connect_status_change: %d\n",
1755                             dwc_otg_hcd->flags.b.port_connect_status_change);
1756                 DWC_DEBUGPL(DBG_HCDV, "  port_reset_change: %d\n",
1757                             dwc_otg_hcd->flags.b.port_reset_change);
1758                 DWC_DEBUGPL(DBG_HCDV, "  port_enable_change: %d\n",
1759                             dwc_otg_hcd->flags.b.port_enable_change);
1760                 DWC_DEBUGPL(DBG_HCDV, "  port_suspend_change: %d\n",
1761                             dwc_otg_hcd->flags.b.port_suspend_change);
1762                 DWC_DEBUGPL(DBG_HCDV, "  port_over_current_change: %d\n",
1763                             dwc_otg_hcd->flags.b.port_over_current_change);
1764         }
1765 #endif
1766         return (_buf[0] != 0);
1767 }
1768
1769 #ifdef DWC_HS_ELECT_TST
1770 /*
1771  * Quick and dirty hack to implement the HS Electrical Test
1772  * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature.
1773  *
1774  * This code was copied from our userspace app "hset". It sends a
1775  * Get Device Descriptor control sequence in two parts, first the
1776  * Setup packet by itself, followed some time later by the In and
1777  * Ack packets. Rather than trying to figure out how to add this
1778  * functionality to the normal driver code, we just hijack the
1779  * hardware, using these two function to drive the hardware
1780  * directly.
1781  */
1782
1783 dwc_otg_core_global_regs_t *global_regs;
1784 dwc_otg_host_global_regs_t *hc_global_regs;
1785 dwc_otg_hc_regs_t *hc_regs;
1786 uint32_t *data_fifo;
1787
1788 static void do_setup(void)
1789 {
1790         gintsts_data_t gintsts;
1791         hctsiz_data_t hctsiz;
1792         hcchar_data_t hcchar;
1793         haint_data_t haint;
1794         hcint_data_t hcint;
1795
1796         /* Enable HAINTs */
1797         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1798
1799         /* Enable HCINTs */
1800         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1801
1802         /* Read GINTSTS */
1803         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1804         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1805
1806         /* Read HAINT */
1807         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1808         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1809
1810         /* Read HCINT */
1811         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1812         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1813
1814         /* Read HCCHAR */
1815         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1816         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1817
1818         /* Clear HCINT */
1819         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1820
1821         /* Clear HAINT */
1822         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1823
1824         /* Clear GINTSTS */
1825         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1826
1827         /* Read GINTSTS */
1828         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1829         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1830
1831         /*
1832          * Send Setup packet (Get Device Descriptor)
1833          */
1834
1835         /* Make sure channel is disabled */
1836         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1837         if (hcchar.b.chen) {
1838                 //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32);
1839                 hcchar.b.chdis = 1;
1840 //              hcchar.b.chen = 1;
1841                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1842                 //sleep(1);
1843                 mdelay(1000);
1844
1845                 /* Read GINTSTS */
1846                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1847                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1848
1849                 /* Read HAINT */
1850                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1851                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1852
1853                 /* Read HCINT */
1854                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1855                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1856
1857                 /* Read HCCHAR */
1858                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1859                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1860
1861                 /* Clear HCINT */
1862                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1863
1864                 /* Clear HAINT */
1865                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1866
1867                 /* Clear GINTSTS */
1868                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1869
1870                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1871                 //if (hcchar.b.chen) {
1872                 //      fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32);
1873                 //}
1874         }
1875
1876         /* Set HCTSIZ */
1877         hctsiz.d32 = 0;
1878         hctsiz.b.xfersize = 8;
1879         hctsiz.b.pktcnt = 1;
1880         hctsiz.b.pid = DWC_OTG_HC_PID_SETUP;
1881         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
1882
1883         /* Set HCCHAR */
1884         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1885         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
1886         hcchar.b.epdir = 0;
1887         hcchar.b.epnum = 0;
1888         hcchar.b.mps = 8;
1889         hcchar.b.chen = 1;
1890         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1891
1892         /* Fill FIFO with Setup data for Get Device Descriptor */
1893         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
1894         dwc_write_reg32(data_fifo++, 0x01000680);
1895         dwc_write_reg32(data_fifo++, 0x00080000);
1896
1897         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1898         //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1899
1900         /* Wait for host channel interrupt */
1901         do {
1902                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1903         } while (gintsts.b.hcintr == 0);
1904
1905         //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32);
1906
1907         /* Disable HCINTs */
1908         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
1909
1910         /* Disable HAINTs */
1911         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
1912
1913         /* Read HAINT */
1914         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1915         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1916
1917         /* Read HCINT */
1918         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1919         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1920
1921         /* Read HCCHAR */
1922         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1923         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1924
1925         /* Clear HCINT */
1926         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1927
1928         /* Clear HAINT */
1929         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1930
1931         /* Clear GINTSTS */
1932         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1933
1934         /* Read GINTSTS */
1935         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1936         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1937 }
1938
1939 static void do_in_ack(void)
1940 {
1941         gintsts_data_t gintsts;
1942         hctsiz_data_t hctsiz;
1943         hcchar_data_t hcchar;
1944         haint_data_t haint;
1945         hcint_data_t hcint;
1946         host_grxsts_data_t grxsts;
1947
1948         /* Enable HAINTs */
1949         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001);
1950
1951         /* Enable HCINTs */
1952         dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3);
1953
1954         /* Read GINTSTS */
1955         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1956         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1957
1958         /* Read HAINT */
1959         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
1960         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
1961
1962         /* Read HCINT */
1963         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
1964         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
1965
1966         /* Read HCCHAR */
1967         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1968         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
1969
1970         /* Clear HCINT */
1971         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
1972
1973         /* Clear HAINT */
1974         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
1975
1976         /* Clear GINTSTS */
1977         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
1978
1979         /* Read GINTSTS */
1980         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1981         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
1982
1983         /*
1984          * Receive Control In packet
1985          */
1986
1987         /* Make sure channel is disabled */
1988         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
1989         if (hcchar.b.chen) {
1990                 //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32);
1991                 hcchar.b.chdis = 1;
1992                 hcchar.b.chen = 1;
1993                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
1994                 //sleep(1);
1995                 mdelay(1000);
1996
1997                 /* Read GINTSTS */
1998                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
1999                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2000
2001                 /* Read HAINT */
2002                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2003                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2004
2005                 /* Read HCINT */
2006                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2007                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2008
2009                 /* Read HCCHAR */
2010                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2011                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2012
2013                 /* Clear HCINT */
2014                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2015
2016                 /* Clear HAINT */
2017                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2018
2019                 /* Clear GINTSTS */
2020                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2021
2022                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2023                 //if (hcchar.b.chen) {
2024                 //      fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32);
2025                 //}
2026         }
2027
2028         /* Set HCTSIZ */
2029         hctsiz.d32 = 0;
2030         hctsiz.b.xfersize = 8;
2031         hctsiz.b.pktcnt = 1;
2032         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2033         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2034
2035         /* Set HCCHAR */
2036         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2037         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2038         hcchar.b.epdir = 1;
2039         hcchar.b.epnum = 0;
2040         hcchar.b.mps = 8;
2041         hcchar.b.chen = 1;
2042         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2043
2044         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2045         //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2046
2047         /* Wait for receive status queue interrupt */
2048         do {
2049                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2050         } while (gintsts.b.rxstsqlvl == 0);
2051
2052         //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32);
2053
2054         /* Read RXSTS */
2055         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2056         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2057
2058         /* Clear RXSTSQLVL in GINTSTS */
2059         gintsts.d32 = 0;
2060         gintsts.b.rxstsqlvl = 1;
2061         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2062
2063         switch (grxsts.b.pktsts) {
2064         case DWC_GRXSTS_PKTSTS_IN:
2065                 /* Read the data into the host buffer */
2066                 if (grxsts.b.bcnt > 0) {
2067                         int i;
2068                         int word_count = (grxsts.b.bcnt + 3) / 4;
2069
2070                         data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2071
2072                         for (i = 0; i < word_count; i++) {
2073                                 (void)dwc_read_reg32(data_fifo++);
2074                         }
2075                 }
2076
2077                 //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt);
2078         break;
2079
2080         default:
2081                 //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n");
2082         break;
2083         }
2084
2085         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2086         //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2087
2088         /* Wait for receive status queue interrupt */
2089         do {
2090                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2091         } while (gintsts.b.rxstsqlvl == 0);
2092
2093         //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32);
2094
2095         /* Read RXSTS */
2096         grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp);
2097         //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32);
2098
2099         /* Clear RXSTSQLVL in GINTSTS */
2100         gintsts.d32 = 0;
2101         gintsts.b.rxstsqlvl = 1;
2102         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2103
2104         switch (grxsts.b.pktsts) {
2105         case DWC_GRXSTS_PKTSTS_IN_XFER_COMP:
2106         break;
2107
2108         default:
2109                 //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n");
2110         break;
2111         }
2112
2113         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2114         //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2115
2116         /* Wait for host channel interrupt */
2117         do {
2118                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2119         } while (gintsts.b.hcintr == 0);
2120
2121         //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32);
2122
2123         /* Read HAINT */
2124         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2125         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2126
2127         /* Read HCINT */
2128         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2129         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2130
2131         /* Read HCCHAR */
2132         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2133         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2134
2135         /* Clear HCINT */
2136         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2137
2138         /* Clear HAINT */
2139         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2140
2141         /* Clear GINTSTS */
2142         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2143
2144         /* Read GINTSTS */
2145         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2146         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2147
2148 //      usleep(100000);
2149 //      mdelay(100);
2150         mdelay(1);
2151
2152         /*
2153          * Send handshake packet
2154          */
2155
2156         /* Read HAINT */
2157         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2158         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2159
2160         /* Read HCINT */
2161         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2162         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2163
2164         /* Read HCCHAR */
2165         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2166         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2167
2168         /* Clear HCINT */
2169         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2170
2171         /* Clear HAINT */
2172         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2173
2174         /* Clear GINTSTS */
2175         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2176
2177         /* Read GINTSTS */
2178         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2179         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2180
2181         /* Make sure channel is disabled */
2182         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2183         if (hcchar.b.chen) {
2184                 //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32);
2185                 hcchar.b.chdis = 1;
2186                 hcchar.b.chen = 1;
2187                 dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2188                 //sleep(1);
2189                 mdelay(1000);
2190
2191                 /* Read GINTSTS */
2192                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2193                 //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2194
2195                 /* Read HAINT */
2196                 haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2197                 //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2198
2199                 /* Read HCINT */
2200                 hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2201                 //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2202
2203                 /* Read HCCHAR */
2204                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2205                 //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2206
2207                 /* Clear HCINT */
2208                 dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2209
2210                 /* Clear HAINT */
2211                 dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2212
2213                 /* Clear GINTSTS */
2214                 dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2215
2216                 hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2217                 //if (hcchar.b.chen) {
2218                 //      fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32);
2219                 //}
2220         }
2221
2222         /* Set HCTSIZ */
2223         hctsiz.d32 = 0;
2224         hctsiz.b.xfersize = 0;
2225         hctsiz.b.pktcnt = 1;
2226         hctsiz.b.pid = DWC_OTG_HC_PID_DATA1;
2227         dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32);
2228
2229         /* Set HCCHAR */
2230         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2231         hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL;
2232         hcchar.b.epdir = 0;
2233         hcchar.b.epnum = 0;
2234         hcchar.b.mps = 8;
2235         hcchar.b.chen = 1;
2236         dwc_write_reg32(&hc_regs->hcchar, hcchar.d32);
2237
2238         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2239         //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2240
2241         /* Wait for host channel interrupt */
2242         do {
2243                 gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2244         } while (gintsts.b.hcintr == 0);
2245
2246         //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32);
2247
2248         /* Disable HCINTs */
2249         dwc_write_reg32(&hc_regs->hcintmsk, 0x0000);
2250
2251         /* Disable HAINTs */
2252         dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000);
2253
2254         /* Read HAINT */
2255         haint.d32 = dwc_read_reg32(&hc_global_regs->haint);
2256         //fprintf(stderr, "HAINT: %08x\n", haint.d32);
2257
2258         /* Read HCINT */
2259         hcint.d32 = dwc_read_reg32(&hc_regs->hcint);
2260         //fprintf(stderr, "HCINT: %08x\n", hcint.d32);
2261
2262         /* Read HCCHAR */
2263         hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar);
2264         //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32);
2265
2266         /* Clear HCINT */
2267         dwc_write_reg32(&hc_regs->hcint, hcint.d32);
2268
2269         /* Clear HAINT */
2270         dwc_write_reg32(&hc_global_regs->haint, haint.d32);
2271
2272         /* Clear GINTSTS */
2273         dwc_write_reg32(&global_regs->gintsts, gintsts.d32);
2274
2275         /* Read GINTSTS */
2276         gintsts.d32 = dwc_read_reg32(&global_regs->gintsts);
2277         //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32);
2278 }
2279 #endif /* DWC_HS_ELECT_TST */
2280
2281 /** Handles hub class-specific requests.*/
2282 int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd,
2283                             u16 _typeReq,
2284                             u16 _wValue,
2285                             u16 _wIndex,
2286                             char *_buf,
2287                             u16 _wLength)
2288 {
2289         int retval = 0;
2290         unsigned long flags;
2291
2292         dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd);
2293         dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if;
2294         struct usb_hub_descriptor *desc;
2295         hprt0_data_t hprt0 = {.d32 = 0};
2296
2297         uint32_t port_status;
2298         spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2299
2300         switch (_typeReq) {
2301         case ClearHubFeature:
2302                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2303                             "ClearHubFeature 0x%x\n", _wValue);
2304                 switch (_wValue) {
2305                 case C_HUB_LOCAL_POWER:
2306                 case C_HUB_OVER_CURRENT:
2307                         /* Nothing required here */
2308                         break;
2309                 default:
2310                         retval = -EINVAL;
2311                         DWC_ERROR ("DWC OTG HCD - "
2312                                    "ClearHubFeature request %xh unknown\n", _wValue);
2313                 }
2314                 break;
2315         case ClearPortFeature:
2316                 if (!_wIndex || _wIndex > 1)
2317                         goto error;
2318
2319                 switch (_wValue) {
2320                 case USB_PORT_FEAT_ENABLE:
2321                         DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - "
2322                                      "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
2323                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2324                         hprt0.b.prtena = 1;
2325                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2326                         break;
2327                 case USB_PORT_FEAT_SUSPEND:
2328                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2329                                      "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
2330                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2331                         hprt0.b.prtres = 1;
2332                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2333                         /* Clear Resume bit */
2334             spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2335                         mdelay (100);
2336             spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2337                         hprt0.b.prtres = 0;
2338                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2339                         break;
2340                 case USB_PORT_FEAT_POWER:
2341                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2342                                      "ClearPortFeature USB_PORT_FEAT_POWER\n");
2343                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2344                         hprt0.b.prtpwr = 0;
2345                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2346                         break;
2347                 case USB_PORT_FEAT_INDICATOR:
2348                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2349                                      "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
2350                         /* Port inidicator not supported */
2351                         break;
2352                 case USB_PORT_FEAT_C_CONNECTION:
2353                         /* Clears drivers internal connect status change
2354                          * flag */
2355                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2356                                      "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
2357                         dwc_otg_hcd->flags.b.port_connect_status_change = 0;
2358                         break;
2359                 case USB_PORT_FEAT_C_RESET:
2360                         /* Clears the driver's internal Port Reset Change
2361                          * flag */
2362                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2363                                      "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
2364                         dwc_otg_hcd->flags.b.port_reset_change = 0;
2365                         break;
2366                 case USB_PORT_FEAT_C_ENABLE:
2367                         /* Clears the driver's internal Port
2368                          * Enable/Disable Change flag */
2369                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2370                                      "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
2371                         dwc_otg_hcd->flags.b.port_enable_change = 0;
2372                         break;
2373                 case USB_PORT_FEAT_C_SUSPEND:
2374                         /* Clears the driver's internal Port Suspend
2375                          * Change flag, which is set when resume signaling on
2376                          * the host port is complete */
2377                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2378                                      "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
2379                         dwc_otg_hcd->flags.b.port_suspend_change = 0;
2380                         break;
2381                 case USB_PORT_FEAT_C_OVER_CURRENT:
2382                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2383                                      "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
2384                         dwc_otg_hcd->flags.b.port_over_current_change = 0;
2385                         break;
2386                 default:
2387                         retval = -EINVAL;
2388                         DWC_ERROR ("DWC OTG HCD - "
2389                                    "ClearPortFeature request %xh "
2390                                    "unknown or unsupported\n", _wValue);
2391                 }
2392                 break;
2393         case GetHubDescriptor:
2394                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2395                              "GetHubDescriptor\n");
2396                 desc = (struct usb_hub_descriptor *)_buf;
2397                 desc->bDescLength = 9;
2398                 desc->bDescriptorType = 0x29;
2399                 desc->bNbrPorts = 1;
2400                 desc->wHubCharacteristics = 0x08;
2401                 desc->bPwrOn2PwrGood = 1;
2402                 desc->bHubContrCurrent = 0;
2403 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39))
2404                 desc->u.hs.DeviceRemovable[0] = 0;
2405                 desc->u.hs.DeviceRemovable[1] = 0xff;
2406 #else
2407                 desc->bitmap[0] = 0;
2408                 desc->bitmap[1] = 0xff;
2409 #endif
2410                 break;
2411         case GetHubStatus:
2412                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2413                              "GetHubStatus\n");
2414                 memset (_buf, 0, 4);
2415                 break;
2416         case GetPortStatus:
2417                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2418                              "GetPortStatus\n");
2419
2420                 if (!_wIndex || _wIndex > 1)
2421                         goto error;
2422
2423                 port_status = 0;
2424
2425                 if (dwc_otg_hcd->flags.b.port_connect_status_change)
2426                         port_status |= (1 << USB_PORT_FEAT_C_CONNECTION);
2427
2428                 if (dwc_otg_hcd->flags.b.port_enable_change)
2429                         port_status |= (1 << USB_PORT_FEAT_C_ENABLE);
2430
2431                 if (dwc_otg_hcd->flags.b.port_suspend_change)
2432                         port_status |= (1 << USB_PORT_FEAT_C_SUSPEND);
2433
2434                 if (dwc_otg_hcd->flags.b.port_reset_change)
2435                         port_status |= (1 << USB_PORT_FEAT_C_RESET);
2436
2437                 if (dwc_otg_hcd->flags.b.port_over_current_change) {
2438                         DWC_ERROR("Device Not Supported\n");
2439                         port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT);
2440                 }
2441
2442                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2443                         /*
2444                          * The port is disconnected, which means the core is
2445                          * either in device mode or it soon will be. Just
2446                          * return 0's for the remainder of the port status
2447                          * since the port register can't be read if the core
2448                          * is in device mode.
2449                          */
2450                         *((__le32 *) _buf) = cpu_to_le32(port_status);
2451                         break;
2452                 }
2453
2454                 hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0);
2455                 DWC_DEBUGPL(DBG_HCDV, "  HPRT0: 0x%08x\n", hprt0.d32);
2456
2457                 if (hprt0.b.prtconnsts)
2458                         port_status |= (1 << USB_PORT_FEAT_CONNECTION);
2459
2460                 if (hprt0.b.prtena)
2461                         port_status |= (1 << USB_PORT_FEAT_ENABLE);
2462
2463                 if (hprt0.b.prtsusp)
2464                         port_status |= (1 << USB_PORT_FEAT_SUSPEND);
2465
2466                 if (hprt0.b.prtovrcurract)
2467                         port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT);
2468
2469                 if (hprt0.b.prtrst)
2470                         port_status |= (1 << USB_PORT_FEAT_RESET);
2471
2472                 if (hprt0.b.prtpwr)
2473                         port_status |= (1 << USB_PORT_FEAT_POWER);
2474
2475                 if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED)
2476                         port_status |= USB_PORT_STAT_HIGH_SPEED;
2477
2478                 else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED)
2479                         port_status |= USB_PORT_STAT_LOW_SPEED;
2480
2481                 if (hprt0.b.prttstctl)
2482                         port_status |= (1 << USB_PORT_FEAT_TEST);
2483
2484                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
2485
2486                 *((__le32 *) _buf) = cpu_to_le32(port_status);
2487
2488                 break;
2489         case SetHubFeature:
2490                 DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2491                              "SetHubFeature\n");
2492                 /* No HUB features supported */
2493                 break;
2494         case SetPortFeature:
2495                 if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1))
2496                         goto error;
2497
2498                 if (!dwc_otg_hcd->flags.b.port_connect_status) {
2499                         /*
2500                          * The port is disconnected, which means the core is
2501                          * either in device mode or it soon will be. Just
2502                          * return without doing anything since the port
2503                          * register can't be written if the core is in device
2504                          * mode.
2505                          */
2506                         break;
2507                 }
2508
2509                 switch (_wValue) {
2510                 case USB_PORT_FEAT_SUSPEND:
2511                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2512                                      "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
2513                         if (_hcd->self.otg_port == _wIndex &&
2514                             _hcd->self.b_hnp_enable) {
2515                                 gotgctl_data_t  gotgctl = {.d32=0};
2516                                 gotgctl.b.hstsethnpen = 1;
2517                                 dwc_modify_reg32( &core_if->core_global_regs->gotgctl,
2518                                                   0, gotgctl.d32);
2519                                 core_if->op_state = A_SUSPEND;
2520                         }
2521                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2522                         hprt0.b.prtsusp = 1;
2523                                     dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2524                         //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32);
2525                         /* Suspend the Phy Clock */
2526                         {
2527                                 pcgcctl_data_t pcgcctl = {.d32=0};
2528                                 pcgcctl.b.stoppclk = 1;
2529                                 dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32);
2530                         }
2531
2532                         /* For HNP the bus must be suspended for at least 200ms.*/
2533                         if (_hcd->self.b_hnp_enable) {
2534                                 spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2535                                 mdelay(200);
2536                                 spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2537                                 //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state);
2538                         }
2539                         break;
2540                 case USB_PORT_FEAT_POWER:
2541                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2542                                      "SetPortFeature - USB_PORT_FEAT_POWER\n");
2543                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2544                         hprt0.b.prtpwr = 1;
2545                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2546                         break;
2547                 case USB_PORT_FEAT_RESET:
2548                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2549                                      "SetPortFeature - USB_PORT_FEAT_RESET\n");
2550                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2551                         /* When B-Host the Port reset bit is set in
2552                          * the Start HCD Callback function, so that
2553                          * the reset is started within 1ms of the HNP
2554                          * success interrupt. */
2555                         if (!_hcd->self.is_b_host) {
2556                                 hprt0.b.prtrst = 1;
2557                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2558                         }
2559             spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2560                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
2561                         // kever @rk 20110712
2562                         // can not use mdelay(60) while irq disable
2563                         //MDELAY (60);
2564                         msleep(60);
2565             spin_lock_irqsave(&dwc_otg_hcd->global_lock, flags);
2566                         hprt0.b.prtrst = 0;
2567                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2568                         break;
2569
2570 #ifdef DWC_HS_ELECT_TST
2571                 case USB_PORT_FEAT_TEST:
2572                 {
2573                         uint32_t t;
2574                         gintmsk_data_t gintmsk;
2575
2576                         t = (_wIndex >> 8); /* MSB wIndex USB */
2577                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2578                                      "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t);
2579                         warn("USB_PORT_FEAT_TEST %d\n", t);
2580                         if (t < 6) {
2581                                 hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2582                                 hprt0.b.prttstctl = t;
2583                                 dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2584                         } else {
2585                                 /* Setup global vars with reg addresses (quick and
2586                                  * dirty hack, should be cleaned up)
2587                                  */
2588                                 global_regs = core_if->core_global_regs;
2589                                 hc_global_regs = core_if->host_if->host_global_regs;
2590                                 hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500);
2591                                 data_fifo = (uint32_t *)((char *)global_regs + 0x1000);
2592
2593                                 if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */
2594                                         /* Save current interrupt mask */
2595                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2596
2597                                         /* Disable all interrupts while we muck with
2598                                          * the hardware directly
2599                                          */
2600                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2601
2602                                         /* 15 second delay per the test spec */
2603                                         mdelay(15000);
2604
2605                                         /* Drive suspend on the root port */
2606                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2607                                         hprt0.b.prtsusp = 1;
2608                                         hprt0.b.prtres = 0;
2609                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2610
2611                                         /* 15 second delay per the test spec */
2612                                         mdelay(15000);
2613
2614                                         /* Drive resume on the root port */
2615                                         hprt0.d32 = dwc_otg_read_hprt0 (core_if);
2616                                         hprt0.b.prtsusp = 0;
2617                                         hprt0.b.prtres = 1;
2618                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2619                                         mdelay(100);
2620
2621                                         /* Clear the resume bit */
2622                                         hprt0.b.prtres = 0;
2623                                         dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32);
2624
2625                                         /* Restore interrupts */
2626                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2627                                 } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */
2628                                         /* Save current interrupt mask */
2629                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2630
2631                                         /* Disable all interrupts while we muck with
2632                                          * the hardware directly
2633                                          */
2634                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2635
2636                                         /* 15 second delay per the test spec */
2637                                         mdelay(15000);
2638
2639                                         /* Send the Setup packet */
2640                                         do_setup();
2641
2642                                         /* 15 second delay so nothing else happens for awhile */
2643                                         mdelay(15000);
2644
2645                                         /* Restore interrupts */
2646                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2647                                 } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */
2648                                         /* Save current interrupt mask */
2649                                         gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk);
2650
2651                                         /* Disable all interrupts while we muck with
2652                                          * the hardware directly
2653                                          */
2654                                         dwc_write_reg32(&global_regs->gintmsk, 0);
2655
2656                                         /* Send the Setup packet */
2657                                         do_setup();
2658
2659                                         /* 15 second delay so nothing else happens for awhile */
2660                                         mdelay(15000);
2661
2662                                         /* Send the In and Ack packets */
2663                                         do_in_ack();
2664
2665                                         /* 15 second delay so nothing else happens for awhile */
2666                                         mdelay(15000);
2667
2668                                         /* Restore interrupts */
2669                                         dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32);
2670                                 }
2671                         }
2672                         break;
2673                 }
2674 #endif /* DWC_HS_ELECT_TST */
2675
2676                 case USB_PORT_FEAT_INDICATOR:
2677                         DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - "
2678                                      "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
2679                         /* Not supported */
2680                         break;
2681                 default:
2682                         retval = -EINVAL;
2683                         DWC_ERROR ("DWC OTG HCD - "
2684                                    "SetPortFeature request %xh "
2685                                    "unknown or unsupported\n", _wValue);
2686                         break;
2687                 }
2688                 break;
2689         default:
2690         error:
2691                 retval = -EINVAL;
2692                 DWC_WARN ("DWC OTG HCD - "
2693                           "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n",
2694                           _typeReq, _wIndex, _wValue);
2695                 break;
2696         }
2697
2698         spin_unlock_irqrestore(&dwc_otg_hcd->global_lock, flags);
2699         return retval;
2700 }
2701
2702
2703 /**
2704  * Assigns transactions from a QTD to a free host channel and initializes the
2705  * host channel to perform the transactions. The host channel is removed from
2706  * the free list.
2707  *
2708  * @param _hcd The HCD state structure.
2709  * @param _qh Transactions from the first QTD for this QH are selected and
2710  * assigned to a free host channel.
2711  */
2712 static int assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh)
2713 {
2714         dwc_hc_t        *hc;
2715         dwc_otg_qtd_t   *qtd;
2716         struct urb      *urb;
2717         int  retval = 0;
2718
2719         DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh);
2720         hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry);
2721
2722         /* Remove the host channel from the free list. */
2723         list_del_init(&hc->hc_list_entry);
2724
2725         qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry);
2726         urb = qtd->urb;
2727         if (urb == NULL){
2728                 printk("%s : urb is NULL\n", __func__);
2729                 retval = -EINVAL;
2730                 return retval;
2731         }else{
2732                 _qh->channel = hc;
2733                 _qh->qtd_in_process = qtd;
2734
2735         /*
2736          * Use usb_pipedevice to determine device address. This address is
2737          * 0 before the SET_ADDRESS command and the correct address afterward.
2738          */
2739         hc->dev_addr = usb_pipedevice(urb->pipe);
2740         hc->ep_num = usb_pipeendpoint(urb->pipe);
2741
2742         if (urb->dev->speed == USB_SPEED_LOW) {
2743                 hc->speed = DWC_OTG_EP_SPEED_LOW;
2744                 /*
2745                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2746                  * device connected.
2747                  */
2748         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2749         } else if (urb->dev->speed == USB_SPEED_FULL) {
2750                 hc->speed = DWC_OTG_EP_SPEED_FULL;
2751                 /*
2752                  * yk@rk 20101216 fix bandwidth check error when full/low speed
2753                  * device connected. warning: only support 1 device at root hub.
2754                  */
2755         _hcd->core_if->core_params->speed = DWC_SPEED_PARAM_FULL;
2756         } else {
2757                 hc->speed = DWC_OTG_EP_SPEED_HIGH;
2758         }
2759
2760         hc->max_packet = dwc_max_packet(_qh->maxp);
2761
2762         hc->xfer_started = 0;
2763         hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS;
2764         hc->error_state = (qtd->error_count > 0);
2765         hc->halt_on_queue = 0;
2766         hc->halt_pending = 0;
2767         hc->requests = 0;
2768
2769         /*
2770          * The following values may be modified in the transfer type section
2771          * below. The xfer_len value may be reduced when the transfer is
2772          * started to accommodate the max widths of the XferSize and PktCnt
2773          * fields in the HCTSIZn register.
2774          */
2775         hc->do_ping = _qh->ping_state;
2776         hc->ep_is_in = (usb_pipein(urb->pipe) != 0);
2777         hc->data_pid_start = _qh->data_toggle;
2778         hc->multi_count = 1;
2779
2780         if (_hcd->core_if->dma_enable) {
2781                 hc->xfer_buff = (uint8_t *)urb->transfer_dma + urb->actual_length;
2782         } else {
2783                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length;
2784         }
2785         hc->xfer_len = urb->transfer_buffer_length - urb->actual_length;
2786         hc->xfer_count = 0;
2787
2788         /*
2789          * Set the split attributes
2790          */
2791         hc->do_split = 0;
2792         if (_qh->do_split) {
2793                 hc->do_split = 1;
2794                 hc->xact_pos = qtd->isoc_split_pos;
2795                 hc->complete_split = qtd->complete_split;
2796                 hc->hub_addr = urb->dev->tt->hub->devnum;
2797                 hc->port_addr = urb->dev->ttport;
2798         }
2799
2800         switch (usb_pipetype(urb->pipe)) {
2801         case PIPE_CONTROL:
2802                 hc->ep_type = DWC_OTG_EP_TYPE_CONTROL;
2803                 switch (qtd->control_phase) {
2804                 case DWC_OTG_CONTROL_SETUP:
2805                         DWC_DEBUGPL(DBG_HCDV, "  Control setup transaction\n");
2806                         hc->do_ping = 0;
2807                         hc->ep_is_in = 0;
2808                         hc->data_pid_start = DWC_OTG_HC_PID_SETUP;
2809                         if (_hcd->core_if->dma_enable) {
2810                                 hc->xfer_buff = (uint8_t *)urb->setup_dma;
2811                         } else {
2812                                 hc->xfer_buff = (uint8_t *)urb->setup_packet;
2813                         }
2814                         hc->xfer_len = 8;
2815                         break;
2816                 case DWC_OTG_CONTROL_DATA:
2817                         DWC_DEBUGPL(DBG_HCDV, "  Control data transaction\n");
2818                         hc->data_pid_start = qtd->data_toggle;
2819                         break;
2820                 case DWC_OTG_CONTROL_STATUS:
2821                         /*
2822                          * Direction is opposite of data direction or IN if no
2823                          * data.
2824                          */
2825                         DWC_DEBUGPL(DBG_HCDV, "  Control status transaction\n");
2826                         if (urb->transfer_buffer_length == 0) {
2827                                 hc->ep_is_in = 1;
2828                         } else {
2829                                 hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN);
2830                         }
2831                         if (hc->ep_is_in) {
2832                                 hc->do_ping = 0;
2833                         }
2834                         hc->data_pid_start = DWC_OTG_HC_PID_DATA1;
2835                         hc->xfer_len = 0;
2836                         if (_hcd->core_if->dma_enable) {
2837                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma;
2838                         } else {
2839                                 hc->xfer_buff = (uint8_t *)_hcd->status_buf;
2840                         }
2841                         break;
2842                 }
2843                 break;
2844         case PIPE_BULK:
2845                 hc->ep_type = DWC_OTG_EP_TYPE_BULK;
2846                 break;
2847         case PIPE_INTERRUPT:
2848                 hc->ep_type = DWC_OTG_EP_TYPE_INTR;
2849                 break;
2850         case PIPE_ISOCHRONOUS:
2851                 {
2852                         struct usb_iso_packet_descriptor *frame_desc;
2853                         frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index];
2854                         hc->ep_type = DWC_OTG_EP_TYPE_ISOC;
2855                         if (_hcd->core_if->dma_enable) {
2856                                 hc->xfer_buff = (uint8_t *)urb->transfer_dma;
2857                         } else {
2858                                 hc->xfer_buff = (uint8_t *)urb->transfer_buffer;
2859                         }
2860                         hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset;
2861                         hc->xfer_len = frame_desc->length - qtd->isoc_split_offset;
2862
2863                         if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) {
2864                                 if (hc->xfer_len <= 188) {
2865                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL;
2866                                 }
2867                                 else {
2868                                         hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN;
2869                                 }
2870                         }
2871                 }
2872                 break;
2873         }
2874
2875         if (hc->ep_type == DWC_OTG_EP_TYPE_INTR ||
2876             hc->ep_type == DWC_OTG_EP_TYPE_ISOC) {
2877                 /*
2878                  * This value may be modified when the transfer is started to
2879                  * reflect the actual transfer length.
2880                  */
2881                 hc->multi_count = dwc_hb_mult(_qh->maxp);
2882         }
2883
2884         dwc_otg_hc_init(_hcd->core_if, hc);
2885         hc->qh = _qh;
2886         return retval;
2887         }
2888 }
2889
2890 /**
2891  * This function selects transactions from the HCD transfer schedule and
2892  * assigns them to available host channels. It is called from HCD interrupt
2893  * handler functions.
2894  *
2895  * @param _hcd The HCD state structure.
2896  *
2897  * @return The types of new transactions that were assigned to host channels.
2898  */
2899 dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd)
2900 {
2901         struct list_head                *qh_ptr;
2902         dwc_otg_qh_t                    *qh;
2903         int                             num_channels;
2904         dwc_otg_transaction_type_e      ret_val = DWC_OTG_TRANSACTION_NONE;
2905         int err;
2906
2907 #ifdef DEBUG_SOF
2908         DWC_DEBUGPL(DBG_HCD, "  Select Transactions\n");
2909 #endif
2910
2911         /* Process entries in the periodic ready list. */
2912         qh_ptr = _hcd->periodic_sched_inactive.next;
2913         while ((qh_ptr != &_hcd->periodic_sched_inactive)&&
2914                !list_empty(&_hcd->free_hc_list)) {
2915                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2916                 if(qh->qh_state != QH_READY){
2917                 qh_ptr = qh_ptr->next;
2918                 continue;
2919                 }
2920
2921                 assign_and_init_hc(_hcd, qh);
2922
2923                 /*
2924                  * Move the QH from the periodic ready schedule to the
2925                  * periodic assigned schedule.
2926                  */
2927                 qh_ptr = qh_ptr->next;
2928                 //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_assigned);
2929                 qh->qh_state = QH_ASSIGNED;
2930
2931                 ret_val = DWC_OTG_TRANSACTION_PERIODIC;
2932         }
2933
2934         /*
2935          * Process entries in the inactive portion of the non-periodic
2936          * schedule. Some free host channels may not be used if they are
2937          * reserved for periodic transfers.
2938          */
2939         qh_ptr = _hcd->non_periodic_sched_inactive.next;
2940         num_channels = _hcd->core_if->core_params->host_channels;
2941         while (qh_ptr != &_hcd->non_periodic_sched_inactive &&
2942                 /*yk@rk 20100714
2943                (_hcd->non_periodic_channels <
2944                 num_channels - _hcd->periodic_channels) &&
2945                 */
2946                !list_empty(&_hcd->free_hc_list)) {
2947
2948                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
2949                 err = assign_and_init_hc(_hcd, qh);
2950
2951                 /*
2952                  * Move the QH from the non-periodic inactive schedule to the
2953                  * non-periodic active schedule.
2954                  */
2955                 qh_ptr = qh_ptr->next;
2956                 if (err != 0)
2957                         continue;
2958                 list_move_tail(&qh->qh_list_entry, &_hcd->non_periodic_sched_active);
2959
2960                 if (ret_val == DWC_OTG_TRANSACTION_NONE) {
2961                         ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC;
2962                 } else {
2963                         ret_val = DWC_OTG_TRANSACTION_ALL;
2964                 }
2965
2966                 _hcd->non_periodic_channels++;
2967         }
2968
2969         return ret_val;
2970 }
2971
2972 /**
2973  * Attempts to queue a single transaction request for a host channel
2974  * associated with either a periodic or non-periodic transfer. This function
2975  * assumes that there is space available in the appropriate request queue. For
2976  * an OUT transfer or SETUP transaction in Slave mode, it checks whether space
2977  * is available in the appropriate Tx FIFO.
2978  *
2979  * @param _hcd The HCD state structure.
2980  * @param _hc Host channel descriptor associated with either a periodic or
2981  * non-periodic transfer.
2982  * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx
2983  * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic
2984  * transfers.
2985  *
2986  * @return 1 if a request is queued and more requests may be needed to
2987  * complete the transfer, 0 if no more requests are required for this
2988  * transfer, -1 if there is insufficient space in the Tx FIFO.
2989  */
2990 static int queue_transaction(dwc_otg_hcd_t *_hcd,
2991                              dwc_hc_t *_hc,
2992                              uint16_t _fifo_dwords_avail)
2993 {
2994         int retval;
2995
2996         if (_hcd->core_if->dma_enable) {
2997                 if (!_hc->xfer_started) {
2998                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
2999                         _hc->qh->ping_state = 0;
3000                 }
3001                 retval = 0;
3002         } else  if (_hc->halt_pending) {
3003                 /* Don't queue a request if the channel has been halted. */
3004                 retval = 0;
3005         } else if (_hc->halt_on_queue) {
3006                 dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status);
3007                 retval = 0;
3008         } else if (_hc->do_ping) {
3009                 if (!_hc->xfer_started) {
3010                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3011                 }
3012                 retval = 0;
3013         } else if (!_hc->ep_is_in ||
3014                    _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) {
3015                 if ((_fifo_dwords_avail * 4) >= _hc->max_packet) {
3016                         if (!_hc->xfer_started) {
3017                                 dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3018                                 retval = 1;
3019                         } else {
3020                                 retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3021                         }
3022                 } else {
3023                         retval = -1;
3024                 }
3025         } else {
3026                 if (!_hc->xfer_started) {
3027                         dwc_otg_hc_start_transfer(_hcd->core_if, _hc);
3028                         retval = 1;
3029                 } else {
3030                         retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc);
3031                 }
3032         }
3033
3034         return retval;
3035 }
3036
3037 /**
3038  * Processes active non-periodic channels and queues transactions for these
3039  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
3040  * FIFO Empty interrupt is enabled if there are more transactions to queue as
3041  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
3042  * FIFO Empty interrupt is disabled.
3043  */
3044 static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd)
3045 {
3046         gnptxsts_data_t         tx_status;
3047         struct list_head        *orig_qh_ptr;
3048         dwc_otg_qh_t            *qh;
3049         int                     status;
3050         int                     no_queue_space = 0;
3051         int                     no_fifo_space = 0;
3052         int                     more_to_do = 0;
3053
3054         dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs;
3055
3056         DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n");
3057 #ifdef DEBUG
3058         tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3059         DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (before queue): %d\n",
3060                     tx_status.b.nptxqspcavail);
3061         DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (before queue): %d\n",
3062                     tx_status.b.nptxfspcavail);
3063 #endif
3064         /*
3065          * Keep track of the starting point. Skip over the start-of-list
3066          * entry.
3067          */
3068         if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3069                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3070         }
3071         orig_qh_ptr = _hcd->non_periodic_qh_ptr;
3072
3073         /*
3074          * Process once through the active list or until no more space is
3075          * available in the request queue or the Tx FIFO.
3076          */
3077         do {
3078                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3079                 if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) {
3080                         no_queue_space = 1;
3081                         break;
3082                 }
3083
3084                 qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry);
3085                 status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail);
3086
3087                 if (status > 0) {
3088                         more_to_do = 1;
3089                 } else if (status < 0) {
3090                         no_fifo_space = 1;
3091                         break;
3092                 }
3093
3094                 /* Advance to next QH, skipping start-of-list entry. */
3095                 _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3096                 if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) {
3097                         _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next;
3098                 }
3099
3100         } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr);
3101
3102         if (!_hcd->core_if->dma_enable) {
3103                 gintmsk_data_t intr_mask = {.d32 = 0};
3104                 intr_mask.b.nptxfempty = 1;
3105
3106 #ifdef DEBUG
3107                 tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts);
3108                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx Req Queue Space Avail (after queue): %d\n",
3109                             tx_status.b.nptxqspcavail);
3110                 DWC_DEBUGPL(DBG_HCDV, "  NP Tx FIFO Space Avail (after queue): %d\n",
3111                             tx_status.b.nptxfspcavail);
3112 #endif
3113                 if (more_to_do || no_queue_space || no_fifo_space) {
3114                         /*
3115                          * May need to queue more transactions as the request
3116                          * queue or Tx FIFO empties. Enable the non-periodic
3117                          * Tx FIFO empty interrupt. (Always use the half-empty
3118                          * level to ensure that new requests are loaded as
3119                          * soon as possible.)
3120                          */
3121                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3122                 } else {
3123                         /*
3124                          * Disable the Tx FIFO empty interrupt since there are
3125                          * no more transactions that need to be queued right
3126                          * now. This function is called from interrupt
3127                          * handlers to queue more transactions as transfer
3128                          * states change.
3129                          */
3130                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3131                 }
3132         }
3133 }
3134
3135 /**
3136  * Processes periodic channels for the next frame and queues transactions for
3137  * these channels to the DWC_otg controller. After queueing transactions, the
3138  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
3139  * to queue as Periodic Tx FIFO or request queue space becomes available.
3140  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
3141  */
3142 static void process_periodic_channels(dwc_otg_hcd_t *_hcd)
3143 {
3144         hptxsts_data_t          tx_status;
3145         struct list_head        *qh_ptr;
3146         dwc_otg_qh_t            *qh;
3147         int                     status;
3148         int                     no_queue_space = 0;
3149         int                     no_fifo_space = 0;
3150
3151         dwc_otg_host_global_regs_t *host_regs;
3152         host_regs = _hcd->core_if->host_if->host_global_regs;
3153
3154         DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n");
3155 #ifdef DEBUG
3156         tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3157         DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (before queue): %d\n",
3158                     tx_status.b.ptxqspcavail);
3159         DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (before queue): %d\n",
3160                     tx_status.b.ptxfspcavail);
3161 #endif
3162
3163         qh_ptr = _hcd->periodic_sched_inactive.next;
3164         while (qh_ptr != &_hcd->periodic_sched_inactive) {
3165                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3166                 if (tx_status.b.ptxqspcavail == 0) {
3167                         no_queue_space = 1;
3168                         break;
3169                 }
3170
3171                 qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry);
3172                 if(qh->qh_state != QH_ASSIGNED){
3173                 qh_ptr = qh_ptr->next;
3174                 continue;
3175                 }
3176
3177                 /*
3178                  * Set a flag if we're queuing high-bandwidth in slave mode.
3179                  * The flag prevents any halts to get into the request queue in
3180                  * the middle of multiple high-bandwidth packets getting queued.
3181                  */
3182                 if ((!_hcd->core_if->dma_enable) &&
3183                     (qh->channel->multi_count > 1))
3184                 {
3185                         _hcd->core_if->queuing_high_bandwidth = 1;
3186                 }
3187
3188                 status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail);
3189                 if (status < 0) {
3190                         no_fifo_space = 1;
3191                         break;
3192                 }
3193
3194                 /*
3195                  * In Slave mode, stay on the current transfer until there is
3196                  * nothing more to do or the high-bandwidth request count is
3197                  * reached. In DMA mode, only need to queue one request. The
3198                  * controller automatically handles multiple packets for
3199                  * high-bandwidth transfers.
3200                  */
3201                 if (_hcd->core_if->dma_enable ||
3202                     (status == 0 ||
3203                      qh->channel->requests == qh->channel->multi_count)) {
3204                         qh_ptr = qh_ptr->next;
3205                         /*
3206                          * Move the QH from the periodic assigned schedule to
3207                          * the periodic queued schedule.
3208                          */
3209                         //list_move_tail(&qh->qh_list_entry, &_hcd->periodic_sched_queued);
3210                         qh->qh_state = QH_QUEUED;
3211
3212                         /* done queuing high bandwidth */
3213                         _hcd->core_if->queuing_high_bandwidth = 0;
3214                 }
3215         }
3216
3217         if (!_hcd->core_if->dma_enable) {
3218                 dwc_otg_core_global_regs_t *global_regs;
3219                 gintmsk_data_t intr_mask = {.d32 = 0};
3220
3221                 global_regs = _hcd->core_if->core_global_regs;
3222                 intr_mask.b.ptxfempty = 1;
3223 #ifdef DEBUG
3224                 tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts);
3225                 DWC_DEBUGPL(DBG_HCDV, "  P Tx Req Queue Space Avail (after queue): %d\n",
3226                             tx_status.b.ptxqspcavail);
3227                 DWC_DEBUGPL(DBG_HCDV, "  P Tx FIFO Space Avail (after queue): %d\n",
3228                             tx_status.b.ptxfspcavail);
3229 #endif
3230                 if (//!(list_empty(&_hcd->periodic_sched_assigned)) ||
3231                     no_queue_space || no_fifo_space) {
3232                         /*
3233                          * May need to queue more transactions as the request
3234                          * queue or Tx FIFO empties. Enable the periodic Tx
3235                          * FIFO empty interrupt. (Always use the half-empty
3236                          * level to ensure that new requests are loaded as
3237                          * soon as possible.)
3238                          */
3239                         dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32);
3240                 } else {
3241                         /*
3242                          * Disable the Tx FIFO empty interrupt since there are
3243                          * no more transactions that need to be queued right
3244                          * now. This function is called from interrupt
3245                          * handlers to queue more transactions as transfer
3246                          * states change.
3247                          */
3248                         dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0);
3249                 }
3250         }
3251 }
3252
3253 /**
3254  * This function processes the currently active host channels and queues
3255  * transactions for these channels to the DWC_otg controller. It is called
3256  * from HCD interrupt handler functions.
3257  *
3258  * @param _hcd The HCD state structure.
3259  * @param _tr_type The type(s) of transactions to queue (non-periodic,
3260  * periodic, or both).
3261  */
3262 void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd,
3263                                     dwc_otg_transaction_type_e _tr_type)
3264 {
3265 #ifdef DEBUG_SOF
3266         DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n");
3267 #endif
3268         /* Process host channels associated with periodic transfers. */
3269         if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC ||
3270              _tr_type == DWC_OTG_TRANSACTION_ALL) //&&
3271             //!list_empty(&_hcd->periodic_sched_assigned)
3272             ) {
3273
3274                 process_periodic_channels(_hcd);
3275         }
3276
3277         /* Process host channels associated with non-periodic transfers. */
3278         if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC ||
3279              _tr_type == DWC_OTG_TRANSACTION_ALL)) {
3280                 if (!list_empty(&_hcd->non_periodic_sched_active)) {
3281                         process_non_periodic_channels(_hcd);
3282                 } else {
3283                         /*
3284                          * Ensure NP Tx FIFO empty interrupt is disabled when
3285                          * there are no non-periodic transfers to process.
3286                          */
3287                         gintmsk_data_t gintmsk = {.d32 = 0};
3288                         gintmsk.b.nptxfempty = 1;
3289                         dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk,
3290                                          gintmsk.d32, 0);
3291                 }
3292         }
3293 }
3294
3295 /**
3296  * Sets the final status of an URB and returns it to the device driver. Any
3297  * required cleanup of the URB is performed.
3298  */
3299 void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb,
3300                               int _status)
3301 __releases(_hcd->lock)
3302 __acquires(_hcd->lock)
3303 {
3304
3305 #ifdef DEBUG
3306         if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) {
3307                 DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n",
3308                           __func__, _urb, usb_pipedevice(_urb->pipe),
3309                           usb_pipeendpoint(_urb->pipe),
3310                           usb_pipein(_urb->pipe) ? "IN" : "OUT", _status);
3311                 if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) {
3312                         int i;
3313                         for (i = 0; i < _urb->number_of_packets; i++) {
3314                                 DWC_PRINT("  ISO Desc %d status: %d\n",
3315                                           i, _urb->iso_frame_desc[i].status);
3316                         }
3317                 }
3318         }
3319 #endif
3320
3321         _urb->status = _status;
3322         _urb->hcpriv = NULL;
3323         spin_unlock(&_hcd->global_lock);
3324         usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status);
3325         spin_lock(&_hcd->global_lock);
3326 }
3327
3328 void dwc_otg_clear_halt(struct urb *_urb)
3329 {
3330         struct dwc_otg_qh *_qh;
3331         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3332         if((ep)&&(ep->hcpriv))
3333         {
3334                 _qh =  (dwc_otg_qh_t *) ep->hcpriv;
3335                 _qh->data_toggle = 0;
3336         }
3337 }
3338 /*
3339  * Returns the Queue Head for an URB.
3340  */
3341 dwc_otg_qh_t * dwc_urb_to_qh(struct urb *_urb)
3342 {
3343         struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb);
3344         return (dwc_otg_qh_t *) ep->hcpriv;
3345 }
3346
3347 #ifdef DEBUG
3348 void dwc_print_setup_data (uint8_t *setup)
3349 {
3350         int i;
3351         if (CHK_DEBUG_LEVEL(DBG_HCD)){
3352                 DWC_PRINT("Setup Data = MSB ");
3353                 for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]);
3354                 DWC_PRINT("\n");
3355                 DWC_PRINT("  bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device");
3356                 DWC_PRINT("  bmRequestType Type = ");
3357                 switch ((setup[0]&0x60) >> 5) {
3358                 case 0: DWC_PRINT("Standard\n"); break;
3359                 case 1: DWC_PRINT("Class\n"); break;
3360                 case 2: DWC_PRINT("Vendor\n"); break;
3361                 case 3: DWC_PRINT("Reserved\n"); break;
3362                 }
3363                 DWC_PRINT("  bmRequestType Recipient = ");
3364                 switch (setup[0]&0x1f) {
3365                 case 0: DWC_PRINT("Device\n"); break;
3366                 case 1: DWC_PRINT("Interface\n"); break;
3367                 case 2: DWC_PRINT("Endpoint\n"); break;
3368                 case 3: DWC_PRINT("Other\n"); break;
3369                 default: DWC_PRINT("Reserved\n"); break;
3370                 }
3371                 DWC_PRINT("  bRequest = 0x%0x\n", setup[1]);
3372                 DWC_PRINT("  wValue = 0x%0x\n", *((uint16_t *)&setup[2]));
3373                 DWC_PRINT("  wIndex = 0x%0x\n", *((uint16_t *)&setup[4]));
3374                 DWC_PRINT("  wLength = 0x%0x\n\n", *((uint16_t *)&setup[6]));
3375         }
3376 }
3377 #endif
3378
3379 void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) {
3380 #if 0
3381         DWC_PRINT("Frame remaining at SOF:\n");
3382         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3383                   _hcd->frrem_samples, _hcd->frrem_accum,
3384                   (_hcd->frrem_samples > 0) ?
3385                   _hcd->frrem_accum/_hcd->frrem_samples : 0);
3386
3387         DWC_PRINT("\n");
3388         DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n");
3389         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3390                   _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum,
3391                   (_hcd->core_if->hfnum_7_samples > 0) ?
3392                   _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0);
3393         DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n");
3394         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3395                   _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum,
3396                   (_hcd->core_if->hfnum_0_samples > 0) ?
3397                   _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0);
3398         DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n");
3399         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3400                   _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum,
3401                   (_hcd->core_if->hfnum_other_samples > 0) ?
3402                   _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0);
3403
3404         DWC_PRINT("\n");
3405         DWC_PRINT("Frame remaining at sample point A (uframe 7):\n");
3406         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3407                   _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a,
3408                   (_hcd->hfnum_7_samples_a > 0) ?
3409                   _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0);
3410         DWC_PRINT("Frame remaining at sample point A (uframe 0):\n");
3411         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3412                   _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a,
3413                   (_hcd->hfnum_0_samples_a > 0) ?
3414                   _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0);
3415         DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n");
3416         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3417                   _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a,
3418                   (_hcd->hfnum_other_samples_a > 0) ?
3419                   _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0);
3420
3421         DWC_PRINT("\n");
3422         DWC_PRINT("Frame remaining at sample point B (uframe 7):\n");
3423         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3424                   _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b,
3425                   (_hcd->hfnum_7_samples_b > 0) ?
3426                   _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0);
3427         DWC_PRINT("Frame remaining at sample point B (uframe 0):\n");
3428         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3429                   _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b,
3430                   (_hcd->hfnum_0_samples_b > 0) ?
3431                   _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0);
3432         DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n");
3433         DWC_PRINT("  samples %u, accum %llu, avg %llu\n",
3434                   _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b,
3435                   (_hcd->hfnum_other_samples_b > 0) ?
3436                   _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0);
3437 #endif
3438 }
3439
3440 void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd)
3441 {
3442 #ifdef DEBUG
3443         int num_channels;
3444         int i;
3445         gnptxsts_data_t np_tx_status;
3446         hptxsts_data_t p_tx_status;
3447
3448         num_channels = _hcd->core_if->core_params->host_channels;
3449         DWC_PRINT("\n");
3450         DWC_PRINT("************************************************************\n");
3451         DWC_PRINT("HCD State:\n");
3452         DWC_PRINT("  Num channels: %d\n", num_channels);
3453         for (i = 0; i < num_channels; i++) {
3454                 dwc_hc_t *hc = _hcd->hc_ptr_array[i];
3455                 DWC_PRINT("  Channel %d:\n", i);
3456                 DWC_PRINT("    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
3457                           hc->dev_addr, hc->ep_num, hc->ep_is_in);
3458                 DWC_PRINT("    speed: %d\n", hc->speed);
3459                 DWC_PRINT("    ep_type: %d\n", hc->ep_type);
3460                 DWC_PRINT("    max_packet: %d\n", hc->max_packet);
3461                 DWC_PRINT("    data_pid_start: %d\n", hc->data_pid_start);
3462                 DWC_PRINT("    multi_count: %d\n", hc->multi_count);
3463                 DWC_PRINT("    xfer_started: %d\n", hc->xfer_started);
3464                 DWC_PRINT("    xfer_buff: %p\n", hc->xfer_buff);
3465                 DWC_PRINT("    xfer_len: %d\n", hc->xfer_len);
3466                 DWC_PRINT("    xfer_count: %d\n", hc->xfer_count);
3467                 DWC_PRINT("    halt_on_queue: %d\n", hc->halt_on_queue);
3468                 DWC_PRINT("    halt_pending: %d\n", hc->halt_pending);
3469                 DWC_PRINT("    halt_status: %d\n", hc->halt_status);
3470                 DWC_PRINT("    do_split: %d\n", hc->do_split);
3471                 DWC_PRINT("    complete_split: %d\n", hc->complete_split);
3472                 DWC_PRINT("    hub_addr: %d\n", hc->hub_addr);
3473                 DWC_PRINT("    port_addr: %d\n", hc->port_addr);
3474                 DWC_PRINT("    xact_pos: %d\n", hc->xact_pos);
3475                 DWC_PRINT("    requests: %d\n", hc->requests);
3476                 DWC_PRINT("    qh: %p\n", hc->qh);
3477                 if (hc->xfer_started) {
3478                         hfnum_data_t hfnum;
3479                         hcchar_data_t hcchar;
3480                         hctsiz_data_t hctsiz;
3481                         hcint_data_t hcint;
3482                         hcintmsk_data_t hcintmsk;
3483                         hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum);
3484                         hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar);
3485                         hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz);
3486                         hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint);
3487                         hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk);
3488                         DWC_PRINT("    hfnum: 0x%08x\n", hfnum.d32);
3489                         DWC_PRINT("    hcchar: 0x%08x\n", hcchar.d32);
3490                         DWC_PRINT("    hctsiz: 0x%08x\n", hctsiz.d32);
3491                         DWC_PRINT("    hcint: 0x%08x\n", hcint.d32);
3492                         DWC_PRINT("    hcintmsk: 0x%08x\n", hcintmsk.d32);
3493                 }
3494                 if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) {
3495                         dwc_otg_qtd_t *qtd;
3496                         struct urb *urb;
3497                         qtd = hc->qh->qtd_in_process;
3498                         urb = qtd->urb;
3499                         DWC_PRINT("    URB Info:\n");
3500                         DWC_PRINT("      qtd: %p, urb: %p\n", qtd, urb);
3501                         if (urb != NULL) {
3502                                 DWC_PRINT("      Dev: %d, EP: %d %s\n",
3503                                           usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe),
3504                                           usb_pipein(urb->pipe) ? "IN" : "OUT");
3505                                 DWC_PRINT("      Max packet size: %d\n",
3506                                           usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
3507                                 DWC_PRINT("      transfer_buffer: %p\n", urb->transfer_buffer);
3508                                 DWC_PRINT("      transfer_dma: %p\n", (void *)urb->transfer_dma);
3509                                 DWC_PRINT("      transfer_buffer_length: %d\n", urb->transfer_buffer_length);
3510                                 DWC_PRINT("      actual_length: %d\n", urb->actual_length);
3511                         }
3512                 }
3513         }
3514         DWC_PRINT("  non_periodic_channels: %d\n", _hcd->non_periodic_channels);
3515         DWC_PRINT("  periodic_channels: %d\n", _hcd->periodic_channels);
3516         DWC_PRINT("  periodic_usecs: %d\n", _hcd->periodic_usecs);
3517         np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts);
3518         DWC_PRINT("  NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail);
3519         DWC_PRINT("  NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail);
3520         p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts);
3521         DWC_PRINT("  P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail);
3522         DWC_PRINT("  P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail);
3523         dwc_otg_hcd_dump_frrem(_hcd);
3524         dwc_otg_dump_global_registers(_hcd->core_if);
3525         dwc_otg_dump_host_registers(_hcd->core_if);
3526         DWC_PRINT("************************************************************\n");
3527         DWC_PRINT("\n");
3528 #endif
3529 }
3530 #endif /* DWC_DEVICE_ONLY */