drivers/usb/dwc_otg/dwc_otg_driver.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
   3  * $Revision: #12 $
   4  * $Date: 2007/02/07 $
   5  * $Change: 791271 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  * The dwc_otg_driver module provides the initialization and cleanup entry
  36  * points for the DWC_otg driver. This module will be dynamically installed
  37  * after Linux is booted using the insmod command. When the module is
  38  * installed, the dwc_otg_driver_init function is called. When the module is
  39  * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
  40  *
  41  * This module also defines a data structure for the dwc_otg_driver, which is
  42  * used in conjunction with the standard ARM lm_device structure. These
  43  * structures allow the OTG driver to comply with the standard Linux driver
  44  * model in which devices and drivers are registered with a bus driver. This
  45  * has the benefit that Linux can expose attributes of the driver and device
  46  * in its special sysfs file system. Users can then read or write files in
  47  * this file system to perform diagnostics on the driver components or the
  48  * device.
  49  */
  50
  51 #include <linux/clk.h>
  52 #include <linux/kernel.h>
  53 #include <linux/module.h>
  54 #include <linux/moduleparam.h>
  55 #include <linux/init.h>
  56 #include <linux/device.h>
  57 #include <linux/errno.h>
  58 #include <linux/types.h>
  59 #include <linux/stat.h>  /* permission constants */
  60
  61 #include <asm/io.h>
  62 #include <asm/sizes.h>
  63
  64 #ifdef CONFIG_MACH_RK30_DS1001B
  65 #include <mach/io.h>
  66 #include <mach/gpio.h>
  67 #include <mach/iomux.h>
  68 #endif
  69
  70 #include "linux/dwc_otg_plat.h"
  71 #include <linux/platform_device.h>
  72 #include "dwc_otg_attr.h"
  73 #include "dwc_otg_driver.h"
  74 #include "dwc_otg_cil.h"
  75 #include "dwc_otg_pcd.h"
  76 #include "dwc_otg_hcd.h"
  77 //#include <mach/cru.h>
  78 //#define DWC_DRIVER_VERSION    "2.60a 22-NOV-2006"
  79 //#define DWC_DRIVER_VERSION    "2.70 2009-12-31"
  80 #define DWC_DRIVER_VERSION      "3.00 2010-12-12 rockchip"
  81
  82 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
  83
  84 static const char dwc_driver_name[] = "usb20_otg";
  85
  86 dwc_otg_device_t* g_otgdev = NULL;
  87
  88 /*-------------------------------------------------------------------------*/
  89 /* Encapsulate the module parameter settings */
  90
  91 static dwc_otg_core_params_t dwc_otg_module_params = {
  92         .opt = -1,
  93         .otg_cap = -1,
  94         .dma_enable = -1,
  95         .dma_burst_size = -1,
  96         .speed = -1,
  97         .host_support_fs_ls_low_power = -1,
  98         .host_ls_low_power_phy_clk = -1,
  99         .enable_dynamic_fifo = -1,
 100         .data_fifo_size = -1,
 101         .dev_rx_fifo_size = -1,
 102         .dev_nperio_tx_fifo_size = -1,
 103         .dev_perio_tx_fifo_size =
 104         {       /* dev_perio_tx_fifo_size_1 */
 105                         -1,
 106                         -1,
 107                         -1,
 108                         -1,
 109                         -1,
 110                         -1,
 111                         -1,
 112                         -1,
 113                         -1,
 114                         -1,
 115                         -1,
 116                         -1,
 117                         -1,
 118                         -1,
 119                         -1
 120         },      /* 15 */
 121         .host_rx_fifo_size = -1,
 122         .host_nperio_tx_fifo_size = -1,
 123         //.host_perio_tx_fifo_size = 512,
 124         .host_perio_tx_fifo_size = -1,
 125         .max_transfer_size = -1,
 126         .max_packet_count = -1,
 127         .host_channels = -1,
 128         .dev_endpoints = -1,
 129         .phy_type = -1,
 130         .phy_utmi_width = -1,
 131         .phy_ulpi_ddr = -1,
 132         .phy_ulpi_ext_vbus = -1,
 133         .i2c_enable = -1,
 134         .ulpi_fs_ls = -1,
 135         .ts_dline = -1,
 136         .en_multiple_tx_fifo = -1,
 137         .dev_tx_fifo_size =
 138         {       /* dev_tx_fifo_size */
 139                         -1,
 140                         -1,
 141                         -1,
 142                         -1,
 143                         -1,
 144                         -1,
 145                         -1,
 146                         -1,
 147                         -1,
 148                         -1,
 149                         -1,
 150                         -1,
 151                         -1,
 152                         -1,
 153                         -1
 154         },      /* 15 */
 155         .thr_ctl = -1,
 156         .tx_thr_length = -1,
 157         .rx_thr_length = -1,
 158 };
 159
 160 #ifdef CONFIG_USB11_HOST
 161
 162 dwc_otg_device_t* g_host11 = NULL;
 163
 164 static dwc_otg_core_params_t host11_module_params = {
 165         .opt = -1,
 166         .otg_cap = -1,
 167         .dma_enable = -1,
 168         .dma_burst_size = -1,
 169         .speed = -1,
 170         .host_support_fs_ls_low_power = 1,
 171         .host_ls_low_power_phy_clk = -1,
 172         .enable_dynamic_fifo = -1,
 173         .data_fifo_size = -1,
 174         .dev_rx_fifo_size = -1,
 175         .dev_nperio_tx_fifo_size = -1,
 176         .dev_perio_tx_fifo_size =
 177         {       /* dev_perio_tx_fifo_size_1 */
 178                         -1,
 179                         -1,
 180                         -1,
 181                         -1,
 182                         -1,
 183                         -1,
 184                         -1,
 185                         -1,
 186                         -1,
 187                         -1,
 188                         -1,
 189                         -1,
 190                         -1,
 191                         -1,
 192                         -1
 193         },      /* 15 */
 194         .host_rx_fifo_size = -1,
 195         .host_nperio_tx_fifo_size = -1,
 196         //.host_perio_tx_fifo_size = 512,
 197         .host_perio_tx_fifo_size = -1,
 198         .max_transfer_size = -1,
 199         .max_packet_count = -1,
 200         .host_channels = -1,
 201         .dev_endpoints = -1,
 202         .phy_type = -1,
 203         .phy_utmi_width = -1,
 204         .phy_ulpi_ddr = -1,
 205         .phy_ulpi_ext_vbus = -1,
 206         .i2c_enable = -1,
 207         .ulpi_fs_ls = -1,
 208         .ts_dline = -1,
 209         .en_multiple_tx_fifo = -1,
 210         .dev_tx_fifo_size =
 211         {       /* dev_tx_fifo_size */
 212                         -1,
 213                         -1,
 214                         -1,
 215                         -1,
 216                         -1,
 217                         -1,
 218                         -1,
 219                         -1,
 220                         -1,
 221                         -1,
 222                         -1,
 223                         -1,
 224                         -1,
 225                         -1,
 226                         -1
 227         },      /* 15 */
 228         .thr_ctl = -1,
 229         .tx_thr_length = -1,
 230         .rx_thr_length = -1,
 231 };
 232 #endif
 233
 234 #ifdef CONFIG_USB20_HOST
 235 dwc_otg_device_t* g_host20 = NULL;
 236
 237 static dwc_otg_core_params_t host20_module_params = {
 238         .opt = -1,
 239         .otg_cap = -1,
 240         .dma_enable = -1,
 241         .dma_burst_size = -1,
 242         .speed = -1,
 243         .host_support_fs_ls_low_power = -1,
 244         .host_ls_low_power_phy_clk = -1,
 245         .enable_dynamic_fifo = -1,
 246         .data_fifo_size = -1,
 247         .dev_rx_fifo_size = -1,
 248         .dev_nperio_tx_fifo_size = -1,
 249         .dev_perio_tx_fifo_size =
 250         {       /* dev_perio_tx_fifo_size_1 */
 251                         -1,
 252                         -1,
 253                         -1,
 254                         -1,
 255                         -1,
 256                         -1,
 257                         -1,
 258                         -1,
 259                         -1,
 260                         -1,
 261                         -1,
 262                         -1,
 263                         -1,
 264                         -1,
 265                         -1
 266         },      /* 15 */
 267         .host_rx_fifo_size = -1,
 268         .host_nperio_tx_fifo_size = -1,
 269         //.host_perio_tx_fifo_size = 512,
 270         .host_perio_tx_fifo_size = -1,
 271         .max_transfer_size = -1,
 272         .max_packet_count = -1,
 273         .host_channels = -1,
 274         .dev_endpoints = -1,
 275         .phy_type = -1,
 276         .phy_utmi_width = -1,
 277         .phy_ulpi_ddr = -1,
 278         .phy_ulpi_ext_vbus = -1,
 279         .i2c_enable = -1,
 280         .ulpi_fs_ls = -1,
 281         .ts_dline = -1,
 282         .en_multiple_tx_fifo = -1,
 283         .dev_tx_fifo_size =
 284         {       /* dev_tx_fifo_size */
 285                         -1,
 286                         -1,
 287                         -1,
 288                         -1,
 289                         -1,
 290                         -1,
 291                         -1,
 292                         -1,
 293                         -1,
 294                         -1,
 295                         -1,
 296                         -1,
 297                         -1,
 298                         -1,
 299                         -1
 300         },      /* 15 */
 301         .thr_ctl = -1,
 302         .tx_thr_length = -1,
 303         .rx_thr_length = -1,
 304 };
 305 #endif
 306
 307 /**
 308  * This function shows the Driver Version.
 309  */
 310 static ssize_t version_show(struct device_driver *dev, char *buf)
 311 {
 312         return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
 313                 DWC_DRIVER_VERSION);
 314 }
 315 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
 316
 317 /**
 318  * Global Debug Level Mask.
 319  */
 320 uint32_t g_dbg_lvl = DBG_OFF;//0xFFFF;//DBG_CIL|DBG_CILV|DBG_PCDV|DBG_HCDV|DBG_HCD|DBG_HCD_URB; /* OFF */
 321
 322 /**
 323  * This function shows the driver Debug Level.
 324  */
 325 static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
 326 {
 327         return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
 328 }
 329 /**
 330  * This function stores the driver Debug Level.
 331  */
 332 static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
 333                                                            size_t _count)
 334 {
 335         g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
 336                 return _count;
 337 }
 338 static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
 339 #ifdef CONFIG_USB
 340
 341 extern struct usb_hub *g_root_hub20;
 342 #ifdef DWC_BOTH_HOST_SLAVE
 343 extern void hcd_start( dwc_otg_core_if_t *_core_if );
 344
 345 extern int dwc_otg20phy_suspend( int exitsuspend );
 346 extern void hub_disconnect_device(struct usb_hub *hub);
 347
 348 static ssize_t force_usb_mode_show(struct device_driver *_drv, char *_buf)
 349 {
 350     dwc_otg_device_t *otg_dev = g_otgdev;
 351     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 352 #if 1
 353     return sprintf (_buf, "%d\n", core_if->usb_mode);
 354 #else
 355     dwc_otg_device_t *otg_dev = lm_get_drvdata(g_lmdev);
 356     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 357     gotgctl_data_t    gctrl;
 358     gctrl.d32 = dwc_read_reg32( &core_if->core_global_regs->gotgctl );
 359     printk("OTGCTL=0x%08X\n", gctrl.d32);
 360
 361     if(g_usb_mode == USB_NORMAL_MODE)
 362         return sprintf (_buf, "Current usb mode: Normal Mode\n");
 363     else if(g_usb_mode == FORCE_HOST_MODE)
 364         return sprintf (_buf, "Current usb mode: Force Host\n");
 365     else if(g_usb_mode == FORCE_DEVICE_MODE)
 366         return sprintf (_buf, "Current usb mode: Force Device\n");
 367     else
 368         return sprintf (_buf, "Current usb mode: Unknown\n");
 369 #endif
 370 }
 371
 372 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
 373 {
 374     dwc_otg_device_t *otg_dev = g_otgdev;
 375     dctl_data_t dctl = {.d32=0};
 376     if(core_if->op_state == A_HOST)
 377     {
 378         printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
 379         return;
 380     }
 381         if((otg_dev->pcd)&&(otg_dev->pcd->phy_suspend == 1))
 382         {
 383                 dwc_otg20phy_suspend( 1 );
 384         }
 385     del_timer(&otg_dev->pcd->check_vbus_timer);
 386     // force disconnect
 387     /* soft disconnect */
 388     dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
 389     dctl.b.sftdiscon = 1;
 390     dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
 391
 392     if (core_if->pcd_cb && core_if->pcd_cb->stop ) {
 393             core_if->pcd_cb->stop( core_if->pcd_cb->p );
 394     }
 395
 396     //core_if->op_state = A_HOST;
 397     /*
 398      * Initialize the Core for Host mode.
 399      */
 400         dwc_otg_core_init(core_if);
 401         dwc_otg_enable_global_interrupts(core_if);
 402     hcd_start( core_if );
 403
 404 }
 405 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
 406 {
 407     dwc_otg_device_t *otg_dev = g_otgdev;
 408     dwc_otg_disable_global_interrupts( core_if );
 409     if (core_if->hcd_cb && core_if->hcd_cb->stop) {
 410         core_if->hcd_cb->stop( core_if->hcd_cb->p );
 411     }
 412     if(core_if->op_state == B_PERIPHERAL)
 413     {
 414         printk("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
 415         return;
 416     }
 417         hub_disconnect_device(g_root_hub20);
 418     otg_dev->core_if->op_state = B_PERIPHERAL;
 419         /* Reset the Controller */
 420         dwc_otg_core_reset( core_if );
 421     //otg_dev->pcd->phy_suspend = 1;
 422     otg_dev->pcd->vbus_status = 0;
 423     dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 424
 425 }
 426 static void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, int mode)
 427 {
 428         gusbcfg_data_t usbcfg = { .d32 = 0 };
 429
 430     usbcfg.d32 = dwc_read_reg32( &core_if->core_global_regs->gusbcfg);
 431     switch(mode)
 432     {
 433     case USB_MODE_FORCE_HOST:
 434         usbcfg.b.force_hst_mode = 1;
 435         usbcfg.b.force_dev_mode = 0;
 436         break;
 437     case USB_MODE_FORCE_DEVICE:
 438         usbcfg.b.force_hst_mode = 0;
 439         usbcfg.b.force_dev_mode = 1;
 440         break;
 441     case USB_MODE_NORMAL:
 442         usbcfg.b.force_hst_mode = 0;
 443         usbcfg.b.force_dev_mode = 0;
 444         break;
 445     }
 446     dwc_write_reg32( &core_if->core_global_regs->gusbcfg, usbcfg.d32 );
 447 }
 448
 449 static ssize_t force_usb_mode_store(struct device_driver *_drv, const char *_buf,
 450                           size_t _count )
 451 {
 452     int new_mode = simple_strtoul(_buf, NULL, 16);
 453     dwc_otg_device_t *otg_dev = g_otgdev;
 454     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 455     DWC_PRINT("%s %d->%d\n",__func__, core_if->usb_mode, new_mode);
 456     if(core_if->usb_mode == new_mode)
 457     {
 458         return _count;
 459     }
 460
 461         switch(new_mode)
 462         {
 463                 case USB_MODE_FORCE_HOST:
 464                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 465                         {/* device-->host */
 466                                 core_if->usb_mode = new_mode;
 467                                 dwc_otg_force_host(core_if);
 468                         }
 469                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 470                         {
 471                                 core_if->usb_mode = new_mode;
 472                                 if(dwc_otg_is_host_mode(core_if))
 473                                 {
 474                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 475                                 }
 476                                 else
 477                                 {
 478                                         dwc_otg_force_host(core_if);
 479                                 }
 480                         }
 481                         else
 482                             core_if->usb_mode = new_mode;
 483                         break;
 484                 case USB_MODE_FORCE_DEVICE:
 485                         if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 486                         {
 487                                 core_if->usb_mode = new_mode;
 488                                 dwc_otg_force_device(core_if);
 489                         }
 490                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 491                         {
 492                                 core_if->usb_mode = new_mode;
 493                                 if(dwc_otg_is_device_mode(core_if))
 494                                 {
 495                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 496                                 }
 497                                 else
 498                                 {
 499                                         dwc_otg_force_device(core_if);
 500                                 }
 501                         }
 502                         break;
 503                 case USB_MODE_NORMAL:
 504                         #if 1
 505                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 506                         {
 507                                 core_if->usb_mode = new_mode;
 508                                 if((otg_dev->pcd)&&(otg_dev->pcd->phy_suspend == 1))
 509                                 {
 510                                         dwc_otg20phy_suspend( 1 );
 511                                 }
 512                                 del_timer(&otg_dev->pcd->check_vbus_timer);
 513                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 514                                 msleep(50);
 515                                 if(dwc_otg_is_host_mode(core_if))
 516                                 {
 517                                         dwc_otg_force_host(core_if);
 518                                 }
 519                                 else
 520                                 {
 521                                         dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 522                                 }
 523                                 //mdelay(10);
 524                                 //core_if->usb_mode = new_mode;
 525                                 //if(!dwc_otg_connid(core_if))
 526                                 //      dwc_otg_force_host(core_if);
 527                         }
 528                         else if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 529                         {
 530                                 if((otg_dev->pcd)&&(otg_dev->pcd->phy_suspend == 1))
 531                                 {
 532                                         dwc_otg20phy_suspend( 1 );
 533                                 }
 534                                 core_if->usb_mode = new_mode;
 535                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 536                                 msleep(100);
 537                                 if(dwc_otg_is_device_mode(core_if))
 538                                 {
 539                                         dwc_otg_force_device(core_if);
 540                                 }
 541                                 //if(dwc_otg_connid(core_if))
 542                                 //      hub_disconnect_device();
 543                                 //core_if->usb_mode = new_mode;
 544                                 //      dwc_otg_force_device(core_if);
 545                         }
 546                         #endif
 547                         break;
 548                 default:
 549                         break;
 550         }
 551         return _count;
 552 }
 553 static DRIVER_ATTR(force_usb_mode, 0666/*S_IRUGO|S_IWUSR*/, force_usb_mode_show, force_usb_mode_store);
 554 #endif
 555 static ssize_t dwc_otg_enable_show( struct device *_dev,
 556                                                                 struct device_attribute *attr, char *buf)
 557 {
 558     dwc_otg_device_t *otg_dev = _dev->platform_data;
 559     return sprintf (buf, "%d\n", otg_dev->hcd->host_enabled);
 560 }
 561
 562 static ssize_t dwc_otg_enable_store( struct device *_dev,
 563                                                                 struct device_attribute *attr,
 564                                                                 const char *buf, size_t count )
 565 {
 566     dwc_otg_device_t *otg_dev = _dev->platform_data;
 567     dwc_otg_core_if_t *_core_if = otg_dev->core_if;
 568     struct platform_device *pdev = to_platform_device(_dev);
 569         uint32_t val = simple_strtoul(buf, NULL, 16);
 570         if(otg_dev->hcd->host_enabled == val)
 571             return count;
 572
 573         otg_dev->hcd->host_enabled = val;
 574         if(val == 0)    // enable -> disable
 575         {
 576             DWC_PRINT("disable host controller:%s,id:%d\n",pdev->name,pdev->id);
 577             #if 1
 578         if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
 579                 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
 580         }
 581         #endif
 582         if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
 583                 _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
 584         }
 585         if (_core_if->hcd_cb && _core_if->hcd_cb->suspend) {
 586                 _core_if->hcd_cb->suspend( _core_if->hcd_cb->p, val);
 587         }
 588         udelay(3);
 589         clk_disable(otg_dev->phyclk);
 590         clk_disable(otg_dev->ahbclk);
 591         }
 592         else if(val == 1)
 593         {
 594             DWC_PRINT("enable host controller:%s\n",pdev->name);
 595         clk_enable(otg_dev->phyclk);
 596         clk_enable(otg_dev->ahbclk);
 597         if (_core_if->hcd_cb && _core_if->hcd_cb->suspend) {
 598                 _core_if->hcd_cb->suspend( _core_if->hcd_cb->p, val);
 599         }
 600         mdelay(5);
 601         if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
 602                 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
 603         }
 604         }
 605
 606     return count;
 607 }
 608 static DEVICE_ATTR(enable, S_IRUGO|S_IWUSR, dwc_otg_enable_show, dwc_otg_enable_store);
 609 #endif
 610 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
 611 {
 612 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 613     dwc_otg_device_t *otg_dev = g_otgdev;
 614     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 615     return sprintf (_buf, "%d\n", _pcd->conn_en);
 616 #else
 617     return sprintf(_buf, "0\n");
 618 #endif
 619 }
 620
 621 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
 622                                      size_t _count)
 623 {
 624 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 625     int enable = simple_strtoul(_buf, NULL, 10);
 626     dwc_otg_device_t *otg_dev = g_otgdev;
 627     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 628     DWC_PRINT("%s %d->%d\n",__func__, _pcd->conn_en, enable);
 629
 630     _pcd->conn_en = enable;
 631 #endif
 632     return _count;
 633 }
 634 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
 635 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 636 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
 637 {
 638     dwc_otg_device_t *otg_dev = g_otgdev;
 639     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 640     return sprintf (_buf, "%d\n", _pcd->vbus_status);
 641 }
 642 static DRIVER_ATTR(vbus_status, S_IRUGO|S_IWUSR, vbus_status_show, NULL);
 643 #endif
 644 volatile depctl_data_t depctl_ep0 = {.d32 = 0};
 645 volatile depctl_data_t depctl_ep2 = {.d32 = 0};
 646 volatile depctl_data_t depctl_ep4 = {.d32 = 0};
 647 void dwc_otg_epout_save(void)
 648 {
 649     dwc_otg_device_t *otg_dev = g_otgdev;
 650         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 651     volatile depctl_data_t depctl = {.d32 = 0};
 652     volatile grstctl_t grstctl = {.d32 = 0};
 653     grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 654
 655     while(grstctl.b.ahbidle != 1)
 656     {
 657         grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 658     }
 659     depctl_ep0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
 660     depctl.d32 = depctl_ep0.d32;
 661     if(depctl.b.epena)
 662     {
 663         depctl.b.epena = 0;
 664         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl.d32);
 665     }
 666     depctl_ep2.d32 = dwc_read_reg32(&dev_if->out_ep_regs[2]->doepctl);
 667     depctl.d32 = depctl_ep2.d32;
 668     if(depctl.b.epena)
 669     {
 670         depctl.b.epena = 0;
 671         dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl.d32);
 672     }
 673     depctl_ep4.d32 = dwc_read_reg32(&dev_if->out_ep_regs[4]->doepctl);
 674     depctl.d32 = depctl_ep4.d32;
 675     if(depctl.b.epena)
 676     {
 677         depctl.b.epena = 0;
 678         dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl.d32);
 679     }
 680 }
 681 void dwc_otg_epout_restore(void)
 682 {
 683     dwc_otg_device_t *otg_dev = g_otgdev;
 684         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 685     dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl_ep0.d32);
 686     dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl_ep2.d32);
 687     dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl_ep4.d32);
 688 }
 689
 690 /**
 691  * This function is called during module intialization to verify that
 692  * the module parameters are in a valid state.
 693  */
 694 static int check_parameters(dwc_otg_core_if_t *core_if)
 695 {
 696         int i;
 697         int retval = 0;
 698         dwc_otg_core_params_t      *core_params;
 699         core_params = core_if->core_params;
 700 /* Checks if the parameter is outside of its valid range of values */
 701 #define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
 702                 ((core_params->_param_ < (_low_)) || \
 703                 (core_params->_param_ > (_high_)))
 704
 705 /* If the parameter has been set by the user, check that the parameter value is
 706  * within the value range of values.  If not, report a module error. */
 707 #define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
 708                 do { \
 709                         if (core_params->_param_ != -1) { \
 710                                 if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
 711                                         DWC_ERROR("`%d' invalid for parameter `%s'\n", \
 712                                                 core_params->_param_, _string_); \
 713                                         core_params->_param_ = dwc_param_##_param_##_default; \
 714                                         retval ++; \
 715                                 } \
 716                         } \
 717                 } while (0)
 718
 719         DWC_OTG_PARAM_ERR(opt,0,1,"opt");
 720         DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
 721         DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
 722         DWC_OTG_PARAM_ERR(speed,0,1,"speed");
 723         DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
 724         DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
 725         DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
 726         DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
 727         DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
 728         DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
 729         DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
 730         DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
 731         DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
 732         DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
 733         DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
 734         DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
 735         DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
 736         DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
 737         DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
 738         DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
 739         DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
 740         DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
 741         DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
 742
 743         if (core_params->dma_burst_size != -1)
 744         {
 745                 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
 746                         DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
 747                         DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
 748                         DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
 749                         DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
 750                         DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
 751                         DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
 752                         DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
 753                 {
 754                         DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
 755                                   core_params->dma_burst_size);
 756                         core_params->dma_burst_size = 32;
 757                         retval ++;
 758                 }
 759         }
 760
 761         if (core_params->phy_utmi_width != -1)
 762         {
 763                 if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
 764                         DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
 765                 {
 766                         DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
 767                                   core_params->phy_utmi_width);
 768                         core_params->phy_utmi_width = 16;
 769                         retval ++;
 770                 }
 771         }
 772
 773         for (i=0; i<15; i++)
 774         {
 775                 /** @todo should be like above */
 776                 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
 777                 if (core_params->dev_perio_tx_fifo_size[i] != -1)
 778                 {
 779                         if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768))
 780                         {
 781                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 782                                           core_params->dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
 783                                 core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 784                                 retval ++;
 785                         }
 786                 }
 787         }
 788
 789         DWC_OTG_PARAM_ERR(en_multiple_tx_fifo,0,1,"en_multiple_tx_fifo");
 790
 791         for (i=0; i<15; i++)
 792         {
 793                 /** @todo should be like above */
 794                 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
 795                 if (core_params->dev_tx_fifo_size[i] != -1)
 796                 {
 797                         if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i],4,768))
 798                         {
 799                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 800                                           core_params->dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
 801                                 core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 802                                 retval ++;
 803                         }
 804                 }
 805         }
 806
 807         DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
 808         DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
 809         DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
 810
 811
 812         /* At this point, all module parameters that have been set by the user
 813          * are valid, and those that have not are left unset.  Now set their
 814          * default values and/or check the parameters against the hardware
 815          * configurations of the OTG core. */
 816
 817
 818
 819 /* This sets the parameter to the default value if it has not been set by the
 820  * user */
 821 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
 822         ({ \
 823                 int changed = 1; \
 824                 if (core_params->_param_ == -1) { \
 825                         changed = 0; \
 826                         core_params->_param_ = dwc_param_##_param_##_default; \
 827                 } \
 828                 changed; \
 829         })
 830
 831 /* This checks the macro agains the hardware configuration to see if it is
 832  * valid.  It is possible that the default value could be invalid.      In this
 833  * case, it will report a module error if the user touched the parameter.
 834  * Otherwise it will adjust the value without any error. */
 835 #define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
 836         ({ \
 837                         int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
 838                 int error = 0; \
 839                 if (!(_is_valid_)) { \
 840                         if (changed) { \
 841                                 DWC_ERROR("`%d' invalid for parameter `%s'.      Check HW configuration.\n", core_params->_param_,_str_); \
 842                                 error = 1; \
 843                         } \
 844                         core_params->_param_ = (_set_valid_); \
 845                 } \
 846                 error; \
 847         })
 848
 849         /* OTG Cap */
 850         retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
 851                                   ({
 852                                           int valid;
 853                                           valid = 1;
 854                                           switch (core_params->otg_cap) {
 855                                           case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
 856                                                   if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
 857                                                   break;
 858                                           case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
 859                                                   if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
 860                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
 861                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
 862                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
 863                                                   {
 864                                                           valid = 0;
 865                                                   }
 866                                                   break;
 867                                           case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 868                                                   /* always valid */
 869                                                   break;
 870                                           }
 871                                           valid;
 872                           }),
 873                                         (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
 874                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
 875                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 876                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
 877                                         DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
 878                                         DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
 879
 880         retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
 881                                 ((core_params->dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
 882                                 0);
 883
 884         retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
 885                                 1,
 886                                 0);
 887
 888         DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
 889
 890         retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
 891                                 "host_support_fs_ls_low_power",
 892                                 1, 0);
 893
 894         retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
 895                                         "enable_dynamic_fifo",
 896                                         ((core_params->enable_dynamic_fifo == 0) ||
 897                                         (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
 898
 899
 900         retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
 901                                         "data_fifo_size",
 902                                         (core_params->data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
 903                                         core_if->hwcfg3.b.dfifo_depth);
 904
 905         retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
 906                                         "dev_rx_fifo_size",
 907                                         (core_params->dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 908                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 909
 910         retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
 911                                         "dev_nperio_tx_fifo_size",
 912                                         (core_params->dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 913                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 914
 915         retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
 916                                         "host_rx_fifo_size",
 917                                         (core_params->host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 918                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 919
 920
 921         retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
 922                                         "host_nperio_tx_fifo_size",
 923                                         (core_params->host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 924                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 925         retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
 926                                         "host_perio_tx_fifo_size",
 927                                         (core_params->host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
 928                                         ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
 929
 930         retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
 931                                         "max_transfer_size",
 932                                         (core_params->max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
 933                                         ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
 934
 935         retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
 936                                         "max_packet_count",
 937                                         (core_params->max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
 938                                         ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
 939
 940         retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
 941                                         "host_channels",
 942                                         (core_params->host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
 943                                         (core_if->hwcfg2.b.num_host_chan + 1));
 944
 945         retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
 946                                         "dev_endpoints",
 947                                         (core_params->dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
 948                                         core_if->hwcfg2.b.num_dev_ep);
 949
 950 /*
 951  * Define the following to disable the FS PHY Hardware checking.  This is for
 952  * internal testing only.
 953  *
 954  * #define NO_FS_PHY_HW_CHECKS
 955  */
 956
 957 #ifdef NO_FS_PHY_HW_CHECKS
 958         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 959                                 "phy_type", 1, 0);
 960 #else
 961         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 962                                 "phy_type",
 963                                 ({
 964                                         int valid = 0;
 965                                         if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
 966                                         ((core_if->hwcfg2.b.hs_phy_type == 1) ||
 967                                          (core_if->hwcfg2.b.hs_phy_type == 3)))
 968                                         {
 969                                                 valid = 1;
 970                                         }
 971                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
 972                                                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
 973                                                   (core_if->hwcfg2.b.hs_phy_type == 3)))
 974                                         {
 975                                                 valid = 1;
 976                                         }
 977                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
 978                                                  (core_if->hwcfg2.b.fs_phy_type == 1))
 979                                         {
 980                                                 valid = 1;
 981                                         }
 982                                         valid;
 983                                 }),
 984                                 ({
 985                                         int set = DWC_PHY_TYPE_PARAM_FS;
 986                                         if (core_if->hwcfg2.b.hs_phy_type) {
 987                                                 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
 988                                                 (core_if->hwcfg2.b.hs_phy_type == 1)) {
 989                                                         set = DWC_PHY_TYPE_PARAM_UTMI;
 990                                                 }
 991                                                 else {
 992                                                         set = DWC_PHY_TYPE_PARAM_ULPI;
 993                                                 }
 994                                         }
 995                                         set;
 996                                 }));
 997 #endif
 998
 999         retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
1000                                 (core_params->speed == 0) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
1001                                 core_params->phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
1002
1003         retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
1004                                 "host_ls_low_power_phy_clk",
1005                                 ((core_params->host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
1006                                 ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
1007
1008         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
1009         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
1010         DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
1011         DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
1012         DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
1013
1014 #ifdef NO_FS_PHY_HW_CHECKS
1015         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1016                                 "i2c_enable", 1, 0);
1017 #else
1018         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1019                                 "i2c_enable",
1020                                 (core_params->i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
1021                                 0);
1022 #endif
1023
1024         for (i=0; i<15; i++)
1025         {
1026                 int changed = 1;
1027                 int error = 0;
1028
1029                 if (core_params->dev_perio_tx_fifo_size[i] == -1)
1030                 {
1031                         changed = 0;
1032                         core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
1033                 }
1034                 if (!(core_params->dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1035                 {
1036                         if (changed)
1037                         {
1038                                 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_perio_tx_fifo_size[i],i);
1039                                 error = 1;
1040                         }
1041                         core_params->dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1042                 }
1043                 retval += error;
1044         }
1045
1046
1047         retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,"en_multiple_tx_fifo",
1048                                                 ((core_params->en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
1049                                                 0);
1050
1051
1052         for (i=0; i<15; i++)
1053         {
1054
1055                 int changed = 1;
1056                 int error = 0;
1057
1058                 if (core_params->dev_tx_fifo_size[i] == -1)
1059                 {
1060                         changed = 0;
1061                         core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
1062                 }
1063                 if (!(core_params->dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1064                 {
1065                         if (changed)
1066                         {
1067                                 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_tx_fifo_size[i],i);
1068                                 error = 1;
1069                         }
1070                         core_params->dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1071                 }
1072                 retval += error;
1073
1074
1075         }
1076
1077         DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
1078         DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
1079         DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
1080
1081         return retval;
1082 }
1083 /**
1084  * This function is the top level interrupt handler for the Common
1085  * (Device and host modes) interrupts.
1086  */
1087 static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
1088 {
1089         dwc_otg_device_t *otg_dev = _dev;
1090         int32_t retval = IRQ_NONE;
1091
1092         retval = dwc_otg_handle_common_intr( otg_dev->core_if );
1093         return IRQ_RETVAL(retval);
1094 }
1095
1096 /**
1097  * This function is called when a lm_device is unregistered with the
1098  * dwc_otg_driver. This happens, for example, when the rmmod command is
1099  * executed. The device may or may not be electrically present. If it is
1100  * present, the driver stops device processing. Any resources used on behalf
1101  * of this device are freed.
1102  *
1103  * @param[in] pdev
1104  */
1105 static int dwc_otg_driver_remove(struct platform_device *pdev)
1106 {
1107         struct device *dev = &pdev->dev;
1108         dwc_otg_device_t *otg_dev = dev->platform_data;
1109         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1110
1111         if (otg_dev == NULL)
1112         {
1113                 /* Memory allocation for the dwc_otg_device failed. */
1114                 return 0;
1115         }
1116
1117         /*
1118          * Free the IRQ
1119          */
1120         if (otg_dev->common_irq_installed)
1121         {
1122                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1123         }
1124
1125 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1126         if (otg_dev->hcd != NULL)
1127         {
1128                 dwc_otg_hcd_remove(dev);
1129         }
1130 #endif
1131
1132 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1133         if (otg_dev->pcd != NULL)
1134         {
1135                 dwc_otg_pcd_remove(dev);
1136         }
1137 #endif
1138         if (otg_dev->core_if != NULL)
1139         {
1140                 dwc_otg_cil_remove( otg_dev->core_if );
1141         }
1142
1143         /*
1144          * Remove the device attributes
1145          */
1146         dwc_otg_attr_remove(dev);
1147
1148         /*
1149          * Return the memory.
1150          */
1151         if (otg_dev->base != NULL)
1152         {
1153                 iounmap(otg_dev->base);
1154         }
1155         clk_put(otg_dev->phyclk);
1156         clk_disable(otg_dev->phyclk);
1157         clk_put(otg_dev->ahbclk);
1158         clk_disable(otg_dev->ahbclk);
1159 #ifdef CONFIG_ARCH_RK29
1160         clk_put(otg_dev->busclk);
1161         clk_disable(otg_dev->busclk);
1162 #endif
1163         kfree(otg_dev);
1164
1165         /*
1166          * Clear the drvdata pointer.
1167          */
1168         dev->platform_data = 0;
1169
1170 #ifdef DWC_BOTH_HOST_SLAVE
1171         dwc_otg_module_params.host_rx_fifo_size = -1;
1172         dwc_otg_module_params.dev_nperio_tx_fifo_size = -1;
1173         dwc_otg_module_params.host_nperio_tx_fifo_size = -1;
1174         dwc_otg_module_params.dev_rx_fifo_size = -1;
1175 #endif
1176         return 0;
1177 }
1178
1179 /**
1180  * This function is called when an lm_device is bound to a
1181  * dwc_otg_driver. It creates the driver components required to
1182  * control the device (CIL, HCD, and PCD) and it initializes the
1183  * device. The driver components are stored in a dwc_otg_device
1184  * structure. A reference to the dwc_otg_device is saved in the
1185  * lm_device. This allows the driver to access the dwc_otg_device
1186  * structure on subsequent calls to driver methods for this device.
1187  *
1188  * @param[in] pdev  platform_device definition
1189  */
1190 static __devinit int dwc_otg_driver_probe(struct platform_device *pdev)
1191 {
1192         int retval = 0;
1193         struct resource *res_base;
1194         struct device *dev = &pdev->dev;
1195         dwc_otg_device_t *dwc_otg_device;
1196         int32_t snpsid;
1197         int irq;
1198         int32_t regval;
1199     struct clk *ahbclk,*phyclk,*busclk;
1200 #ifdef CONFIG_ARCH_RK29
1201     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
1202 #endif
1203 #ifdef CONFIG_ARCH_RK30
1204     unsigned int * otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON2);
1205 #endif
1206 #ifdef CONFIG_ARCH_RK2928
1207     unsigned int * otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON5);
1208 #endif
1209
1210 #ifdef CONFIG_ARCH_RK29
1211     regval = * otg_phy_con1;
1212 #ifndef CONFIG_USB11_HOST
1213         /*
1214          * disable usb host 1.1 controller if not support
1215          */
1216     phyclk = clk_get(NULL, "uhost");
1217     if (IS_ERR(phyclk)) {
1218             retval = PTR_ERR(phyclk);
1219             DWC_ERROR("can't get UHOST clock\n");
1220            goto fail;
1221     }
1222     clk_enable(phyclk);
1223
1224     ahbclk = clk_get(NULL, "hclk_uhost");
1225     if (IS_ERR(ahbclk)) {
1226             retval = PTR_ERR(ahbclk);
1227             DWC_ERROR("can't get UHOST ahb bus clock\n");
1228            goto fail;
1229     }
1230     clk_enable(ahbclk);
1231
1232         regval |= (0x01<<28);
1233
1234     *otg_phy_con1 = regval;
1235
1236     udelay(3);
1237     clk_disable(phyclk);
1238     clk_disable(ahbclk);
1239 #endif
1240 #ifndef CONFIG_USB20_HOST
1241         /*
1242          * disable usb host 2.0 phy if not support
1243          */
1244     phyclk = clk_get(NULL, "otgphy1");
1245     if (IS_ERR(phyclk)) {
1246             retval = PTR_ERR(phyclk);
1247             DWC_ERROR("can't get USBPHY1 clock\n");
1248            goto fail;
1249     }
1250     clk_enable(phyclk);
1251
1252     ahbclk = clk_get(NULL, "usbotg1");
1253     if (IS_ERR(ahbclk)) {
1254             retval = PTR_ERR(ahbclk);
1255             DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
1256            goto fail;
1257     }
1258     clk_enable(ahbclk);
1259
1260     regval &= ~(0x01<<14);    // enter suspend.
1261     regval |= (0x01<<13);    // software control enable.
1262
1263     *otg_phy_con1 = regval;
1264     udelay(3);
1265     clk_disable(phyclk);
1266     clk_disable(ahbclk);
1267 #endif
1268 #endif
1269
1270 #ifdef CONFIG_ARCH_RK30
1271 #ifndef CONFIG_USB20_HOST
1272     otg_phy_con = (unsigned int*)(USBGRF_UOC1_CON2);
1273     /*
1274      * disable usb host 2.0 phy if not support
1275      */
1276     phyclk = clk_get(NULL, "otgphy1");
1277     if (IS_ERR(phyclk)) {
1278             retval = PTR_ERR(phyclk);
1279             DWC_ERROR("can't get USBPHY1 clock\n");
1280            goto fail;
1281     }
1282     clk_enable(phyclk);
1283
1284     ahbclk = clk_get(NULL, "hclk_otg1");
1285     if (IS_ERR(ahbclk)) {
1286             retval = PTR_ERR(ahbclk);
1287             DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
1288            goto fail;
1289     }
1290     clk_enable(ahbclk);
1291
1292     *otg_phy_con = ((0x01<<2)|(0x00<<3)|(0x05<<6))|(((0x01<<2)|(0x01<<3)|(0x07<<6))<<16);   // enter suspend.
1293     udelay(3);
1294     clk_disable(phyclk);
1295     clk_disable(ahbclk);
1296 #endif
1297 #endif
1298 #ifdef CONFIG_ARCH_RK2928
1299 #ifndef CONFIG_USB20_HOST
1300     otg_phy_con = (unsigned int*)(USBGRF_UOC1_CON5);
1301     /*
1302      * disable usb host 2.0 phy if not support
1303      */
1304     phyclk = clk_get(NULL, "otgphy1");
1305     if (IS_ERR(phyclk)) {
1306             retval = PTR_ERR(phyclk);
1307             DWC_ERROR("can't get USBPHY1 clock\n");
1308            goto fail;
1309     }
1310     clk_enable(phyclk);
1311
1312     ahbclk = clk_get(NULL, "hclk_otg1");
1313     if (IS_ERR(ahbclk)) {
1314             retval = PTR_ERR(ahbclk);
1315             DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
1316            goto fail;
1317     }
1318     clk_enable(ahbclk);
1319
1320     *otg_phy_con = ((0x01<<0)|(0x00<<1)|(0x05<<4))|(((0x01<<0)|(0x01<<1)|(0x07<<4))<<16);   // enter suspend.
1321     udelay(3);
1322     clk_disable(phyclk);
1323     clk_disable(ahbclk);
1324 #endif
1325 #endif
1326         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1327
1328         if (dwc_otg_device == 0)
1329         {
1330                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1331                 retval = -ENOMEM;
1332                 goto fail;
1333         }
1334
1335         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1336         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1337
1338 #ifdef CONFIG_ARCH_RK29
1339         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, true);
1340         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, true);
1341         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, true);
1342     udelay(1);
1343
1344         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_AHB_BUS, false);
1345         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_PHY, false);
1346         cru_set_soft_reset(SOFT_RST_USB_OTG_2_0_CONTROLLER, false);
1347     busclk = clk_get(NULL, "hclk_usb_peri");
1348     if (IS_ERR(busclk)) {
1349             retval = PTR_ERR(busclk);
1350             DWC_ERROR("can't get USB PERIPH AHB bus clock\n");
1351            goto fail;
1352     }
1353     clk_enable(busclk);
1354
1355     phyclk = clk_get(NULL, "otgphy0");
1356     if (IS_ERR(phyclk)) {
1357             retval = PTR_ERR(phyclk);
1358             DWC_ERROR("can't get USBPHY0 clock\n");
1359            goto fail;
1360     }
1361     clk_enable(phyclk);
1362
1363     ahbclk = clk_get(NULL, "usbotg0");
1364     if (IS_ERR(ahbclk)) {
1365             retval = PTR_ERR(ahbclk);
1366             DWC_ERROR("can't get USB otg0 ahb bus clock\n");
1367            goto fail;
1368     }
1369     clk_enable(ahbclk);
1370
1371         /*
1372          * Enable usb phy 0
1373          */
1374     regval = * otg_phy_con1;
1375     regval |= (0x01<<2);
1376     regval |= (0x01<<3);    // exit suspend.
1377     regval &= ~(0x01<<2);
1378     *otg_phy_con1 = regval;
1379
1380         dwc_otg_device->phyclk = phyclk;
1381         dwc_otg_device->ahbclk = ahbclk;
1382         dwc_otg_device->busclk = busclk;
1383 #endif
1384 #ifdef CONFIG_ARCH_RK30
1385     otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON2);
1386     cru_set_soft_reset(SOFT_RST_USBPHY0, true);
1387         cru_set_soft_reset(SOFT_RST_OTGC0, true);
1388         cru_set_soft_reset(SOFT_RST_USBOTG0, true);
1389     udelay(1);
1390
1391         cru_set_soft_reset(SOFT_RST_USBOTG0, false);
1392         cru_set_soft_reset(SOFT_RST_OTGC0, false);
1393         cru_set_soft_reset(SOFT_RST_USBPHY0, false);
1394
1395     phyclk = clk_get(NULL, "otgphy0");
1396     if (IS_ERR(phyclk)) {
1397             retval = PTR_ERR(phyclk);
1398             DWC_ERROR("can't get USBPHY0 clock\n");
1399            goto fail;
1400     }
1401     clk_enable(phyclk);
1402
1403     ahbclk = clk_get(NULL, "hclk_otg0");
1404     if (IS_ERR(ahbclk)) {
1405             retval = PTR_ERR(ahbclk);
1406             DWC_ERROR("can't get USB otg0 ahb bus clock\n");
1407            goto fail;
1408     }
1409     clk_enable(ahbclk);
1410
1411         /*
1412          * Enable usb phy 0
1413          */
1414     *otg_phy_con = ((0x01<<2)<<16);
1415
1416         dwc_otg_device->phyclk = phyclk;
1417         dwc_otg_device->ahbclk = ahbclk;
1418 #endif
1419 #if 0//def CONFIG_ARCH_RK2928
1420     otg_phy_con = (unsigned int*)(USBGRF_UOC0_CON5);
1421         cru_set_soft_reset(SOFT_RST_USBPHY0, true);
1422         cru_set_soft_reset(SOFT_RST_OTGC0, true);
1423         cru_set_soft_reset(SOFT_RST_USBOTG0, true);
1424     udelay(1);
1425
1426         cru_set_soft_reset(SOFT_RST_USBOTG0, false);
1427         cru_set_soft_reset(SOFT_RST_OTGC0, false);
1428         cru_set_soft_reset(SOFT_RST_USBPHY0, false);
1429
1430     phyclk = clk_get(NULL, "otgphy0");
1431     if (IS_ERR(phyclk)) {
1432             retval = PTR_ERR(phyclk);
1433             DWC_ERROR("can't get USBPHY0 clock\n");
1434            goto fail;
1435     }
1436     clk_enable(phyclk);
1437
1438     ahbclk = clk_get(NULL, "hclk_otg0");
1439     if (IS_ERR(ahbclk)) {
1440             retval = PTR_ERR(ahbclk);
1441             DWC_ERROR("can't get USB otg0 ahb bus clock\n");
1442            goto fail;
1443     }
1444     clk_enable(ahbclk);
1445
1446         /*
1447          * Enable usb phy 0
1448          */
1449     *otg_phy_con =  (0x01<<16);
1450
1451         dwc_otg_device->phyclk = phyclk;
1452         dwc_otg_device->ahbclk = ahbclk;
1453 #endif
1454         /*
1455          * Map the DWC_otg Core memory into virtual address space.
1456          */
1457
1458         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1459         if (!res_base)
1460                 goto fail;
1461
1462         dwc_otg_device->base =  ioremap(res_base->start,USBOTG_SIZE);
1463         if (dwc_otg_device->base == NULL)
1464         {
1465                 dev_err(dev, "ioremap() failed\n");
1466                 retval = -ENOMEM;
1467                 goto fail;
1468         }
1469 #if 0
1470         dwc_otg_device->base = (void*)(USB_OTG_BASE_ADDR_VA);
1471
1472         if (dwc_otg_device->base == NULL)
1473         {
1474                 dev_err(dev, "ioremap() failed\n");
1475                 retval = -ENOMEM;
1476                 goto fail;
1477         }
1478 #endif
1479         dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
1480         /*
1481          * Attempt to ensure this device is really a DWC_otg Controller.
1482          * Read and verify the SNPSID register contents. The value should be
1483          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1484          */
1485         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1486         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1487         {
1488                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1489                 retval = -EINVAL;
1490                 goto fail;
1491         }
1492
1493         /*
1494          * Initialize driver data to point to the global DWC_otg
1495          * Device structure.
1496          */
1497         dev->platform_data = dwc_otg_device;
1498         dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1499         g_otgdev = dwc_otg_device;
1500
1501         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1502                                                         &dwc_otg_module_params);
1503         if (dwc_otg_device->core_if == 0)
1504         {
1505                 dev_err(dev, "CIL initialization failed!\n");
1506                 retval = -ENOMEM;
1507                 goto fail;
1508         }
1509         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1510         /*
1511          * Validate parameter values.
1512          */
1513         if (check_parameters(dwc_otg_device->core_if) != 0)
1514         {
1515                 retval = -EINVAL;
1516                 goto fail;
1517         }
1518
1519         /*
1520          * Create Device Attributes in sysfs
1521          */
1522         dwc_otg_attr_create(dev);
1523 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1524         retval |= device_create_file(dev, &dev_attr_enable);
1525 #endif
1526
1527         /*
1528          * Disable the global interrupt until all the interrupt
1529          * handlers are installed.
1530          */
1531         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1532         /*
1533          * Install the interrupt handler for the common interrupts before
1534          * enabling common interrupts in core_init below.
1535          */
1536         irq = platform_get_irq(to_platform_device(dev),0);
1537         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1538                          irq);
1539         retval = request_irq(irq, dwc_otg_common_irq,
1540                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1541         if (retval != 0)
1542         {
1543                 DWC_ERROR("request of irq%d failed\n", irq);
1544                 retval = -EBUSY;
1545                 goto fail;
1546         }
1547         else
1548         {
1549                 dwc_otg_device->common_irq_installed = 1;
1550         }
1551
1552 #ifdef CONFIG_MACH_IPMATE
1553         set_irq_type(irq, IRQT_LOW);
1554 #endif
1555
1556 #ifdef CONFIG_DWC_OTG_DEVICE_ONLY
1557         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1558 #else
1559 #ifdef CONFIG_DWC_OTG_HOST_ONLY
1560         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1561 #else
1562
1563 #ifdef CONFIG_DWC_OTG_DEFAULT_HOST
1564         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1565 #else
1566         dwc_otg_device->core_if->usb_mode = USB_MODE_NORMAL;
1567 #ifdef CONFIG_DWC_OTG_DEFAULT_DEVICE
1568         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1569 #endif
1570 #endif
1571
1572 #endif
1573 #endif
1574
1575         /*
1576          * Initialize the DWC_otg core.
1577          */
1578         dwc_otg_core_init( dwc_otg_device->core_if );
1579
1580 /* Initialize the bus state.  If the core is in Device Mode
1581  * HALT the USB bus and return. */
1582 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1583 #ifdef CONFIG_ARCH_RK29
1584     USB_IOMUX_INIT(GPIO4A5_OTG0DRVVBUS_NAME, GPIO4L_OTG0_DRV_VBUS);
1585 #endif
1586 #ifdef CONFIG_ARCH_RK30
1587     USB_IOMUX_INIT(GPIO0A5_OTGDRVVBUS_NAME, GPIO0A_OTG_DRV_VBUS);
1588 #endif
1589 #ifdef CONFIG_ARCH_RK2928
1590     USB_IOMUX_INIT(GPIO3C1_OTG_DRVVBUS_NAME, GPIO3C_OTG_DRVVBUS);
1591 #endif
1592         /*
1593          * Initialize the HCD
1594          */
1595         retval = dwc_otg_hcd_init(dev);
1596         if (retval != 0)
1597         {
1598                 DWC_ERROR("dwc_otg_hcd_init failed\n");
1599                 dwc_otg_device->hcd = NULL;
1600                 goto fail;
1601         }
1602 #endif
1603 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1604         /*
1605          * Initialize the PCD
1606          */
1607         retval = dwc_otg_pcd_init(dev);
1608         if (retval != 0)
1609         {
1610                 DWC_ERROR("dwc_otg_pcd_init failed\n");
1611                 dwc_otg_device->pcd = NULL;
1612                 goto fail;
1613         }
1614 #endif
1615
1616
1617         /*
1618          * Enable the global interrupt after all the interrupt
1619          * handlers are installed.
1620          */
1621         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
1622 #ifdef CONFIG_ARCH_RK29
1623 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1624     if(dwc_otg_device->hcd->host_enabled == 0)
1625     {
1626         clk_disable(dwc_otg_device->phyclk);
1627         clk_disable(dwc_otg_device->ahbclk);
1628         *otg_phy_con1 |= (0x01<<2);
1629         *otg_phy_con1 &= ~(0x01<<3);    // enter suspend.
1630     }
1631 #endif
1632 #endif
1633 #ifdef CONFIG_ARCH_RK30
1634 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1635     if(dwc_otg_device->hcd->host_enabled == 0)
1636     {
1637         clk_disable(dwc_otg_device->phyclk);
1638         clk_disable(dwc_otg_device->ahbclk);
1639        *otg_phy_con = ((0x01<<2)|(0x00<<3)|(0x05<<6))|(((0x01<<2)|(0x01<<3)|(0x07<<6))<<16);   // enter suspend.
1640     }
1641 #endif
1642 #endif
1643 #ifdef CONFIG_ARCH_RK2928
1644 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1645     if(dwc_otg_device->hcd->host_enabled == 0)
1646     {
1647         clk_disable(dwc_otg_device->phyclk);
1648         clk_disable(dwc_otg_device->ahbclk);
1649        *otg_phy_con =   ((0x01<<0)|(0x00<<1)|(0x05<<4))|(((0x01<<0)|(0x01<<1)|(0x07<<4))<<16);   // enter suspend.
1650     }
1651 #endif
1652 #endif
1653         return 0;
1654  fail:
1655         devm_kfree(&pdev->dev, dwc_otg_device);
1656         DWC_PRINT("dwc_otg_driver_probe fail,everest\n");
1657         return retval;
1658 }
1659
1660 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1661 extern int dwc_otg20phy_suspend( int exitsuspend );
1662 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1663 {
1664         struct device *dev = &_dev->dev;
1665         dwc_otg_device_t *otg_dev = dev->platform_data;
1666     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1667     if(core_if->op_state == A_HOST)
1668     {
1669         DWC_PRINT("%s,A_HOST mode\n", __func__);
1670         return 0;
1671     }
1672     /* Clear any pending interrupts */
1673     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1674     dwc_otg_disable_global_interrupts(core_if);
1675     dwc_otg20phy_suspend(0);
1676     del_timer(&otg_dev->pcd->check_vbus_timer);
1677
1678     return 0;
1679 }
1680 #else
1681 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1682 {
1683     return 0;
1684 }
1685 #endif
1686
1687 static int dwc_otg_driver_resume(struct platform_device *_dev )
1688 {
1689         struct device *dev = &_dev->dev;
1690         dwc_otg_device_t *otg_dev = dev->platform_data;
1691     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1692     dctl_data_t dctl = {.d32=0};
1693
1694     dwc_otg_core_global_regs_t *global_regs =
1695         core_if->core_global_regs;
1696     if(core_if->op_state == A_HOST)
1697     {
1698         DWC_PRINT("%s,A_HOST mode\n", __func__);
1699         return 0;
1700     }
1701 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1702
1703     dwc_otg20phy_suspend(1);
1704
1705     /* soft disconnect */
1706     /* 20100226,HSL@RK,if not disconnect,when usb cable in,will auto reconnect
1707      *  besause now USB PHY is enable,and get USB RESET irq.
1708     */
1709     /* soft disconnect */
1710     dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
1711     dctl.b.sftdiscon = 1;
1712     dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1713
1714     /* Clear any pending interrupts */
1715     dwc_write_reg32( &global_regs->gintsts, 0xeFFFFFFF);
1716
1717     dwc_otg_enable_global_interrupts(core_if);
1718     mod_timer(&otg_dev->pcd->check_vbus_timer , jiffies + HZ);
1719
1720 //sendwakeup:
1721     if(core_if->usb_wakeup)
1722     {
1723         core_if->usb_wakeup = 0;
1724     }
1725     DWC_PRINT("%s gahbcfg:0x%x\n", __func__, global_regs->gahbcfg);
1726 #endif
1727     return 0;
1728 }
1729
1730 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1731 {
1732         struct device *dev = &_dev->dev;
1733         dwc_otg_device_t *otg_dev = dev->platform_data;
1734     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1735     dctl_data_t dctl = {.d32=0};
1736
1737     DWC_PRINT("%s:: disconnect USB\n" , __func__ );
1738     /* soft disconnect */
1739     dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
1740     dctl.b.sftdiscon = 1;
1741     dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1742
1743     /* Clear any pending interrupts */
1744     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1745
1746 }
1747
1748 /**
1749  * This structure defines the methods to be called by a bus driver
1750  * during the lifecycle of a device on that bus. Both drivers and
1751  * devices are registered with a bus driver. The bus driver matches
1752  * devices to drivers based on information in the device and driver
1753  * structures.
1754  *
1755  * The probe function is called when the bus driver matches a device
1756  * to this driver. The remove function is called when a device is
1757  * unregistered with the bus driver.
1758  */
1759 static struct platform_driver dwc_otg_driver = {
1760         .probe = dwc_otg_driver_probe,
1761         .remove = dwc_otg_driver_remove,
1762         .suspend = dwc_otg_driver_suspend,
1763         .resume = dwc_otg_driver_resume,
1764         .shutdown = dwc_otg_driver_shutdown,
1765         .driver = {
1766                    .name = dwc_driver_name,
1767                    .owner = THIS_MODULE},
1768 };
1769
1770 #ifdef CONFIG_USB11_HOST
1771 extern void dwc_otg_hcd_remove(struct device *dev);
1772 extern int __devinit host11_hcd_init(struct device *dev);
1773
1774 static int host11_driver_remove(struct platform_device *pdev)
1775 {
1776         struct device *dev = &pdev->dev;
1777         dwc_otg_device_t *otg_dev = dev->platform_data;
1778         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1779
1780         if (otg_dev == NULL)
1781         {
1782                 /* Memory allocation for the dwc_otg_device failed. */
1783                 return 0;
1784         }
1785
1786         /*
1787          * Free the IRQ
1788          */
1789         if (otg_dev->common_irq_installed)
1790         {
1791                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1792         }
1793
1794         if (otg_dev->hcd != NULL)
1795         {
1796                 dwc_otg_hcd_remove(dev);
1797         }
1798
1799         if (otg_dev->core_if != NULL)
1800         {
1801                 dwc_otg_cil_remove( otg_dev->core_if );
1802         }
1803
1804         /*
1805          * Remove the device attributes
1806          */
1807         //dwc_otg_attr_remove(dev);
1808
1809         /*
1810          * Return the memory.
1811          */
1812         if (otg_dev->base != NULL)
1813         {
1814                 iounmap(otg_dev->base);
1815         }
1816         clk_put(otg_dev->phyclk);
1817         clk_disable(otg_dev->phyclk);
1818         clk_put(otg_dev->ahbclk);
1819         clk_disable(otg_dev->ahbclk);
1820         kfree(otg_dev);
1821
1822         /*
1823          * Clear the drvdata pointer.
1824          */
1825         dev->platform_data = 0;
1826
1827         return 0;
1828 }
1829
1830 /**
1831  * This function is called when an lm_device is bound to a
1832  * dwc_otg_driver. It creates the driver components required to
1833  * control the device (CIL, HCD, and PCD) and it initializes the
1834  * device. The driver components are stored in a dwc_otg_device
1835  * structure. A reference to the dwc_otg_device is saved in the
1836  * lm_device. This allows the driver to access the dwc_otg_device
1837  * structure on subsequent calls to driver methods for this device.
1838  *
1839  * @param[in] pdev  platform_device definition
1840  */
1841 static __devinit int host11_driver_probe(struct platform_device *pdev)
1842 {
1843         struct resource *res_base;
1844         int retval = 0;
1845         struct device *dev = &pdev->dev;
1846         dwc_otg_device_t *dwc_otg_device;
1847         int32_t snpsid;
1848         int irq;
1849     struct clk* ahbclk,*phyclk;
1850         /*
1851          *Enable usb phy
1852          */
1853     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
1854
1855     *otg_phy_con1 &= ~(0x01<<28);    // exit suspend.
1856     #if 0
1857     *otg_phy_con1 |= (0x01<<2);
1858     *otg_phy_con1 |= (0x01<<3);    // exit suspend.
1859     *otg_phy_con1 &= ~(0x01<<2);
1860     otgreg = ioremap(RK2818_USBOTG_PHYS,RK2818_USBOTG_SIZE);
1861     DWC_PRINT("%s otg2.0 reg addr: 0x%x",__func__,otgreg);
1862     dwc_modify_reg32((uint32_t *)(otgreg+0xc),0x20000000,0x20000000);
1863         dwc_write_reg32((uint32_t *)(otgreg+0x440), 0x1000);
1864     #endif
1865
1866         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1867
1868         if (dwc_otg_device == 0)
1869         {
1870                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1871                 retval = -ENOMEM;
1872                 goto fail;
1873         }
1874
1875         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1876         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1877
1878         cru_set_soft_reset(SOFT_RST_UHOST, true);
1879     udelay(1);
1880
1881         cru_set_soft_reset(SOFT_RST_UHOST, false);
1882
1883     phyclk = clk_get(NULL, "uhost");
1884     if (IS_ERR(phyclk)) {
1885             retval = PTR_ERR(phyclk);
1886             DWC_ERROR("can't get UHOST clock\n");
1887            goto fail;
1888     }
1889     clk_enable(phyclk);
1890
1891     ahbclk = clk_get(NULL, "hclk_uhost");
1892     if (IS_ERR(ahbclk)) {
1893             retval = PTR_ERR(ahbclk);
1894             DWC_ERROR("can't get UHOST ahb bus clock\n");
1895            goto fail1;
1896     }
1897     clk_enable(ahbclk);
1898
1899     if (clk_get_rate(phyclk) != 48000000) {
1900         DWC_PRINT("Bad USB clock (%d Hz), changing to 48000000 Hz\n",
1901                  (int)clk_get_rate(phyclk));
1902         if (clk_set_rate(phyclk, 48000000)) {
1903             DWC_ERROR("Unable to set correct USB clock (48MHz)\n");
1904             retval = -EIO;
1905             goto fail2;
1906         }
1907     }
1908         dwc_otg_device->ahbclk = ahbclk;
1909         dwc_otg_device->phyclk = phyclk;
1910
1911         /*
1912          * Map the DWC_otg Core memory into virtual address space.
1913          */
1914
1915         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1916         if (!res_base)
1917                 goto fail;
1918
1919         dwc_otg_device->base =
1920                 ioremap(res_base->start,USBOTG_SIZE);
1921     DWC_PRINT("%s host1.1 reg addr: 0x%x remap:0x%x\n",__func__,
1922                 (unsigned)res_base->start, (unsigned)dwc_otg_device->base);
1923         if (dwc_otg_device->base == NULL)
1924         {
1925                 DWC_ERROR("ioremap() failed\n");
1926                 retval = -ENOMEM;
1927                 goto fail;
1928         }
1929         DWC_DEBUGPL( DBG_CIL, "base addr for rk29 host11:0x%x\n", (unsigned)dwc_otg_device->base);
1930         /*
1931          * Attempt to ensure this device is really a DWC_otg Controller.
1932          * Read and verify the SNPSID register contents. The value should be
1933          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1934          */
1935         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1936         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1937         {
1938                         DWC_PRINT("%s::snpsid=0x%x,want 0x%x" , __func__ , snpsid , 0x4F542000 );
1939                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1940                 retval = -EINVAL;
1941                 goto fail;
1942         }
1943
1944         /*
1945          * Initialize driver data to point to the global DWC_otg
1946          * Device structure.
1947          */
1948         dev->platform_data = dwc_otg_device;
1949         DWC_DEBUGPL(DBG_CIL, "dwc_otg_device=0x%p\n", dwc_otg_device);
1950         g_host11 = dwc_otg_device;
1951
1952         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1953                                                         &host11_module_params);
1954         if (dwc_otg_device->core_if == 0)
1955         {
1956                 dev_err(dev, "CIL initialization failed!\n");
1957                 retval = -ENOMEM;
1958                 goto fail;
1959         }
1960
1961         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1962         /*
1963          * Validate parameter values.
1964          */
1965         if (check_parameters(dwc_otg_device->core_if) != 0)
1966         {
1967                 retval = -EINVAL;
1968                 goto fail;
1969         }
1970
1971         /*
1972          * Create Device Attributes in sysfs
1973          */
1974         dwc_otg_attr_create(dev);
1975         retval |= device_create_file(dev, &dev_attr_enable);
1976
1977         /*
1978          * Disable the global interrupt until all the interrupt
1979          * handlers are installed.
1980          */
1981         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1982         /*
1983          * Install the interrupt handler for the common interrupts before
1984          * enabling common interrupts in core_init below.
1985          */
1986         irq = platform_get_irq(to_platform_device(dev),0);
1987         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1988                          irq);
1989         retval = request_irq(irq, dwc_otg_common_irq,
1990                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1991         if (retval != 0)
1992         {
1993                 DWC_ERROR("request of irq%d failed\n", irq);
1994                 retval = -EBUSY;
1995                 goto fail;
1996         }
1997         else
1998         {
1999                 dwc_otg_device->common_irq_installed = 1;
2000         }
2001
2002         /*
2003          * Initialize the DWC_otg core.
2004          */
2005         dwc_otg_core_init( dwc_otg_device->core_if );
2006
2007         /*
2008          * Initialize the HCD
2009          */
2010         retval = host11_hcd_init(dev);
2011         if (retval != 0)
2012         {
2013                 DWC_ERROR("host11_hcd_init failed\n");
2014                 dwc_otg_device->hcd = NULL;
2015                 goto fail;
2016         }
2017         /*
2018          * Enable the global interrupt after all the interrupt
2019          * handlers are installed.
2020          */
2021         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
2022 #ifndef CONFIG_USB11_HOST_EN
2023     *otg_phy_con1 |= (0x01<<28);    // enter suspend.
2024     clk_disable(phyclk);
2025     clk_disable(ahbclk);
2026 #endif
2027         return 0;
2028
2029 fail2:
2030     clk_put(ahbclk);
2031     clk_disable(ahbclk);
2032 fail1:
2033     clk_put(phyclk);
2034     clk_disable(phyclk);
2035
2036  fail:
2037         devm_kfree(&pdev->dev, dwc_otg_device);
2038         DWC_PRINT("host11_driver_probe fail,everest\n");
2039         return retval;
2040 }
2041
2042 static struct platform_driver host11_driver = {
2043         .probe = host11_driver_probe,
2044         .remove = host11_driver_remove,
2045         .driver = {
2046                    .name = "usb11_host",
2047                    .owner = THIS_MODULE},
2048 };
2049 #endif
2050
2051 #ifdef CONFIG_USB20_HOST
2052 extern void dwc_otg_hcd_remove(struct device *dev);
2053 extern int __devinit host20_hcd_init(struct device *_dev);
2054
2055
2056 static int host20_driver_remove(struct platform_device *pdev)
2057 {
2058         struct device *dev = &pdev->dev;
2059         dwc_otg_device_t *otg_dev = dev->platform_data;
2060         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
2061
2062         if (otg_dev == NULL)
2063         {
2064                 /* Memory allocation for the dwc_otg_device failed. */
2065                 return 0;
2066         }
2067
2068         /*
2069          * Free the IRQ
2070          */
2071         if (otg_dev->common_irq_installed)
2072         {
2073                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
2074         }
2075
2076         if (otg_dev->hcd != NULL)
2077         {
2078                 dwc_otg_hcd_remove(dev);
2079         }
2080
2081         if (otg_dev->core_if != NULL)
2082         {
2083                 dwc_otg_cil_remove( otg_dev->core_if );
2084         }
2085
2086         /*
2087          * Remove the device attributes
2088          */
2089         //dwc_otg_attr_remove(dev);
2090
2091         /*
2092          * Return the memory.
2093          */
2094         if (otg_dev->base != NULL)
2095         {
2096                 iounmap(otg_dev->base);
2097         }
2098         clk_put(otg_dev->phyclk);
2099         clk_disable(otg_dev->phyclk);
2100         clk_put(otg_dev->ahbclk);
2101         clk_disable(otg_dev->ahbclk);
2102         kfree(otg_dev);
2103
2104         /*
2105          * Clear the drvdata pointer.
2106          */
2107         dev->platform_data = 0;
2108
2109
2110         return 0;
2111 }
2112
2113 /**
2114  * This function is called when an lm_device is bound to a
2115  * dwc_otg_driver. It creates the driver components required to
2116  * control the device (CIL, HCD, and PCD) and it initializes the
2117  * device. The driver components are stored in a dwc_otg_device
2118  * structure. A reference to the dwc_otg_device is saved in the
2119  * lm_device. This allows the driver to access the dwc_otg_device
2120  * structure on subsequent calls to driver methods for this device.
2121  *
2122  * @param[in] pdev  platform_device definition
2123  */
2124 static __devinit int host20_driver_probe(struct platform_device *pdev)
2125 {
2126         struct resource *res_base;
2127         int retval = 0;
2128         struct device *dev = &pdev->dev;
2129         dwc_otg_device_t *dwc_otg_device;
2130         int32_t snpsid;
2131         int irq;
2132         uint32_t otgreg;
2133     struct clk* ahbclk,*phyclk;
2134         /*
2135          *Enable usb phy
2136          */
2137 #ifdef CONFIG_ARCH_RK29
2138     unsigned int * otg_phy_con1 = (unsigned int*)(USB_GRF_CON);
2139     otgreg = * otg_phy_con1;
2140     otgreg |= (0x01<<13);    // software control enable
2141     otgreg |= (0x01<<14);    // exit suspend.
2142     otgreg &= ~(0x01<<13);    // software control disable
2143     *otg_phy_con1 = otgreg;
2144 #endif
2145 #ifdef CONFIG_ARCH_RK30
2146     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON2);
2147     *otg_phy_con1 = ((0x01<<2)<<16);    // exit suspend.
2148 #endif
2149 #ifdef CONFIG_ARCH_RK2928
2150     unsigned int * otg_phy_con1 = (unsigned int*)(USBGRF_UOC1_CON5);
2151     *otg_phy_con1 = (0x01<<16);    // exit suspend.
2152 #endif
2153     #if 0
2154     *otg_phy_con1 |= (0x01<<2);
2155     *otg_phy_con1 |= (0x01<<3);    // exit suspend.
2156     *otg_phy_con1 &= ~(0x01<<2);
2157     otgreg = ioremap(RK2818_USBOTG_PHYS,RK2818_USBOTG_SIZE);
2158     DWC_PRINT("%s otg2.0 reg addr: 0x%x",__func__,otgreg);
2159     dwc_modify_reg32((uint32_t *)(otgreg+0xc),0x20000000,0x20000000);
2160         dwc_write_reg32((uint32_t *)(otgreg+0x440), 0x1000);
2161     #endif
2162
2163         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
2164
2165 #ifdef CONFIG_ARCH_RK29
2166         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_AHB_BUS, true);
2167         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, true);
2168         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, true);
2169
2170     udelay(1);
2171
2172         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_AHB_BUS, false);
2173         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_PHY, false);
2174         cru_set_soft_reset(SOFT_RST_USB_HOST_2_0_CONTROLLER, false);
2175 #endif
2176 #ifdef CONFIG_ARCH_RK30
2177     *(unsigned int*)(USBGRF_UOC1_CON2+4) = ((1<<5)|((1<<5)<<16));
2178 #endif
2179         if (dwc_otg_device == 0)
2180         {
2181                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
2182                 retval = -ENOMEM;
2183                 goto fail;
2184         }
2185
2186         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
2187         dwc_otg_device->reg_offset = 0xFFFFFFFF;
2188
2189     phyclk = clk_get(NULL, "otgphy1");
2190     if (IS_ERR(phyclk)) {
2191             retval = PTR_ERR(phyclk);
2192             DWC_ERROR("can't get USBPHY1 clock\n");
2193            goto fail;
2194     }
2195     clk_enable(phyclk);
2196
2197 #ifdef CONFIG_ARCH_RK29
2198     ahbclk = clk_get(NULL, "usbotg1");
2199 #endif
2200 #ifdef CONFIG_ARCH_RK30
2201     ahbclk = clk_get(NULL, "hclk_otg1");
2202 #endif
2203 #ifdef CONFIG_ARCH_RK2928
2204     ahbclk = clk_get(NULL, "hclk_otg1");    //check
2205 #endif
2206     if (IS_ERR(ahbclk)) {
2207             retval = PTR_ERR(ahbclk);
2208             DWC_ERROR("can't get USBOTG1 ahb bus clock\n");
2209            goto fail;
2210     }
2211     clk_enable(ahbclk);
2212         dwc_otg_device->phyclk = phyclk;
2213         dwc_otg_device->ahbclk = ahbclk;
2214
2215         /*
2216          * Map the DWC_otg Core memory into virtual address space.
2217          */
2218
2219         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2220         if (!res_base)
2221                 goto fail;
2222
2223         dwc_otg_device->base =
2224                 ioremap(res_base->start,USBOTG_SIZE);
2225     DWC_PRINT("%s host2.0 reg addr: 0x%x remap:0x%x\n",__func__,
2226                 (unsigned)res_base->start, (unsigned)dwc_otg_device->base);
2227         if (dwc_otg_device->base == NULL)
2228         {
2229                 DWC_ERROR("ioremap() failed\n");
2230                 retval = -ENOMEM;
2231                 goto fail;
2232         }
2233         DWC_DEBUGPL( DBG_CIL, "base addr for rk29 host20:0x%x\n", (unsigned)dwc_otg_device->base);
2234         /*
2235          * Attempt to ensure this device is really a DWC_otg Controller.
2236          * Read and verify the SNPSID register contents. The value should be
2237          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
2238          */
2239         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
2240         if ((snpsid & 0xFFFFF000) != 0x4F542000)
2241         {
2242                         DWC_PRINT("%s::snpsid=0x%x,want 0x%x" , __func__ , snpsid , 0x4F542000 );
2243                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
2244                 retval = -EINVAL;
2245                 goto fail;
2246         }
2247
2248         /*
2249          * Initialize driver data to point to the global DWC_otg
2250          * Device structure.
2251          */
2252         dev->platform_data = dwc_otg_device;
2253         DWC_DEBUGPL(DBG_CIL, "dwc_otg_device=0x%p\n", dwc_otg_device);
2254         g_host20 = dwc_otg_device;
2255
2256         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
2257                                                         &host20_module_params);
2258         if (dwc_otg_device->core_if == 0)
2259         {
2260                 dev_err(dev, "CIL initialization failed!\n");
2261                 retval = -ENOMEM;
2262                 goto fail;
2263         }
2264
2265         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
2266         /*
2267          * Validate parameter values.
2268          */
2269         if (check_parameters(dwc_otg_device->core_if) != 0)
2270         {
2271                 retval = -EINVAL;
2272                 goto fail;
2273         }
2274
2275         /*
2276          * Create Device Attributes in sysfs
2277          */
2278         dwc_otg_attr_create(dev);
2279         retval |= device_create_file(dev, &dev_attr_enable);
2280
2281         /*
2282          * Disable the global interrupt until all the interrupt
2283          * handlers are installed.
2284          */
2285         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
2286         /*
2287          * Install the interrupt handler for the common interrupts before
2288          * enabling common interrupts in core_init below.
2289          */
2290         irq = platform_get_irq(to_platform_device(dev),0);
2291         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
2292                          irq);
2293         retval = request_irq(irq, dwc_otg_common_irq,
2294                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
2295         if (retval != 0)
2296         {
2297                 DWC_ERROR("request of irq%d failed\n", irq);
2298                 retval = -EBUSY;
2299                 goto fail;
2300         }
2301         else
2302         {
2303                 dwc_otg_device->common_irq_installed = 1;
2304         }
2305
2306 #ifdef CONFIG_ARCH_RK29
2307     USB_IOMUX_INIT(GPIO4A6_OTG1DRVVBUS_NAME, GPIO4L_OTG1_DRV_VBUS);
2308 #endif
2309 #ifdef CONFIG_ARCH_RK30
2310     USB_IOMUX_INIT(GPIO0A6_HOSTDRVVBUS_NAME, GPIO0A_HOST_DRV_VBUS);
2311 #endif
2312         /*
2313          * Initialize the DWC_otg core.
2314          */
2315         dwc_otg_core_init( dwc_otg_device->core_if );
2316
2317         /*
2318          * Initialize the HCD
2319          */
2320         retval = host20_hcd_init(dev);
2321         if (retval != 0)
2322         {
2323                 DWC_ERROR("host20_hcd_init failed\n");
2324                 dwc_otg_device->hcd = NULL;
2325                 goto fail;
2326         }
2327         /*
2328          * Enable the global interrupt after all the interrupt
2329          * handlers are installed.
2330          */
2331         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
2332 #ifndef CONFIG_USB20_HOST_EN
2333     clk_disable(phyclk);
2334     clk_disable(ahbclk);
2335 #if defined(CONFIG_ARCH_RK29)
2336     otgreg &= ~(0x01<<14);    // suspend.
2337     otgreg |= (0x01<<13);     // software control enable
2338     *otg_phy_con1 = otgreg;
2339 #elif defined(CONFIG_ARCH_RK30)
2340     *otg_phy_con1 = ((0x01<<2)|(0x00<<3)|(0x05<<6))|(((0x01<<2)|(0x01<<3)|(0x07<<6))<<16);   // enter suspend.
2341 #elif defined(CONFIG_ARCH_RK2928)
2342     *otg_phy_con1 = ((0x01<<0)|(0x00<<1)|(0x05<<4))|(((0x01<<0)|(0x01<<1)|(0x07<<4))<<16);   // enter suspend.
2343 #endif
2344 #endif
2345         return 0;
2346
2347  fail:
2348         devm_kfree(&pdev->dev, dwc_otg_device);
2349         DWC_PRINT("host20_driver_probe fail,everest\n");
2350         return retval;
2351 }
2352
2353 static struct platform_driver host20_driver = {
2354         .probe = host20_driver_probe,
2355         .remove = host20_driver_remove,
2356         .driver = {
2357                    .name = "usb20_host",
2358                    .owner = THIS_MODULE},
2359 };
2360 #endif
2361
2362 /**
2363  * This function is called when the dwc_otg_driver is installed with the
2364  * insmod command. It registers the dwc_otg_driver structure with the
2365  * appropriate bus driver. This will cause the dwc_otg_driver_probe function
2366  * to be called. In addition, the bus driver will automatically expose
2367  * attributes defined for the device and driver in the special sysfs file
2368  * system.
2369  *
2370  * @return
2371  */
2372 static int __init dwc_otg_driver_init(void)
2373 {
2374         int retval = 0;
2375     /*
2376      *  USB2.0 OTG controller
2377      */
2378         retval = platform_driver_register(&dwc_otg_driver);
2379         if (retval < 0)
2380         {
2381                 DWC_ERROR("%s retval=%d\n", __func__, retval);
2382                 return retval;
2383         }
2384         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_version))
2385                 pr_warning("DWC_OTG: Failed to create driver version file\n");
2386         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel))
2387                 pr_warning("DWC_OTG: Failed to create driver debug level file\n");
2388 #ifndef CONFIG_DWC_OTG_HOST_ONLY
2389         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en))
2390                 pr_warning("DWC_OTG: Failed to create driver dwc_otg_conn_en file");
2391 #endif
2392 #ifndef CONFIG_DWC_OTG_HOST_ONLY
2393         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status))
2394                 pr_warning("DWC_OTG: Failed to create driver vbus status file");
2395 #endif
2396 #ifdef DWC_BOTH_HOST_SLAVE
2397     if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode))
2398                 pr_warning("DWC_OTG: Failed to create driver force usb mode file\n");
2399 #endif
2400
2401     /*
2402      *  USB2.0 host controller
2403      */
2404 #ifdef CONFIG_USB20_HOST
2405     retval = platform_driver_register(&host20_driver);
2406     if (retval < 0)
2407     {
2408         DWC_ERROR("%s retval=%d\n", __func__, retval);
2409         return retval;
2410     }
2411 #endif
2412
2413     /*
2414      *  USB1.1 host controller
2415      */
2416
2417 #ifdef CONFIG_USB11_HOST
2418         retval = platform_driver_register(&host11_driver);
2419         if (retval < 0)
2420         {
2421                 DWC_ERROR("%s retval=%d\n", __func__, retval);
2422                 return retval;
2423         }
2424 //      retval = driver_create_file(&host11_driver.driver, &driver_attr_enable_usb11);
2425 #endif
2426
2427         return retval;
2428 }
2429 module_init(dwc_otg_driver_init);
2430
2431 /**
2432  * This function is called when the driver is removed from the kernel
2433  * with the rmmod command. The driver unregisters itself with its bus
2434  * driver.
2435  *
2436  */
2437 static void __exit dwc_otg_driver_cleanup(void)
2438 {
2439         DWC_PRINT("dwc_otg_driver_cleanup()\n");
2440
2441         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
2442         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
2443
2444 #ifdef DWC_BOTH_HOST_SLAVE
2445         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
2446 #endif
2447 #ifndef CONFIG_DWC_OTG_HOST_ONLY
2448     driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
2449 #endif
2450 #ifndef CONFIG_DWC_OTG_HOST_ONLY
2451     driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
2452 #endif
2453
2454         platform_driver_unregister(&dwc_otg_driver);
2455
2456 #ifdef CONFIG_USB11_HOST
2457         platform_driver_unregister(&host11_driver);
2458 #endif
2459
2460 #ifdef CONFIG_USB20_HOST
2461         platform_driver_unregister(&host20_driver);
2462 #endif
2463         DWC_PRINT("%s module removed\n", dwc_driver_name);
2464 }
2465 module_exit(dwc_otg_driver_cleanup);
2466
2467 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
2468 MODULE_AUTHOR("Synopsys Inc.");
2469 MODULE_LICENSE("GPL");
2470
2471 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
2472 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
2473 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
2474 MODULE_PARM_DESC(opt, "OPT Mode");
2475 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
2476 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
2477 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
2478 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
2479 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
2480 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
2481 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
2482 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
2483 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
2484 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
2485 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
2486 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
2487 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
2488 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
2489 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
2490 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
2491 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
2492 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
2493 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
2494 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
2495 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
2496 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
2497 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
2498 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
2499 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
2500 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
2501 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
2502 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
2503 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
2504 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
2505 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
2506 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
2507 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
2508 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
2509 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
2510 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
2511 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
2512 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
2513 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
2514 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
2515 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
2516 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
2517 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
2518 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
2519 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
2520 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
2521 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
2522 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
2523 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
2524 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
2525 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
2526 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
2527 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
2528 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
2529 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
2530 /** @todo Set the max to 512K, modify checks */
2531 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
2532 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
2533 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
2534 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
2535 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
2536 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
2537 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
2538 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
2539 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
2540 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
2541 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
2542 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
2543 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
2544 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
2545 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
2546 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
2547 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
2548 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
2549 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
2550 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
2551 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
2552 module_param_named(debug, g_dbg_lvl, int, 0444);
2553 MODULE_PARM_DESC(debug, "");
2554
2555 module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
2556 MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
2557 module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
2558 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
2559 module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
2560 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2561 module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2562 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2563 module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2564 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2565 module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2566 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2567 module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2568 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2569 module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2570 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2571 module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2572 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2573 module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2574 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2575 module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2576 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2577 module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2578 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2579 module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2580 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2581 module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2582 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2583 module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2584 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2585 module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2586 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2587
2588 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2589 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2590 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
2591 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2592 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
2593 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2594 /** @page "Module Parameters"
2595  *
2596  * The following parameters may be specified when starting the module.
2597  * These parameters define how the DWC_otg controller should be
2598  * configured.  Parameter values are passed to the CIL initialization
2599  * function dwc_otg_cil_init
2600  *
2601  * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2602  *
2603
2604  <table>
2605  <tr><td>Parameter Name</td><td>Meaning</td></tr>
2606
2607  <tr>
2608  <td>otg_cap</td>
2609  <td>Specifies the OTG capabilities. The driver will automatically detect the
2610  value for this parameter if none is specified.
2611  - 0: HNP and SRP capable (default, if available)
2612  - 1: SRP Only capable
2613  - 2: No HNP/SRP capable
2614  </td></tr>
2615
2616  <tr>
2617  <td>dma_enable</td>
2618  <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2619  The driver will automatically detect the value for this parameter if none is
2620  specified.
2621  - 0: Slave
2622  - 1: DMA (default, if available)
2623  </td></tr>
2624
2625  <tr>
2626  <td>dma_burst_size</td>
2627  <td>The DMA Burst size (applicable only for External DMA Mode).
2628  - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2629  </td></tr>
2630
2631  <tr>
2632  <td>speed</td>
2633  <td>Specifies the maximum speed of operation in host and device mode. The
2634  actual speed depends on the speed of the attached device and the value of
2635  phy_type.
2636  - 0: High Speed (default)
2637  - 1: Full Speed
2638  </td></tr>
2639
2640  <tr>
2641  <td>host_support_fs_ls_low_power</td>
2642  <td>Specifies whether low power mode is supported when attached to a Full
2643  Speed or Low Speed device in host mode.
2644  - 0: Don't support low power mode (default)
2645  - 1: Support low power mode
2646  </td></tr>
2647
2648  <tr>
2649  <td>host_ls_low_power_phy_clk</td>
2650  <td>Specifies the PHY clock rate in low power mode when connected to a Low
2651  Speed device in host mode. This parameter is applicable only if
2652  HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2653  - 0: 48 MHz (default)
2654  - 1: 6 MHz
2655  </td></tr>
2656
2657  <tr>
2658  <td>enable_dynamic_fifo</td>
2659  <td> Specifies whether FIFOs may be resized by the driver software.
2660  - 0: Use cC FIFO size parameters
2661  - 1: Allow dynamic FIFO sizing (default)
2662  </td></tr>
2663
2664  <tr>
2665  <td>data_fifo_size</td>
2666  <td>Total number of 4-byte words in the data FIFO memory. This memory
2667  includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2668  - Values: 32 to 32768 (default 8192)
2669
2670  Note: The total FIFO memory depth in the FPGA configuration is 8192.
2671  </td></tr>
2672
2673  <tr>
2674  <td>dev_rx_fifo_size</td>
2675  <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2676  FIFO sizing is enabled.
2677  - Values: 16 to 32768 (default 1064)
2678  </td></tr>
2679
2680  <tr>
2681  <td>dev_nperio_tx_fifo_size</td>
2682  <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2683  dynamic FIFO sizing is enabled.
2684  - Values: 16 to 32768 (default 1024)
2685  </td></tr>
2686
2687  <tr>
2688  <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2689  <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2690  when dynamic FIFO sizing is enabled.
2691  - Values: 4 to 768 (default 256)
2692  </td></tr>
2693
2694  <tr>
2695  <td>host_rx_fifo_size</td>
2696  <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2697  sizing is enabled.
2698  - Values: 16 to 32768 (default 1024)
2699  </td></tr>
2700
2701  <tr>
2702  <td>host_nperio_tx_fifo_size</td>
2703  <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2704  dynamic FIFO sizing is enabled in the core.
2705  - Values: 16 to 32768 (default 1024)
2706  </td></tr>
2707
2708  <tr>
2709  <td>host_perio_tx_fifo_size</td>
2710  <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2711  sizing is enabled.
2712  - Values: 16 to 32768 (default 1024)
2713  </td></tr>
2714
2715  <tr>
2716  <td>max_transfer_size</td>
2717  <td>The maximum transfer size supported in bytes.
2718  - Values: 2047 to 65,535 (default 65,535)
2719  </td></tr>
2720
2721  <tr>
2722  <td>max_packet_count</td>
2723  <td>The maximum number of packets in a transfer.
2724  - Values: 15 to 511 (default 511)
2725  </td></tr>
2726
2727  <tr>
2728  <td>host_channels</td>
2729  <td>The number of host channel registers to use.
2730  - Values: 1 to 16 (default 12)
2731
2732  Note: The FPGA configuration supports a maximum of 12 host channels.
2733  </td></tr>
2734
2735  <tr>
2736  <td>dev_endpoints</td>
2737  <td>The number of endpoints in addition to EP0 available for device mode
2738  operations.
2739  - Values: 1 to 15 (default 6 IN and OUT)
2740
2741  Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2742  addition to EP0.
2743  </td></tr>
2744
2745  <tr>
2746  <td>phy_type</td>
2747  <td>Specifies the type of PHY interface to use. By default, the driver will
2748  automatically detect the phy_type.
2749  - 0: Full Speed
2750  - 1: UTMI+ (default, if available)
2751  - 2: ULPI
2752  </td></tr>
2753
2754  <tr>
2755  <td>phy_utmi_width</td>
2756  <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2757  phy_type of UTMI+. Also, this parameter is applicable only if the
2758  OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2759  core has been configured to work at either data path width.
2760  - Values: 8 or 16 bits (default 16)
2761  </td></tr>
2762
2763  <tr>
2764  <td>phy_ulpi_ddr</td>
2765  <td>Specifies whether the ULPI operates at double or single data rate. This
2766  parameter is only applicable if phy_type is ULPI.
2767  - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2768  - 1: double data rate ULPI interface with 4 bit wide data bus
2769  </td></tr>
2770
2771  <tr>
2772  <td>i2c_enable</td>
2773  <td>Specifies whether to use the I2C interface for full speed PHY. This
2774  parameter is only applicable if PHY_TYPE is FS.
2775  - 0: Disabled (default)
2776  - 1: Enabled
2777  </td></tr>
2778
2779  <tr>
2780  <td>otg_en_multiple_tx_fifo</td>
2781  <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2782  The driver will automatically detect the value for this parameter if none is
2783  specified.
2784  - 0: Disabled
2785  - 1: Enabled (default, if available)
2786  </td></tr>
2787
2788  <tr>
2789  <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2790  <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2791  when dynamic FIFO sizing is enabled.
2792  - Values: 4 to 768 (default 256)
2793  </td></tr>
2794
2795 */