drivers/usb/dwc_otg/dwc_otg_driver.c

   1 /* ==========================================================================
   2  * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $
   3  * $Revision: #12 $
   4  * $Date: 2007/02/07 $
   5  * $Change: 791271 $
   6  *
   7  * Synopsys HS OTG Linux Software Driver and documentation (hereinafter,
   8  * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless
   9  * otherwise expressly agreed to in writing between Synopsys and you.
  10  *
  11  * The Software IS NOT an item of Licensed Software or Licensed Product under
  12  * any End User Software License Agreement or Agreement for Licensed Product
  13  * with Synopsys or any supplement thereto. You are permitted to use and
  14  * redistribute this Software in source and binary forms, with or without
  15  * modification, provided that redistributions of source code must retain this
  16  * notice. You may not view, use, disclose, copy or distribute this file or
  17  * any information contained herein except pursuant to this license grant from
  18  * Synopsys. If you do not agree with this notice, including the disclaimer
  19  * below, then you are not authorized to use the Software.
  20  *
  21  * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS
  22  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT,
  25  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  26  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  27  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  28  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
  31  * DAMAGE.
  32  * ========================================================================== */
  33
  34 /** @file
  35  * The dwc_otg_driver module provides the initialization and cleanup entry
  36  * points for the DWC_otg driver. This module will be dynamically installed
  37  * after Linux is booted using the insmod command. When the module is
  38  * installed, the dwc_otg_driver_init function is called. When the module is
  39  * removed (using rmmod), the dwc_otg_driver_cleanup function is called.
  40  *
  41  * This module also defines a data structure for the dwc_otg_driver, which is
  42  * used in conjunction with the standard ARM lm_device structure. These
  43  * structures allow the OTG driver to comply with the standard Linux driver
  44  * model in which devices and drivers are registered with a bus driver. This
  45  * has the benefit that Linux can expose attributes of the driver and device
  46  * in its special sysfs file system. Users can then read or write files in
  47  * this file system to perform diagnostics on the driver components or the
  48  * device.
  49  */
  50
  51 #include <linux/kernel.h>
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/init.h>
  55 #include <linux/device.h>
  56 #include <linux/errno.h>
  57 #include <linux/types.h>
  58 #include <linux/stat.h>  /* permission constants */
  59
  60 #include <asm/io.h>
  61 #include <asm/sizes.h>
  62
  63 #include "linux/dwc_otg_plat.h"
  64 #include <linux/platform_device.h>
  65 #include <linux/of.h>
  66 #include <linux/of_platform.h>
  67 #include "dwc_otg_attr.h"
  68 #include "dwc_otg_driver.h"
  69 #include "dwc_otg_cil.h"
  70 #include "dwc_otg_pcd.h"
  71 #include "dwc_otg_hcd.h"
  72
  73 #include "usbdev_rk.h"
  74 //#define DWC_DRIVER_VERSION    "2.60a 22-NOV-2006"
  75 //#define DWC_DRIVER_VERSION    "2.70 2009-12-31"
  76 #define DWC_DRIVER_VERSION      "3.00 2010-12-12 rockchip"
  77
  78 #define DWC_DRIVER_DESC         "HS OTG USB Controller driver"
  79
  80 static const char dwc_driver_name[] = "usb20_otg";
  81
  82 dwc_otg_device_t* g_otgdev = NULL;
  83
  84 extern struct dwc_otg_platform_data usb20otg_pdata;
  85 extern struct dwc_otg_platform_data usb20host_pdata;
  86 /*-------------------------------------------------------------------------*/
  87 /* Encapsulate the module parameter settings */
  88
  89 static dwc_otg_core_params_t dwc_otg_module_params = {
  90         .opt = -1,
  91         .otg_cap = -1,
  92         .dma_enable = -1,
  93         .dma_burst_size = -1,
  94         .speed = -1,
  95         .host_support_fs_ls_low_power = -1,
  96         .host_ls_low_power_phy_clk = -1,
  97         .enable_dynamic_fifo = -1,
  98         .data_fifo_size = -1,
  99         .dev_rx_fifo_size = -1,
 100         .dev_nperio_tx_fifo_size = -1,
 101         .dev_perio_tx_fifo_size =
 102         {       /* dev_perio_tx_fifo_size_1 */
 103                         -1,
 104                         -1,
 105                         -1,
 106                         -1,
 107                         -1,
 108                         -1,
 109                         -1,
 110                         -1,
 111                         -1,
 112                         -1,
 113                         -1,
 114                         -1,
 115                         -1,
 116                         -1,
 117                         -1
 118         },      /* 15 */
 119         .host_rx_fifo_size = -1,
 120         .host_nperio_tx_fifo_size = -1,
 121         //.host_perio_tx_fifo_size = 512,
 122         .host_perio_tx_fifo_size = -1,
 123         .max_transfer_size = -1,
 124         .max_packet_count = -1,
 125         .host_channels = -1,
 126         .dev_endpoints = -1,
 127         .phy_type = -1,
 128         .phy_utmi_width = -1,
 129         .phy_ulpi_ddr = -1,
 130         .phy_ulpi_ext_vbus = -1,
 131         .i2c_enable = -1,
 132         .ulpi_fs_ls = -1,
 133         .ts_dline = -1,
 134         .en_multiple_tx_fifo = -1,
 135         .dev_tx_fifo_size =
 136         {       /* dev_tx_fifo_size */
 137                         -1,
 138                         -1,
 139                         -1,
 140                         -1,
 141                         -1,
 142                         -1,
 143                         -1,
 144                         -1,
 145                         -1,
 146                         -1,
 147                         -1,
 148                         -1,
 149                         -1,
 150                         -1,
 151                         -1
 152         },      /* 15 */
 153         .thr_ctl = -1,
 154         .tx_thr_length = -1,
 155         .rx_thr_length = -1,
 156 };
 157
 158 #ifdef CONFIG_USB11_HOST
 159
 160 dwc_otg_device_t* g_host11 = NULL;
 161
 162 static dwc_otg_core_params_t host11_module_params = {
 163         .opt = -1,
 164         .otg_cap = -1,
 165         .dma_enable = -1,
 166         .dma_burst_size = -1,
 167         .speed = -1,
 168         .host_support_fs_ls_low_power = 1,
 169         .host_ls_low_power_phy_clk = -1,
 170         .enable_dynamic_fifo = -1,
 171         .data_fifo_size = -1,
 172         .dev_rx_fifo_size = -1,
 173         .dev_nperio_tx_fifo_size = -1,
 174         .dev_perio_tx_fifo_size =
 175         {       /* dev_perio_tx_fifo_size_1 */
 176                         -1,
 177                         -1,
 178                         -1,
 179                         -1,
 180                         -1,
 181                         -1,
 182                         -1,
 183                         -1,
 184                         -1,
 185                         -1,
 186                         -1,
 187                         -1,
 188                         -1,
 189                         -1,
 190                         -1
 191         },      /* 15 */
 192         .host_rx_fifo_size = -1,
 193         .host_nperio_tx_fifo_size = -1,
 194         //.host_perio_tx_fifo_size = 512,
 195         .host_perio_tx_fifo_size = -1,
 196         .max_transfer_size = -1,
 197         .max_packet_count = -1,
 198         .host_channels = -1,
 199         .dev_endpoints = -1,
 200         .phy_type = -1,
 201         .phy_utmi_width = -1,
 202         .phy_ulpi_ddr = -1,
 203         .phy_ulpi_ext_vbus = -1,
 204         .i2c_enable = -1,
 205         .ulpi_fs_ls = -1,
 206         .ts_dline = -1,
 207         .en_multiple_tx_fifo = -1,
 208         .dev_tx_fifo_size =
 209         {       /* dev_tx_fifo_size */
 210                         -1,
 211                         -1,
 212                         -1,
 213                         -1,
 214                         -1,
 215                         -1,
 216                         -1,
 217                         -1,
 218                         -1,
 219                         -1,
 220                         -1,
 221                         -1,
 222                         -1,
 223                         -1,
 224                         -1
 225         },      /* 15 */
 226         .thr_ctl = -1,
 227         .tx_thr_length = -1,
 228         .rx_thr_length = -1,
 229 };
 230 #endif
 231
 232 #ifdef CONFIG_USB20_HOST
 233 dwc_otg_device_t* g_host20 = NULL;
 234
 235 static dwc_otg_core_params_t host20_module_params = {
 236         .opt = -1,
 237         .otg_cap = -1,
 238         .dma_enable = -1,
 239         .dma_burst_size = -1,
 240         .speed = -1,
 241         .host_support_fs_ls_low_power = -1,
 242         .host_ls_low_power_phy_clk = -1,
 243         .enable_dynamic_fifo = -1,
 244         .data_fifo_size = -1,
 245         .dev_rx_fifo_size = -1,
 246         .dev_nperio_tx_fifo_size = -1,
 247         .dev_perio_tx_fifo_size =
 248         {       /* dev_perio_tx_fifo_size_1 */
 249                         -1,
 250                         -1,
 251                         -1,
 252                         -1,
 253                         -1,
 254                         -1,
 255                         -1,
 256                         -1,
 257                         -1,
 258                         -1,
 259                         -1,
 260                         -1,
 261                         -1,
 262                         -1,
 263                         -1
 264         },      /* 15 */
 265         .host_rx_fifo_size = -1,
 266         .host_nperio_tx_fifo_size = -1,
 267         //.host_perio_tx_fifo_size = 512,
 268         .host_perio_tx_fifo_size = -1,
 269         .max_transfer_size = -1,
 270         .max_packet_count = -1,
 271         .host_channels = -1,
 272         .dev_endpoints = -1,
 273         .phy_type = -1,
 274         .phy_utmi_width = -1,
 275         .phy_ulpi_ddr = -1,
 276         .phy_ulpi_ext_vbus = -1,
 277         .i2c_enable = -1,
 278         .ulpi_fs_ls = -1,
 279         .ts_dline = -1,
 280         .en_multiple_tx_fifo = -1,
 281         .dev_tx_fifo_size =
 282         {       /* dev_tx_fifo_size */
 283                         -1,
 284                         -1,
 285                         -1,
 286                         -1,
 287                         -1,
 288                         -1,
 289                         -1,
 290                         -1,
 291                         -1,
 292                         -1,
 293                         -1,
 294                         -1,
 295                         -1,
 296                         -1,
 297                         -1
 298         },      /* 15 */
 299         .thr_ctl = -1,
 300         .tx_thr_length = -1,
 301         .rx_thr_length = -1,
 302 };
 303 #endif
 304
 305 /**
 306  * This function shows the Driver Version.
 307  */
 308 static ssize_t version_show(struct device_driver *dev, char *buf)
 309 {
 310         return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n",
 311                 DWC_DRIVER_VERSION);
 312 }
 313 static DRIVER_ATTR(version, S_IRUGO, version_show, NULL);
 314
 315 /**
 316  * Global Debug Level Mask.
 317  */
 318 uint32_t g_dbg_lvl = DBG_OFF;//0xFFFF;//DBG_CIL|DBG_CILV|DBG_PCDV|DBG_HCDV|DBG_HCD|DBG_HCD_URB; /* OFF */
 319
 320 /**
 321  * This function shows the driver Debug Level.
 322  */
 323 static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf)
 324 {
 325         return sprintf(_buf, "0x%0x\n", g_dbg_lvl);
 326 }
 327 /**
 328  * This function stores the driver Debug Level.
 329  */
 330 static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf,
 331                                                            size_t _count)
 332 {
 333         g_dbg_lvl = simple_strtoul(_buf, NULL, 16);
 334                 return _count;
 335 }
 336 static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store);
 337 #ifdef CONFIG_USB
 338
 339 extern struct usb_hub *g_dwc_otg_root_hub20;
 340 #ifdef DWC_BOTH_HOST_SLAVE
 341 extern void hcd_start( dwc_otg_core_if_t *_core_if );
 342
 343 extern void dwc_otg_hub_disconnect_device(struct usb_hub *hub);
 344
 345 static ssize_t force_usb_mode_show(struct device_driver *_drv, char *_buf)
 346 {
 347     dwc_otg_device_t *otg_dev = g_otgdev;
 348     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 349
 350     return sprintf (_buf, "%d\n", core_if->usb_mode);
 351 }
 352
 353 void dwc_otg_force_host(dwc_otg_core_if_t *core_if)
 354 {
 355     dwc_otg_device_t *otg_dev = g_otgdev;
 356     dctl_data_t dctl = {.d32=0};
 357         struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 358     if(core_if->op_state == A_HOST)
 359     {
 360         printk("dwc_otg_force_host,already in A_HOST mode,everest\n");
 361         return;
 362     }
 363     del_timer(&otg_dev->pcd->check_vbus_timer);
 364     // force disconnect
 365     /* soft disconnect */
 366     dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
 367     dctl.b.sftdiscon = 1;
 368     dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
 369
 370     if (core_if->pcd_cb && core_if->pcd_cb->stop ) {
 371             core_if->pcd_cb->stop( core_if->pcd_cb->p );
 372     }
 373
 374     //core_if->op_state = A_HOST;
 375     /*
 376      * Initialize the Core for Host mode.
 377      */
 378         dwc_otg_core_init(core_if);
 379         dwc_otg_enable_global_interrupts(core_if);
 380     hcd_start( core_if );
 381
 382 }
 383 void dwc_otg_force_device(dwc_otg_core_if_t *core_if)
 384 {
 385     dwc_otg_device_t *otg_dev = g_otgdev;
 386     dwc_otg_disable_global_interrupts( core_if );
 387     if (core_if->hcd_cb && core_if->hcd_cb->stop) {
 388         core_if->hcd_cb->stop( core_if->hcd_cb->p );
 389     }
 390     if(core_if->op_state == B_PERIPHERAL)
 391     {
 392         printk("dwc_otg_force_device,already in B_PERIPHERAL,everest\n");
 393         return;
 394     }
 395     dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20);
 396     otg_dev->core_if->op_state = B_PERIPHERAL;
 397         /* Reset the Controller */
 398         dwc_otg_core_reset( core_if );
 399     otg_dev->pcd->vbus_status = 0;
 400     dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 401
 402 }
 403 static void dwc_otg_set_gusbcfg(dwc_otg_core_if_t *core_if, int mode)
 404 {
 405         gusbcfg_data_t usbcfg = { .d32 = 0 };
 406
 407     usbcfg.d32 = dwc_read_reg32( &core_if->core_global_regs->gusbcfg);
 408     switch(mode)
 409     {
 410     case USB_MODE_FORCE_HOST:
 411         usbcfg.b.force_hst_mode = 1;
 412         usbcfg.b.force_dev_mode = 0;
 413         break;
 414     case USB_MODE_FORCE_DEVICE:
 415         usbcfg.b.force_hst_mode = 0;
 416         usbcfg.b.force_dev_mode = 1;
 417         break;
 418     case USB_MODE_NORMAL:
 419         usbcfg.b.force_hst_mode = 0;
 420         usbcfg.b.force_dev_mode = 0;
 421         break;
 422     }
 423     dwc_write_reg32( &core_if->core_global_regs->gusbcfg, usbcfg.d32 );
 424 }
 425
 426 static ssize_t force_usb_mode_store(struct device_driver *_drv, const char *_buf,
 427                           size_t _count )
 428 {
 429     int new_mode = simple_strtoul(_buf, NULL, 16);
 430     dwc_otg_device_t *otg_dev = g_otgdev;
 431     dwc_otg_core_if_t *core_if = otg_dev->core_if;
 432         struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 433     DWC_PRINT("%s %d->%d\n",__func__, core_if->usb_mode, new_mode);
 434     if(core_if->usb_mode == new_mode)
 435     {
 436         return _count;
 437     }
 438
 439     if(pldata->phy_status==USB_PHY_SUSPEND){
 440         pldata->clock_enable(pldata, 1);
 441         pldata->phy_suspend(pldata,USB_PHY_ENABLED);
 442     }
 443
 444         switch(new_mode)
 445         {
 446                 case USB_MODE_FORCE_HOST:
 447                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 448                         {/* device-->host */
 449                                 core_if->usb_mode = new_mode;
 450                                 dwc_otg_force_host(core_if);
 451                         }
 452                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 453                         {
 454                                 core_if->usb_mode = new_mode;
 455                                 if(dwc_otg_is_host_mode(core_if))
 456                                 {
 457                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 458                                 }
 459                                 else
 460                                 {
 461                                         dwc_otg_force_host(core_if);
 462                                 }
 463                         }
 464                         else
 465                             core_if->usb_mode = new_mode;
 466                         break;
 467                 case USB_MODE_FORCE_DEVICE:
 468                         if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 469                         {
 470                                 core_if->usb_mode = new_mode;
 471                                 dwc_otg_force_device(core_if);
 472                         }
 473                         else if(USB_MODE_NORMAL == core_if->usb_mode)
 474                         {
 475                                 core_if->usb_mode = new_mode;
 476                                 if(dwc_otg_is_device_mode(core_if))
 477                                 {
 478                                         dwc_otg_set_gusbcfg(core_if, new_mode);
 479                                 }
 480                                 else
 481                                 {
 482                                         dwc_otg_force_device(core_if);
 483                                 }
 484                         }
 485                         break;
 486                 case USB_MODE_NORMAL:
 487                         #if 1
 488                         if(USB_MODE_FORCE_DEVICE == core_if->usb_mode)
 489                         {
 490                                 core_if->usb_mode = new_mode;
 491                                 del_timer(&otg_dev->pcd->check_vbus_timer);
 492                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 493                                 msleep(50);
 494                                 if(dwc_otg_is_host_mode(core_if))
 495                                 {
 496                                         dwc_otg_force_host(core_if);
 497                                 }
 498                                 else
 499                                 {
 500                                         dwc_otg_pcd_start_vbus_timer( otg_dev->pcd );
 501                                 }
 502                                 //mdelay(10);
 503                                 //core_if->usb_mode = new_mode;
 504                                 //if(!dwc_otg_connid(core_if))
 505                                 //      dwc_otg_force_host(core_if);
 506                         }
 507                         else if(USB_MODE_FORCE_HOST == core_if->usb_mode)
 508                         {
 509                                 core_if->usb_mode = new_mode;
 510                                 dwc_otg_set_gusbcfg(core_if, new_mode);
 511                                 msleep(100);
 512                                 if(dwc_otg_is_device_mode(core_if))
 513                                 {
 514                                         dwc_otg_force_device(core_if);
 515                                 }
 516                                 //if(dwc_otg_connid(core_if))
 517                                 //      dwc_otg_hub_disconnect_device(g_dwc_otg_root_hub20);
 518                                 //core_if->usb_mode = new_mode;
 519                                 //      dwc_otg_force_device(core_if);
 520                         }
 521                         #endif
 522                         break;
 523                 default:
 524                         break;
 525         }
 526         return _count;
 527 }
 528 static DRIVER_ATTR(force_usb_mode, 0666/*S_IRUGO|S_IWUSR*/, force_usb_mode_show, force_usb_mode_store);
 529 #endif
 530 static ssize_t dwc_otg_enable_show( struct device *_dev,
 531                                                                 struct device_attribute *attr, char *buf)
 532 {
 533     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
 534     return sprintf (buf, "%d\n", otg_dev->hcd->host_enabled);
 535 }
 536
 537 static ssize_t dwc_otg_enable_store( struct device *_dev,
 538                                                                 struct device_attribute *attr,
 539                                                                 const char *buf, size_t count )
 540 {
 541     dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)_dev->platform_data));
 542     dwc_otg_core_if_t *_core_if = otg_dev->core_if;
 543     struct platform_device *pdev = to_platform_device(_dev);
 544         uint32_t val = simple_strtoul(buf, NULL, 16);
 545         struct dwc_otg_platform_data *pldata = _dev->platform_data;
 546         if(otg_dev->hcd->host_enabled == val)
 547             return count;
 548
 549         otg_dev->hcd->host_enabled = val;
 550         if(val == 0)    // enable -> disable
 551         {
 552             DWC_PRINT("disable host controller:%s,id:%d\n",pdev->name,pdev->id);
 553             #if 1
 554         if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) {
 555                 _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p );
 556         }
 557         #endif
 558         if (_core_if->hcd_cb && _core_if->hcd_cb->stop) {
 559                 _core_if->hcd_cb->stop( _core_if->hcd_cb->p );
 560         }
 561         if(pldata->phy_status==USB_PHY_ENABLED){
 562             pldata->phy_suspend(pldata,USB_PHY_SUSPEND);
 563             udelay(3);
 564             pldata->clock_enable(pldata, 0);
 565         }
 566         }
 567         else if(val == 1)
 568         {
 569             DWC_PRINT("enable host controller:%s\n",pdev->name);
 570         if( pldata->phy_status == USB_PHY_SUSPEND ){
 571             pldata->clock_enable( pldata, 1);
 572             pldata->phy_suspend(pldata, USB_PHY_ENABLED);
 573         }
 574         mdelay(5);
 575         if (_core_if->hcd_cb && _core_if->hcd_cb->start) {
 576                 _core_if->hcd_cb->start( _core_if->hcd_cb->p );
 577         }
 578         }
 579
 580     return count;
 581 }
 582 static DEVICE_ATTR(enable, S_IRUGO|S_IWUSR, dwc_otg_enable_show, dwc_otg_enable_store);
 583 #endif
 584 static ssize_t dwc_otg_conn_en_show(struct device_driver *_drv, char *_buf)
 585 {
 586 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 587     dwc_otg_device_t *otg_dev = g_otgdev;
 588     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 589     return sprintf (_buf, "%d\n", _pcd->conn_en);
 590 #else
 591     return sprintf(_buf, "0\n");
 592 #endif
 593 }
 594
 595 static ssize_t dwc_otg_conn_en_store(struct device_driver *_drv, const char *_buf,
 596                                      size_t _count)
 597 {
 598 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 599     int enable = simple_strtoul(_buf, NULL, 10);
 600     dwc_otg_device_t *otg_dev = g_otgdev;
 601     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 602     DWC_PRINT("%s %d->%d\n",__func__, _pcd->conn_en, enable);
 603
 604     _pcd->conn_en = enable;
 605 #endif
 606     return _count;
 607 }
 608 static DRIVER_ATTR(dwc_otg_conn_en, S_IRUGO|S_IWUSR, dwc_otg_conn_en_show, dwc_otg_conn_en_store);
 609
 610 #ifdef CONFIG_RK_USB_UART
 611
 612 extern int get_gadget_connect_flag(void);
 613 extern int dwc_vbus_status(void);
 614
 615 /*
 616
 617 write 1 to /sys/bus/platform/drivers/usb20_otg/dwc_otg_force_uart
 618 can stop check_vbus_timer and force usb_phy bypass to uart mode
 619
 620 write 0 comes back to normal usb operate mode
 621
 622 */
 623 static ssize_t dwc_otg_force_uart_store(struct device_driver *_drv, const char *_buf,
 624                                      size_t _count)
 625 {
 626     int enable = simple_strtoul(_buf, NULL, 10);
 627     dwc_otg_device_t *otg_dev = g_otgdev;
 628     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 629     struct dwc_otg_platform_data *pldata = otg_dev->pldata;
 630
 631     if(1 == enable)
 632     {
 633         if(!get_gadget_connect_flag() &&
 634             dwc_otg_is_device_mode(otg_dev->core_if))
 635         {
 636             disable_irq(IRQ_OTG_BVALID);
 637             del_timer(&_pcd->check_vbus_timer);
 638             pldata->phy_suspend(pldata,USB_PHY_SUSPEND);
 639             pldata->dwc_otg_uart_mode(pldata,PHY_UART_MODE);
 640             _pcd->vbus_status = 2;
 641         }
 642         else
 643             printk("mode mismatch!\n");
 644     }
 645
 646     if(0 == enable)
 647     {
 648         _pcd->vbus_status == 0;
 649         _pcd->vbus_status = 0;
 650         pldata->dwc_otg_uart_mode(pldata,PHY_USB_MODE);
 651         dwc_otg_pcd_start_vbus_timer(_pcd);
 652         enable_irq(IRQ_OTG_BVALID);
 653     }
 654     return _count;
 655 }
 656 static DRIVER_ATTR(dwc_otg_force_uart, S_IRUGO|S_IWUSR, NULL, dwc_otg_force_uart_store);
 657 #endif
 658 #ifndef CONFIG_DWC_OTG_HOST_ONLY
 659 static ssize_t vbus_status_show(struct device_driver *_drv, char *_buf)
 660 {
 661     dwc_otg_device_t *otg_dev = g_otgdev;
 662     dwc_otg_pcd_t *_pcd = otg_dev->pcd;
 663     return sprintf (_buf, "%d\n", _pcd->vbus_status);
 664 }
 665 static DRIVER_ATTR(vbus_status, S_IRUGO|S_IWUSR, vbus_status_show, NULL);
 666 #endif
 667 volatile depctl_data_t depctl_ep0 = {.d32 = 0};
 668 volatile depctl_data_t depctl_ep2 = {.d32 = 0};
 669 volatile depctl_data_t depctl_ep4 = {.d32 = 0};
 670 void dwc_otg_epout_save(void)
 671 {
 672     dwc_otg_device_t *otg_dev = g_otgdev;
 673         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 674     volatile depctl_data_t depctl = {.d32 = 0};
 675     volatile grstctl_t grstctl = {.d32 = 0};
 676     grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 677
 678     while(grstctl.b.ahbidle != 1)
 679     {
 680         grstctl.d32 = dwc_read_reg32(&otg_dev->core_if->core_global_regs->grstctl);
 681     }
 682     depctl_ep0.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl);
 683     depctl.d32 = depctl_ep0.d32;
 684     if(depctl.b.epena)
 685     {
 686         depctl.b.epena = 0;
 687         dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl.d32);
 688     }
 689     depctl_ep2.d32 = dwc_read_reg32(&dev_if->out_ep_regs[2]->doepctl);
 690     depctl.d32 = depctl_ep2.d32;
 691     if(depctl.b.epena)
 692     {
 693         depctl.b.epena = 0;
 694         dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl.d32);
 695     }
 696     depctl_ep4.d32 = dwc_read_reg32(&dev_if->out_ep_regs[4]->doepctl);
 697     depctl.d32 = depctl_ep4.d32;
 698     if(depctl.b.epena)
 699     {
 700         depctl.b.epena = 0;
 701         dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl.d32);
 702     }
 703 }
 704 void dwc_otg_epout_restore(void)
 705 {
 706     dwc_otg_device_t *otg_dev = g_otgdev;
 707         dwc_otg_dev_if_t *dev_if = otg_dev->core_if->dev_if;
 708     dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, depctl_ep0.d32);
 709     dwc_write_reg32(&dev_if->out_ep_regs[2]->doepctl, depctl_ep2.d32);
 710     dwc_write_reg32(&dev_if->out_ep_regs[4]->doepctl, depctl_ep4.d32);
 711 }
 712
 713 /**
 714  * This function is called during module intialization to verify that
 715  * the module parameters are in a valid state.
 716  */
 717 static int check_parameters(dwc_otg_core_if_t *core_if)
 718 {
 719         int i;
 720         int retval = 0;
 721         dwc_otg_core_params_t      *core_params;
 722         core_params = core_if->core_params;
 723 /* Checks if the parameter is outside of its valid range of values */
 724 #define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \
 725                 ((core_params->_param_ < (_low_)) || \
 726                 (core_params->_param_ > (_high_)))
 727
 728 /* If the parameter has been set by the user, check that the parameter value is
 729  * within the value range of values.  If not, report a module error. */
 730 #define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \
 731                 do { \
 732                         if (core_params->_param_ != -1) { \
 733                                 if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \
 734                                         DWC_ERROR("`%d' invalid for parameter `%s'\n", \
 735                                                 core_params->_param_, _string_); \
 736                                         core_params->_param_ = dwc_param_##_param_##_default; \
 737                                         retval ++; \
 738                                 } \
 739                         } \
 740                 } while (0)
 741
 742         DWC_OTG_PARAM_ERR(opt,0,1,"opt");
 743         DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap");
 744         DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable");
 745         DWC_OTG_PARAM_ERR(speed,0,1,"speed");
 746         DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power");
 747         DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk");
 748         DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo");
 749         DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size");
 750         DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size");
 751         DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size");
 752         DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size");
 753         DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size");
 754         DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size");
 755         DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size");
 756         DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count");
 757         DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels");
 758         DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints");
 759         DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type");
 760         DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr");
 761         DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus");
 762         DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable");
 763         DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls");
 764         DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline");
 765
 766         if (core_params->dma_burst_size != -1)
 767         {
 768                 if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) &&
 769                         DWC_OTG_PARAM_TEST(dma_burst_size,4,4) &&
 770                         DWC_OTG_PARAM_TEST(dma_burst_size,8,8) &&
 771                         DWC_OTG_PARAM_TEST(dma_burst_size,16,16) &&
 772                         DWC_OTG_PARAM_TEST(dma_burst_size,32,32) &&
 773                         DWC_OTG_PARAM_TEST(dma_burst_size,64,64) &&
 774                         DWC_OTG_PARAM_TEST(dma_burst_size,128,128) &&
 775                         DWC_OTG_PARAM_TEST(dma_burst_size,256,256))
 776                 {
 777                         DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n",
 778                                   core_params->dma_burst_size);
 779                         core_params->dma_burst_size = 32;
 780                         retval ++;
 781                 }
 782         }
 783
 784         if (core_params->phy_utmi_width != -1)
 785         {
 786                 if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) &&
 787                         DWC_OTG_PARAM_TEST(phy_utmi_width,16,16))
 788                 {
 789                         DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n",
 790                                   core_params->phy_utmi_width);
 791                         core_params->phy_utmi_width = 16;
 792                         retval ++;
 793                 }
 794         }
 795
 796         for (i=0; i<15; i++)
 797         {
 798                 /** @todo should be like above */
 799                 //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size");
 800                 if (core_params->dev_perio_tx_fifo_size[i] != -1)
 801                 {
 802                         if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768))
 803                         {
 804                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 805                                           core_params->dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i);
 806                                 core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
 807                                 retval ++;
 808                         }
 809                 }
 810         }
 811
 812         DWC_OTG_PARAM_ERR(en_multiple_tx_fifo,0,1,"en_multiple_tx_fifo");
 813
 814         for (i=0; i<15; i++)
 815         {
 816                 /** @todo should be like above */
 817                 //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size");
 818                 if (core_params->dev_tx_fifo_size[i] != -1)
 819                 {
 820                         if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i],4,768))
 821                         {
 822                                 DWC_ERROR("`%d' invalid for parameter `%s_%d'\n",
 823                                           core_params->dev_tx_fifo_size[i], "dev_tx_fifo_size", i);
 824                                 core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
 825                                 retval ++;
 826                         }
 827                 }
 828         }
 829
 830         DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl");
 831         DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length");
 832         DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length");
 833
 834
 835         /* At this point, all module parameters that have been set by the user
 836          * are valid, and those that have not are left unset.  Now set their
 837          * default values and/or check the parameters against the hardware
 838          * configurations of the OTG core. */
 839
 840
 841
 842 /* This sets the parameter to the default value if it has not been set by the
 843  * user */
 844 #define DWC_OTG_PARAM_SET_DEFAULT(_param_) \
 845         ({ \
 846                 int changed = 1; \
 847                 if (core_params->_param_ == -1) { \
 848                         changed = 0; \
 849                         core_params->_param_ = dwc_param_##_param_##_default; \
 850                 } \
 851                 changed; \
 852         })
 853
 854 /* This checks the macro agains the hardware configuration to see if it is
 855  * valid.  It is possible that the default value could be invalid.      In this
 856  * case, it will report a module error if the user touched the parameter.
 857  * Otherwise it will adjust the value without any error. */
 858 #define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \
 859         ({ \
 860                         int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \
 861                 int error = 0; \
 862                 if (!(_is_valid_)) { \
 863                         if (changed) { \
 864                                 DWC_ERROR("`%d' invalid for parameter `%s'.      Check HW configuration.\n", core_params->_param_,_str_); \
 865                                 error = 1; \
 866                         } \
 867                         core_params->_param_ = (_set_valid_); \
 868                 } \
 869                 error; \
 870         })
 871
 872         /* OTG Cap */
 873         retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap",
 874                                   ({
 875                                           int valid;
 876                                           valid = 1;
 877                                           switch (core_params->otg_cap) {
 878                                           case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE:
 879                                                   if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0;
 880                                                   break;
 881                                           case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE:
 882                                                   if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) &&
 883                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) &&
 884                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) &&
 885                                                           (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST))
 886                                                   {
 887                                                           valid = 0;
 888                                                   }
 889                                                   break;
 890                                           case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE:
 891                                                   /* always valid */
 892                                                   break;
 893                                           }
 894                                           valid;
 895                           }),
 896                                         (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) ||
 897                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) ||
 898                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
 899                                         (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ?
 900                                         DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE :
 901                                         DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE));
 902
 903         retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable",
 904                                 ((core_params->dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1,
 905                                 0);
 906
 907         retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt",
 908                                 1,
 909                                 0);
 910
 911         DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size);
 912
 913         retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power,
 914                                 "host_support_fs_ls_low_power",
 915                                 1, 0);
 916
 917         retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo,
 918                                         "enable_dynamic_fifo",
 919                                         ((core_params->enable_dynamic_fifo == 0) ||
 920                                         (core_if->hwcfg2.b.dynamic_fifo == 1)), 0);
 921
 922
 923         retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size,
 924                                         "data_fifo_size",
 925                                         (core_params->data_fifo_size <= core_if->hwcfg3.b.dfifo_depth),
 926                                         core_if->hwcfg3.b.dfifo_depth);
 927
 928         retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size,
 929                                         "dev_rx_fifo_size",
 930                                         (core_params->dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 931                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 932
 933         retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size,
 934                                         "dev_nperio_tx_fifo_size",
 935                                         (core_params->dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 936                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 937
 938         retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size,
 939                                         "host_rx_fifo_size",
 940                                         (core_params->host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)),
 941                                         dwc_read_reg32(&core_if->core_global_regs->grxfsiz));
 942
 943
 944         retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size,
 945                                         "host_nperio_tx_fifo_size",
 946                                         (core_params->host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)),
 947                                         (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16));
 948         retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size,
 949                                         "host_perio_tx_fifo_size",
 950                                         (core_params->host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))),
 951                                         ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16)));
 952
 953         retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size,
 954                                         "max_transfer_size",
 955                                         (core_params->max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))),
 956                                         ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1));
 957
 958         retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count,
 959                                         "max_packet_count",
 960                                         (core_params->max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))),
 961                                         ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1));
 962
 963         retval += DWC_OTG_PARAM_CHECK_VALID(host_channels,
 964                                         "host_channels",
 965                                         (core_params->host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)),
 966                                         (core_if->hwcfg2.b.num_host_chan + 1));
 967
 968         retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints,
 969                                         "dev_endpoints",
 970                                         (core_params->dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)),
 971                                         core_if->hwcfg2.b.num_dev_ep);
 972
 973 /*
 974  * Define the following to disable the FS PHY Hardware checking.  This is for
 975  * internal testing only.
 976  *
 977  * #define NO_FS_PHY_HW_CHECKS
 978  */
 979
 980 #ifdef NO_FS_PHY_HW_CHECKS
 981         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 982                                 "phy_type", 1, 0);
 983 #else
 984         retval += DWC_OTG_PARAM_CHECK_VALID(phy_type,
 985                                 "phy_type",
 986                                 ({
 987                                         int valid = 0;
 988                                         if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_UTMI) &&
 989                                         ((core_if->hwcfg2.b.hs_phy_type == 1) ||
 990                                          (core_if->hwcfg2.b.hs_phy_type == 3)))
 991                                         {
 992                                                 valid = 1;
 993                                         }
 994                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_ULPI) &&
 995                                                  ((core_if->hwcfg2.b.hs_phy_type == 2) ||
 996                                                   (core_if->hwcfg2.b.hs_phy_type == 3)))
 997                                         {
 998                                                 valid = 1;
 999                                         }
1000                                         else if ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) &&
1001                                                  (core_if->hwcfg2.b.fs_phy_type == 1))
1002                                         {
1003                                                 valid = 1;
1004                                         }
1005                                         valid;
1006                                 }),
1007                                 ({
1008                                         int set = DWC_PHY_TYPE_PARAM_FS;
1009                                         if (core_if->hwcfg2.b.hs_phy_type) {
1010                                                 if ((core_if->hwcfg2.b.hs_phy_type == 3) ||
1011                                                 (core_if->hwcfg2.b.hs_phy_type == 1)) {
1012                                                         set = DWC_PHY_TYPE_PARAM_UTMI;
1013                                                 }
1014                                                 else {
1015                                                         set = DWC_PHY_TYPE_PARAM_ULPI;
1016                                                 }
1017                                         }
1018                                         set;
1019                                 }));
1020 #endif
1021
1022         retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed",
1023                                 (core_params->speed == 0) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1,
1024                                 core_params->phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0);
1025
1026         retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk,
1027                                 "host_ls_low_power_phy_clk",
1028                                 ((core_params->host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1),
1029                                 ((core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ));
1030
1031         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr);
1032         DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus);
1033         DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width);
1034         DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls);
1035         DWC_OTG_PARAM_SET_DEFAULT(ts_dline);
1036
1037 #ifdef NO_FS_PHY_HW_CHECKS
1038         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1039                                 "i2c_enable", 1, 0);
1040 #else
1041         retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable,
1042                                 "i2c_enable",
1043                                 (core_params->i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1,
1044                                 0);
1045 #endif
1046
1047         for (i=0; i<15; i++)
1048         {
1049                 int changed = 1;
1050                 int error = 0;
1051
1052                 if (core_params->dev_perio_tx_fifo_size[i] == -1)
1053                 {
1054                         changed = 0;
1055                         core_params->dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default;
1056                 }
1057                 if (!(core_params->dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1058                 {
1059                         if (changed)
1060                         {
1061                                 DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_perio_tx_fifo_size[i],i);
1062                                 error = 1;
1063                         }
1064                         core_params->dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1065                 }
1066                 retval += error;
1067         }
1068
1069
1070         retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo,"en_multiple_tx_fifo",
1071                                                 ((core_params->en_multiple_tx_fifo == 1) && (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1,
1072                                                 0);
1073
1074
1075         for (i=0; i<15; i++)
1076         {
1077
1078                 int changed = 1;
1079                 int error = 0;
1080
1081                 if (core_params->dev_tx_fifo_size[i] == -1)
1082                 {
1083                         changed = 0;
1084                         core_params->dev_tx_fifo_size[i] = dwc_param_dev_tx_fifo_size_default;
1085                 }
1086                 if (!(core_params->dev_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]))))
1087                 {
1088                         if (changed)
1089                         {
1090                                 DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'.  Check HW configuration.\n", core_params->dev_tx_fifo_size[i],i);
1091                                 error = 1;
1092                         }
1093                         core_params->dev_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]);
1094                 }
1095                 retval += error;
1096
1097
1098         }
1099
1100         DWC_OTG_PARAM_SET_DEFAULT(thr_ctl);
1101         DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length);
1102         DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length);
1103
1104         return retval;
1105 }
1106 /**
1107  * This function is the top level interrupt handler for the Common
1108  * (Device and host modes) interrupts.
1109  */
1110 static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev)
1111 {
1112         dwc_otg_device_t *otg_dev = _dev;
1113         int32_t retval = IRQ_NONE;
1114
1115         retval = dwc_otg_handle_common_intr( otg_dev->core_if );
1116         return IRQ_RETVAL(retval);
1117 }
1118
1119 #ifdef CONFIG_USB20_OTG
1120 /**
1121  * This function is called when a lm_device is unregistered with the
1122  * dwc_otg_driver. This happens, for example, when the rmmod command is
1123  * executed. The device may or may not be electrically present. If it is
1124  * present, the driver stops device processing. Any resources used on behalf
1125  * of this device are freed.
1126  *
1127  * @param[in] pdev
1128  */
1129 static int dwc_otg_driver_remove(struct platform_device *pdev)
1130 {
1131         struct device *dev = &pdev->dev;
1132         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1133         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1134
1135         if (otg_dev == NULL)
1136         {
1137                 /* Memory allocation for the dwc_otg_device failed. */
1138                 return 0;
1139         }
1140
1141         /*
1142          * Free the IRQ
1143          */
1144         if (otg_dev->common_irq_installed)
1145         {
1146                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1147         }
1148
1149 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1150         if (otg_dev->hcd != NULL)
1151         {
1152                 dwc_otg_hcd_remove(dev);
1153         }
1154 #endif
1155
1156 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1157         if (otg_dev->pcd != NULL)
1158         {
1159                 dwc_otg_pcd_remove(dev);
1160         }
1161 #endif
1162         if (otg_dev->core_if != NULL)
1163         {
1164                 dwc_otg_cil_remove( otg_dev->core_if );
1165         }
1166
1167         /*
1168          * Remove the device attributes
1169          */
1170         dwc_otg_attr_remove(dev);
1171
1172         /*
1173          * Return the memory.
1174          */
1175         if (otg_dev->base != NULL)
1176         {
1177                 iounmap(otg_dev->base);
1178         }
1179         kfree(otg_dev);
1180
1181         /*
1182          * Clear the drvdata pointer.
1183          */
1184 //      dev->platform_data = 0;
1185
1186 #ifdef DWC_BOTH_HOST_SLAVE
1187         dwc_otg_module_params.host_rx_fifo_size = -1;
1188         dwc_otg_module_params.dev_nperio_tx_fifo_size = -1;
1189         dwc_otg_module_params.host_nperio_tx_fifo_size = -1;
1190         dwc_otg_module_params.dev_rx_fifo_size = -1;
1191 #endif
1192         return 0;
1193 }
1194
1195 /**
1196  * This function is called when an lm_device is bound to a
1197  * dwc_otg_driver. It creates the driver components required to
1198  * control the device (CIL, HCD, and PCD) and it initializes the
1199  * device. The driver components are stored in a dwc_otg_device
1200  * structure. A reference to the dwc_otg_device is saved in the
1201  * lm_device. This allows the driver to access the dwc_otg_device
1202  * structure on subsequent calls to driver methods for this device.
1203  *
1204  * @param[in] pdev  platform_device definition
1205  */
1206 static int dwc_otg_driver_probe(struct platform_device *pdev)
1207 {
1208         struct device_node      *node = pdev->dev.of_node;
1209         int                     retval = 0;
1210         struct resource         *res_base;
1211         struct device           *dev = &pdev->dev;
1212         dwc_otg_device_t        *dwc_otg_device;
1213         int32_t                 snpsid;
1214         int                     irq;
1215         struct                  dwc_otg_platform_data *pldata;
1216
1217         dev->platform_data = &usb20otg_pdata;
1218         pldata =  dev->platform_data;
1219         pldata->dev = dev;
1220
1221         if (!node) {
1222                 dev_err(dev, "device node not found\n");
1223                 return -EINVAL;
1224         }
1225
1226         // clock and hw init
1227         if(pldata->hw_init)
1228                 pldata->hw_init();
1229
1230
1231         if(pldata->clock_init){
1232                 pldata->clock_init(pldata);
1233                 pldata->clock_enable(pldata, 1);
1234         }
1235
1236         if(pldata->phy_suspend)
1237                 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1238
1239         if(pldata->soft_reset)
1240                 pldata->soft_reset();
1241
1242         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1243
1244         if (dwc_otg_device == 0)
1245         {
1246                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1247                 retval = -ENOMEM;
1248                 goto fail;
1249         }
1250
1251         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1252         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1253
1254         /*
1255          * Map the DWC_otg Core memory into virtual address space.
1256          */
1257
1258         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1259         if (!res_base)
1260                 goto fail;
1261
1262         dwc_otg_device->base =  devm_ioremap_resource(dev, res_base);
1263         if (dwc_otg_device->base == NULL)
1264         {
1265                 dev_err(dev, "ioremap() failed\n");
1266                 retval = -ENOMEM;
1267                 goto fail;
1268         }
1269 #if 0
1270         dwc_otg_device->base = (void*)(USB_OTG_BASE_ADDR_VA);
1271
1272         if (dwc_otg_device->base == NULL)
1273         {
1274                 dev_err(dev, "ioremap() failed\n");
1275                 retval = -ENOMEM;
1276                 goto fail;
1277         }
1278 #endif
1279         dev_dbg(dev, "base=0x%08x\n", (unsigned)dwc_otg_device->base);
1280         /*
1281          * Attempt to ensure this device is really a DWC_otg Controller.
1282          * Read and verify the SNPSID register contents. The value should be
1283          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1284          */
1285         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1286         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1287         {
1288                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1289                 retval = -EINVAL;
1290                 goto fail;
1291         }
1292
1293         /*
1294          * Initialize driver data to point to the global DWC_otg
1295          * Device structure.
1296          */
1297     //dev->platform_data = dwc_otg_device;
1298         pldata->privdata =  dwc_otg_device;
1299         dwc_otg_device->pldata = (void *)pldata;
1300
1301         dev_dbg(dev, "dwc_otg_device=0x%p\n", dwc_otg_device);
1302
1303         g_otgdev = dwc_otg_device;
1304
1305         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1306                                                         &dwc_otg_module_params);
1307         if (dwc_otg_device->core_if == 0)
1308         {
1309                 dev_err(dev, "CIL initialization failed!\n");
1310                 retval = -ENOMEM;
1311                 goto fail;
1312         }
1313         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1314         /*
1315          * Validate parameter values.
1316          */
1317         if (check_parameters(dwc_otg_device->core_if) != 0)
1318         {
1319                 retval = -EINVAL;
1320                 goto fail;
1321         }
1322
1323         /*
1324          * Create Device Attributes in sysfs
1325          */
1326         dwc_otg_attr_create(dev);
1327 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1328         retval |= device_create_file(dev, &dev_attr_enable);
1329 #endif
1330
1331         /*
1332          * Disable the global interrupt until all the interrupt
1333          * handlers are installed.
1334          */
1335         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1336         /*
1337          * Install the interrupt handler for the common interrupts before
1338          * enabling common interrupts in core_init below.
1339          */
1340         irq = platform_get_irq(to_platform_device(dev),0);
1341         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1342                          irq);
1343         retval = request_irq(irq, dwc_otg_common_irq,
1344                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1345         if (retval != 0)
1346         {
1347                 DWC_ERROR("request of irq%d failed\n", irq);
1348                 retval = -EBUSY;
1349                 goto fail;
1350         }
1351         else
1352         {
1353                 dwc_otg_device->common_irq_installed = 1;
1354         }
1355
1356 #ifdef CONFIG_MACH_IPMATE
1357         set_irq_type(irq, IRQT_LOW);
1358 #endif
1359
1360 #ifdef CONFIG_DWC_OTG_DEVICE_ONLY
1361         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1362 #else
1363 #ifdef CONFIG_DWC_OTG_HOST_ONLY
1364         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1365 #else
1366
1367 #ifdef CONFIG_DWC_OTG_DEFAULT_HOST
1368         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_HOST;
1369 #else
1370         dwc_otg_device->core_if->usb_mode = USB_MODE_NORMAL;
1371 #ifdef CONFIG_DWC_OTG_DEFAULT_DEVICE
1372         dwc_otg_device->core_if->usb_mode = USB_MODE_FORCE_DEVICE;
1373 #endif
1374 #endif
1375
1376 #endif
1377 #endif
1378
1379         /*
1380          * Initialize the DWC_otg core.
1381          */
1382         dwc_otg_core_init( dwc_otg_device->core_if );
1383
1384 /* Initialize the bus state.  If the core is in Device Mode
1385  * HALT the USB bus and return. */
1386 #ifndef CONFIG_DWC_OTG_DEVICE_ONLY
1387         /*
1388          * Initialize the HCD
1389          */
1390         retval = dwc_otg_hcd_init(dev);
1391         if (retval != 0)
1392         {
1393                 DWC_ERROR("dwc_otg_hcd_init failed\n");
1394                 dwc_otg_device->hcd = NULL;
1395                 goto fail;
1396         }
1397 #endif
1398 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1399         /*
1400          * Initialize the PCD
1401          */
1402         retval = dwc_otg_pcd_init(dev);
1403         if (retval != 0)
1404         {
1405                 DWC_ERROR("dwc_otg_pcd_init failed\n");
1406                 dwc_otg_device->pcd = NULL;
1407                 goto fail;
1408         }
1409 #endif
1410
1411
1412         /*
1413          * Enable the global interrupt after all the interrupt
1414          * handlers are installed.
1415          */
1416         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
1417         return 0;
1418  fail:
1419         devm_kfree(&pdev->dev, dwc_otg_device);
1420         DWC_PRINT("dwc_otg_driver_probe fail,everest\n");
1421         return retval;
1422 }
1423
1424 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1425 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1426 {
1427         struct device *dev = &_dev->dev;
1428         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1429     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1430         struct dwc_otg_platform_data *pldata = dev->platform_data;
1431     if(core_if->op_state == A_HOST)
1432     {
1433         DWC_PRINT("%s,A_HOST mode\n", __func__);
1434         return 0;
1435     }
1436     /* Clear any pending interrupts */
1437     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1438 //    dwc_otg_disable_global_interrupts(core_if);
1439     if( pldata->phy_status == 0 ){
1440         /* no vbus detect here , close usb phy  */
1441         pldata->phy_suspend(pldata, USB_PHY_SUSPEND);
1442         udelay(3);
1443         pldata->clock_enable( pldata, 0);
1444     }
1445 //    del_timer(&otg_dev->pcd->check_vbus_timer);
1446
1447     return 0;
1448 }
1449 #else
1450 static int dwc_otg_driver_suspend(struct platform_device *_dev , pm_message_t state )
1451 {
1452     return 0;
1453 }
1454 #endif
1455
1456 static int dwc_otg_driver_resume(struct platform_device *_dev )
1457 {
1458         struct device *dev = &_dev->dev;
1459         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1460     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1461     dctl_data_t dctl = {.d32=0};
1462         struct dwc_otg_platform_data *pldata = dev->platform_data;
1463
1464     dwc_otg_core_global_regs_t *global_regs =
1465         core_if->core_global_regs;
1466     if(core_if->op_state == A_HOST)
1467     {
1468         DWC_PRINT("%s,A_HOST mode\n", __func__);
1469         return 0;
1470     }
1471     return 0;
1472 }
1473
1474 static void dwc_otg_driver_shutdown(struct platform_device *_dev )
1475 {
1476         struct device *dev = &_dev->dev;
1477         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1478     dwc_otg_core_if_t *core_if = otg_dev->core_if;
1479     dctl_data_t dctl = {.d32=0};
1480
1481     DWC_PRINT("%s:: disconnect USB\n" , __func__ );
1482     if(core_if->op_state == A_HOST)
1483     {
1484         if (core_if->hcd_cb && core_if->hcd_cb->stop) {
1485                 core_if->hcd_cb->stop( core_if->hcd_cb->p );
1486         }
1487     }
1488     else{
1489         /* soft disconnect */
1490         dctl.d32 = dwc_read_reg32( &core_if->dev_if->dev_global_regs->dctl );
1491         dctl.b.sftdiscon = 1;
1492         dwc_write_reg32( &core_if->dev_if->dev_global_regs->dctl, dctl.d32 );
1493     }
1494     /* Clear any pending interrupts */
1495     dwc_write_reg32( &core_if->core_global_regs->gintsts, 0xFFFFFFFF);
1496
1497 }
1498
1499 /**
1500  * This structure defines the methods to be called by a bus driver
1501  * during the lifecycle of a device on that bus. Both drivers and
1502  * devices are registered with a bus driver. The bus driver matches
1503  * devices to drivers based on information in the device and driver
1504  * structures.
1505  *
1506  * The probe function is called when the bus driver matches a device
1507  * to this driver. The remove function is called when a device is
1508  * unregistered with the bus driver.
1509  */
1510 static const struct of_device_id usb20_otg_of_match[] = {
1511         { .compatible = "rockchip,usb20_otg", },
1512         {},
1513 };
1514 MODULE_DEVICE_TABLE(of, usb20_otg_of_match);
1515 static struct platform_driver dwc_otg_driver = {
1516         .probe = dwc_otg_driver_probe,
1517         .remove = dwc_otg_driver_remove,
1518         .suspend = dwc_otg_driver_suspend,
1519         .resume = dwc_otg_driver_resume,
1520         .shutdown = dwc_otg_driver_shutdown,
1521         .driver = {
1522                    .name = dwc_driver_name,
1523                    .owner = THIS_MODULE,
1524                    .of_match_table = of_match_ptr(usb20_otg_of_match),
1525         },
1526 };
1527 #endif
1528
1529 #ifdef CONFIG_USB20_HOST
1530 extern void dwc_otg_hcd_remove(struct device *dev);
1531 extern int host20_hcd_init(struct device *_dev);
1532
1533
1534 static int host20_driver_remove(struct platform_device *pdev)
1535 {
1536         struct device *dev = &pdev->dev;
1537         dwc_otg_device_t *otg_dev = (dwc_otg_device_t *)(*((uint32_t *)dev->platform_data));
1538         DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, pdev);
1539
1540         if (otg_dev == NULL)
1541         {
1542                 /* Memory allocation for the dwc_otg_device failed. */
1543                 return 0;
1544         }
1545
1546         /*
1547          * Free the IRQ
1548          */
1549         if (otg_dev->common_irq_installed)
1550         {
1551                 free_irq( platform_get_irq(to_platform_device(dev),0), otg_dev );
1552         }
1553
1554         if (otg_dev->hcd != NULL)
1555         {
1556                 dwc_otg_hcd_remove(dev);
1557         }
1558
1559         if (otg_dev->core_if != NULL)
1560         {
1561                 dwc_otg_cil_remove( otg_dev->core_if );
1562         }
1563
1564         /*
1565          * Remove the device attributes
1566          */
1567         //dwc_otg_attr_remove(dev);
1568
1569         /*
1570          * Return the memory.
1571          */
1572         if (otg_dev->base != NULL)
1573         {
1574                 iounmap(otg_dev->base);
1575         }
1576         kfree(otg_dev);
1577
1578         /*
1579          * Clear the drvdata pointer.
1580          */
1581 //      dev->platform_data = 0;
1582
1583
1584         return 0;
1585 }
1586
1587 /**
1588  * This function is called when an lm_device is bound to a
1589  * dwc_otg_driver. It creates the driver components required to
1590  * control the device (CIL, HCD, and PCD) and it initializes the
1591  * device. The driver components are stored in a dwc_otg_device
1592  * structure. A reference to the dwc_otg_device is saved in the
1593  * lm_device. This allows the driver to access the dwc_otg_device
1594  * structure on subsequent calls to driver methods for this device.
1595  *
1596  * @param[in] pdev  platform_device definition
1597  */
1598 static int host20_driver_probe(struct platform_device *pdev)
1599 {
1600         struct device_node      *node = pdev->dev.of_node;
1601         struct resource         *res_base;
1602         int                     retval = 0;
1603         struct device           *dev = &pdev->dev;
1604         dwc_otg_device_t        *dwc_otg_device;
1605         int32_t                 snpsid;
1606         int                     irq;
1607         struct dwc_otg_platform_data *pldata;
1608
1609         dev->platform_data = &usb20host_pdata;
1610         pldata = dev->platform_data;
1611         pldata->dev = dev;
1612
1613         if (!node) {
1614                 dev_err(dev, "device node not found\n");
1615                 return -EINVAL;
1616         }
1617
1618         // clock and hw init
1619         if(pldata->hw_init)
1620                 pldata->hw_init();
1621
1622         if(pldata->clock_init){
1623                 pldata->clock_init(pldata);
1624                 pldata->clock_enable(pldata, 1);
1625         }
1626
1627         if(pldata->phy_suspend)
1628                 pldata->phy_suspend(pldata, USB_PHY_ENABLED);
1629
1630         if(pldata->soft_reset)
1631                 pldata->soft_reset();
1632
1633         /*
1634          *Enable usb phy
1635          */
1636
1637         dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL);
1638
1639         if (dwc_otg_device == 0)
1640         {
1641                 dev_err(dev, "kmalloc of dwc_otg_device failed\n");
1642                 retval = -ENOMEM;
1643                 goto fail;
1644         }
1645
1646         memset(dwc_otg_device, 0, sizeof(*dwc_otg_device));
1647         dwc_otg_device->reg_offset = 0xFFFFFFFF;
1648
1649         /*
1650          * Map the DWC_otg Core memory into virtual address space.
1651          */
1652
1653         res_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1654         if (!res_base)
1655                 goto fail;
1656
1657         dwc_otg_device->base = devm_ioremap_resource(dev, res_base);
1658         DWC_PRINT("%s host2.0 reg addr: 0x%x remap:0x%x\n",__func__,
1659                 (unsigned)res_base->start, (unsigned)dwc_otg_device->base);
1660         if (dwc_otg_device->base == NULL)
1661         {
1662                 DWC_ERROR("ioremap() failed\n");
1663                 retval = -ENOMEM;
1664                 goto fail;
1665         }
1666         DWC_DEBUGPL( DBG_CIL, "base addr for rk29 host20:0x%x\n", (unsigned)dwc_otg_device->base);
1667         /*
1668          * Attempt to ensure this device is really a DWC_otg Controller.
1669          * Read and verify the SNPSID register contents. The value should be
1670          * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX".
1671          */
1672         snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40));
1673         if ((snpsid & 0xFFFFF000) != 0x4F542000)
1674         {
1675                         DWC_PRINT("%s::snpsid=0x%x,want 0x%x" , __func__ , snpsid , 0x4F542000 );
1676                 dev_err(dev, "Bad value for SNPSID: 0x%08x\n", snpsid);
1677                 retval = -EINVAL;
1678                 goto fail;
1679         }
1680
1681         /*
1682          * Initialize driver data to point to the global DWC_otg
1683          * Device structure.
1684          */
1685         pldata->privdata = dwc_otg_device;
1686         dwc_otg_device->pldata = (void *)pldata;
1687
1688         DWC_DEBUGPL(DBG_CIL, "dwc_otg_device=0x%p\n", dwc_otg_device);
1689         g_host20 = dwc_otg_device;
1690
1691         dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base,
1692                                                         &host20_module_params);
1693         if (dwc_otg_device->core_if == 0)
1694         {
1695                 dev_err(dev, "CIL initialization failed!\n");
1696                 retval = -ENOMEM;
1697                 goto fail;
1698         }
1699
1700         dwc_otg_device->core_if->otg_dev = dwc_otg_device;
1701         /*
1702          * Validate parameter values.
1703          */
1704         if (check_parameters(dwc_otg_device->core_if) != 0)
1705         {
1706                 retval = -EINVAL;
1707                 goto fail;
1708         }
1709
1710         /*
1711          * Create Device Attributes in sysfs
1712          */
1713         dwc_otg_attr_create(dev);
1714         retval |= device_create_file(dev, &dev_attr_enable);
1715
1716         /*
1717          * Disable the global interrupt until all the interrupt
1718          * handlers are installed.
1719          */
1720         dwc_otg_disable_global_interrupts( dwc_otg_device->core_if );
1721         /*
1722          * Install the interrupt handler for the common interrupts before
1723          * enabling common interrupts in core_init below.
1724          */
1725         irq = platform_get_irq(to_platform_device(dev),0);
1726         DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n",
1727                          irq);
1728         retval = request_irq(irq, dwc_otg_common_irq,
1729                                  IRQF_SHARED, "dwc_otg", dwc_otg_device );
1730         if (retval != 0)
1731         {
1732                 DWC_ERROR("request of irq%d failed\n", irq);
1733                 retval = -EBUSY;
1734                 goto fail;
1735         }
1736         else
1737         {
1738                 dwc_otg_device->common_irq_installed = 1;
1739         }
1740
1741         /*
1742          * Initialize the DWC_otg core.
1743          */
1744         dwc_otg_core_init( dwc_otg_device->core_if );
1745
1746         /*
1747          * Initialize the HCD
1748          */
1749         retval = host20_hcd_init(dev);
1750         if (retval != 0)
1751         {
1752                 DWC_ERROR("host20_hcd_init failed\n");
1753                 dwc_otg_device->hcd = NULL;
1754                 goto fail;
1755         }
1756         /*
1757          * Enable the global interrupt after all the interrupt
1758          * handlers are installed.
1759          */
1760         dwc_otg_enable_global_interrupts( dwc_otg_device->core_if );
1761
1762         return 0;
1763
1764  fail:
1765         devm_kfree(&pdev->dev, dwc_otg_device);
1766         DWC_PRINT("host20_driver_probe fail,everest\n");
1767         return retval;
1768 }
1769
1770 static const struct of_device_id usb20_host_of_match[] = {
1771         { .compatible = "rockchip,usb20_host", },
1772         {},
1773 };
1774 MODULE_DEVICE_TABLE(of, usb20_host_of_match);
1775 static struct platform_driver host20_driver = {
1776         .probe = host20_driver_probe,
1777         .remove = host20_driver_remove,
1778         .driver = {
1779                    .name = "usb20_host",
1780                    .owner = THIS_MODULE,
1781                    .of_match_table = of_match_ptr(usb20_host_of_match),
1782         },
1783 };
1784 #endif
1785
1786 /**
1787  * This function is called when the dwc_otg_driver is installed with the
1788  * insmod command. It registers the dwc_otg_driver structure with the
1789  * appropriate bus driver. This will cause the dwc_otg_driver_probe function
1790  * to be called. In addition, the bus driver will automatically expose
1791  * attributes defined for the device and driver in the special sysfs file
1792  * system.
1793  *
1794  * @return
1795  */
1796 static int __init dwc_otg_driver_init(void)
1797 {
1798         int retval = 0;
1799     /*
1800      *  USB2.0 OTG controller
1801      */
1802 #ifdef CONFIG_USB20_OTG
1803         retval = platform_driver_register(&dwc_otg_driver);
1804         if (retval < 0)
1805         {
1806                 DWC_ERROR("%s retval=%d\n", __func__, retval);
1807                 return retval;
1808         }
1809         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_version))
1810                 pr_warning("DWC_OTG: Failed to create driver version file\n");
1811         if (driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel))
1812                 pr_warning("DWC_OTG: Failed to create driver debug level file\n");
1813 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1814         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en))
1815                 pr_warning("DWC_OTG: Failed to create driver dwc_otg_conn_en file");
1816 #endif
1817
1818 #ifdef CONFIG_RK_USB_UART
1819         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_force_uart))
1820                 pr_warning("DWC_OTG: Failed to create driver dwc_otg_force_uart file");
1821 #endif
1822
1823 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1824         if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_vbus_status))
1825                 pr_warning("DWC_OTG: Failed to create driver vbus status file");
1826 #endif
1827
1828 #ifdef DWC_BOTH_HOST_SLAVE
1829     if(driver_create_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode))
1830                 pr_warning("DWC_OTG: Failed to create driver force usb mode file\n");
1831 #endif
1832
1833 #endif
1834
1835     /*
1836      *  USB2.0 host controller
1837      */
1838 #ifdef CONFIG_USB20_HOST
1839     retval = platform_driver_register(&host20_driver);
1840     if (retval < 0)
1841     {
1842         DWC_ERROR("%s retval=%d\n", __func__, retval);
1843         return retval;
1844     }
1845 #endif
1846
1847     /*
1848      *  USB1.1 host controller
1849      */
1850
1851 #ifdef CONFIG_USB11_HOST
1852         retval = platform_driver_register(&host11_driver);
1853         if (retval < 0)
1854         {
1855                 DWC_ERROR("%s retval=%d\n", __func__, retval);
1856                 return retval;
1857         }
1858 //      retval = driver_create_file(&host11_driver.driver, &driver_attr_enable_usb11);
1859 #endif
1860
1861         return retval;
1862 }
1863 module_init(dwc_otg_driver_init);
1864
1865 /**
1866  * This function is called when the driver is removed from the kernel
1867  * with the rmmod command. The driver unregisters itself with its bus
1868  * driver.
1869  *
1870  */
1871 static void __exit dwc_otg_driver_cleanup(void)
1872 {
1873         DWC_PRINT("dwc_otg_driver_cleanup()\n");
1874
1875 #ifdef CONFIG_USB20_OTG
1876         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version);
1877         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel);
1878
1879 #ifdef DWC_BOTH_HOST_SLAVE
1880         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_force_usb_mode);
1881 #endif
1882
1883 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1884         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_conn_en);
1885 #endif
1886
1887 #ifdef CONFIG_RK_USB_UART
1888         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_dwc_otg_force_uart);
1889 #endif
1890
1891 #ifndef CONFIG_DWC_OTG_HOST_ONLY
1892         driver_remove_file(&dwc_otg_driver.driver, &driver_attr_vbus_status);
1893 #endif
1894
1895         platform_driver_unregister(&dwc_otg_driver);
1896 #endif
1897
1898 #ifdef CONFIG_USB11_HOST
1899         platform_driver_unregister(&host11_driver);
1900 #endif
1901
1902 #ifdef CONFIG_USB20_HOST
1903         platform_driver_unregister(&host20_driver);
1904 #endif
1905         DWC_PRINT("%s module removed\n", dwc_driver_name);
1906 }
1907 module_exit(dwc_otg_driver_cleanup);
1908
1909 MODULE_DESCRIPTION(DWC_DRIVER_DESC);
1910 MODULE_AUTHOR("Synopsys Inc.");
1911 MODULE_LICENSE("GPL");
1912
1913 module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444);
1914 MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None");
1915 module_param_named(opt, dwc_otg_module_params.opt, int, 0444);
1916 MODULE_PARM_DESC(opt, "OPT Mode");
1917 module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444);
1918 MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled");
1919 module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444);
1920 MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
1921 module_param_named(speed, dwc_otg_module_params.speed, int, 0444);
1922 MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed");
1923 module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444);
1924 MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support");
1925 module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444);
1926 MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
1927 module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444);
1928 MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing");
1929 module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444);
1930 MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768");
1931 module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444);
1932 MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1933 module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444);
1934 MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
1935 module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444);
1936 MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768");
1937 module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444);
1938 MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768");
1939 module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444);
1940 MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768");
1941 module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444);
1942 MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768");
1943 module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444);
1944 MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768");
1945 module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444);
1946 MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768");
1947 module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444);
1948 MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768");
1949 module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444);
1950 MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768");
1951 module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444);
1952 MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768");
1953 module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444);
1954 MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768");
1955 module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444);
1956 MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768");
1957 module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444);
1958 MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768");
1959 module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444);
1960 MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768");
1961 module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444);
1962 MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768");
1963 module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444);
1964 MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768");
1965 module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444);
1966 MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768");
1967 module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444);
1968 MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768");
1969 module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444);
1970 MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768");
1971 module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444);
1972 /** @todo Set the max to 512K, modify checks */
1973 MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535");
1974 module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444);
1975 MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511");
1976 module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444);
1977 MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16");
1978 module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444);
1979 MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15");
1980 module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444);
1981 MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI");
1982 module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444);
1983 MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits");
1984 module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444);
1985 MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double");
1986 module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444);
1987 MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal");
1988 module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444);
1989 MODULE_PARM_DESC(i2c_enable, "FS PHY Interface");
1990 module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444);
1991 MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only");
1992 module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444);
1993 MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs");
1994 module_param_named(debug, g_dbg_lvl, int, 0444);
1995 MODULE_PARM_DESC(debug, "");
1996
1997 module_param_named(en_multiple_tx_fifo, dwc_otg_module_params.en_multiple_tx_fifo, int, 0444);
1998 MODULE_PARM_DESC(en_multiple_tx_fifo, "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled");
1999 module_param_named(dev_tx_fifo_size_1, dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444);
2000 MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768");
2001 module_param_named(dev_tx_fifo_size_2, dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444);
2002 MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768");
2003 module_param_named(dev_tx_fifo_size_3, dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444);
2004 MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768");
2005 module_param_named(dev_tx_fifo_size_4, dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444);
2006 MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768");
2007 module_param_named(dev_tx_fifo_size_5, dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444);
2008 MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768");
2009 module_param_named(dev_tx_fifo_size_6, dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444);
2010 MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768");
2011 module_param_named(dev_tx_fifo_size_7, dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444);
2012 MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768");
2013 module_param_named(dev_tx_fifo_size_8, dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444);
2014 MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768");
2015 module_param_named(dev_tx_fifo_size_9, dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444);
2016 MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768");
2017 module_param_named(dev_tx_fifo_size_10, dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444);
2018 MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768");
2019 module_param_named(dev_tx_fifo_size_11, dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444);
2020 MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768");
2021 module_param_named(dev_tx_fifo_size_12, dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444);
2022 MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768");
2023 module_param_named(dev_tx_fifo_size_13, dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444);
2024 MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768");
2025 module_param_named(dev_tx_fifo_size_14, dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444);
2026 MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768");
2027 module_param_named(dev_tx_fifo_size_15, dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444);
2028 MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768");
2029
2030 module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444);
2031 MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit 0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled");
2032 module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444);
2033 MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs");
2034 module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444);
2035 MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs");
2036 /** @page "Module Parameters"
2037  *
2038  * The following parameters may be specified when starting the module.
2039  * These parameters define how the DWC_otg controller should be
2040  * configured.  Parameter values are passed to the CIL initialization
2041  * function dwc_otg_cil_init
2042  *
2043  * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code>
2044  *
2045
2046  <table>
2047  <tr><td>Parameter Name</td><td>Meaning</td></tr>
2048
2049  <tr>
2050  <td>otg_cap</td>
2051  <td>Specifies the OTG capabilities. The driver will automatically detect the
2052  value for this parameter if none is specified.
2053  - 0: HNP and SRP capable (default, if available)
2054  - 1: SRP Only capable
2055  - 2: No HNP/SRP capable
2056  </td></tr>
2057
2058  <tr>
2059  <td>dma_enable</td>
2060  <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs.
2061  The driver will automatically detect the value for this parameter if none is
2062  specified.
2063  - 0: Slave
2064  - 1: DMA (default, if available)
2065  </td></tr>
2066
2067  <tr>
2068  <td>dma_burst_size</td>
2069  <td>The DMA Burst size (applicable only for External DMA Mode).
2070  - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32)
2071  </td></tr>
2072
2073  <tr>
2074  <td>speed</td>
2075  <td>Specifies the maximum speed of operation in host and device mode. The
2076  actual speed depends on the speed of the attached device and the value of
2077  phy_type.
2078  - 0: High Speed (default)
2079  - 1: Full Speed
2080  </td></tr>
2081
2082  <tr>
2083  <td>host_support_fs_ls_low_power</td>
2084  <td>Specifies whether low power mode is supported when attached to a Full
2085  Speed or Low Speed device in host mode.
2086  - 0: Don't support low power mode (default)
2087  - 1: Support low power mode
2088  </td></tr>
2089
2090  <tr>
2091  <td>host_ls_low_power_phy_clk</td>
2092  <td>Specifies the PHY clock rate in low power mode when connected to a Low
2093  Speed device in host mode. This parameter is applicable only if
2094  HOST_SUPPORT_FS_LS_LOW_POWER is enabled.
2095  - 0: 48 MHz (default)
2096  - 1: 6 MHz
2097  </td></tr>
2098
2099  <tr>
2100  <td>enable_dynamic_fifo</td>
2101  <td> Specifies whether FIFOs may be resized by the driver software.
2102  - 0: Use cC FIFO size parameters
2103  - 1: Allow dynamic FIFO sizing (default)
2104  </td></tr>
2105
2106  <tr>
2107  <td>data_fifo_size</td>
2108  <td>Total number of 4-byte words in the data FIFO memory. This memory
2109  includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs.
2110  - Values: 32 to 32768 (default 8192)
2111
2112  Note: The total FIFO memory depth in the FPGA configuration is 8192.
2113  </td></tr>
2114
2115  <tr>
2116  <td>dev_rx_fifo_size</td>
2117  <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic
2118  FIFO sizing is enabled.
2119  - Values: 16 to 32768 (default 1064)
2120  </td></tr>
2121
2122  <tr>
2123  <td>dev_nperio_tx_fifo_size</td>
2124  <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when
2125  dynamic FIFO sizing is enabled.
2126  - Values: 16 to 32768 (default 1024)
2127  </td></tr>
2128
2129  <tr>
2130  <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td>
2131  <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode
2132  when dynamic FIFO sizing is enabled.
2133  - Values: 4 to 768 (default 256)
2134  </td></tr>
2135
2136  <tr>
2137  <td>host_rx_fifo_size</td>
2138  <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO
2139  sizing is enabled.
2140  - Values: 16 to 32768 (default 1024)
2141  </td></tr>
2142
2143  <tr>
2144  <td>host_nperio_tx_fifo_size</td>
2145  <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when
2146  dynamic FIFO sizing is enabled in the core.
2147  - Values: 16 to 32768 (default 1024)
2148  </td></tr>
2149
2150  <tr>
2151  <td>host_perio_tx_fifo_size</td>
2152  <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO
2153  sizing is enabled.
2154  - Values: 16 to 32768 (default 1024)
2155  </td></tr>
2156
2157  <tr>
2158  <td>max_transfer_size</td>
2159  <td>The maximum transfer size supported in bytes.
2160  - Values: 2047 to 65,535 (default 65,535)
2161  </td></tr>
2162
2163  <tr>
2164  <td>max_packet_count</td>
2165  <td>The maximum number of packets in a transfer.
2166  - Values: 15 to 511 (default 511)
2167  </td></tr>
2168
2169  <tr>
2170  <td>host_channels</td>
2171  <td>The number of host channel registers to use.
2172  - Values: 1 to 16 (default 12)
2173
2174  Note: The FPGA configuration supports a maximum of 12 host channels.
2175  </td></tr>
2176
2177  <tr>
2178  <td>dev_endpoints</td>
2179  <td>The number of endpoints in addition to EP0 available for device mode
2180  operations.
2181  - Values: 1 to 15 (default 6 IN and OUT)
2182
2183  Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in
2184  addition to EP0.
2185  </td></tr>
2186
2187  <tr>
2188  <td>phy_type</td>
2189  <td>Specifies the type of PHY interface to use. By default, the driver will
2190  automatically detect the phy_type.
2191  - 0: Full Speed
2192  - 1: UTMI+ (default, if available)
2193  - 2: ULPI
2194  </td></tr>
2195
2196  <tr>
2197  <td>phy_utmi_width</td>
2198  <td>Specifies the UTMI+ Data Width. This parameter is applicable for a
2199  phy_type of UTMI+. Also, this parameter is applicable only if the
2200  OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the
2201  core has been configured to work at either data path width.
2202  - Values: 8 or 16 bits (default 16)
2203  </td></tr>
2204
2205  <tr>
2206  <td>phy_ulpi_ddr</td>
2207  <td>Specifies whether the ULPI operates at double or single data rate. This
2208  parameter is only applicable if phy_type is ULPI.
2209  - 0: single data rate ULPI interface with 8 bit wide data bus (default)
2210  - 1: double data rate ULPI interface with 4 bit wide data bus
2211  </td></tr>
2212
2213  <tr>
2214  <td>i2c_enable</td>
2215  <td>Specifies whether to use the I2C interface for full speed PHY. This
2216  parameter is only applicable if PHY_TYPE is FS.
2217  - 0: Disabled (default)
2218  - 1: Enabled
2219  </td></tr>
2220
2221  <tr>
2222  <td>otg_en_multiple_tx_fifo</td>
2223  <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs.
2224  The driver will automatically detect the value for this parameter if none is
2225  specified.
2226  - 0: Disabled
2227  - 1: Enabled (default, if available)
2228  </td></tr>
2229
2230  <tr>
2231  <td>dev_tx_fifo_size_n (n = 1 to 15)</td>
2232  <td>Number of 4-byte words in each of the Tx FIFOs in device mode
2233  when dynamic FIFO sizing is enabled.
2234  - Values: 4 to 768 (default 256)
2235  </td></tr>
2236
2237 */