drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue))
 181                                 dwc3_ep_inc_deq(dep);
 182                 } while(++i < req->request.num_mapped_sgs);
 183                 req->started = false;
 184         }
 185         list_del(&req->list);
 186         req->trb = NULL;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (dwc->ep0_bounced && dep->number == 0)
 192                 dwc->ep0_bounced = false;
 193         else
 194                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 195                                 req->direction);
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202 }
 203
 204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 205 {
 206         u32             timeout = 500;
 207         u32             reg;
 208
 209         trace_dwc3_gadget_generic_cmd(cmd, param);
 210
 211         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 212         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 213
 214         do {
 215                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 216                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 217                         dwc3_trace(trace_dwc3_gadget,
 218                                         "Command Complete --> %d",
 219                                         DWC3_DGCMD_STATUS(reg));
 220                         if (DWC3_DGCMD_STATUS(reg))
 221                                 return -EINVAL;
 222                         return 0;
 223                 }
 224
 225                 /*
 226                  * We can't sleep here, because it's also called from
 227                  * interrupt context.
 228                  */
 229                 timeout--;
 230                 if (!timeout) {
 231                         dwc3_trace(trace_dwc3_gadget,
 232                                         "Command Timed Out");
 233                         return -ETIMEDOUT;
 234                 }
 235                 udelay(1);
 236         } while (1);
 237 }
 238
 239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 240
 241 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 242                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 243 {
 244         struct dwc3_ep          *dep = dwc->eps[ep];
 245         u32                     timeout = 500;
 246         u32                     reg;
 247
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 252
 253         /*
 254          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 255          * we're issuing an endpoint command, we must check if
 256          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 257          *
 258          * We will also set SUSPHY bit to what it was before returning as stated
 259          * by the same section on Synopsys databook.
 260          */
 261         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 262         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 263                 susphy = true;
 264                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 265                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 283         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 284         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 285
 286         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         int cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         dwc3_trace(trace_dwc3_gadget,
 293                                         "Command Complete --> %d",
 294                                         cmd_status);
 295
 296                         switch (cmd_status) {
 297                         case 0:
 298                                 ret = 0;
 299                                 break;
 300                         case DEPEVT_TRANSFER_NO_RESOURCE:
 301                                 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
 302                                 ret = -EINVAL;
 303                                 break;
 304                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 305                                 /*
 306                                  * SW issues START TRANSFER command to
 307                                  * isochronous ep with future frame interval. If
 308                                  * future interval time has already passed when
 309                                  * core receives the command, it will respond
 310                                  * with an error status of 'Bus Expiry'.
 311                                  *
 312                                  * Instead of always returning -EINVAL, let's
 313                                  * give a hint to the gadget driver that this is
 314                                  * the case by returning -EAGAIN.
 315                                  */
 316                                 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
 317                                 ret = -EAGAIN;
 318                                 break;
 319                         default:
 320                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 321                         }
 322
 323                         break;
 324                 }
 325
 326                 /*
 327                  * We can't sleep here, because it is also called from
 328                  * interrupt context.
 329                  */
 330                 timeout--;
 331                 if (!timeout) {
 332                         dwc3_trace(trace_dwc3_gadget,
 333                                         "Command Timed Out");
 334                         ret = -ETIMEDOUT;
 335                         break;
 336                 }
 337         } while (1);
 338
 339         if (unlikely(susphy)) {
 340                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 341                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 342                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 343         }
 344
 345         return ret;
 346 }
 347
 348 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 349 {
 350         struct dwc3 *dwc = dep->dwc;
 351         struct dwc3_gadget_ep_cmd_params params;
 352         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 353
 354         /*
 355          * As of core revision 2.60a the recommended programming model
 356          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 357          * command for IN endpoints. This is to prevent an issue where
 358          * some (non-compliant) hosts may not send ACK TPs for pending
 359          * IN transfers due to a mishandled error condition. Synopsys
 360          * STAR 9000614252.
 361          */
 362         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 363                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 364
 365         memset(&params, 0, sizeof(params));
 366
 367         return dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 368 }
 369
 370 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 371                 struct dwc3_trb *trb)
 372 {
 373         u32             offset = (char *) trb - (char *) dep->trb_pool;
 374
 375         return dep->trb_pool_dma + offset;
 376 }
 377
 378 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 379 {
 380         struct dwc3             *dwc = dep->dwc;
 381
 382         if (dep->trb_pool)
 383                 return 0;
 384
 385         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 386                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 387                         &dep->trb_pool_dma, GFP_KERNEL);
 388         if (!dep->trb_pool) {
 389                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 390                                 dep->name);
 391                 return -ENOMEM;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 398 {
 399         struct dwc3             *dwc = dep->dwc;
 400
 401         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 402                         dep->trb_pool, dep->trb_pool_dma);
 403
 404         dep->trb_pool = NULL;
 405         dep->trb_pool_dma = 0;
 406 }
 407
 408 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 409
 410 /**
 411  * dwc3_gadget_start_config - Configure EP resources
 412  * @dwc: pointer to our controller context structure
 413  * @dep: endpoint that is being enabled
 414  *
 415  * The assignment of transfer resources cannot perfectly follow the
 416  * data book due to the fact that the controller driver does not have
 417  * all knowledge of the configuration in advance. It is given this
 418  * information piecemeal by the composite gadget framework after every
 419  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 420  * programming model in this scenario can cause errors. For two
 421  * reasons:
 422  *
 423  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 424  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 425  * multiple interfaces.
 426  *
 427  * 2) The databook does not mention doing more DEPXFERCFG for new
 428  * endpoint on alt setting (8.1.6).
 429  *
 430  * The following simplified method is used instead:
 431  *
 432  * All hardware endpoints can be assigned a transfer resource and this
 433  * setting will stay persistent until either a core reset or
 434  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 435  * do DEPXFERCFG for every hardware endpoint as well. We are
 436  * guaranteed that there are as many transfer resources as endpoints.
 437  *
 438  * This function is called for each endpoint when it is being enabled
 439  * but is triggered only when called for EP0-out, which always happens
 440  * first, and which should only happen in one of the above conditions.
 441  */
 442 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 443 {
 444         struct dwc3_gadget_ep_cmd_params params;
 445         u32                     cmd;
 446         int                     i;
 447         int                     ret;
 448
 449         if (dep->number)
 450                 return 0;
 451
 452         memset(&params, 0x00, sizeof(params));
 453         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 454
 455         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 456         if (ret)
 457                 return ret;
 458
 459         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 460                 struct dwc3_ep *dep = dwc->eps[i];
 461
 462                 if (!dep)
 463                         continue;
 464
 465                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 466                 if (ret)
 467                         return ret;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 474                 const struct usb_endpoint_descriptor *desc,
 475                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 476                 bool ignore, bool restore)
 477 {
 478         struct dwc3_gadget_ep_cmd_params params;
 479
 480         memset(&params, 0x00, sizeof(params));
 481
 482         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 483                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 484
 485         /* Burst size is only needed in SuperSpeed mode */
 486         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 487                 u32 burst = dep->endpoint.maxburst;
 488                 u32 nump;
 489                 u32 reg;
 490
 491                 /* update NumP */
 492                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 493                 nump = DWC3_DCFG_NUMP(reg);
 494                 nump = max(nump, burst);
 495                 reg &= ~DWC3_DCFG_NUMP_MASK;
 496                 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
 497                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 498
 499                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 500         }
 501
 502         if (ignore)
 503                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 504
 505         if (restore) {
 506                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 507                 params.param2 |= dep->saved_state;
 508         }
 509
 510         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 511                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 512
 513         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 514                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 515                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 516                 dep->stream_capable = true;
 517         }
 518
 519         if (!usb_endpoint_xfer_control(desc))
 520                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 521
 522         /*
 523          * We are doing 1:1 mapping for endpoints, meaning
 524          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 525          * so on. We consider the direction bit as part of the physical
 526          * endpoint number. So USB endpoint 0x81 is 0x03.
 527          */
 528         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 529
 530         /*
 531          * We must use the lower 16 TX FIFOs even though
 532          * HW might have more
 533          */
 534         if (dep->direction)
 535                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 536
 537         if (desc->bInterval) {
 538                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 539                 dep->interval = 1 << (desc->bInterval - 1);
 540         }
 541
 542         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 543                         DWC3_DEPCMD_SETEPCONFIG, &params);
 544 }
 545
 546 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 547 {
 548         struct dwc3_gadget_ep_cmd_params params;
 549
 550         memset(&params, 0x00, sizeof(params));
 551
 552         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 553
 554         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 555                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 556 }
 557
 558 /**
 559  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 560  * @dep: endpoint to be initialized
 561  * @desc: USB Endpoint Descriptor
 562  *
 563  * Caller should take care of locking
 564  */
 565 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 566                 const struct usb_endpoint_descriptor *desc,
 567                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 568                 bool ignore, bool restore)
 569 {
 570         struct dwc3             *dwc = dep->dwc;
 571         u32                     reg;
 572         int                     ret;
 573
 574         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 575
 576         if (!(dep->flags & DWC3_EP_ENABLED)) {
 577                 ret = dwc3_gadget_start_config(dwc, dep);
 578                 if (ret)
 579                         return ret;
 580         }
 581
 582         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 583                         restore);
 584         if (ret)
 585                 return ret;
 586
 587         if (!(dep->flags & DWC3_EP_ENABLED)) {
 588                 struct dwc3_trb *trb_st_hw;
 589                 struct dwc3_trb *trb_link;
 590
 591                 dep->endpoint.desc = desc;
 592                 dep->comp_desc = comp_desc;
 593                 dep->type = usb_endpoint_type(desc);
 594                 dep->flags |= DWC3_EP_ENABLED;
 595
 596                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 597                 reg |= DWC3_DALEPENA_EP(dep->number);
 598                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 599
 600                 if (usb_endpoint_xfer_control(desc))
 601                         goto out;
 602
 603                 /* Link TRB. The HWO bit is never reset */
 604                 trb_st_hw = &dep->trb_pool[0];
 605
 606                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 607                 memset(trb_link, 0, sizeof(*trb_link));
 608
 609                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 610                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 611                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 612                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 613         }
 614
 615 out:
 616         switch (usb_endpoint_type(desc)) {
 617         case USB_ENDPOINT_XFER_CONTROL:
 618                 /* don't change name */
 619                 break;
 620         case USB_ENDPOINT_XFER_ISOC:
 621                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 622                 break;
 623         case USB_ENDPOINT_XFER_BULK:
 624                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 625                 break;
 626         case USB_ENDPOINT_XFER_INT:
 627                 strlcat(dep->name, "-int", sizeof(dep->name));
 628                 break;
 629         default:
 630                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 631         }
 632
 633         return 0;
 634 }
 635
 636 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 637 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 638 {
 639         struct dwc3_request             *req;
 640
 641         if (!list_empty(&dep->started_list)) {
 642                 dwc3_stop_active_transfer(dwc, dep->number, true);
 643
 644                 /* - giveback all requests to gadget driver */
 645                 while (!list_empty(&dep->started_list)) {
 646                         req = next_request(&dep->started_list);
 647
 648                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 649                 }
 650         }
 651
 652         while (!list_empty(&dep->pending_list)) {
 653                 req = next_request(&dep->pending_list);
 654
 655                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 656         }
 657 }
 658
 659 /**
 660  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 661  * @dep: the endpoint to disable
 662  *
 663  * This function also removes requests which are currently processed ny the
 664  * hardware and those which are not yet scheduled.
 665  * Caller should take care of locking.
 666  */
 667 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 668 {
 669         struct dwc3             *dwc = dep->dwc;
 670         u32                     reg;
 671
 672         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 673
 674         dwc3_remove_requests(dwc, dep);
 675
 676         /* make sure HW endpoint isn't stalled */
 677         if (dep->flags & DWC3_EP_STALL)
 678                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 679
 680         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 681         reg &= ~DWC3_DALEPENA_EP(dep->number);
 682         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 683
 684         dep->stream_capable = false;
 685         dep->endpoint.desc = NULL;
 686         dep->comp_desc = NULL;
 687         dep->type = 0;
 688         dep->flags = 0;
 689
 690         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 691                         dep->number >> 1,
 692                         (dep->number & 1) ? "in" : "out");
 693
 694         return 0;
 695 }
 696
 697 /* -------------------------------------------------------------------------- */
 698
 699 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 700                 const struct usb_endpoint_descriptor *desc)
 701 {
 702         return -EINVAL;
 703 }
 704
 705 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 706 {
 707         return -EINVAL;
 708 }
 709
 710 /* -------------------------------------------------------------------------- */
 711
 712 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 713                 const struct usb_endpoint_descriptor *desc)
 714 {
 715         struct dwc3_ep                  *dep;
 716         struct dwc3                     *dwc;
 717         unsigned long                   flags;
 718         int                             ret;
 719
 720         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 721                 pr_debug("dwc3: invalid parameters\n");
 722                 return -EINVAL;
 723         }
 724
 725         if (!desc->wMaxPacketSize) {
 726                 pr_debug("dwc3: missing wMaxPacketSize\n");
 727                 return -EINVAL;
 728         }
 729
 730         dep = to_dwc3_ep(ep);
 731         dwc = dep->dwc;
 732
 733         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 734                                         "%s is already enabled\n",
 735                                         dep->name))
 736                 return 0;
 737
 738         spin_lock_irqsave(&dwc->lock, flags);
 739         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 740         spin_unlock_irqrestore(&dwc->lock, flags);
 741
 742         return ret;
 743 }
 744
 745 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 746 {
 747         struct dwc3_ep                  *dep;
 748         struct dwc3                     *dwc;
 749         unsigned long                   flags;
 750         int                             ret;
 751
 752         if (!ep) {
 753                 pr_debug("dwc3: invalid parameters\n");
 754                 return -EINVAL;
 755         }
 756
 757         dep = to_dwc3_ep(ep);
 758         dwc = dep->dwc;
 759
 760         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 761                                         "%s is already disabled\n",
 762                                         dep->name))
 763                 return 0;
 764
 765         spin_lock_irqsave(&dwc->lock, flags);
 766         ret = __dwc3_gadget_ep_disable(dep);
 767         spin_unlock_irqrestore(&dwc->lock, flags);
 768
 769         return ret;
 770 }
 771
 772 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 773         gfp_t gfp_flags)
 774 {
 775         struct dwc3_request             *req;
 776         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 777
 778         req = kzalloc(sizeof(*req), gfp_flags);
 779         if (!req)
 780                 return NULL;
 781
 782         req->epnum      = dep->number;
 783         req->dep        = dep;
 784
 785         trace_dwc3_alloc_request(req);
 786
 787         return &req->request;
 788 }
 789
 790 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 791                 struct usb_request *request)
 792 {
 793         struct dwc3_request             *req = to_dwc3_request(request);
 794
 795         trace_dwc3_free_request(req);
 796         kfree(req);
 797 }
 798
 799 /**
 800  * dwc3_prepare_one_trb - setup one TRB from one request
 801  * @dep: endpoint for which this request is prepared
 802  * @req: dwc3_request pointer
 803  */
 804 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 805                 struct dwc3_request *req, dma_addr_t dma,
 806                 unsigned length, unsigned last, unsigned chain, unsigned node)
 807 {
 808         struct dwc3_trb         *trb;
 809
 810         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 811                         dep->name, req, (unsigned long long) dma,
 812                         length, last ? " last" : "",
 813                         chain ? " chain" : "");
 814
 815
 816         trb = &dep->trb_pool[dep->trb_enqueue];
 817
 818         if (!req->trb) {
 819                 dwc3_gadget_move_started_request(req);
 820                 req->trb = trb;
 821                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 822                 req->first_trb_index = dep->trb_enqueue;
 823         }
 824
 825         dwc3_ep_inc_enq(dep);
 826         /* Skip the LINK-TRB */
 827         if (dwc3_ep_is_last_trb(dep->trb_enqueue))
 828                 dwc3_ep_inc_enq(dep);
 829
 830         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 831         trb->bpl = lower_32_bits(dma);
 832         trb->bph = upper_32_bits(dma);
 833
 834         switch (usb_endpoint_type(dep->endpoint.desc)) {
 835         case USB_ENDPOINT_XFER_CONTROL:
 836                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 837                 break;
 838
 839         case USB_ENDPOINT_XFER_ISOC:
 840                 if (!node)
 841                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 842                 else
 843                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 844
 845                 /* always enable Interrupt on Missed ISOC */
 846                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 847                 break;
 848
 849         case USB_ENDPOINT_XFER_BULK:
 850         case USB_ENDPOINT_XFER_INT:
 851                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 852                 break;
 853         default:
 854                 /*
 855                  * This is only possible with faulty memory because we
 856                  * checked it already :)
 857                  */
 858                 BUG();
 859         }
 860
 861         /* always enable Continue on Short Packet */
 862         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 863
 864         if (!req->request.no_interrupt && !chain)
 865                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 866
 867         if (last)
 868                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 869
 870         if (chain)
 871                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 872
 873         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 874                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 875
 876         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 877
 878         trace_dwc3_prepare_trb(dep, trb);
 879 }
 880
 881 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 882 {
 883         struct dwc3_trb         *tmp;
 884
 885         /*
 886          * If enqueue & dequeue are equal than it is either full or empty.
 887          *
 888          * One way to know for sure is if the TRB right before us has HWO bit
 889          * set or not. If it has, then we're definitely full and can't fit any
 890          * more transfers in our ring.
 891          */
 892         if (dep->trb_enqueue == dep->trb_dequeue) {
 893                 /* If we're full, enqueue/dequeue are > 0 */
 894                 if (dep->trb_enqueue) {
 895                         tmp = &dep->trb_pool[dep->trb_enqueue - 1];
 896                         if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 897                                 return 0;
 898                 }
 899
 900                 return DWC3_TRB_NUM - 1;
 901         }
 902
 903         return dep->trb_dequeue - dep->trb_enqueue;
 904 }
 905
 906 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 907                 struct dwc3_request *req, unsigned int trbs_left)
 908 {
 909         struct usb_request *request = &req->request;
 910         struct scatterlist *sg = request->sg;
 911         struct scatterlist *s;
 912         unsigned int    last = false;
 913         unsigned int    length;
 914         dma_addr_t      dma;
 915         int             i;
 916
 917         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 918                 unsigned chain = true;
 919
 920                 length = sg_dma_len(s);
 921                 dma = sg_dma_address(s);
 922
 923                 if (sg_is_last(s)) {
 924                         if (list_is_last(&req->list, &dep->pending_list))
 925                                 last = true;
 926
 927                         chain = false;
 928                 }
 929
 930                 if (!trbs_left)
 931                         last = true;
 932
 933                 if (last)
 934                         chain = false;
 935
 936                 dwc3_prepare_one_trb(dep, req, dma, length,
 937                                 last, chain, i);
 938
 939                 if (last)
 940                         break;
 941         }
 942 }
 943
 944 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 945                 struct dwc3_request *req, unsigned int trbs_left)
 946 {
 947         unsigned int    last = false;
 948         unsigned int    length;
 949         dma_addr_t      dma;
 950
 951         dma = req->request.dma;
 952         length = req->request.length;
 953
 954         if (!trbs_left)
 955                 last = true;
 956
 957         /* Is this the last request? */
 958         if (list_is_last(&req->list, &dep->pending_list))
 959                 last = true;
 960
 961         dwc3_prepare_one_trb(dep, req, dma, length,
 962                         last, false, 0);
 963 }
 964
 965 /*
 966  * dwc3_prepare_trbs - setup TRBs from requests
 967  * @dep: endpoint for which requests are being prepared
 968  *
 969  * The function goes through the requests list and sets up TRBs for the
 970  * transfers. The function returns once there are no more TRBs available or
 971  * it runs out of requests.
 972  */
 973 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 974 {
 975         struct dwc3_request     *req, *n;
 976         u32                     trbs_left;
 977
 978         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 979
 980         trbs_left = dwc3_calc_trbs_left(dep);
 981
 982         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 983                 if (req->request.num_mapped_sgs > 0)
 984                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
 985                 else
 986                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
 987
 988                 if (!trbs_left)
 989                         return;
 990         }
 991 }
 992
 993 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 994 {
 995         struct dwc3_gadget_ep_cmd_params params;
 996         struct dwc3_request             *req;
 997         struct dwc3                     *dwc = dep->dwc;
 998         int                             starting;
 999         int                             ret;
1000         u32                             cmd;
1001
1002         starting = !(dep->flags & DWC3_EP_BUSY);
1003
1004         dwc3_prepare_trbs(dep);
1005         req = next_request(&dep->started_list);
1006         if (!req) {
1007                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1008                 return 0;
1009         }
1010
1011         memset(&params, 0, sizeof(params));
1012
1013         if (starting) {
1014                 params.param0 = upper_32_bits(req->trb_dma);
1015                 params.param1 = lower_32_bits(req->trb_dma);
1016                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1017         } else {
1018                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1019         }
1020
1021         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1022         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1023         if (ret < 0) {
1024                 /*
1025                  * FIXME we need to iterate over the list of requests
1026                  * here and stop, unmap, free and del each of the linked
1027                  * requests instead of what we do now.
1028                  */
1029                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1030                                 req->direction);
1031                 list_del(&req->list);
1032                 return ret;
1033         }
1034
1035         dep->flags |= DWC3_EP_BUSY;
1036
1037         if (starting) {
1038                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1039                                 dep->number);
1040                 WARN_ON_ONCE(!dep->resource_index);
1041         }
1042
1043         return 0;
1044 }
1045
1046 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1047                 struct dwc3_ep *dep, u32 cur_uf)
1048 {
1049         u32 uf;
1050
1051         if (list_empty(&dep->pending_list)) {
1052                 dwc3_trace(trace_dwc3_gadget,
1053                                 "ISOC ep %s run out for requests",
1054                                 dep->name);
1055                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1056                 return;
1057         }
1058
1059         /* 4 micro frames in the future */
1060         uf = cur_uf + dep->interval * 4;
1061
1062         __dwc3_gadget_kick_transfer(dep, uf);
1063 }
1064
1065 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1066                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1067 {
1068         u32 cur_uf, mask;
1069
1070         mask = ~(dep->interval - 1);
1071         cur_uf = event->parameters & mask;
1072
1073         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1074 }
1075
1076 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1077 {
1078         struct dwc3             *dwc = dep->dwc;
1079         int                     ret;
1080
1081         if (!dep->endpoint.desc) {
1082                 dwc3_trace(trace_dwc3_gadget,
1083                                 "trying to queue request %p to disabled %s\n",
1084                                 &req->request, dep->endpoint.name);
1085                 return -ESHUTDOWN;
1086         }
1087
1088         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1089                                 &req->request, req->dep->name)) {
1090                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1091                                 &req->request, req->dep->name);
1092                 return -EINVAL;
1093         }
1094
1095         req->request.actual     = 0;
1096         req->request.status     = -EINPROGRESS;
1097         req->direction          = dep->direction;
1098         req->epnum              = dep->number;
1099
1100         trace_dwc3_ep_queue(req);
1101
1102         /*
1103          * Per databook, the total size of buffer must be a multiple
1104          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1105          * configed for endpoints in dwc3_gadget_set_ep_config(),
1106          * set to usb_endpoint_descriptor->wMaxPacketSize.
1107          */
1108         if (dep->direction == 0 &&
1109             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1110                 req->request.length = roundup(req->request.length,
1111                                         dep->endpoint.desc->wMaxPacketSize);
1112
1113         /*
1114          * We only add to our list of requests now and
1115          * start consuming the list once we get XferNotReady
1116          * IRQ.
1117          *
1118          * That way, we avoid doing anything that we don't need
1119          * to do now and defer it until the point we receive a
1120          * particular token from the Host side.
1121          *
1122          * This will also avoid Host cancelling URBs due to too
1123          * many NAKs.
1124          */
1125         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1126                         dep->direction);
1127         if (ret)
1128                 return ret;
1129
1130         list_add_tail(&req->list, &dep->pending_list);
1131
1132         /*
1133          * If there are no pending requests and the endpoint isn't already
1134          * busy, we will just start the request straight away.
1135          *
1136          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1137          * little bit faster.
1138          */
1139         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1140                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1141                         !(dep->flags & DWC3_EP_BUSY)) {
1142                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1143                 goto out;
1144         }
1145
1146         /*
1147          * There are a few special cases:
1148          *
1149          * 1. XferNotReady with empty list of requests. We need to kick the
1150          *    transfer here in that situation, otherwise we will be NAKing
1151          *    forever. If we get XferNotReady before gadget driver has a
1152          *    chance to queue a request, we will ACK the IRQ but won't be
1153          *    able to receive the data until the next request is queued.
1154          *    The following code is handling exactly that.
1155          *
1156          */
1157         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1158                 /*
1159                  * If xfernotready is already elapsed and it is a case
1160                  * of isoc transfer, then issue END TRANSFER, so that
1161                  * you can receive xfernotready again and can have
1162                  * notion of current microframe.
1163                  */
1164                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1165                         if (list_empty(&dep->started_list)) {
1166                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1167                                 dep->flags = DWC3_EP_ENABLED;
1168                         }
1169                         return 0;
1170                 }
1171
1172                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1173                 if (!ret)
1174                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1175
1176                 goto out;
1177         }
1178
1179         /*
1180          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1181          *    kick the transfer here after queuing a request, otherwise the
1182          *    core may not see the modified TRB(s).
1183          */
1184         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1185                         (dep->flags & DWC3_EP_BUSY) &&
1186                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1187                 WARN_ON_ONCE(!dep->resource_index);
1188                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1189                 goto out;
1190         }
1191
1192         /*
1193          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1194          * right away, otherwise host will not know we have streams to be
1195          * handled.
1196          */
1197         if (dep->stream_capable)
1198                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1199
1200 out:
1201         if (ret && ret != -EBUSY)
1202                 dwc3_trace(trace_dwc3_gadget,
1203                                 "%s: failed to kick transfers\n",
1204                                 dep->name);
1205         if (ret == -EBUSY)
1206                 ret = 0;
1207
1208         return ret;
1209 }
1210
1211 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1212                 struct usb_request *request)
1213 {
1214         dwc3_gadget_ep_free_request(ep, request);
1215 }
1216
1217 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1218 {
1219         struct dwc3_request             *req;
1220         struct usb_request              *request;
1221         struct usb_ep                   *ep = &dep->endpoint;
1222
1223         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1224         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1225         if (!request)
1226                 return -ENOMEM;
1227
1228         request->length = 0;
1229         request->buf = dwc->zlp_buf;
1230         request->complete = __dwc3_gadget_ep_zlp_complete;
1231
1232         req = to_dwc3_request(request);
1233
1234         return __dwc3_gadget_ep_queue(dep, req);
1235 }
1236
1237 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1238         gfp_t gfp_flags)
1239 {
1240         struct dwc3_request             *req = to_dwc3_request(request);
1241         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1242         struct dwc3                     *dwc = dep->dwc;
1243
1244         unsigned long                   flags;
1245
1246         int                             ret;
1247
1248         spin_lock_irqsave(&dwc->lock, flags);
1249         ret = __dwc3_gadget_ep_queue(dep, req);
1250
1251         /*
1252          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1253          * setting request->zero, instead of doing magic, we will just queue an
1254          * extra usb_request ourselves so that it gets handled the same way as
1255          * any other request.
1256          */
1257         if (ret == 0 && request->zero && request->length &&
1258             (request->length % ep->desc->wMaxPacketSize == 0))
1259                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1260
1261         spin_unlock_irqrestore(&dwc->lock, flags);
1262
1263         return ret;
1264 }
1265
1266 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1267                 struct usb_request *request)
1268 {
1269         struct dwc3_request             *req = to_dwc3_request(request);
1270         struct dwc3_request             *r = NULL;
1271
1272         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1273         struct dwc3                     *dwc = dep->dwc;
1274
1275         unsigned long                   flags;
1276         int                             ret = 0;
1277
1278         trace_dwc3_ep_dequeue(req);
1279
1280         spin_lock_irqsave(&dwc->lock, flags);
1281
1282         list_for_each_entry(r, &dep->pending_list, list) {
1283                 if (r == req)
1284                         break;
1285         }
1286
1287         if (r != req) {
1288                 list_for_each_entry(r, &dep->started_list, list) {
1289                         if (r == req)
1290                                 break;
1291                 }
1292                 if (r == req) {
1293                         /* wait until it is processed */
1294                         dwc3_stop_active_transfer(dwc, dep->number, true);
1295                         goto out1;
1296                 }
1297                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1298                                 request, ep->name);
1299                 ret = -EINVAL;
1300                 goto out0;
1301         }
1302
1303 out1:
1304         /* giveback the request */
1305         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1306
1307 out0:
1308         spin_unlock_irqrestore(&dwc->lock, flags);
1309
1310         return ret;
1311 }
1312
1313 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1314 {
1315         struct dwc3_gadget_ep_cmd_params        params;
1316         struct dwc3                             *dwc = dep->dwc;
1317         int                                     ret;
1318
1319         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1320                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1321                 return -EINVAL;
1322         }
1323
1324         memset(&params, 0x00, sizeof(params));
1325
1326         if (value) {
1327                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1328                                 (!list_empty(&dep->started_list) ||
1329                                  !list_empty(&dep->pending_list)))) {
1330                         dwc3_trace(trace_dwc3_gadget,
1331                                         "%s: pending request, cannot halt",
1332                                         dep->name);
1333                         return -EAGAIN;
1334                 }
1335
1336                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1337                         DWC3_DEPCMD_SETSTALL, &params);
1338                 if (ret)
1339                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1340                                         dep->name);
1341                 else
1342                         dep->flags |= DWC3_EP_STALL;
1343         } else {
1344                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1345                 if (ret)
1346                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1347                                         dep->name);
1348                 else
1349                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1350         }
1351
1352         return ret;
1353 }
1354
1355 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1356 {
1357         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1358         struct dwc3                     *dwc = dep->dwc;
1359
1360         unsigned long                   flags;
1361
1362         int                             ret;
1363
1364         spin_lock_irqsave(&dwc->lock, flags);
1365         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1366         spin_unlock_irqrestore(&dwc->lock, flags);
1367
1368         return ret;
1369 }
1370
1371 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1372 {
1373         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1374         struct dwc3                     *dwc = dep->dwc;
1375         unsigned long                   flags;
1376         int                             ret;
1377
1378         spin_lock_irqsave(&dwc->lock, flags);
1379         dep->flags |= DWC3_EP_WEDGE;
1380
1381         if (dep->number == 0 || dep->number == 1)
1382                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1383         else
1384                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1385         spin_unlock_irqrestore(&dwc->lock, flags);
1386
1387         return ret;
1388 }
1389
1390 /* -------------------------------------------------------------------------- */
1391
1392 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1393         .bLength        = USB_DT_ENDPOINT_SIZE,
1394         .bDescriptorType = USB_DT_ENDPOINT,
1395         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1396 };
1397
1398 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1399         .enable         = dwc3_gadget_ep0_enable,
1400         .disable        = dwc3_gadget_ep0_disable,
1401         .alloc_request  = dwc3_gadget_ep_alloc_request,
1402         .free_request   = dwc3_gadget_ep_free_request,
1403         .queue          = dwc3_gadget_ep0_queue,
1404         .dequeue        = dwc3_gadget_ep_dequeue,
1405         .set_halt       = dwc3_gadget_ep0_set_halt,
1406         .set_wedge      = dwc3_gadget_ep_set_wedge,
1407 };
1408
1409 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1410         .enable         = dwc3_gadget_ep_enable,
1411         .disable        = dwc3_gadget_ep_disable,
1412         .alloc_request  = dwc3_gadget_ep_alloc_request,
1413         .free_request   = dwc3_gadget_ep_free_request,
1414         .queue          = dwc3_gadget_ep_queue,
1415         .dequeue        = dwc3_gadget_ep_dequeue,
1416         .set_halt       = dwc3_gadget_ep_set_halt,
1417         .set_wedge      = dwc3_gadget_ep_set_wedge,
1418 };
1419
1420 /* -------------------------------------------------------------------------- */
1421
1422 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1423 {
1424         struct dwc3             *dwc = gadget_to_dwc(g);
1425         u32                     reg;
1426
1427         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1428         return DWC3_DSTS_SOFFN(reg);
1429 }
1430
1431 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1432 {
1433         unsigned long           timeout;
1434
1435         int                     ret;
1436         u32                     reg;
1437
1438         u8                      link_state;
1439         u8                      speed;
1440
1441         /*
1442          * According to the Databook Remote wakeup request should
1443          * be issued only when the device is in early suspend state.
1444          *
1445          * We can check that via USB Link State bits in DSTS register.
1446          */
1447         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1448
1449         speed = reg & DWC3_DSTS_CONNECTSPD;
1450         if (speed == DWC3_DSTS_SUPERSPEED) {
1451                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1452                 return 0;
1453         }
1454
1455         link_state = DWC3_DSTS_USBLNKST(reg);
1456
1457         switch (link_state) {
1458         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1459         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1460                 break;
1461         default:
1462                 dwc3_trace(trace_dwc3_gadget,
1463                                 "can't wakeup from '%s'\n",
1464                                 dwc3_gadget_link_string(link_state));
1465                 return -EINVAL;
1466         }
1467
1468         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1469         if (ret < 0) {
1470                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1471                 return ret;
1472         }
1473
1474         /* Recent versions do this automatically */
1475         if (dwc->revision < DWC3_REVISION_194A) {
1476                 /* write zeroes to Link Change Request */
1477                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1478                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1479                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1480         }
1481
1482         /* poll until Link State changes to ON */
1483         timeout = jiffies + msecs_to_jiffies(100);
1484
1485         while (!time_after(jiffies, timeout)) {
1486                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1487
1488                 /* in HS, means ON */
1489                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1490                         break;
1491         }
1492
1493         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1494                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1495                 return -EINVAL;
1496         }
1497
1498         return 0;
1499 }
1500
1501 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1502 {
1503         struct dwc3             *dwc = gadget_to_dwc(g);
1504         unsigned long           flags;
1505         int                     ret;
1506
1507         spin_lock_irqsave(&dwc->lock, flags);
1508         ret = __dwc3_gadget_wakeup(dwc);
1509         spin_unlock_irqrestore(&dwc->lock, flags);
1510
1511         return ret;
1512 }
1513
1514 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1515                 int is_selfpowered)
1516 {
1517         struct dwc3             *dwc = gadget_to_dwc(g);
1518         unsigned long           flags;
1519
1520         spin_lock_irqsave(&dwc->lock, flags);
1521         g->is_selfpowered = !!is_selfpowered;
1522         spin_unlock_irqrestore(&dwc->lock, flags);
1523
1524         return 0;
1525 }
1526
1527 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1528 {
1529         u32                     reg;
1530         u32                     timeout = 500;
1531
1532         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1533         if (is_on) {
1534                 if (dwc->revision <= DWC3_REVISION_187A) {
1535                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1536                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1537                 }
1538
1539                 if (dwc->revision >= DWC3_REVISION_194A)
1540                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1541                 reg |= DWC3_DCTL_RUN_STOP;
1542
1543                 if (dwc->has_hibernation)
1544                         reg |= DWC3_DCTL_KEEP_CONNECT;
1545
1546                 dwc->pullups_connected = true;
1547         } else {
1548                 reg &= ~DWC3_DCTL_RUN_STOP;
1549
1550                 if (dwc->has_hibernation && !suspend)
1551                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1552
1553                 dwc->pullups_connected = false;
1554         }
1555
1556         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1557
1558         do {
1559                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1560                 if (is_on) {
1561                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1562                                 break;
1563                 } else {
1564                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1565                                 break;
1566                 }
1567                 timeout--;
1568                 if (!timeout)
1569                         return -ETIMEDOUT;
1570                 udelay(1);
1571         } while (1);
1572
1573         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1574                         dwc->gadget_driver
1575                         ? dwc->gadget_driver->function : "no-function",
1576                         is_on ? "connect" : "disconnect");
1577
1578         return 0;
1579 }
1580
1581 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1582 {
1583         struct dwc3             *dwc = gadget_to_dwc(g);
1584         unsigned long           flags;
1585         int                     ret;
1586
1587         is_on = !!is_on;
1588
1589         spin_lock_irqsave(&dwc->lock, flags);
1590         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1591         spin_unlock_irqrestore(&dwc->lock, flags);
1592
1593         return ret;
1594 }
1595
1596 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1597 {
1598         u32                     reg;
1599
1600         /* Enable all but Start and End of Frame IRQs */
1601         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1602                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1603                         DWC3_DEVTEN_CMDCMPLTEN |
1604                         DWC3_DEVTEN_ERRTICERREN |
1605                         DWC3_DEVTEN_WKUPEVTEN |
1606                         DWC3_DEVTEN_ULSTCNGEN |
1607                         DWC3_DEVTEN_CONNECTDONEEN |
1608                         DWC3_DEVTEN_USBRSTEN |
1609                         DWC3_DEVTEN_DISCONNEVTEN);
1610
1611         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1612 }
1613
1614 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1615 {
1616         /* mask all interrupts */
1617         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1618 }
1619
1620 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1621 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1622
1623 static int __dwc3_gadget_start(struct dwc3 *dwc)
1624 {
1625         struct dwc3_ep          *dep;
1626         int                     ret = 0;
1627         u32                     reg;
1628
1629         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1630         reg &= ~(DWC3_DCFG_SPEED_MASK);
1631
1632         /**
1633          * WORKAROUND: DWC3 revision < 2.20a have an issue
1634          * which would cause metastability state on Run/Stop
1635          * bit if we try to force the IP to USB2-only mode.
1636          *
1637          * Because of that, we cannot configure the IP to any
1638          * speed other than the SuperSpeed
1639          *
1640          * Refers to:
1641          *
1642          * STAR#9000525659: Clock Domain Crossing on DCTL in
1643          * USB 2.0 Mode
1644          */
1645         if (dwc->revision < DWC3_REVISION_220A) {
1646                 reg |= DWC3_DCFG_SUPERSPEED;
1647         } else {
1648                 switch (dwc->maximum_speed) {
1649                 case USB_SPEED_LOW:
1650                         reg |= DWC3_DSTS_LOWSPEED;
1651                         break;
1652                 case USB_SPEED_FULL:
1653                         reg |= DWC3_DSTS_FULLSPEED1;
1654                         break;
1655                 case USB_SPEED_HIGH:
1656                         reg |= DWC3_DSTS_HIGHSPEED;
1657                         break;
1658                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1659                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1660                 default:
1661                         reg |= DWC3_DSTS_SUPERSPEED;
1662                 }
1663         }
1664         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1665
1666         /*
1667          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1668          * field instead of letting dwc3 itself calculate that automatically.
1669          *
1670          * This way, we maximize the chances that we'll be able to get several
1671          * bursts of data without going through any sort of endpoint throttling.
1672          */
1673         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1674         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1675         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1676
1677         /* Start with SuperSpeed Default */
1678         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1679
1680         dep = dwc->eps[0];
1681         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1682                         false);
1683         if (ret) {
1684                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1685                 goto err0;
1686         }
1687
1688         dep = dwc->eps[1];
1689         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690                         false);
1691         if (ret) {
1692                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693                 goto err1;
1694         }
1695
1696         /* begin to receive SETUP packets */
1697         dwc->ep0state = EP0_SETUP_PHASE;
1698         dwc3_ep0_out_start(dwc);
1699
1700         dwc3_gadget_enable_irq(dwc);
1701
1702         return 0;
1703
1704 err1:
1705         __dwc3_gadget_ep_disable(dwc->eps[0]);
1706
1707 err0:
1708         return ret;
1709 }
1710
1711 static int dwc3_gadget_start(struct usb_gadget *g,
1712                 struct usb_gadget_driver *driver)
1713 {
1714         struct dwc3             *dwc = gadget_to_dwc(g);
1715         unsigned long           flags;
1716         int                     ret = 0;
1717         int                     irq;
1718
1719         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1720         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1721                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1722         if (ret) {
1723                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1724                                 irq, ret);
1725                 goto err0;
1726         }
1727
1728         spin_lock_irqsave(&dwc->lock, flags);
1729         if (dwc->gadget_driver) {
1730                 dev_err(dwc->dev, "%s is already bound to %s\n",
1731                                 dwc->gadget.name,
1732                                 dwc->gadget_driver->driver.name);
1733                 ret = -EBUSY;
1734                 goto err1;
1735         }
1736
1737         dwc->gadget_driver      = driver;
1738
1739         __dwc3_gadget_start(dwc);
1740         spin_unlock_irqrestore(&dwc->lock, flags);
1741
1742         return 0;
1743
1744 err1:
1745         spin_unlock_irqrestore(&dwc->lock, flags);
1746         free_irq(irq, dwc);
1747
1748 err0:
1749         return ret;
1750 }
1751
1752 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1753 {
1754         dwc3_gadget_disable_irq(dwc);
1755         __dwc3_gadget_ep_disable(dwc->eps[0]);
1756         __dwc3_gadget_ep_disable(dwc->eps[1]);
1757 }
1758
1759 static int dwc3_gadget_stop(struct usb_gadget *g)
1760 {
1761         struct dwc3             *dwc = gadget_to_dwc(g);
1762         unsigned long           flags;
1763         int                     irq;
1764
1765         spin_lock_irqsave(&dwc->lock, flags);
1766         __dwc3_gadget_stop(dwc);
1767         dwc->gadget_driver      = NULL;
1768         spin_unlock_irqrestore(&dwc->lock, flags);
1769
1770         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1771         free_irq(irq, dwc->ev_buf);
1772
1773         return 0;
1774 }
1775
1776 static const struct usb_gadget_ops dwc3_gadget_ops = {
1777         .get_frame              = dwc3_gadget_get_frame,
1778         .wakeup                 = dwc3_gadget_wakeup,
1779         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1780         .pullup                 = dwc3_gadget_pullup,
1781         .udc_start              = dwc3_gadget_start,
1782         .udc_stop               = dwc3_gadget_stop,
1783 };
1784
1785 /* -------------------------------------------------------------------------- */
1786
1787 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1788                 u8 num, u32 direction)
1789 {
1790         struct dwc3_ep                  *dep;
1791         u8                              i;
1792
1793         for (i = 0; i < num; i++) {
1794                 u8 epnum = (i << 1) | (!!direction);
1795
1796                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1797                 if (!dep)
1798                         return -ENOMEM;
1799
1800                 dep->dwc = dwc;
1801                 dep->number = epnum;
1802                 dep->direction = !!direction;
1803                 dwc->eps[epnum] = dep;
1804
1805                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1806                                 (epnum & 1) ? "in" : "out");
1807
1808                 dep->endpoint.name = dep->name;
1809
1810                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1811
1812                 if (epnum == 0 || epnum == 1) {
1813                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1814                         dep->endpoint.maxburst = 1;
1815                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1816                         if (!epnum)
1817                                 dwc->gadget.ep0 = &dep->endpoint;
1818                 } else {
1819                         int             ret;
1820
1821                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1822                         dep->endpoint.max_streams = 15;
1823                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1824                         list_add_tail(&dep->endpoint.ep_list,
1825                                         &dwc->gadget.ep_list);
1826
1827                         ret = dwc3_alloc_trb_pool(dep);
1828                         if (ret)
1829                                 return ret;
1830                 }
1831
1832                 if (epnum == 0 || epnum == 1) {
1833                         dep->endpoint.caps.type_control = true;
1834                 } else {
1835                         dep->endpoint.caps.type_iso = true;
1836                         dep->endpoint.caps.type_bulk = true;
1837                         dep->endpoint.caps.type_int = true;
1838                 }
1839
1840                 dep->endpoint.caps.dir_in = !!direction;
1841                 dep->endpoint.caps.dir_out = !direction;
1842
1843                 INIT_LIST_HEAD(&dep->pending_list);
1844                 INIT_LIST_HEAD(&dep->started_list);
1845         }
1846
1847         return 0;
1848 }
1849
1850 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1851 {
1852         int                             ret;
1853
1854         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1855
1856         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1857         if (ret < 0) {
1858                 dwc3_trace(trace_dwc3_gadget,
1859                                 "failed to allocate OUT endpoints");
1860                 return ret;
1861         }
1862
1863         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1864         if (ret < 0) {
1865                 dwc3_trace(trace_dwc3_gadget,
1866                                 "failed to allocate IN endpoints");
1867                 return ret;
1868         }
1869
1870         return 0;
1871 }
1872
1873 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1874 {
1875         struct dwc3_ep                  *dep;
1876         u8                              epnum;
1877
1878         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1879                 dep = dwc->eps[epnum];
1880                 if (!dep)
1881                         continue;
1882                 /*
1883                  * Physical endpoints 0 and 1 are special; they form the
1884                  * bi-directional USB endpoint 0.
1885                  *
1886                  * For those two physical endpoints, we don't allocate a TRB
1887                  * pool nor do we add them the endpoints list. Due to that, we
1888                  * shouldn't do these two operations otherwise we would end up
1889                  * with all sorts of bugs when removing dwc3.ko.
1890                  */
1891                 if (epnum != 0 && epnum != 1) {
1892                         dwc3_free_trb_pool(dep);
1893                         list_del(&dep->endpoint.ep_list);
1894                 }
1895
1896                 kfree(dep);
1897         }
1898 }
1899
1900 /* -------------------------------------------------------------------------- */
1901
1902 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1903                 struct dwc3_request *req, struct dwc3_trb *trb,
1904                 const struct dwc3_event_depevt *event, int status)
1905 {
1906         unsigned int            count;
1907         unsigned int            s_pkt = 0;
1908         unsigned int            trb_status;
1909
1910         trace_dwc3_complete_trb(dep, trb);
1911
1912         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1913                 /*
1914                  * We continue despite the error. There is not much we
1915                  * can do. If we don't clean it up we loop forever. If
1916                  * we skip the TRB then it gets overwritten after a
1917                  * while since we use them in a ring buffer. A BUG()
1918                  * would help. Lets hope that if this occurs, someone
1919                  * fixes the root cause instead of looking away :)
1920                  */
1921                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1922                                 dep->name, trb);
1923         count = trb->size & DWC3_TRB_SIZE_MASK;
1924
1925         if (dep->direction) {
1926                 if (count) {
1927                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1928                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1929                                 dwc3_trace(trace_dwc3_gadget,
1930                                                 "%s: incomplete IN transfer\n",
1931                                                 dep->name);
1932                                 /*
1933                                  * If missed isoc occurred and there is
1934                                  * no request queued then issue END
1935                                  * TRANSFER, so that core generates
1936                                  * next xfernotready and we will issue
1937                                  * a fresh START TRANSFER.
1938                                  * If there are still queued request
1939                                  * then wait, do not issue either END
1940                                  * or UPDATE TRANSFER, just attach next
1941                                  * request in pending_list during
1942                                  * giveback.If any future queued request
1943                                  * is successfully transferred then we
1944                                  * will issue UPDATE TRANSFER for all
1945                                  * request in the pending_list.
1946                                  */
1947                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1948                         } else {
1949                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1950                                                 dep->name);
1951                                 status = -ECONNRESET;
1952                         }
1953                 } else {
1954                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1955                 }
1956         } else {
1957                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1958                         s_pkt = 1;
1959         }
1960
1961         /*
1962          * We assume here we will always receive the entire data block
1963          * which we should receive. Meaning, if we program RX to
1964          * receive 4K but we receive only 2K, we assume that's all we
1965          * should receive and we simply bounce the request back to the
1966          * gadget driver for further processing.
1967          */
1968         req->request.actual += req->request.length - count;
1969         if (s_pkt)
1970                 return 1;
1971         if ((event->status & DEPEVT_STATUS_LST) &&
1972                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1973                                 DWC3_TRB_CTRL_HWO)))
1974                 return 1;
1975         if ((event->status & DEPEVT_STATUS_IOC) &&
1976                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1977                 return 1;
1978         return 0;
1979 }
1980
1981 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1982                 const struct dwc3_event_depevt *event, int status)
1983 {
1984         struct dwc3_request     *req;
1985         struct dwc3_trb         *trb;
1986         unsigned int            slot;
1987         unsigned int            i;
1988         int                     ret;
1989
1990         do {
1991                 req = next_request(&dep->started_list);
1992                 if (WARN_ON_ONCE(!req))
1993                         return 1;
1994
1995                 i = 0;
1996                 do {
1997                         slot = req->first_trb_index + i;
1998                         if (slot == DWC3_TRB_NUM - 1)
1999                                 slot++;
2000                         slot %= DWC3_TRB_NUM;
2001                         trb = &dep->trb_pool[slot];
2002
2003                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2004                                         event, status);
2005                         if (ret)
2006                                 break;
2007                 } while (++i < req->request.num_mapped_sgs);
2008
2009                 dwc3_gadget_giveback(dep, req, status);
2010
2011                 if (ret)
2012                         break;
2013         } while (1);
2014
2015         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2016                         list_empty(&dep->started_list)) {
2017                 if (list_empty(&dep->pending_list)) {
2018                         /*
2019                          * If there is no entry in request list then do
2020                          * not issue END TRANSFER now. Just set PENDING
2021                          * flag, so that END TRANSFER is issued when an
2022                          * entry is added into request list.
2023                          */
2024                         dep->flags = DWC3_EP_PENDING_REQUEST;
2025                 } else {
2026                         dwc3_stop_active_transfer(dwc, dep->number, true);
2027                         dep->flags = DWC3_EP_ENABLED;
2028                 }
2029                 return 1;
2030         }
2031
2032         return 1;
2033 }
2034
2035 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2036                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2037 {
2038         unsigned                status = 0;
2039         int                     clean_busy;
2040         u32                     is_xfer_complete;
2041
2042         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2043
2044         if (event->status & DEPEVT_STATUS_BUSERR)
2045                 status = -ECONNRESET;
2046
2047         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2048         if (clean_busy && (is_xfer_complete ||
2049                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2050                 dep->flags &= ~DWC3_EP_BUSY;
2051
2052         /*
2053          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2054          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2055          */
2056         if (dwc->revision < DWC3_REVISION_183A) {
2057                 u32             reg;
2058                 int             i;
2059
2060                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2061                         dep = dwc->eps[i];
2062
2063                         if (!(dep->flags & DWC3_EP_ENABLED))
2064                                 continue;
2065
2066                         if (!list_empty(&dep->started_list))
2067                                 return;
2068                 }
2069
2070                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2071                 reg |= dwc->u1u2;
2072                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2073
2074                 dwc->u1u2 = 0;
2075         }
2076
2077         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2078                 int ret;
2079
2080                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2081                 if (!ret || ret == -EBUSY)
2082                         return;
2083         }
2084 }
2085
2086 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2087                 const struct dwc3_event_depevt *event)
2088 {
2089         struct dwc3_ep          *dep;
2090         u8                      epnum = event->endpoint_number;
2091
2092         dep = dwc->eps[epnum];
2093
2094         if (!(dep->flags & DWC3_EP_ENABLED))
2095                 return;
2096
2097         if (epnum == 0 || epnum == 1) {
2098                 dwc3_ep0_interrupt(dwc, event);
2099                 return;
2100         }
2101
2102         switch (event->endpoint_event) {
2103         case DWC3_DEPEVT_XFERCOMPLETE:
2104                 dep->resource_index = 0;
2105
2106                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2107                         dwc3_trace(trace_dwc3_gadget,
2108                                         "%s is an Isochronous endpoint\n",
2109                                         dep->name);
2110                         return;
2111                 }
2112
2113                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2114                 break;
2115         case DWC3_DEPEVT_XFERINPROGRESS:
2116                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2117                 break;
2118         case DWC3_DEPEVT_XFERNOTREADY:
2119                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2120                         dwc3_gadget_start_isoc(dwc, dep, event);
2121                 } else {
2122                         int active;
2123                         int ret;
2124
2125                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2126
2127                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2128                                         dep->name, active ? "Transfer Active"
2129                                         : "Transfer Not Active");
2130
2131                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2132                         if (!ret || ret == -EBUSY)
2133                                 return;
2134
2135                         dwc3_trace(trace_dwc3_gadget,
2136                                         "%s: failed to kick transfers\n",
2137                                         dep->name);
2138                 }
2139
2140                 break;
2141         case DWC3_DEPEVT_STREAMEVT:
2142                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2143                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2144                                         dep->name);
2145                         return;
2146                 }
2147
2148                 switch (event->status) {
2149                 case DEPEVT_STREAMEVT_FOUND:
2150                         dwc3_trace(trace_dwc3_gadget,
2151                                         "Stream %d found and started",
2152                                         event->parameters);
2153
2154                         break;
2155                 case DEPEVT_STREAMEVT_NOTFOUND:
2156                         /* FALLTHROUGH */
2157                 default:
2158                         dwc3_trace(trace_dwc3_gadget,
2159                                         "unable to find suitable stream\n");
2160                 }
2161                 break;
2162         case DWC3_DEPEVT_RXTXFIFOEVT:
2163                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2164                 break;
2165         case DWC3_DEPEVT_EPCMDCMPLT:
2166                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2167                 break;
2168         }
2169 }
2170
2171 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2172 {
2173         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2174                 spin_unlock(&dwc->lock);
2175                 dwc->gadget_driver->disconnect(&dwc->gadget);
2176                 spin_lock(&dwc->lock);
2177         }
2178 }
2179
2180 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2181 {
2182         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2183                 spin_unlock(&dwc->lock);
2184                 dwc->gadget_driver->suspend(&dwc->gadget);
2185                 spin_lock(&dwc->lock);
2186         }
2187 }
2188
2189 static void dwc3_resume_gadget(struct dwc3 *dwc)
2190 {
2191         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2192                 spin_unlock(&dwc->lock);
2193                 dwc->gadget_driver->resume(&dwc->gadget);
2194                 spin_lock(&dwc->lock);
2195         }
2196 }
2197
2198 static void dwc3_reset_gadget(struct dwc3 *dwc)
2199 {
2200         if (!dwc->gadget_driver)
2201                 return;
2202
2203         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2204                 spin_unlock(&dwc->lock);
2205                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2206                 spin_lock(&dwc->lock);
2207         }
2208 }
2209
2210 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2211 {
2212         struct dwc3_ep *dep;
2213         struct dwc3_gadget_ep_cmd_params params;
2214         u32 cmd;
2215         int ret;
2216
2217         dep = dwc->eps[epnum];
2218
2219         if (!dep->resource_index)
2220                 return;
2221
2222         /*
2223          * NOTICE: We are violating what the Databook says about the
2224          * EndTransfer command. Ideally we would _always_ wait for the
2225          * EndTransfer Command Completion IRQ, but that's causing too
2226          * much trouble synchronizing between us and gadget driver.
2227          *
2228          * We have discussed this with the IP Provider and it was
2229          * suggested to giveback all requests here, but give HW some
2230          * extra time to synchronize with the interconnect. We're using
2231          * an arbitrary 100us delay for that.
2232          *
2233          * Note also that a similar handling was tested by Synopsys
2234          * (thanks a lot Paul) and nothing bad has come out of it.
2235          * In short, what we're doing is:
2236          *
2237          * - Issue EndTransfer WITH CMDIOC bit set
2238          * - Wait 100us
2239          */
2240
2241         cmd = DWC3_DEPCMD_ENDTRANSFER;
2242         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2243         cmd |= DWC3_DEPCMD_CMDIOC;
2244         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2245         memset(&params, 0, sizeof(params));
2246         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2247         WARN_ON_ONCE(ret);
2248         dep->resource_index = 0;
2249         dep->flags &= ~DWC3_EP_BUSY;
2250         udelay(100);
2251 }
2252
2253 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2254 {
2255         u32 epnum;
2256
2257         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2258                 struct dwc3_ep *dep;
2259
2260                 dep = dwc->eps[epnum];
2261                 if (!dep)
2262                         continue;
2263
2264                 if (!(dep->flags & DWC3_EP_ENABLED))
2265                         continue;
2266
2267                 dwc3_remove_requests(dwc, dep);
2268         }
2269 }
2270
2271 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2272 {
2273         u32 epnum;
2274
2275         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2276                 struct dwc3_ep *dep;
2277                 int ret;
2278
2279                 dep = dwc->eps[epnum];
2280                 if (!dep)
2281                         continue;
2282
2283                 if (!(dep->flags & DWC3_EP_STALL))
2284                         continue;
2285
2286                 dep->flags &= ~DWC3_EP_STALL;
2287
2288                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2289                 WARN_ON_ONCE(ret);
2290         }
2291 }
2292
2293 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2294 {
2295         int                     reg;
2296
2297         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2298         reg &= ~DWC3_DCTL_INITU1ENA;
2299         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2300
2301         reg &= ~DWC3_DCTL_INITU2ENA;
2302         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2303
2304         dwc3_disconnect_gadget(dwc);
2305
2306         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2307         dwc->setup_packet_pending = false;
2308         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2309 }
2310
2311 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2312 {
2313         u32                     reg;
2314
2315         /*
2316          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2317          * would cause a missing Disconnect Event if there's a
2318          * pending Setup Packet in the FIFO.
2319          *
2320          * There's no suggested workaround on the official Bug
2321          * report, which states that "unless the driver/application
2322          * is doing any special handling of a disconnect event,
2323          * there is no functional issue".
2324          *
2325          * Unfortunately, it turns out that we _do_ some special
2326          * handling of a disconnect event, namely complete all
2327          * pending transfers, notify gadget driver of the
2328          * disconnection, and so on.
2329          *
2330          * Our suggested workaround is to follow the Disconnect
2331          * Event steps here, instead, based on a setup_packet_pending
2332          * flag. Such flag gets set whenever we have a SETUP_PENDING
2333          * status for EP0 TRBs and gets cleared on XferComplete for the
2334          * same endpoint.
2335          *
2336          * Refers to:
2337          *
2338          * STAR#9000466709: RTL: Device : Disconnect event not
2339          * generated if setup packet pending in FIFO
2340          */
2341         if (dwc->revision < DWC3_REVISION_188A) {
2342                 if (dwc->setup_packet_pending)
2343                         dwc3_gadget_disconnect_interrupt(dwc);
2344         }
2345
2346         dwc3_reset_gadget(dwc);
2347
2348         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2349         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2350         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2351         dwc->test_mode = false;
2352
2353         dwc3_stop_active_transfers(dwc);
2354         dwc3_clear_stall_all_ep(dwc);
2355
2356         /* Reset device address to zero */
2357         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2358         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2359         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2360 }
2361
2362 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2363 {
2364         u32 reg;
2365         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2366
2367         /*
2368          * We change the clock only at SS but I dunno why I would want to do
2369          * this. Maybe it becomes part of the power saving plan.
2370          */
2371
2372         if (speed != DWC3_DSTS_SUPERSPEED)
2373                 return;
2374
2375         /*
2376          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2377          * each time on Connect Done.
2378          */
2379         if (!usb30_clock)
2380                 return;
2381
2382         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2383         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2384         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2385 }
2386
2387 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2388 {
2389         struct dwc3_ep          *dep;
2390         int                     ret;
2391         u32                     reg;
2392         u8                      speed;
2393
2394         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2395         speed = reg & DWC3_DSTS_CONNECTSPD;
2396         dwc->speed = speed;
2397
2398         dwc3_update_ram_clk_sel(dwc, speed);
2399
2400         switch (speed) {
2401         case DWC3_DCFG_SUPERSPEED:
2402                 /*
2403                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2404                  * would cause a missing USB3 Reset event.
2405                  *
2406                  * In such situations, we should force a USB3 Reset
2407                  * event by calling our dwc3_gadget_reset_interrupt()
2408                  * routine.
2409                  *
2410                  * Refers to:
2411                  *
2412                  * STAR#9000483510: RTL: SS : USB3 reset event may
2413                  * not be generated always when the link enters poll
2414                  */
2415                 if (dwc->revision < DWC3_REVISION_190A)
2416                         dwc3_gadget_reset_interrupt(dwc);
2417
2418                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2419                 dwc->gadget.ep0->maxpacket = 512;
2420                 dwc->gadget.speed = USB_SPEED_SUPER;
2421                 break;
2422         case DWC3_DCFG_HIGHSPEED:
2423                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2424                 dwc->gadget.ep0->maxpacket = 64;
2425                 dwc->gadget.speed = USB_SPEED_HIGH;
2426                 break;
2427         case DWC3_DCFG_FULLSPEED2:
2428         case DWC3_DCFG_FULLSPEED1:
2429                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2430                 dwc->gadget.ep0->maxpacket = 64;
2431                 dwc->gadget.speed = USB_SPEED_FULL;
2432                 break;
2433         case DWC3_DCFG_LOWSPEED:
2434                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2435                 dwc->gadget.ep0->maxpacket = 8;
2436                 dwc->gadget.speed = USB_SPEED_LOW;
2437                 break;
2438         }
2439
2440         /* Enable USB2 LPM Capability */
2441
2442         if ((dwc->revision > DWC3_REVISION_194A)
2443                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2444                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2445                 reg |= DWC3_DCFG_LPM_CAP;
2446                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2447
2448                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2449                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2450
2451                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2452
2453                 /*
2454                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2455                  * DCFG.LPMCap is set, core responses with an ACK and the
2456                  * BESL value in the LPM token is less than or equal to LPM
2457                  * NYET threshold.
2458                  */
2459                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2460                                 && dwc->has_lpm_erratum,
2461                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2462
2463                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2464                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2465
2466                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2467         } else {
2468                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2469                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2470                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2471         }
2472
2473         dep = dwc->eps[0];
2474         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2475                         false);
2476         if (ret) {
2477                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2478                 return;
2479         }
2480
2481         dep = dwc->eps[1];
2482         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2483                         false);
2484         if (ret) {
2485                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2486                 return;
2487         }
2488
2489         /*
2490          * Configure PHY via GUSB3PIPECTLn if required.
2491          *
2492          * Update GTXFIFOSIZn
2493          *
2494          * In both cases reset values should be sufficient.
2495          */
2496 }
2497
2498 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2499 {
2500         /*
2501          * TODO take core out of low power mode when that's
2502          * implemented.
2503          */
2504
2505         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2506                 spin_unlock(&dwc->lock);
2507                 dwc->gadget_driver->resume(&dwc->gadget);
2508                 spin_lock(&dwc->lock);
2509         }
2510 }
2511
2512 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2513                 unsigned int evtinfo)
2514 {
2515         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2516         unsigned int            pwropt;
2517
2518         /*
2519          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2520          * Hibernation mode enabled which would show up when device detects
2521          * host-initiated U3 exit.
2522          *
2523          * In that case, device will generate a Link State Change Interrupt
2524          * from U3 to RESUME which is only necessary if Hibernation is
2525          * configured in.
2526          *
2527          * There are no functional changes due to such spurious event and we
2528          * just need to ignore it.
2529          *
2530          * Refers to:
2531          *
2532          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2533          * operational mode
2534          */
2535         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2536         if ((dwc->revision < DWC3_REVISION_250A) &&
2537                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2538                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2539                                 (next == DWC3_LINK_STATE_RESUME)) {
2540                         dwc3_trace(trace_dwc3_gadget,
2541                                         "ignoring transition U3 -> Resume");
2542                         return;
2543                 }
2544         }
2545
2546         /*
2547          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2548          * on the link partner, the USB session might do multiple entry/exit
2549          * of low power states before a transfer takes place.
2550          *
2551          * Due to this problem, we might experience lower throughput. The
2552          * suggested workaround is to disable DCTL[12:9] bits if we're
2553          * transitioning from U1/U2 to U0 and enable those bits again
2554          * after a transfer completes and there are no pending transfers
2555          * on any of the enabled endpoints.
2556          *
2557          * This is the first half of that workaround.
2558          *
2559          * Refers to:
2560          *
2561          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2562          * core send LGO_Ux entering U0
2563          */
2564         if (dwc->revision < DWC3_REVISION_183A) {
2565                 if (next == DWC3_LINK_STATE_U0) {
2566                         u32     u1u2;
2567                         u32     reg;
2568
2569                         switch (dwc->link_state) {
2570                         case DWC3_LINK_STATE_U1:
2571                         case DWC3_LINK_STATE_U2:
2572                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2573                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2574                                                 | DWC3_DCTL_ACCEPTU2ENA
2575                                                 | DWC3_DCTL_INITU1ENA
2576                                                 | DWC3_DCTL_ACCEPTU1ENA);
2577
2578                                 if (!dwc->u1u2)
2579                                         dwc->u1u2 = reg & u1u2;
2580
2581                                 reg &= ~u1u2;
2582
2583                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2584                                 break;
2585                         default:
2586                                 /* do nothing */
2587                                 break;
2588                         }
2589                 }
2590         }
2591
2592         switch (next) {
2593         case DWC3_LINK_STATE_U1:
2594                 if (dwc->speed == USB_SPEED_SUPER)
2595                         dwc3_suspend_gadget(dwc);
2596                 break;
2597         case DWC3_LINK_STATE_U2:
2598         case DWC3_LINK_STATE_U3:
2599                 dwc3_suspend_gadget(dwc);
2600                 break;
2601         case DWC3_LINK_STATE_RESUME:
2602                 dwc3_resume_gadget(dwc);
2603                 break;
2604         default:
2605                 /* do nothing */
2606                 break;
2607         }
2608
2609         dwc->link_state = next;
2610 }
2611
2612 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2613                 unsigned int evtinfo)
2614 {
2615         unsigned int is_ss = evtinfo & BIT(4);
2616
2617         /**
2618          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2619          * have a known issue which can cause USB CV TD.9.23 to fail
2620          * randomly.
2621          *
2622          * Because of this issue, core could generate bogus hibernation
2623          * events which SW needs to ignore.
2624          *
2625          * Refers to:
2626          *
2627          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2628          * Device Fallback from SuperSpeed
2629          */
2630         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2631                 return;
2632
2633         /* enter hibernation here */
2634 }
2635
2636 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2637                 const struct dwc3_event_devt *event)
2638 {
2639         switch (event->type) {
2640         case DWC3_DEVICE_EVENT_DISCONNECT:
2641                 dwc3_gadget_disconnect_interrupt(dwc);
2642                 break;
2643         case DWC3_DEVICE_EVENT_RESET:
2644                 dwc3_gadget_reset_interrupt(dwc);
2645                 break;
2646         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2647                 dwc3_gadget_conndone_interrupt(dwc);
2648                 break;
2649         case DWC3_DEVICE_EVENT_WAKEUP:
2650                 dwc3_gadget_wakeup_interrupt(dwc);
2651                 break;
2652         case DWC3_DEVICE_EVENT_HIBER_REQ:
2653                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2654                                         "unexpected hibernation event\n"))
2655                         break;
2656
2657                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2658                 break;
2659         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2660                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2661                 break;
2662         case DWC3_DEVICE_EVENT_EOPF:
2663                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2664                 break;
2665         case DWC3_DEVICE_EVENT_SOF:
2666                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2667                 break;
2668         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2669                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2670                 break;
2671         case DWC3_DEVICE_EVENT_CMD_CMPL:
2672                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2673                 break;
2674         case DWC3_DEVICE_EVENT_OVERFLOW:
2675                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2676                 break;
2677         default:
2678                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2679         }
2680 }
2681
2682 static void dwc3_process_event_entry(struct dwc3 *dwc,
2683                 const union dwc3_event *event)
2684 {
2685         trace_dwc3_event(event->raw);
2686
2687         /* Endpoint IRQ, handle it and return early */
2688         if (event->type.is_devspec == 0) {
2689                 /* depevt */
2690                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2691         }
2692
2693         switch (event->type.type) {
2694         case DWC3_EVENT_TYPE_DEV:
2695                 dwc3_gadget_interrupt(dwc, &event->devt);
2696                 break;
2697         /* REVISIT what to do with Carkit and I2C events ? */
2698         default:
2699                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2700         }
2701 }
2702
2703 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2704 {
2705         struct dwc3 *dwc = evt->dwc;
2706         irqreturn_t ret = IRQ_NONE;
2707         int left;
2708         u32 reg;
2709
2710         left = evt->count;
2711
2712         if (!(evt->flags & DWC3_EVENT_PENDING))
2713                 return IRQ_NONE;
2714
2715         while (left > 0) {
2716                 union dwc3_event event;
2717
2718                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2719
2720                 dwc3_process_event_entry(dwc, &event);
2721
2722                 /*
2723                  * FIXME we wrap around correctly to the next entry as
2724                  * almost all entries are 4 bytes in size. There is one
2725                  * entry which has 12 bytes which is a regular entry
2726                  * followed by 8 bytes data. ATM I don't know how
2727                  * things are organized if we get next to the a
2728                  * boundary so I worry about that once we try to handle
2729                  * that.
2730                  */
2731                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2732                 left -= 4;
2733
2734                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2735         }
2736
2737         evt->count = 0;
2738         evt->flags &= ~DWC3_EVENT_PENDING;
2739         ret = IRQ_HANDLED;
2740
2741         /* Unmask interrupt */
2742         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2743         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2744         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2745
2746         return ret;
2747 }
2748
2749 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2750 {
2751         struct dwc3_event_buffer *evt = _evt;
2752         struct dwc3 *dwc = evt->dwc;
2753         unsigned long flags;
2754         irqreturn_t ret = IRQ_NONE;
2755
2756         spin_lock_irqsave(&dwc->lock, flags);
2757         ret = dwc3_process_event_buf(evt);
2758         spin_unlock_irqrestore(&dwc->lock, flags);
2759
2760         return ret;
2761 }
2762
2763 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2764 {
2765         struct dwc3 *dwc = evt->dwc;
2766         u32 count;
2767         u32 reg;
2768
2769         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2770         count &= DWC3_GEVNTCOUNT_MASK;
2771         if (!count)
2772                 return IRQ_NONE;
2773
2774         evt->count = count;
2775         evt->flags |= DWC3_EVENT_PENDING;
2776
2777         /* Mask interrupt */
2778         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2779         reg |= DWC3_GEVNTSIZ_INTMASK;
2780         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2781
2782         return IRQ_WAKE_THREAD;
2783 }
2784
2785 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2786 {
2787         struct dwc3_event_buffer        *evt = _evt;
2788
2789         return dwc3_check_event_buf(evt);
2790 }
2791
2792 /**
2793  * dwc3_gadget_init - Initializes gadget related registers
2794  * @dwc: pointer to our controller context structure
2795  *
2796  * Returns 0 on success otherwise negative errno.
2797  */
2798 int dwc3_gadget_init(struct dwc3 *dwc)
2799 {
2800         int                                     ret;
2801
2802         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2803                         &dwc->ctrl_req_addr, GFP_KERNEL);
2804         if (!dwc->ctrl_req) {
2805                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2806                 ret = -ENOMEM;
2807                 goto err0;
2808         }
2809
2810         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2811                         &dwc->ep0_trb_addr, GFP_KERNEL);
2812         if (!dwc->ep0_trb) {
2813                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2814                 ret = -ENOMEM;
2815                 goto err1;
2816         }
2817
2818         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2819         if (!dwc->setup_buf) {
2820                 ret = -ENOMEM;
2821                 goto err2;
2822         }
2823
2824         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2825                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2826                         GFP_KERNEL);
2827         if (!dwc->ep0_bounce) {
2828                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2829                 ret = -ENOMEM;
2830                 goto err3;
2831         }
2832
2833         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2834         if (!dwc->zlp_buf) {
2835                 ret = -ENOMEM;
2836                 goto err4;
2837         }
2838
2839         dwc->gadget.ops                 = &dwc3_gadget_ops;
2840         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2841         dwc->gadget.sg_supported        = true;
2842         dwc->gadget.name                = "dwc3-gadget";
2843         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2844
2845         /*
2846          * FIXME We might be setting max_speed to <SUPER, however versions
2847          * <2.20a of dwc3 have an issue with metastability (documented
2848          * elsewhere in this driver) which tells us we can't set max speed to
2849          * anything lower than SUPER.
2850          *
2851          * Because gadget.max_speed is only used by composite.c and function
2852          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2853          * to happen so we avoid sending SuperSpeed Capability descriptor
2854          * together with our BOS descriptor as that could confuse host into
2855          * thinking we can handle super speed.
2856          *
2857          * Note that, in fact, we won't even support GetBOS requests when speed
2858          * is less than super speed because we don't have means, yet, to tell
2859          * composite.c that we are USB 2.0 + LPM ECN.
2860          */
2861         if (dwc->revision < DWC3_REVISION_220A)
2862                 dwc3_trace(trace_dwc3_gadget,
2863                                 "Changing max_speed on rev %08x\n",
2864                                 dwc->revision);
2865
2866         dwc->gadget.max_speed           = dwc->maximum_speed;
2867
2868         /*
2869          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2870          * on ep out.
2871          */
2872         dwc->gadget.quirk_ep_out_aligned_size = true;
2873
2874         /*
2875          * REVISIT: Here we should clear all pending IRQs to be
2876          * sure we're starting from a well known location.
2877          */
2878
2879         ret = dwc3_gadget_init_endpoints(dwc);
2880         if (ret)
2881                 goto err5;
2882
2883         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2884         if (ret) {
2885                 dev_err(dwc->dev, "failed to register udc\n");
2886                 goto err5;
2887         }
2888
2889         return 0;
2890
2891 err5:
2892         kfree(dwc->zlp_buf);
2893
2894 err4:
2895         dwc3_gadget_free_endpoints(dwc);
2896         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2897                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2898
2899 err3:
2900         kfree(dwc->setup_buf);
2901
2902 err2:
2903         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2904                         dwc->ep0_trb, dwc->ep0_trb_addr);
2905
2906 err1:
2907         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2908                         dwc->ctrl_req, dwc->ctrl_req_addr);
2909
2910 err0:
2911         return ret;
2912 }
2913
2914 /* -------------------------------------------------------------------------- */
2915
2916 void dwc3_gadget_exit(struct dwc3 *dwc)
2917 {
2918         usb_del_gadget_udc(&dwc->gadget);
2919
2920         dwc3_gadget_free_endpoints(dwc);
2921
2922         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2923                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2924
2925         kfree(dwc->setup_buf);
2926         kfree(dwc->zlp_buf);
2927
2928         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2929                         dwc->ep0_trb, dwc->ep0_trb_addr);
2930
2931         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2932                         dwc->ctrl_req, dwc->ctrl_req_addr);
2933 }
2934
2935 int dwc3_gadget_suspend(struct dwc3 *dwc)
2936 {
2937         int ret;
2938
2939         if (!dwc->gadget_driver)
2940                 return 0;
2941
2942         ret = dwc3_gadget_run_stop(dwc, false, false);
2943         if (ret < 0)
2944                 return ret;
2945
2946         dwc3_disconnect_gadget(dwc);
2947         __dwc3_gadget_stop(dwc);
2948
2949         return 0;
2950 }
2951
2952 int dwc3_gadget_resume(struct dwc3 *dwc)
2953 {
2954         int                     ret;
2955
2956         if (!dwc->gadget_driver)
2957                 return 0;
2958
2959         ret = __dwc3_gadget_start(dwc);
2960         if (ret < 0)
2961                 goto err0;
2962
2963         ret = dwc3_gadget_run_stop(dwc, true, false);
2964         if (ret < 0)
2965                 goto err1;
2966
2967         return 0;
2968
2969 err1:
2970         __dwc3_gadget_stop(dwc);
2971
2972 err0:
2973         return ret;
2974 }