2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/kernel.h>
40 #include <linux/delay.h>
41 #include <linux/slab.h>
42 #include <linux/spinlock.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/interrupt.h>
47 #include <linux/list.h>
48 #include <linux/dma-mapping.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
58 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
59 * @dwc: pointer to our context structure
60 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
62 * Caller should take care of locking. This function will
63 * return 0 on success or -EINVAL if wrong Test Selector
66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
70 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
71 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
85 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
91 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
92 * @dwc: pointer to our context structure
93 * @state: the state to put link into
95 * Caller should take care of locking. This function will
96 * return 0 on success or -ETIMEDOUT.
98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
104 * Wait until device controller is ready. Only applies to 1.94a and
107 if (dwc->revision >= DWC3_REVISION_194A) {
109 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
110 if (reg & DWC3_DSTS_DCNRD)
120 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
121 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
123 /* set requested state */
124 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
125 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
128 * The following code is racy when called from dwc3_gadget_wakeup,
129 * and is not needed, at least on newer versions
131 if (dwc->revision >= DWC3_REVISION_194A)
134 /* wait for a change in DSTS */
137 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
139 if (DWC3_DSTS_USBLNKST(reg) == state)
145 dev_vdbg(dwc->dev, "link state change request timed out\n");
151 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
152 * @dwc: pointer to our context structure
154 * This function will a best effort FIFO allocation in order
155 * to improve FIFO usage and throughput, while still allowing
156 * us to enable as many endpoints as possible.
158 * Keep in mind that this operation will be highly dependent
159 * on the configured size for RAM1 - which contains TxFifo -,
160 * the amount of endpoints enabled on coreConsultant tool, and
161 * the width of the Master Bus.
163 * In the ideal world, we would always be able to satisfy the
164 * following equation:
166 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
167 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
169 * Unfortunately, due to many variables that's not always the case.
171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
173 int last_fifo_depth = 0;
179 if (!dwc->needs_fifo_resize)
182 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
183 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
185 /* MDWIDTH is represented in bits, we need it in bytes */
189 * FIXME For now we will only allocate 1 wMaxPacketSize space
190 * for each enabled endpoint, later patches will come to
191 * improve this algorithm so that we better use the internal
194 for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
195 struct dwc3_ep *dep = dwc->eps[num];
196 int fifo_number = dep->number >> 1;
200 if (!(dep->number & 1))
203 if (!(dep->flags & DWC3_EP_ENABLED))
206 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
207 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
211 * REVISIT: the following assumes we will always have enough
212 * space available on the FIFO RAM for all possible use cases.
213 * Make sure that's true somehow and change FIFO allocation
216 * If we have Bulk or Isochronous endpoints, we want
217 * them to be able to be very, very fast. So we're giving
218 * those endpoints a fifo_size which is enough for 3 full
221 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
224 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
226 fifo_size |= (last_fifo_depth << 16);
228 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
229 dep->name, last_fifo_depth, fifo_size & 0xffff);
231 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
234 last_fifo_depth += (fifo_size & 0xffff);
240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
243 struct dwc3 *dwc = dep->dwc;
251 * Skip LINK TRB. We can't use req->trb and check for
252 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
253 * just completed (not the LINK TRB).
255 if (((dep->busy_slot & DWC3_TRB_MASK) ==
257 usb_endpoint_xfer_isoc(dep->endpoint.desc))
259 } while(++i < req->request.num_mapped_sgs);
262 list_del(&req->list);
265 if (req->request.status == -EINPROGRESS)
266 req->request.status = status;
268 if (dwc->ep0_bounced && dep->number == 0)
269 dwc->ep0_bounced = false;
271 usb_gadget_unmap_request(&dwc->gadget, &req->request,
274 dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
275 req, dep->name, req->request.actual,
276 req->request.length, status);
278 spin_unlock(&dwc->lock);
279 req->request.complete(&dep->endpoint, &req->request);
280 spin_lock(&dwc->lock);
283 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
286 case DWC3_DEPCMD_DEPSTARTCFG:
287 return "Start New Configuration";
288 case DWC3_DEPCMD_ENDTRANSFER:
289 return "End Transfer";
290 case DWC3_DEPCMD_UPDATETRANSFER:
291 return "Update Transfer";
292 case DWC3_DEPCMD_STARTTRANSFER:
293 return "Start Transfer";
294 case DWC3_DEPCMD_CLEARSTALL:
295 return "Clear Stall";
296 case DWC3_DEPCMD_SETSTALL:
298 case DWC3_DEPCMD_GETEPSTATE:
299 return "Get Endpoint State";
300 case DWC3_DEPCMD_SETTRANSFRESOURCE:
301 return "Set Endpoint Transfer Resource";
302 case DWC3_DEPCMD_SETEPCONFIG:
303 return "Set Endpoint Configuration";
305 return "UNKNOWN command";
309 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
314 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
315 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
318 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
319 if (!(reg & DWC3_DGCMD_CMDACT)) {
320 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
321 DWC3_DGCMD_STATUS(reg));
326 * We can't sleep here, because it's also called from
336 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
337 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
339 struct dwc3_ep *dep = dwc->eps[ep];
343 dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
345 dwc3_gadget_ep_cmd_string(cmd), params->param0,
346 params->param1, params->param2);
348 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
349 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
350 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
352 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
354 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
355 if (!(reg & DWC3_DEPCMD_CMDACT)) {
356 dev_vdbg(dwc->dev, "Command Complete --> %d\n",
357 DWC3_DEPCMD_STATUS(reg));
362 * We can't sleep here, because it is also called from
373 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
374 struct dwc3_trb *trb)
376 u32 offset = (char *) trb - (char *) dep->trb_pool;
378 return dep->trb_pool_dma + offset;
381 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
383 struct dwc3 *dwc = dep->dwc;
388 if (dep->number == 0 || dep->number == 1)
391 dep->trb_pool = dma_alloc_coherent(dwc->dev,
392 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
393 &dep->trb_pool_dma, GFP_KERNEL);
394 if (!dep->trb_pool) {
395 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
403 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
405 struct dwc3 *dwc = dep->dwc;
407 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
408 dep->trb_pool, dep->trb_pool_dma);
410 dep->trb_pool = NULL;
411 dep->trb_pool_dma = 0;
414 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
416 struct dwc3_gadget_ep_cmd_params params;
419 memset(¶ms, 0x00, sizeof(params));
421 if (dep->number != 1) {
422 cmd = DWC3_DEPCMD_DEPSTARTCFG;
423 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
424 if (dep->number > 1) {
425 if (dwc->start_config_issued)
427 dwc->start_config_issued = true;
428 cmd |= DWC3_DEPCMD_PARAM(2);
431 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
437 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
438 const struct usb_endpoint_descriptor *desc,
439 const struct usb_ss_ep_comp_descriptor *comp_desc,
442 struct dwc3_gadget_ep_cmd_params params;
444 memset(¶ms, 0x00, sizeof(params));
446 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
447 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
449 /* Burst size is only needed in SuperSpeed mode */
450 if (dwc->gadget.speed == USB_SPEED_SUPER) {
451 u32 burst = dep->endpoint.maxburst - 1;
453 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
457 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
459 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
460 | DWC3_DEPCFG_XFER_NOT_READY_EN;
462 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
463 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
464 | DWC3_DEPCFG_STREAM_EVENT_EN;
465 dep->stream_capable = true;
468 if (usb_endpoint_xfer_isoc(desc))
469 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
472 * We are doing 1:1 mapping for endpoints, meaning
473 * Physical Endpoints 2 maps to Logical Endpoint 2 and
474 * so on. We consider the direction bit as part of the physical
475 * endpoint number. So USB endpoint 0x81 is 0x03.
477 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
480 * We must use the lower 16 TX FIFOs even though
484 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
486 if (desc->bInterval) {
487 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
488 dep->interval = 1 << (desc->bInterval - 1);
491 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
492 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
495 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
497 struct dwc3_gadget_ep_cmd_params params;
499 memset(¶ms, 0x00, sizeof(params));
501 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
503 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
504 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
508 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
509 * @dep: endpoint to be initialized
510 * @desc: USB Endpoint Descriptor
512 * Caller should take care of locking
514 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
515 const struct usb_endpoint_descriptor *desc,
516 const struct usb_ss_ep_comp_descriptor *comp_desc,
519 struct dwc3 *dwc = dep->dwc;
523 if (!(dep->flags & DWC3_EP_ENABLED)) {
524 ret = dwc3_gadget_start_config(dwc, dep);
529 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
533 if (!(dep->flags & DWC3_EP_ENABLED)) {
534 struct dwc3_trb *trb_st_hw;
535 struct dwc3_trb *trb_link;
537 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
541 dep->endpoint.desc = desc;
542 dep->comp_desc = comp_desc;
543 dep->type = usb_endpoint_type(desc);
544 dep->flags |= DWC3_EP_ENABLED;
546 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
547 reg |= DWC3_DALEPENA_EP(dep->number);
548 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
550 if (!usb_endpoint_xfer_isoc(desc))
553 /* Link TRB for ISOC. The HWO bit is never reset */
554 trb_st_hw = &dep->trb_pool[0];
556 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
557 memset(trb_link, 0, sizeof(*trb_link));
559 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
560 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
561 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
562 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
568 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
569 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
571 struct dwc3_request *req;
573 if (!list_empty(&dep->req_queued)) {
574 dwc3_stop_active_transfer(dwc, dep->number);
576 /* - giveback all requests to gadget driver */
577 while (!list_empty(&dep->req_queued)) {
578 req = next_request(&dep->req_queued);
580 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
584 while (!list_empty(&dep->request_list)) {
585 req = next_request(&dep->request_list);
587 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
592 * __dwc3_gadget_ep_disable - Disables a HW endpoint
593 * @dep: the endpoint to disable
595 * This function also removes requests which are currently processed ny the
596 * hardware and those which are not yet scheduled.
597 * Caller should take care of locking.
599 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
601 struct dwc3 *dwc = dep->dwc;
604 dwc3_remove_requests(dwc, dep);
606 /* make sure HW endpoint isn't stalled */
607 if (dep->flags & DWC3_EP_STALL)
608 __dwc3_gadget_ep_set_halt(dep, 0, false);
610 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
611 reg &= ~DWC3_DALEPENA_EP(dep->number);
612 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
614 dep->stream_capable = false;
615 dep->endpoint.desc = NULL;
616 dep->comp_desc = NULL;
623 /* -------------------------------------------------------------------------- */
625 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
626 const struct usb_endpoint_descriptor *desc)
631 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
636 /* -------------------------------------------------------------------------- */
638 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
639 const struct usb_endpoint_descriptor *desc)
646 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
647 pr_debug("dwc3: invalid parameters\n");
651 if (!desc->wMaxPacketSize) {
652 pr_debug("dwc3: missing wMaxPacketSize\n");
656 dep = to_dwc3_ep(ep);
659 if (dep->flags & DWC3_EP_ENABLED) {
660 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
665 switch (usb_endpoint_type(desc)) {
666 case USB_ENDPOINT_XFER_CONTROL:
667 strlcat(dep->name, "-control", sizeof(dep->name));
669 case USB_ENDPOINT_XFER_ISOC:
670 strlcat(dep->name, "-isoc", sizeof(dep->name));
672 case USB_ENDPOINT_XFER_BULK:
673 strlcat(dep->name, "-bulk", sizeof(dep->name));
675 case USB_ENDPOINT_XFER_INT:
676 strlcat(dep->name, "-int", sizeof(dep->name));
679 dev_err(dwc->dev, "invalid endpoint transfer type\n");
682 dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
684 spin_lock_irqsave(&dwc->lock, flags);
685 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
686 spin_unlock_irqrestore(&dwc->lock, flags);
691 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
699 pr_debug("dwc3: invalid parameters\n");
703 dep = to_dwc3_ep(ep);
706 if (!(dep->flags & DWC3_EP_ENABLED)) {
707 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
712 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
714 (dep->number & 1) ? "in" : "out");
716 spin_lock_irqsave(&dwc->lock, flags);
717 ret = __dwc3_gadget_ep_disable(dep);
718 spin_unlock_irqrestore(&dwc->lock, flags);
723 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
726 struct dwc3_request *req;
727 struct dwc3_ep *dep = to_dwc3_ep(ep);
728 struct dwc3 *dwc = dep->dwc;
730 req = kzalloc(sizeof(*req), gfp_flags);
732 dev_err(dwc->dev, "not enough memory\n");
736 req->epnum = dep->number;
739 return &req->request;
742 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
743 struct usb_request *request)
745 struct dwc3_request *req = to_dwc3_request(request);
751 * dwc3_prepare_one_trb - setup one TRB from one request
752 * @dep: endpoint for which this request is prepared
753 * @req: dwc3_request pointer
755 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
756 struct dwc3_request *req, dma_addr_t dma,
757 unsigned length, unsigned last, unsigned chain, unsigned node)
759 struct dwc3 *dwc = dep->dwc;
760 struct dwc3_trb *trb;
762 dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
763 dep->name, req, (unsigned long long) dma,
764 length, last ? " last" : "",
765 chain ? " chain" : "");
767 /* Skip the LINK-TRB on ISOC */
768 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
769 usb_endpoint_xfer_isoc(dep->endpoint.desc))
772 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
775 dwc3_gadget_move_request_queued(req);
777 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
778 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
783 trb->size = DWC3_TRB_SIZE_LENGTH(length);
784 trb->bpl = lower_32_bits(dma);
785 trb->bph = upper_32_bits(dma);
787 switch (usb_endpoint_type(dep->endpoint.desc)) {
788 case USB_ENDPOINT_XFER_CONTROL:
789 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
792 case USB_ENDPOINT_XFER_ISOC:
794 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
796 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
798 if (!req->request.no_interrupt && !chain)
799 trb->ctrl |= DWC3_TRB_CTRL_IOC;
802 case USB_ENDPOINT_XFER_BULK:
803 case USB_ENDPOINT_XFER_INT:
804 trb->ctrl = DWC3_TRBCTL_NORMAL;
808 * This is only possible with faulty memory because we
809 * checked it already :)
814 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
815 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
816 trb->ctrl |= DWC3_TRB_CTRL_CSP;
818 trb->ctrl |= DWC3_TRB_CTRL_LST;
822 trb->ctrl |= DWC3_TRB_CTRL_CHN;
824 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
825 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
827 trb->ctrl |= DWC3_TRB_CTRL_HWO;
831 * dwc3_prepare_trbs - setup TRBs from requests
832 * @dep: endpoint for which requests are being prepared
833 * @starting: true if the endpoint is idle and no requests are queued.
835 * The function goes through the requests list and sets up TRBs for the
836 * transfers. The function returns once there are no more TRBs available or
837 * it runs out of requests.
839 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
841 struct dwc3_request *req, *n;
844 unsigned int last_one = 0;
846 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
848 /* the first request must not be queued */
849 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
851 /* Can't wrap around on a non-isoc EP since there's no link TRB */
852 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
853 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
859 * If busy & slot are equal than it is either full or empty. If we are
860 * starting to process requests then we are empty. Otherwise we are
861 * full and don't do anything
866 trbs_left = DWC3_TRB_NUM;
868 * In case we start from scratch, we queue the ISOC requests
869 * starting from slot 1. This is done because we use ring
870 * buffer and have no LST bit to stop us. Instead, we place
871 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
872 * after the first request so we start at slot 1 and have
873 * 7 requests proceed before we hit the first IOC.
874 * Other transfer types don't use the ring buffer and are
875 * processed from the first TRB until the last one. Since we
876 * don't wrap around we have to start at the beginning.
878 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
887 /* The last TRB is a link TRB, not used for xfer */
888 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
891 list_for_each_entry_safe(req, n, &dep->request_list, list) {
896 if (req->request.num_mapped_sgs > 0) {
897 struct usb_request *request = &req->request;
898 struct scatterlist *sg = request->sg;
899 struct scatterlist *s;
902 for_each_sg(sg, s, request->num_mapped_sgs, i) {
903 unsigned chain = true;
905 length = sg_dma_len(s);
906 dma = sg_dma_address(s);
908 if (i == (request->num_mapped_sgs - 1) ||
910 if (list_is_last(&req->list,
923 dwc3_prepare_one_trb(dep, req, dma, length,
930 dma = req->request.dma;
931 length = req->request.length;
937 /* Is this the last request? */
938 if (list_is_last(&req->list, &dep->request_list))
941 dwc3_prepare_one_trb(dep, req, dma, length,
950 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
953 struct dwc3_gadget_ep_cmd_params params;
954 struct dwc3_request *req;
955 struct dwc3 *dwc = dep->dwc;
959 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
960 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
963 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
966 * If we are getting here after a short-out-packet we don't enqueue any
967 * new requests as we try to set the IOC bit only on the last request.
970 if (list_empty(&dep->req_queued))
971 dwc3_prepare_trbs(dep, start_new);
973 /* req points to the first request which will be sent */
974 req = next_request(&dep->req_queued);
976 dwc3_prepare_trbs(dep, start_new);
979 * req points to the first request where HWO changed from 0 to 1
981 req = next_request(&dep->req_queued);
984 dep->flags |= DWC3_EP_PENDING_REQUEST;
988 memset(¶ms, 0, sizeof(params));
991 params.param0 = upper_32_bits(req->trb_dma);
992 params.param1 = lower_32_bits(req->trb_dma);
993 cmd = DWC3_DEPCMD_STARTTRANSFER;
995 cmd = DWC3_DEPCMD_UPDATETRANSFER;
998 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
999 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1001 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1004 * FIXME we need to iterate over the list of requests
1005 * here and stop, unmap, free and del each of the linked
1006 * requests instead of what we do now.
1008 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1010 list_del(&req->list);
1014 dep->flags |= DWC3_EP_BUSY;
1017 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1019 WARN_ON_ONCE(!dep->resource_index);
1025 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1026 struct dwc3_ep *dep, u32 cur_uf)
1030 if (list_empty(&dep->request_list)) {
1031 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1033 dep->flags |= DWC3_EP_PENDING_REQUEST;
1037 /* 4 micro frames in the future */
1038 uf = cur_uf + dep->interval * 4;
1040 __dwc3_gadget_kick_transfer(dep, uf, 1);
1043 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1048 mask = ~(dep->interval - 1);
1049 cur_uf = event->parameters & mask;
1051 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1054 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1056 struct dwc3 *dwc = dep->dwc;
1059 req->request.actual = 0;
1060 req->request.status = -EINPROGRESS;
1061 req->direction = dep->direction;
1062 req->epnum = dep->number;
1065 * We only add to our list of requests now and
1066 * start consuming the list once we get XferNotReady
1069 * That way, we avoid doing anything that we don't need
1070 * to do now and defer it until the point we receive a
1071 * particular token from the Host side.
1073 * This will also avoid Host cancelling URBs due to too
1076 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1081 list_add_tail(&req->list, &dep->request_list);
1084 * There are a few special cases:
1086 * 1. XferNotReady with empty list of requests. We need to kick the
1087 * transfer here in that situation, otherwise we will be NAKing
1088 * forever. If we get XferNotReady before gadget driver has a
1089 * chance to queue a request, we will ACK the IRQ but won't be
1090 * able to receive the data until the next request is queued.
1091 * The following code is handling exactly that.
1094 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1096 * If xfernotready is already elapsed and it is a case
1097 * of isoc transfer, then issue END TRANSFER, so that
1098 * you can receive xfernotready again and can have
1099 * notion of current microframe.
1101 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1102 if (list_empty(&dep->req_queued)) {
1103 dwc3_stop_active_transfer(dwc, dep->number);
1104 dep->flags = DWC3_EP_ENABLED;
1109 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1110 if (ret && ret != -EBUSY)
1111 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1117 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1118 * kick the transfer here after queuing a request, otherwise the
1119 * core may not see the modified TRB(s).
1121 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1122 (dep->flags & DWC3_EP_BUSY) &&
1123 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1124 WARN_ON_ONCE(!dep->resource_index);
1125 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1127 if (ret && ret != -EBUSY)
1128 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1136 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1139 struct dwc3_request *req = to_dwc3_request(request);
1140 struct dwc3_ep *dep = to_dwc3_ep(ep);
1141 struct dwc3 *dwc = dep->dwc;
1143 unsigned long flags;
1147 if (!dep->endpoint.desc) {
1148 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1153 dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1154 request, ep->name, request->length);
1156 spin_lock_irqsave(&dwc->lock, flags);
1157 ret = __dwc3_gadget_ep_queue(dep, req);
1158 spin_unlock_irqrestore(&dwc->lock, flags);
1163 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1164 struct usb_request *request)
1166 struct dwc3_request *req = to_dwc3_request(request);
1167 struct dwc3_request *r = NULL;
1169 struct dwc3_ep *dep = to_dwc3_ep(ep);
1170 struct dwc3 *dwc = dep->dwc;
1172 unsigned long flags;
1175 spin_lock_irqsave(&dwc->lock, flags);
1177 list_for_each_entry(r, &dep->request_list, list) {
1183 list_for_each_entry(r, &dep->req_queued, list) {
1188 /* wait until it is processed */
1189 dwc3_stop_active_transfer(dwc, dep->number);
1192 dev_err(dwc->dev, "request %p was not queued to %s\n",
1199 /* giveback the request */
1200 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1203 spin_unlock_irqrestore(&dwc->lock, flags);
1208 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1210 struct dwc3_gadget_ep_cmd_params params;
1211 struct dwc3 *dwc = dep->dwc;
1214 memset(¶ms, 0x00, sizeof(params));
1217 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1218 (!list_empty(&dep->req_queued) ||
1219 !list_empty(&dep->request_list)))) {
1220 dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1225 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1226 DWC3_DEPCMD_SETSTALL, ¶ms);
1228 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1229 value ? "set" : "clear",
1232 dep->flags |= DWC3_EP_STALL;
1234 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1235 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1237 dev_err(dwc->dev, "failed to %s STALL on %s\n",
1238 value ? "set" : "clear",
1241 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1247 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1249 struct dwc3_ep *dep = to_dwc3_ep(ep);
1250 struct dwc3 *dwc = dep->dwc;
1252 unsigned long flags;
1256 spin_lock_irqsave(&dwc->lock, flags);
1258 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1259 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1264 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1266 spin_unlock_irqrestore(&dwc->lock, flags);
1271 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1273 struct dwc3_ep *dep = to_dwc3_ep(ep);
1274 struct dwc3 *dwc = dep->dwc;
1275 unsigned long flags;
1277 spin_lock_irqsave(&dwc->lock, flags);
1278 dep->flags |= DWC3_EP_WEDGE;
1279 spin_unlock_irqrestore(&dwc->lock, flags);
1281 if (dep->number == 0 || dep->number == 1)
1282 return dwc3_gadget_ep0_set_halt(ep, 1);
1284 return __dwc3_gadget_ep_set_halt(dep, 1, false);
1287 /* -------------------------------------------------------------------------- */
1289 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1290 .bLength = USB_DT_ENDPOINT_SIZE,
1291 .bDescriptorType = USB_DT_ENDPOINT,
1292 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1295 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1296 .enable = dwc3_gadget_ep0_enable,
1297 .disable = dwc3_gadget_ep0_disable,
1298 .alloc_request = dwc3_gadget_ep_alloc_request,
1299 .free_request = dwc3_gadget_ep_free_request,
1300 .queue = dwc3_gadget_ep0_queue,
1301 .dequeue = dwc3_gadget_ep_dequeue,
1302 .set_halt = dwc3_gadget_ep0_set_halt,
1303 .set_wedge = dwc3_gadget_ep_set_wedge,
1306 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1307 .enable = dwc3_gadget_ep_enable,
1308 .disable = dwc3_gadget_ep_disable,
1309 .alloc_request = dwc3_gadget_ep_alloc_request,
1310 .free_request = dwc3_gadget_ep_free_request,
1311 .queue = dwc3_gadget_ep_queue,
1312 .dequeue = dwc3_gadget_ep_dequeue,
1313 .set_halt = dwc3_gadget_ep_set_halt,
1314 .set_wedge = dwc3_gadget_ep_set_wedge,
1317 /* -------------------------------------------------------------------------- */
1319 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1321 struct dwc3 *dwc = gadget_to_dwc(g);
1324 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1325 return DWC3_DSTS_SOFFN(reg);
1328 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1330 struct dwc3 *dwc = gadget_to_dwc(g);
1332 unsigned long timeout;
1333 unsigned long flags;
1342 spin_lock_irqsave(&dwc->lock, flags);
1345 * According to the Databook Remote wakeup request should
1346 * be issued only when the device is in early suspend state.
1348 * We can check that via USB Link State bits in DSTS register.
1350 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1352 speed = reg & DWC3_DSTS_CONNECTSPD;
1353 if (speed == DWC3_DSTS_SUPERSPEED) {
1354 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1359 link_state = DWC3_DSTS_USBLNKST(reg);
1361 switch (link_state) {
1362 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1363 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1366 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1372 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1374 dev_err(dwc->dev, "failed to put link in Recovery\n");
1378 /* Recent versions do this automatically */
1379 if (dwc->revision < DWC3_REVISION_194A) {
1380 /* write zeroes to Link Change Request */
1381 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1382 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1383 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386 /* poll until Link State changes to ON */
1387 timeout = jiffies + msecs_to_jiffies(100);
1389 while (!time_after(jiffies, timeout)) {
1390 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1392 /* in HS, means ON */
1393 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1397 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1398 dev_err(dwc->dev, "failed to send remote wakeup\n");
1403 spin_unlock_irqrestore(&dwc->lock, flags);
1408 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1411 struct dwc3 *dwc = gadget_to_dwc(g);
1412 unsigned long flags;
1414 spin_lock_irqsave(&dwc->lock, flags);
1415 dwc->is_selfpowered = !!is_selfpowered;
1416 spin_unlock_irqrestore(&dwc->lock, flags);
1421 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1426 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1428 if (dwc->revision <= DWC3_REVISION_187A) {
1429 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1430 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1433 if (dwc->revision >= DWC3_REVISION_194A)
1434 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1435 reg |= DWC3_DCTL_RUN_STOP;
1436 dwc->pullups_connected = true;
1438 reg &= ~DWC3_DCTL_RUN_STOP;
1439 dwc->pullups_connected = false;
1442 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1445 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1447 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1450 if (reg & DWC3_DSTS_DEVCTRLHLT)
1459 dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1461 ? dwc->gadget_driver->function : "no-function",
1462 is_on ? "connect" : "disconnect");
1467 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1469 struct dwc3 *dwc = gadget_to_dwc(g);
1470 unsigned long flags;
1475 spin_lock_irqsave(&dwc->lock, flags);
1476 ret = dwc3_gadget_run_stop(dwc, is_on);
1477 spin_unlock_irqrestore(&dwc->lock, flags);
1482 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1486 /* Enable all but Start and End of Frame IRQs */
1487 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1488 DWC3_DEVTEN_EVNTOVERFLOWEN |
1489 DWC3_DEVTEN_CMDCMPLTEN |
1490 DWC3_DEVTEN_ERRTICERREN |
1491 DWC3_DEVTEN_WKUPEVTEN |
1492 DWC3_DEVTEN_ULSTCNGEN |
1493 DWC3_DEVTEN_CONNECTDONEEN |
1494 DWC3_DEVTEN_USBRSTEN |
1495 DWC3_DEVTEN_DISCONNEVTEN);
1497 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1500 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1502 /* mask all interrupts */
1503 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1506 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1507 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1509 static int dwc3_gadget_start(struct usb_gadget *g,
1510 struct usb_gadget_driver *driver)
1512 struct dwc3 *dwc = gadget_to_dwc(g);
1513 struct dwc3_ep *dep;
1514 unsigned long flags;
1519 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1520 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1521 IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);
1523 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1528 spin_lock_irqsave(&dwc->lock, flags);
1530 if (dwc->gadget_driver) {
1531 dev_err(dwc->dev, "%s is already bound to %s\n",
1533 dwc->gadget_driver->driver.name);
1538 dwc->gadget_driver = driver;
1540 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1541 reg &= ~(DWC3_DCFG_SPEED_MASK);
1544 * WORKAROUND: DWC3 revision < 2.20a have an issue
1545 * which would cause metastability state on Run/Stop
1546 * bit if we try to force the IP to USB2-only mode.
1548 * Because of that, we cannot configure the IP to any
1549 * speed other than the SuperSpeed
1553 * STAR#9000525659: Clock Domain Crossing on DCTL in
1556 if (dwc->revision < DWC3_REVISION_220A)
1557 reg |= DWC3_DCFG_SUPERSPEED;
1559 reg |= dwc->maximum_speed;
1560 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1562 dwc->start_config_issued = false;
1564 /* Start with SuperSpeed Default */
1565 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1568 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1570 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1575 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1577 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1581 /* begin to receive SETUP packets */
1582 dwc->ep0state = EP0_SETUP_PHASE;
1583 dwc3_ep0_out_start(dwc);
1585 dwc3_gadget_enable_irq(dwc);
1587 spin_unlock_irqrestore(&dwc->lock, flags);
1592 __dwc3_gadget_ep_disable(dwc->eps[0]);
1595 dwc->gadget_driver = NULL;
1598 spin_unlock_irqrestore(&dwc->lock, flags);
1606 static int dwc3_gadget_stop(struct usb_gadget *g,
1607 struct usb_gadget_driver *driver)
1609 struct dwc3 *dwc = gadget_to_dwc(g);
1610 unsigned long flags;
1613 spin_lock_irqsave(&dwc->lock, flags);
1615 dwc3_gadget_disable_irq(dwc);
1616 __dwc3_gadget_ep_disable(dwc->eps[0]);
1617 __dwc3_gadget_ep_disable(dwc->eps[1]);
1619 dwc->gadget_driver = NULL;
1621 spin_unlock_irqrestore(&dwc->lock, flags);
1623 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1629 static const struct usb_gadget_ops dwc3_gadget_ops = {
1630 .get_frame = dwc3_gadget_get_frame,
1631 .wakeup = dwc3_gadget_wakeup,
1632 .set_selfpowered = dwc3_gadget_set_selfpowered,
1633 .pullup = dwc3_gadget_pullup,
1634 .udc_start = dwc3_gadget_start,
1635 .udc_stop = dwc3_gadget_stop,
1638 /* -------------------------------------------------------------------------- */
1640 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1641 u8 num, u32 direction)
1643 struct dwc3_ep *dep;
1646 for (i = 0; i < num; i++) {
1647 u8 epnum = (i << 1) | (!!direction);
1649 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1651 dev_err(dwc->dev, "can't allocate endpoint %d\n",
1657 dep->number = epnum;
1658 dwc->eps[epnum] = dep;
1660 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1661 (epnum & 1) ? "in" : "out");
1663 dep->endpoint.name = dep->name;
1664 dep->direction = (epnum & 1);
1666 if (epnum == 0 || epnum == 1) {
1667 dep->endpoint.maxpacket = 512;
1668 dep->endpoint.maxburst = 1;
1669 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1671 dwc->gadget.ep0 = &dep->endpoint;
1675 dep->endpoint.maxpacket = 1024;
1676 dep->endpoint.max_streams = 15;
1677 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1678 list_add_tail(&dep->endpoint.ep_list,
1679 &dwc->gadget.ep_list);
1681 ret = dwc3_alloc_trb_pool(dep);
1686 INIT_LIST_HEAD(&dep->request_list);
1687 INIT_LIST_HEAD(&dep->req_queued);
1693 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1697 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1699 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1701 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1705 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1707 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1714 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1716 struct dwc3_ep *dep;
1719 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1720 dep = dwc->eps[epnum];
1724 * Physical endpoints 0 and 1 are special; they form the
1725 * bi-directional USB endpoint 0.
1727 * For those two physical endpoints, we don't allocate a TRB
1728 * pool nor do we add them the endpoints list. Due to that, we
1729 * shouldn't do these two operations otherwise we would end up
1730 * with all sorts of bugs when removing dwc3.ko.
1732 if (epnum != 0 && epnum != 1) {
1733 dwc3_free_trb_pool(dep);
1734 list_del(&dep->endpoint.ep_list);
1741 /* -------------------------------------------------------------------------- */
1743 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1744 struct dwc3_request *req, struct dwc3_trb *trb,
1745 const struct dwc3_event_depevt *event, int status)
1748 unsigned int s_pkt = 0;
1749 unsigned int trb_status;
1751 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1753 * We continue despite the error. There is not much we
1754 * can do. If we don't clean it up we loop forever. If
1755 * we skip the TRB then it gets overwritten after a
1756 * while since we use them in a ring buffer. A BUG()
1757 * would help. Lets hope that if this occurs, someone
1758 * fixes the root cause instead of looking away :)
1760 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1762 count = trb->size & DWC3_TRB_SIZE_MASK;
1764 if (dep->direction) {
1766 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1767 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1768 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1771 * If missed isoc occurred and there is
1772 * no request queued then issue END
1773 * TRANSFER, so that core generates
1774 * next xfernotready and we will issue
1775 * a fresh START TRANSFER.
1776 * If there are still queued request
1777 * then wait, do not issue either END
1778 * or UPDATE TRANSFER, just attach next
1779 * request in request_list during
1780 * giveback.If any future queued request
1781 * is successfully transferred then we
1782 * will issue UPDATE TRANSFER for all
1783 * request in the request_list.
1785 dep->flags |= DWC3_EP_MISSED_ISOC;
1787 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1789 status = -ECONNRESET;
1792 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1795 if (count && (event->status & DEPEVT_STATUS_SHORT))
1800 * We assume here we will always receive the entire data block
1801 * which we should receive. Meaning, if we program RX to
1802 * receive 4K but we receive only 2K, we assume that's all we
1803 * should receive and we simply bounce the request back to the
1804 * gadget driver for further processing.
1806 req->request.actual += req->request.length - count;
1809 if ((event->status & DEPEVT_STATUS_LST) &&
1810 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1811 DWC3_TRB_CTRL_HWO)))
1813 if ((event->status & DEPEVT_STATUS_IOC) &&
1814 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1819 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1820 const struct dwc3_event_depevt *event, int status)
1822 struct dwc3_request *req;
1823 struct dwc3_trb *trb;
1829 req = next_request(&dep->req_queued);
1836 slot = req->start_slot + i;
1837 if ((slot == DWC3_TRB_NUM - 1) &&
1838 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1840 slot %= DWC3_TRB_NUM;
1841 trb = &dep->trb_pool[slot];
1843 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1847 }while (++i < req->request.num_mapped_sgs);
1849 dwc3_gadget_giveback(dep, req, status);
1855 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1856 list_empty(&dep->req_queued)) {
1857 if (list_empty(&dep->request_list)) {
1859 * If there is no entry in request list then do
1860 * not issue END TRANSFER now. Just set PENDING
1861 * flag, so that END TRANSFER is issued when an
1862 * entry is added into request list.
1864 dep->flags = DWC3_EP_PENDING_REQUEST;
1866 dwc3_stop_active_transfer(dwc, dep->number);
1867 dep->flags = DWC3_EP_ENABLED;
1872 if ((event->status & DEPEVT_STATUS_IOC) &&
1873 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1878 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1879 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1882 unsigned status = 0;
1885 if (event->status & DEPEVT_STATUS_BUSERR)
1886 status = -ECONNRESET;
1888 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1890 dep->flags &= ~DWC3_EP_BUSY;
1893 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1894 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1896 if (dwc->revision < DWC3_REVISION_183A) {
1900 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1903 if (!(dep->flags & DWC3_EP_ENABLED))
1906 if (!list_empty(&dep->req_queued))
1910 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1912 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1918 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1919 const struct dwc3_event_depevt *event)
1921 struct dwc3_ep *dep;
1922 u8 epnum = event->endpoint_number;
1924 dep = dwc->eps[epnum];
1926 if (!(dep->flags & DWC3_EP_ENABLED))
1929 dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1930 dwc3_ep_event_string(event->endpoint_event));
1932 if (epnum == 0 || epnum == 1) {
1933 dwc3_ep0_interrupt(dwc, event);
1937 switch (event->endpoint_event) {
1938 case DWC3_DEPEVT_XFERCOMPLETE:
1939 dep->resource_index = 0;
1941 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1942 dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1947 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1949 case DWC3_DEPEVT_XFERINPROGRESS:
1950 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1951 dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1956 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1958 case DWC3_DEPEVT_XFERNOTREADY:
1959 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1960 dwc3_gadget_start_isoc(dwc, dep, event);
1964 dev_vdbg(dwc->dev, "%s: reason %s\n",
1965 dep->name, event->status &
1966 DEPEVT_STATUS_TRANSFER_ACTIVE
1968 : "Transfer Not Active");
1970 ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1971 if (!ret || ret == -EBUSY)
1974 dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1979 case DWC3_DEPEVT_STREAMEVT:
1980 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1981 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1986 switch (event->status) {
1987 case DEPEVT_STREAMEVT_FOUND:
1988 dev_vdbg(dwc->dev, "Stream %d found and started\n",
1992 case DEPEVT_STREAMEVT_NOTFOUND:
1995 dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1998 case DWC3_DEPEVT_RXTXFIFOEVT:
1999 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2001 case DWC3_DEPEVT_EPCMDCMPLT:
2002 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2007 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2009 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2010 spin_unlock(&dwc->lock);
2011 dwc->gadget_driver->disconnect(&dwc->gadget);
2012 spin_lock(&dwc->lock);
2016 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2018 struct dwc3_ep *dep;
2019 struct dwc3_gadget_ep_cmd_params params;
2023 dep = dwc->eps[epnum];
2025 if (!dep->resource_index)
2029 * NOTICE: We are violating what the Databook says about the
2030 * EndTransfer command. Ideally we would _always_ wait for the
2031 * EndTransfer Command Completion IRQ, but that's causing too
2032 * much trouble synchronizing between us and gadget driver.
2034 * We have discussed this with the IP Provider and it was
2035 * suggested to giveback all requests here, but give HW some
2036 * extra time to synchronize with the interconnect. We're using
2037 * an arbitraty 100us delay for that.
2039 * Note also that a similar handling was tested by Synopsys
2040 * (thanks a lot Paul) and nothing bad has come out of it.
2041 * In short, what we're doing is:
2043 * - Issue EndTransfer WITH CMDIOC bit set
2047 cmd = DWC3_DEPCMD_ENDTRANSFER;
2048 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2049 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2050 memset(¶ms, 0, sizeof(params));
2051 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2053 dep->resource_index = 0;
2054 dep->flags &= ~DWC3_EP_BUSY;
2058 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2062 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2063 struct dwc3_ep *dep;
2065 dep = dwc->eps[epnum];
2069 if (!(dep->flags & DWC3_EP_ENABLED))
2072 dwc3_remove_requests(dwc, dep);
2076 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2080 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2081 struct dwc3_ep *dep;
2082 struct dwc3_gadget_ep_cmd_params params;
2085 dep = dwc->eps[epnum];
2089 if (!(dep->flags & DWC3_EP_STALL))
2092 dep->flags &= ~DWC3_EP_STALL;
2094 memset(¶ms, 0, sizeof(params));
2095 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2096 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2101 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2105 dev_vdbg(dwc->dev, "%s\n", __func__);
2107 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2108 reg &= ~DWC3_DCTL_INITU1ENA;
2109 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2111 reg &= ~DWC3_DCTL_INITU2ENA;
2112 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2114 dwc3_disconnect_gadget(dwc);
2115 dwc->start_config_issued = false;
2117 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2118 dwc->setup_packet_pending = false;
2121 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
2125 reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
2128 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
2130 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
2132 dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2135 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
2139 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2142 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
2144 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2146 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2149 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2153 dev_vdbg(dwc->dev, "%s\n", __func__);
2156 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2157 * would cause a missing Disconnect Event if there's a
2158 * pending Setup Packet in the FIFO.
2160 * There's no suggested workaround on the official Bug
2161 * report, which states that "unless the driver/application
2162 * is doing any special handling of a disconnect event,
2163 * there is no functional issue".
2165 * Unfortunately, it turns out that we _do_ some special
2166 * handling of a disconnect event, namely complete all
2167 * pending transfers, notify gadget driver of the
2168 * disconnection, and so on.
2170 * Our suggested workaround is to follow the Disconnect
2171 * Event steps here, instead, based on a setup_packet_pending
2172 * flag. Such flag gets set whenever we have a XferNotReady
2173 * event on EP0 and gets cleared on XferComplete for the
2178 * STAR#9000466709: RTL: Device : Disconnect event not
2179 * generated if setup packet pending in FIFO
2181 if (dwc->revision < DWC3_REVISION_188A) {
2182 if (dwc->setup_packet_pending)
2183 dwc3_gadget_disconnect_interrupt(dwc);
2186 /* after reset -> Default State */
2187 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2189 /* Recent versions support automatic phy suspend and don't need this */
2190 if (dwc->revision < DWC3_REVISION_194A) {
2192 dwc3_gadget_usb2_phy_suspend(dwc, false);
2193 dwc3_gadget_usb3_phy_suspend(dwc, false);
2196 if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2197 dwc3_disconnect_gadget(dwc);
2199 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2200 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2201 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2202 dwc->test_mode = false;
2204 dwc3_stop_active_transfers(dwc);
2205 dwc3_clear_stall_all_ep(dwc);
2206 dwc->start_config_issued = false;
2208 /* Reset device address to zero */
2209 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2210 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2211 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2214 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2217 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2220 * We change the clock only at SS but I dunno why I would want to do
2221 * this. Maybe it becomes part of the power saving plan.
2224 if (speed != DWC3_DSTS_SUPERSPEED)
2228 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2229 * each time on Connect Done.
2234 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2235 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2236 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2239 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2242 case USB_SPEED_SUPER:
2243 dwc3_gadget_usb2_phy_suspend(dwc, true);
2245 case USB_SPEED_HIGH:
2246 case USB_SPEED_FULL:
2248 dwc3_gadget_usb3_phy_suspend(dwc, true);
2253 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2255 struct dwc3_ep *dep;
2260 dev_vdbg(dwc->dev, "%s\n", __func__);
2262 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2263 speed = reg & DWC3_DSTS_CONNECTSPD;
2266 dwc3_update_ram_clk_sel(dwc, speed);
2269 case DWC3_DCFG_SUPERSPEED:
2271 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2272 * would cause a missing USB3 Reset event.
2274 * In such situations, we should force a USB3 Reset
2275 * event by calling our dwc3_gadget_reset_interrupt()
2280 * STAR#9000483510: RTL: SS : USB3 reset event may
2281 * not be generated always when the link enters poll
2283 if (dwc->revision < DWC3_REVISION_190A)
2284 dwc3_gadget_reset_interrupt(dwc);
2286 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2287 dwc->gadget.ep0->maxpacket = 512;
2288 dwc->gadget.speed = USB_SPEED_SUPER;
2290 case DWC3_DCFG_HIGHSPEED:
2291 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2292 dwc->gadget.ep0->maxpacket = 64;
2293 dwc->gadget.speed = USB_SPEED_HIGH;
2295 case DWC3_DCFG_FULLSPEED2:
2296 case DWC3_DCFG_FULLSPEED1:
2297 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2298 dwc->gadget.ep0->maxpacket = 64;
2299 dwc->gadget.speed = USB_SPEED_FULL;
2301 case DWC3_DCFG_LOWSPEED:
2302 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2303 dwc->gadget.ep0->maxpacket = 8;
2304 dwc->gadget.speed = USB_SPEED_LOW;
2308 /* Enable USB2 LPM Capability */
2310 if ((dwc->revision > DWC3_REVISION_194A)
2311 && (speed != DWC3_DCFG_SUPERSPEED)) {
2312 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2313 reg |= DWC3_DCFG_LPM_CAP;
2314 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2316 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2317 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2320 * TODO: This should be configurable. For now using
2321 * maximum allowed HIRD threshold value of 0b1100
2323 reg |= DWC3_DCTL_HIRD_THRES(12);
2325 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2328 /* Recent versions support automatic phy suspend and don't need this */
2329 if (dwc->revision < DWC3_REVISION_194A) {
2330 /* Suspend unneeded PHY */
2331 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2335 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2337 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2342 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2344 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2349 * Configure PHY via GUSB3PIPECTLn if required.
2351 * Update GTXFIFOSIZn
2353 * In both cases reset values should be sufficient.
2357 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2359 dev_vdbg(dwc->dev, "%s\n", __func__);
2362 * TODO take core out of low power mode when that's
2366 dwc->gadget_driver->resume(&dwc->gadget);
2369 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2370 unsigned int evtinfo)
2372 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2373 unsigned int pwropt;
2376 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2377 * Hibernation mode enabled which would show up when device detects
2378 * host-initiated U3 exit.
2380 * In that case, device will generate a Link State Change Interrupt
2381 * from U3 to RESUME which is only necessary if Hibernation is
2384 * There are no functional changes due to such spurious event and we
2385 * just need to ignore it.
2389 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2392 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2393 if ((dwc->revision < DWC3_REVISION_250A) &&
2394 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2395 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2396 (next == DWC3_LINK_STATE_RESUME)) {
2397 dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2403 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2404 * on the link partner, the USB session might do multiple entry/exit
2405 * of low power states before a transfer takes place.
2407 * Due to this problem, we might experience lower throughput. The
2408 * suggested workaround is to disable DCTL[12:9] bits if we're
2409 * transitioning from U1/U2 to U0 and enable those bits again
2410 * after a transfer completes and there are no pending transfers
2411 * on any of the enabled endpoints.
2413 * This is the first half of that workaround.
2417 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2418 * core send LGO_Ux entering U0
2420 if (dwc->revision < DWC3_REVISION_183A) {
2421 if (next == DWC3_LINK_STATE_U0) {
2425 switch (dwc->link_state) {
2426 case DWC3_LINK_STATE_U1:
2427 case DWC3_LINK_STATE_U2:
2428 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2429 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2430 | DWC3_DCTL_ACCEPTU2ENA
2431 | DWC3_DCTL_INITU1ENA
2432 | DWC3_DCTL_ACCEPTU1ENA);
2435 dwc->u1u2 = reg & u1u2;
2439 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2448 dwc->link_state = next;
2450 dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2453 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2454 const struct dwc3_event_devt *event)
2456 switch (event->type) {
2457 case DWC3_DEVICE_EVENT_DISCONNECT:
2458 dwc3_gadget_disconnect_interrupt(dwc);
2460 case DWC3_DEVICE_EVENT_RESET:
2461 dwc3_gadget_reset_interrupt(dwc);
2463 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2464 dwc3_gadget_conndone_interrupt(dwc);
2466 case DWC3_DEVICE_EVENT_WAKEUP:
2467 dwc3_gadget_wakeup_interrupt(dwc);
2469 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2470 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2472 case DWC3_DEVICE_EVENT_EOPF:
2473 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2475 case DWC3_DEVICE_EVENT_SOF:
2476 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2478 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2479 dev_vdbg(dwc->dev, "Erratic Error\n");
2481 case DWC3_DEVICE_EVENT_CMD_CMPL:
2482 dev_vdbg(dwc->dev, "Command Complete\n");
2484 case DWC3_DEVICE_EVENT_OVERFLOW:
2485 dev_vdbg(dwc->dev, "Overflow\n");
2488 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2492 static void dwc3_process_event_entry(struct dwc3 *dwc,
2493 const union dwc3_event *event)
2495 /* Endpoint IRQ, handle it and return early */
2496 if (event->type.is_devspec == 0) {
2498 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2501 switch (event->type.type) {
2502 case DWC3_EVENT_TYPE_DEV:
2503 dwc3_gadget_interrupt(dwc, &event->devt);
2505 /* REVISIT what to do with Carkit and I2C events ? */
2507 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2511 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2513 struct dwc3 *dwc = _dwc;
2514 unsigned long flags;
2515 irqreturn_t ret = IRQ_NONE;
2518 spin_lock_irqsave(&dwc->lock, flags);
2520 for (i = 0; i < dwc->num_event_buffers; i++) {
2521 struct dwc3_event_buffer *evt;
2524 evt = dwc->ev_buffs[i];
2527 if (!(evt->flags & DWC3_EVENT_PENDING))
2531 union dwc3_event event;
2533 event.raw = *(u32 *) (evt->buf + evt->lpos);
2535 dwc3_process_event_entry(dwc, &event);
2538 * FIXME we wrap around correctly to the next entry as
2539 * almost all entries are 4 bytes in size. There is one
2540 * entry which has 12 bytes which is a regular entry
2541 * followed by 8 bytes data. ATM I don't know how
2542 * things are organized if we get next to the a
2543 * boundary so I worry about that once we try to handle
2546 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2549 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);
2553 evt->flags &= ~DWC3_EVENT_PENDING;
2557 spin_unlock_irqrestore(&dwc->lock, flags);
2562 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2564 struct dwc3_event_buffer *evt;
2567 evt = dwc->ev_buffs[buf];
2569 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2570 count &= DWC3_GEVNTCOUNT_MASK;
2575 evt->flags |= DWC3_EVENT_PENDING;
2577 return IRQ_WAKE_THREAD;
2580 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2582 struct dwc3 *dwc = _dwc;
2584 irqreturn_t ret = IRQ_NONE;
2586 spin_lock(&dwc->lock);
2588 for (i = 0; i < dwc->num_event_buffers; i++) {
2591 status = dwc3_process_event_buf(dwc, i);
2592 if (status == IRQ_WAKE_THREAD)
2596 spin_unlock(&dwc->lock);
2602 * dwc3_gadget_init - Initializes gadget related registers
2603 * @dwc: pointer to our controller context structure
2605 * Returns 0 on success otherwise negative errno.
2607 int dwc3_gadget_init(struct dwc3 *dwc)
2612 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2613 &dwc->ctrl_req_addr, GFP_KERNEL);
2614 if (!dwc->ctrl_req) {
2615 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2620 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2621 &dwc->ep0_trb_addr, GFP_KERNEL);
2622 if (!dwc->ep0_trb) {
2623 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2628 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2629 if (!dwc->setup_buf) {
2630 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2635 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2636 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2638 if (!dwc->ep0_bounce) {
2639 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2644 dwc->gadget.ops = &dwc3_gadget_ops;
2645 dwc->gadget.max_speed = USB_SPEED_SUPER;
2646 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2647 dwc->gadget.sg_supported = true;
2648 dwc->gadget.name = "dwc3-gadget";
2651 * REVISIT: Here we should clear all pending IRQs to be
2652 * sure we're starting from a well known location.
2655 ret = dwc3_gadget_init_endpoints(dwc);
2659 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2660 reg |= DWC3_DCFG_LPM_CAP;
2661 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2663 /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2664 if (dwc->revision >= DWC3_REVISION_194A) {
2665 dwc3_gadget_usb2_phy_suspend(dwc, false);
2666 dwc3_gadget_usb3_phy_suspend(dwc, false);
2669 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2671 dev_err(dwc->dev, "failed to register udc\n");
2678 dwc3_gadget_free_endpoints(dwc);
2681 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2682 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2685 kfree(dwc->setup_buf);
2688 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2689 dwc->ep0_trb, dwc->ep0_trb_addr);
2692 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2693 dwc->ctrl_req, dwc->ctrl_req_addr);
2699 /* -------------------------------------------------------------------------- */
2701 void dwc3_gadget_exit(struct dwc3 *dwc)
2703 usb_del_gadget_udc(&dwc->gadget);
2705 dwc3_gadget_free_endpoints(dwc);
2707 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2708 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2710 kfree(dwc->setup_buf);
2712 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2713 dwc->ep0_trb, dwc->ep0_trb_addr);
2715 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2716 dwc->ctrl_req, dwc->ctrl_req_addr);
2719 int dwc3_gadget_prepare(struct dwc3 *dwc)
2721 if (dwc->pullups_connected)
2722 dwc3_gadget_disable_irq(dwc);
2727 void dwc3_gadget_complete(struct dwc3 *dwc)
2729 if (dwc->pullups_connected) {
2730 dwc3_gadget_enable_irq(dwc);
2731 dwc3_gadget_run_stop(dwc, true);
2735 int dwc3_gadget_suspend(struct dwc3 *dwc)
2737 __dwc3_gadget_ep_disable(dwc->eps[0]);
2738 __dwc3_gadget_ep_disable(dwc->eps[1]);
2740 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2745 int dwc3_gadget_resume(struct dwc3 *dwc)
2747 struct dwc3_ep *dep;
2750 /* Start with SuperSpeed Default */
2751 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2754 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2759 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2763 /* begin to receive SETUP packets */
2764 dwc->ep0state = EP0_SETUP_PHASE;
2765 dwc3_ep0_out_start(dwc);
2767 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2772 __dwc3_gadget_ep_disable(dwc->eps[0]);