2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
151 dep->trb_enqueue %= DWC3_TRB_NUM;
154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
157 dep->trb_dequeue %= DWC3_TRB_NUM;
160 static int dwc3_ep_is_last_trb(unsigned int index)
162 return index == DWC3_TRB_NUM - 1;
165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
168 struct dwc3 *dwc = dep->dwc;
174 dwc3_ep_inc_deq(dep);
176 * Skip LINK TRB. We can't use req->trb and check for
177 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
178 * just completed (not the LINK TRB).
180 if (dwc3_ep_is_last_trb(dep->trb_dequeue))
181 dwc3_ep_inc_deq(dep);
182 } while(++i < req->request.num_mapped_sgs);
183 req->started = false;
185 list_del(&req->list);
188 if (req->request.status == -EINPROGRESS)
189 req->request.status = status;
191 if (dwc->ep0_bounced && dep->number == 0)
192 dwc->ep0_bounced = false;
194 usb_gadget_unmap_request(&dwc->gadget, &req->request,
197 trace_dwc3_gadget_giveback(req);
199 spin_unlock(&dwc->lock);
200 usb_gadget_giveback_request(&dep->endpoint, &req->request);
201 spin_lock(&dwc->lock);
204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
209 trace_dwc3_gadget_generic_cmd(cmd, param);
211 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
212 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
215 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
216 if (!(reg & DWC3_DGCMD_CMDACT)) {
217 dwc3_trace(trace_dwc3_gadget,
218 "Command Complete --> %d",
219 DWC3_DGCMD_STATUS(reg));
220 if (DWC3_DGCMD_STATUS(reg))
226 * We can't sleep here, because it's also called from
231 dwc3_trace(trace_dwc3_gadget,
232 "Command Timed Out");
239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
241 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
242 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
244 struct dwc3_ep *dep = dwc->eps[ep];
251 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
254 * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
255 * we're issuing an endpoint command, we must check if
256 * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
258 * We will also set SUSPHY bit to what it was before returning as stated
259 * by the same section on Synopsys databook.
261 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
262 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
264 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
265 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
268 if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
271 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
272 dwc->link_state == DWC3_LINK_STATE_U2 ||
273 dwc->link_state == DWC3_LINK_STATE_U3);
275 if (unlikely(needs_wakeup)) {
276 ret = __dwc3_gadget_wakeup(dwc);
277 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
282 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
283 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
284 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
286 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
288 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
289 if (!(reg & DWC3_DEPCMD_CMDACT)) {
290 int cmd_status = DWC3_DEPCMD_STATUS(reg);
292 dwc3_trace(trace_dwc3_gadget,
293 "Command Complete --> %d",
296 switch (cmd_status) {
300 case DEPEVT_TRANSFER_NO_RESOURCE:
301 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
304 case DEPEVT_TRANSFER_BUS_EXPIRY:
306 * SW issues START TRANSFER command to
307 * isochronous ep with future frame interval. If
308 * future interval time has already passed when
309 * core receives the command, it will respond
310 * with an error status of 'Bus Expiry'.
312 * Instead of always returning -EINVAL, let's
313 * give a hint to the gadget driver that this is
314 * the case by returning -EAGAIN.
316 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
320 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
327 * We can't sleep here, because it is also called from
332 dwc3_trace(trace_dwc3_gadget,
333 "Command Timed Out");
339 if (unlikely(susphy)) {
340 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
341 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
342 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
348 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
350 struct dwc3 *dwc = dep->dwc;
351 struct dwc3_gadget_ep_cmd_params params;
352 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
355 * As of core revision 2.60a the recommended programming model
356 * is to set the ClearPendIN bit when issuing a Clear Stall EP
357 * command for IN endpoints. This is to prevent an issue where
358 * some (non-compliant) hosts may not send ACK TPs for pending
359 * IN transfers due to a mishandled error condition. Synopsys
362 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
363 cmd |= DWC3_DEPCMD_CLEARPENDIN;
365 memset(¶ms, 0, sizeof(params));
367 return dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
370 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
371 struct dwc3_trb *trb)
373 u32 offset = (char *) trb - (char *) dep->trb_pool;
375 return dep->trb_pool_dma + offset;
378 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
380 struct dwc3 *dwc = dep->dwc;
385 dep->trb_pool = dma_alloc_coherent(dwc->dev,
386 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
387 &dep->trb_pool_dma, GFP_KERNEL);
388 if (!dep->trb_pool) {
389 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
397 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
399 struct dwc3 *dwc = dep->dwc;
401 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
402 dep->trb_pool, dep->trb_pool_dma);
404 dep->trb_pool = NULL;
405 dep->trb_pool_dma = 0;
408 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
411 * dwc3_gadget_start_config - Configure EP resources
412 * @dwc: pointer to our controller context structure
413 * @dep: endpoint that is being enabled
415 * The assignment of transfer resources cannot perfectly follow the
416 * data book due to the fact that the controller driver does not have
417 * all knowledge of the configuration in advance. It is given this
418 * information piecemeal by the composite gadget framework after every
419 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
420 * programming model in this scenario can cause errors. For two
423 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
424 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
425 * multiple interfaces.
427 * 2) The databook does not mention doing more DEPXFERCFG for new
428 * endpoint on alt setting (8.1.6).
430 * The following simplified method is used instead:
432 * All hardware endpoints can be assigned a transfer resource and this
433 * setting will stay persistent until either a core reset or
434 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
435 * do DEPXFERCFG for every hardware endpoint as well. We are
436 * guaranteed that there are as many transfer resources as endpoints.
438 * This function is called for each endpoint when it is being enabled
439 * but is triggered only when called for EP0-out, which always happens
440 * first, and which should only happen in one of the above conditions.
442 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
444 struct dwc3_gadget_ep_cmd_params params;
452 memset(¶ms, 0x00, sizeof(params));
453 cmd = DWC3_DEPCMD_DEPSTARTCFG;
455 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
459 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
460 struct dwc3_ep *dep = dwc->eps[i];
465 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
473 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
474 const struct usb_endpoint_descriptor *desc,
475 const struct usb_ss_ep_comp_descriptor *comp_desc,
476 bool ignore, bool restore)
478 struct dwc3_gadget_ep_cmd_params params;
480 memset(¶ms, 0x00, sizeof(params));
482 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
483 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
485 /* Burst size is only needed in SuperSpeed mode */
486 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
487 u32 burst = dep->endpoint.maxburst;
488 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
492 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
495 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
496 params.param2 |= dep->saved_state;
499 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
500 | DWC3_DEPCFG_XFER_NOT_READY_EN;
502 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
503 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
504 | DWC3_DEPCFG_STREAM_EVENT_EN;
505 dep->stream_capable = true;
508 if (!usb_endpoint_xfer_control(desc))
509 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
512 * We are doing 1:1 mapping for endpoints, meaning
513 * Physical Endpoints 2 maps to Logical Endpoint 2 and
514 * so on. We consider the direction bit as part of the physical
515 * endpoint number. So USB endpoint 0x81 is 0x03.
517 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
520 * We must use the lower 16 TX FIFOs even though
524 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
526 if (desc->bInterval) {
527 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
528 dep->interval = 1 << (desc->bInterval - 1);
531 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
532 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
535 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
537 struct dwc3_gadget_ep_cmd_params params;
539 memset(¶ms, 0x00, sizeof(params));
541 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
543 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
544 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
548 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
549 * @dep: endpoint to be initialized
550 * @desc: USB Endpoint Descriptor
552 * Caller should take care of locking
554 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
555 const struct usb_endpoint_descriptor *desc,
556 const struct usb_ss_ep_comp_descriptor *comp_desc,
557 bool ignore, bool restore)
559 struct dwc3 *dwc = dep->dwc;
563 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
565 if (!(dep->flags & DWC3_EP_ENABLED)) {
566 ret = dwc3_gadget_start_config(dwc, dep);
571 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
576 if (!(dep->flags & DWC3_EP_ENABLED)) {
577 struct dwc3_trb *trb_st_hw;
578 struct dwc3_trb *trb_link;
580 dep->endpoint.desc = desc;
581 dep->comp_desc = comp_desc;
582 dep->type = usb_endpoint_type(desc);
583 dep->flags |= DWC3_EP_ENABLED;
585 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
586 reg |= DWC3_DALEPENA_EP(dep->number);
587 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
589 if (usb_endpoint_xfer_control(desc))
592 /* Link TRB. The HWO bit is never reset */
593 trb_st_hw = &dep->trb_pool[0];
595 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
596 memset(trb_link, 0, sizeof(*trb_link));
598 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
599 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
600 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
601 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
605 switch (usb_endpoint_type(desc)) {
606 case USB_ENDPOINT_XFER_CONTROL:
607 /* don't change name */
609 case USB_ENDPOINT_XFER_ISOC:
610 strlcat(dep->name, "-isoc", sizeof(dep->name));
612 case USB_ENDPOINT_XFER_BULK:
613 strlcat(dep->name, "-bulk", sizeof(dep->name));
615 case USB_ENDPOINT_XFER_INT:
616 strlcat(dep->name, "-int", sizeof(dep->name));
619 dev_err(dwc->dev, "invalid endpoint transfer type\n");
625 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
626 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
628 struct dwc3_request *req;
630 if (!list_empty(&dep->started_list)) {
631 dwc3_stop_active_transfer(dwc, dep->number, true);
633 /* - giveback all requests to gadget driver */
634 while (!list_empty(&dep->started_list)) {
635 req = next_request(&dep->started_list);
637 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
641 while (!list_empty(&dep->pending_list)) {
642 req = next_request(&dep->pending_list);
644 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
649 * __dwc3_gadget_ep_disable - Disables a HW endpoint
650 * @dep: the endpoint to disable
652 * This function also removes requests which are currently processed ny the
653 * hardware and those which are not yet scheduled.
654 * Caller should take care of locking.
656 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
658 struct dwc3 *dwc = dep->dwc;
661 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
663 dwc3_remove_requests(dwc, dep);
665 /* make sure HW endpoint isn't stalled */
666 if (dep->flags & DWC3_EP_STALL)
667 __dwc3_gadget_ep_set_halt(dep, 0, false);
669 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
670 reg &= ~DWC3_DALEPENA_EP(dep->number);
671 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
673 dep->stream_capable = false;
674 dep->endpoint.desc = NULL;
675 dep->comp_desc = NULL;
679 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
681 (dep->number & 1) ? "in" : "out");
686 /* -------------------------------------------------------------------------- */
688 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
689 const struct usb_endpoint_descriptor *desc)
694 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
699 /* -------------------------------------------------------------------------- */
701 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
702 const struct usb_endpoint_descriptor *desc)
709 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
710 pr_debug("dwc3: invalid parameters\n");
714 if (!desc->wMaxPacketSize) {
715 pr_debug("dwc3: missing wMaxPacketSize\n");
719 dep = to_dwc3_ep(ep);
722 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
723 "%s is already enabled\n",
727 spin_lock_irqsave(&dwc->lock, flags);
728 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
729 spin_unlock_irqrestore(&dwc->lock, flags);
734 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
742 pr_debug("dwc3: invalid parameters\n");
746 dep = to_dwc3_ep(ep);
749 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
750 "%s is already disabled\n",
754 spin_lock_irqsave(&dwc->lock, flags);
755 ret = __dwc3_gadget_ep_disable(dep);
756 spin_unlock_irqrestore(&dwc->lock, flags);
761 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
764 struct dwc3_request *req;
765 struct dwc3_ep *dep = to_dwc3_ep(ep);
767 req = kzalloc(sizeof(*req), gfp_flags);
771 req->epnum = dep->number;
774 trace_dwc3_alloc_request(req);
776 return &req->request;
779 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
780 struct usb_request *request)
782 struct dwc3_request *req = to_dwc3_request(request);
784 trace_dwc3_free_request(req);
789 * dwc3_prepare_one_trb - setup one TRB from one request
790 * @dep: endpoint for which this request is prepared
791 * @req: dwc3_request pointer
793 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
794 struct dwc3_request *req, dma_addr_t dma,
795 unsigned length, unsigned last, unsigned chain, unsigned node)
797 struct dwc3_trb *trb;
799 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
800 dep->name, req, (unsigned long long) dma,
801 length, last ? " last" : "",
802 chain ? " chain" : "");
805 trb = &dep->trb_pool[dep->trb_enqueue];
808 dwc3_gadget_move_started_request(req);
810 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
811 req->first_trb_index = dep->trb_enqueue;
814 dwc3_ep_inc_enq(dep);
815 /* Skip the LINK-TRB */
816 if (dwc3_ep_is_last_trb(dep->trb_enqueue))
817 dwc3_ep_inc_enq(dep);
819 trb->size = DWC3_TRB_SIZE_LENGTH(length);
820 trb->bpl = lower_32_bits(dma);
821 trb->bph = upper_32_bits(dma);
823 switch (usb_endpoint_type(dep->endpoint.desc)) {
824 case USB_ENDPOINT_XFER_CONTROL:
825 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
828 case USB_ENDPOINT_XFER_ISOC:
830 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
832 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
834 /* always enable Interrupt on Missed ISOC */
835 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
838 case USB_ENDPOINT_XFER_BULK:
839 case USB_ENDPOINT_XFER_INT:
840 trb->ctrl = DWC3_TRBCTL_NORMAL;
844 * This is only possible with faulty memory because we
845 * checked it already :)
850 /* always enable Continue on Short Packet */
851 trb->ctrl |= DWC3_TRB_CTRL_CSP;
853 if (!req->request.no_interrupt && !chain)
854 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
857 trb->ctrl |= DWC3_TRB_CTRL_LST;
860 trb->ctrl |= DWC3_TRB_CTRL_CHN;
862 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
863 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
865 trb->ctrl |= DWC3_TRB_CTRL_HWO;
867 trace_dwc3_prepare_trb(dep, trb);
870 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
872 struct dwc3_trb *tmp;
875 * If enqueue & dequeue are equal than it is either full or empty.
877 * One way to know for sure is if the TRB right before us has HWO bit
878 * set or not. If it has, then we're definitely full and can't fit any
879 * more transfers in our ring.
881 if (dep->trb_enqueue == dep->trb_dequeue) {
882 /* If we're full, enqueue/dequeue are > 0 */
883 if (dep->trb_enqueue) {
884 tmp = &dep->trb_pool[dep->trb_enqueue - 1];
885 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
889 return DWC3_TRB_NUM - 1;
892 return dep->trb_dequeue - dep->trb_enqueue;
895 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
896 struct dwc3_request *req, unsigned int trbs_left)
898 struct usb_request *request = &req->request;
899 struct scatterlist *sg = request->sg;
900 struct scatterlist *s;
901 unsigned int last = false;
906 for_each_sg(sg, s, request->num_mapped_sgs, i) {
907 unsigned chain = true;
909 length = sg_dma_len(s);
910 dma = sg_dma_address(s);
913 if (list_is_last(&req->list, &dep->pending_list))
925 dwc3_prepare_one_trb(dep, req, dma, length,
933 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
934 struct dwc3_request *req, unsigned int trbs_left)
936 unsigned int last = false;
940 dma = req->request.dma;
941 length = req->request.length;
946 /* Is this the last request? */
947 if (list_is_last(&req->list, &dep->pending_list))
950 dwc3_prepare_one_trb(dep, req, dma, length,
955 * dwc3_prepare_trbs - setup TRBs from requests
956 * @dep: endpoint for which requests are being prepared
958 * The function goes through the requests list and sets up TRBs for the
959 * transfers. The function returns once there are no more TRBs available or
960 * it runs out of requests.
962 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
964 struct dwc3_request *req, *n;
967 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
969 trbs_left = dwc3_calc_trbs_left(dep);
971 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
972 if (req->request.num_mapped_sgs > 0)
973 dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
975 dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
982 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
984 struct dwc3_gadget_ep_cmd_params params;
985 struct dwc3_request *req;
986 struct dwc3 *dwc = dep->dwc;
991 starting = !(dep->flags & DWC3_EP_BUSY);
993 dwc3_prepare_trbs(dep);
994 req = next_request(&dep->started_list);
996 dep->flags |= DWC3_EP_PENDING_REQUEST;
1000 memset(¶ms, 0, sizeof(params));
1003 params.param0 = upper_32_bits(req->trb_dma);
1004 params.param1 = lower_32_bits(req->trb_dma);
1005 cmd = DWC3_DEPCMD_STARTTRANSFER;
1007 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1010 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1011 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1014 * FIXME we need to iterate over the list of requests
1015 * here and stop, unmap, free and del each of the linked
1016 * requests instead of what we do now.
1018 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1020 list_del(&req->list);
1024 dep->flags |= DWC3_EP_BUSY;
1027 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1029 WARN_ON_ONCE(!dep->resource_index);
1035 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1036 struct dwc3_ep *dep, u32 cur_uf)
1040 if (list_empty(&dep->pending_list)) {
1041 dwc3_trace(trace_dwc3_gadget,
1042 "ISOC ep %s run out for requests",
1044 dep->flags |= DWC3_EP_PENDING_REQUEST;
1048 /* 4 micro frames in the future */
1049 uf = cur_uf + dep->interval * 4;
1051 __dwc3_gadget_kick_transfer(dep, uf);
1054 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1055 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1059 mask = ~(dep->interval - 1);
1060 cur_uf = event->parameters & mask;
1062 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1065 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1067 struct dwc3 *dwc = dep->dwc;
1070 if (!dep->endpoint.desc) {
1071 dwc3_trace(trace_dwc3_gadget,
1072 "trying to queue request %p to disabled %s\n",
1073 &req->request, dep->endpoint.name);
1077 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1078 &req->request, req->dep->name)) {
1079 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1080 &req->request, req->dep->name);
1084 req->request.actual = 0;
1085 req->request.status = -EINPROGRESS;
1086 req->direction = dep->direction;
1087 req->epnum = dep->number;
1089 trace_dwc3_ep_queue(req);
1092 * Per databook, the total size of buffer must be a multiple
1093 * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1094 * configed for endpoints in dwc3_gadget_set_ep_config(),
1095 * set to usb_endpoint_descriptor->wMaxPacketSize.
1097 if (dep->direction == 0 &&
1098 req->request.length % dep->endpoint.desc->wMaxPacketSize)
1099 req->request.length = roundup(req->request.length,
1100 dep->endpoint.desc->wMaxPacketSize);
1103 * We only add to our list of requests now and
1104 * start consuming the list once we get XferNotReady
1107 * That way, we avoid doing anything that we don't need
1108 * to do now and defer it until the point we receive a
1109 * particular token from the Host side.
1111 * This will also avoid Host cancelling URBs due to too
1114 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1119 list_add_tail(&req->list, &dep->pending_list);
1122 * If there are no pending requests and the endpoint isn't already
1123 * busy, we will just start the request straight away.
1125 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1126 * little bit faster.
1128 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1129 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1130 !(dep->flags & DWC3_EP_BUSY)) {
1131 ret = __dwc3_gadget_kick_transfer(dep, 0);
1136 * There are a few special cases:
1138 * 1. XferNotReady with empty list of requests. We need to kick the
1139 * transfer here in that situation, otherwise we will be NAKing
1140 * forever. If we get XferNotReady before gadget driver has a
1141 * chance to queue a request, we will ACK the IRQ but won't be
1142 * able to receive the data until the next request is queued.
1143 * The following code is handling exactly that.
1146 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1148 * If xfernotready is already elapsed and it is a case
1149 * of isoc transfer, then issue END TRANSFER, so that
1150 * you can receive xfernotready again and can have
1151 * notion of current microframe.
1153 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1154 if (list_empty(&dep->started_list)) {
1155 dwc3_stop_active_transfer(dwc, dep->number, true);
1156 dep->flags = DWC3_EP_ENABLED;
1161 ret = __dwc3_gadget_kick_transfer(dep, 0);
1163 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1169 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1170 * kick the transfer here after queuing a request, otherwise the
1171 * core may not see the modified TRB(s).
1173 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1174 (dep->flags & DWC3_EP_BUSY) &&
1175 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1176 WARN_ON_ONCE(!dep->resource_index);
1177 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1182 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1183 * right away, otherwise host will not know we have streams to be
1186 if (dep->stream_capable)
1187 ret = __dwc3_gadget_kick_transfer(dep, 0);
1190 if (ret && ret != -EBUSY)
1191 dwc3_trace(trace_dwc3_gadget,
1192 "%s: failed to kick transfers\n",
1200 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1201 struct usb_request *request)
1203 dwc3_gadget_ep_free_request(ep, request);
1206 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1208 struct dwc3_request *req;
1209 struct usb_request *request;
1210 struct usb_ep *ep = &dep->endpoint;
1212 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1213 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1217 request->length = 0;
1218 request->buf = dwc->zlp_buf;
1219 request->complete = __dwc3_gadget_ep_zlp_complete;
1221 req = to_dwc3_request(request);
1223 return __dwc3_gadget_ep_queue(dep, req);
1226 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1229 struct dwc3_request *req = to_dwc3_request(request);
1230 struct dwc3_ep *dep = to_dwc3_ep(ep);
1231 struct dwc3 *dwc = dep->dwc;
1233 unsigned long flags;
1237 spin_lock_irqsave(&dwc->lock, flags);
1238 ret = __dwc3_gadget_ep_queue(dep, req);
1241 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1242 * setting request->zero, instead of doing magic, we will just queue an
1243 * extra usb_request ourselves so that it gets handled the same way as
1244 * any other request.
1246 if (ret == 0 && request->zero && request->length &&
1247 (request->length % ep->desc->wMaxPacketSize == 0))
1248 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1250 spin_unlock_irqrestore(&dwc->lock, flags);
1255 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1256 struct usb_request *request)
1258 struct dwc3_request *req = to_dwc3_request(request);
1259 struct dwc3_request *r = NULL;
1261 struct dwc3_ep *dep = to_dwc3_ep(ep);
1262 struct dwc3 *dwc = dep->dwc;
1264 unsigned long flags;
1267 trace_dwc3_ep_dequeue(req);
1269 spin_lock_irqsave(&dwc->lock, flags);
1271 list_for_each_entry(r, &dep->pending_list, list) {
1277 list_for_each_entry(r, &dep->started_list, list) {
1282 /* wait until it is processed */
1283 dwc3_stop_active_transfer(dwc, dep->number, true);
1286 dev_err(dwc->dev, "request %p was not queued to %s\n",
1293 /* giveback the request */
1294 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1297 spin_unlock_irqrestore(&dwc->lock, flags);
1302 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1304 struct dwc3_gadget_ep_cmd_params params;
1305 struct dwc3 *dwc = dep->dwc;
1308 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1309 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1313 memset(¶ms, 0x00, sizeof(params));
1316 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1317 (!list_empty(&dep->started_list) ||
1318 !list_empty(&dep->pending_list)))) {
1319 dwc3_trace(trace_dwc3_gadget,
1320 "%s: pending request, cannot halt",
1325 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1326 DWC3_DEPCMD_SETSTALL, ¶ms);
1328 dev_err(dwc->dev, "failed to set STALL on %s\n",
1331 dep->flags |= DWC3_EP_STALL;
1333 ret = dwc3_send_clear_stall_ep_cmd(dep);
1335 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1338 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1344 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1346 struct dwc3_ep *dep = to_dwc3_ep(ep);
1347 struct dwc3 *dwc = dep->dwc;
1349 unsigned long flags;
1353 spin_lock_irqsave(&dwc->lock, flags);
1354 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1355 spin_unlock_irqrestore(&dwc->lock, flags);
1360 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1362 struct dwc3_ep *dep = to_dwc3_ep(ep);
1363 struct dwc3 *dwc = dep->dwc;
1364 unsigned long flags;
1367 spin_lock_irqsave(&dwc->lock, flags);
1368 dep->flags |= DWC3_EP_WEDGE;
1370 if (dep->number == 0 || dep->number == 1)
1371 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1373 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1374 spin_unlock_irqrestore(&dwc->lock, flags);
1379 /* -------------------------------------------------------------------------- */
1381 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1382 .bLength = USB_DT_ENDPOINT_SIZE,
1383 .bDescriptorType = USB_DT_ENDPOINT,
1384 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1387 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1388 .enable = dwc3_gadget_ep0_enable,
1389 .disable = dwc3_gadget_ep0_disable,
1390 .alloc_request = dwc3_gadget_ep_alloc_request,
1391 .free_request = dwc3_gadget_ep_free_request,
1392 .queue = dwc3_gadget_ep0_queue,
1393 .dequeue = dwc3_gadget_ep_dequeue,
1394 .set_halt = dwc3_gadget_ep0_set_halt,
1395 .set_wedge = dwc3_gadget_ep_set_wedge,
1398 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1399 .enable = dwc3_gadget_ep_enable,
1400 .disable = dwc3_gadget_ep_disable,
1401 .alloc_request = dwc3_gadget_ep_alloc_request,
1402 .free_request = dwc3_gadget_ep_free_request,
1403 .queue = dwc3_gadget_ep_queue,
1404 .dequeue = dwc3_gadget_ep_dequeue,
1405 .set_halt = dwc3_gadget_ep_set_halt,
1406 .set_wedge = dwc3_gadget_ep_set_wedge,
1409 /* -------------------------------------------------------------------------- */
1411 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1413 struct dwc3 *dwc = gadget_to_dwc(g);
1416 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1417 return DWC3_DSTS_SOFFN(reg);
1420 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1422 unsigned long timeout;
1431 * According to the Databook Remote wakeup request should
1432 * be issued only when the device is in early suspend state.
1434 * We can check that via USB Link State bits in DSTS register.
1436 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1438 speed = reg & DWC3_DSTS_CONNECTSPD;
1439 if (speed == DWC3_DSTS_SUPERSPEED) {
1440 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1444 link_state = DWC3_DSTS_USBLNKST(reg);
1446 switch (link_state) {
1447 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1448 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1451 dwc3_trace(trace_dwc3_gadget,
1452 "can't wakeup from '%s'\n",
1453 dwc3_gadget_link_string(link_state));
1457 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1459 dev_err(dwc->dev, "failed to put link in Recovery\n");
1463 /* Recent versions do this automatically */
1464 if (dwc->revision < DWC3_REVISION_194A) {
1465 /* write zeroes to Link Change Request */
1466 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1467 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1468 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1471 /* poll until Link State changes to ON */
1472 timeout = jiffies + msecs_to_jiffies(100);
1474 while (!time_after(jiffies, timeout)) {
1475 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1477 /* in HS, means ON */
1478 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1482 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1483 dev_err(dwc->dev, "failed to send remote wakeup\n");
1490 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1492 struct dwc3 *dwc = gadget_to_dwc(g);
1493 unsigned long flags;
1496 spin_lock_irqsave(&dwc->lock, flags);
1497 ret = __dwc3_gadget_wakeup(dwc);
1498 spin_unlock_irqrestore(&dwc->lock, flags);
1503 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1506 struct dwc3 *dwc = gadget_to_dwc(g);
1507 unsigned long flags;
1509 spin_lock_irqsave(&dwc->lock, flags);
1510 g->is_selfpowered = !!is_selfpowered;
1511 spin_unlock_irqrestore(&dwc->lock, flags);
1516 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1521 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1523 if (dwc->revision <= DWC3_REVISION_187A) {
1524 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1525 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1528 if (dwc->revision >= DWC3_REVISION_194A)
1529 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1530 reg |= DWC3_DCTL_RUN_STOP;
1532 if (dwc->has_hibernation)
1533 reg |= DWC3_DCTL_KEEP_CONNECT;
1535 dwc->pullups_connected = true;
1537 reg &= ~DWC3_DCTL_RUN_STOP;
1539 if (dwc->has_hibernation && !suspend)
1540 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1542 dwc->pullups_connected = false;
1545 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1548 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1550 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1553 if (reg & DWC3_DSTS_DEVCTRLHLT)
1562 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1564 ? dwc->gadget_driver->function : "no-function",
1565 is_on ? "connect" : "disconnect");
1570 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1572 struct dwc3 *dwc = gadget_to_dwc(g);
1573 unsigned long flags;
1578 spin_lock_irqsave(&dwc->lock, flags);
1579 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1580 spin_unlock_irqrestore(&dwc->lock, flags);
1585 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1589 /* Enable all but Start and End of Frame IRQs */
1590 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1591 DWC3_DEVTEN_EVNTOVERFLOWEN |
1592 DWC3_DEVTEN_CMDCMPLTEN |
1593 DWC3_DEVTEN_ERRTICERREN |
1594 DWC3_DEVTEN_WKUPEVTEN |
1595 DWC3_DEVTEN_ULSTCNGEN |
1596 DWC3_DEVTEN_CONNECTDONEEN |
1597 DWC3_DEVTEN_USBRSTEN |
1598 DWC3_DEVTEN_DISCONNEVTEN);
1600 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1603 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1605 /* mask all interrupts */
1606 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1609 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1610 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1613 * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1614 * dwc: pointer to our context structure
1616 * The following looks like complex but it's actually very simple. In order to
1617 * calculate the number of packets we can burst at once on OUT transfers, we're
1618 * gonna use RxFIFO size.
1620 * To calculate RxFIFO size we need two numbers:
1621 * MDWIDTH = size, in bits, of the internal memory bus
1622 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1624 * Given these two numbers, the formula is simple:
1626 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1628 * 24 bytes is for 3x SETUP packets
1629 * 16 bytes is a clock domain crossing tolerance
1631 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1633 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1640 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1641 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1643 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1644 nump = min_t(u32, nump, 16);
1647 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1648 reg &= ~DWC3_DCFG_NUMP_MASK;
1649 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1650 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1653 static int __dwc3_gadget_start(struct dwc3 *dwc)
1655 struct dwc3_ep *dep;
1659 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1660 reg &= ~(DWC3_DCFG_SPEED_MASK);
1663 * WORKAROUND: DWC3 revision < 2.20a have an issue
1664 * which would cause metastability state on Run/Stop
1665 * bit if we try to force the IP to USB2-only mode.
1667 * Because of that, we cannot configure the IP to any
1668 * speed other than the SuperSpeed
1672 * STAR#9000525659: Clock Domain Crossing on DCTL in
1675 if (dwc->revision < DWC3_REVISION_220A) {
1676 reg |= DWC3_DCFG_SUPERSPEED;
1678 switch (dwc->maximum_speed) {
1680 reg |= DWC3_DSTS_LOWSPEED;
1682 case USB_SPEED_FULL:
1683 reg |= DWC3_DSTS_FULLSPEED1;
1685 case USB_SPEED_HIGH:
1686 reg |= DWC3_DSTS_HIGHSPEED;
1688 case USB_SPEED_SUPER: /* FALLTHROUGH */
1689 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1691 reg |= DWC3_DSTS_SUPERSPEED;
1694 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1697 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1698 * field instead of letting dwc3 itself calculate that automatically.
1700 * This way, we maximize the chances that we'll be able to get several
1701 * bursts of data without going through any sort of endpoint throttling.
1703 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1704 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1705 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1707 dwc3_gadget_setup_nump(dwc);
1709 /* Start with SuperSpeed Default */
1710 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1713 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1716 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1721 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1724 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1728 /* begin to receive SETUP packets */
1729 dwc->ep0state = EP0_SETUP_PHASE;
1730 dwc3_ep0_out_start(dwc);
1732 dwc3_gadget_enable_irq(dwc);
1737 __dwc3_gadget_ep_disable(dwc->eps[0]);
1743 static int dwc3_gadget_start(struct usb_gadget *g,
1744 struct usb_gadget_driver *driver)
1746 struct dwc3 *dwc = gadget_to_dwc(g);
1747 unsigned long flags;
1751 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1752 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1753 IRQF_SHARED, "dwc3", dwc->ev_buf);
1755 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1760 spin_lock_irqsave(&dwc->lock, flags);
1761 if (dwc->gadget_driver) {
1762 dev_err(dwc->dev, "%s is already bound to %s\n",
1764 dwc->gadget_driver->driver.name);
1769 dwc->gadget_driver = driver;
1771 __dwc3_gadget_start(dwc);
1772 spin_unlock_irqrestore(&dwc->lock, flags);
1777 spin_unlock_irqrestore(&dwc->lock, flags);
1784 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1786 dwc3_gadget_disable_irq(dwc);
1787 __dwc3_gadget_ep_disable(dwc->eps[0]);
1788 __dwc3_gadget_ep_disable(dwc->eps[1]);
1791 static int dwc3_gadget_stop(struct usb_gadget *g)
1793 struct dwc3 *dwc = gadget_to_dwc(g);
1794 unsigned long flags;
1797 spin_lock_irqsave(&dwc->lock, flags);
1798 __dwc3_gadget_stop(dwc);
1799 dwc->gadget_driver = NULL;
1800 spin_unlock_irqrestore(&dwc->lock, flags);
1802 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1803 free_irq(irq, dwc->ev_buf);
1808 static const struct usb_gadget_ops dwc3_gadget_ops = {
1809 .get_frame = dwc3_gadget_get_frame,
1810 .wakeup = dwc3_gadget_wakeup,
1811 .set_selfpowered = dwc3_gadget_set_selfpowered,
1812 .pullup = dwc3_gadget_pullup,
1813 .udc_start = dwc3_gadget_start,
1814 .udc_stop = dwc3_gadget_stop,
1817 /* -------------------------------------------------------------------------- */
1819 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1820 u8 num, u32 direction)
1822 struct dwc3_ep *dep;
1825 for (i = 0; i < num; i++) {
1826 u8 epnum = (i << 1) | (!!direction);
1828 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1833 dep->number = epnum;
1834 dep->direction = !!direction;
1835 dwc->eps[epnum] = dep;
1837 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1838 (epnum & 1) ? "in" : "out");
1840 dep->endpoint.name = dep->name;
1842 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1844 if (epnum == 0 || epnum == 1) {
1845 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1846 dep->endpoint.maxburst = 1;
1847 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1849 dwc->gadget.ep0 = &dep->endpoint;
1853 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1854 dep->endpoint.max_streams = 15;
1855 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1856 list_add_tail(&dep->endpoint.ep_list,
1857 &dwc->gadget.ep_list);
1859 ret = dwc3_alloc_trb_pool(dep);
1864 if (epnum == 0 || epnum == 1) {
1865 dep->endpoint.caps.type_control = true;
1867 dep->endpoint.caps.type_iso = true;
1868 dep->endpoint.caps.type_bulk = true;
1869 dep->endpoint.caps.type_int = true;
1872 dep->endpoint.caps.dir_in = !!direction;
1873 dep->endpoint.caps.dir_out = !direction;
1875 INIT_LIST_HEAD(&dep->pending_list);
1876 INIT_LIST_HEAD(&dep->started_list);
1882 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1886 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1888 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1890 dwc3_trace(trace_dwc3_gadget,
1891 "failed to allocate OUT endpoints");
1895 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1897 dwc3_trace(trace_dwc3_gadget,
1898 "failed to allocate IN endpoints");
1905 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1907 struct dwc3_ep *dep;
1910 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1911 dep = dwc->eps[epnum];
1915 * Physical endpoints 0 and 1 are special; they form the
1916 * bi-directional USB endpoint 0.
1918 * For those two physical endpoints, we don't allocate a TRB
1919 * pool nor do we add them the endpoints list. Due to that, we
1920 * shouldn't do these two operations otherwise we would end up
1921 * with all sorts of bugs when removing dwc3.ko.
1923 if (epnum != 0 && epnum != 1) {
1924 dwc3_free_trb_pool(dep);
1925 list_del(&dep->endpoint.ep_list);
1932 /* -------------------------------------------------------------------------- */
1934 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1935 struct dwc3_request *req, struct dwc3_trb *trb,
1936 const struct dwc3_event_depevt *event, int status)
1939 unsigned int s_pkt = 0;
1940 unsigned int trb_status;
1942 trace_dwc3_complete_trb(dep, trb);
1944 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1946 * We continue despite the error. There is not much we
1947 * can do. If we don't clean it up we loop forever. If
1948 * we skip the TRB then it gets overwritten after a
1949 * while since we use them in a ring buffer. A BUG()
1950 * would help. Lets hope that if this occurs, someone
1951 * fixes the root cause instead of looking away :)
1953 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1955 count = trb->size & DWC3_TRB_SIZE_MASK;
1957 if (dep->direction) {
1959 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1960 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1961 dwc3_trace(trace_dwc3_gadget,
1962 "%s: incomplete IN transfer\n",
1965 * If missed isoc occurred and there is
1966 * no request queued then issue END
1967 * TRANSFER, so that core generates
1968 * next xfernotready and we will issue
1969 * a fresh START TRANSFER.
1970 * If there are still queued request
1971 * then wait, do not issue either END
1972 * or UPDATE TRANSFER, just attach next
1973 * request in pending_list during
1974 * giveback.If any future queued request
1975 * is successfully transferred then we
1976 * will issue UPDATE TRANSFER for all
1977 * request in the pending_list.
1979 dep->flags |= DWC3_EP_MISSED_ISOC;
1981 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1983 status = -ECONNRESET;
1986 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1989 if (count && (event->status & DEPEVT_STATUS_SHORT))
1994 * We assume here we will always receive the entire data block
1995 * which we should receive. Meaning, if we program RX to
1996 * receive 4K but we receive only 2K, we assume that's all we
1997 * should receive and we simply bounce the request back to the
1998 * gadget driver for further processing.
2000 req->request.actual += req->request.length - count;
2003 if ((event->status & DEPEVT_STATUS_LST) &&
2004 (trb->ctrl & (DWC3_TRB_CTRL_LST |
2005 DWC3_TRB_CTRL_HWO)))
2007 if ((event->status & DEPEVT_STATUS_IOC) &&
2008 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2013 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2014 const struct dwc3_event_depevt *event, int status)
2016 struct dwc3_request *req;
2017 struct dwc3_trb *trb;
2023 req = next_request(&dep->started_list);
2024 if (WARN_ON_ONCE(!req))
2029 slot = req->first_trb_index + i;
2030 if (slot == DWC3_TRB_NUM - 1)
2032 slot %= DWC3_TRB_NUM;
2033 trb = &dep->trb_pool[slot];
2035 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2039 } while (++i < req->request.num_mapped_sgs);
2041 dwc3_gadget_giveback(dep, req, status);
2047 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2048 list_empty(&dep->started_list)) {
2049 if (list_empty(&dep->pending_list)) {
2051 * If there is no entry in request list then do
2052 * not issue END TRANSFER now. Just set PENDING
2053 * flag, so that END TRANSFER is issued when an
2054 * entry is added into request list.
2056 dep->flags = DWC3_EP_PENDING_REQUEST;
2058 dwc3_stop_active_transfer(dwc, dep->number, true);
2059 dep->flags = DWC3_EP_ENABLED;
2067 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2068 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2070 unsigned status = 0;
2072 u32 is_xfer_complete;
2074 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2076 if (event->status & DEPEVT_STATUS_BUSERR)
2077 status = -ECONNRESET;
2079 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2080 if (clean_busy && (is_xfer_complete ||
2081 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2082 dep->flags &= ~DWC3_EP_BUSY;
2085 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2086 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2088 if (dwc->revision < DWC3_REVISION_183A) {
2092 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2095 if (!(dep->flags & DWC3_EP_ENABLED))
2098 if (!list_empty(&dep->started_list))
2102 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2104 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2109 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2112 ret = __dwc3_gadget_kick_transfer(dep, 0);
2113 if (!ret || ret == -EBUSY)
2118 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2119 const struct dwc3_event_depevt *event)
2121 struct dwc3_ep *dep;
2122 u8 epnum = event->endpoint_number;
2124 dep = dwc->eps[epnum];
2126 if (!(dep->flags & DWC3_EP_ENABLED))
2129 if (epnum == 0 || epnum == 1) {
2130 dwc3_ep0_interrupt(dwc, event);
2134 switch (event->endpoint_event) {
2135 case DWC3_DEPEVT_XFERCOMPLETE:
2136 dep->resource_index = 0;
2138 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2139 dwc3_trace(trace_dwc3_gadget,
2140 "%s is an Isochronous endpoint\n",
2145 dwc3_endpoint_transfer_complete(dwc, dep, event);
2147 case DWC3_DEPEVT_XFERINPROGRESS:
2148 dwc3_endpoint_transfer_complete(dwc, dep, event);
2150 case DWC3_DEPEVT_XFERNOTREADY:
2151 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2152 dwc3_gadget_start_isoc(dwc, dep, event);
2157 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2159 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2160 dep->name, active ? "Transfer Active"
2161 : "Transfer Not Active");
2163 ret = __dwc3_gadget_kick_transfer(dep, 0);
2164 if (!ret || ret == -EBUSY)
2167 dwc3_trace(trace_dwc3_gadget,
2168 "%s: failed to kick transfers\n",
2173 case DWC3_DEPEVT_STREAMEVT:
2174 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2175 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2180 switch (event->status) {
2181 case DEPEVT_STREAMEVT_FOUND:
2182 dwc3_trace(trace_dwc3_gadget,
2183 "Stream %d found and started",
2187 case DEPEVT_STREAMEVT_NOTFOUND:
2190 dwc3_trace(trace_dwc3_gadget,
2191 "unable to find suitable stream\n");
2194 case DWC3_DEPEVT_RXTXFIFOEVT:
2195 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2197 case DWC3_DEPEVT_EPCMDCMPLT:
2198 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2203 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2205 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2206 spin_unlock(&dwc->lock);
2207 dwc->gadget_driver->disconnect(&dwc->gadget);
2208 spin_lock(&dwc->lock);
2212 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2214 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2215 spin_unlock(&dwc->lock);
2216 dwc->gadget_driver->suspend(&dwc->gadget);
2217 spin_lock(&dwc->lock);
2221 static void dwc3_resume_gadget(struct dwc3 *dwc)
2223 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2224 spin_unlock(&dwc->lock);
2225 dwc->gadget_driver->resume(&dwc->gadget);
2226 spin_lock(&dwc->lock);
2230 static void dwc3_reset_gadget(struct dwc3 *dwc)
2232 if (!dwc->gadget_driver)
2235 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2236 spin_unlock(&dwc->lock);
2237 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2238 spin_lock(&dwc->lock);
2242 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2244 struct dwc3_ep *dep;
2245 struct dwc3_gadget_ep_cmd_params params;
2249 dep = dwc->eps[epnum];
2251 if (!dep->resource_index)
2255 * NOTICE: We are violating what the Databook says about the
2256 * EndTransfer command. Ideally we would _always_ wait for the
2257 * EndTransfer Command Completion IRQ, but that's causing too
2258 * much trouble synchronizing between us and gadget driver.
2260 * We have discussed this with the IP Provider and it was
2261 * suggested to giveback all requests here, but give HW some
2262 * extra time to synchronize with the interconnect. We're using
2263 * an arbitrary 100us delay for that.
2265 * Note also that a similar handling was tested by Synopsys
2266 * (thanks a lot Paul) and nothing bad has come out of it.
2267 * In short, what we're doing is:
2269 * - Issue EndTransfer WITH CMDIOC bit set
2273 cmd = DWC3_DEPCMD_ENDTRANSFER;
2274 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2275 cmd |= DWC3_DEPCMD_CMDIOC;
2276 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2277 memset(¶ms, 0, sizeof(params));
2278 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2280 dep->resource_index = 0;
2281 dep->flags &= ~DWC3_EP_BUSY;
2285 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2289 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2290 struct dwc3_ep *dep;
2292 dep = dwc->eps[epnum];
2296 if (!(dep->flags & DWC3_EP_ENABLED))
2299 dwc3_remove_requests(dwc, dep);
2303 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2307 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2308 struct dwc3_ep *dep;
2311 dep = dwc->eps[epnum];
2315 if (!(dep->flags & DWC3_EP_STALL))
2318 dep->flags &= ~DWC3_EP_STALL;
2320 ret = dwc3_send_clear_stall_ep_cmd(dep);
2325 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2329 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2330 reg &= ~DWC3_DCTL_INITU1ENA;
2331 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333 reg &= ~DWC3_DCTL_INITU2ENA;
2334 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2336 dwc3_disconnect_gadget(dwc);
2338 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2339 dwc->setup_packet_pending = false;
2340 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2343 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2348 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2349 * would cause a missing Disconnect Event if there's a
2350 * pending Setup Packet in the FIFO.
2352 * There's no suggested workaround on the official Bug
2353 * report, which states that "unless the driver/application
2354 * is doing any special handling of a disconnect event,
2355 * there is no functional issue".
2357 * Unfortunately, it turns out that we _do_ some special
2358 * handling of a disconnect event, namely complete all
2359 * pending transfers, notify gadget driver of the
2360 * disconnection, and so on.
2362 * Our suggested workaround is to follow the Disconnect
2363 * Event steps here, instead, based on a setup_packet_pending
2364 * flag. Such flag gets set whenever we have a SETUP_PENDING
2365 * status for EP0 TRBs and gets cleared on XferComplete for the
2370 * STAR#9000466709: RTL: Device : Disconnect event not
2371 * generated if setup packet pending in FIFO
2373 if (dwc->revision < DWC3_REVISION_188A) {
2374 if (dwc->setup_packet_pending)
2375 dwc3_gadget_disconnect_interrupt(dwc);
2378 dwc3_reset_gadget(dwc);
2380 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2381 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2382 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2383 dwc->test_mode = false;
2385 dwc3_stop_active_transfers(dwc);
2386 dwc3_clear_stall_all_ep(dwc);
2388 /* Reset device address to zero */
2389 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2390 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2391 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2394 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2397 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2400 * We change the clock only at SS but I dunno why I would want to do
2401 * this. Maybe it becomes part of the power saving plan.
2404 if (speed != DWC3_DSTS_SUPERSPEED)
2408 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2409 * each time on Connect Done.
2414 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2415 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2416 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2419 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2421 struct dwc3_ep *dep;
2426 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2427 speed = reg & DWC3_DSTS_CONNECTSPD;
2430 dwc3_update_ram_clk_sel(dwc, speed);
2433 case DWC3_DCFG_SUPERSPEED:
2435 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2436 * would cause a missing USB3 Reset event.
2438 * In such situations, we should force a USB3 Reset
2439 * event by calling our dwc3_gadget_reset_interrupt()
2444 * STAR#9000483510: RTL: SS : USB3 reset event may
2445 * not be generated always when the link enters poll
2447 if (dwc->revision < DWC3_REVISION_190A)
2448 dwc3_gadget_reset_interrupt(dwc);
2450 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2451 dwc->gadget.ep0->maxpacket = 512;
2452 dwc->gadget.speed = USB_SPEED_SUPER;
2454 case DWC3_DCFG_HIGHSPEED:
2455 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2456 dwc->gadget.ep0->maxpacket = 64;
2457 dwc->gadget.speed = USB_SPEED_HIGH;
2459 case DWC3_DCFG_FULLSPEED2:
2460 case DWC3_DCFG_FULLSPEED1:
2461 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2462 dwc->gadget.ep0->maxpacket = 64;
2463 dwc->gadget.speed = USB_SPEED_FULL;
2465 case DWC3_DCFG_LOWSPEED:
2466 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2467 dwc->gadget.ep0->maxpacket = 8;
2468 dwc->gadget.speed = USB_SPEED_LOW;
2472 /* Enable USB2 LPM Capability */
2474 if ((dwc->revision > DWC3_REVISION_194A)
2475 && (speed != DWC3_DCFG_SUPERSPEED)) {
2476 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2477 reg |= DWC3_DCFG_LPM_CAP;
2478 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2480 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2481 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2483 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2486 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2487 * DCFG.LPMCap is set, core responses with an ACK and the
2488 * BESL value in the LPM token is less than or equal to LPM
2491 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2492 && dwc->has_lpm_erratum,
2493 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2495 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2496 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2498 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2500 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2501 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2502 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2506 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2509 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2514 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2517 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2522 * Configure PHY via GUSB3PIPECTLn if required.
2524 * Update GTXFIFOSIZn
2526 * In both cases reset values should be sufficient.
2530 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2533 * TODO take core out of low power mode when that's
2537 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2538 spin_unlock(&dwc->lock);
2539 dwc->gadget_driver->resume(&dwc->gadget);
2540 spin_lock(&dwc->lock);
2544 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2545 unsigned int evtinfo)
2547 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2548 unsigned int pwropt;
2551 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2552 * Hibernation mode enabled which would show up when device detects
2553 * host-initiated U3 exit.
2555 * In that case, device will generate a Link State Change Interrupt
2556 * from U3 to RESUME which is only necessary if Hibernation is
2559 * There are no functional changes due to such spurious event and we
2560 * just need to ignore it.
2564 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2567 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2568 if ((dwc->revision < DWC3_REVISION_250A) &&
2569 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2570 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2571 (next == DWC3_LINK_STATE_RESUME)) {
2572 dwc3_trace(trace_dwc3_gadget,
2573 "ignoring transition U3 -> Resume");
2579 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2580 * on the link partner, the USB session might do multiple entry/exit
2581 * of low power states before a transfer takes place.
2583 * Due to this problem, we might experience lower throughput. The
2584 * suggested workaround is to disable DCTL[12:9] bits if we're
2585 * transitioning from U1/U2 to U0 and enable those bits again
2586 * after a transfer completes and there are no pending transfers
2587 * on any of the enabled endpoints.
2589 * This is the first half of that workaround.
2593 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2594 * core send LGO_Ux entering U0
2596 if (dwc->revision < DWC3_REVISION_183A) {
2597 if (next == DWC3_LINK_STATE_U0) {
2601 switch (dwc->link_state) {
2602 case DWC3_LINK_STATE_U1:
2603 case DWC3_LINK_STATE_U2:
2604 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2605 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2606 | DWC3_DCTL_ACCEPTU2ENA
2607 | DWC3_DCTL_INITU1ENA
2608 | DWC3_DCTL_ACCEPTU1ENA);
2611 dwc->u1u2 = reg & u1u2;
2615 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2625 case DWC3_LINK_STATE_U1:
2626 if (dwc->speed == USB_SPEED_SUPER)
2627 dwc3_suspend_gadget(dwc);
2629 case DWC3_LINK_STATE_U2:
2630 case DWC3_LINK_STATE_U3:
2631 dwc3_suspend_gadget(dwc);
2633 case DWC3_LINK_STATE_RESUME:
2634 dwc3_resume_gadget(dwc);
2641 dwc->link_state = next;
2644 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2645 unsigned int evtinfo)
2647 unsigned int is_ss = evtinfo & BIT(4);
2650 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2651 * have a known issue which can cause USB CV TD.9.23 to fail
2654 * Because of this issue, core could generate bogus hibernation
2655 * events which SW needs to ignore.
2659 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2660 * Device Fallback from SuperSpeed
2662 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2665 /* enter hibernation here */
2668 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2669 const struct dwc3_event_devt *event)
2671 switch (event->type) {
2672 case DWC3_DEVICE_EVENT_DISCONNECT:
2673 dwc3_gadget_disconnect_interrupt(dwc);
2675 case DWC3_DEVICE_EVENT_RESET:
2676 dwc3_gadget_reset_interrupt(dwc);
2678 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2679 dwc3_gadget_conndone_interrupt(dwc);
2681 case DWC3_DEVICE_EVENT_WAKEUP:
2682 dwc3_gadget_wakeup_interrupt(dwc);
2684 case DWC3_DEVICE_EVENT_HIBER_REQ:
2685 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2686 "unexpected hibernation event\n"))
2689 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2691 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2692 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2694 case DWC3_DEVICE_EVENT_EOPF:
2695 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2697 case DWC3_DEVICE_EVENT_SOF:
2698 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2700 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2701 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2703 case DWC3_DEVICE_EVENT_CMD_CMPL:
2704 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2706 case DWC3_DEVICE_EVENT_OVERFLOW:
2707 dwc3_trace(trace_dwc3_gadget, "Overflow");
2710 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2714 static void dwc3_process_event_entry(struct dwc3 *dwc,
2715 const union dwc3_event *event)
2717 trace_dwc3_event(event->raw);
2719 /* Endpoint IRQ, handle it and return early */
2720 if (event->type.is_devspec == 0) {
2722 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2725 switch (event->type.type) {
2726 case DWC3_EVENT_TYPE_DEV:
2727 dwc3_gadget_interrupt(dwc, &event->devt);
2729 /* REVISIT what to do with Carkit and I2C events ? */
2731 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2735 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2737 struct dwc3 *dwc = evt->dwc;
2738 irqreturn_t ret = IRQ_NONE;
2744 if (!(evt->flags & DWC3_EVENT_PENDING))
2748 union dwc3_event event;
2750 event.raw = *(u32 *) (evt->buf + evt->lpos);
2752 dwc3_process_event_entry(dwc, &event);
2755 * FIXME we wrap around correctly to the next entry as
2756 * almost all entries are 4 bytes in size. There is one
2757 * entry which has 12 bytes which is a regular entry
2758 * followed by 8 bytes data. ATM I don't know how
2759 * things are organized if we get next to the a
2760 * boundary so I worry about that once we try to handle
2763 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2766 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2770 evt->flags &= ~DWC3_EVENT_PENDING;
2773 /* Unmask interrupt */
2774 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2775 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2776 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2781 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2783 struct dwc3_event_buffer *evt = _evt;
2784 struct dwc3 *dwc = evt->dwc;
2785 unsigned long flags;
2786 irqreturn_t ret = IRQ_NONE;
2788 spin_lock_irqsave(&dwc->lock, flags);
2789 ret = dwc3_process_event_buf(evt);
2790 spin_unlock_irqrestore(&dwc->lock, flags);
2795 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2797 struct dwc3 *dwc = evt->dwc;
2801 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2802 count &= DWC3_GEVNTCOUNT_MASK;
2807 evt->flags |= DWC3_EVENT_PENDING;
2809 /* Mask interrupt */
2810 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2811 reg |= DWC3_GEVNTSIZ_INTMASK;
2812 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2814 return IRQ_WAKE_THREAD;
2817 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2819 struct dwc3_event_buffer *evt = _evt;
2821 return dwc3_check_event_buf(evt);
2825 * dwc3_gadget_init - Initializes gadget related registers
2826 * @dwc: pointer to our controller context structure
2828 * Returns 0 on success otherwise negative errno.
2830 int dwc3_gadget_init(struct dwc3 *dwc)
2834 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2835 &dwc->ctrl_req_addr, GFP_KERNEL);
2836 if (!dwc->ctrl_req) {
2837 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2842 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2843 &dwc->ep0_trb_addr, GFP_KERNEL);
2844 if (!dwc->ep0_trb) {
2845 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2850 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2851 if (!dwc->setup_buf) {
2856 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2857 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2859 if (!dwc->ep0_bounce) {
2860 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2865 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2866 if (!dwc->zlp_buf) {
2871 dwc->gadget.ops = &dwc3_gadget_ops;
2872 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2873 dwc->gadget.sg_supported = true;
2874 dwc->gadget.name = "dwc3-gadget";
2875 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2878 * FIXME We might be setting max_speed to <SUPER, however versions
2879 * <2.20a of dwc3 have an issue with metastability (documented
2880 * elsewhere in this driver) which tells us we can't set max speed to
2881 * anything lower than SUPER.
2883 * Because gadget.max_speed is only used by composite.c and function
2884 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2885 * to happen so we avoid sending SuperSpeed Capability descriptor
2886 * together with our BOS descriptor as that could confuse host into
2887 * thinking we can handle super speed.
2889 * Note that, in fact, we won't even support GetBOS requests when speed
2890 * is less than super speed because we don't have means, yet, to tell
2891 * composite.c that we are USB 2.0 + LPM ECN.
2893 if (dwc->revision < DWC3_REVISION_220A)
2894 dwc3_trace(trace_dwc3_gadget,
2895 "Changing max_speed on rev %08x\n",
2898 dwc->gadget.max_speed = dwc->maximum_speed;
2901 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2904 dwc->gadget.quirk_ep_out_aligned_size = true;
2907 * REVISIT: Here we should clear all pending IRQs to be
2908 * sure we're starting from a well known location.
2911 ret = dwc3_gadget_init_endpoints(dwc);
2915 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2917 dev_err(dwc->dev, "failed to register udc\n");
2924 kfree(dwc->zlp_buf);
2927 dwc3_gadget_free_endpoints(dwc);
2928 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2929 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2932 kfree(dwc->setup_buf);
2935 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2936 dwc->ep0_trb, dwc->ep0_trb_addr);
2939 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2940 dwc->ctrl_req, dwc->ctrl_req_addr);
2946 /* -------------------------------------------------------------------------- */
2948 void dwc3_gadget_exit(struct dwc3 *dwc)
2950 usb_del_gadget_udc(&dwc->gadget);
2952 dwc3_gadget_free_endpoints(dwc);
2954 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2955 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2957 kfree(dwc->setup_buf);
2958 kfree(dwc->zlp_buf);
2960 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2961 dwc->ep0_trb, dwc->ep0_trb_addr);
2963 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2964 dwc->ctrl_req, dwc->ctrl_req_addr);
2967 int dwc3_gadget_suspend(struct dwc3 *dwc)
2971 if (!dwc->gadget_driver)
2974 ret = dwc3_gadget_run_stop(dwc, false, false);
2978 dwc3_disconnect_gadget(dwc);
2979 __dwc3_gadget_stop(dwc);
2984 int dwc3_gadget_resume(struct dwc3 *dwc)
2988 if (!dwc->gadget_driver)
2991 ret = __dwc3_gadget_start(dwc);
2995 ret = dwc3_gadget_run_stop(dwc, true, false);
3002 __dwc3_gadget_stop(dwc);