drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 /**
  58  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  59  * @dwc: pointer to our context structure
  60  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  61  *
  62  * Caller should take care of locking. This function will
  63  * return 0 on success or -EINVAL if wrong Test Selector
  64  * is passed
  65  */
  66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  67 {
  68         u32             reg;
  69
  70         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  71         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  72
  73         switch (mode) {
  74         case TEST_J:
  75         case TEST_K:
  76         case TEST_SE0_NAK:
  77         case TEST_PACKET:
  78         case TEST_FORCE_EN:
  79                 reg |= mode << 1;
  80                 break;
  81         default:
  82                 return -EINVAL;
  83         }
  84
  85         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  86
  87         return 0;
  88 }
  89
  90 /**
  91  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  92  * @dwc: pointer to our context structure
  93  * @state: the state to put link into
  94  *
  95  * Caller should take care of locking. This function will
  96  * return 0 on success or -ETIMEDOUT.
  97  */
  98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  99 {
 100         int             retries = 10000;
 101         u32             reg;
 102
 103         /*
 104          * Wait until device controller is ready. Only applies to 1.94a and
 105          * later RTL.
 106          */
 107         if (dwc->revision >= DWC3_REVISION_194A) {
 108                 while (--retries) {
 109                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 110                         if (reg & DWC3_DSTS_DCNRD)
 111                                 udelay(5);
 112                         else
 113                                 break;
 114                 }
 115
 116                 if (retries <= 0)
 117                         return -ETIMEDOUT;
 118         }
 119
 120         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 122
 123         /* set requested state */
 124         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 125         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 126
 127         /*
 128          * The following code is racy when called from dwc3_gadget_wakeup,
 129          * and is not needed, at least on newer versions
 130          */
 131         if (dwc->revision >= DWC3_REVISION_194A)
 132                 return 0;
 133
 134         /* wait for a change in DSTS */
 135         retries = 10000;
 136         while (--retries) {
 137                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 138
 139                 if (DWC3_DSTS_USBLNKST(reg) == state)
 140                         return 0;
 141
 142                 udelay(5);
 143         }
 144
 145         dev_vdbg(dwc->dev, "link state change request timed out\n");
 146
 147         return -ETIMEDOUT;
 148 }
 149
 150 /**
 151  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 152  * @dwc: pointer to our context structure
 153  *
 154  * This function will a best effort FIFO allocation in order
 155  * to improve FIFO usage and throughput, while still allowing
 156  * us to enable as many endpoints as possible.
 157  *
 158  * Keep in mind that this operation will be highly dependent
 159  * on the configured size for RAM1 - which contains TxFifo -,
 160  * the amount of endpoints enabled on coreConsultant tool, and
 161  * the width of the Master Bus.
 162  *
 163  * In the ideal world, we would always be able to satisfy the
 164  * following equation:
 165  *
 166  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 167  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 168  *
 169  * Unfortunately, due to many variables that's not always the case.
 170  */
 171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 172 {
 173         int             last_fifo_depth = 0;
 174         int             ram1_depth;
 175         int             fifo_size;
 176         int             mdwidth;
 177         int             num;
 178
 179         if (!dwc->needs_fifo_resize)
 180                 return 0;
 181
 182         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 183         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 184
 185         /* MDWIDTH is represented in bits, we need it in bytes */
 186         mdwidth >>= 3;
 187
 188         /*
 189          * FIXME For now we will only allocate 1 wMaxPacketSize space
 190          * for each enabled endpoint, later patches will come to
 191          * improve this algorithm so that we better use the internal
 192          * FIFO space
 193          */
 194         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 195                 struct dwc3_ep  *dep = dwc->eps[num];
 196                 int             fifo_number = dep->number >> 1;
 197                 int             mult = 1;
 198                 int             tmp;
 199
 200                 if (!(dep->number & 1))
 201                         continue;
 202
 203                 if (!(dep->flags & DWC3_EP_ENABLED))
 204                         continue;
 205
 206                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 207                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 208                         mult = 3;
 209
 210                 /*
 211                  * REVISIT: the following assumes we will always have enough
 212                  * space available on the FIFO RAM for all possible use cases.
 213                  * Make sure that's true somehow and change FIFO allocation
 214                  * accordingly.
 215                  *
 216                  * If we have Bulk or Isochronous endpoints, we want
 217                  * them to be able to be very, very fast. So we're giving
 218                  * those endpoints a fifo_size which is enough for 3 full
 219                  * packets
 220                  */
 221                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 222                 tmp += mdwidth;
 223
 224                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 225
 226                 fifo_size |= (last_fifo_depth << 16);
 227
 228                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 229                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 230
 231                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 232                                 fifo_size);
 233
 234                 last_fifo_depth += (fifo_size & 0xffff);
 235         }
 236
 237         return 0;
 238 }
 239
 240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 241                 int status)
 242 {
 243         struct dwc3                     *dwc = dep->dwc;
 244         int                             i;
 245
 246         if (req->queued) {
 247                 i = 0;
 248                 do {
 249                         dep->busy_slot++;
 250                         /*
 251                          * Skip LINK TRB. We can't use req->trb and check for
 252                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 253                          * just completed (not the LINK TRB).
 254                          */
 255                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 256                                 DWC3_TRB_NUM- 1) &&
 257                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 258                                 dep->busy_slot++;
 259                 } while(++i < req->request.num_mapped_sgs);
 260                 req->queued = false;
 261         }
 262         list_del(&req->list);
 263         req->trb = NULL;
 264
 265         if (req->request.status == -EINPROGRESS)
 266                 req->request.status = status;
 267
 268         if (dwc->ep0_bounced && dep->number == 0)
 269                 dwc->ep0_bounced = false;
 270         else
 271                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 272                                 req->direction);
 273
 274         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 275                         req, dep->name, req->request.actual,
 276                         req->request.length, status);
 277
 278         spin_unlock(&dwc->lock);
 279         req->request.complete(&dep->endpoint, &req->request);
 280         spin_lock(&dwc->lock);
 281 }
 282
 283 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 284 {
 285         switch (cmd) {
 286         case DWC3_DEPCMD_DEPSTARTCFG:
 287                 return "Start New Configuration";
 288         case DWC3_DEPCMD_ENDTRANSFER:
 289                 return "End Transfer";
 290         case DWC3_DEPCMD_UPDATETRANSFER:
 291                 return "Update Transfer";
 292         case DWC3_DEPCMD_STARTTRANSFER:
 293                 return "Start Transfer";
 294         case DWC3_DEPCMD_CLEARSTALL:
 295                 return "Clear Stall";
 296         case DWC3_DEPCMD_SETSTALL:
 297                 return "Set Stall";
 298         case DWC3_DEPCMD_GETEPSTATE:
 299                 return "Get Endpoint State";
 300         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 301                 return "Set Endpoint Transfer Resource";
 302         case DWC3_DEPCMD_SETEPCONFIG:
 303                 return "Set Endpoint Configuration";
 304         default:
 305                 return "UNKNOWN command";
 306         }
 307 }
 308
 309 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 310 {
 311         u32             timeout = 500;
 312         u32             reg;
 313
 314         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 315         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 316
 317         do {
 318                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 319                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 320                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 321                                         DWC3_DGCMD_STATUS(reg));
 322                         return 0;
 323                 }
 324
 325                 /*
 326                  * We can't sleep here, because it's also called from
 327                  * interrupt context.
 328                  */
 329                 timeout--;
 330                 if (!timeout)
 331                         return -ETIMEDOUT;
 332                 udelay(1);
 333         } while (1);
 334 }
 335
 336 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 337                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 338 {
 339         struct dwc3_ep          *dep = dwc->eps[ep];
 340         u32                     timeout = 500;
 341         u32                     reg;
 342
 343         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 344                         dep->name,
 345                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 346                         params->param1, params->param2);
 347
 348         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 349         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 350         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 351
 352         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 353         do {
 354                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 355                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 356                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 357                                         DWC3_DEPCMD_STATUS(reg));
 358                         return 0;
 359                 }
 360
 361                 /*
 362                  * We can't sleep here, because it is also called from
 363                  * interrupt context.
 364                  */
 365                 timeout--;
 366                 if (!timeout)
 367                         return -ETIMEDOUT;
 368
 369                 udelay(1);
 370         } while (1);
 371 }
 372
 373 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 374                 struct dwc3_trb *trb)
 375 {
 376         u32             offset = (char *) trb - (char *) dep->trb_pool;
 377
 378         return dep->trb_pool_dma + offset;
 379 }
 380
 381 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 382 {
 383         struct dwc3             *dwc = dep->dwc;
 384
 385         if (dep->trb_pool)
 386                 return 0;
 387
 388         if (dep->number == 0 || dep->number == 1)
 389                 return 0;
 390
 391         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 392                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 393                         &dep->trb_pool_dma, GFP_KERNEL);
 394         if (!dep->trb_pool) {
 395                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 396                                 dep->name);
 397                 return -ENOMEM;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 404 {
 405         struct dwc3             *dwc = dep->dwc;
 406
 407         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 408                         dep->trb_pool, dep->trb_pool_dma);
 409
 410         dep->trb_pool = NULL;
 411         dep->trb_pool_dma = 0;
 412 }
 413
 414 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 415 {
 416         struct dwc3_gadget_ep_cmd_params params;
 417         u32                     cmd;
 418
 419         memset(&params, 0x00, sizeof(params));
 420
 421         if (dep->number != 1) {
 422                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 423                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 424                 if (dep->number > 1) {
 425                         if (dwc->start_config_issued)
 426                                 return 0;
 427                         dwc->start_config_issued = true;
 428                         cmd |= DWC3_DEPCMD_PARAM(2);
 429                 }
 430
 431                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 438                 const struct usb_endpoint_descriptor *desc,
 439                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 440                 bool ignore)
 441 {
 442         struct dwc3_gadget_ep_cmd_params params;
 443
 444         memset(&params, 0x00, sizeof(params));
 445
 446         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 447                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 448
 449         /* Burst size is only needed in SuperSpeed mode */
 450         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 451                 u32 burst = dep->endpoint.maxburst - 1;
 452
 453                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 454         }
 455
 456         if (ignore)
 457                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 458
 459         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 460                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 461
 462         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 463                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 464                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 465                 dep->stream_capable = true;
 466         }
 467
 468         if (usb_endpoint_xfer_isoc(desc))
 469                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 470
 471         /*
 472          * We are doing 1:1 mapping for endpoints, meaning
 473          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 474          * so on. We consider the direction bit as part of the physical
 475          * endpoint number. So USB endpoint 0x81 is 0x03.
 476          */
 477         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 478
 479         /*
 480          * We must use the lower 16 TX FIFOs even though
 481          * HW might have more
 482          */
 483         if (dep->direction)
 484                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 485
 486         if (desc->bInterval) {
 487                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 488                 dep->interval = 1 << (desc->bInterval - 1);
 489         }
 490
 491         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 492                         DWC3_DEPCMD_SETEPCONFIG, &params);
 493 }
 494
 495 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 496 {
 497         struct dwc3_gadget_ep_cmd_params params;
 498
 499         memset(&params, 0x00, sizeof(params));
 500
 501         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 502
 503         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 504                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 505 }
 506
 507 /**
 508  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 509  * @dep: endpoint to be initialized
 510  * @desc: USB Endpoint Descriptor
 511  *
 512  * Caller should take care of locking
 513  */
 514 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 515                 const struct usb_endpoint_descriptor *desc,
 516                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 517                 bool ignore)
 518 {
 519         struct dwc3             *dwc = dep->dwc;
 520         u32                     reg;
 521         int                     ret = -ENOMEM;
 522
 523         if (!(dep->flags & DWC3_EP_ENABLED)) {
 524                 ret = dwc3_gadget_start_config(dwc, dep);
 525                 if (ret)
 526                         return ret;
 527         }
 528
 529         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
 530         if (ret)
 531                 return ret;
 532
 533         if (!(dep->flags & DWC3_EP_ENABLED)) {
 534                 struct dwc3_trb *trb_st_hw;
 535                 struct dwc3_trb *trb_link;
 536
 537                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 538                 if (ret)
 539                         return ret;
 540
 541                 dep->endpoint.desc = desc;
 542                 dep->comp_desc = comp_desc;
 543                 dep->type = usb_endpoint_type(desc);
 544                 dep->flags |= DWC3_EP_ENABLED;
 545
 546                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 547                 reg |= DWC3_DALEPENA_EP(dep->number);
 548                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 549
 550                 if (!usb_endpoint_xfer_isoc(desc))
 551                         return 0;
 552
 553                 memset(&trb_link, 0, sizeof(trb_link));
 554
 555                 /* Link TRB for ISOC. The HWO bit is never reset */
 556                 trb_st_hw = &dep->trb_pool[0];
 557
 558                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 559
 560                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 561                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 562                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 563                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 564         }
 565
 566         return 0;
 567 }
 568
 569 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 570 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 571 {
 572         struct dwc3_request             *req;
 573
 574         if (!list_empty(&dep->req_queued)) {
 575                 dwc3_stop_active_transfer(dwc, dep->number);
 576
 577                 /* - giveback all requests to gadget driver */
 578                 while (!list_empty(&dep->req_queued)) {
 579                         req = next_request(&dep->req_queued);
 580
 581                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 582                 }
 583         }
 584
 585         while (!list_empty(&dep->request_list)) {
 586                 req = next_request(&dep->request_list);
 587
 588                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 589         }
 590 }
 591
 592 /**
 593  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 594  * @dep: the endpoint to disable
 595  *
 596  * This function also removes requests which are currently processed ny the
 597  * hardware and those which are not yet scheduled.
 598  * Caller should take care of locking.
 599  */
 600 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 601 {
 602         struct dwc3             *dwc = dep->dwc;
 603         u32                     reg;
 604
 605         dwc3_remove_requests(dwc, dep);
 606
 607         /* make sure HW endpoint isn't stalled */
 608         if (dep->flags & DWC3_EP_STALL)
 609                 __dwc3_gadget_ep_set_halt(dep, 0);
 610
 611         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 612         reg &= ~DWC3_DALEPENA_EP(dep->number);
 613         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 614
 615         dep->stream_capable = false;
 616         dep->endpoint.desc = NULL;
 617         dep->comp_desc = NULL;
 618         dep->type = 0;
 619         dep->flags = 0;
 620
 621         return 0;
 622 }
 623
 624 /* -------------------------------------------------------------------------- */
 625
 626 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 627                 const struct usb_endpoint_descriptor *desc)
 628 {
 629         return -EINVAL;
 630 }
 631
 632 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 633 {
 634         return -EINVAL;
 635 }
 636
 637 /* -------------------------------------------------------------------------- */
 638
 639 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 640                 const struct usb_endpoint_descriptor *desc)
 641 {
 642         struct dwc3_ep                  *dep;
 643         struct dwc3                     *dwc;
 644         unsigned long                   flags;
 645         int                             ret;
 646
 647         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 648                 pr_debug("dwc3: invalid parameters\n");
 649                 return -EINVAL;
 650         }
 651
 652         if (!desc->wMaxPacketSize) {
 653                 pr_debug("dwc3: missing wMaxPacketSize\n");
 654                 return -EINVAL;
 655         }
 656
 657         dep = to_dwc3_ep(ep);
 658         dwc = dep->dwc;
 659
 660         if (dep->flags & DWC3_EP_ENABLED) {
 661                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 662                                 dep->name);
 663                 return 0;
 664         }
 665
 666         switch (usb_endpoint_type(desc)) {
 667         case USB_ENDPOINT_XFER_CONTROL:
 668                 strlcat(dep->name, "-control", sizeof(dep->name));
 669                 break;
 670         case USB_ENDPOINT_XFER_ISOC:
 671                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 672                 break;
 673         case USB_ENDPOINT_XFER_BULK:
 674                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 675                 break;
 676         case USB_ENDPOINT_XFER_INT:
 677                 strlcat(dep->name, "-int", sizeof(dep->name));
 678                 break;
 679         default:
 680                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 681         }
 682
 683         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 684
 685         spin_lock_irqsave(&dwc->lock, flags);
 686         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
 687         spin_unlock_irqrestore(&dwc->lock, flags);
 688
 689         return ret;
 690 }
 691
 692 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 693 {
 694         struct dwc3_ep                  *dep;
 695         struct dwc3                     *dwc;
 696         unsigned long                   flags;
 697         int                             ret;
 698
 699         if (!ep) {
 700                 pr_debug("dwc3: invalid parameters\n");
 701                 return -EINVAL;
 702         }
 703
 704         dep = to_dwc3_ep(ep);
 705         dwc = dep->dwc;
 706
 707         if (!(dep->flags & DWC3_EP_ENABLED)) {
 708                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 709                                 dep->name);
 710                 return 0;
 711         }
 712
 713         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 714                         dep->number >> 1,
 715                         (dep->number & 1) ? "in" : "out");
 716
 717         spin_lock_irqsave(&dwc->lock, flags);
 718         ret = __dwc3_gadget_ep_disable(dep);
 719         spin_unlock_irqrestore(&dwc->lock, flags);
 720
 721         return ret;
 722 }
 723
 724 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 725         gfp_t gfp_flags)
 726 {
 727         struct dwc3_request             *req;
 728         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 729         struct dwc3                     *dwc = dep->dwc;
 730
 731         req = kzalloc(sizeof(*req), gfp_flags);
 732         if (!req) {
 733                 dev_err(dwc->dev, "not enough memory\n");
 734                 return NULL;
 735         }
 736
 737         req->epnum      = dep->number;
 738         req->dep        = dep;
 739
 740         return &req->request;
 741 }
 742
 743 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 744                 struct usb_request *request)
 745 {
 746         struct dwc3_request             *req = to_dwc3_request(request);
 747
 748         kfree(req);
 749 }
 750
 751 /**
 752  * dwc3_prepare_one_trb - setup one TRB from one request
 753  * @dep: endpoint for which this request is prepared
 754  * @req: dwc3_request pointer
 755  */
 756 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 757                 struct dwc3_request *req, dma_addr_t dma,
 758                 unsigned length, unsigned last, unsigned chain, unsigned node)
 759 {
 760         struct dwc3             *dwc = dep->dwc;
 761         struct dwc3_trb         *trb;
 762
 763         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 764                         dep->name, req, (unsigned long long) dma,
 765                         length, last ? " last" : "",
 766                         chain ? " chain" : "");
 767
 768         /* Skip the LINK-TRB on ISOC */
 769         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 770                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 771                 dep->free_slot++;
 772
 773         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 774
 775         if (!req->trb) {
 776                 dwc3_gadget_move_request_queued(req);
 777                 req->trb = trb;
 778                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 779                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 780         }
 781
 782         dep->free_slot++;
 783
 784         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 785         trb->bpl = lower_32_bits(dma);
 786         trb->bph = upper_32_bits(dma);
 787
 788         switch (usb_endpoint_type(dep->endpoint.desc)) {
 789         case USB_ENDPOINT_XFER_CONTROL:
 790                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 791                 break;
 792
 793         case USB_ENDPOINT_XFER_ISOC:
 794                 if (!node)
 795                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 796                 else
 797                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 798
 799                 if (!req->request.no_interrupt && !chain)
 800                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 801                 break;
 802
 803         case USB_ENDPOINT_XFER_BULK:
 804         case USB_ENDPOINT_XFER_INT:
 805                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 806                 break;
 807         default:
 808                 /*
 809                  * This is only possible with faulty memory because we
 810                  * checked it already :)
 811                  */
 812                 BUG();
 813         }
 814
 815         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 816                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 817                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 818         } else if (last) {
 819                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 820         }
 821
 822         if (chain)
 823                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 824
 825         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 826                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 827
 828         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 829 }
 830
 831 /*
 832  * dwc3_prepare_trbs - setup TRBs from requests
 833  * @dep: endpoint for which requests are being prepared
 834  * @starting: true if the endpoint is idle and no requests are queued.
 835  *
 836  * The function goes through the requests list and sets up TRBs for the
 837  * transfers. The function returns once there are no more TRBs available or
 838  * it runs out of requests.
 839  */
 840 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 841 {
 842         struct dwc3_request     *req, *n;
 843         u32                     trbs_left;
 844         u32                     max;
 845         unsigned int            last_one = 0;
 846
 847         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 848
 849         /* the first request must not be queued */
 850         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 851
 852         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 853         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 854                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 855                 if (trbs_left > max)
 856                         trbs_left = max;
 857         }
 858
 859         /*
 860          * If busy & slot are equal than it is either full or empty. If we are
 861          * starting to process requests then we are empty. Otherwise we are
 862          * full and don't do anything
 863          */
 864         if (!trbs_left) {
 865                 if (!starting)
 866                         return;
 867                 trbs_left = DWC3_TRB_NUM;
 868                 /*
 869                  * In case we start from scratch, we queue the ISOC requests
 870                  * starting from slot 1. This is done because we use ring
 871                  * buffer and have no LST bit to stop us. Instead, we place
 872                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 873                  * after the first request so we start at slot 1 and have
 874                  * 7 requests proceed before we hit the first IOC.
 875                  * Other transfer types don't use the ring buffer and are
 876                  * processed from the first TRB until the last one. Since we
 877                  * don't wrap around we have to start at the beginning.
 878                  */
 879                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 880                         dep->busy_slot = 1;
 881                         dep->free_slot = 1;
 882                 } else {
 883                         dep->busy_slot = 0;
 884                         dep->free_slot = 0;
 885                 }
 886         }
 887
 888         /* The last TRB is a link TRB, not used for xfer */
 889         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 890                 return;
 891
 892         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 893                 unsigned        length;
 894                 dma_addr_t      dma;
 895                 last_one = false;
 896
 897                 if (req->request.num_mapped_sgs > 0) {
 898                         struct usb_request *request = &req->request;
 899                         struct scatterlist *sg = request->sg;
 900                         struct scatterlist *s;
 901                         int             i;
 902
 903                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 904                                 unsigned chain = true;
 905
 906                                 length = sg_dma_len(s);
 907                                 dma = sg_dma_address(s);
 908
 909                                 if (i == (request->num_mapped_sgs - 1) ||
 910                                                 sg_is_last(s)) {
 911                                         if (list_is_last(&req->list,
 912                                                         &dep->request_list))
 913                                                 last_one = true;
 914                                         chain = false;
 915                                 }
 916
 917                                 trbs_left--;
 918                                 if (!trbs_left)
 919                                         last_one = true;
 920
 921                                 if (last_one)
 922                                         chain = false;
 923
 924                                 dwc3_prepare_one_trb(dep, req, dma, length,
 925                                                 last_one, chain, i);
 926
 927                                 if (last_one)
 928                                         break;
 929                         }
 930                 } else {
 931                         dma = req->request.dma;
 932                         length = req->request.length;
 933                         trbs_left--;
 934
 935                         if (!trbs_left)
 936                                 last_one = 1;
 937
 938                         /* Is this the last request? */
 939                         if (list_is_last(&req->list, &dep->request_list))
 940                                 last_one = 1;
 941
 942                         dwc3_prepare_one_trb(dep, req, dma, length,
 943                                         last_one, false, 0);
 944
 945                         if (last_one)
 946                                 break;
 947                 }
 948         }
 949 }
 950
 951 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 952                 int start_new)
 953 {
 954         struct dwc3_gadget_ep_cmd_params params;
 955         struct dwc3_request             *req;
 956         struct dwc3                     *dwc = dep->dwc;
 957         int                             ret;
 958         u32                             cmd;
 959
 960         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 961                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 962                 return -EBUSY;
 963         }
 964         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 965
 966         /*
 967          * If we are getting here after a short-out-packet we don't enqueue any
 968          * new requests as we try to set the IOC bit only on the last request.
 969          */
 970         if (start_new) {
 971                 if (list_empty(&dep->req_queued))
 972                         dwc3_prepare_trbs(dep, start_new);
 973
 974                 /* req points to the first request which will be sent */
 975                 req = next_request(&dep->req_queued);
 976         } else {
 977                 dwc3_prepare_trbs(dep, start_new);
 978
 979                 /*
 980                  * req points to the first request where HWO changed from 0 to 1
 981                  */
 982                 req = next_request(&dep->req_queued);
 983         }
 984         if (!req) {
 985                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 986                 return 0;
 987         }
 988
 989         memset(&params, 0, sizeof(params));
 990
 991         if (start_new) {
 992                 params.param0 = upper_32_bits(req->trb_dma);
 993                 params.param1 = lower_32_bits(req->trb_dma);
 994                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 995         } else {
 996                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 997         }
 998
 999         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1000         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1001         if (ret < 0) {
1002                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1003
1004                 /*
1005                  * FIXME we need to iterate over the list of requests
1006                  * here and stop, unmap, free and del each of the linked
1007                  * requests instead of what we do now.
1008                  */
1009                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1010                                 req->direction);
1011                 list_del(&req->list);
1012                 return ret;
1013         }
1014
1015         dep->flags |= DWC3_EP_BUSY;
1016
1017         if (start_new) {
1018                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1019                                 dep->number);
1020                 WARN_ON_ONCE(!dep->resource_index);
1021         }
1022
1023         return 0;
1024 }
1025
1026 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1027                 struct dwc3_ep *dep, u32 cur_uf)
1028 {
1029         u32 uf;
1030
1031         if (list_empty(&dep->request_list)) {
1032                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1033                         dep->name);
1034                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1035                 return;
1036         }
1037
1038         /* 4 micro frames in the future */
1039         uf = cur_uf + dep->interval * 4;
1040
1041         __dwc3_gadget_kick_transfer(dep, uf, 1);
1042 }
1043
1044 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1045                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1046 {
1047         u32 cur_uf, mask;
1048
1049         mask = ~(dep->interval - 1);
1050         cur_uf = event->parameters & mask;
1051
1052         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1053 }
1054
1055 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1056 {
1057         struct dwc3             *dwc = dep->dwc;
1058         int                     ret;
1059
1060         req->request.actual     = 0;
1061         req->request.status     = -EINPROGRESS;
1062         req->direction          = dep->direction;
1063         req->epnum              = dep->number;
1064
1065         /*
1066          * We only add to our list of requests now and
1067          * start consuming the list once we get XferNotReady
1068          * IRQ.
1069          *
1070          * That way, we avoid doing anything that we don't need
1071          * to do now and defer it until the point we receive a
1072          * particular token from the Host side.
1073          *
1074          * This will also avoid Host cancelling URBs due to too
1075          * many NAKs.
1076          */
1077         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1078                         dep->direction);
1079         if (ret)
1080                 return ret;
1081
1082         list_add_tail(&req->list, &dep->request_list);
1083
1084         /*
1085          * There are a few special cases:
1086          *
1087          * 1. XferNotReady with empty list of requests. We need to kick the
1088          *    transfer here in that situation, otherwise we will be NAKing
1089          *    forever. If we get XferNotReady before gadget driver has a
1090          *    chance to queue a request, we will ACK the IRQ but won't be
1091          *    able to receive the data until the next request is queued.
1092          *    The following code is handling exactly that.
1093          *
1094          */
1095         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1096                 /*
1097                  * If xfernotready is already elapsed and it is a case
1098                  * of isoc transfer, then issue END TRANSFER, so that
1099                  * you can receive xfernotready again and can have
1100                  * notion of current microframe.
1101                  */
1102                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1103                         if (list_empty(&dep->req_queued)) {
1104                                 dwc3_stop_active_transfer(dwc, dep->number);
1105                                 dep->flags = DWC3_EP_ENABLED;
1106                         }
1107                         return 0;
1108                 }
1109
1110                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1111                 if (ret && ret != -EBUSY)
1112                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1113                                         dep->name);
1114                 return ret;
1115         }
1116
1117         /*
1118          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1119          *    kick the transfer here after queuing a request, otherwise the
1120          *    core may not see the modified TRB(s).
1121          */
1122         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1123                         (dep->flags & DWC3_EP_BUSY) &&
1124                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1125                 WARN_ON_ONCE(!dep->resource_index);
1126                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1127                                 false);
1128                 if (ret && ret != -EBUSY)
1129                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1130                                         dep->name);
1131                 return ret;
1132         }
1133
1134         return 0;
1135 }
1136
1137 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1138         gfp_t gfp_flags)
1139 {
1140         struct dwc3_request             *req = to_dwc3_request(request);
1141         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1142         struct dwc3                     *dwc = dep->dwc;
1143
1144         unsigned long                   flags;
1145
1146         int                             ret;
1147
1148         if (!dep->endpoint.desc) {
1149                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1150                                 request, ep->name);
1151                 return -ESHUTDOWN;
1152         }
1153
1154         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1155                         request, ep->name, request->length);
1156
1157         spin_lock_irqsave(&dwc->lock, flags);
1158         ret = __dwc3_gadget_ep_queue(dep, req);
1159         spin_unlock_irqrestore(&dwc->lock, flags);
1160
1161         return ret;
1162 }
1163
1164 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1165                 struct usb_request *request)
1166 {
1167         struct dwc3_request             *req = to_dwc3_request(request);
1168         struct dwc3_request             *r = NULL;
1169
1170         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1171         struct dwc3                     *dwc = dep->dwc;
1172
1173         unsigned long                   flags;
1174         int                             ret = 0;
1175
1176         spin_lock_irqsave(&dwc->lock, flags);
1177
1178         list_for_each_entry(r, &dep->request_list, list) {
1179                 if (r == req)
1180                         break;
1181         }
1182
1183         if (r != req) {
1184                 list_for_each_entry(r, &dep->req_queued, list) {
1185                         if (r == req)
1186                                 break;
1187                 }
1188                 if (r == req) {
1189                         /* wait until it is processed */
1190                         dwc3_stop_active_transfer(dwc, dep->number);
1191                         goto out1;
1192                 }
1193                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1194                                 request, ep->name);
1195                 ret = -EINVAL;
1196                 goto out0;
1197         }
1198
1199 out1:
1200         /* giveback the request */
1201         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1202
1203 out0:
1204         spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206         return ret;
1207 }
1208
1209 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1210 {
1211         struct dwc3_gadget_ep_cmd_params        params;
1212         struct dwc3                             *dwc = dep->dwc;
1213         int                                     ret;
1214
1215         memset(&params, 0x00, sizeof(params));
1216
1217         if (value) {
1218                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1219                         DWC3_DEPCMD_SETSTALL, &params);
1220                 if (ret)
1221                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1222                                         value ? "set" : "clear",
1223                                         dep->name);
1224                 else
1225                         dep->flags |= DWC3_EP_STALL;
1226         } else {
1227                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1228                         DWC3_DEPCMD_CLEARSTALL, &params);
1229                 if (ret)
1230                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1231                                         value ? "set" : "clear",
1232                                         dep->name);
1233                 else
1234                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1235         }
1236
1237         return ret;
1238 }
1239
1240 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1241 {
1242         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1243         struct dwc3                     *dwc = dep->dwc;
1244
1245         unsigned long                   flags;
1246
1247         int                             ret;
1248
1249         spin_lock_irqsave(&dwc->lock, flags);
1250
1251         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1252                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1253                 ret = -EINVAL;
1254                 goto out;
1255         }
1256
1257         ret = __dwc3_gadget_ep_set_halt(dep, value);
1258 out:
1259         spin_unlock_irqrestore(&dwc->lock, flags);
1260
1261         return ret;
1262 }
1263
1264 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1265 {
1266         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1267         struct dwc3                     *dwc = dep->dwc;
1268         unsigned long                   flags;
1269
1270         spin_lock_irqsave(&dwc->lock, flags);
1271         dep->flags |= DWC3_EP_WEDGE;
1272         spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274         if (dep->number == 0 || dep->number == 1)
1275                 return dwc3_gadget_ep0_set_halt(ep, 1);
1276         else
1277                 return dwc3_gadget_ep_set_halt(ep, 1);
1278 }
1279
1280 /* -------------------------------------------------------------------------- */
1281
1282 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1283         .bLength        = USB_DT_ENDPOINT_SIZE,
1284         .bDescriptorType = USB_DT_ENDPOINT,
1285         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1286 };
1287
1288 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1289         .enable         = dwc3_gadget_ep0_enable,
1290         .disable        = dwc3_gadget_ep0_disable,
1291         .alloc_request  = dwc3_gadget_ep_alloc_request,
1292         .free_request   = dwc3_gadget_ep_free_request,
1293         .queue          = dwc3_gadget_ep0_queue,
1294         .dequeue        = dwc3_gadget_ep_dequeue,
1295         .set_halt       = dwc3_gadget_ep0_set_halt,
1296         .set_wedge      = dwc3_gadget_ep_set_wedge,
1297 };
1298
1299 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1300         .enable         = dwc3_gadget_ep_enable,
1301         .disable        = dwc3_gadget_ep_disable,
1302         .alloc_request  = dwc3_gadget_ep_alloc_request,
1303         .free_request   = dwc3_gadget_ep_free_request,
1304         .queue          = dwc3_gadget_ep_queue,
1305         .dequeue        = dwc3_gadget_ep_dequeue,
1306         .set_halt       = dwc3_gadget_ep_set_halt,
1307         .set_wedge      = dwc3_gadget_ep_set_wedge,
1308 };
1309
1310 /* -------------------------------------------------------------------------- */
1311
1312 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1313 {
1314         struct dwc3             *dwc = gadget_to_dwc(g);
1315         u32                     reg;
1316
1317         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1318         return DWC3_DSTS_SOFFN(reg);
1319 }
1320
1321 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1322 {
1323         struct dwc3             *dwc = gadget_to_dwc(g);
1324
1325         unsigned long           timeout;
1326         unsigned long           flags;
1327
1328         u32                     reg;
1329
1330         int                     ret = 0;
1331
1332         u8                      link_state;
1333         u8                      speed;
1334
1335         spin_lock_irqsave(&dwc->lock, flags);
1336
1337         /*
1338          * According to the Databook Remote wakeup request should
1339          * be issued only when the device is in early suspend state.
1340          *
1341          * We can check that via USB Link State bits in DSTS register.
1342          */
1343         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1344
1345         speed = reg & DWC3_DSTS_CONNECTSPD;
1346         if (speed == DWC3_DSTS_SUPERSPEED) {
1347                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1348                 ret = -EINVAL;
1349                 goto out;
1350         }
1351
1352         link_state = DWC3_DSTS_USBLNKST(reg);
1353
1354         switch (link_state) {
1355         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1356         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1357                 break;
1358         default:
1359                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1360                                 link_state);
1361                 ret = -EINVAL;
1362                 goto out;
1363         }
1364
1365         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1366         if (ret < 0) {
1367                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1368                 goto out;
1369         }
1370
1371         /* Recent versions do this automatically */
1372         if (dwc->revision < DWC3_REVISION_194A) {
1373                 /* write zeroes to Link Change Request */
1374                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1375                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1376                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1377         }
1378
1379         /* poll until Link State changes to ON */
1380         timeout = jiffies + msecs_to_jiffies(100);
1381
1382         while (!time_after(jiffies, timeout)) {
1383                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1384
1385                 /* in HS, means ON */
1386                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1387                         break;
1388         }
1389
1390         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1391                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1392                 ret = -EINVAL;
1393         }
1394
1395 out:
1396         spin_unlock_irqrestore(&dwc->lock, flags);
1397
1398         return ret;
1399 }
1400
1401 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1402                 int is_selfpowered)
1403 {
1404         struct dwc3             *dwc = gadget_to_dwc(g);
1405         unsigned long           flags;
1406
1407         spin_lock_irqsave(&dwc->lock, flags);
1408         dwc->is_selfpowered = !!is_selfpowered;
1409         spin_unlock_irqrestore(&dwc->lock, flags);
1410
1411         return 0;
1412 }
1413
1414 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1415 {
1416         u32                     reg;
1417         u32                     timeout = 500;
1418
1419         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1420         if (is_on) {
1421                 if (dwc->revision <= DWC3_REVISION_187A) {
1422                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1423                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1424                 }
1425
1426                 if (dwc->revision >= DWC3_REVISION_194A)
1427                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1428                 reg |= DWC3_DCTL_RUN_STOP;
1429                 dwc->pullups_connected = true;
1430         } else {
1431                 reg &= ~DWC3_DCTL_RUN_STOP;
1432                 dwc->pullups_connected = false;
1433         }
1434
1435         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1436
1437         do {
1438                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1439                 if (is_on) {
1440                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1441                                 break;
1442                 } else {
1443                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1444                                 break;
1445                 }
1446                 timeout--;
1447                 if (!timeout)
1448                         return -ETIMEDOUT;
1449                 udelay(1);
1450         } while (1);
1451
1452         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1453                         dwc->gadget_driver
1454                         ? dwc->gadget_driver->function : "no-function",
1455                         is_on ? "connect" : "disconnect");
1456
1457         return 0;
1458 }
1459
1460 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1461 {
1462         struct dwc3             *dwc = gadget_to_dwc(g);
1463         unsigned long           flags;
1464         int                     ret;
1465
1466         is_on = !!is_on;
1467
1468         spin_lock_irqsave(&dwc->lock, flags);
1469         ret = dwc3_gadget_run_stop(dwc, is_on);
1470         spin_unlock_irqrestore(&dwc->lock, flags);
1471
1472         return ret;
1473 }
1474
1475 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1476 {
1477         u32                     reg;
1478
1479         /* Enable all but Start and End of Frame IRQs */
1480         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1481                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1482                         DWC3_DEVTEN_CMDCMPLTEN |
1483                         DWC3_DEVTEN_ERRTICERREN |
1484                         DWC3_DEVTEN_WKUPEVTEN |
1485                         DWC3_DEVTEN_ULSTCNGEN |
1486                         DWC3_DEVTEN_CONNECTDONEEN |
1487                         DWC3_DEVTEN_USBRSTEN |
1488                         DWC3_DEVTEN_DISCONNEVTEN);
1489
1490         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1491 }
1492
1493 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1494 {
1495         /* mask all interrupts */
1496         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1497 }
1498
1499 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1500 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1501
1502 static int dwc3_gadget_start(struct usb_gadget *g,
1503                 struct usb_gadget_driver *driver)
1504 {
1505         struct dwc3             *dwc = gadget_to_dwc(g);
1506         struct dwc3_ep          *dep;
1507         unsigned long           flags;
1508         int                     ret = 0;
1509         int                     irq;
1510         u32                     reg;
1511
1512         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1513         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1514                         IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);
1515         if (ret) {
1516                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1517                                 irq, ret);
1518                 goto err0;
1519         }
1520
1521         spin_lock_irqsave(&dwc->lock, flags);
1522
1523         if (dwc->gadget_driver) {
1524                 dev_err(dwc->dev, "%s is already bound to %s\n",
1525                                 dwc->gadget.name,
1526                                 dwc->gadget_driver->driver.name);
1527                 ret = -EBUSY;
1528                 goto err1;
1529         }
1530
1531         dwc->gadget_driver      = driver;
1532
1533         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1534         reg &= ~(DWC3_DCFG_SPEED_MASK);
1535
1536         /**
1537          * WORKAROUND: DWC3 revision < 2.20a have an issue
1538          * which would cause metastability state on Run/Stop
1539          * bit if we try to force the IP to USB2-only mode.
1540          *
1541          * Because of that, we cannot configure the IP to any
1542          * speed other than the SuperSpeed
1543          *
1544          * Refers to:
1545          *
1546          * STAR#9000525659: Clock Domain Crossing on DCTL in
1547          * USB 2.0 Mode
1548          */
1549         if (dwc->revision < DWC3_REVISION_220A)
1550                 reg |= DWC3_DCFG_SUPERSPEED;
1551         else
1552                 reg |= dwc->maximum_speed;
1553         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1554
1555         dwc->start_config_issued = false;
1556
1557         /* Start with SuperSpeed Default */
1558         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1559
1560         dep = dwc->eps[0];
1561         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1562         if (ret) {
1563                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1564                 goto err2;
1565         }
1566
1567         dep = dwc->eps[1];
1568         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1569         if (ret) {
1570                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1571                 goto err3;
1572         }
1573
1574         /* begin to receive SETUP packets */
1575         dwc->ep0state = EP0_SETUP_PHASE;
1576         dwc3_ep0_out_start(dwc);
1577
1578         dwc3_gadget_enable_irq(dwc);
1579
1580         spin_unlock_irqrestore(&dwc->lock, flags);
1581
1582         return 0;
1583
1584 err3:
1585         __dwc3_gadget_ep_disable(dwc->eps[0]);
1586
1587 err2:
1588         dwc->gadget_driver = NULL;
1589
1590 err1:
1591         spin_unlock_irqrestore(&dwc->lock, flags);
1592
1593         free_irq(irq, dwc);
1594
1595 err0:
1596         return ret;
1597 }
1598
1599 static int dwc3_gadget_stop(struct usb_gadget *g,
1600                 struct usb_gadget_driver *driver)
1601 {
1602         struct dwc3             *dwc = gadget_to_dwc(g);
1603         unsigned long           flags;
1604         int                     irq;
1605
1606         spin_lock_irqsave(&dwc->lock, flags);
1607
1608         dwc3_gadget_disable_irq(dwc);
1609         __dwc3_gadget_ep_disable(dwc->eps[0]);
1610         __dwc3_gadget_ep_disable(dwc->eps[1]);
1611
1612         dwc->gadget_driver      = NULL;
1613
1614         spin_unlock_irqrestore(&dwc->lock, flags);
1615
1616         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1617         free_irq(irq, dwc);
1618
1619         return 0;
1620 }
1621
1622 static const struct usb_gadget_ops dwc3_gadget_ops = {
1623         .get_frame              = dwc3_gadget_get_frame,
1624         .wakeup                 = dwc3_gadget_wakeup,
1625         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1626         .pullup                 = dwc3_gadget_pullup,
1627         .udc_start              = dwc3_gadget_start,
1628         .udc_stop               = dwc3_gadget_stop,
1629 };
1630
1631 /* -------------------------------------------------------------------------- */
1632
1633 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1634                 u8 num, u32 direction)
1635 {
1636         struct dwc3_ep                  *dep;
1637         u8                              i;
1638
1639         for (i = 0; i < num; i++) {
1640                 u8 epnum = (i << 1) | (!!direction);
1641
1642                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1643                 if (!dep) {
1644                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1645                                         epnum);
1646                         return -ENOMEM;
1647                 }
1648
1649                 dep->dwc = dwc;
1650                 dep->number = epnum;
1651                 dwc->eps[epnum] = dep;
1652
1653                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1654                                 (epnum & 1) ? "in" : "out");
1655
1656                 dep->endpoint.name = dep->name;
1657                 dep->direction = (epnum & 1);
1658
1659                 if (epnum == 0 || epnum == 1) {
1660                         dep->endpoint.maxpacket = 512;
1661                         dep->endpoint.maxburst = 1;
1662                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1663                         if (!epnum)
1664                                 dwc->gadget.ep0 = &dep->endpoint;
1665                 } else {
1666                         int             ret;
1667
1668                         dep->endpoint.maxpacket = 1024;
1669                         dep->endpoint.max_streams = 15;
1670                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1671                         list_add_tail(&dep->endpoint.ep_list,
1672                                         &dwc->gadget.ep_list);
1673
1674                         ret = dwc3_alloc_trb_pool(dep);
1675                         if (ret)
1676                                 return ret;
1677                 }
1678
1679                 INIT_LIST_HEAD(&dep->request_list);
1680                 INIT_LIST_HEAD(&dep->req_queued);
1681         }
1682
1683         return 0;
1684 }
1685
1686 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1687 {
1688         int                             ret;
1689
1690         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1691
1692         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1693         if (ret < 0) {
1694                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1695                 return ret;
1696         }
1697
1698         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1699         if (ret < 0) {
1700                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1701                 return ret;
1702         }
1703
1704         return 0;
1705 }
1706
1707 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1708 {
1709         struct dwc3_ep                  *dep;
1710         u8                              epnum;
1711
1712         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1713                 dep = dwc->eps[epnum];
1714                 if (!dep)
1715                         continue;
1716                 /*
1717                  * Physical endpoints 0 and 1 are special; they form the
1718                  * bi-directional USB endpoint 0.
1719                  *
1720                  * For those two physical endpoints, we don't allocate a TRB
1721                  * pool nor do we add them the endpoints list. Due to that, we
1722                  * shouldn't do these two operations otherwise we would end up
1723                  * with all sorts of bugs when removing dwc3.ko.
1724                  */
1725                 if (epnum != 0 && epnum != 1) {
1726                         dwc3_free_trb_pool(dep);
1727                         list_del(&dep->endpoint.ep_list);
1728                 }
1729
1730                 kfree(dep);
1731         }
1732 }
1733
1734 /* -------------------------------------------------------------------------- */
1735
1736 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1737                 struct dwc3_request *req, struct dwc3_trb *trb,
1738                 const struct dwc3_event_depevt *event, int status)
1739 {
1740         unsigned int            count;
1741         unsigned int            s_pkt = 0;
1742         unsigned int            trb_status;
1743
1744         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1745                 /*
1746                  * We continue despite the error. There is not much we
1747                  * can do. If we don't clean it up we loop forever. If
1748                  * we skip the TRB then it gets overwritten after a
1749                  * while since we use them in a ring buffer. A BUG()
1750                  * would help. Lets hope that if this occurs, someone
1751                  * fixes the root cause instead of looking away :)
1752                  */
1753                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1754                                 dep->name, trb);
1755         count = trb->size & DWC3_TRB_SIZE_MASK;
1756
1757         if (dep->direction) {
1758                 if (count) {
1759                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1760                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1761                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1762                                                 dep->name);
1763                                 /*
1764                                  * If missed isoc occurred and there is
1765                                  * no request queued then issue END
1766                                  * TRANSFER, so that core generates
1767                                  * next xfernotready and we will issue
1768                                  * a fresh START TRANSFER.
1769                                  * If there are still queued request
1770                                  * then wait, do not issue either END
1771                                  * or UPDATE TRANSFER, just attach next
1772                                  * request in request_list during
1773                                  * giveback.If any future queued request
1774                                  * is successfully transferred then we
1775                                  * will issue UPDATE TRANSFER for all
1776                                  * request in the request_list.
1777                                  */
1778                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1779                         } else {
1780                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1781                                                 dep->name);
1782                                 status = -ECONNRESET;
1783                         }
1784                 } else {
1785                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1786                 }
1787         } else {
1788                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1789                         s_pkt = 1;
1790         }
1791
1792         /*
1793          * We assume here we will always receive the entire data block
1794          * which we should receive. Meaning, if we program RX to
1795          * receive 4K but we receive only 2K, we assume that's all we
1796          * should receive and we simply bounce the request back to the
1797          * gadget driver for further processing.
1798          */
1799         req->request.actual += req->request.length - count;
1800         if (s_pkt)
1801                 return 1;
1802         if ((event->status & DEPEVT_STATUS_LST) &&
1803                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1804                                 DWC3_TRB_CTRL_HWO)))
1805                 return 1;
1806         if ((event->status & DEPEVT_STATUS_IOC) &&
1807                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1808                 return 1;
1809         return 0;
1810 }
1811
1812 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1813                 const struct dwc3_event_depevt *event, int status)
1814 {
1815         struct dwc3_request     *req;
1816         struct dwc3_trb         *trb;
1817         unsigned int            slot;
1818         unsigned int            i;
1819         int                     ret;
1820
1821         do {
1822                 req = next_request(&dep->req_queued);
1823                 if (!req) {
1824                         WARN_ON_ONCE(1);
1825                         return 1;
1826                 }
1827                 i = 0;
1828                 do {
1829                         slot = req->start_slot + i;
1830                         if ((slot == DWC3_TRB_NUM - 1) &&
1831                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1832                                 slot++;
1833                         slot %= DWC3_TRB_NUM;
1834                         trb = &dep->trb_pool[slot];
1835
1836                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1837                                         event, status);
1838                         if (ret)
1839                                 break;
1840                 }while (++i < req->request.num_mapped_sgs);
1841
1842                 dwc3_gadget_giveback(dep, req, status);
1843
1844                 if (ret)
1845                         break;
1846         } while (1);
1847
1848         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1849                         list_empty(&dep->req_queued)) {
1850                 if (list_empty(&dep->request_list)) {
1851                         /*
1852                          * If there is no entry in request list then do
1853                          * not issue END TRANSFER now. Just set PENDING
1854                          * flag, so that END TRANSFER is issued when an
1855                          * entry is added into request list.
1856                          */
1857                         dep->flags = DWC3_EP_PENDING_REQUEST;
1858                 } else {
1859                         dwc3_stop_active_transfer(dwc, dep->number);
1860                         dep->flags = DWC3_EP_ENABLED;
1861                 }
1862                 return 1;
1863         }
1864
1865         if ((event->status & DEPEVT_STATUS_IOC) &&
1866                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1867                 return 0;
1868         return 1;
1869 }
1870
1871 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1872                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1873                 int start_new)
1874 {
1875         unsigned                status = 0;
1876         int                     clean_busy;
1877
1878         if (event->status & DEPEVT_STATUS_BUSERR)
1879                 status = -ECONNRESET;
1880
1881         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1882         if (clean_busy)
1883                 dep->flags &= ~DWC3_EP_BUSY;
1884
1885         /*
1886          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1887          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1888          */
1889         if (dwc->revision < DWC3_REVISION_183A) {
1890                 u32             reg;
1891                 int             i;
1892
1893                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1894                         dep = dwc->eps[i];
1895
1896                         if (!(dep->flags & DWC3_EP_ENABLED))
1897                                 continue;
1898
1899                         if (!list_empty(&dep->req_queued))
1900                                 return;
1901                 }
1902
1903                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1904                 reg |= dwc->u1u2;
1905                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1906
1907                 dwc->u1u2 = 0;
1908         }
1909 }
1910
1911 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1912                 const struct dwc3_event_depevt *event)
1913 {
1914         struct dwc3_ep          *dep;
1915         u8                      epnum = event->endpoint_number;
1916
1917         dep = dwc->eps[epnum];
1918
1919         if (!(dep->flags & DWC3_EP_ENABLED))
1920                 return;
1921
1922         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1923                         dwc3_ep_event_string(event->endpoint_event));
1924
1925         if (epnum == 0 || epnum == 1) {
1926                 dwc3_ep0_interrupt(dwc, event);
1927                 return;
1928         }
1929
1930         switch (event->endpoint_event) {
1931         case DWC3_DEPEVT_XFERCOMPLETE:
1932                 dep->resource_index = 0;
1933
1934                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1935                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1936                                         dep->name);
1937                         return;
1938                 }
1939
1940                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1941                 break;
1942         case DWC3_DEPEVT_XFERINPROGRESS:
1943                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1944                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1945                                         dep->name);
1946                         return;
1947                 }
1948
1949                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1950                 break;
1951         case DWC3_DEPEVT_XFERNOTREADY:
1952                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1953                         dwc3_gadget_start_isoc(dwc, dep, event);
1954                 } else {
1955                         int ret;
1956
1957                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1958                                         dep->name, event->status &
1959                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1960                                         ? "Transfer Active"
1961                                         : "Transfer Not Active");
1962
1963                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1964                         if (!ret || ret == -EBUSY)
1965                                 return;
1966
1967                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1968                                         dep->name);
1969                 }
1970
1971                 break;
1972         case DWC3_DEPEVT_STREAMEVT:
1973                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1974                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1975                                         dep->name);
1976                         return;
1977                 }
1978
1979                 switch (event->status) {
1980                 case DEPEVT_STREAMEVT_FOUND:
1981                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1982                                         event->parameters);
1983
1984                         break;
1985                 case DEPEVT_STREAMEVT_NOTFOUND:
1986                         /* FALLTHROUGH */
1987                 default:
1988                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1989                 }
1990                 break;
1991         case DWC3_DEPEVT_RXTXFIFOEVT:
1992                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1993                 break;
1994         case DWC3_DEPEVT_EPCMDCMPLT:
1995                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
1996                 break;
1997         }
1998 }
1999
2000 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2001 {
2002         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2003                 spin_unlock(&dwc->lock);
2004                 dwc->gadget_driver->disconnect(&dwc->gadget);
2005                 spin_lock(&dwc->lock);
2006         }
2007 }
2008
2009 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2010 {
2011         struct dwc3_ep *dep;
2012         struct dwc3_gadget_ep_cmd_params params;
2013         u32 cmd;
2014         int ret;
2015
2016         dep = dwc->eps[epnum];
2017
2018         if (!dep->resource_index)
2019                 return;
2020
2021         /*
2022          * NOTICE: We are violating what the Databook says about the
2023          * EndTransfer command. Ideally we would _always_ wait for the
2024          * EndTransfer Command Completion IRQ, but that's causing too
2025          * much trouble synchronizing between us and gadget driver.
2026          *
2027          * We have discussed this with the IP Provider and it was
2028          * suggested to giveback all requests here, but give HW some
2029          * extra time to synchronize with the interconnect. We're using
2030          * an arbitraty 100us delay for that.
2031          *
2032          * Note also that a similar handling was tested by Synopsys
2033          * (thanks a lot Paul) and nothing bad has come out of it.
2034          * In short, what we're doing is:
2035          *
2036          * - Issue EndTransfer WITH CMDIOC bit set
2037          * - Wait 100us
2038          */
2039
2040         cmd = DWC3_DEPCMD_ENDTRANSFER;
2041         cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2042         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2043         memset(&params, 0, sizeof(params));
2044         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2045         WARN_ON_ONCE(ret);
2046         dep->resource_index = 0;
2047         dep->flags &= ~DWC3_EP_BUSY;
2048         udelay(100);
2049 }
2050
2051 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2052 {
2053         u32 epnum;
2054
2055         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2056                 struct dwc3_ep *dep;
2057
2058                 dep = dwc->eps[epnum];
2059                 if (!dep)
2060                         continue;
2061
2062                 if (!(dep->flags & DWC3_EP_ENABLED))
2063                         continue;
2064
2065                 dwc3_remove_requests(dwc, dep);
2066         }
2067 }
2068
2069 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2070 {
2071         u32 epnum;
2072
2073         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2074                 struct dwc3_ep *dep;
2075                 struct dwc3_gadget_ep_cmd_params params;
2076                 int ret;
2077
2078                 dep = dwc->eps[epnum];
2079                 if (!dep)
2080                         continue;
2081
2082                 if (!(dep->flags & DWC3_EP_STALL))
2083                         continue;
2084
2085                 dep->flags &= ~DWC3_EP_STALL;
2086
2087                 memset(&params, 0, sizeof(params));
2088                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2089                                 DWC3_DEPCMD_CLEARSTALL, &params);
2090                 WARN_ON_ONCE(ret);
2091         }
2092 }
2093
2094 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2095 {
2096         int                     reg;
2097
2098         dev_vdbg(dwc->dev, "%s\n", __func__);
2099
2100         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2101         reg &= ~DWC3_DCTL_INITU1ENA;
2102         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2103
2104         reg &= ~DWC3_DCTL_INITU2ENA;
2105         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2106
2107         dwc3_disconnect_gadget(dwc);
2108         dwc->start_config_issued = false;
2109
2110         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2111         dwc->setup_packet_pending = false;
2112 }
2113
2114 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
2115 {
2116         u32                     reg;
2117
2118         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
2119
2120         if (suspend)
2121                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
2122         else
2123                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
2124
2125         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2126 }
2127
2128 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
2129 {
2130         u32                     reg;
2131
2132         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2133
2134         if (suspend)
2135                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
2136         else
2137                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2138
2139         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2140 }
2141
2142 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2143 {
2144         u32                     reg;
2145
2146         dev_vdbg(dwc->dev, "%s\n", __func__);
2147
2148         /*
2149          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2150          * would cause a missing Disconnect Event if there's a
2151          * pending Setup Packet in the FIFO.
2152          *
2153          * There's no suggested workaround on the official Bug
2154          * report, which states that "unless the driver/application
2155          * is doing any special handling of a disconnect event,
2156          * there is no functional issue".
2157          *
2158          * Unfortunately, it turns out that we _do_ some special
2159          * handling of a disconnect event, namely complete all
2160          * pending transfers, notify gadget driver of the
2161          * disconnection, and so on.
2162          *
2163          * Our suggested workaround is to follow the Disconnect
2164          * Event steps here, instead, based on a setup_packet_pending
2165          * flag. Such flag gets set whenever we have a XferNotReady
2166          * event on EP0 and gets cleared on XferComplete for the
2167          * same endpoint.
2168          *
2169          * Refers to:
2170          *
2171          * STAR#9000466709: RTL: Device : Disconnect event not
2172          * generated if setup packet pending in FIFO
2173          */
2174         if (dwc->revision < DWC3_REVISION_188A) {
2175                 if (dwc->setup_packet_pending)
2176                         dwc3_gadget_disconnect_interrupt(dwc);
2177         }
2178
2179         /* after reset -> Default State */
2180         usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2181
2182         /* Recent versions support automatic phy suspend and don't need this */
2183         if (dwc->revision < DWC3_REVISION_194A) {
2184                 /* Resume PHYs */
2185                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2186                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2187         }
2188
2189         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2190                 dwc3_disconnect_gadget(dwc);
2191
2192         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2193         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2194         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2195         dwc->test_mode = false;
2196
2197         dwc3_stop_active_transfers(dwc);
2198         dwc3_clear_stall_all_ep(dwc);
2199         dwc->start_config_issued = false;
2200
2201         /* Reset device address to zero */
2202         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2203         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2204         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2205 }
2206
2207 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2208 {
2209         u32 reg;
2210         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2211
2212         /*
2213          * We change the clock only at SS but I dunno why I would want to do
2214          * this. Maybe it becomes part of the power saving plan.
2215          */
2216
2217         if (speed != DWC3_DSTS_SUPERSPEED)
2218                 return;
2219
2220         /*
2221          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2222          * each time on Connect Done.
2223          */
2224         if (!usb30_clock)
2225                 return;
2226
2227         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2228         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2229         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2230 }
2231
2232 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2233 {
2234         switch (speed) {
2235         case USB_SPEED_SUPER:
2236                 dwc3_gadget_usb2_phy_suspend(dwc, true);
2237                 break;
2238         case USB_SPEED_HIGH:
2239         case USB_SPEED_FULL:
2240         case USB_SPEED_LOW:
2241                 dwc3_gadget_usb3_phy_suspend(dwc, true);
2242                 break;
2243         }
2244 }
2245
2246 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2247 {
2248         struct dwc3_ep          *dep;
2249         int                     ret;
2250         u32                     reg;
2251         u8                      speed;
2252
2253         dev_vdbg(dwc->dev, "%s\n", __func__);
2254
2255         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2256         speed = reg & DWC3_DSTS_CONNECTSPD;
2257         dwc->speed = speed;
2258
2259         dwc3_update_ram_clk_sel(dwc, speed);
2260
2261         switch (speed) {
2262         case DWC3_DCFG_SUPERSPEED:
2263                 /*
2264                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2265                  * would cause a missing USB3 Reset event.
2266                  *
2267                  * In such situations, we should force a USB3 Reset
2268                  * event by calling our dwc3_gadget_reset_interrupt()
2269                  * routine.
2270                  *
2271                  * Refers to:
2272                  *
2273                  * STAR#9000483510: RTL: SS : USB3 reset event may
2274                  * not be generated always when the link enters poll
2275                  */
2276                 if (dwc->revision < DWC3_REVISION_190A)
2277                         dwc3_gadget_reset_interrupt(dwc);
2278
2279                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2280                 dwc->gadget.ep0->maxpacket = 512;
2281                 dwc->gadget.speed = USB_SPEED_SUPER;
2282                 break;
2283         case DWC3_DCFG_HIGHSPEED:
2284                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2285                 dwc->gadget.ep0->maxpacket = 64;
2286                 dwc->gadget.speed = USB_SPEED_HIGH;
2287                 break;
2288         case DWC3_DCFG_FULLSPEED2:
2289         case DWC3_DCFG_FULLSPEED1:
2290                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2291                 dwc->gadget.ep0->maxpacket = 64;
2292                 dwc->gadget.speed = USB_SPEED_FULL;
2293                 break;
2294         case DWC3_DCFG_LOWSPEED:
2295                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2296                 dwc->gadget.ep0->maxpacket = 8;
2297                 dwc->gadget.speed = USB_SPEED_LOW;
2298                 break;
2299         }
2300
2301         /* Enable USB2 LPM Capability */
2302
2303         if ((dwc->revision > DWC3_REVISION_194A)
2304                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2305                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2306                 reg |= DWC3_DCFG_LPM_CAP;
2307                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2308
2309                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2310                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2311
2312                 /*
2313                  * TODO: This should be configurable. For now using
2314                  * maximum allowed HIRD threshold value of 0b1100
2315                  */
2316                 reg |= DWC3_DCTL_HIRD_THRES(12);
2317
2318                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2319         }
2320
2321         /* Recent versions support automatic phy suspend and don't need this */
2322         if (dwc->revision < DWC3_REVISION_194A) {
2323                 /* Suspend unneeded PHY */
2324                 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2325         }
2326
2327         dep = dwc->eps[0];
2328         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2329         if (ret) {
2330                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2331                 return;
2332         }
2333
2334         dep = dwc->eps[1];
2335         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2336         if (ret) {
2337                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2338                 return;
2339         }
2340
2341         /*
2342          * Configure PHY via GUSB3PIPECTLn if required.
2343          *
2344          * Update GTXFIFOSIZn
2345          *
2346          * In both cases reset values should be sufficient.
2347          */
2348 }
2349
2350 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2351 {
2352         dev_vdbg(dwc->dev, "%s\n", __func__);
2353
2354         /*
2355          * TODO take core out of low power mode when that's
2356          * implemented.
2357          */
2358
2359         dwc->gadget_driver->resume(&dwc->gadget);
2360 }
2361
2362 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2363                 unsigned int evtinfo)
2364 {
2365         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2366         unsigned int            pwropt;
2367
2368         /*
2369          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2370          * Hibernation mode enabled which would show up when device detects
2371          * host-initiated U3 exit.
2372          *
2373          * In that case, device will generate a Link State Change Interrupt
2374          * from U3 to RESUME which is only necessary if Hibernation is
2375          * configured in.
2376          *
2377          * There are no functional changes due to such spurious event and we
2378          * just need to ignore it.
2379          *
2380          * Refers to:
2381          *
2382          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2383          * operational mode
2384          */
2385         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2386         if ((dwc->revision < DWC3_REVISION_250A) &&
2387                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2388                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2389                                 (next == DWC3_LINK_STATE_RESUME)) {
2390                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2391                         return;
2392                 }
2393         }
2394
2395         /*
2396          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2397          * on the link partner, the USB session might do multiple entry/exit
2398          * of low power states before a transfer takes place.
2399          *
2400          * Due to this problem, we might experience lower throughput. The
2401          * suggested workaround is to disable DCTL[12:9] bits if we're
2402          * transitioning from U1/U2 to U0 and enable those bits again
2403          * after a transfer completes and there are no pending transfers
2404          * on any of the enabled endpoints.
2405          *
2406          * This is the first half of that workaround.
2407          *
2408          * Refers to:
2409          *
2410          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2411          * core send LGO_Ux entering U0
2412          */
2413         if (dwc->revision < DWC3_REVISION_183A) {
2414                 if (next == DWC3_LINK_STATE_U0) {
2415                         u32     u1u2;
2416                         u32     reg;
2417
2418                         switch (dwc->link_state) {
2419                         case DWC3_LINK_STATE_U1:
2420                         case DWC3_LINK_STATE_U2:
2421                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2422                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2423                                                 | DWC3_DCTL_ACCEPTU2ENA
2424                                                 | DWC3_DCTL_INITU1ENA
2425                                                 | DWC3_DCTL_ACCEPTU1ENA);
2426
2427                                 if (!dwc->u1u2)
2428                                         dwc->u1u2 = reg & u1u2;
2429
2430                                 reg &= ~u1u2;
2431
2432                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2433                                 break;
2434                         default:
2435                                 /* do nothing */
2436                                 break;
2437                         }
2438                 }
2439         }
2440
2441         dwc->link_state = next;
2442
2443         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2444 }
2445
2446 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2447                 const struct dwc3_event_devt *event)
2448 {
2449         switch (event->type) {
2450         case DWC3_DEVICE_EVENT_DISCONNECT:
2451                 dwc3_gadget_disconnect_interrupt(dwc);
2452                 break;
2453         case DWC3_DEVICE_EVENT_RESET:
2454                 dwc3_gadget_reset_interrupt(dwc);
2455                 break;
2456         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2457                 dwc3_gadget_conndone_interrupt(dwc);
2458                 break;
2459         case DWC3_DEVICE_EVENT_WAKEUP:
2460                 dwc3_gadget_wakeup_interrupt(dwc);
2461                 break;
2462         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2463                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2464                 break;
2465         case DWC3_DEVICE_EVENT_EOPF:
2466                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2467                 break;
2468         case DWC3_DEVICE_EVENT_SOF:
2469                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2470                 break;
2471         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2472                 dev_vdbg(dwc->dev, "Erratic Error\n");
2473                 break;
2474         case DWC3_DEVICE_EVENT_CMD_CMPL:
2475                 dev_vdbg(dwc->dev, "Command Complete\n");
2476                 break;
2477         case DWC3_DEVICE_EVENT_OVERFLOW:
2478                 dev_vdbg(dwc->dev, "Overflow\n");
2479                 break;
2480         default:
2481                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2482         }
2483 }
2484
2485 static void dwc3_process_event_entry(struct dwc3 *dwc,
2486                 const union dwc3_event *event)
2487 {
2488         /* Endpoint IRQ, handle it and return early */
2489         if (event->type.is_devspec == 0) {
2490                 /* depevt */
2491                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2492         }
2493
2494         switch (event->type.type) {
2495         case DWC3_EVENT_TYPE_DEV:
2496                 dwc3_gadget_interrupt(dwc, &event->devt);
2497                 break;
2498         /* REVISIT what to do with Carkit and I2C events ? */
2499         default:
2500                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2501         }
2502 }
2503
2504 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2505 {
2506         struct dwc3 *dwc = _dwc;
2507         unsigned long flags;
2508         irqreturn_t ret = IRQ_NONE;
2509         int i;
2510
2511         spin_lock_irqsave(&dwc->lock, flags);
2512
2513         for (i = 0; i < dwc->num_event_buffers; i++) {
2514                 struct dwc3_event_buffer *evt;
2515                 int                     left;
2516
2517                 evt = dwc->ev_buffs[i];
2518                 left = evt->count;
2519
2520                 if (!(evt->flags & DWC3_EVENT_PENDING))
2521                         continue;
2522
2523                 while (left > 0) {
2524                         union dwc3_event event;
2525
2526                         event.raw = *(u32 *) (evt->buf + evt->lpos);
2527
2528                         dwc3_process_event_entry(dwc, &event);
2529
2530                         /*
2531                          * FIXME we wrap around correctly to the next entry as
2532                          * almost all entries are 4 bytes in size. There is one
2533                          * entry which has 12 bytes which is a regular entry
2534                          * followed by 8 bytes data. ATM I don't know how
2535                          * things are organized if we get next to the a
2536                          * boundary so I worry about that once we try to handle
2537                          * that.
2538                          */
2539                         evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2540                         left -= 4;
2541
2542                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);
2543                 }
2544
2545                 evt->count = 0;
2546                 evt->flags &= ~DWC3_EVENT_PENDING;
2547                 ret = IRQ_HANDLED;
2548         }
2549
2550         spin_unlock_irqrestore(&dwc->lock, flags);
2551
2552         return ret;
2553 }
2554
2555 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2556 {
2557         struct dwc3_event_buffer *evt;
2558         u32 count;
2559
2560         evt = dwc->ev_buffs[buf];
2561
2562         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2563         count &= DWC3_GEVNTCOUNT_MASK;
2564         if (!count)
2565                 return IRQ_NONE;
2566
2567         evt->count = count;
2568         evt->flags |= DWC3_EVENT_PENDING;
2569
2570         return IRQ_WAKE_THREAD;
2571 }
2572
2573 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2574 {
2575         struct dwc3                     *dwc = _dwc;
2576         int                             i;
2577         irqreturn_t                     ret = IRQ_NONE;
2578
2579         spin_lock(&dwc->lock);
2580
2581         for (i = 0; i < dwc->num_event_buffers; i++) {
2582                 irqreturn_t status;
2583
2584                 status = dwc3_process_event_buf(dwc, i);
2585                 if (status == IRQ_WAKE_THREAD)
2586                         ret = status;
2587         }
2588
2589         spin_unlock(&dwc->lock);
2590
2591         return ret;
2592 }
2593
2594 /**
2595  * dwc3_gadget_init - Initializes gadget related registers
2596  * @dwc: pointer to our controller context structure
2597  *
2598  * Returns 0 on success otherwise negative errno.
2599  */
2600 int dwc3_gadget_init(struct dwc3 *dwc)
2601 {
2602         u32                                     reg;
2603         int                                     ret;
2604
2605         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2606                         &dwc->ctrl_req_addr, GFP_KERNEL);
2607         if (!dwc->ctrl_req) {
2608                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2609                 ret = -ENOMEM;
2610                 goto err0;
2611         }
2612
2613         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2614                         &dwc->ep0_trb_addr, GFP_KERNEL);
2615         if (!dwc->ep0_trb) {
2616                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2617                 ret = -ENOMEM;
2618                 goto err1;
2619         }
2620
2621         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2622         if (!dwc->setup_buf) {
2623                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2624                 ret = -ENOMEM;
2625                 goto err2;
2626         }
2627
2628         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2629                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2630                         GFP_KERNEL);
2631         if (!dwc->ep0_bounce) {
2632                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2633                 ret = -ENOMEM;
2634                 goto err3;
2635         }
2636
2637         dwc->gadget.ops                 = &dwc3_gadget_ops;
2638         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2639         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2640         dwc->gadget.sg_supported        = true;
2641         dwc->gadget.name                = "dwc3-gadget";
2642
2643         /*
2644          * REVISIT: Here we should clear all pending IRQs to be
2645          * sure we're starting from a well known location.
2646          */
2647
2648         ret = dwc3_gadget_init_endpoints(dwc);
2649         if (ret)
2650                 goto err4;
2651
2652         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2653         reg |= DWC3_DCFG_LPM_CAP;
2654         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2655
2656         /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2657         if (dwc->revision >= DWC3_REVISION_194A) {
2658                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2659                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2660         }
2661
2662         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2663         if (ret) {
2664                 dev_err(dwc->dev, "failed to register udc\n");
2665                 goto err5;
2666         }
2667
2668         return 0;
2669
2670 err5:
2671         dwc3_gadget_free_endpoints(dwc);
2672
2673 err4:
2674         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2675                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2676
2677 err3:
2678         kfree(dwc->setup_buf);
2679
2680 err2:
2681         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2682                         dwc->ep0_trb, dwc->ep0_trb_addr);
2683
2684 err1:
2685         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2686                         dwc->ctrl_req, dwc->ctrl_req_addr);
2687
2688 err0:
2689         return ret;
2690 }
2691
2692 /* -------------------------------------------------------------------------- */
2693
2694 void dwc3_gadget_exit(struct dwc3 *dwc)
2695 {
2696         usb_del_gadget_udc(&dwc->gadget);
2697
2698         dwc3_gadget_free_endpoints(dwc);
2699
2700         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2701                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2702
2703         kfree(dwc->setup_buf);
2704
2705         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2706                         dwc->ep0_trb, dwc->ep0_trb_addr);
2707
2708         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2709                         dwc->ctrl_req, dwc->ctrl_req_addr);
2710 }
2711
2712 int dwc3_gadget_prepare(struct dwc3 *dwc)
2713 {
2714         if (dwc->pullups_connected)
2715                 dwc3_gadget_disable_irq(dwc);
2716
2717         return 0;
2718 }
2719
2720 void dwc3_gadget_complete(struct dwc3 *dwc)
2721 {
2722         if (dwc->pullups_connected) {
2723                 dwc3_gadget_enable_irq(dwc);
2724                 dwc3_gadget_run_stop(dwc, true);
2725         }
2726 }
2727
2728 int dwc3_gadget_suspend(struct dwc3 *dwc)
2729 {
2730         __dwc3_gadget_ep_disable(dwc->eps[0]);
2731         __dwc3_gadget_ep_disable(dwc->eps[1]);
2732
2733         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2734
2735         return 0;
2736 }
2737
2738 int dwc3_gadget_resume(struct dwc3 *dwc)
2739 {
2740         struct dwc3_ep          *dep;
2741         int                     ret;
2742
2743         /* Start with SuperSpeed Default */
2744         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2745
2746         dep = dwc->eps[0];
2747         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2748         if (ret)
2749                 goto err0;
2750
2751         dep = dwc->eps[1];
2752         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2753         if (ret)
2754                 goto err1;
2755
2756         /* begin to receive SETUP packets */
2757         dwc->ep0state = EP0_SETUP_PHASE;
2758         dwc3_ep0_out_start(dwc);
2759
2760         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2761
2762         return 0;
2763
2764 err1:
2765         __dwc3_gadget_ep_disable(dwc->eps[0]);
2766
2767 err0:
2768         return ret;
2769 }