drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 150  * @dwc: pointer to our context structure
 151  *
 152  * This function will a best effort FIFO allocation in order
 153  * to improve FIFO usage and throughput, while still allowing
 154  * us to enable as many endpoints as possible.
 155  *
 156  * Keep in mind that this operation will be highly dependent
 157  * on the configured size for RAM1 - which contains TxFifo -,
 158  * the amount of endpoints enabled on coreConsultant tool, and
 159  * the width of the Master Bus.
 160  *
 161  * In the ideal world, we would always be able to satisfy the
 162  * following equation:
 163  *
 164  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 165  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 166  *
 167  * Unfortunately, due to many variables that's not always the case.
 168  */
 169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 170 {
 171         int             last_fifo_depth = 0;
 172         int             ram1_depth;
 173         int             fifo_size;
 174         int             mdwidth;
 175         int             num;
 176
 177         if (!dwc->needs_fifo_resize)
 178                 return 0;
 179
 180         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 181         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 182
 183         /* MDWIDTH is represented in bits, we need it in bytes */
 184         mdwidth >>= 3;
 185
 186         /*
 187          * FIXME For now we will only allocate 1 wMaxPacketSize space
 188          * for each enabled endpoint, later patches will come to
 189          * improve this algorithm so that we better use the internal
 190          * FIFO space
 191          */
 192         for (num = 0; num < dwc->num_in_eps; num++) {
 193                 /* bit0 indicates direction; 1 means IN ep */
 194                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 195                 int             mult = 1;
 196                 int             tmp;
 197
 198                 if (!(dep->flags & DWC3_EP_ENABLED))
 199                         continue;
 200
 201                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 202                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 203                         mult = 3;
 204
 205                 /*
 206                  * REVISIT: the following assumes we will always have enough
 207                  * space available on the FIFO RAM for all possible use cases.
 208                  * Make sure that's true somehow and change FIFO allocation
 209                  * accordingly.
 210                  *
 211                  * If we have Bulk or Isochronous endpoints, we want
 212                  * them to be able to be very, very fast. So we're giving
 213                  * those endpoints a fifo_size which is enough for 3 full
 214                  * packets
 215                  */
 216                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 217                 tmp += mdwidth;
 218
 219                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 220
 221                 fifo_size |= (last_fifo_depth << 16);
 222
 223                 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
 224                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 225
 226                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 227
 228                 last_fifo_depth += (fifo_size & 0xffff);
 229         }
 230
 231         return 0;
 232 }
 233
 234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 235                 int status)
 236 {
 237         struct dwc3                     *dwc = dep->dwc;
 238         int                             i;
 239
 240         if (req->queued) {
 241                 i = 0;
 242                 do {
 243                         dep->busy_slot++;
 244                         /*
 245                          * Skip LINK TRB. We can't use req->trb and check for
 246                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 247                          * just completed (not the LINK TRB).
 248                          */
 249                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 250                                 DWC3_TRB_NUM- 1) &&
 251                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 252                                 dep->busy_slot++;
 253                 } while(++i < req->request.num_mapped_sgs);
 254                 req->queued = false;
 255         }
 256         list_del(&req->list);
 257         req->trb = NULL;
 258
 259         if (req->request.status == -EINPROGRESS)
 260                 req->request.status = status;
 261
 262         if (dwc->ep0_bounced && dep->number == 0)
 263                 dwc->ep0_bounced = false;
 264         else
 265                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 266                                 req->direction);
 267
 268         trace_dwc3_gadget_giveback(req);
 269
 270         spin_unlock(&dwc->lock);
 271         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 272         spin_lock(&dwc->lock);
 273 }
 274
 275 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 276 {
 277         u32             timeout = 500;
 278         u32             reg;
 279
 280         trace_dwc3_gadget_generic_cmd(cmd, param);
 281
 282         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 283         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 284
 285         do {
 286                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 287                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 288                         dwc3_trace(trace_dwc3_gadget,
 289                                         "Command Complete --> %d",
 290                                         DWC3_DGCMD_STATUS(reg));
 291                         if (DWC3_DGCMD_STATUS(reg))
 292                                 return -EINVAL;
 293                         return 0;
 294                 }
 295
 296                 /*
 297                  * We can't sleep here, because it's also called from
 298                  * interrupt context.
 299                  */
 300                 timeout--;
 301                 if (!timeout) {
 302                         dwc3_trace(trace_dwc3_gadget,
 303                                         "Command Timed Out");
 304                         return -ETIMEDOUT;
 305                 }
 306                 udelay(1);
 307         } while (1);
 308 }
 309
 310 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 311                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 312 {
 313         struct dwc3_ep          *dep = dwc->eps[ep];
 314         u32                     timeout = 500;
 315         u32                     reg;
 316
 317         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 318
 319         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 320         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 321         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 322
 323         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 324         do {
 325                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 326                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 327                         dwc3_trace(trace_dwc3_gadget,
 328                                         "Command Complete --> %d",
 329                                         DWC3_DEPCMD_STATUS(reg));
 330                         if (DWC3_DEPCMD_STATUS(reg))
 331                                 return -EINVAL;
 332                         return 0;
 333                 }
 334
 335                 /*
 336                  * We can't sleep here, because it is also called from
 337                  * interrupt context.
 338                  */
 339                 timeout--;
 340                 if (!timeout) {
 341                         dwc3_trace(trace_dwc3_gadget,
 342                                         "Command Timed Out");
 343                         return -ETIMEDOUT;
 344                 }
 345
 346                 udelay(1);
 347         } while (1);
 348 }
 349
 350 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 351                 struct dwc3_trb *trb)
 352 {
 353         u32             offset = (char *) trb - (char *) dep->trb_pool;
 354
 355         return dep->trb_pool_dma + offset;
 356 }
 357
 358 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 359 {
 360         struct dwc3             *dwc = dep->dwc;
 361
 362         if (dep->trb_pool)
 363                 return 0;
 364
 365         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 366                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 367                         &dep->trb_pool_dma, GFP_KERNEL);
 368         if (!dep->trb_pool) {
 369                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 370                                 dep->name);
 371                 return -ENOMEM;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 378 {
 379         struct dwc3             *dwc = dep->dwc;
 380
 381         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 382                         dep->trb_pool, dep->trb_pool_dma);
 383
 384         dep->trb_pool = NULL;
 385         dep->trb_pool_dma = 0;
 386 }
 387
 388 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 389
 390 /**
 391  * dwc3_gadget_start_config - Configure EP resources
 392  * @dwc: pointer to our controller context structure
 393  * @dep: endpoint that is being enabled
 394  *
 395  * The assignment of transfer resources cannot perfectly follow the
 396  * data book due to the fact that the controller driver does not have
 397  * all knowledge of the configuration in advance. It is given this
 398  * information piecemeal by the composite gadget framework after every
 399  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 400  * programming model in this scenario can cause errors. For two
 401  * reasons:
 402  *
 403  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 404  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 405  * multiple interfaces.
 406  *
 407  * 2) The databook does not mention doing more DEPXFERCFG for new
 408  * endpoint on alt setting (8.1.6).
 409  *
 410  * The following simplified method is used instead:
 411  *
 412  * All hardware endpoints can be assigned a transfer resource and this
 413  * setting will stay persistent until either a core reset or
 414  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 415  * do DEPXFERCFG for every hardware endpoint as well. We are
 416  * guaranteed that there are as many transfer resources as endpoints.
 417  *
 418  * This function is called for each endpoint when it is being enabled
 419  * but is triggered only when called for EP0-out, which always happens
 420  * first, and which should only happen in one of the above conditions.
 421  */
 422 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 423 {
 424         struct dwc3_gadget_ep_cmd_params params;
 425         u32                     cmd;
 426         int                     i;
 427         int                     ret;
 428
 429         if (dep->number)
 430                 return 0;
 431
 432         memset(&params, 0x00, sizeof(params));
 433         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 434
 435         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 436         if (ret)
 437                 return ret;
 438
 439         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 440                 struct dwc3_ep *dep = dwc->eps[i];
 441
 442                 if (!dep)
 443                         continue;
 444
 445                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 446                 if (ret)
 447                         return ret;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 454                 const struct usb_endpoint_descriptor *desc,
 455                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 456                 bool ignore, bool restore)
 457 {
 458         struct dwc3_gadget_ep_cmd_params params;
 459
 460         memset(&params, 0x00, sizeof(params));
 461
 462         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 463                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 464
 465         /* Burst size is only needed in SuperSpeed mode */
 466         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 467                 u32 burst = dep->endpoint.maxburst - 1;
 468
 469                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 470         }
 471
 472         if (ignore)
 473                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 474
 475         if (restore) {
 476                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 477                 params.param2 |= dep->saved_state;
 478         }
 479
 480         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 481                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 482
 483         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 484                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 485                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 486                 dep->stream_capable = true;
 487         }
 488
 489         if (!usb_endpoint_xfer_control(desc))
 490                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 491
 492         /*
 493          * We are doing 1:1 mapping for endpoints, meaning
 494          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 495          * so on. We consider the direction bit as part of the physical
 496          * endpoint number. So USB endpoint 0x81 is 0x03.
 497          */
 498         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 499
 500         /*
 501          * We must use the lower 16 TX FIFOs even though
 502          * HW might have more
 503          */
 504         if (dep->direction)
 505                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 506
 507         if (desc->bInterval) {
 508                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 509                 dep->interval = 1 << (desc->bInterval - 1);
 510         }
 511
 512         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 513                         DWC3_DEPCMD_SETEPCONFIG, &params);
 514 }
 515
 516 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519
 520         memset(&params, 0x00, sizeof(params));
 521
 522         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 523
 524         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 525                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 526 }
 527
 528 /**
 529  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 530  * @dep: endpoint to be initialized
 531  * @desc: USB Endpoint Descriptor
 532  *
 533  * Caller should take care of locking
 534  */
 535 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 536                 const struct usb_endpoint_descriptor *desc,
 537                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 538                 bool ignore, bool restore)
 539 {
 540         struct dwc3             *dwc = dep->dwc;
 541         u32                     reg;
 542         int                     ret;
 543
 544         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 545
 546         if (!(dep->flags & DWC3_EP_ENABLED)) {
 547                 ret = dwc3_gadget_start_config(dwc, dep);
 548                 if (ret)
 549                         return ret;
 550         }
 551
 552         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 553                         restore);
 554         if (ret)
 555                 return ret;
 556
 557         if (!(dep->flags & DWC3_EP_ENABLED)) {
 558                 struct dwc3_trb *trb_st_hw;
 559                 struct dwc3_trb *trb_link;
 560
 561                 dep->endpoint.desc = desc;
 562                 dep->comp_desc = comp_desc;
 563                 dep->type = usb_endpoint_type(desc);
 564                 dep->flags |= DWC3_EP_ENABLED;
 565
 566                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 567                 reg |= DWC3_DALEPENA_EP(dep->number);
 568                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 569
 570                 if (!usb_endpoint_xfer_isoc(desc))
 571                         return 0;
 572
 573                 /* Link TRB for ISOC. The HWO bit is never reset */
 574                 trb_st_hw = &dep->trb_pool[0];
 575
 576                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 577                 memset(trb_link, 0, sizeof(*trb_link));
 578
 579                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 580                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 581                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 582                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 583         }
 584
 585         switch (usb_endpoint_type(desc)) {
 586         case USB_ENDPOINT_XFER_CONTROL:
 587                 strlcat(dep->name, "-control", sizeof(dep->name));
 588                 break;
 589         case USB_ENDPOINT_XFER_ISOC:
 590                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 591                 break;
 592         case USB_ENDPOINT_XFER_BULK:
 593                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 594                 break;
 595         case USB_ENDPOINT_XFER_INT:
 596                 strlcat(dep->name, "-int", sizeof(dep->name));
 597                 break;
 598         default:
 599                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 606 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 607 {
 608         struct dwc3_request             *req;
 609
 610         if (!list_empty(&dep->req_queued)) {
 611                 dwc3_stop_active_transfer(dwc, dep->number, true);
 612
 613                 /* - giveback all requests to gadget driver */
 614                 while (!list_empty(&dep->req_queued)) {
 615                         req = next_request(&dep->req_queued);
 616
 617                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 618                 }
 619         }
 620
 621         while (!list_empty(&dep->request_list)) {
 622                 req = next_request(&dep->request_list);
 623
 624                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 625         }
 626 }
 627
 628 /**
 629  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 630  * @dep: the endpoint to disable
 631  *
 632  * This function also removes requests which are currently processed ny the
 633  * hardware and those which are not yet scheduled.
 634  * Caller should take care of locking.
 635  */
 636 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 637 {
 638         struct dwc3             *dwc = dep->dwc;
 639         u32                     reg;
 640
 641         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 642
 643         dwc3_remove_requests(dwc, dep);
 644
 645         /* make sure HW endpoint isn't stalled */
 646         if (dep->flags & DWC3_EP_STALL)
 647                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 648
 649         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 650         reg &= ~DWC3_DALEPENA_EP(dep->number);
 651         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 652
 653         dep->stream_capable = false;
 654         dep->endpoint.desc = NULL;
 655         dep->comp_desc = NULL;
 656         dep->type = 0;
 657         dep->flags = 0;
 658
 659         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 660                         dep->number >> 1,
 661                         (dep->number & 1) ? "in" : "out");
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         trace_dwc3_alloc_request(req);
 755
 756         return &req->request;
 757 }
 758
 759 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 760                 struct usb_request *request)
 761 {
 762         struct dwc3_request             *req = to_dwc3_request(request);
 763
 764         trace_dwc3_free_request(req);
 765         kfree(req);
 766 }
 767
 768 /**
 769  * dwc3_prepare_one_trb - setup one TRB from one request
 770  * @dep: endpoint for which this request is prepared
 771  * @req: dwc3_request pointer
 772  */
 773 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 774                 struct dwc3_request *req, dma_addr_t dma,
 775                 unsigned length, unsigned last, unsigned chain, unsigned node)
 776 {
 777         struct dwc3_trb         *trb;
 778
 779         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 780                         dep->name, req, (unsigned long long) dma,
 781                         length, last ? " last" : "",
 782                         chain ? " chain" : "");
 783
 784
 785         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 786
 787         if (!req->trb) {
 788                 dwc3_gadget_move_request_queued(req);
 789                 req->trb = trb;
 790                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 791                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 792         }
 793
 794         dep->free_slot++;
 795         /* Skip the LINK-TRB on ISOC */
 796         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 797                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 798                 dep->free_slot++;
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814                 break;
 815
 816         case USB_ENDPOINT_XFER_BULK:
 817         case USB_ENDPOINT_XFER_INT:
 818                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 819                 break;
 820         default:
 821                 /*
 822                  * This is only possible with faulty memory because we
 823                  * checked it already :)
 824                  */
 825                 BUG();
 826         }
 827
 828         if (!req->request.no_interrupt && !chain)
 829                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 830
 831         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 832                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 833                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 834         } else if (last) {
 835                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 836         }
 837
 838         if (chain)
 839                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 840
 841         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 842                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 843
 844         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 845
 846         trace_dwc3_prepare_trb(dep, trb);
 847 }
 848
 849 /*
 850  * dwc3_prepare_trbs - setup TRBs from requests
 851  * @dep: endpoint for which requests are being prepared
 852  * @starting: true if the endpoint is idle and no requests are queued.
 853  *
 854  * The function goes through the requests list and sets up TRBs for the
 855  * transfers. The function returns once there are no more TRBs available or
 856  * it runs out of requests.
 857  */
 858 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 859 {
 860         struct dwc3_request     *req, *n;
 861         u32                     trbs_left;
 862         u32                     max;
 863         unsigned int            last_one = 0;
 864
 865         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 866
 867         /* the first request must not be queued */
 868         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 869
 870         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 871         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 872                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 873                 if (trbs_left > max)
 874                         trbs_left = max;
 875         }
 876
 877         /*
 878          * If busy & slot are equal than it is either full or empty. If we are
 879          * starting to process requests then we are empty. Otherwise we are
 880          * full and don't do anything
 881          */
 882         if (!trbs_left) {
 883                 if (!starting)
 884                         return;
 885                 trbs_left = DWC3_TRB_NUM;
 886                 /*
 887                  * In case we start from scratch, we queue the ISOC requests
 888                  * starting from slot 1. This is done because we use ring
 889                  * buffer and have no LST bit to stop us. Instead, we place
 890                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 891                  * after the first request so we start at slot 1 and have
 892                  * 7 requests proceed before we hit the first IOC.
 893                  * Other transfer types don't use the ring buffer and are
 894                  * processed from the first TRB until the last one. Since we
 895                  * don't wrap around we have to start at the beginning.
 896                  */
 897                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 898                         dep->busy_slot = 1;
 899                         dep->free_slot = 1;
 900                 } else {
 901                         dep->busy_slot = 0;
 902                         dep->free_slot = 0;
 903                 }
 904         }
 905
 906         /* The last TRB is a link TRB, not used for xfer */
 907         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 908                 return;
 909
 910         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 911                 unsigned        length;
 912                 dma_addr_t      dma;
 913                 last_one = false;
 914
 915                 if (req->request.num_mapped_sgs > 0) {
 916                         struct usb_request *request = &req->request;
 917                         struct scatterlist *sg = request->sg;
 918                         struct scatterlist *s;
 919                         int             i;
 920
 921                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 922                                 unsigned chain = true;
 923
 924                                 length = sg_dma_len(s);
 925                                 dma = sg_dma_address(s);
 926
 927                                 if (i == (request->num_mapped_sgs - 1) ||
 928                                                 sg_is_last(s)) {
 929                                         if (list_empty(&dep->request_list))
 930                                                 last_one = true;
 931                                         chain = false;
 932                                 }
 933
 934                                 trbs_left--;
 935                                 if (!trbs_left)
 936                                         last_one = true;
 937
 938                                 if (last_one)
 939                                         chain = false;
 940
 941                                 dwc3_prepare_one_trb(dep, req, dma, length,
 942                                                 last_one, chain, i);
 943
 944                                 if (last_one)
 945                                         break;
 946                         }
 947
 948                         if (last_one)
 949                                 break;
 950                 } else {
 951                         dma = req->request.dma;
 952                         length = req->request.length;
 953                         trbs_left--;
 954
 955                         if (!trbs_left)
 956                                 last_one = 1;
 957
 958                         /* Is this the last request? */
 959                         if (list_is_last(&req->list, &dep->request_list))
 960                                 last_one = 1;
 961
 962                         dwc3_prepare_one_trb(dep, req, dma, length,
 963                                         last_one, false, 0);
 964
 965                         if (last_one)
 966                                 break;
 967                 }
 968         }
 969 }
 970
 971 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 972                 int start_new)
 973 {
 974         struct dwc3_gadget_ep_cmd_params params;
 975         struct dwc3_request             *req;
 976         struct dwc3                     *dwc = dep->dwc;
 977         int                             ret;
 978         u32                             cmd;
 979
 980         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 981                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 982                 return -EBUSY;
 983         }
 984
 985         /*
 986          * If we are getting here after a short-out-packet we don't enqueue any
 987          * new requests as we try to set the IOC bit only on the last request.
 988          */
 989         if (start_new) {
 990                 if (list_empty(&dep->req_queued))
 991                         dwc3_prepare_trbs(dep, start_new);
 992
 993                 /* req points to the first request which will be sent */
 994                 req = next_request(&dep->req_queued);
 995         } else {
 996                 dwc3_prepare_trbs(dep, start_new);
 997
 998                 /*
 999                  * req points to the first request where HWO changed from 0 to 1
1000                  */
1001                 req = next_request(&dep->req_queued);
1002         }
1003         if (!req) {
1004                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1005                 return 0;
1006         }
1007
1008         memset(&params, 0, sizeof(params));
1009
1010         if (start_new) {
1011                 params.param0 = upper_32_bits(req->trb_dma);
1012                 params.param1 = lower_32_bits(req->trb_dma);
1013                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1014         } else {
1015                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1016         }
1017
1018         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1020         if (ret < 0) {
1021                 /*
1022                  * FIXME we need to iterate over the list of requests
1023                  * here and stop, unmap, free and del each of the linked
1024                  * requests instead of what we do now.
1025                  */
1026                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1027                                 req->direction);
1028                 list_del(&req->list);
1029                 return ret;
1030         }
1031
1032         dep->flags |= DWC3_EP_BUSY;
1033
1034         if (start_new) {
1035                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1036                                 dep->number);
1037                 WARN_ON_ONCE(!dep->resource_index);
1038         }
1039
1040         return 0;
1041 }
1042
1043 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044                 struct dwc3_ep *dep, u32 cur_uf)
1045 {
1046         u32 uf;
1047
1048         if (list_empty(&dep->request_list)) {
1049                 dwc3_trace(trace_dwc3_gadget,
1050                                 "ISOC ep %s run out for requests",
1051                                 dep->name);
1052                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1053                 return;
1054         }
1055
1056         /* 4 micro frames in the future */
1057         uf = cur_uf + dep->interval * 4;
1058
1059         __dwc3_gadget_kick_transfer(dep, uf, 1);
1060 }
1061
1062 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1064 {
1065         u32 cur_uf, mask;
1066
1067         mask = ~(dep->interval - 1);
1068         cur_uf = event->parameters & mask;
1069
1070         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1071 }
1072
1073 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1074 {
1075         struct dwc3             *dwc = dep->dwc;
1076         int                     ret;
1077
1078         if (!dep->endpoint.desc) {
1079                 dwc3_trace(trace_dwc3_gadget,
1080                                 "trying to queue request %p to disabled %s\n",
1081                                 &req->request, dep->endpoint.name);
1082                 return -ESHUTDOWN;
1083         }
1084
1085         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086                                 &req->request, req->dep->name)) {
1087                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088                                 &req->request, req->dep->name);
1089                 return -EINVAL;
1090         }
1091
1092         req->request.actual     = 0;
1093         req->request.status     = -EINPROGRESS;
1094         req->direction          = dep->direction;
1095         req->epnum              = dep->number;
1096
1097         trace_dwc3_ep_queue(req);
1098
1099         /*
1100          * Per databook, the total size of buffer must be a multiple
1101          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1102          * configed for endpoints in dwc3_gadget_set_ep_config(),
1103          * set to usb_endpoint_descriptor->wMaxPacketSize.
1104          */
1105         if (dep->direction == 0 &&
1106             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1107                 req->request.length = roundup(req->request.length,
1108                                         dep->endpoint.desc->wMaxPacketSize);
1109
1110         /*
1111          * We only add to our list of requests now and
1112          * start consuming the list once we get XferNotReady
1113          * IRQ.
1114          *
1115          * That way, we avoid doing anything that we don't need
1116          * to do now and defer it until the point we receive a
1117          * particular token from the Host side.
1118          *
1119          * This will also avoid Host cancelling URBs due to too
1120          * many NAKs.
1121          */
1122         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1123                         dep->direction);
1124         if (ret)
1125                 return ret;
1126
1127         list_add_tail(&req->list, &dep->request_list);
1128
1129         /*
1130          * If there are no pending requests and the endpoint isn't already
1131          * busy, we will just start the request straight away.
1132          *
1133          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1134          * little bit faster.
1135          */
1136         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1137                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1138                         !(dep->flags & DWC3_EP_BUSY)) {
1139                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1140                 goto out;
1141         }
1142
1143         /*
1144          * There are a few special cases:
1145          *
1146          * 1. XferNotReady with empty list of requests. We need to kick the
1147          *    transfer here in that situation, otherwise we will be NAKing
1148          *    forever. If we get XferNotReady before gadget driver has a
1149          *    chance to queue a request, we will ACK the IRQ but won't be
1150          *    able to receive the data until the next request is queued.
1151          *    The following code is handling exactly that.
1152          *
1153          */
1154         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1155                 /*
1156                  * If xfernotready is already elapsed and it is a case
1157                  * of isoc transfer, then issue END TRANSFER, so that
1158                  * you can receive xfernotready again and can have
1159                  * notion of current microframe.
1160                  */
1161                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1162                         if (list_empty(&dep->req_queued)) {
1163                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1164                                 dep->flags = DWC3_EP_ENABLED;
1165                         }
1166                         return 0;
1167                 }
1168
1169                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1170                 if (!ret)
1171                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1172
1173                 goto out;
1174         }
1175
1176         /*
1177          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1178          *    kick the transfer here after queuing a request, otherwise the
1179          *    core may not see the modified TRB(s).
1180          */
1181         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1182                         (dep->flags & DWC3_EP_BUSY) &&
1183                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1184                 WARN_ON_ONCE(!dep->resource_index);
1185                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1186                                 false);
1187                 goto out;
1188         }
1189
1190         /*
1191          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1192          * right away, otherwise host will not know we have streams to be
1193          * handled.
1194          */
1195         if (dep->stream_capable)
1196                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1197
1198 out:
1199         if (ret && ret != -EBUSY)
1200                 dwc3_trace(trace_dwc3_gadget,
1201                                 "%s: failed to kick transfers\n",
1202                                 dep->name);
1203         if (ret == -EBUSY)
1204                 ret = 0;
1205
1206         return ret;
1207 }
1208
1209 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1210                 struct usb_request *request)
1211 {
1212         dwc3_gadget_ep_free_request(ep, request);
1213 }
1214
1215 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1216 {
1217         struct dwc3_request             *req;
1218         struct usb_request              *request;
1219         struct usb_ep                   *ep = &dep->endpoint;
1220
1221         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1222         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1223         if (!request)
1224                 return -ENOMEM;
1225
1226         request->length = 0;
1227         request->buf = dwc->zlp_buf;
1228         request->complete = __dwc3_gadget_ep_zlp_complete;
1229
1230         req = to_dwc3_request(request);
1231
1232         return __dwc3_gadget_ep_queue(dep, req);
1233 }
1234
1235 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1236         gfp_t gfp_flags)
1237 {
1238         struct dwc3_request             *req = to_dwc3_request(request);
1239         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1240         struct dwc3                     *dwc = dep->dwc;
1241
1242         unsigned long                   flags;
1243
1244         int                             ret;
1245
1246         spin_lock_irqsave(&dwc->lock, flags);
1247         ret = __dwc3_gadget_ep_queue(dep, req);
1248
1249         /*
1250          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1251          * setting request->zero, instead of doing magic, we will just queue an
1252          * extra usb_request ourselves so that it gets handled the same way as
1253          * any other request.
1254          */
1255         if (ret == 0 && request->zero && request->length &&
1256             (request->length % ep->desc->wMaxPacketSize == 0))
1257                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1258
1259         spin_unlock_irqrestore(&dwc->lock, flags);
1260
1261         return ret;
1262 }
1263
1264 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1265                 struct usb_request *request)
1266 {
1267         struct dwc3_request             *req = to_dwc3_request(request);
1268         struct dwc3_request             *r = NULL;
1269
1270         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1271         struct dwc3                     *dwc = dep->dwc;
1272
1273         unsigned long                   flags;
1274         int                             ret = 0;
1275
1276         trace_dwc3_ep_dequeue(req);
1277
1278         spin_lock_irqsave(&dwc->lock, flags);
1279
1280         list_for_each_entry(r, &dep->request_list, list) {
1281                 if (r == req)
1282                         break;
1283         }
1284
1285         if (r != req) {
1286                 list_for_each_entry(r, &dep->req_queued, list) {
1287                         if (r == req)
1288                                 break;
1289                 }
1290                 if (r == req) {
1291                         /* wait until it is processed */
1292                         dwc3_stop_active_transfer(dwc, dep->number, true);
1293                         goto out1;
1294                 }
1295                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1296                                 request, ep->name);
1297                 ret = -EINVAL;
1298                 goto out0;
1299         }
1300
1301 out1:
1302         /* giveback the request */
1303         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1304
1305 out0:
1306         spin_unlock_irqrestore(&dwc->lock, flags);
1307
1308         return ret;
1309 }
1310
1311 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1312 {
1313         struct dwc3_gadget_ep_cmd_params        params;
1314         struct dwc3                             *dwc = dep->dwc;
1315         int                                     ret;
1316
1317         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1318                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1319                 return -EINVAL;
1320         }
1321
1322         memset(&params, 0x00, sizeof(params));
1323
1324         if (value) {
1325                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1326                                 (!list_empty(&dep->req_queued) ||
1327                                  !list_empty(&dep->request_list)))) {
1328                         dwc3_trace(trace_dwc3_gadget,
1329                                         "%s: pending request, cannot halt\n",
1330                                         dep->name);
1331                         return -EAGAIN;
1332                 }
1333
1334                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1335                         DWC3_DEPCMD_SETSTALL, &params);
1336                 if (ret)
1337                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1338                                         dep->name);
1339                 else
1340                         dep->flags |= DWC3_EP_STALL;
1341         } else {
1342                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1343                         DWC3_DEPCMD_CLEARSTALL, &params);
1344                 if (ret)
1345                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1346                                         dep->name);
1347                 else
1348                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1349         }
1350
1351         return ret;
1352 }
1353
1354 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1355 {
1356         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1357         struct dwc3                     *dwc = dep->dwc;
1358
1359         unsigned long                   flags;
1360
1361         int                             ret;
1362
1363         spin_lock_irqsave(&dwc->lock, flags);
1364         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1365         spin_unlock_irqrestore(&dwc->lock, flags);
1366
1367         return ret;
1368 }
1369
1370 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1371 {
1372         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1373         struct dwc3                     *dwc = dep->dwc;
1374         unsigned long                   flags;
1375         int                             ret;
1376
1377         spin_lock_irqsave(&dwc->lock, flags);
1378         dep->flags |= DWC3_EP_WEDGE;
1379
1380         if (dep->number == 0 || dep->number == 1)
1381                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1382         else
1383                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1384         spin_unlock_irqrestore(&dwc->lock, flags);
1385
1386         return ret;
1387 }
1388
1389 /* -------------------------------------------------------------------------- */
1390
1391 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1392         .bLength        = USB_DT_ENDPOINT_SIZE,
1393         .bDescriptorType = USB_DT_ENDPOINT,
1394         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1395 };
1396
1397 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1398         .enable         = dwc3_gadget_ep0_enable,
1399         .disable        = dwc3_gadget_ep0_disable,
1400         .alloc_request  = dwc3_gadget_ep_alloc_request,
1401         .free_request   = dwc3_gadget_ep_free_request,
1402         .queue          = dwc3_gadget_ep0_queue,
1403         .dequeue        = dwc3_gadget_ep_dequeue,
1404         .set_halt       = dwc3_gadget_ep0_set_halt,
1405         .set_wedge      = dwc3_gadget_ep_set_wedge,
1406 };
1407
1408 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1409         .enable         = dwc3_gadget_ep_enable,
1410         .disable        = dwc3_gadget_ep_disable,
1411         .alloc_request  = dwc3_gadget_ep_alloc_request,
1412         .free_request   = dwc3_gadget_ep_free_request,
1413         .queue          = dwc3_gadget_ep_queue,
1414         .dequeue        = dwc3_gadget_ep_dequeue,
1415         .set_halt       = dwc3_gadget_ep_set_halt,
1416         .set_wedge      = dwc3_gadget_ep_set_wedge,
1417 };
1418
1419 /* -------------------------------------------------------------------------- */
1420
1421 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1422 {
1423         struct dwc3             *dwc = gadget_to_dwc(g);
1424         u32                     reg;
1425
1426         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1427         return DWC3_DSTS_SOFFN(reg);
1428 }
1429
1430 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1431 {
1432         struct dwc3             *dwc = gadget_to_dwc(g);
1433
1434         unsigned long           timeout;
1435         unsigned long           flags;
1436
1437         u32                     reg;
1438
1439         int                     ret = 0;
1440
1441         u8                      link_state;
1442         u8                      speed;
1443
1444         spin_lock_irqsave(&dwc->lock, flags);
1445
1446         /*
1447          * According to the Databook Remote wakeup request should
1448          * be issued only when the device is in early suspend state.
1449          *
1450          * We can check that via USB Link State bits in DSTS register.
1451          */
1452         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1453
1454         speed = reg & DWC3_DSTS_CONNECTSPD;
1455         if (speed == DWC3_DSTS_SUPERSPEED) {
1456                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1457                 ret = -EINVAL;
1458                 goto out;
1459         }
1460
1461         link_state = DWC3_DSTS_USBLNKST(reg);
1462
1463         switch (link_state) {
1464         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1465         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1466                 break;
1467         default:
1468                 dwc3_trace(trace_dwc3_gadget,
1469                                 "can't wakeup from '%s'\n",
1470                                 dwc3_gadget_link_string(link_state));
1471                 ret = -EINVAL;
1472                 goto out;
1473         }
1474
1475         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1476         if (ret < 0) {
1477                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1478                 goto out;
1479         }
1480
1481         /* Recent versions do this automatically */
1482         if (dwc->revision < DWC3_REVISION_194A) {
1483                 /* write zeroes to Link Change Request */
1484                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1485                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1486                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1487         }
1488
1489         /* poll until Link State changes to ON */
1490         timeout = jiffies + msecs_to_jiffies(100);
1491
1492         while (!time_after(jiffies, timeout)) {
1493                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1494
1495                 /* in HS, means ON */
1496                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1497                         break;
1498         }
1499
1500         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1501                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1502                 ret = -EINVAL;
1503         }
1504
1505 out:
1506         spin_unlock_irqrestore(&dwc->lock, flags);
1507
1508         return ret;
1509 }
1510
1511 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1512                 int is_selfpowered)
1513 {
1514         struct dwc3             *dwc = gadget_to_dwc(g);
1515         unsigned long           flags;
1516
1517         spin_lock_irqsave(&dwc->lock, flags);
1518         g->is_selfpowered = !!is_selfpowered;
1519         spin_unlock_irqrestore(&dwc->lock, flags);
1520
1521         return 0;
1522 }
1523
1524 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1525 {
1526         u32                     reg;
1527         u32                     timeout = 500;
1528
1529         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1530         if (is_on) {
1531                 if (dwc->revision <= DWC3_REVISION_187A) {
1532                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1533                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1534                 }
1535
1536                 if (dwc->revision >= DWC3_REVISION_194A)
1537                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1538                 reg |= DWC3_DCTL_RUN_STOP;
1539
1540                 if (dwc->has_hibernation)
1541                         reg |= DWC3_DCTL_KEEP_CONNECT;
1542
1543                 dwc->pullups_connected = true;
1544         } else {
1545                 reg &= ~DWC3_DCTL_RUN_STOP;
1546
1547                 if (dwc->has_hibernation && !suspend)
1548                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1549
1550                 dwc->pullups_connected = false;
1551         }
1552
1553         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1554
1555         do {
1556                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1557                 if (is_on) {
1558                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1559                                 break;
1560                 } else {
1561                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1562                                 break;
1563                 }
1564                 timeout--;
1565                 if (!timeout)
1566                         return -ETIMEDOUT;
1567                 udelay(1);
1568         } while (1);
1569
1570         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1571                         dwc->gadget_driver
1572                         ? dwc->gadget_driver->function : "no-function",
1573                         is_on ? "connect" : "disconnect");
1574
1575         return 0;
1576 }
1577
1578 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1579 {
1580         struct dwc3             *dwc = gadget_to_dwc(g);
1581         unsigned long           flags;
1582         int                     ret;
1583
1584         is_on = !!is_on;
1585
1586         spin_lock_irqsave(&dwc->lock, flags);
1587         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1588         spin_unlock_irqrestore(&dwc->lock, flags);
1589
1590         return ret;
1591 }
1592
1593 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1594 {
1595         u32                     reg;
1596
1597         /* Enable all but Start and End of Frame IRQs */
1598         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1599                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1600                         DWC3_DEVTEN_CMDCMPLTEN |
1601                         DWC3_DEVTEN_ERRTICERREN |
1602                         DWC3_DEVTEN_WKUPEVTEN |
1603                         DWC3_DEVTEN_ULSTCNGEN |
1604                         DWC3_DEVTEN_CONNECTDONEEN |
1605                         DWC3_DEVTEN_USBRSTEN |
1606                         DWC3_DEVTEN_DISCONNEVTEN);
1607
1608         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1609 }
1610
1611 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1612 {
1613         /* mask all interrupts */
1614         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1615 }
1616
1617 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1618 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1619
1620 static int dwc3_gadget_start(struct usb_gadget *g,
1621                 struct usb_gadget_driver *driver)
1622 {
1623         struct dwc3             *dwc = gadget_to_dwc(g);
1624         struct dwc3_ep          *dep;
1625         unsigned long           flags;
1626         int                     ret = 0;
1627         int                     irq;
1628         u32                     reg;
1629
1630         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1631         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1632                         IRQF_SHARED, "dwc3", dwc);
1633         if (ret) {
1634                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1635                                 irq, ret);
1636                 goto err0;
1637         }
1638
1639         spin_lock_irqsave(&dwc->lock, flags);
1640
1641         if (dwc->gadget_driver) {
1642                 dev_err(dwc->dev, "%s is already bound to %s\n",
1643                                 dwc->gadget.name,
1644                                 dwc->gadget_driver->driver.name);
1645                 ret = -EBUSY;
1646                 goto err1;
1647         }
1648
1649         dwc->gadget_driver      = driver;
1650
1651         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1652         reg &= ~(DWC3_DCFG_SPEED_MASK);
1653
1654         /**
1655          * WORKAROUND: DWC3 revision < 2.20a have an issue
1656          * which would cause metastability state on Run/Stop
1657          * bit if we try to force the IP to USB2-only mode.
1658          *
1659          * Because of that, we cannot configure the IP to any
1660          * speed other than the SuperSpeed
1661          *
1662          * Refers to:
1663          *
1664          * STAR#9000525659: Clock Domain Crossing on DCTL in
1665          * USB 2.0 Mode
1666          */
1667         if (dwc->revision < DWC3_REVISION_220A) {
1668                 reg |= DWC3_DCFG_SUPERSPEED;
1669         } else {
1670                 switch (dwc->maximum_speed) {
1671                 case USB_SPEED_LOW:
1672                         reg |= DWC3_DSTS_LOWSPEED;
1673                         break;
1674                 case USB_SPEED_FULL:
1675                         reg |= DWC3_DSTS_FULLSPEED1;
1676                         break;
1677                 case USB_SPEED_HIGH:
1678                         reg |= DWC3_DSTS_HIGHSPEED;
1679                         break;
1680                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1681                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1682                 default:
1683                         reg |= DWC3_DSTS_SUPERSPEED;
1684                 }
1685         }
1686         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1687
1688         /* Start with SuperSpeed Default */
1689         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1690
1691         dep = dwc->eps[0];
1692         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1693                         false);
1694         if (ret) {
1695                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1696                 goto err2;
1697         }
1698
1699         dep = dwc->eps[1];
1700         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1701                         false);
1702         if (ret) {
1703                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1704                 goto err3;
1705         }
1706
1707         /* begin to receive SETUP packets */
1708         dwc->ep0state = EP0_SETUP_PHASE;
1709         dwc3_ep0_out_start(dwc);
1710
1711         dwc3_gadget_enable_irq(dwc);
1712
1713         spin_unlock_irqrestore(&dwc->lock, flags);
1714
1715         return 0;
1716
1717 err3:
1718         __dwc3_gadget_ep_disable(dwc->eps[0]);
1719
1720 err2:
1721         dwc->gadget_driver = NULL;
1722
1723 err1:
1724         spin_unlock_irqrestore(&dwc->lock, flags);
1725
1726         free_irq(irq, dwc);
1727
1728 err0:
1729         return ret;
1730 }
1731
1732 static int dwc3_gadget_stop(struct usb_gadget *g)
1733 {
1734         struct dwc3             *dwc = gadget_to_dwc(g);
1735         unsigned long           flags;
1736         int                     irq;
1737
1738         spin_lock_irqsave(&dwc->lock, flags);
1739
1740         dwc3_gadget_disable_irq(dwc);
1741         __dwc3_gadget_ep_disable(dwc->eps[0]);
1742         __dwc3_gadget_ep_disable(dwc->eps[1]);
1743
1744         dwc->gadget_driver      = NULL;
1745
1746         spin_unlock_irqrestore(&dwc->lock, flags);
1747
1748         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1749         free_irq(irq, dwc);
1750
1751         return 0;
1752 }
1753
1754 static const struct usb_gadget_ops dwc3_gadget_ops = {
1755         .get_frame              = dwc3_gadget_get_frame,
1756         .wakeup                 = dwc3_gadget_wakeup,
1757         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1758         .pullup                 = dwc3_gadget_pullup,
1759         .udc_start              = dwc3_gadget_start,
1760         .udc_stop               = dwc3_gadget_stop,
1761 };
1762
1763 /* -------------------------------------------------------------------------- */
1764
1765 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1766                 u8 num, u32 direction)
1767 {
1768         struct dwc3_ep                  *dep;
1769         u8                              i;
1770
1771         for (i = 0; i < num; i++) {
1772                 u8 epnum = (i << 1) | (!!direction);
1773
1774                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1775                 if (!dep)
1776                         return -ENOMEM;
1777
1778                 dep->dwc = dwc;
1779                 dep->number = epnum;
1780                 dep->direction = !!direction;
1781                 dwc->eps[epnum] = dep;
1782
1783                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1784                                 (epnum & 1) ? "in" : "out");
1785
1786                 dep->endpoint.name = dep->name;
1787
1788                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1789
1790                 if (epnum == 0 || epnum == 1) {
1791                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1792                         dep->endpoint.maxburst = 1;
1793                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1794                         if (!epnum)
1795                                 dwc->gadget.ep0 = &dep->endpoint;
1796                 } else {
1797                         int             ret;
1798
1799                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1800                         dep->endpoint.max_streams = 15;
1801                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1802                         list_add_tail(&dep->endpoint.ep_list,
1803                                         &dwc->gadget.ep_list);
1804
1805                         ret = dwc3_alloc_trb_pool(dep);
1806                         if (ret)
1807                                 return ret;
1808                 }
1809
1810                 if (epnum == 0 || epnum == 1) {
1811                         dep->endpoint.caps.type_control = true;
1812                 } else {
1813                         dep->endpoint.caps.type_iso = true;
1814                         dep->endpoint.caps.type_bulk = true;
1815                         dep->endpoint.caps.type_int = true;
1816                 }
1817
1818                 dep->endpoint.caps.dir_in = !!direction;
1819                 dep->endpoint.caps.dir_out = !direction;
1820
1821                 INIT_LIST_HEAD(&dep->request_list);
1822                 INIT_LIST_HEAD(&dep->req_queued);
1823         }
1824
1825         return 0;
1826 }
1827
1828 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1829 {
1830         int                             ret;
1831
1832         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1833
1834         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1835         if (ret < 0) {
1836                 dwc3_trace(trace_dwc3_gadget,
1837                                 "failed to allocate OUT endpoints");
1838                 return ret;
1839         }
1840
1841         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1842         if (ret < 0) {
1843                 dwc3_trace(trace_dwc3_gadget,
1844                                 "failed to allocate IN endpoints");
1845                 return ret;
1846         }
1847
1848         return 0;
1849 }
1850
1851 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1852 {
1853         struct dwc3_ep                  *dep;
1854         u8                              epnum;
1855
1856         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1857                 dep = dwc->eps[epnum];
1858                 if (!dep)
1859                         continue;
1860                 /*
1861                  * Physical endpoints 0 and 1 are special; they form the
1862                  * bi-directional USB endpoint 0.
1863                  *
1864                  * For those two physical endpoints, we don't allocate a TRB
1865                  * pool nor do we add them the endpoints list. Due to that, we
1866                  * shouldn't do these two operations otherwise we would end up
1867                  * with all sorts of bugs when removing dwc3.ko.
1868                  */
1869                 if (epnum != 0 && epnum != 1) {
1870                         dwc3_free_trb_pool(dep);
1871                         list_del(&dep->endpoint.ep_list);
1872                 }
1873
1874                 kfree(dep);
1875         }
1876 }
1877
1878 /* -------------------------------------------------------------------------- */
1879
1880 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1881                 struct dwc3_request *req, struct dwc3_trb *trb,
1882                 const struct dwc3_event_depevt *event, int status)
1883 {
1884         unsigned int            count;
1885         unsigned int            s_pkt = 0;
1886         unsigned int            trb_status;
1887
1888         trace_dwc3_complete_trb(dep, trb);
1889
1890         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1891                 /*
1892                  * We continue despite the error. There is not much we
1893                  * can do. If we don't clean it up we loop forever. If
1894                  * we skip the TRB then it gets overwritten after a
1895                  * while since we use them in a ring buffer. A BUG()
1896                  * would help. Lets hope that if this occurs, someone
1897                  * fixes the root cause instead of looking away :)
1898                  */
1899                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1900                                 dep->name, trb);
1901         count = trb->size & DWC3_TRB_SIZE_MASK;
1902
1903         if (dep->direction) {
1904                 if (count) {
1905                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1906                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1907                                 dwc3_trace(trace_dwc3_gadget,
1908                                                 "%s: incomplete IN transfer\n",
1909                                                 dep->name);
1910                                 /*
1911                                  * If missed isoc occurred and there is
1912                                  * no request queued then issue END
1913                                  * TRANSFER, so that core generates
1914                                  * next xfernotready and we will issue
1915                                  * a fresh START TRANSFER.
1916                                  * If there are still queued request
1917                                  * then wait, do not issue either END
1918                                  * or UPDATE TRANSFER, just attach next
1919                                  * request in request_list during
1920                                  * giveback.If any future queued request
1921                                  * is successfully transferred then we
1922                                  * will issue UPDATE TRANSFER for all
1923                                  * request in the request_list.
1924                                  */
1925                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1926                         } else {
1927                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1928                                                 dep->name);
1929                                 status = -ECONNRESET;
1930                         }
1931                 } else {
1932                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1933                 }
1934         } else {
1935                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1936                         s_pkt = 1;
1937         }
1938
1939         /*
1940          * We assume here we will always receive the entire data block
1941          * which we should receive. Meaning, if we program RX to
1942          * receive 4K but we receive only 2K, we assume that's all we
1943          * should receive and we simply bounce the request back to the
1944          * gadget driver for further processing.
1945          */
1946         req->request.actual += req->request.length - count;
1947         if (s_pkt)
1948                 return 1;
1949         if ((event->status & DEPEVT_STATUS_LST) &&
1950                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1951                                 DWC3_TRB_CTRL_HWO)))
1952                 return 1;
1953         if ((event->status & DEPEVT_STATUS_IOC) &&
1954                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1955                 return 1;
1956         return 0;
1957 }
1958
1959 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1960                 const struct dwc3_event_depevt *event, int status)
1961 {
1962         struct dwc3_request     *req;
1963         struct dwc3_trb         *trb;
1964         unsigned int            slot;
1965         unsigned int            i;
1966         int                     ret;
1967
1968         do {
1969                 req = next_request(&dep->req_queued);
1970                 if (WARN_ON_ONCE(!req))
1971                         return 1;
1972
1973                 i = 0;
1974                 do {
1975                         slot = req->start_slot + i;
1976                         if ((slot == DWC3_TRB_NUM - 1) &&
1977                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1978                                 slot++;
1979                         slot %= DWC3_TRB_NUM;
1980                         trb = &dep->trb_pool[slot];
1981
1982                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1983                                         event, status);
1984                         if (ret)
1985                                 break;
1986                 } while (++i < req->request.num_mapped_sgs);
1987
1988                 dwc3_gadget_giveback(dep, req, status);
1989
1990                 if (ret)
1991                         break;
1992         } while (1);
1993
1994         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1995                         list_empty(&dep->req_queued)) {
1996                 if (list_empty(&dep->request_list)) {
1997                         /*
1998                          * If there is no entry in request list then do
1999                          * not issue END TRANSFER now. Just set PENDING
2000                          * flag, so that END TRANSFER is issued when an
2001                          * entry is added into request list.
2002                          */
2003                         dep->flags = DWC3_EP_PENDING_REQUEST;
2004                 } else {
2005                         dwc3_stop_active_transfer(dwc, dep->number, true);
2006                         dep->flags = DWC3_EP_ENABLED;
2007                 }
2008                 return 1;
2009         }
2010
2011         return 1;
2012 }
2013
2014 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2015                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2016 {
2017         unsigned                status = 0;
2018         int                     clean_busy;
2019         u32                     is_xfer_complete;
2020
2021         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2022
2023         if (event->status & DEPEVT_STATUS_BUSERR)
2024                 status = -ECONNRESET;
2025
2026         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2027         if (clean_busy && (is_xfer_complete ||
2028                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2029                 dep->flags &= ~DWC3_EP_BUSY;
2030
2031         /*
2032          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2033          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2034          */
2035         if (dwc->revision < DWC3_REVISION_183A) {
2036                 u32             reg;
2037                 int             i;
2038
2039                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2040                         dep = dwc->eps[i];
2041
2042                         if (!(dep->flags & DWC3_EP_ENABLED))
2043                                 continue;
2044
2045                         if (!list_empty(&dep->req_queued))
2046                                 return;
2047                 }
2048
2049                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2050                 reg |= dwc->u1u2;
2051                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2052
2053                 dwc->u1u2 = 0;
2054         }
2055
2056         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2057                 int ret;
2058
2059                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2060                 if (!ret || ret == -EBUSY)
2061                         return;
2062         }
2063 }
2064
2065 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2066                 const struct dwc3_event_depevt *event)
2067 {
2068         struct dwc3_ep          *dep;
2069         u8                      epnum = event->endpoint_number;
2070
2071         dep = dwc->eps[epnum];
2072
2073         if (!(dep->flags & DWC3_EP_ENABLED))
2074                 return;
2075
2076         if (epnum == 0 || epnum == 1) {
2077                 dwc3_ep0_interrupt(dwc, event);
2078                 return;
2079         }
2080
2081         switch (event->endpoint_event) {
2082         case DWC3_DEPEVT_XFERCOMPLETE:
2083                 dep->resource_index = 0;
2084
2085                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2086                         dwc3_trace(trace_dwc3_gadget,
2087                                         "%s is an Isochronous endpoint\n",
2088                                         dep->name);
2089                         return;
2090                 }
2091
2092                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2093                 break;
2094         case DWC3_DEPEVT_XFERINPROGRESS:
2095                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2096                 break;
2097         case DWC3_DEPEVT_XFERNOTREADY:
2098                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2099                         dwc3_gadget_start_isoc(dwc, dep, event);
2100                 } else {
2101                         int active;
2102                         int ret;
2103
2104                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2105
2106                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2107                                         dep->name, active ? "Transfer Active"
2108                                         : "Transfer Not Active");
2109
2110                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2111                         if (!ret || ret == -EBUSY)
2112                                 return;
2113
2114                         dwc3_trace(trace_dwc3_gadget,
2115                                         "%s: failed to kick transfers\n",
2116                                         dep->name);
2117                 }
2118
2119                 break;
2120         case DWC3_DEPEVT_STREAMEVT:
2121                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2122                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2123                                         dep->name);
2124                         return;
2125                 }
2126
2127                 switch (event->status) {
2128                 case DEPEVT_STREAMEVT_FOUND:
2129                         dwc3_trace(trace_dwc3_gadget,
2130                                         "Stream %d found and started",
2131                                         event->parameters);
2132
2133                         break;
2134                 case DEPEVT_STREAMEVT_NOTFOUND:
2135                         /* FALLTHROUGH */
2136                 default:
2137                         dwc3_trace(trace_dwc3_gadget,
2138                                         "unable to find suitable stream\n");
2139                 }
2140                 break;
2141         case DWC3_DEPEVT_RXTXFIFOEVT:
2142                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2143                 break;
2144         case DWC3_DEPEVT_EPCMDCMPLT:
2145                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2146                 break;
2147         }
2148 }
2149
2150 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2151 {
2152         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2153                 spin_unlock(&dwc->lock);
2154                 dwc->gadget_driver->disconnect(&dwc->gadget);
2155                 spin_lock(&dwc->lock);
2156         }
2157 }
2158
2159 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2160 {
2161         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2162                 spin_unlock(&dwc->lock);
2163                 dwc->gadget_driver->suspend(&dwc->gadget);
2164                 spin_lock(&dwc->lock);
2165         }
2166 }
2167
2168 static void dwc3_resume_gadget(struct dwc3 *dwc)
2169 {
2170         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2171                 spin_unlock(&dwc->lock);
2172                 dwc->gadget_driver->resume(&dwc->gadget);
2173                 spin_lock(&dwc->lock);
2174         }
2175 }
2176
2177 static void dwc3_reset_gadget(struct dwc3 *dwc)
2178 {
2179         if (!dwc->gadget_driver)
2180                 return;
2181
2182         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2183                 spin_unlock(&dwc->lock);
2184                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2185                 spin_lock(&dwc->lock);
2186         }
2187 }
2188
2189 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2190 {
2191         struct dwc3_ep *dep;
2192         struct dwc3_gadget_ep_cmd_params params;
2193         u32 cmd;
2194         int ret;
2195
2196         dep = dwc->eps[epnum];
2197
2198         if (!dep->resource_index)
2199                 return;
2200
2201         /*
2202          * NOTICE: We are violating what the Databook says about the
2203          * EndTransfer command. Ideally we would _always_ wait for the
2204          * EndTransfer Command Completion IRQ, but that's causing too
2205          * much trouble synchronizing between us and gadget driver.
2206          *
2207          * We have discussed this with the IP Provider and it was
2208          * suggested to giveback all requests here, but give HW some
2209          * extra time to synchronize with the interconnect. We're using
2210          * an arbitrary 100us delay for that.
2211          *
2212          * Note also that a similar handling was tested by Synopsys
2213          * (thanks a lot Paul) and nothing bad has come out of it.
2214          * In short, what we're doing is:
2215          *
2216          * - Issue EndTransfer WITH CMDIOC bit set
2217          * - Wait 100us
2218          */
2219
2220         cmd = DWC3_DEPCMD_ENDTRANSFER;
2221         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2222         cmd |= DWC3_DEPCMD_CMDIOC;
2223         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2224         memset(&params, 0, sizeof(params));
2225         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2226         WARN_ON_ONCE(ret);
2227         dep->resource_index = 0;
2228         dep->flags &= ~DWC3_EP_BUSY;
2229         udelay(100);
2230 }
2231
2232 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2233 {
2234         u32 epnum;
2235
2236         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2237                 struct dwc3_ep *dep;
2238
2239                 dep = dwc->eps[epnum];
2240                 if (!dep)
2241                         continue;
2242
2243                 if (!(dep->flags & DWC3_EP_ENABLED))
2244                         continue;
2245
2246                 dwc3_remove_requests(dwc, dep);
2247         }
2248 }
2249
2250 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2251 {
2252         u32 epnum;
2253
2254         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2255                 struct dwc3_ep *dep;
2256                 struct dwc3_gadget_ep_cmd_params params;
2257                 int ret;
2258
2259                 dep = dwc->eps[epnum];
2260                 if (!dep)
2261                         continue;
2262
2263                 if (!(dep->flags & DWC3_EP_STALL))
2264                         continue;
2265
2266                 dep->flags &= ~DWC3_EP_STALL;
2267
2268                 memset(&params, 0, sizeof(params));
2269                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2270                                 DWC3_DEPCMD_CLEARSTALL, &params);
2271                 WARN_ON_ONCE(ret);
2272         }
2273 }
2274
2275 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2276 {
2277         int                     reg;
2278
2279         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2280         reg &= ~DWC3_DCTL_INITU1ENA;
2281         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2282
2283         reg &= ~DWC3_DCTL_INITU2ENA;
2284         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2285
2286         dwc3_disconnect_gadget(dwc);
2287
2288         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2289         dwc->setup_packet_pending = false;
2290         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2291 }
2292
2293 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2294 {
2295         u32                     reg;
2296
2297         /*
2298          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2299          * would cause a missing Disconnect Event if there's a
2300          * pending Setup Packet in the FIFO.
2301          *
2302          * There's no suggested workaround on the official Bug
2303          * report, which states that "unless the driver/application
2304          * is doing any special handling of a disconnect event,
2305          * there is no functional issue".
2306          *
2307          * Unfortunately, it turns out that we _do_ some special
2308          * handling of a disconnect event, namely complete all
2309          * pending transfers, notify gadget driver of the
2310          * disconnection, and so on.
2311          *
2312          * Our suggested workaround is to follow the Disconnect
2313          * Event steps here, instead, based on a setup_packet_pending
2314          * flag. Such flag gets set whenever we have a SETUP_PENDING
2315          * status for EP0 TRBs and gets cleared on XferComplete for the
2316          * same endpoint.
2317          *
2318          * Refers to:
2319          *
2320          * STAR#9000466709: RTL: Device : Disconnect event not
2321          * generated if setup packet pending in FIFO
2322          */
2323         if (dwc->revision < DWC3_REVISION_188A) {
2324                 if (dwc->setup_packet_pending)
2325                         dwc3_gadget_disconnect_interrupt(dwc);
2326         }
2327
2328         dwc3_reset_gadget(dwc);
2329
2330         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2331         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2332         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333         dwc->test_mode = false;
2334
2335         dwc3_stop_active_transfers(dwc);
2336         dwc3_clear_stall_all_ep(dwc);
2337
2338         /* Reset device address to zero */
2339         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2340         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2341         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2342 }
2343
2344 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2345 {
2346         u32 reg;
2347         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2348
2349         /*
2350          * We change the clock only at SS but I dunno why I would want to do
2351          * this. Maybe it becomes part of the power saving plan.
2352          */
2353
2354         if (speed != DWC3_DSTS_SUPERSPEED)
2355                 return;
2356
2357         /*
2358          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2359          * each time on Connect Done.
2360          */
2361         if (!usb30_clock)
2362                 return;
2363
2364         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2365         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2366         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2367 }
2368
2369 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2370 {
2371         struct dwc3_ep          *dep;
2372         int                     ret;
2373         u32                     reg;
2374         u8                      speed;
2375
2376         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2377         speed = reg & DWC3_DSTS_CONNECTSPD;
2378         dwc->speed = speed;
2379
2380         dwc3_update_ram_clk_sel(dwc, speed);
2381
2382         switch (speed) {
2383         case DWC3_DCFG_SUPERSPEED:
2384                 /*
2385                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2386                  * would cause a missing USB3 Reset event.
2387                  *
2388                  * In such situations, we should force a USB3 Reset
2389                  * event by calling our dwc3_gadget_reset_interrupt()
2390                  * routine.
2391                  *
2392                  * Refers to:
2393                  *
2394                  * STAR#9000483510: RTL: SS : USB3 reset event may
2395                  * not be generated always when the link enters poll
2396                  */
2397                 if (dwc->revision < DWC3_REVISION_190A)
2398                         dwc3_gadget_reset_interrupt(dwc);
2399
2400                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2401                 dwc->gadget.ep0->maxpacket = 512;
2402                 dwc->gadget.speed = USB_SPEED_SUPER;
2403                 break;
2404         case DWC3_DCFG_HIGHSPEED:
2405                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2406                 dwc->gadget.ep0->maxpacket = 64;
2407                 dwc->gadget.speed = USB_SPEED_HIGH;
2408                 break;
2409         case DWC3_DCFG_FULLSPEED2:
2410         case DWC3_DCFG_FULLSPEED1:
2411                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2412                 dwc->gadget.ep0->maxpacket = 64;
2413                 dwc->gadget.speed = USB_SPEED_FULL;
2414                 break;
2415         case DWC3_DCFG_LOWSPEED:
2416                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2417                 dwc->gadget.ep0->maxpacket = 8;
2418                 dwc->gadget.speed = USB_SPEED_LOW;
2419                 break;
2420         }
2421
2422         /* Enable USB2 LPM Capability */
2423
2424         if ((dwc->revision > DWC3_REVISION_194A)
2425                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2426                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2427                 reg |= DWC3_DCFG_LPM_CAP;
2428                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2429
2430                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2431                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2432
2433                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2434
2435                 /*
2436                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2437                  * DCFG.LPMCap is set, core responses with an ACK and the
2438                  * BESL value in the LPM token is less than or equal to LPM
2439                  * NYET threshold.
2440                  */
2441                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2442                                 && dwc->has_lpm_erratum,
2443                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2444
2445                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2446                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2447
2448                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2449         } else {
2450                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2451                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2452                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2453         }
2454
2455         dep = dwc->eps[0];
2456         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2457                         false);
2458         if (ret) {
2459                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2460                 return;
2461         }
2462
2463         dep = dwc->eps[1];
2464         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2465                         false);
2466         if (ret) {
2467                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2468                 return;
2469         }
2470
2471         /*
2472          * Configure PHY via GUSB3PIPECTLn if required.
2473          *
2474          * Update GTXFIFOSIZn
2475          *
2476          * In both cases reset values should be sufficient.
2477          */
2478 }
2479
2480 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2481 {
2482         /*
2483          * TODO take core out of low power mode when that's
2484          * implemented.
2485          */
2486
2487         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2488                 spin_unlock(&dwc->lock);
2489                 dwc->gadget_driver->resume(&dwc->gadget);
2490                 spin_lock(&dwc->lock);
2491         }
2492 }
2493
2494 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2495                 unsigned int evtinfo)
2496 {
2497         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2498         unsigned int            pwropt;
2499
2500         /*
2501          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2502          * Hibernation mode enabled which would show up when device detects
2503          * host-initiated U3 exit.
2504          *
2505          * In that case, device will generate a Link State Change Interrupt
2506          * from U3 to RESUME which is only necessary if Hibernation is
2507          * configured in.
2508          *
2509          * There are no functional changes due to such spurious event and we
2510          * just need to ignore it.
2511          *
2512          * Refers to:
2513          *
2514          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2515          * operational mode
2516          */
2517         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2518         if ((dwc->revision < DWC3_REVISION_250A) &&
2519                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2520                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2521                                 (next == DWC3_LINK_STATE_RESUME)) {
2522                         dwc3_trace(trace_dwc3_gadget,
2523                                         "ignoring transition U3 -> Resume");
2524                         return;
2525                 }
2526         }
2527
2528         /*
2529          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2530          * on the link partner, the USB session might do multiple entry/exit
2531          * of low power states before a transfer takes place.
2532          *
2533          * Due to this problem, we might experience lower throughput. The
2534          * suggested workaround is to disable DCTL[12:9] bits if we're
2535          * transitioning from U1/U2 to U0 and enable those bits again
2536          * after a transfer completes and there are no pending transfers
2537          * on any of the enabled endpoints.
2538          *
2539          * This is the first half of that workaround.
2540          *
2541          * Refers to:
2542          *
2543          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2544          * core send LGO_Ux entering U0
2545          */
2546         if (dwc->revision < DWC3_REVISION_183A) {
2547                 if (next == DWC3_LINK_STATE_U0) {
2548                         u32     u1u2;
2549                         u32     reg;
2550
2551                         switch (dwc->link_state) {
2552                         case DWC3_LINK_STATE_U1:
2553                         case DWC3_LINK_STATE_U2:
2554                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2555                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2556                                                 | DWC3_DCTL_ACCEPTU2ENA
2557                                                 | DWC3_DCTL_INITU1ENA
2558                                                 | DWC3_DCTL_ACCEPTU1ENA);
2559
2560                                 if (!dwc->u1u2)
2561                                         dwc->u1u2 = reg & u1u2;
2562
2563                                 reg &= ~u1u2;
2564
2565                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2566                                 break;
2567                         default:
2568                                 /* do nothing */
2569                                 break;
2570                         }
2571                 }
2572         }
2573
2574         switch (next) {
2575         case DWC3_LINK_STATE_U1:
2576                 if (dwc->speed == USB_SPEED_SUPER)
2577                         dwc3_suspend_gadget(dwc);
2578                 break;
2579         case DWC3_LINK_STATE_U2:
2580         case DWC3_LINK_STATE_U3:
2581                 dwc3_suspend_gadget(dwc);
2582                 break;
2583         case DWC3_LINK_STATE_RESUME:
2584                 dwc3_resume_gadget(dwc);
2585                 break;
2586         default:
2587                 /* do nothing */
2588                 break;
2589         }
2590
2591         dwc->link_state = next;
2592 }
2593
2594 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2595                 unsigned int evtinfo)
2596 {
2597         unsigned int is_ss = evtinfo & BIT(4);
2598
2599         /**
2600          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2601          * have a known issue which can cause USB CV TD.9.23 to fail
2602          * randomly.
2603          *
2604          * Because of this issue, core could generate bogus hibernation
2605          * events which SW needs to ignore.
2606          *
2607          * Refers to:
2608          *
2609          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2610          * Device Fallback from SuperSpeed
2611          */
2612         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2613                 return;
2614
2615         /* enter hibernation here */
2616 }
2617
2618 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2619                 const struct dwc3_event_devt *event)
2620 {
2621         switch (event->type) {
2622         case DWC3_DEVICE_EVENT_DISCONNECT:
2623                 dwc3_gadget_disconnect_interrupt(dwc);
2624                 break;
2625         case DWC3_DEVICE_EVENT_RESET:
2626                 dwc3_gadget_reset_interrupt(dwc);
2627                 break;
2628         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2629                 dwc3_gadget_conndone_interrupt(dwc);
2630                 break;
2631         case DWC3_DEVICE_EVENT_WAKEUP:
2632                 dwc3_gadget_wakeup_interrupt(dwc);
2633                 break;
2634         case DWC3_DEVICE_EVENT_HIBER_REQ:
2635                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2636                                         "unexpected hibernation event\n"))
2637                         break;
2638
2639                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2640                 break;
2641         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2642                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2643                 break;
2644         case DWC3_DEVICE_EVENT_EOPF:
2645                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2646                 break;
2647         case DWC3_DEVICE_EVENT_SOF:
2648                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2649                 break;
2650         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2651                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2652                 break;
2653         case DWC3_DEVICE_EVENT_CMD_CMPL:
2654                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2655                 break;
2656         case DWC3_DEVICE_EVENT_OVERFLOW:
2657                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2658                 break;
2659         default:
2660                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2661         }
2662 }
2663
2664 static void dwc3_process_event_entry(struct dwc3 *dwc,
2665                 const union dwc3_event *event)
2666 {
2667         trace_dwc3_event(event->raw);
2668
2669         /* Endpoint IRQ, handle it and return early */
2670         if (event->type.is_devspec == 0) {
2671                 /* depevt */
2672                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2673         }
2674
2675         switch (event->type.type) {
2676         case DWC3_EVENT_TYPE_DEV:
2677                 dwc3_gadget_interrupt(dwc, &event->devt);
2678                 break;
2679         /* REVISIT what to do with Carkit and I2C events ? */
2680         default:
2681                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2682         }
2683 }
2684
2685 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2686 {
2687         struct dwc3_event_buffer *evt;
2688         irqreturn_t ret = IRQ_NONE;
2689         int left;
2690         u32 reg;
2691
2692         evt = dwc->ev_buffs[buf];
2693         left = evt->count;
2694
2695         if (!(evt->flags & DWC3_EVENT_PENDING))
2696                 return IRQ_NONE;
2697
2698         while (left > 0) {
2699                 union dwc3_event event;
2700
2701                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2702
2703                 dwc3_process_event_entry(dwc, &event);
2704
2705                 /*
2706                  * FIXME we wrap around correctly to the next entry as
2707                  * almost all entries are 4 bytes in size. There is one
2708                  * entry which has 12 bytes which is a regular entry
2709                  * followed by 8 bytes data. ATM I don't know how
2710                  * things are organized if we get next to the a
2711                  * boundary so I worry about that once we try to handle
2712                  * that.
2713                  */
2714                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2715                 left -= 4;
2716
2717                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2718         }
2719
2720         evt->count = 0;
2721         evt->flags &= ~DWC3_EVENT_PENDING;
2722         ret = IRQ_HANDLED;
2723
2724         /* Unmask interrupt */
2725         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2726         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2727         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2728
2729         return ret;
2730 }
2731
2732 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2733 {
2734         struct dwc3 *dwc = _dwc;
2735         unsigned long flags;
2736         irqreturn_t ret = IRQ_NONE;
2737         int i;
2738
2739         spin_lock_irqsave(&dwc->lock, flags);
2740
2741         for (i = 0; i < dwc->num_event_buffers; i++)
2742                 ret |= dwc3_process_event_buf(dwc, i);
2743
2744         spin_unlock_irqrestore(&dwc->lock, flags);
2745
2746         return ret;
2747 }
2748
2749 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2750 {
2751         struct dwc3_event_buffer *evt;
2752         u32 count;
2753         u32 reg;
2754
2755         evt = dwc->ev_buffs[buf];
2756
2757         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2758         count &= DWC3_GEVNTCOUNT_MASK;
2759         if (!count)
2760                 return IRQ_NONE;
2761
2762         evt->count = count;
2763         evt->flags |= DWC3_EVENT_PENDING;
2764
2765         /* Mask interrupt */
2766         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2767         reg |= DWC3_GEVNTSIZ_INTMASK;
2768         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2769
2770         return IRQ_WAKE_THREAD;
2771 }
2772
2773 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2774 {
2775         struct dwc3                     *dwc = _dwc;
2776         int                             i;
2777         irqreturn_t                     ret = IRQ_NONE;
2778
2779         for (i = 0; i < dwc->num_event_buffers; i++) {
2780                 irqreturn_t status;
2781
2782                 status = dwc3_check_event_buf(dwc, i);
2783                 if (status == IRQ_WAKE_THREAD)
2784                         ret = status;
2785         }
2786
2787         return ret;
2788 }
2789
2790 /**
2791  * dwc3_gadget_init - Initializes gadget related registers
2792  * @dwc: pointer to our controller context structure
2793  *
2794  * Returns 0 on success otherwise negative errno.
2795  */
2796 int dwc3_gadget_init(struct dwc3 *dwc)
2797 {
2798         int                                     ret;
2799
2800         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2801                         &dwc->ctrl_req_addr, GFP_KERNEL);
2802         if (!dwc->ctrl_req) {
2803                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2804                 ret = -ENOMEM;
2805                 goto err0;
2806         }
2807
2808         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2809                         &dwc->ep0_trb_addr, GFP_KERNEL);
2810         if (!dwc->ep0_trb) {
2811                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2812                 ret = -ENOMEM;
2813                 goto err1;
2814         }
2815
2816         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2817         if (!dwc->setup_buf) {
2818                 ret = -ENOMEM;
2819                 goto err2;
2820         }
2821
2822         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2823                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2824                         GFP_KERNEL);
2825         if (!dwc->ep0_bounce) {
2826                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2827                 ret = -ENOMEM;
2828                 goto err3;
2829         }
2830
2831         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2832         if (!dwc->zlp_buf) {
2833                 ret = -ENOMEM;
2834                 goto err4;
2835         }
2836
2837         dwc->gadget.ops                 = &dwc3_gadget_ops;
2838         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2839         dwc->gadget.sg_supported        = true;
2840         dwc->gadget.name                = "dwc3-gadget";
2841         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2842
2843         /*
2844          * FIXME We might be setting max_speed to <SUPER, however versions
2845          * <2.20a of dwc3 have an issue with metastability (documented
2846          * elsewhere in this driver) which tells us we can't set max speed to
2847          * anything lower than SUPER.
2848          *
2849          * Because gadget.max_speed is only used by composite.c and function
2850          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2851          * to happen so we avoid sending SuperSpeed Capability descriptor
2852          * together with our BOS descriptor as that could confuse host into
2853          * thinking we can handle super speed.
2854          *
2855          * Note that, in fact, we won't even support GetBOS requests when speed
2856          * is less than super speed because we don't have means, yet, to tell
2857          * composite.c that we are USB 2.0 + LPM ECN.
2858          */
2859         if (dwc->revision < DWC3_REVISION_220A)
2860                 dwc3_trace(trace_dwc3_gadget,
2861                                 "Changing max_speed on rev %08x\n",
2862                                 dwc->revision);
2863
2864         dwc->gadget.max_speed           = dwc->maximum_speed;
2865
2866         /*
2867          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2868          * on ep out.
2869          */
2870         dwc->gadget.quirk_ep_out_aligned_size = true;
2871
2872         /*
2873          * REVISIT: Here we should clear all pending IRQs to be
2874          * sure we're starting from a well known location.
2875          */
2876
2877         ret = dwc3_gadget_init_endpoints(dwc);
2878         if (ret)
2879                 goto err5;
2880
2881         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2882         if (ret) {
2883                 dev_err(dwc->dev, "failed to register udc\n");
2884                 goto err5;
2885         }
2886
2887         return 0;
2888
2889 err5:
2890         kfree(dwc->zlp_buf);
2891
2892 err4:
2893         dwc3_gadget_free_endpoints(dwc);
2894         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2895                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2896
2897 err3:
2898         kfree(dwc->setup_buf);
2899
2900 err2:
2901         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2902                         dwc->ep0_trb, dwc->ep0_trb_addr);
2903
2904 err1:
2905         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2906                         dwc->ctrl_req, dwc->ctrl_req_addr);
2907
2908 err0:
2909         return ret;
2910 }
2911
2912 /* -------------------------------------------------------------------------- */
2913
2914 void dwc3_gadget_exit(struct dwc3 *dwc)
2915 {
2916         usb_del_gadget_udc(&dwc->gadget);
2917
2918         dwc3_gadget_free_endpoints(dwc);
2919
2920         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2921                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2922
2923         kfree(dwc->setup_buf);
2924         kfree(dwc->zlp_buf);
2925
2926         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2927                         dwc->ep0_trb, dwc->ep0_trb_addr);
2928
2929         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2930                         dwc->ctrl_req, dwc->ctrl_req_addr);
2931 }
2932
2933 int dwc3_gadget_suspend(struct dwc3 *dwc)
2934 {
2935         if (dwc->pullups_connected) {
2936                 dwc3_gadget_disable_irq(dwc);
2937                 dwc3_gadget_run_stop(dwc, true, true);
2938         }
2939
2940         __dwc3_gadget_ep_disable(dwc->eps[0]);
2941         __dwc3_gadget_ep_disable(dwc->eps[1]);
2942
2943         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2944
2945         return 0;
2946 }
2947
2948 int dwc3_gadget_resume(struct dwc3 *dwc)
2949 {
2950         struct dwc3_ep          *dep;
2951         int                     ret;
2952
2953         /* Start with SuperSpeed Default */
2954         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2955
2956         dep = dwc->eps[0];
2957         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2958                         false);
2959         if (ret)
2960                 goto err0;
2961
2962         dep = dwc->eps[1];
2963         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2964                         false);
2965         if (ret)
2966                 goto err1;
2967
2968         /* begin to receive SETUP packets */
2969         dwc->ep0state = EP0_SETUP_PHASE;
2970         dwc3_ep0_out_start(dwc);
2971
2972         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2973
2974         if (dwc->pullups_connected) {
2975                 dwc3_gadget_enable_irq(dwc);
2976                 dwc3_gadget_run_stop(dwc, true, false);
2977         }
2978
2979         return 0;
2980
2981 err1:
2982         __dwc3_gadget_ep_disable(dwc->eps[0]);
2983
2984 err0:
2985         return ret;
2986 }