drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue))
 181                                 dwc3_ep_inc_deq(dep);
 182                 } while(++i < req->request.num_mapped_sgs);
 183                 req->started = false;
 184         }
 185         list_del(&req->list);
 186         req->trb = NULL;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (dwc->ep0_bounced && dep->number == 0)
 192                 dwc->ep0_bounced = false;
 193         else
 194                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 195                                 req->direction);
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202 }
 203
 204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 205 {
 206         u32             timeout = 500;
 207         u32             reg;
 208
 209         trace_dwc3_gadget_generic_cmd(cmd, param);
 210
 211         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 212         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 213
 214         do {
 215                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 216                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 217                         dwc3_trace(trace_dwc3_gadget,
 218                                         "Command Complete --> %d",
 219                                         DWC3_DGCMD_STATUS(reg));
 220                         if (DWC3_DGCMD_STATUS(reg))
 221                                 return -EINVAL;
 222                         return 0;
 223                 }
 224
 225                 /*
 226                  * We can't sleep here, because it's also called from
 227                  * interrupt context.
 228                  */
 229                 timeout--;
 230                 if (!timeout) {
 231                         dwc3_trace(trace_dwc3_gadget,
 232                                         "Command Timed Out");
 233                         return -ETIMEDOUT;
 234                 }
 235                 udelay(1);
 236         } while (1);
 237 }
 238
 239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 240
 241 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 242                 struct dwc3_gadget_ep_cmd_params *params)
 243 {
 244         struct dwc3             *dwc = dep->dwc;
 245         u32                     timeout = 500;
 246         u32                     reg;
 247
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 252
 253         /*
 254          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 255          * we're issuing an endpoint command, we must check if
 256          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 257          *
 258          * We will also set SUSPHY bit to what it was before returning as stated
 259          * by the same section on Synopsys databook.
 260          */
 261         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 262         if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 263                 susphy = true;
 264                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 265                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 283         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 285
 286         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         int cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         dwc3_trace(trace_dwc3_gadget,
 293                                         "Command Complete --> %d",
 294                                         cmd_status);
 295
 296                         switch (cmd_status) {
 297                         case 0:
 298                                 ret = 0;
 299                                 break;
 300                         case DEPEVT_TRANSFER_NO_RESOURCE:
 301                                 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
 302                                 ret = -EINVAL;
 303                                 break;
 304                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 305                                 /*
 306                                  * SW issues START TRANSFER command to
 307                                  * isochronous ep with future frame interval. If
 308                                  * future interval time has already passed when
 309                                  * core receives the command, it will respond
 310                                  * with an error status of 'Bus Expiry'.
 311                                  *
 312                                  * Instead of always returning -EINVAL, let's
 313                                  * give a hint to the gadget driver that this is
 314                                  * the case by returning -EAGAIN.
 315                                  */
 316                                 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
 317                                 ret = -EAGAIN;
 318                                 break;
 319                         default:
 320                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 321                         }
 322
 323                         break;
 324                 }
 325
 326                 /*
 327                  * We can't sleep here, because it is also called from
 328                  * interrupt context.
 329                  */
 330                 timeout--;
 331                 if (!timeout) {
 332                         dwc3_trace(trace_dwc3_gadget,
 333                                         "Command Timed Out");
 334                         ret = -ETIMEDOUT;
 335                         break;
 336                 }
 337         } while (1);
 338
 339         if (unlikely(susphy)) {
 340                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 341                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 342                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 343         }
 344
 345         return ret;
 346 }
 347
 348 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 349 {
 350         struct dwc3 *dwc = dep->dwc;
 351         struct dwc3_gadget_ep_cmd_params params;
 352         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 353
 354         /*
 355          * As of core revision 2.60a the recommended programming model
 356          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 357          * command for IN endpoints. This is to prevent an issue where
 358          * some (non-compliant) hosts may not send ACK TPs for pending
 359          * IN transfers due to a mishandled error condition. Synopsys
 360          * STAR 9000614252.
 361          */
 362         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 363                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 364
 365         memset(&params, 0, sizeof(params));
 366
 367         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 368 }
 369
 370 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 371                 struct dwc3_trb *trb)
 372 {
 373         u32             offset = (char *) trb - (char *) dep->trb_pool;
 374
 375         return dep->trb_pool_dma + offset;
 376 }
 377
 378 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 379 {
 380         struct dwc3             *dwc = dep->dwc;
 381
 382         if (dep->trb_pool)
 383                 return 0;
 384
 385         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 386                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 387                         &dep->trb_pool_dma, GFP_KERNEL);
 388         if (!dep->trb_pool) {
 389                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 390                                 dep->name);
 391                 return -ENOMEM;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 398 {
 399         struct dwc3             *dwc = dep->dwc;
 400
 401         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 402                         dep->trb_pool, dep->trb_pool_dma);
 403
 404         dep->trb_pool = NULL;
 405         dep->trb_pool_dma = 0;
 406 }
 407
 408 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 409
 410 /**
 411  * dwc3_gadget_start_config - Configure EP resources
 412  * @dwc: pointer to our controller context structure
 413  * @dep: endpoint that is being enabled
 414  *
 415  * The assignment of transfer resources cannot perfectly follow the
 416  * data book due to the fact that the controller driver does not have
 417  * all knowledge of the configuration in advance. It is given this
 418  * information piecemeal by the composite gadget framework after every
 419  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 420  * programming model in this scenario can cause errors. For two
 421  * reasons:
 422  *
 423  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 424  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 425  * multiple interfaces.
 426  *
 427  * 2) The databook does not mention doing more DEPXFERCFG for new
 428  * endpoint on alt setting (8.1.6).
 429  *
 430  * The following simplified method is used instead:
 431  *
 432  * All hardware endpoints can be assigned a transfer resource and this
 433  * setting will stay persistent until either a core reset or
 434  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 435  * do DEPXFERCFG for every hardware endpoint as well. We are
 436  * guaranteed that there are as many transfer resources as endpoints.
 437  *
 438  * This function is called for each endpoint when it is being enabled
 439  * but is triggered only when called for EP0-out, which always happens
 440  * first, and which should only happen in one of the above conditions.
 441  */
 442 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 443 {
 444         struct dwc3_gadget_ep_cmd_params params;
 445         u32                     cmd;
 446         int                     i;
 447         int                     ret;
 448
 449         if (dep->number)
 450                 return 0;
 451
 452         memset(&params, 0x00, sizeof(params));
 453         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 454
 455         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 456         if (ret)
 457                 return ret;
 458
 459         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 460                 struct dwc3_ep *dep = dwc->eps[i];
 461
 462                 if (!dep)
 463                         continue;
 464
 465                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 466                 if (ret)
 467                         return ret;
 468         }
 469
 470         return 0;
 471 }
 472
 473 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 474                 const struct usb_endpoint_descriptor *desc,
 475                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 476                 bool ignore, bool restore)
 477 {
 478         struct dwc3_gadget_ep_cmd_params params;
 479
 480         memset(&params, 0x00, sizeof(params));
 481
 482         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 483                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 484
 485         /* Burst size is only needed in SuperSpeed mode */
 486         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 487                 u32 burst = dep->endpoint.maxburst;
 488                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 489         }
 490
 491         if (ignore)
 492                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 493
 494         if (restore) {
 495                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 496                 params.param2 |= dep->saved_state;
 497         }
 498
 499         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 500                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 501
 502         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 503                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 504                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 505                 dep->stream_capable = true;
 506         }
 507
 508         if (!usb_endpoint_xfer_control(desc))
 509                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 510
 511         /*
 512          * We are doing 1:1 mapping for endpoints, meaning
 513          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 514          * so on. We consider the direction bit as part of the physical
 515          * endpoint number. So USB endpoint 0x81 is 0x03.
 516          */
 517         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 518
 519         /*
 520          * We must use the lower 16 TX FIFOs even though
 521          * HW might have more
 522          */
 523         if (dep->direction)
 524                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 525
 526         if (desc->bInterval) {
 527                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 528                 dep->interval = 1 << (desc->bInterval - 1);
 529         }
 530
 531         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 532 }
 533
 534 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 535 {
 536         struct dwc3_gadget_ep_cmd_params params;
 537
 538         memset(&params, 0x00, sizeof(params));
 539
 540         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 541
 542         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 543                         &params);
 544 }
 545
 546 /**
 547  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 548  * @dep: endpoint to be initialized
 549  * @desc: USB Endpoint Descriptor
 550  *
 551  * Caller should take care of locking
 552  */
 553 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 554                 const struct usb_endpoint_descriptor *desc,
 555                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 556                 bool ignore, bool restore)
 557 {
 558         struct dwc3             *dwc = dep->dwc;
 559         u32                     reg;
 560         int                     ret;
 561
 562         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 563
 564         if (!(dep->flags & DWC3_EP_ENABLED)) {
 565                 ret = dwc3_gadget_start_config(dwc, dep);
 566                 if (ret)
 567                         return ret;
 568         }
 569
 570         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 571                         restore);
 572         if (ret)
 573                 return ret;
 574
 575         if (!(dep->flags & DWC3_EP_ENABLED)) {
 576                 struct dwc3_trb *trb_st_hw;
 577                 struct dwc3_trb *trb_link;
 578
 579                 dep->endpoint.desc = desc;
 580                 dep->comp_desc = comp_desc;
 581                 dep->type = usb_endpoint_type(desc);
 582                 dep->flags |= DWC3_EP_ENABLED;
 583
 584                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 585                 reg |= DWC3_DALEPENA_EP(dep->number);
 586                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 587
 588                 if (usb_endpoint_xfer_control(desc))
 589                         goto out;
 590
 591                 /* Link TRB. The HWO bit is never reset */
 592                 trb_st_hw = &dep->trb_pool[0];
 593
 594                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 595                 memset(trb_link, 0, sizeof(*trb_link));
 596
 597                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 598                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 599                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 600                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 601         }
 602
 603 out:
 604         switch (usb_endpoint_type(desc)) {
 605         case USB_ENDPOINT_XFER_CONTROL:
 606                 /* don't change name */
 607                 break;
 608         case USB_ENDPOINT_XFER_ISOC:
 609                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 610                 break;
 611         case USB_ENDPOINT_XFER_BULK:
 612                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 613                 break;
 614         case USB_ENDPOINT_XFER_INT:
 615                 strlcat(dep->name, "-int", sizeof(dep->name));
 616                 break;
 617         default:
 618                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 619         }
 620
 621         return 0;
 622 }
 623
 624 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 625 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 626 {
 627         struct dwc3_request             *req;
 628
 629         if (!list_empty(&dep->started_list)) {
 630                 dwc3_stop_active_transfer(dwc, dep->number, true);
 631
 632                 /* - giveback all requests to gadget driver */
 633                 while (!list_empty(&dep->started_list)) {
 634                         req = next_request(&dep->started_list);
 635
 636                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 637                 }
 638         }
 639
 640         while (!list_empty(&dep->pending_list)) {
 641                 req = next_request(&dep->pending_list);
 642
 643                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 644         }
 645 }
 646
 647 /**
 648  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 649  * @dep: the endpoint to disable
 650  *
 651  * This function also removes requests which are currently processed ny the
 652  * hardware and those which are not yet scheduled.
 653  * Caller should take care of locking.
 654  */
 655 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 656 {
 657         struct dwc3             *dwc = dep->dwc;
 658         u32                     reg;
 659
 660         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 661
 662         dwc3_remove_requests(dwc, dep);
 663
 664         /* make sure HW endpoint isn't stalled */
 665         if (dep->flags & DWC3_EP_STALL)
 666                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 667
 668         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 669         reg &= ~DWC3_DALEPENA_EP(dep->number);
 670         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 671
 672         dep->stream_capable = false;
 673         dep->endpoint.desc = NULL;
 674         dep->comp_desc = NULL;
 675         dep->type = 0;
 676         dep->flags = 0;
 677
 678         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 679                         dep->number >> 1,
 680                         (dep->number & 1) ? "in" : "out");
 681
 682         return 0;
 683 }
 684
 685 /* -------------------------------------------------------------------------- */
 686
 687 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 688                 const struct usb_endpoint_descriptor *desc)
 689 {
 690         return -EINVAL;
 691 }
 692
 693 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 694 {
 695         return -EINVAL;
 696 }
 697
 698 /* -------------------------------------------------------------------------- */
 699
 700 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 701                 const struct usb_endpoint_descriptor *desc)
 702 {
 703         struct dwc3_ep                  *dep;
 704         struct dwc3                     *dwc;
 705         unsigned long                   flags;
 706         int                             ret;
 707
 708         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 709                 pr_debug("dwc3: invalid parameters\n");
 710                 return -EINVAL;
 711         }
 712
 713         if (!desc->wMaxPacketSize) {
 714                 pr_debug("dwc3: missing wMaxPacketSize\n");
 715                 return -EINVAL;
 716         }
 717
 718         dep = to_dwc3_ep(ep);
 719         dwc = dep->dwc;
 720
 721         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 722                                         "%s is already enabled\n",
 723                                         dep->name))
 724                 return 0;
 725
 726         spin_lock_irqsave(&dwc->lock, flags);
 727         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 728         spin_unlock_irqrestore(&dwc->lock, flags);
 729
 730         return ret;
 731 }
 732
 733 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 734 {
 735         struct dwc3_ep                  *dep;
 736         struct dwc3                     *dwc;
 737         unsigned long                   flags;
 738         int                             ret;
 739
 740         if (!ep) {
 741                 pr_debug("dwc3: invalid parameters\n");
 742                 return -EINVAL;
 743         }
 744
 745         dep = to_dwc3_ep(ep);
 746         dwc = dep->dwc;
 747
 748         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 749                                         "%s is already disabled\n",
 750                                         dep->name))
 751                 return 0;
 752
 753         spin_lock_irqsave(&dwc->lock, flags);
 754         ret = __dwc3_gadget_ep_disable(dep);
 755         spin_unlock_irqrestore(&dwc->lock, flags);
 756
 757         return ret;
 758 }
 759
 760 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 761         gfp_t gfp_flags)
 762 {
 763         struct dwc3_request             *req;
 764         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 765
 766         req = kzalloc(sizeof(*req), gfp_flags);
 767         if (!req)
 768                 return NULL;
 769
 770         req->epnum      = dep->number;
 771         req->dep        = dep;
 772
 773         trace_dwc3_alloc_request(req);
 774
 775         return &req->request;
 776 }
 777
 778 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 779                 struct usb_request *request)
 780 {
 781         struct dwc3_request             *req = to_dwc3_request(request);
 782
 783         trace_dwc3_free_request(req);
 784         kfree(req);
 785 }
 786
 787 /**
 788  * dwc3_prepare_one_trb - setup one TRB from one request
 789  * @dep: endpoint for which this request is prepared
 790  * @req: dwc3_request pointer
 791  */
 792 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 793                 struct dwc3_request *req, dma_addr_t dma,
 794                 unsigned length, unsigned last, unsigned chain, unsigned node)
 795 {
 796         struct dwc3_trb         *trb;
 797
 798         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 799                         dep->name, req, (unsigned long long) dma,
 800                         length, last ? " last" : "",
 801                         chain ? " chain" : "");
 802
 803
 804         trb = &dep->trb_pool[dep->trb_enqueue];
 805
 806         if (!req->trb) {
 807                 dwc3_gadget_move_started_request(req);
 808                 req->trb = trb;
 809                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 810                 req->first_trb_index = dep->trb_enqueue;
 811         }
 812
 813         dwc3_ep_inc_enq(dep);
 814         /* Skip the LINK-TRB */
 815         if (dwc3_ep_is_last_trb(dep->trb_enqueue))
 816                 dwc3_ep_inc_enq(dep);
 817
 818         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 819         trb->bpl = lower_32_bits(dma);
 820         trb->bph = upper_32_bits(dma);
 821
 822         switch (usb_endpoint_type(dep->endpoint.desc)) {
 823         case USB_ENDPOINT_XFER_CONTROL:
 824                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 825                 break;
 826
 827         case USB_ENDPOINT_XFER_ISOC:
 828                 if (!node)
 829                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 830                 else
 831                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 832
 833                 /* always enable Interrupt on Missed ISOC */
 834                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 835                 break;
 836
 837         case USB_ENDPOINT_XFER_BULK:
 838         case USB_ENDPOINT_XFER_INT:
 839                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 840                 break;
 841         default:
 842                 /*
 843                  * This is only possible with faulty memory because we
 844                  * checked it already :)
 845                  */
 846                 BUG();
 847         }
 848
 849         /* always enable Continue on Short Packet */
 850         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 851
 852         if (!req->request.no_interrupt && !chain)
 853                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 854
 855         if (last)
 856                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 857
 858         if (chain)
 859                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 860
 861         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 862                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 863
 864         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 865
 866         trace_dwc3_prepare_trb(dep, trb);
 867 }
 868
 869 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 870 {
 871         struct dwc3_trb         *tmp;
 872
 873         /*
 874          * If enqueue & dequeue are equal than it is either full or empty.
 875          *
 876          * One way to know for sure is if the TRB right before us has HWO bit
 877          * set or not. If it has, then we're definitely full and can't fit any
 878          * more transfers in our ring.
 879          */
 880         if (dep->trb_enqueue == dep->trb_dequeue) {
 881                 /* If we're full, enqueue/dequeue are > 0 */
 882                 if (dep->trb_enqueue) {
 883                         tmp = &dep->trb_pool[dep->trb_enqueue - 1];
 884                         if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 885                                 return 0;
 886                 }
 887
 888                 return DWC3_TRB_NUM - 1;
 889         }
 890
 891         return dep->trb_dequeue - dep->trb_enqueue;
 892 }
 893
 894 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 895                 struct dwc3_request *req, unsigned int trbs_left)
 896 {
 897         struct usb_request *request = &req->request;
 898         struct scatterlist *sg = request->sg;
 899         struct scatterlist *s;
 900         unsigned int    last = false;
 901         unsigned int    length;
 902         dma_addr_t      dma;
 903         int             i;
 904
 905         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 906                 unsigned chain = true;
 907
 908                 length = sg_dma_len(s);
 909                 dma = sg_dma_address(s);
 910
 911                 if (sg_is_last(s)) {
 912                         if (list_is_last(&req->list, &dep->pending_list))
 913                                 last = true;
 914
 915                         chain = false;
 916                 }
 917
 918                 if (!trbs_left)
 919                         last = true;
 920
 921                 if (last)
 922                         chain = false;
 923
 924                 dwc3_prepare_one_trb(dep, req, dma, length,
 925                                 last, chain, i);
 926
 927                 if (last)
 928                         break;
 929         }
 930 }
 931
 932 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 933                 struct dwc3_request *req, unsigned int trbs_left)
 934 {
 935         unsigned int    last = false;
 936         unsigned int    length;
 937         dma_addr_t      dma;
 938
 939         dma = req->request.dma;
 940         length = req->request.length;
 941
 942         if (!trbs_left)
 943                 last = true;
 944
 945         /* Is this the last request? */
 946         if (list_is_last(&req->list, &dep->pending_list))
 947                 last = true;
 948
 949         dwc3_prepare_one_trb(dep, req, dma, length,
 950                         last, false, 0);
 951 }
 952
 953 /*
 954  * dwc3_prepare_trbs - setup TRBs from requests
 955  * @dep: endpoint for which requests are being prepared
 956  *
 957  * The function goes through the requests list and sets up TRBs for the
 958  * transfers. The function returns once there are no more TRBs available or
 959  * it runs out of requests.
 960  */
 961 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 962 {
 963         struct dwc3_request     *req, *n;
 964         u32                     trbs_left;
 965
 966         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 967
 968         trbs_left = dwc3_calc_trbs_left(dep);
 969
 970         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 971                 if (req->request.num_mapped_sgs > 0)
 972                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
 973                 else
 974                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
 975
 976                 if (!trbs_left)
 977                         return;
 978         }
 979 }
 980
 981 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 982 {
 983         struct dwc3_gadget_ep_cmd_params params;
 984         struct dwc3_request             *req;
 985         struct dwc3                     *dwc = dep->dwc;
 986         int                             starting;
 987         int                             ret;
 988         u32                             cmd;
 989
 990         starting = !(dep->flags & DWC3_EP_BUSY);
 991
 992         dwc3_prepare_trbs(dep);
 993         req = next_request(&dep->started_list);
 994         if (!req) {
 995                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 996                 return 0;
 997         }
 998
 999         memset(&params, 0, sizeof(params));
1000
1001         if (starting) {
1002                 params.param0 = upper_32_bits(req->trb_dma);
1003                 params.param1 = lower_32_bits(req->trb_dma);
1004                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1005         } else {
1006                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1007         }
1008
1009         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1010         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1011         if (ret < 0) {
1012                 /*
1013                  * FIXME we need to iterate over the list of requests
1014                  * here and stop, unmap, free and del each of the linked
1015                  * requests instead of what we do now.
1016                  */
1017                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1018                                 req->direction);
1019                 list_del(&req->list);
1020                 return ret;
1021         }
1022
1023         dep->flags |= DWC3_EP_BUSY;
1024
1025         if (starting) {
1026                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1027                 WARN_ON_ONCE(!dep->resource_index);
1028         }
1029
1030         return 0;
1031 }
1032
1033 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1034                 struct dwc3_ep *dep, u32 cur_uf)
1035 {
1036         u32 uf;
1037
1038         if (list_empty(&dep->pending_list)) {
1039                 dwc3_trace(trace_dwc3_gadget,
1040                                 "ISOC ep %s run out for requests",
1041                                 dep->name);
1042                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1043                 return;
1044         }
1045
1046         /* 4 micro frames in the future */
1047         uf = cur_uf + dep->interval * 4;
1048
1049         __dwc3_gadget_kick_transfer(dep, uf);
1050 }
1051
1052 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1053                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1054 {
1055         u32 cur_uf, mask;
1056
1057         mask = ~(dep->interval - 1);
1058         cur_uf = event->parameters & mask;
1059
1060         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1061 }
1062
1063 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1064 {
1065         struct dwc3             *dwc = dep->dwc;
1066         int                     ret;
1067
1068         if (!dep->endpoint.desc) {
1069                 dwc3_trace(trace_dwc3_gadget,
1070                                 "trying to queue request %p to disabled %s\n",
1071                                 &req->request, dep->endpoint.name);
1072                 return -ESHUTDOWN;
1073         }
1074
1075         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1076                                 &req->request, req->dep->name)) {
1077                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1078                                 &req->request, req->dep->name);
1079                 return -EINVAL;
1080         }
1081
1082         req->request.actual     = 0;
1083         req->request.status     = -EINPROGRESS;
1084         req->direction          = dep->direction;
1085         req->epnum              = dep->number;
1086
1087         trace_dwc3_ep_queue(req);
1088
1089         /*
1090          * Per databook, the total size of buffer must be a multiple
1091          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1092          * configed for endpoints in dwc3_gadget_set_ep_config(),
1093          * set to usb_endpoint_descriptor->wMaxPacketSize.
1094          */
1095         if (dep->direction == 0 &&
1096             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1097                 req->request.length = roundup(req->request.length,
1098                                         dep->endpoint.desc->wMaxPacketSize);
1099
1100         /*
1101          * We only add to our list of requests now and
1102          * start consuming the list once we get XferNotReady
1103          * IRQ.
1104          *
1105          * That way, we avoid doing anything that we don't need
1106          * to do now and defer it until the point we receive a
1107          * particular token from the Host side.
1108          *
1109          * This will also avoid Host cancelling URBs due to too
1110          * many NAKs.
1111          */
1112         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1113                         dep->direction);
1114         if (ret)
1115                 return ret;
1116
1117         list_add_tail(&req->list, &dep->pending_list);
1118
1119         /*
1120          * If there are no pending requests and the endpoint isn't already
1121          * busy, we will just start the request straight away.
1122          *
1123          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1124          * little bit faster.
1125          */
1126         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1127                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1128                         !(dep->flags & DWC3_EP_BUSY)) {
1129                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1130                 goto out;
1131         }
1132
1133         /*
1134          * There are a few special cases:
1135          *
1136          * 1. XferNotReady with empty list of requests. We need to kick the
1137          *    transfer here in that situation, otherwise we will be NAKing
1138          *    forever. If we get XferNotReady before gadget driver has a
1139          *    chance to queue a request, we will ACK the IRQ but won't be
1140          *    able to receive the data until the next request is queued.
1141          *    The following code is handling exactly that.
1142          *
1143          */
1144         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145                 /*
1146                  * If xfernotready is already elapsed and it is a case
1147                  * of isoc transfer, then issue END TRANSFER, so that
1148                  * you can receive xfernotready again and can have
1149                  * notion of current microframe.
1150                  */
1151                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1152                         if (list_empty(&dep->started_list)) {
1153                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1154                                 dep->flags = DWC3_EP_ENABLED;
1155                         }
1156                         return 0;
1157                 }
1158
1159                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1160                 if (!ret)
1161                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1162
1163                 goto out;
1164         }
1165
1166         /*
1167          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1168          *    kick the transfer here after queuing a request, otherwise the
1169          *    core may not see the modified TRB(s).
1170          */
1171         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1172                         (dep->flags & DWC3_EP_BUSY) &&
1173                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1174                 WARN_ON_ONCE(!dep->resource_index);
1175                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1176                 goto out;
1177         }
1178
1179         /*
1180          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1181          * right away, otherwise host will not know we have streams to be
1182          * handled.
1183          */
1184         if (dep->stream_capable)
1185                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1186
1187 out:
1188         if (ret && ret != -EBUSY)
1189                 dwc3_trace(trace_dwc3_gadget,
1190                                 "%s: failed to kick transfers\n",
1191                                 dep->name);
1192         if (ret == -EBUSY)
1193                 ret = 0;
1194
1195         return ret;
1196 }
1197
1198 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1199                 struct usb_request *request)
1200 {
1201         dwc3_gadget_ep_free_request(ep, request);
1202 }
1203
1204 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1205 {
1206         struct dwc3_request             *req;
1207         struct usb_request              *request;
1208         struct usb_ep                   *ep = &dep->endpoint;
1209
1210         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1211         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1212         if (!request)
1213                 return -ENOMEM;
1214
1215         request->length = 0;
1216         request->buf = dwc->zlp_buf;
1217         request->complete = __dwc3_gadget_ep_zlp_complete;
1218
1219         req = to_dwc3_request(request);
1220
1221         return __dwc3_gadget_ep_queue(dep, req);
1222 }
1223
1224 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1225         gfp_t gfp_flags)
1226 {
1227         struct dwc3_request             *req = to_dwc3_request(request);
1228         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1229         struct dwc3                     *dwc = dep->dwc;
1230
1231         unsigned long                   flags;
1232
1233         int                             ret;
1234
1235         spin_lock_irqsave(&dwc->lock, flags);
1236         ret = __dwc3_gadget_ep_queue(dep, req);
1237
1238         /*
1239          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1240          * setting request->zero, instead of doing magic, we will just queue an
1241          * extra usb_request ourselves so that it gets handled the same way as
1242          * any other request.
1243          */
1244         if (ret == 0 && request->zero && request->length &&
1245             (request->length % ep->desc->wMaxPacketSize == 0))
1246                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1247
1248         spin_unlock_irqrestore(&dwc->lock, flags);
1249
1250         return ret;
1251 }
1252
1253 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1254                 struct usb_request *request)
1255 {
1256         struct dwc3_request             *req = to_dwc3_request(request);
1257         struct dwc3_request             *r = NULL;
1258
1259         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1260         struct dwc3                     *dwc = dep->dwc;
1261
1262         unsigned long                   flags;
1263         int                             ret = 0;
1264
1265         trace_dwc3_ep_dequeue(req);
1266
1267         spin_lock_irqsave(&dwc->lock, flags);
1268
1269         list_for_each_entry(r, &dep->pending_list, list) {
1270                 if (r == req)
1271                         break;
1272         }
1273
1274         if (r != req) {
1275                 list_for_each_entry(r, &dep->started_list, list) {
1276                         if (r == req)
1277                                 break;
1278                 }
1279                 if (r == req) {
1280                         /* wait until it is processed */
1281                         dwc3_stop_active_transfer(dwc, dep->number, true);
1282                         goto out1;
1283                 }
1284                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1285                                 request, ep->name);
1286                 ret = -EINVAL;
1287                 goto out0;
1288         }
1289
1290 out1:
1291         /* giveback the request */
1292         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1293
1294 out0:
1295         spin_unlock_irqrestore(&dwc->lock, flags);
1296
1297         return ret;
1298 }
1299
1300 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1301 {
1302         struct dwc3_gadget_ep_cmd_params        params;
1303         struct dwc3                             *dwc = dep->dwc;
1304         int                                     ret;
1305
1306         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1307                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1308                 return -EINVAL;
1309         }
1310
1311         memset(&params, 0x00, sizeof(params));
1312
1313         if (value) {
1314                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1315                                 (!list_empty(&dep->started_list) ||
1316                                  !list_empty(&dep->pending_list)))) {
1317                         dwc3_trace(trace_dwc3_gadget,
1318                                         "%s: pending request, cannot halt",
1319                                         dep->name);
1320                         return -EAGAIN;
1321                 }
1322
1323                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1324                                 &params);
1325                 if (ret)
1326                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1327                                         dep->name);
1328                 else
1329                         dep->flags |= DWC3_EP_STALL;
1330         } else {
1331
1332                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1333                 if (ret)
1334                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1335                                         dep->name);
1336                 else
1337                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1338         }
1339
1340         return ret;
1341 }
1342
1343 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1344 {
1345         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1346         struct dwc3                     *dwc = dep->dwc;
1347
1348         unsigned long                   flags;
1349
1350         int                             ret;
1351
1352         spin_lock_irqsave(&dwc->lock, flags);
1353         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1354         spin_unlock_irqrestore(&dwc->lock, flags);
1355
1356         return ret;
1357 }
1358
1359 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1360 {
1361         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1362         struct dwc3                     *dwc = dep->dwc;
1363         unsigned long                   flags;
1364         int                             ret;
1365
1366         spin_lock_irqsave(&dwc->lock, flags);
1367         dep->flags |= DWC3_EP_WEDGE;
1368
1369         if (dep->number == 0 || dep->number == 1)
1370                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1371         else
1372                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1373         spin_unlock_irqrestore(&dwc->lock, flags);
1374
1375         return ret;
1376 }
1377
1378 /* -------------------------------------------------------------------------- */
1379
1380 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1381         .bLength        = USB_DT_ENDPOINT_SIZE,
1382         .bDescriptorType = USB_DT_ENDPOINT,
1383         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1384 };
1385
1386 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1387         .enable         = dwc3_gadget_ep0_enable,
1388         .disable        = dwc3_gadget_ep0_disable,
1389         .alloc_request  = dwc3_gadget_ep_alloc_request,
1390         .free_request   = dwc3_gadget_ep_free_request,
1391         .queue          = dwc3_gadget_ep0_queue,
1392         .dequeue        = dwc3_gadget_ep_dequeue,
1393         .set_halt       = dwc3_gadget_ep0_set_halt,
1394         .set_wedge      = dwc3_gadget_ep_set_wedge,
1395 };
1396
1397 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1398         .enable         = dwc3_gadget_ep_enable,
1399         .disable        = dwc3_gadget_ep_disable,
1400         .alloc_request  = dwc3_gadget_ep_alloc_request,
1401         .free_request   = dwc3_gadget_ep_free_request,
1402         .queue          = dwc3_gadget_ep_queue,
1403         .dequeue        = dwc3_gadget_ep_dequeue,
1404         .set_halt       = dwc3_gadget_ep_set_halt,
1405         .set_wedge      = dwc3_gadget_ep_set_wedge,
1406 };
1407
1408 /* -------------------------------------------------------------------------- */
1409
1410 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1411 {
1412         struct dwc3             *dwc = gadget_to_dwc(g);
1413         u32                     reg;
1414
1415         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1416         return DWC3_DSTS_SOFFN(reg);
1417 }
1418
1419 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1420 {
1421         unsigned long           timeout;
1422
1423         int                     ret;
1424         u32                     reg;
1425
1426         u8                      link_state;
1427         u8                      speed;
1428
1429         /*
1430          * According to the Databook Remote wakeup request should
1431          * be issued only when the device is in early suspend state.
1432          *
1433          * We can check that via USB Link State bits in DSTS register.
1434          */
1435         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1436
1437         speed = reg & DWC3_DSTS_CONNECTSPD;
1438         if (speed == DWC3_DSTS_SUPERSPEED) {
1439                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1440                 return 0;
1441         }
1442
1443         link_state = DWC3_DSTS_USBLNKST(reg);
1444
1445         switch (link_state) {
1446         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1447         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1448                 break;
1449         default:
1450                 dwc3_trace(trace_dwc3_gadget,
1451                                 "can't wakeup from '%s'\n",
1452                                 dwc3_gadget_link_string(link_state));
1453                 return -EINVAL;
1454         }
1455
1456         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1457         if (ret < 0) {
1458                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1459                 return ret;
1460         }
1461
1462         /* Recent versions do this automatically */
1463         if (dwc->revision < DWC3_REVISION_194A) {
1464                 /* write zeroes to Link Change Request */
1465                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1466                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1467                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1468         }
1469
1470         /* poll until Link State changes to ON */
1471         timeout = jiffies + msecs_to_jiffies(100);
1472
1473         while (!time_after(jiffies, timeout)) {
1474                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1475
1476                 /* in HS, means ON */
1477                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1478                         break;
1479         }
1480
1481         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1482                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1483                 return -EINVAL;
1484         }
1485
1486         return 0;
1487 }
1488
1489 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1490 {
1491         struct dwc3             *dwc = gadget_to_dwc(g);
1492         unsigned long           flags;
1493         int                     ret;
1494
1495         spin_lock_irqsave(&dwc->lock, flags);
1496         ret = __dwc3_gadget_wakeup(dwc);
1497         spin_unlock_irqrestore(&dwc->lock, flags);
1498
1499         return ret;
1500 }
1501
1502 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503                 int is_selfpowered)
1504 {
1505         struct dwc3             *dwc = gadget_to_dwc(g);
1506         unsigned long           flags;
1507
1508         spin_lock_irqsave(&dwc->lock, flags);
1509         g->is_selfpowered = !!is_selfpowered;
1510         spin_unlock_irqrestore(&dwc->lock, flags);
1511
1512         return 0;
1513 }
1514
1515 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1516 {
1517         u32                     reg;
1518         u32                     timeout = 500;
1519
1520         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1521         if (is_on) {
1522                 if (dwc->revision <= DWC3_REVISION_187A) {
1523                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1524                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525                 }
1526
1527                 if (dwc->revision >= DWC3_REVISION_194A)
1528                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1529                 reg |= DWC3_DCTL_RUN_STOP;
1530
1531                 if (dwc->has_hibernation)
1532                         reg |= DWC3_DCTL_KEEP_CONNECT;
1533
1534                 dwc->pullups_connected = true;
1535         } else {
1536                 reg &= ~DWC3_DCTL_RUN_STOP;
1537
1538                 if (dwc->has_hibernation && !suspend)
1539                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1540
1541                 dwc->pullups_connected = false;
1542         }
1543
1544         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545
1546         do {
1547                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1548                 if (is_on) {
1549                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550                                 break;
1551                 } else {
1552                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1553                                 break;
1554                 }
1555                 timeout--;
1556                 if (!timeout)
1557                         return -ETIMEDOUT;
1558                 udelay(1);
1559         } while (1);
1560
1561         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1562                         dwc->gadget_driver
1563                         ? dwc->gadget_driver->function : "no-function",
1564                         is_on ? "connect" : "disconnect");
1565
1566         return 0;
1567 }
1568
1569 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1570 {
1571         struct dwc3             *dwc = gadget_to_dwc(g);
1572         unsigned long           flags;
1573         int                     ret;
1574
1575         is_on = !!is_on;
1576
1577         spin_lock_irqsave(&dwc->lock, flags);
1578         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1579         spin_unlock_irqrestore(&dwc->lock, flags);
1580
1581         return ret;
1582 }
1583
1584 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1585 {
1586         u32                     reg;
1587
1588         /* Enable all but Start and End of Frame IRQs */
1589         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1590                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1591                         DWC3_DEVTEN_CMDCMPLTEN |
1592                         DWC3_DEVTEN_ERRTICERREN |
1593                         DWC3_DEVTEN_WKUPEVTEN |
1594                         DWC3_DEVTEN_ULSTCNGEN |
1595                         DWC3_DEVTEN_CONNECTDONEEN |
1596                         DWC3_DEVTEN_USBRSTEN |
1597                         DWC3_DEVTEN_DISCONNEVTEN);
1598
1599         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1600 }
1601
1602 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1603 {
1604         /* mask all interrupts */
1605         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1606 }
1607
1608 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1609 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1610
1611 /**
1612  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1613  * dwc: pointer to our context structure
1614  *
1615  * The following looks like complex but it's actually very simple. In order to
1616  * calculate the number of packets we can burst at once on OUT transfers, we're
1617  * gonna use RxFIFO size.
1618  *
1619  * To calculate RxFIFO size we need two numbers:
1620  * MDWIDTH = size, in bits, of the internal memory bus
1621  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1622  *
1623  * Given these two numbers, the formula is simple:
1624  *
1625  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1626  *
1627  * 24 bytes is for 3x SETUP packets
1628  * 16 bytes is a clock domain crossing tolerance
1629  *
1630  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1631  */
1632 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1633 {
1634         u32 ram2_depth;
1635         u32 mdwidth;
1636         u32 nump;
1637         u32 reg;
1638
1639         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1640         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1641
1642         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1643         nump = min_t(u32, nump, 16);
1644
1645         /* update NumP */
1646         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1647         reg &= ~DWC3_DCFG_NUMP_MASK;
1648         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1649         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1650 }
1651
1652 static int __dwc3_gadget_start(struct dwc3 *dwc)
1653 {
1654         struct dwc3_ep          *dep;
1655         int                     ret = 0;
1656         u32                     reg;
1657
1658         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1659         reg &= ~(DWC3_DCFG_SPEED_MASK);
1660
1661         /**
1662          * WORKAROUND: DWC3 revision < 2.20a have an issue
1663          * which would cause metastability state on Run/Stop
1664          * bit if we try to force the IP to USB2-only mode.
1665          *
1666          * Because of that, we cannot configure the IP to any
1667          * speed other than the SuperSpeed
1668          *
1669          * Refers to:
1670          *
1671          * STAR#9000525659: Clock Domain Crossing on DCTL in
1672          * USB 2.0 Mode
1673          */
1674         if (dwc->revision < DWC3_REVISION_220A) {
1675                 reg |= DWC3_DCFG_SUPERSPEED;
1676         } else {
1677                 switch (dwc->maximum_speed) {
1678                 case USB_SPEED_LOW:
1679                         reg |= DWC3_DSTS_LOWSPEED;
1680                         break;
1681                 case USB_SPEED_FULL:
1682                         reg |= DWC3_DSTS_FULLSPEED1;
1683                         break;
1684                 case USB_SPEED_HIGH:
1685                         reg |= DWC3_DSTS_HIGHSPEED;
1686                         break;
1687                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1688                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1689                 default:
1690                         reg |= DWC3_DSTS_SUPERSPEED;
1691                 }
1692         }
1693         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1694
1695         /*
1696          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1697          * field instead of letting dwc3 itself calculate that automatically.
1698          *
1699          * This way, we maximize the chances that we'll be able to get several
1700          * bursts of data without going through any sort of endpoint throttling.
1701          */
1702         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1703         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1704         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1705
1706         dwc3_gadget_setup_nump(dwc);
1707
1708         /* Start with SuperSpeed Default */
1709         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1710
1711         dep = dwc->eps[0];
1712         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1713                         false);
1714         if (ret) {
1715                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1716                 goto err0;
1717         }
1718
1719         dep = dwc->eps[1];
1720         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1721                         false);
1722         if (ret) {
1723                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1724                 goto err1;
1725         }
1726
1727         /* begin to receive SETUP packets */
1728         dwc->ep0state = EP0_SETUP_PHASE;
1729         dwc3_ep0_out_start(dwc);
1730
1731         dwc3_gadget_enable_irq(dwc);
1732
1733         return 0;
1734
1735 err1:
1736         __dwc3_gadget_ep_disable(dwc->eps[0]);
1737
1738 err0:
1739         return ret;
1740 }
1741
1742 static int dwc3_gadget_start(struct usb_gadget *g,
1743                 struct usb_gadget_driver *driver)
1744 {
1745         struct dwc3             *dwc = gadget_to_dwc(g);
1746         unsigned long           flags;
1747         int                     ret = 0;
1748         int                     irq;
1749
1750         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1751         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1752                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1753         if (ret) {
1754                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1755                                 irq, ret);
1756                 goto err0;
1757         }
1758
1759         spin_lock_irqsave(&dwc->lock, flags);
1760         if (dwc->gadget_driver) {
1761                 dev_err(dwc->dev, "%s is already bound to %s\n",
1762                                 dwc->gadget.name,
1763                                 dwc->gadget_driver->driver.name);
1764                 ret = -EBUSY;
1765                 goto err1;
1766         }
1767
1768         dwc->gadget_driver      = driver;
1769
1770         __dwc3_gadget_start(dwc);
1771         spin_unlock_irqrestore(&dwc->lock, flags);
1772
1773         return 0;
1774
1775 err1:
1776         spin_unlock_irqrestore(&dwc->lock, flags);
1777         free_irq(irq, dwc);
1778
1779 err0:
1780         return ret;
1781 }
1782
1783 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1784 {
1785         dwc3_gadget_disable_irq(dwc);
1786         __dwc3_gadget_ep_disable(dwc->eps[0]);
1787         __dwc3_gadget_ep_disable(dwc->eps[1]);
1788 }
1789
1790 static int dwc3_gadget_stop(struct usb_gadget *g)
1791 {
1792         struct dwc3             *dwc = gadget_to_dwc(g);
1793         unsigned long           flags;
1794         int                     irq;
1795
1796         spin_lock_irqsave(&dwc->lock, flags);
1797         __dwc3_gadget_stop(dwc);
1798         dwc->gadget_driver      = NULL;
1799         spin_unlock_irqrestore(&dwc->lock, flags);
1800
1801         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1802         free_irq(irq, dwc->ev_buf);
1803
1804         return 0;
1805 }
1806
1807 static const struct usb_gadget_ops dwc3_gadget_ops = {
1808         .get_frame              = dwc3_gadget_get_frame,
1809         .wakeup                 = dwc3_gadget_wakeup,
1810         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1811         .pullup                 = dwc3_gadget_pullup,
1812         .udc_start              = dwc3_gadget_start,
1813         .udc_stop               = dwc3_gadget_stop,
1814 };
1815
1816 /* -------------------------------------------------------------------------- */
1817
1818 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1819                 u8 num, u32 direction)
1820 {
1821         struct dwc3_ep                  *dep;
1822         u8                              i;
1823
1824         for (i = 0; i < num; i++) {
1825                 u8 epnum = (i << 1) | (!!direction);
1826
1827                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1828                 if (!dep)
1829                         return -ENOMEM;
1830
1831                 dep->dwc = dwc;
1832                 dep->number = epnum;
1833                 dep->direction = !!direction;
1834                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1835                 dwc->eps[epnum] = dep;
1836
1837                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1838                                 (epnum & 1) ? "in" : "out");
1839
1840                 dep->endpoint.name = dep->name;
1841
1842                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1843
1844                 if (epnum == 0 || epnum == 1) {
1845                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1846                         dep->endpoint.maxburst = 1;
1847                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1848                         if (!epnum)
1849                                 dwc->gadget.ep0 = &dep->endpoint;
1850                 } else {
1851                         int             ret;
1852
1853                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1854                         dep->endpoint.max_streams = 15;
1855                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1856                         list_add_tail(&dep->endpoint.ep_list,
1857                                         &dwc->gadget.ep_list);
1858
1859                         ret = dwc3_alloc_trb_pool(dep);
1860                         if (ret)
1861                                 return ret;
1862                 }
1863
1864                 if (epnum == 0 || epnum == 1) {
1865                         dep->endpoint.caps.type_control = true;
1866                 } else {
1867                         dep->endpoint.caps.type_iso = true;
1868                         dep->endpoint.caps.type_bulk = true;
1869                         dep->endpoint.caps.type_int = true;
1870                 }
1871
1872                 dep->endpoint.caps.dir_in = !!direction;
1873                 dep->endpoint.caps.dir_out = !direction;
1874
1875                 INIT_LIST_HEAD(&dep->pending_list);
1876                 INIT_LIST_HEAD(&dep->started_list);
1877         }
1878
1879         return 0;
1880 }
1881
1882 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1883 {
1884         int                             ret;
1885
1886         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1887
1888         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1889         if (ret < 0) {
1890                 dwc3_trace(trace_dwc3_gadget,
1891                                 "failed to allocate OUT endpoints");
1892                 return ret;
1893         }
1894
1895         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1896         if (ret < 0) {
1897                 dwc3_trace(trace_dwc3_gadget,
1898                                 "failed to allocate IN endpoints");
1899                 return ret;
1900         }
1901
1902         return 0;
1903 }
1904
1905 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1906 {
1907         struct dwc3_ep                  *dep;
1908         u8                              epnum;
1909
1910         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1911                 dep = dwc->eps[epnum];
1912                 if (!dep)
1913                         continue;
1914                 /*
1915                  * Physical endpoints 0 and 1 are special; they form the
1916                  * bi-directional USB endpoint 0.
1917                  *
1918                  * For those two physical endpoints, we don't allocate a TRB
1919                  * pool nor do we add them the endpoints list. Due to that, we
1920                  * shouldn't do these two operations otherwise we would end up
1921                  * with all sorts of bugs when removing dwc3.ko.
1922                  */
1923                 if (epnum != 0 && epnum != 1) {
1924                         dwc3_free_trb_pool(dep);
1925                         list_del(&dep->endpoint.ep_list);
1926                 }
1927
1928                 kfree(dep);
1929         }
1930 }
1931
1932 /* -------------------------------------------------------------------------- */
1933
1934 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1935                 struct dwc3_request *req, struct dwc3_trb *trb,
1936                 const struct dwc3_event_depevt *event, int status)
1937 {
1938         unsigned int            count;
1939         unsigned int            s_pkt = 0;
1940         unsigned int            trb_status;
1941
1942         trace_dwc3_complete_trb(dep, trb);
1943
1944         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1945                 /*
1946                  * We continue despite the error. There is not much we
1947                  * can do. If we don't clean it up we loop forever. If
1948                  * we skip the TRB then it gets overwritten after a
1949                  * while since we use them in a ring buffer. A BUG()
1950                  * would help. Lets hope that if this occurs, someone
1951                  * fixes the root cause instead of looking away :)
1952                  */
1953                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1954                                 dep->name, trb);
1955         count = trb->size & DWC3_TRB_SIZE_MASK;
1956
1957         if (dep->direction) {
1958                 if (count) {
1959                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1960                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1961                                 dwc3_trace(trace_dwc3_gadget,
1962                                                 "%s: incomplete IN transfer\n",
1963                                                 dep->name);
1964                                 /*
1965                                  * If missed isoc occurred and there is
1966                                  * no request queued then issue END
1967                                  * TRANSFER, so that core generates
1968                                  * next xfernotready and we will issue
1969                                  * a fresh START TRANSFER.
1970                                  * If there are still queued request
1971                                  * then wait, do not issue either END
1972                                  * or UPDATE TRANSFER, just attach next
1973                                  * request in pending_list during
1974                                  * giveback.If any future queued request
1975                                  * is successfully transferred then we
1976                                  * will issue UPDATE TRANSFER for all
1977                                  * request in the pending_list.
1978                                  */
1979                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1980                         } else {
1981                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1982                                                 dep->name);
1983                                 status = -ECONNRESET;
1984                         }
1985                 } else {
1986                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1987                 }
1988         } else {
1989                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1990                         s_pkt = 1;
1991         }
1992
1993         /*
1994          * We assume here we will always receive the entire data block
1995          * which we should receive. Meaning, if we program RX to
1996          * receive 4K but we receive only 2K, we assume that's all we
1997          * should receive and we simply bounce the request back to the
1998          * gadget driver for further processing.
1999          */
2000         req->request.actual += req->request.length - count;
2001         if (s_pkt)
2002                 return 1;
2003         if ((event->status & DEPEVT_STATUS_LST) &&
2004                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2005                                 DWC3_TRB_CTRL_HWO)))
2006                 return 1;
2007         if ((event->status & DEPEVT_STATUS_IOC) &&
2008                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2009                 return 1;
2010         return 0;
2011 }
2012
2013 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2014                 const struct dwc3_event_depevt *event, int status)
2015 {
2016         struct dwc3_request     *req;
2017         struct dwc3_trb         *trb;
2018         unsigned int            slot;
2019         unsigned int            i;
2020         int                     ret;
2021
2022         do {
2023                 req = next_request(&dep->started_list);
2024                 if (WARN_ON_ONCE(!req))
2025                         return 1;
2026
2027                 i = 0;
2028                 do {
2029                         slot = req->first_trb_index + i;
2030                         if (slot == DWC3_TRB_NUM - 1)
2031                                 slot++;
2032                         slot %= DWC3_TRB_NUM;
2033                         trb = &dep->trb_pool[slot];
2034
2035                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2036                                         event, status);
2037                         if (ret)
2038                                 break;
2039                 } while (++i < req->request.num_mapped_sgs);
2040
2041                 dwc3_gadget_giveback(dep, req, status);
2042
2043                 if (ret)
2044                         break;
2045         } while (1);
2046
2047         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2048                         list_empty(&dep->started_list)) {
2049                 if (list_empty(&dep->pending_list)) {
2050                         /*
2051                          * If there is no entry in request list then do
2052                          * not issue END TRANSFER now. Just set PENDING
2053                          * flag, so that END TRANSFER is issued when an
2054                          * entry is added into request list.
2055                          */
2056                         dep->flags = DWC3_EP_PENDING_REQUEST;
2057                 } else {
2058                         dwc3_stop_active_transfer(dwc, dep->number, true);
2059                         dep->flags = DWC3_EP_ENABLED;
2060                 }
2061                 return 1;
2062         }
2063
2064         return 1;
2065 }
2066
2067 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2068                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2069 {
2070         unsigned                status = 0;
2071         int                     clean_busy;
2072         u32                     is_xfer_complete;
2073
2074         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2075
2076         if (event->status & DEPEVT_STATUS_BUSERR)
2077                 status = -ECONNRESET;
2078
2079         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2080         if (clean_busy && (is_xfer_complete ||
2081                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2082                 dep->flags &= ~DWC3_EP_BUSY;
2083
2084         /*
2085          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2086          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2087          */
2088         if (dwc->revision < DWC3_REVISION_183A) {
2089                 u32             reg;
2090                 int             i;
2091
2092                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2093                         dep = dwc->eps[i];
2094
2095                         if (!(dep->flags & DWC3_EP_ENABLED))
2096                                 continue;
2097
2098                         if (!list_empty(&dep->started_list))
2099                                 return;
2100                 }
2101
2102                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2103                 reg |= dwc->u1u2;
2104                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2105
2106                 dwc->u1u2 = 0;
2107         }
2108
2109         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2110                 int ret;
2111
2112                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2113                 if (!ret || ret == -EBUSY)
2114                         return;
2115         }
2116 }
2117
2118 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2119                 const struct dwc3_event_depevt *event)
2120 {
2121         struct dwc3_ep          *dep;
2122         u8                      epnum = event->endpoint_number;
2123
2124         dep = dwc->eps[epnum];
2125
2126         if (!(dep->flags & DWC3_EP_ENABLED))
2127                 return;
2128
2129         if (epnum == 0 || epnum == 1) {
2130                 dwc3_ep0_interrupt(dwc, event);
2131                 return;
2132         }
2133
2134         switch (event->endpoint_event) {
2135         case DWC3_DEPEVT_XFERCOMPLETE:
2136                 dep->resource_index = 0;
2137
2138                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2139                         dwc3_trace(trace_dwc3_gadget,
2140                                         "%s is an Isochronous endpoint\n",
2141                                         dep->name);
2142                         return;
2143                 }
2144
2145                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2146                 break;
2147         case DWC3_DEPEVT_XFERINPROGRESS:
2148                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2149                 break;
2150         case DWC3_DEPEVT_XFERNOTREADY:
2151                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2152                         dwc3_gadget_start_isoc(dwc, dep, event);
2153                 } else {
2154                         int active;
2155                         int ret;
2156
2157                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2158
2159                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2160                                         dep->name, active ? "Transfer Active"
2161                                         : "Transfer Not Active");
2162
2163                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2164                         if (!ret || ret == -EBUSY)
2165                                 return;
2166
2167                         dwc3_trace(trace_dwc3_gadget,
2168                                         "%s: failed to kick transfers\n",
2169                                         dep->name);
2170                 }
2171
2172                 break;
2173         case DWC3_DEPEVT_STREAMEVT:
2174                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2175                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2176                                         dep->name);
2177                         return;
2178                 }
2179
2180                 switch (event->status) {
2181                 case DEPEVT_STREAMEVT_FOUND:
2182                         dwc3_trace(trace_dwc3_gadget,
2183                                         "Stream %d found and started",
2184                                         event->parameters);
2185
2186                         break;
2187                 case DEPEVT_STREAMEVT_NOTFOUND:
2188                         /* FALLTHROUGH */
2189                 default:
2190                         dwc3_trace(trace_dwc3_gadget,
2191                                         "unable to find suitable stream\n");
2192                 }
2193                 break;
2194         case DWC3_DEPEVT_RXTXFIFOEVT:
2195                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2196                 break;
2197         case DWC3_DEPEVT_EPCMDCMPLT:
2198                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2199                 break;
2200         }
2201 }
2202
2203 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2204 {
2205         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2206                 spin_unlock(&dwc->lock);
2207                 dwc->gadget_driver->disconnect(&dwc->gadget);
2208                 spin_lock(&dwc->lock);
2209         }
2210 }
2211
2212 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2213 {
2214         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2215                 spin_unlock(&dwc->lock);
2216                 dwc->gadget_driver->suspend(&dwc->gadget);
2217                 spin_lock(&dwc->lock);
2218         }
2219 }
2220
2221 static void dwc3_resume_gadget(struct dwc3 *dwc)
2222 {
2223         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2224                 spin_unlock(&dwc->lock);
2225                 dwc->gadget_driver->resume(&dwc->gadget);
2226                 spin_lock(&dwc->lock);
2227         }
2228 }
2229
2230 static void dwc3_reset_gadget(struct dwc3 *dwc)
2231 {
2232         if (!dwc->gadget_driver)
2233                 return;
2234
2235         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2236                 spin_unlock(&dwc->lock);
2237                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2238                 spin_lock(&dwc->lock);
2239         }
2240 }
2241
2242 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2243 {
2244         struct dwc3_ep *dep;
2245         struct dwc3_gadget_ep_cmd_params params;
2246         u32 cmd;
2247         int ret;
2248
2249         dep = dwc->eps[epnum];
2250
2251         if (!dep->resource_index)
2252                 return;
2253
2254         /*
2255          * NOTICE: We are violating what the Databook says about the
2256          * EndTransfer command. Ideally we would _always_ wait for the
2257          * EndTransfer Command Completion IRQ, but that's causing too
2258          * much trouble synchronizing between us and gadget driver.
2259          *
2260          * We have discussed this with the IP Provider and it was
2261          * suggested to giveback all requests here, but give HW some
2262          * extra time to synchronize with the interconnect. We're using
2263          * an arbitrary 100us delay for that.
2264          *
2265          * Note also that a similar handling was tested by Synopsys
2266          * (thanks a lot Paul) and nothing bad has come out of it.
2267          * In short, what we're doing is:
2268          *
2269          * - Issue EndTransfer WITH CMDIOC bit set
2270          * - Wait 100us
2271          */
2272
2273         cmd = DWC3_DEPCMD_ENDTRANSFER;
2274         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2275         cmd |= DWC3_DEPCMD_CMDIOC;
2276         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2277         memset(&params, 0, sizeof(params));
2278         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2279         WARN_ON_ONCE(ret);
2280         dep->resource_index = 0;
2281         dep->flags &= ~DWC3_EP_BUSY;
2282         udelay(100);
2283 }
2284
2285 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2286 {
2287         u32 epnum;
2288
2289         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2290                 struct dwc3_ep *dep;
2291
2292                 dep = dwc->eps[epnum];
2293                 if (!dep)
2294                         continue;
2295
2296                 if (!(dep->flags & DWC3_EP_ENABLED))
2297                         continue;
2298
2299                 dwc3_remove_requests(dwc, dep);
2300         }
2301 }
2302
2303 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2304 {
2305         u32 epnum;
2306
2307         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2308                 struct dwc3_ep *dep;
2309                 int ret;
2310
2311                 dep = dwc->eps[epnum];
2312                 if (!dep)
2313                         continue;
2314
2315                 if (!(dep->flags & DWC3_EP_STALL))
2316                         continue;
2317
2318                 dep->flags &= ~DWC3_EP_STALL;
2319
2320                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2321                 WARN_ON_ONCE(ret);
2322         }
2323 }
2324
2325 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2326 {
2327         int                     reg;
2328
2329         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2330         reg &= ~DWC3_DCTL_INITU1ENA;
2331         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2332
2333         reg &= ~DWC3_DCTL_INITU2ENA;
2334         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2335
2336         dwc3_disconnect_gadget(dwc);
2337
2338         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2339         dwc->setup_packet_pending = false;
2340         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2341 }
2342
2343 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2344 {
2345         u32                     reg;
2346
2347         /*
2348          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2349          * would cause a missing Disconnect Event if there's a
2350          * pending Setup Packet in the FIFO.
2351          *
2352          * There's no suggested workaround on the official Bug
2353          * report, which states that "unless the driver/application
2354          * is doing any special handling of a disconnect event,
2355          * there is no functional issue".
2356          *
2357          * Unfortunately, it turns out that we _do_ some special
2358          * handling of a disconnect event, namely complete all
2359          * pending transfers, notify gadget driver of the
2360          * disconnection, and so on.
2361          *
2362          * Our suggested workaround is to follow the Disconnect
2363          * Event steps here, instead, based on a setup_packet_pending
2364          * flag. Such flag gets set whenever we have a SETUP_PENDING
2365          * status for EP0 TRBs and gets cleared on XferComplete for the
2366          * same endpoint.
2367          *
2368          * Refers to:
2369          *
2370          * STAR#9000466709: RTL: Device : Disconnect event not
2371          * generated if setup packet pending in FIFO
2372          */
2373         if (dwc->revision < DWC3_REVISION_188A) {
2374                 if (dwc->setup_packet_pending)
2375                         dwc3_gadget_disconnect_interrupt(dwc);
2376         }
2377
2378         dwc3_reset_gadget(dwc);
2379
2380         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2381         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2382         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2383         dwc->test_mode = false;
2384
2385         dwc3_stop_active_transfers(dwc);
2386         dwc3_clear_stall_all_ep(dwc);
2387
2388         /* Reset device address to zero */
2389         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2390         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2391         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2392 }
2393
2394 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2395 {
2396         u32 reg;
2397         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2398
2399         /*
2400          * We change the clock only at SS but I dunno why I would want to do
2401          * this. Maybe it becomes part of the power saving plan.
2402          */
2403
2404         if (speed != DWC3_DSTS_SUPERSPEED)
2405                 return;
2406
2407         /*
2408          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2409          * each time on Connect Done.
2410          */
2411         if (!usb30_clock)
2412                 return;
2413
2414         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2415         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2416         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2417 }
2418
2419 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2420 {
2421         struct dwc3_ep          *dep;
2422         int                     ret;
2423         u32                     reg;
2424         u8                      speed;
2425
2426         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2427         speed = reg & DWC3_DSTS_CONNECTSPD;
2428         dwc->speed = speed;
2429
2430         dwc3_update_ram_clk_sel(dwc, speed);
2431
2432         switch (speed) {
2433         case DWC3_DCFG_SUPERSPEED:
2434                 /*
2435                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2436                  * would cause a missing USB3 Reset event.
2437                  *
2438                  * In such situations, we should force a USB3 Reset
2439                  * event by calling our dwc3_gadget_reset_interrupt()
2440                  * routine.
2441                  *
2442                  * Refers to:
2443                  *
2444                  * STAR#9000483510: RTL: SS : USB3 reset event may
2445                  * not be generated always when the link enters poll
2446                  */
2447                 if (dwc->revision < DWC3_REVISION_190A)
2448                         dwc3_gadget_reset_interrupt(dwc);
2449
2450                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2451                 dwc->gadget.ep0->maxpacket = 512;
2452                 dwc->gadget.speed = USB_SPEED_SUPER;
2453                 break;
2454         case DWC3_DCFG_HIGHSPEED:
2455                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2456                 dwc->gadget.ep0->maxpacket = 64;
2457                 dwc->gadget.speed = USB_SPEED_HIGH;
2458                 break;
2459         case DWC3_DCFG_FULLSPEED2:
2460         case DWC3_DCFG_FULLSPEED1:
2461                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2462                 dwc->gadget.ep0->maxpacket = 64;
2463                 dwc->gadget.speed = USB_SPEED_FULL;
2464                 break;
2465         case DWC3_DCFG_LOWSPEED:
2466                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2467                 dwc->gadget.ep0->maxpacket = 8;
2468                 dwc->gadget.speed = USB_SPEED_LOW;
2469                 break;
2470         }
2471
2472         /* Enable USB2 LPM Capability */
2473
2474         if ((dwc->revision > DWC3_REVISION_194A)
2475                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2476                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2477                 reg |= DWC3_DCFG_LPM_CAP;
2478                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2479
2480                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2481                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2482
2483                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2484
2485                 /*
2486                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2487                  * DCFG.LPMCap is set, core responses with an ACK and the
2488                  * BESL value in the LPM token is less than or equal to LPM
2489                  * NYET threshold.
2490                  */
2491                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2492                                 && dwc->has_lpm_erratum,
2493                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2494
2495                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2496                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2497
2498                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2499         } else {
2500                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2501                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2502                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2503         }
2504
2505         dep = dwc->eps[0];
2506         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2507                         false);
2508         if (ret) {
2509                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2510                 return;
2511         }
2512
2513         dep = dwc->eps[1];
2514         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2515                         false);
2516         if (ret) {
2517                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2518                 return;
2519         }
2520
2521         /*
2522          * Configure PHY via GUSB3PIPECTLn if required.
2523          *
2524          * Update GTXFIFOSIZn
2525          *
2526          * In both cases reset values should be sufficient.
2527          */
2528 }
2529
2530 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2531 {
2532         /*
2533          * TODO take core out of low power mode when that's
2534          * implemented.
2535          */
2536
2537         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2538                 spin_unlock(&dwc->lock);
2539                 dwc->gadget_driver->resume(&dwc->gadget);
2540                 spin_lock(&dwc->lock);
2541         }
2542 }
2543
2544 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2545                 unsigned int evtinfo)
2546 {
2547         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2548         unsigned int            pwropt;
2549
2550         /*
2551          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2552          * Hibernation mode enabled which would show up when device detects
2553          * host-initiated U3 exit.
2554          *
2555          * In that case, device will generate a Link State Change Interrupt
2556          * from U3 to RESUME which is only necessary if Hibernation is
2557          * configured in.
2558          *
2559          * There are no functional changes due to such spurious event and we
2560          * just need to ignore it.
2561          *
2562          * Refers to:
2563          *
2564          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2565          * operational mode
2566          */
2567         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2568         if ((dwc->revision < DWC3_REVISION_250A) &&
2569                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2570                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2571                                 (next == DWC3_LINK_STATE_RESUME)) {
2572                         dwc3_trace(trace_dwc3_gadget,
2573                                         "ignoring transition U3 -> Resume");
2574                         return;
2575                 }
2576         }
2577
2578         /*
2579          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2580          * on the link partner, the USB session might do multiple entry/exit
2581          * of low power states before a transfer takes place.
2582          *
2583          * Due to this problem, we might experience lower throughput. The
2584          * suggested workaround is to disable DCTL[12:9] bits if we're
2585          * transitioning from U1/U2 to U0 and enable those bits again
2586          * after a transfer completes and there are no pending transfers
2587          * on any of the enabled endpoints.
2588          *
2589          * This is the first half of that workaround.
2590          *
2591          * Refers to:
2592          *
2593          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2594          * core send LGO_Ux entering U0
2595          */
2596         if (dwc->revision < DWC3_REVISION_183A) {
2597                 if (next == DWC3_LINK_STATE_U0) {
2598                         u32     u1u2;
2599                         u32     reg;
2600
2601                         switch (dwc->link_state) {
2602                         case DWC3_LINK_STATE_U1:
2603                         case DWC3_LINK_STATE_U2:
2604                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2605                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2606                                                 | DWC3_DCTL_ACCEPTU2ENA
2607                                                 | DWC3_DCTL_INITU1ENA
2608                                                 | DWC3_DCTL_ACCEPTU1ENA);
2609
2610                                 if (!dwc->u1u2)
2611                                         dwc->u1u2 = reg & u1u2;
2612
2613                                 reg &= ~u1u2;
2614
2615                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2616                                 break;
2617                         default:
2618                                 /* do nothing */
2619                                 break;
2620                         }
2621                 }
2622         }
2623
2624         switch (next) {
2625         case DWC3_LINK_STATE_U1:
2626                 if (dwc->speed == USB_SPEED_SUPER)
2627                         dwc3_suspend_gadget(dwc);
2628                 break;
2629         case DWC3_LINK_STATE_U2:
2630         case DWC3_LINK_STATE_U3:
2631                 dwc3_suspend_gadget(dwc);
2632                 break;
2633         case DWC3_LINK_STATE_RESUME:
2634                 dwc3_resume_gadget(dwc);
2635                 break;
2636         default:
2637                 /* do nothing */
2638                 break;
2639         }
2640
2641         dwc->link_state = next;
2642 }
2643
2644 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2645                 unsigned int evtinfo)
2646 {
2647         unsigned int is_ss = evtinfo & BIT(4);
2648
2649         /**
2650          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2651          * have a known issue which can cause USB CV TD.9.23 to fail
2652          * randomly.
2653          *
2654          * Because of this issue, core could generate bogus hibernation
2655          * events which SW needs to ignore.
2656          *
2657          * Refers to:
2658          *
2659          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2660          * Device Fallback from SuperSpeed
2661          */
2662         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2663                 return;
2664
2665         /* enter hibernation here */
2666 }
2667
2668 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2669                 const struct dwc3_event_devt *event)
2670 {
2671         switch (event->type) {
2672         case DWC3_DEVICE_EVENT_DISCONNECT:
2673                 dwc3_gadget_disconnect_interrupt(dwc);
2674                 break;
2675         case DWC3_DEVICE_EVENT_RESET:
2676                 dwc3_gadget_reset_interrupt(dwc);
2677                 break;
2678         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2679                 dwc3_gadget_conndone_interrupt(dwc);
2680                 break;
2681         case DWC3_DEVICE_EVENT_WAKEUP:
2682                 dwc3_gadget_wakeup_interrupt(dwc);
2683                 break;
2684         case DWC3_DEVICE_EVENT_HIBER_REQ:
2685                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2686                                         "unexpected hibernation event\n"))
2687                         break;
2688
2689                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2690                 break;
2691         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2692                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2693                 break;
2694         case DWC3_DEVICE_EVENT_EOPF:
2695                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2696                 break;
2697         case DWC3_DEVICE_EVENT_SOF:
2698                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2699                 break;
2700         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2701                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2702                 break;
2703         case DWC3_DEVICE_EVENT_CMD_CMPL:
2704                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2705                 break;
2706         case DWC3_DEVICE_EVENT_OVERFLOW:
2707                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2708                 break;
2709         default:
2710                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2711         }
2712 }
2713
2714 static void dwc3_process_event_entry(struct dwc3 *dwc,
2715                 const union dwc3_event *event)
2716 {
2717         trace_dwc3_event(event->raw);
2718
2719         /* Endpoint IRQ, handle it and return early */
2720         if (event->type.is_devspec == 0) {
2721                 /* depevt */
2722                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2723         }
2724
2725         switch (event->type.type) {
2726         case DWC3_EVENT_TYPE_DEV:
2727                 dwc3_gadget_interrupt(dwc, &event->devt);
2728                 break;
2729         /* REVISIT what to do with Carkit and I2C events ? */
2730         default:
2731                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2732         }
2733 }
2734
2735 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2736 {
2737         struct dwc3 *dwc = evt->dwc;
2738         irqreturn_t ret = IRQ_NONE;
2739         int left;
2740         u32 reg;
2741
2742         left = evt->count;
2743
2744         if (!(evt->flags & DWC3_EVENT_PENDING))
2745                 return IRQ_NONE;
2746
2747         while (left > 0) {
2748                 union dwc3_event event;
2749
2750                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2751
2752                 dwc3_process_event_entry(dwc, &event);
2753
2754                 /*
2755                  * FIXME we wrap around correctly to the next entry as
2756                  * almost all entries are 4 bytes in size. There is one
2757                  * entry which has 12 bytes which is a regular entry
2758                  * followed by 8 bytes data. ATM I don't know how
2759                  * things are organized if we get next to the a
2760                  * boundary so I worry about that once we try to handle
2761                  * that.
2762                  */
2763                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2764                 left -= 4;
2765
2766                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2767         }
2768
2769         evt->count = 0;
2770         evt->flags &= ~DWC3_EVENT_PENDING;
2771         ret = IRQ_HANDLED;
2772
2773         /* Unmask interrupt */
2774         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2775         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2776         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2777
2778         return ret;
2779 }
2780
2781 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2782 {
2783         struct dwc3_event_buffer *evt = _evt;
2784         struct dwc3 *dwc = evt->dwc;
2785         unsigned long flags;
2786         irqreturn_t ret = IRQ_NONE;
2787
2788         spin_lock_irqsave(&dwc->lock, flags);
2789         ret = dwc3_process_event_buf(evt);
2790         spin_unlock_irqrestore(&dwc->lock, flags);
2791
2792         return ret;
2793 }
2794
2795 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2796 {
2797         struct dwc3 *dwc = evt->dwc;
2798         u32 count;
2799         u32 reg;
2800
2801         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2802         count &= DWC3_GEVNTCOUNT_MASK;
2803         if (!count)
2804                 return IRQ_NONE;
2805
2806         evt->count = count;
2807         evt->flags |= DWC3_EVENT_PENDING;
2808
2809         /* Mask interrupt */
2810         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2811         reg |= DWC3_GEVNTSIZ_INTMASK;
2812         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2813
2814         return IRQ_WAKE_THREAD;
2815 }
2816
2817 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2818 {
2819         struct dwc3_event_buffer        *evt = _evt;
2820
2821         return dwc3_check_event_buf(evt);
2822 }
2823
2824 /**
2825  * dwc3_gadget_init - Initializes gadget related registers
2826  * @dwc: pointer to our controller context structure
2827  *
2828  * Returns 0 on success otherwise negative errno.
2829  */
2830 int dwc3_gadget_init(struct dwc3 *dwc)
2831 {
2832         int                                     ret;
2833
2834         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2835                         &dwc->ctrl_req_addr, GFP_KERNEL);
2836         if (!dwc->ctrl_req) {
2837                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2838                 ret = -ENOMEM;
2839                 goto err0;
2840         }
2841
2842         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2843                         &dwc->ep0_trb_addr, GFP_KERNEL);
2844         if (!dwc->ep0_trb) {
2845                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2846                 ret = -ENOMEM;
2847                 goto err1;
2848         }
2849
2850         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2851         if (!dwc->setup_buf) {
2852                 ret = -ENOMEM;
2853                 goto err2;
2854         }
2855
2856         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2857                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2858                         GFP_KERNEL);
2859         if (!dwc->ep0_bounce) {
2860                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2861                 ret = -ENOMEM;
2862                 goto err3;
2863         }
2864
2865         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2866         if (!dwc->zlp_buf) {
2867                 ret = -ENOMEM;
2868                 goto err4;
2869         }
2870
2871         dwc->gadget.ops                 = &dwc3_gadget_ops;
2872         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2873         dwc->gadget.sg_supported        = true;
2874         dwc->gadget.name                = "dwc3-gadget";
2875         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2876
2877         /*
2878          * FIXME We might be setting max_speed to <SUPER, however versions
2879          * <2.20a of dwc3 have an issue with metastability (documented
2880          * elsewhere in this driver) which tells us we can't set max speed to
2881          * anything lower than SUPER.
2882          *
2883          * Because gadget.max_speed is only used by composite.c and function
2884          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2885          * to happen so we avoid sending SuperSpeed Capability descriptor
2886          * together with our BOS descriptor as that could confuse host into
2887          * thinking we can handle super speed.
2888          *
2889          * Note that, in fact, we won't even support GetBOS requests when speed
2890          * is less than super speed because we don't have means, yet, to tell
2891          * composite.c that we are USB 2.0 + LPM ECN.
2892          */
2893         if (dwc->revision < DWC3_REVISION_220A)
2894                 dwc3_trace(trace_dwc3_gadget,
2895                                 "Changing max_speed on rev %08x\n",
2896                                 dwc->revision);
2897
2898         dwc->gadget.max_speed           = dwc->maximum_speed;
2899
2900         /*
2901          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2902          * on ep out.
2903          */
2904         dwc->gadget.quirk_ep_out_aligned_size = true;
2905
2906         /*
2907          * REVISIT: Here we should clear all pending IRQs to be
2908          * sure we're starting from a well known location.
2909          */
2910
2911         ret = dwc3_gadget_init_endpoints(dwc);
2912         if (ret)
2913                 goto err5;
2914
2915         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2916         if (ret) {
2917                 dev_err(dwc->dev, "failed to register udc\n");
2918                 goto err5;
2919         }
2920
2921         return 0;
2922
2923 err5:
2924         kfree(dwc->zlp_buf);
2925
2926 err4:
2927         dwc3_gadget_free_endpoints(dwc);
2928         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2929                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2930
2931 err3:
2932         kfree(dwc->setup_buf);
2933
2934 err2:
2935         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2936                         dwc->ep0_trb, dwc->ep0_trb_addr);
2937
2938 err1:
2939         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2940                         dwc->ctrl_req, dwc->ctrl_req_addr);
2941
2942 err0:
2943         return ret;
2944 }
2945
2946 /* -------------------------------------------------------------------------- */
2947
2948 void dwc3_gadget_exit(struct dwc3 *dwc)
2949 {
2950         usb_del_gadget_udc(&dwc->gadget);
2951
2952         dwc3_gadget_free_endpoints(dwc);
2953
2954         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2955                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2956
2957         kfree(dwc->setup_buf);
2958         kfree(dwc->zlp_buf);
2959
2960         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2961                         dwc->ep0_trb, dwc->ep0_trb_addr);
2962
2963         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2964                         dwc->ctrl_req, dwc->ctrl_req_addr);
2965 }
2966
2967 int dwc3_gadget_suspend(struct dwc3 *dwc)
2968 {
2969         int ret;
2970
2971         if (!dwc->gadget_driver)
2972                 return 0;
2973
2974         ret = dwc3_gadget_run_stop(dwc, false, false);
2975         if (ret < 0)
2976                 return ret;
2977
2978         dwc3_disconnect_gadget(dwc);
2979         __dwc3_gadget_stop(dwc);
2980
2981         return 0;
2982 }
2983
2984 int dwc3_gadget_resume(struct dwc3 *dwc)
2985 {
2986         int                     ret;
2987
2988         if (!dwc->gadget_driver)
2989                 return 0;
2990
2991         ret = __dwc3_gadget_start(dwc);
2992         if (ret < 0)
2993                 goto err0;
2994
2995         ret = dwc3_gadget_run_stop(dwc, true, false);
2996         if (ret < 0)
2997                 goto err1;
2998
2999         return 0;
3000
3001 err1:
3002         __dwc3_gadget_stop(dwc);
3003
3004 err0:
3005         return ret;
3006 }