drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
  58
  59 /**
  60  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  61  * @dwc: pointer to our context structure
  62  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  63  *
  64  * Caller should take care of locking. This function will
  65  * return 0 on success or -EINVAL if wrong Test Selector
  66  * is passed
  67  */
  68 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  69 {
  70         u32             reg;
  71
  72         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  73         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  74
  75         switch (mode) {
  76         case TEST_J:
  77         case TEST_K:
  78         case TEST_SE0_NAK:
  79         case TEST_PACKET:
  80         case TEST_FORCE_EN:
  81                 reg |= mode << 1;
  82                 break;
  83         default:
  84                 return -EINVAL;
  85         }
  86
  87         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  88
  89         return 0;
  90 }
  91
  92 /**
  93  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  94  * @dwc: pointer to our context structure
  95  * @state: the state to put link into
  96  *
  97  * Caller should take care of locking. This function will
  98  * return 0 on success or -ETIMEDOUT.
  99  */
 100 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
 101 {
 102         int             retries = 10000;
 103         u32             reg;
 104
 105         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 106         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 107
 108         /* set requested state */
 109         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 110         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 111
 112         /* wait for a change in DSTS */
 113         while (--retries) {
 114                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 115
 116                 if (DWC3_DSTS_USBLNKST(reg) == state)
 117                         return 0;
 118
 119                 udelay(5);
 120         }
 121
 122         dev_vdbg(dwc->dev, "link state change request timed out\n");
 123
 124         return -ETIMEDOUT;
 125 }
 126
 127 /**
 128  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 129  * @dwc: pointer to our context structure
 130  *
 131  * This function will a best effort FIFO allocation in order
 132  * to improve FIFO usage and throughput, while still allowing
 133  * us to enable as many endpoints as possible.
 134  *
 135  * Keep in mind that this operation will be highly dependent
 136  * on the configured size for RAM1 - which contains TxFifo -,
 137  * the amount of endpoints enabled on coreConsultant tool, and
 138  * the width of the Master Bus.
 139  *
 140  * In the ideal world, we would always be able to satisfy the
 141  * following equation:
 142  *
 143  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 144  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 145  *
 146  * Unfortunately, due to many variables that's not always the case.
 147  */
 148 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 149 {
 150         int             last_fifo_depth = 0;
 151         int             ram1_depth;
 152         int             fifo_size;
 153         int             mdwidth;
 154         int             num;
 155
 156         if (!dwc->needs_fifo_resize)
 157                 return 0;
 158
 159         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 160         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 161
 162         /* MDWIDTH is represented in bits, we need it in bytes */
 163         mdwidth >>= 3;
 164
 165         /*
 166          * FIXME For now we will only allocate 1 wMaxPacketSize space
 167          * for each enabled endpoint, later patches will come to
 168          * improve this algorithm so that we better use the internal
 169          * FIFO space
 170          */
 171         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 172                 struct dwc3_ep  *dep = dwc->eps[num];
 173                 int             fifo_number = dep->number >> 1;
 174                 int             mult = 1;
 175                 int             tmp;
 176
 177                 if (!(dep->number & 1))
 178                         continue;
 179
 180                 if (!(dep->flags & DWC3_EP_ENABLED))
 181                         continue;
 182
 183                 if (usb_endpoint_xfer_bulk(dep->desc)
 184                                 || usb_endpoint_xfer_isoc(dep->desc))
 185                         mult = 3;
 186
 187                 /*
 188                  * REVISIT: the following assumes we will always have enough
 189                  * space available on the FIFO RAM for all possible use cases.
 190                  * Make sure that's true somehow and change FIFO allocation
 191                  * accordingly.
 192                  *
 193                  * If we have Bulk or Isochronous endpoints, we want
 194                  * them to be able to be very, very fast. So we're giving
 195                  * those endpoints a fifo_size which is enough for 3 full
 196                  * packets
 197                  */
 198                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 199                 tmp += mdwidth;
 200
 201                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 202
 203                 fifo_size |= (last_fifo_depth << 16);
 204
 205                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 206                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 207
 208                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 209                                 fifo_size);
 210
 211                 last_fifo_depth += (fifo_size & 0xffff);
 212         }
 213
 214         return 0;
 215 }
 216
 217 void dwc3_map_buffer_to_dma(struct dwc3_request *req)
 218 {
 219         struct dwc3                     *dwc = req->dep->dwc;
 220
 221         if (req->request.length == 0) {
 222                 /* req->request.dma = dwc->setup_buf_addr; */
 223                 return;
 224         }
 225
 226         if (req->request.num_sgs) {
 227                 int     mapped;
 228
 229                 mapped = dma_map_sg(dwc->dev, req->request.sg,
 230                                 req->request.num_sgs,
 231                                 req->direction ? DMA_TO_DEVICE
 232                                 : DMA_FROM_DEVICE);
 233                 if (mapped < 0) {
 234                         dev_err(dwc->dev, "failed to map SGs\n");
 235                         return;
 236                 }
 237
 238                 req->request.num_mapped_sgs = mapped;
 239                 return;
 240         }
 241
 242         if (req->request.dma == DMA_ADDR_INVALID) {
 243                 req->request.dma = dma_map_single(dwc->dev, req->request.buf,
 244                                 req->request.length, req->direction
 245                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 246                 req->mapped = true;
 247         }
 248 }
 249
 250 void dwc3_unmap_buffer_from_dma(struct dwc3_request *req)
 251 {
 252         struct dwc3                     *dwc = req->dep->dwc;
 253
 254         if (req->request.length == 0) {
 255                 req->request.dma = DMA_ADDR_INVALID;
 256                 return;
 257         }
 258
 259         if (req->request.num_mapped_sgs) {
 260                 req->request.dma = DMA_ADDR_INVALID;
 261                 dma_unmap_sg(dwc->dev, req->request.sg,
 262                                 req->request.num_mapped_sgs,
 263                                 req->direction ? DMA_TO_DEVICE
 264                                 : DMA_FROM_DEVICE);
 265
 266                 req->request.num_mapped_sgs = 0;
 267                 return;
 268         }
 269
 270         if (req->mapped) {
 271                 dma_unmap_single(dwc->dev, req->request.dma,
 272                                 req->request.length, req->direction
 273                                 ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
 274                 req->mapped = 0;
 275                 req->request.dma = DMA_ADDR_INVALID;
 276         }
 277 }
 278
 279 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 280                 int status)
 281 {
 282         struct dwc3                     *dwc = dep->dwc;
 283
 284         if (req->queued) {
 285                 if (req->request.num_mapped_sgs)
 286                         dep->busy_slot += req->request.num_mapped_sgs;
 287                 else
 288                         dep->busy_slot++;
 289
 290                 /*
 291                  * Skip LINK TRB. We can't use req->trb and check for
 292                  * DWC3_TRBCTL_LINK_TRB because it points the TRB we just
 293                  * completed (not the LINK TRB).
 294                  */
 295                 if (((dep->busy_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 296                                 usb_endpoint_xfer_isoc(dep->desc))
 297                         dep->busy_slot++;
 298         }
 299         list_del(&req->list);
 300         req->trb = NULL;
 301
 302         if (req->request.status == -EINPROGRESS)
 303                 req->request.status = status;
 304
 305         dwc3_unmap_buffer_from_dma(req);
 306
 307         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 308                         req, dep->name, req->request.actual,
 309                         req->request.length, status);
 310
 311         spin_unlock(&dwc->lock);
 312         req->request.complete(&req->dep->endpoint, &req->request);
 313         spin_lock(&dwc->lock);
 314 }
 315
 316 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 317 {
 318         switch (cmd) {
 319         case DWC3_DEPCMD_DEPSTARTCFG:
 320                 return "Start New Configuration";
 321         case DWC3_DEPCMD_ENDTRANSFER:
 322                 return "End Transfer";
 323         case DWC3_DEPCMD_UPDATETRANSFER:
 324                 return "Update Transfer";
 325         case DWC3_DEPCMD_STARTTRANSFER:
 326                 return "Start Transfer";
 327         case DWC3_DEPCMD_CLEARSTALL:
 328                 return "Clear Stall";
 329         case DWC3_DEPCMD_SETSTALL:
 330                 return "Set Stall";
 331         case DWC3_DEPCMD_GETSEQNUMBER:
 332                 return "Get Data Sequence Number";
 333         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 334                 return "Set Endpoint Transfer Resource";
 335         case DWC3_DEPCMD_SETEPCONFIG:
 336                 return "Set Endpoint Configuration";
 337         default:
 338                 return "UNKNOWN command";
 339         }
 340 }
 341
 342 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 343                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 344 {
 345         struct dwc3_ep          *dep = dwc->eps[ep];
 346         u32                     timeout = 500;
 347         u32                     reg;
 348
 349         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 350                         dep->name,
 351                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 352                         params->param1, params->param2);
 353
 354         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 355         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 356         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 357
 358         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 359         do {
 360                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 361                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 362                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 363                                         DWC3_DEPCMD_STATUS(reg));
 364                         return 0;
 365                 }
 366
 367                 /*
 368                  * We can't sleep here, because it is also called from
 369                  * interrupt context.
 370                  */
 371                 timeout--;
 372                 if (!timeout)
 373                         return -ETIMEDOUT;
 374
 375                 udelay(1);
 376         } while (1);
 377 }
 378
 379 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 380                 struct dwc3_trb *trb)
 381 {
 382         u32             offset = (char *) trb - (char *) dep->trb_pool;
 383
 384         return dep->trb_pool_dma + offset;
 385 }
 386
 387 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 388 {
 389         struct dwc3             *dwc = dep->dwc;
 390
 391         if (dep->trb_pool)
 392                 return 0;
 393
 394         if (dep->number == 0 || dep->number == 1)
 395                 return 0;
 396
 397         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 398                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 399                         &dep->trb_pool_dma, GFP_KERNEL);
 400         if (!dep->trb_pool) {
 401                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 402                                 dep->name);
 403                 return -ENOMEM;
 404         }
 405
 406         return 0;
 407 }
 408
 409 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 410 {
 411         struct dwc3             *dwc = dep->dwc;
 412
 413         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 414                         dep->trb_pool, dep->trb_pool_dma);
 415
 416         dep->trb_pool = NULL;
 417         dep->trb_pool_dma = 0;
 418 }
 419
 420 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 421 {
 422         struct dwc3_gadget_ep_cmd_params params;
 423         u32                     cmd;
 424
 425         memset(&params, 0x00, sizeof(params));
 426
 427         if (dep->number != 1) {
 428                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 429                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 430                 if (dep->number > 1) {
 431                         if (dwc->start_config_issued)
 432                                 return 0;
 433                         dwc->start_config_issued = true;
 434                         cmd |= DWC3_DEPCMD_PARAM(2);
 435                 }
 436
 437                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 444                 const struct usb_endpoint_descriptor *desc,
 445                 const struct usb_ss_ep_comp_descriptor *comp_desc)
 446 {
 447         struct dwc3_gadget_ep_cmd_params params;
 448
 449         memset(&params, 0x00, sizeof(params));
 450
 451         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 452                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc))
 453                 | DWC3_DEPCFG_BURST_SIZE(dep->endpoint.maxburst);
 454
 455         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 456                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 457
 458         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 459                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 460                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 461                 dep->stream_capable = true;
 462         }
 463
 464         if (usb_endpoint_xfer_isoc(desc))
 465                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 466
 467         /*
 468          * We are doing 1:1 mapping for endpoints, meaning
 469          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 470          * so on. We consider the direction bit as part of the physical
 471          * endpoint number. So USB endpoint 0x81 is 0x03.
 472          */
 473         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 474
 475         /*
 476          * We must use the lower 16 TX FIFOs even though
 477          * HW might have more
 478          */
 479         if (dep->direction)
 480                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 481
 482         if (desc->bInterval) {
 483                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 484                 dep->interval = 1 << (desc->bInterval - 1);
 485         }
 486
 487         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 488                         DWC3_DEPCMD_SETEPCONFIG, &params);
 489 }
 490
 491 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 492 {
 493         struct dwc3_gadget_ep_cmd_params params;
 494
 495         memset(&params, 0x00, sizeof(params));
 496
 497         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 498
 499         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 500                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 501 }
 502
 503 /**
 504  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 505  * @dep: endpoint to be initialized
 506  * @desc: USB Endpoint Descriptor
 507  *
 508  * Caller should take care of locking
 509  */
 510 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 511                 const struct usb_endpoint_descriptor *desc,
 512                 const struct usb_ss_ep_comp_descriptor *comp_desc)
 513 {
 514         struct dwc3             *dwc = dep->dwc;
 515         u32                     reg;
 516         int                     ret = -ENOMEM;
 517
 518         if (!(dep->flags & DWC3_EP_ENABLED)) {
 519                 ret = dwc3_gadget_start_config(dwc, dep);
 520                 if (ret)
 521                         return ret;
 522         }
 523
 524         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc);
 525         if (ret)
 526                 return ret;
 527
 528         if (!(dep->flags & DWC3_EP_ENABLED)) {
 529                 struct dwc3_trb *trb_st_hw;
 530                 struct dwc3_trb *trb_link;
 531
 532                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 533                 if (ret)
 534                         return ret;
 535
 536                 dep->desc = desc;
 537                 dep->comp_desc = comp_desc;
 538                 dep->type = usb_endpoint_type(desc);
 539                 dep->flags |= DWC3_EP_ENABLED;
 540
 541                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 542                 reg |= DWC3_DALEPENA_EP(dep->number);
 543                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 544
 545                 if (!usb_endpoint_xfer_isoc(desc))
 546                         return 0;
 547
 548                 memset(&trb_link, 0, sizeof(trb_link));
 549
 550                 /* Link TRB for ISOC. The HWO bit is never reset */
 551                 trb_st_hw = &dep->trb_pool[0];
 552
 553                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 554
 555                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 556                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 557                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 558                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 559         }
 560
 561         return 0;
 562 }
 563
 564 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 565 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 566 {
 567         struct dwc3_request             *req;
 568
 569         if (!list_empty(&dep->req_queued))
 570                 dwc3_stop_active_transfer(dwc, dep->number);
 571
 572         while (!list_empty(&dep->request_list)) {
 573                 req = next_request(&dep->request_list);
 574
 575                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 576         }
 577 }
 578
 579 /**
 580  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 581  * @dep: the endpoint to disable
 582  *
 583  * This function also removes requests which are currently processed ny the
 584  * hardware and those which are not yet scheduled.
 585  * Caller should take care of locking.
 586  */
 587 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 588 {
 589         struct dwc3             *dwc = dep->dwc;
 590         u32                     reg;
 591
 592         dwc3_remove_requests(dwc, dep);
 593
 594         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 595         reg &= ~DWC3_DALEPENA_EP(dep->number);
 596         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 597
 598         dep->stream_capable = false;
 599         dep->desc = NULL;
 600         dep->comp_desc = NULL;
 601         dep->type = 0;
 602         dep->flags = 0;
 603
 604         return 0;
 605 }
 606
 607 /* -------------------------------------------------------------------------- */
 608
 609 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 610                 const struct usb_endpoint_descriptor *desc)
 611 {
 612         return -EINVAL;
 613 }
 614
 615 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 616 {
 617         return -EINVAL;
 618 }
 619
 620 /* -------------------------------------------------------------------------- */
 621
 622 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 623                 const struct usb_endpoint_descriptor *desc)
 624 {
 625         struct dwc3_ep                  *dep;
 626         struct dwc3                     *dwc;
 627         unsigned long                   flags;
 628         int                             ret;
 629
 630         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 631                 pr_debug("dwc3: invalid parameters\n");
 632                 return -EINVAL;
 633         }
 634
 635         if (!desc->wMaxPacketSize) {
 636                 pr_debug("dwc3: missing wMaxPacketSize\n");
 637                 return -EINVAL;
 638         }
 639
 640         dep = to_dwc3_ep(ep);
 641         dwc = dep->dwc;
 642
 643         switch (usb_endpoint_type(desc)) {
 644         case USB_ENDPOINT_XFER_CONTROL:
 645                 strlcat(dep->name, "-control", sizeof(dep->name));
 646                 break;
 647         case USB_ENDPOINT_XFER_ISOC:
 648                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 649                 break;
 650         case USB_ENDPOINT_XFER_BULK:
 651                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 652                 break;
 653         case USB_ENDPOINT_XFER_INT:
 654                 strlcat(dep->name, "-int", sizeof(dep->name));
 655                 break;
 656         default:
 657                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 658         }
 659
 660         if (dep->flags & DWC3_EP_ENABLED) {
 661                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 662                                 dep->name);
 663                 return 0;
 664         }
 665
 666         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 667
 668         spin_lock_irqsave(&dwc->lock, flags);
 669         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc);
 670         spin_unlock_irqrestore(&dwc->lock, flags);
 671
 672         return ret;
 673 }
 674
 675 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 676 {
 677         struct dwc3_ep                  *dep;
 678         struct dwc3                     *dwc;
 679         unsigned long                   flags;
 680         int                             ret;
 681
 682         if (!ep) {
 683                 pr_debug("dwc3: invalid parameters\n");
 684                 return -EINVAL;
 685         }
 686
 687         dep = to_dwc3_ep(ep);
 688         dwc = dep->dwc;
 689
 690         if (!(dep->flags & DWC3_EP_ENABLED)) {
 691                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 692                                 dep->name);
 693                 return 0;
 694         }
 695
 696         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 697                         dep->number >> 1,
 698                         (dep->number & 1) ? "in" : "out");
 699
 700         spin_lock_irqsave(&dwc->lock, flags);
 701         ret = __dwc3_gadget_ep_disable(dep);
 702         spin_unlock_irqrestore(&dwc->lock, flags);
 703
 704         return ret;
 705 }
 706
 707 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 708         gfp_t gfp_flags)
 709 {
 710         struct dwc3_request             *req;
 711         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 712         struct dwc3                     *dwc = dep->dwc;
 713
 714         req = kzalloc(sizeof(*req), gfp_flags);
 715         if (!req) {
 716                 dev_err(dwc->dev, "not enough memory\n");
 717                 return NULL;
 718         }
 719
 720         req->epnum      = dep->number;
 721         req->dep        = dep;
 722         req->request.dma = DMA_ADDR_INVALID;
 723
 724         return &req->request;
 725 }
 726
 727 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 728                 struct usb_request *request)
 729 {
 730         struct dwc3_request             *req = to_dwc3_request(request);
 731
 732         kfree(req);
 733 }
 734
 735 /**
 736  * dwc3_prepare_one_trb - setup one TRB from one request
 737  * @dep: endpoint for which this request is prepared
 738  * @req: dwc3_request pointer
 739  */
 740 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 741                 struct dwc3_request *req, dma_addr_t dma,
 742                 unsigned length, unsigned last, unsigned chain)
 743 {
 744         struct dwc3             *dwc = dep->dwc;
 745         struct dwc3_trb         *trb;
 746
 747         unsigned int            cur_slot;
 748
 749         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 750                         dep->name, req, (unsigned long long) dma,
 751                         length, last ? " last" : "",
 752                         chain ? " chain" : "");
 753
 754         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 755         cur_slot = dep->free_slot;
 756         dep->free_slot++;
 757
 758         /* Skip the LINK-TRB on ISOC */
 759         if (((cur_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 760                         usb_endpoint_xfer_isoc(dep->desc))
 761                 return;
 762
 763         if (!req->trb) {
 764                 dwc3_gadget_move_request_queued(req);
 765                 req->trb = trb;
 766                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 767         }
 768
 769         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 770         trb->bpl = lower_32_bits(dma);
 771         trb->bph = upper_32_bits(dma);
 772
 773         switch (usb_endpoint_type(dep->desc)) {
 774         case USB_ENDPOINT_XFER_CONTROL:
 775                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 776                 break;
 777
 778         case USB_ENDPOINT_XFER_ISOC:
 779                 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 780
 781                 /* IOC every DWC3_TRB_NUM / 4 so we can refill */
 782                 if (!(cur_slot % (DWC3_TRB_NUM / 4)))
 783                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 784                 break;
 785
 786         case USB_ENDPOINT_XFER_BULK:
 787         case USB_ENDPOINT_XFER_INT:
 788                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 789                 break;
 790         default:
 791                 /*
 792                  * This is only possible with faulty memory because we
 793                  * checked it already :)
 794                  */
 795                 BUG();
 796         }
 797
 798         if (usb_endpoint_xfer_isoc(dep->desc)) {
 799                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 800                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 801         } else {
 802                 if (chain)
 803                         trb->ctrl |= DWC3_TRB_CTRL_CHN;
 804
 805                 if (last)
 806                         trb->ctrl |= DWC3_TRB_CTRL_LST;
 807         }
 808
 809         if (usb_endpoint_xfer_bulk(dep->desc) && dep->stream_capable)
 810                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 811
 812         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 813 }
 814
 815 /*
 816  * dwc3_prepare_trbs - setup TRBs from requests
 817  * @dep: endpoint for which requests are being prepared
 818  * @starting: true if the endpoint is idle and no requests are queued.
 819  *
 820  * The function goes through the requests list and sets up TRBs for the
 821  * transfers. The function returns once there are no more TRBs available or
 822  * it runs out of requests.
 823  */
 824 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 825 {
 826         struct dwc3_request     *req, *n;
 827         u32                     trbs_left;
 828         u32                     max;
 829         unsigned int            last_one = 0;
 830
 831         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 832
 833         /* the first request must not be queued */
 834         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 835
 836         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 837         if (!usb_endpoint_xfer_isoc(dep->desc)) {
 838                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 839                 if (trbs_left > max)
 840                         trbs_left = max;
 841         }
 842
 843         /*
 844          * If busy & slot are equal than it is either full or empty. If we are
 845          * starting to process requests then we are empty. Otherwise we are
 846          * full and don't do anything
 847          */
 848         if (!trbs_left) {
 849                 if (!starting)
 850                         return;
 851                 trbs_left = DWC3_TRB_NUM;
 852                 /*
 853                  * In case we start from scratch, we queue the ISOC requests
 854                  * starting from slot 1. This is done because we use ring
 855                  * buffer and have no LST bit to stop us. Instead, we place
 856                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 857                  * after the first request so we start at slot 1 and have
 858                  * 7 requests proceed before we hit the first IOC.
 859                  * Other transfer types don't use the ring buffer and are
 860                  * processed from the first TRB until the last one. Since we
 861                  * don't wrap around we have to start at the beginning.
 862                  */
 863                 if (usb_endpoint_xfer_isoc(dep->desc)) {
 864                         dep->busy_slot = 1;
 865                         dep->free_slot = 1;
 866                 } else {
 867                         dep->busy_slot = 0;
 868                         dep->free_slot = 0;
 869                 }
 870         }
 871
 872         /* The last TRB is a link TRB, not used for xfer */
 873         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->desc))
 874                 return;
 875
 876         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 877                 unsigned        length;
 878                 dma_addr_t      dma;
 879
 880                 if (req->request.num_mapped_sgs > 0) {
 881                         struct usb_request *request = &req->request;
 882                         struct scatterlist *sg = request->sg;
 883                         struct scatterlist *s;
 884                         int             i;
 885
 886                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 887                                 unsigned chain = true;
 888
 889                                 length = sg_dma_len(s);
 890                                 dma = sg_dma_address(s);
 891
 892                                 if (i == (request->num_mapped_sgs - 1) ||
 893                                                 sg_is_last(s)) {
 894                                         last_one = true;
 895                                         chain = false;
 896                                 }
 897
 898                                 trbs_left--;
 899                                 if (!trbs_left)
 900                                         last_one = true;
 901
 902                                 if (last_one)
 903                                         chain = false;
 904
 905                                 dwc3_prepare_one_trb(dep, req, dma, length,
 906                                                 last_one, chain);
 907
 908                                 if (last_one)
 909                                         break;
 910                         }
 911                 } else {
 912                         dma = req->request.dma;
 913                         length = req->request.length;
 914                         trbs_left--;
 915
 916                         if (!trbs_left)
 917                                 last_one = 1;
 918
 919                         /* Is this the last request? */
 920                         if (list_is_last(&req->list, &dep->request_list))
 921                                 last_one = 1;
 922
 923                         dwc3_prepare_one_trb(dep, req, dma, length,
 924                                         last_one, false);
 925
 926                         if (last_one)
 927                                 break;
 928                 }
 929         }
 930 }
 931
 932 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 933                 int start_new)
 934 {
 935         struct dwc3_gadget_ep_cmd_params params;
 936         struct dwc3_request             *req;
 937         struct dwc3                     *dwc = dep->dwc;
 938         int                             ret;
 939         u32                             cmd;
 940
 941         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 942                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 943                 return -EBUSY;
 944         }
 945         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 946
 947         /*
 948          * If we are getting here after a short-out-packet we don't enqueue any
 949          * new requests as we try to set the IOC bit only on the last request.
 950          */
 951         if (start_new) {
 952                 if (list_empty(&dep->req_queued))
 953                         dwc3_prepare_trbs(dep, start_new);
 954
 955                 /* req points to the first request which will be sent */
 956                 req = next_request(&dep->req_queued);
 957         } else {
 958                 dwc3_prepare_trbs(dep, start_new);
 959
 960                 /*
 961                  * req points to the first request where HWO changed from 0 to 1
 962                  */
 963                 req = next_request(&dep->req_queued);
 964         }
 965         if (!req) {
 966                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 967                 return 0;
 968         }
 969
 970         memset(&params, 0, sizeof(params));
 971         params.param0 = upper_32_bits(req->trb_dma);
 972         params.param1 = lower_32_bits(req->trb_dma);
 973
 974         if (start_new)
 975                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 976         else
 977                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 978
 979         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
 980         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
 981         if (ret < 0) {
 982                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
 983
 984                 /*
 985                  * FIXME we need to iterate over the list of requests
 986                  * here and stop, unmap, free and del each of the linked
 987                  * requests instead of what we do now.
 988                  */
 989                 dwc3_unmap_buffer_from_dma(req);
 990                 list_del(&req->list);
 991                 return ret;
 992         }
 993
 994         dep->flags |= DWC3_EP_BUSY;
 995         dep->res_trans_idx = dwc3_gadget_ep_get_transfer_index(dwc,
 996                         dep->number);
 997
 998         WARN_ON_ONCE(!dep->res_trans_idx);
 999
1000         return 0;
1001 }
1002
1003 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1004 {
1005         req->request.actual     = 0;
1006         req->request.status     = -EINPROGRESS;
1007         req->direction          = dep->direction;
1008         req->epnum              = dep->number;
1009
1010         /*
1011          * We only add to our list of requests now and
1012          * start consuming the list once we get XferNotReady
1013          * IRQ.
1014          *
1015          * That way, we avoid doing anything that we don't need
1016          * to do now and defer it until the point we receive a
1017          * particular token from the Host side.
1018          *
1019          * This will also avoid Host cancelling URBs due to too
1020          * many NAKs.
1021          */
1022         dwc3_map_buffer_to_dma(req);
1023         list_add_tail(&req->list, &dep->request_list);
1024
1025         /*
1026          * There is one special case: XferNotReady with
1027          * empty list of requests. We need to kick the
1028          * transfer here in that situation, otherwise
1029          * we will be NAKing forever.
1030          *
1031          * If we get XferNotReady before gadget driver
1032          * has a chance to queue a request, we will ACK
1033          * the IRQ but won't be able to receive the data
1034          * until the next request is queued. The following
1035          * code is handling exactly that.
1036          */
1037         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1038                 int ret;
1039                 int start_trans;
1040
1041                 start_trans = 1;
1042                 if (usb_endpoint_xfer_isoc(dep->desc) &&
1043                                 (dep->flags & DWC3_EP_BUSY))
1044                         start_trans = 0;
1045
1046                 ret = __dwc3_gadget_kick_transfer(dep, 0, start_trans);
1047                 if (ret && ret != -EBUSY) {
1048                         struct dwc3     *dwc = dep->dwc;
1049
1050                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1051                                         dep->name);
1052                 }
1053         };
1054
1055         return 0;
1056 }
1057
1058 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1059         gfp_t gfp_flags)
1060 {
1061         struct dwc3_request             *req = to_dwc3_request(request);
1062         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1063         struct dwc3                     *dwc = dep->dwc;
1064
1065         unsigned long                   flags;
1066
1067         int                             ret;
1068
1069         if (!dep->desc) {
1070                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1071                                 request, ep->name);
1072                 return -ESHUTDOWN;
1073         }
1074
1075         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1076                         request, ep->name, request->length);
1077
1078         spin_lock_irqsave(&dwc->lock, flags);
1079         ret = __dwc3_gadget_ep_queue(dep, req);
1080         spin_unlock_irqrestore(&dwc->lock, flags);
1081
1082         return ret;
1083 }
1084
1085 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1086                 struct usb_request *request)
1087 {
1088         struct dwc3_request             *req = to_dwc3_request(request);
1089         struct dwc3_request             *r = NULL;
1090
1091         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1092         struct dwc3                     *dwc = dep->dwc;
1093
1094         unsigned long                   flags;
1095         int                             ret = 0;
1096
1097         spin_lock_irqsave(&dwc->lock, flags);
1098
1099         list_for_each_entry(r, &dep->request_list, list) {
1100                 if (r == req)
1101                         break;
1102         }
1103
1104         if (r != req) {
1105                 list_for_each_entry(r, &dep->req_queued, list) {
1106                         if (r == req)
1107                                 break;
1108                 }
1109                 if (r == req) {
1110                         /* wait until it is processed */
1111                         dwc3_stop_active_transfer(dwc, dep->number);
1112                         goto out0;
1113                 }
1114                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1115                                 request, ep->name);
1116                 ret = -EINVAL;
1117                 goto out0;
1118         }
1119
1120         /* giveback the request */
1121         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1122
1123 out0:
1124         spin_unlock_irqrestore(&dwc->lock, flags);
1125
1126         return ret;
1127 }
1128
1129 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value)
1130 {
1131         struct dwc3_gadget_ep_cmd_params        params;
1132         struct dwc3                             *dwc = dep->dwc;
1133         int                                     ret;
1134
1135         memset(&params, 0x00, sizeof(params));
1136
1137         if (value) {
1138                 if (dep->number == 0 || dep->number == 1) {
1139                         /*
1140                          * Whenever EP0 is stalled, we will restart
1141                          * the state machine, thus moving back to
1142                          * Setup Phase
1143                          */
1144                         dwc->ep0state = EP0_SETUP_PHASE;
1145                 }
1146
1147                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1148                         DWC3_DEPCMD_SETSTALL, &params);
1149                 if (ret)
1150                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1151                                         value ? "set" : "clear",
1152                                         dep->name);
1153                 else
1154                         dep->flags |= DWC3_EP_STALL;
1155         } else {
1156                 if (dep->flags & DWC3_EP_WEDGE)
1157                         return 0;
1158
1159                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1160                         DWC3_DEPCMD_CLEARSTALL, &params);
1161                 if (ret)
1162                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1163                                         value ? "set" : "clear",
1164                                         dep->name);
1165                 else
1166                         dep->flags &= ~DWC3_EP_STALL;
1167         }
1168
1169         return ret;
1170 }
1171
1172 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1173 {
1174         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1175         struct dwc3                     *dwc = dep->dwc;
1176
1177         unsigned long                   flags;
1178
1179         int                             ret;
1180
1181         spin_lock_irqsave(&dwc->lock, flags);
1182
1183         if (usb_endpoint_xfer_isoc(dep->desc)) {
1184                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1185                 ret = -EINVAL;
1186                 goto out;
1187         }
1188
1189         ret = __dwc3_gadget_ep_set_halt(dep, value);
1190 out:
1191         spin_unlock_irqrestore(&dwc->lock, flags);
1192
1193         return ret;
1194 }
1195
1196 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1197 {
1198         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1199         struct dwc3                     *dwc = dep->dwc;
1200         unsigned long                   flags;
1201
1202         spin_lock_irqsave(&dwc->lock, flags);
1203         dep->flags |= DWC3_EP_WEDGE;
1204         spin_unlock_irqrestore(&dwc->lock, flags);
1205
1206         return dwc3_gadget_ep_set_halt(ep, 1);
1207 }
1208
1209 /* -------------------------------------------------------------------------- */
1210
1211 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1212         .bLength        = USB_DT_ENDPOINT_SIZE,
1213         .bDescriptorType = USB_DT_ENDPOINT,
1214         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1215 };
1216
1217 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1218         .enable         = dwc3_gadget_ep0_enable,
1219         .disable        = dwc3_gadget_ep0_disable,
1220         .alloc_request  = dwc3_gadget_ep_alloc_request,
1221         .free_request   = dwc3_gadget_ep_free_request,
1222         .queue          = dwc3_gadget_ep0_queue,
1223         .dequeue        = dwc3_gadget_ep_dequeue,
1224         .set_halt       = dwc3_gadget_ep_set_halt,
1225         .set_wedge      = dwc3_gadget_ep_set_wedge,
1226 };
1227
1228 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1229         .enable         = dwc3_gadget_ep_enable,
1230         .disable        = dwc3_gadget_ep_disable,
1231         .alloc_request  = dwc3_gadget_ep_alloc_request,
1232         .free_request   = dwc3_gadget_ep_free_request,
1233         .queue          = dwc3_gadget_ep_queue,
1234         .dequeue        = dwc3_gadget_ep_dequeue,
1235         .set_halt       = dwc3_gadget_ep_set_halt,
1236         .set_wedge      = dwc3_gadget_ep_set_wedge,
1237 };
1238
1239 /* -------------------------------------------------------------------------- */
1240
1241 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1242 {
1243         struct dwc3             *dwc = gadget_to_dwc(g);
1244         u32                     reg;
1245
1246         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1247         return DWC3_DSTS_SOFFN(reg);
1248 }
1249
1250 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1251 {
1252         struct dwc3             *dwc = gadget_to_dwc(g);
1253
1254         unsigned long           timeout;
1255         unsigned long           flags;
1256
1257         u32                     reg;
1258
1259         int                     ret = 0;
1260
1261         u8                      link_state;
1262         u8                      speed;
1263
1264         spin_lock_irqsave(&dwc->lock, flags);
1265
1266         /*
1267          * According to the Databook Remote wakeup request should
1268          * be issued only when the device is in early suspend state.
1269          *
1270          * We can check that via USB Link State bits in DSTS register.
1271          */
1272         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1273
1274         speed = reg & DWC3_DSTS_CONNECTSPD;
1275         if (speed == DWC3_DSTS_SUPERSPEED) {
1276                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1277                 ret = -EINVAL;
1278                 goto out;
1279         }
1280
1281         link_state = DWC3_DSTS_USBLNKST(reg);
1282
1283         switch (link_state) {
1284         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1285         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1286                 break;
1287         default:
1288                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1289                                 link_state);
1290                 ret = -EINVAL;
1291                 goto out;
1292         }
1293
1294         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1295         if (ret < 0) {
1296                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1297                 goto out;
1298         }
1299
1300         /* write zeroes to Link Change Request */
1301         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1302         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1303
1304         /* poll until Link State changes to ON */
1305         timeout = jiffies + msecs_to_jiffies(100);
1306
1307         while (!time_after(jiffies, timeout)) {
1308                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1309
1310                 /* in HS, means ON */
1311                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1312                         break;
1313         }
1314
1315         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1316                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1317                 ret = -EINVAL;
1318         }
1319
1320 out:
1321         spin_unlock_irqrestore(&dwc->lock, flags);
1322
1323         return ret;
1324 }
1325
1326 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1327                 int is_selfpowered)
1328 {
1329         struct dwc3             *dwc = gadget_to_dwc(g);
1330         unsigned long           flags;
1331
1332         spin_lock_irqsave(&dwc->lock, flags);
1333         dwc->is_selfpowered = !!is_selfpowered;
1334         spin_unlock_irqrestore(&dwc->lock, flags);
1335
1336         return 0;
1337 }
1338
1339 static void dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1340 {
1341         u32                     reg;
1342         u32                     timeout = 500;
1343
1344         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1345         if (is_on) {
1346                 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1347                 reg |= (DWC3_DCTL_RUN_STOP
1348                                 | DWC3_DCTL_TRGTULST_RX_DET);
1349         } else {
1350                 reg &= ~DWC3_DCTL_RUN_STOP;
1351         }
1352
1353         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1354
1355         do {
1356                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1357                 if (is_on) {
1358                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1359                                 break;
1360                 } else {
1361                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1362                                 break;
1363                 }
1364                 timeout--;
1365                 if (!timeout)
1366                         break;
1367                 udelay(1);
1368         } while (1);
1369
1370         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1371                         dwc->gadget_driver
1372                         ? dwc->gadget_driver->function : "no-function",
1373                         is_on ? "connect" : "disconnect");
1374 }
1375
1376 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1377 {
1378         struct dwc3             *dwc = gadget_to_dwc(g);
1379         unsigned long           flags;
1380
1381         is_on = !!is_on;
1382
1383         spin_lock_irqsave(&dwc->lock, flags);
1384         dwc3_gadget_run_stop(dwc, is_on);
1385         spin_unlock_irqrestore(&dwc->lock, flags);
1386
1387         return 0;
1388 }
1389
1390 static int dwc3_gadget_start(struct usb_gadget *g,
1391                 struct usb_gadget_driver *driver)
1392 {
1393         struct dwc3             *dwc = gadget_to_dwc(g);
1394         struct dwc3_ep          *dep;
1395         unsigned long           flags;
1396         int                     ret = 0;
1397         u32                     reg;
1398
1399         spin_lock_irqsave(&dwc->lock, flags);
1400
1401         if (dwc->gadget_driver) {
1402                 dev_err(dwc->dev, "%s is already bound to %s\n",
1403                                 dwc->gadget.name,
1404                                 dwc->gadget_driver->driver.name);
1405                 ret = -EBUSY;
1406                 goto err0;
1407         }
1408
1409         dwc->gadget_driver      = driver;
1410         dwc->gadget.dev.driver  = &driver->driver;
1411
1412         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1413         reg &= ~(DWC3_DCFG_SPEED_MASK);
1414         reg |= dwc->maximum_speed;
1415         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1416
1417         dwc->start_config_issued = false;
1418
1419         /* Start with SuperSpeed Default */
1420         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1421
1422         dep = dwc->eps[0];
1423         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1424         if (ret) {
1425                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1426                 goto err0;
1427         }
1428
1429         dep = dwc->eps[1];
1430         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
1431         if (ret) {
1432                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1433                 goto err1;
1434         }
1435
1436         /* begin to receive SETUP packets */
1437         dwc->ep0state = EP0_SETUP_PHASE;
1438         dwc3_ep0_out_start(dwc);
1439
1440         spin_unlock_irqrestore(&dwc->lock, flags);
1441
1442         return 0;
1443
1444 err1:
1445         __dwc3_gadget_ep_disable(dwc->eps[0]);
1446
1447 err0:
1448         spin_unlock_irqrestore(&dwc->lock, flags);
1449
1450         return ret;
1451 }
1452
1453 static int dwc3_gadget_stop(struct usb_gadget *g,
1454                 struct usb_gadget_driver *driver)
1455 {
1456         struct dwc3             *dwc = gadget_to_dwc(g);
1457         unsigned long           flags;
1458
1459         spin_lock_irqsave(&dwc->lock, flags);
1460
1461         __dwc3_gadget_ep_disable(dwc->eps[0]);
1462         __dwc3_gadget_ep_disable(dwc->eps[1]);
1463
1464         dwc->gadget_driver      = NULL;
1465         dwc->gadget.dev.driver  = NULL;
1466
1467         spin_unlock_irqrestore(&dwc->lock, flags);
1468
1469         return 0;
1470 }
1471 static const struct usb_gadget_ops dwc3_gadget_ops = {
1472         .get_frame              = dwc3_gadget_get_frame,
1473         .wakeup                 = dwc3_gadget_wakeup,
1474         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1475         .pullup                 = dwc3_gadget_pullup,
1476         .udc_start              = dwc3_gadget_start,
1477         .udc_stop               = dwc3_gadget_stop,
1478 };
1479
1480 /* -------------------------------------------------------------------------- */
1481
1482 static int __devinit dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1483 {
1484         struct dwc3_ep                  *dep;
1485         u8                              epnum;
1486
1487         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1488
1489         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1490                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1491                 if (!dep) {
1492                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1493                                         epnum);
1494                         return -ENOMEM;
1495                 }
1496
1497                 dep->dwc = dwc;
1498                 dep->number = epnum;
1499                 dwc->eps[epnum] = dep;
1500
1501                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1502                                 (epnum & 1) ? "in" : "out");
1503                 dep->endpoint.name = dep->name;
1504                 dep->direction = (epnum & 1);
1505
1506                 if (epnum == 0 || epnum == 1) {
1507                         dep->endpoint.maxpacket = 512;
1508                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1509                         if (!epnum)
1510                                 dwc->gadget.ep0 = &dep->endpoint;
1511                 } else {
1512                         int             ret;
1513
1514                         dep->endpoint.maxpacket = 1024;
1515                         dep->endpoint.max_streams = 15;
1516                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1517                         list_add_tail(&dep->endpoint.ep_list,
1518                                         &dwc->gadget.ep_list);
1519
1520                         ret = dwc3_alloc_trb_pool(dep);
1521                         if (ret)
1522                                 return ret;
1523                 }
1524
1525                 INIT_LIST_HEAD(&dep->request_list);
1526                 INIT_LIST_HEAD(&dep->req_queued);
1527         }
1528
1529         return 0;
1530 }
1531
1532 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1533 {
1534         struct dwc3_ep                  *dep;
1535         u8                              epnum;
1536
1537         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1538                 dep = dwc->eps[epnum];
1539                 dwc3_free_trb_pool(dep);
1540
1541                 if (epnum != 0 && epnum != 1)
1542                         list_del(&dep->endpoint.ep_list);
1543
1544                 kfree(dep);
1545         }
1546 }
1547
1548 static void dwc3_gadget_release(struct device *dev)
1549 {
1550         dev_dbg(dev, "%s\n", __func__);
1551 }
1552
1553 /* -------------------------------------------------------------------------- */
1554 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1555                 const struct dwc3_event_depevt *event, int status)
1556 {
1557         struct dwc3_request     *req;
1558         struct dwc3_trb         *trb;
1559         unsigned int            count;
1560         unsigned int            s_pkt = 0;
1561
1562         do {
1563                 req = next_request(&dep->req_queued);
1564                 if (!req) {
1565                         WARN_ON_ONCE(1);
1566                         return 1;
1567                 }
1568
1569                 trb = req->trb;
1570
1571                 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1572                         /*
1573                          * We continue despite the error. There is not much we
1574                          * can do. If we don't clean it up we loop forever. If
1575                          * we skip the TRB then it gets overwritten after a
1576                          * while since we use them in a ring buffer. A BUG()
1577                          * would help. Lets hope that if this occurs, someone
1578                          * fixes the root cause instead of looking away :)
1579                          */
1580                         dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1581                                         dep->name, req->trb);
1582                 count = trb->size & DWC3_TRB_SIZE_MASK;
1583
1584                 if (dep->direction) {
1585                         if (count) {
1586                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1587                                                 dep->name);
1588                                 status = -ECONNRESET;
1589                         }
1590                 } else {
1591                         if (count && (event->status & DEPEVT_STATUS_SHORT))
1592                                 s_pkt = 1;
1593                 }
1594
1595                 /*
1596                  * We assume here we will always receive the entire data block
1597                  * which we should receive. Meaning, if we program RX to
1598                  * receive 4K but we receive only 2K, we assume that's all we
1599                  * should receive and we simply bounce the request back to the
1600                  * gadget driver for further processing.
1601                  */
1602                 req->request.actual += req->request.length - count;
1603                 dwc3_gadget_giveback(dep, req, status);
1604                 if (s_pkt)
1605                         break;
1606                 if ((event->status & DEPEVT_STATUS_LST) &&
1607                                 (trb->ctrl & DWC3_TRB_CTRL_LST))
1608                         break;
1609                 if ((event->status & DEPEVT_STATUS_IOC) &&
1610                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1611                         break;
1612         } while (1);
1613
1614         if ((event->status & DEPEVT_STATUS_IOC) &&
1615                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1616                 return 0;
1617         return 1;
1618 }
1619
1620 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1621                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1622                 int start_new)
1623 {
1624         unsigned                status = 0;
1625         int                     clean_busy;
1626
1627         if (event->status & DEPEVT_STATUS_BUSERR)
1628                 status = -ECONNRESET;
1629
1630         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1631         if (clean_busy)
1632                 dep->flags &= ~DWC3_EP_BUSY;
1633
1634         /*
1635          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1636          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1637          */
1638         if (dwc->revision < DWC3_REVISION_183A) {
1639                 u32             reg;
1640                 int             i;
1641
1642                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1643                         struct dwc3_ep  *dep = dwc->eps[i];
1644
1645                         if (!(dep->flags & DWC3_EP_ENABLED))
1646                                 continue;
1647
1648                         if (!list_empty(&dep->req_queued))
1649                                 return;
1650                 }
1651
1652                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1653                 reg |= dwc->u1u2;
1654                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1655
1656                 dwc->u1u2 = 0;
1657         }
1658 }
1659
1660 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1661                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1662 {
1663         u32 uf, mask;
1664
1665         if (list_empty(&dep->request_list)) {
1666                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1667                         dep->name);
1668                 return;
1669         }
1670
1671         mask = ~(dep->interval - 1);
1672         uf = event->parameters & mask;
1673         /* 4 micro frames in the future */
1674         uf += dep->interval * 4;
1675
1676         __dwc3_gadget_kick_transfer(dep, uf, 1);
1677 }
1678
1679 static void dwc3_process_ep_cmd_complete(struct dwc3_ep *dep,
1680                 const struct dwc3_event_depevt *event)
1681 {
1682         struct dwc3 *dwc = dep->dwc;
1683         struct dwc3_event_depevt mod_ev = *event;
1684
1685         /*
1686          * We were asked to remove one request. It is possible that this
1687          * request and a few others were started together and have the same
1688          * transfer index. Since we stopped the complete endpoint we don't
1689          * know how many requests were already completed (and not yet)
1690          * reported and how could be done (later). We purge them all until
1691          * the end of the list.
1692          */
1693         mod_ev.status = DEPEVT_STATUS_LST;
1694         dwc3_cleanup_done_reqs(dwc, dep, &mod_ev, -ESHUTDOWN);
1695         dep->flags &= ~DWC3_EP_BUSY;
1696         /* pending requests are ignored and are queued on XferNotReady */
1697 }
1698
1699 static void dwc3_ep_cmd_compl(struct dwc3_ep *dep,
1700                 const struct dwc3_event_depevt *event)
1701 {
1702         u32 param = event->parameters;
1703         u32 cmd_type = (param >> 8) & ((1 << 5) - 1);
1704
1705         switch (cmd_type) {
1706         case DWC3_DEPCMD_ENDTRANSFER:
1707                 dwc3_process_ep_cmd_complete(dep, event);
1708                 break;
1709         case DWC3_DEPCMD_STARTTRANSFER:
1710                 dep->res_trans_idx = param & 0x7f;
1711                 break;
1712         default:
1713                 printk(KERN_ERR "%s() unknown /unexpected type: %d\n",
1714                                 __func__, cmd_type);
1715                 break;
1716         };
1717 }
1718
1719 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1720                 const struct dwc3_event_depevt *event)
1721 {
1722         struct dwc3_ep          *dep;
1723         u8                      epnum = event->endpoint_number;
1724
1725         dep = dwc->eps[epnum];
1726
1727         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1728                         dwc3_ep_event_string(event->endpoint_event));
1729
1730         if (epnum == 0 || epnum == 1) {
1731                 dwc3_ep0_interrupt(dwc, event);
1732                 return;
1733         }
1734
1735         switch (event->endpoint_event) {
1736         case DWC3_DEPEVT_XFERCOMPLETE:
1737                 dep->res_trans_idx = 0;
1738
1739                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1740                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1741                                         dep->name);
1742                         return;
1743                 }
1744
1745                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1746                 break;
1747         case DWC3_DEPEVT_XFERINPROGRESS:
1748                 if (!usb_endpoint_xfer_isoc(dep->desc)) {
1749                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1750                                         dep->name);
1751                         return;
1752                 }
1753
1754                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1755                 break;
1756         case DWC3_DEPEVT_XFERNOTREADY:
1757                 if (usb_endpoint_xfer_isoc(dep->desc)) {
1758                         dwc3_gadget_start_isoc(dwc, dep, event);
1759                 } else {
1760                         int ret;
1761
1762                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1763                                         dep->name, event->status &
1764                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1765                                         ? "Transfer Active"
1766                                         : "Transfer Not Active");
1767
1768                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1769                         if (!ret || ret == -EBUSY)
1770                                 return;
1771
1772                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1773                                         dep->name);
1774                 }
1775
1776                 break;
1777         case DWC3_DEPEVT_STREAMEVT:
1778                 if (!usb_endpoint_xfer_bulk(dep->desc)) {
1779                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1780                                         dep->name);
1781                         return;
1782                 }
1783
1784                 switch (event->status) {
1785                 case DEPEVT_STREAMEVT_FOUND:
1786                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1787                                         event->parameters);
1788
1789                         break;
1790                 case DEPEVT_STREAMEVT_NOTFOUND:
1791                         /* FALLTHROUGH */
1792                 default:
1793                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1794                 }
1795                 break;
1796         case DWC3_DEPEVT_RXTXFIFOEVT:
1797                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
1798                 break;
1799         case DWC3_DEPEVT_EPCMDCMPLT:
1800                 dwc3_ep_cmd_compl(dep, event);
1801                 break;
1802         }
1803 }
1804
1805 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
1806 {
1807         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
1808                 spin_unlock(&dwc->lock);
1809                 dwc->gadget_driver->disconnect(&dwc->gadget);
1810                 spin_lock(&dwc->lock);
1811         }
1812 }
1813
1814 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
1815 {
1816         struct dwc3_ep *dep;
1817         struct dwc3_gadget_ep_cmd_params params;
1818         u32 cmd;
1819         int ret;
1820
1821         dep = dwc->eps[epnum];
1822
1823         WARN_ON(!dep->res_trans_idx);
1824         if (dep->res_trans_idx) {
1825                 cmd = DWC3_DEPCMD_ENDTRANSFER;
1826                 cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
1827                 cmd |= DWC3_DEPCMD_PARAM(dep->res_trans_idx);
1828                 memset(&params, 0, sizeof(params));
1829                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1830                 WARN_ON_ONCE(ret);
1831                 dep->res_trans_idx = 0;
1832         }
1833 }
1834
1835 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
1836 {
1837         u32 epnum;
1838
1839         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1840                 struct dwc3_ep *dep;
1841
1842                 dep = dwc->eps[epnum];
1843                 if (!(dep->flags & DWC3_EP_ENABLED))
1844                         continue;
1845
1846                 dwc3_remove_requests(dwc, dep);
1847         }
1848 }
1849
1850 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
1851 {
1852         u32 epnum;
1853
1854         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1855                 struct dwc3_ep *dep;
1856                 struct dwc3_gadget_ep_cmd_params params;
1857                 int ret;
1858
1859                 dep = dwc->eps[epnum];
1860
1861                 if (!(dep->flags & DWC3_EP_STALL))
1862                         continue;
1863
1864                 dep->flags &= ~DWC3_EP_STALL;
1865
1866                 memset(&params, 0, sizeof(params));
1867                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1868                                 DWC3_DEPCMD_CLEARSTALL, &params);
1869                 WARN_ON_ONCE(ret);
1870         }
1871 }
1872
1873 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
1874 {
1875         dev_vdbg(dwc->dev, "%s\n", __func__);
1876 #if 0
1877         XXX
1878         U1/U2 is powersave optimization. Skip it for now. Anyway we need to
1879         enable it before we can disable it.
1880
1881         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1882         reg &= ~DWC3_DCTL_INITU1ENA;
1883         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1884
1885         reg &= ~DWC3_DCTL_INITU2ENA;
1886         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1887 #endif
1888
1889         dwc3_stop_active_transfers(dwc);
1890         dwc3_disconnect_gadget(dwc);
1891         dwc->start_config_issued = false;
1892
1893         dwc->gadget.speed = USB_SPEED_UNKNOWN;
1894         dwc->setup_packet_pending = false;
1895 }
1896
1897 static void dwc3_gadget_usb3_phy_power(struct dwc3 *dwc, int on)
1898 {
1899         u32                     reg;
1900
1901         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1902
1903         if (on)
1904                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
1905         else
1906                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1907
1908         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1909 }
1910
1911 static void dwc3_gadget_usb2_phy_power(struct dwc3 *dwc, int on)
1912 {
1913         u32                     reg;
1914
1915         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1916
1917         if (on)
1918                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1919         else
1920                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1921
1922         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1923 }
1924
1925 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
1926 {
1927         u32                     reg;
1928
1929         dev_vdbg(dwc->dev, "%s\n", __func__);
1930
1931         /*
1932          * WORKAROUND: DWC3 revisions <1.88a have an issue which
1933          * would cause a missing Disconnect Event if there's a
1934          * pending Setup Packet in the FIFO.
1935          *
1936          * There's no suggested workaround on the official Bug
1937          * report, which states that "unless the driver/application
1938          * is doing any special handling of a disconnect event,
1939          * there is no functional issue".
1940          *
1941          * Unfortunately, it turns out that we _do_ some special
1942          * handling of a disconnect event, namely complete all
1943          * pending transfers, notify gadget driver of the
1944          * disconnection, and so on.
1945          *
1946          * Our suggested workaround is to follow the Disconnect
1947          * Event steps here, instead, based on a setup_packet_pending
1948          * flag. Such flag gets set whenever we have a XferNotReady
1949          * event on EP0 and gets cleared on XferComplete for the
1950          * same endpoint.
1951          *
1952          * Refers to:
1953          *
1954          * STAR#9000466709: RTL: Device : Disconnect event not
1955          * generated if setup packet pending in FIFO
1956          */
1957         if (dwc->revision < DWC3_REVISION_188A) {
1958                 if (dwc->setup_packet_pending)
1959                         dwc3_gadget_disconnect_interrupt(dwc);
1960         }
1961
1962         /* after reset -> Default State */
1963         dwc->dev_state = DWC3_DEFAULT_STATE;
1964
1965         /* Enable PHYs */
1966         dwc3_gadget_usb2_phy_power(dwc, true);
1967         dwc3_gadget_usb3_phy_power(dwc, true);
1968
1969         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
1970                 dwc3_disconnect_gadget(dwc);
1971
1972         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1973         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
1974         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1975         dwc->test_mode = false;
1976
1977         dwc3_stop_active_transfers(dwc);
1978         dwc3_clear_stall_all_ep(dwc);
1979         dwc->start_config_issued = false;
1980
1981         /* Reset device address to zero */
1982         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1983         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
1984         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1985 }
1986
1987 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
1988 {
1989         u32 reg;
1990         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
1991
1992         /*
1993          * We change the clock only at SS but I dunno why I would want to do
1994          * this. Maybe it becomes part of the power saving plan.
1995          */
1996
1997         if (speed != DWC3_DSTS_SUPERSPEED)
1998                 return;
1999
2000         /*
2001          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2002          * each time on Connect Done.
2003          */
2004         if (!usb30_clock)
2005                 return;
2006
2007         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2008         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2009         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2010 }
2011
2012 static void dwc3_gadget_disable_phy(struct dwc3 *dwc, u8 speed)
2013 {
2014         switch (speed) {
2015         case USB_SPEED_SUPER:
2016                 dwc3_gadget_usb2_phy_power(dwc, false);
2017                 break;
2018         case USB_SPEED_HIGH:
2019         case USB_SPEED_FULL:
2020         case USB_SPEED_LOW:
2021                 dwc3_gadget_usb3_phy_power(dwc, false);
2022                 break;
2023         }
2024 }
2025
2026 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2027 {
2028         struct dwc3_gadget_ep_cmd_params params;
2029         struct dwc3_ep          *dep;
2030         int                     ret;
2031         u32                     reg;
2032         u8                      speed;
2033
2034         dev_vdbg(dwc->dev, "%s\n", __func__);
2035
2036         memset(&params, 0x00, sizeof(params));
2037
2038         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2039         speed = reg & DWC3_DSTS_CONNECTSPD;
2040         dwc->speed = speed;
2041
2042         dwc3_update_ram_clk_sel(dwc, speed);
2043
2044         switch (speed) {
2045         case DWC3_DCFG_SUPERSPEED:
2046                 /*
2047                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2048                  * would cause a missing USB3 Reset event.
2049                  *
2050                  * In such situations, we should force a USB3 Reset
2051                  * event by calling our dwc3_gadget_reset_interrupt()
2052                  * routine.
2053                  *
2054                  * Refers to:
2055                  *
2056                  * STAR#9000483510: RTL: SS : USB3 reset event may
2057                  * not be generated always when the link enters poll
2058                  */
2059                 if (dwc->revision < DWC3_REVISION_190A)
2060                         dwc3_gadget_reset_interrupt(dwc);
2061
2062                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2063                 dwc->gadget.ep0->maxpacket = 512;
2064                 dwc->gadget.speed = USB_SPEED_SUPER;
2065                 break;
2066         case DWC3_DCFG_HIGHSPEED:
2067                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2068                 dwc->gadget.ep0->maxpacket = 64;
2069                 dwc->gadget.speed = USB_SPEED_HIGH;
2070                 break;
2071         case DWC3_DCFG_FULLSPEED2:
2072         case DWC3_DCFG_FULLSPEED1:
2073                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2074                 dwc->gadget.ep0->maxpacket = 64;
2075                 dwc->gadget.speed = USB_SPEED_FULL;
2076                 break;
2077         case DWC3_DCFG_LOWSPEED:
2078                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2079                 dwc->gadget.ep0->maxpacket = 8;
2080                 dwc->gadget.speed = USB_SPEED_LOW;
2081                 break;
2082         }
2083
2084         /* Disable unneded PHY */
2085         dwc3_gadget_disable_phy(dwc, dwc->gadget.speed);
2086
2087         dep = dwc->eps[0];
2088         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2089         if (ret) {
2090                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2091                 return;
2092         }
2093
2094         dep = dwc->eps[1];
2095         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL);
2096         if (ret) {
2097                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2098                 return;
2099         }
2100
2101         /*
2102          * Configure PHY via GUSB3PIPECTLn if required.
2103          *
2104          * Update GTXFIFOSIZn
2105          *
2106          * In both cases reset values should be sufficient.
2107          */
2108 }
2109
2110 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2111 {
2112         dev_vdbg(dwc->dev, "%s\n", __func__);
2113
2114         /*
2115          * TODO take core out of low power mode when that's
2116          * implemented.
2117          */
2118
2119         dwc->gadget_driver->resume(&dwc->gadget);
2120 }
2121
2122 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2123                 unsigned int evtinfo)
2124 {
2125         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2126
2127         /*
2128          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2129          * on the link partner, the USB session might do multiple entry/exit
2130          * of low power states before a transfer takes place.
2131          *
2132          * Due to this problem, we might experience lower throughput. The
2133          * suggested workaround is to disable DCTL[12:9] bits if we're
2134          * transitioning from U1/U2 to U0 and enable those bits again
2135          * after a transfer completes and there are no pending transfers
2136          * on any of the enabled endpoints.
2137          *
2138          * This is the first half of that workaround.
2139          *
2140          * Refers to:
2141          *
2142          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2143          * core send LGO_Ux entering U0
2144          */
2145         if (dwc->revision < DWC3_REVISION_183A) {
2146                 if (next == DWC3_LINK_STATE_U0) {
2147                         u32     u1u2;
2148                         u32     reg;
2149
2150                         switch (dwc->link_state) {
2151                         case DWC3_LINK_STATE_U1:
2152                         case DWC3_LINK_STATE_U2:
2153                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2154                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2155                                                 | DWC3_DCTL_ACCEPTU2ENA
2156                                                 | DWC3_DCTL_INITU1ENA
2157                                                 | DWC3_DCTL_ACCEPTU1ENA);
2158
2159                                 if (!dwc->u1u2)
2160                                         dwc->u1u2 = reg & u1u2;
2161
2162                                 reg &= ~u1u2;
2163
2164                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2165                                 break;
2166                         default:
2167                                 /* do nothing */
2168                                 break;
2169                         }
2170                 }
2171         }
2172
2173         dwc->link_state = next;
2174
2175         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2176 }
2177
2178 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2179                 const struct dwc3_event_devt *event)
2180 {
2181         switch (event->type) {
2182         case DWC3_DEVICE_EVENT_DISCONNECT:
2183                 dwc3_gadget_disconnect_interrupt(dwc);
2184                 break;
2185         case DWC3_DEVICE_EVENT_RESET:
2186                 dwc3_gadget_reset_interrupt(dwc);
2187                 break;
2188         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2189                 dwc3_gadget_conndone_interrupt(dwc);
2190                 break;
2191         case DWC3_DEVICE_EVENT_WAKEUP:
2192                 dwc3_gadget_wakeup_interrupt(dwc);
2193                 break;
2194         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2195                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2196                 break;
2197         case DWC3_DEVICE_EVENT_EOPF:
2198                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2199                 break;
2200         case DWC3_DEVICE_EVENT_SOF:
2201                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2202                 break;
2203         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2204                 dev_vdbg(dwc->dev, "Erratic Error\n");
2205                 break;
2206         case DWC3_DEVICE_EVENT_CMD_CMPL:
2207                 dev_vdbg(dwc->dev, "Command Complete\n");
2208                 break;
2209         case DWC3_DEVICE_EVENT_OVERFLOW:
2210                 dev_vdbg(dwc->dev, "Overflow\n");
2211                 break;
2212         default:
2213                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2214         }
2215 }
2216
2217 static void dwc3_process_event_entry(struct dwc3 *dwc,
2218                 const union dwc3_event *event)
2219 {
2220         /* Endpoint IRQ, handle it and return early */
2221         if (event->type.is_devspec == 0) {
2222                 /* depevt */
2223                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2224         }
2225
2226         switch (event->type.type) {
2227         case DWC3_EVENT_TYPE_DEV:
2228                 dwc3_gadget_interrupt(dwc, &event->devt);
2229                 break;
2230         /* REVISIT what to do with Carkit and I2C events ? */
2231         default:
2232                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2233         }
2234 }
2235
2236 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2237 {
2238         struct dwc3_event_buffer *evt;
2239         int left;
2240         u32 count;
2241
2242         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2243         count &= DWC3_GEVNTCOUNT_MASK;
2244         if (!count)
2245                 return IRQ_NONE;
2246
2247         evt = dwc->ev_buffs[buf];
2248         left = count;
2249
2250         while (left > 0) {
2251                 union dwc3_event event;
2252
2253                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2254
2255                 dwc3_process_event_entry(dwc, &event);
2256                 /*
2257                  * XXX we wrap around correctly to the next entry as almost all
2258                  * entries are 4 bytes in size. There is one entry which has 12
2259                  * bytes which is a regular entry followed by 8 bytes data. ATM
2260                  * I don't know how things are organized if were get next to the
2261                  * a boundary so I worry about that once we try to handle that.
2262                  */
2263                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2264                 left -= 4;
2265
2266                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2267         }
2268
2269         return IRQ_HANDLED;
2270 }
2271
2272 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2273 {
2274         struct dwc3                     *dwc = _dwc;
2275         int                             i;
2276         irqreturn_t                     ret = IRQ_NONE;
2277
2278         spin_lock(&dwc->lock);
2279
2280         for (i = 0; i < dwc->num_event_buffers; i++) {
2281                 irqreturn_t status;
2282
2283                 status = dwc3_process_event_buf(dwc, i);
2284                 if (status == IRQ_HANDLED)
2285                         ret = status;
2286         }
2287
2288         spin_unlock(&dwc->lock);
2289
2290         return ret;
2291 }
2292
2293 /**
2294  * dwc3_gadget_init - Initializes gadget related registers
2295  * @dwc: pointer to our controller context structure
2296  *
2297  * Returns 0 on success otherwise negative errno.
2298  */
2299 int __devinit dwc3_gadget_init(struct dwc3 *dwc)
2300 {
2301         u32                                     reg;
2302         int                                     ret;
2303         int                                     irq;
2304
2305         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2306                         &dwc->ctrl_req_addr, GFP_KERNEL);
2307         if (!dwc->ctrl_req) {
2308                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2309                 ret = -ENOMEM;
2310                 goto err0;
2311         }
2312
2313         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2314                         &dwc->ep0_trb_addr, GFP_KERNEL);
2315         if (!dwc->ep0_trb) {
2316                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2317                 ret = -ENOMEM;
2318                 goto err1;
2319         }
2320
2321         dwc->setup_buf = dma_alloc_coherent(dwc->dev,
2322                         sizeof(*dwc->setup_buf) * 2,
2323                         &dwc->setup_buf_addr, GFP_KERNEL);
2324         if (!dwc->setup_buf) {
2325                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2326                 ret = -ENOMEM;
2327                 goto err2;
2328         }
2329
2330         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2331                         512, &dwc->ep0_bounce_addr, GFP_KERNEL);
2332         if (!dwc->ep0_bounce) {
2333                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2334                 ret = -ENOMEM;
2335                 goto err3;
2336         }
2337
2338         dev_set_name(&dwc->gadget.dev, "gadget");
2339
2340         dwc->gadget.ops                 = &dwc3_gadget_ops;
2341         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2342         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2343         dwc->gadget.dev.parent          = dwc->dev;
2344         dwc->gadget.sg_supported        = true;
2345
2346         dma_set_coherent_mask(&dwc->gadget.dev, dwc->dev->coherent_dma_mask);
2347
2348         dwc->gadget.dev.dma_parms       = dwc->dev->dma_parms;
2349         dwc->gadget.dev.dma_mask        = dwc->dev->dma_mask;
2350         dwc->gadget.dev.release         = dwc3_gadget_release;
2351         dwc->gadget.name                = "dwc3-gadget";
2352
2353         /*
2354          * REVISIT: Here we should clear all pending IRQs to be
2355          * sure we're starting from a well known location.
2356          */
2357
2358         ret = dwc3_gadget_init_endpoints(dwc);
2359         if (ret)
2360                 goto err4;
2361
2362         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2363
2364         ret = request_irq(irq, dwc3_interrupt, IRQF_SHARED,
2365                         "dwc3", dwc);
2366         if (ret) {
2367                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
2368                                 irq, ret);
2369                 goto err5;
2370         }
2371
2372         /* Enable all but Start and End of Frame IRQs */
2373         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
2374                         DWC3_DEVTEN_EVNTOVERFLOWEN |
2375                         DWC3_DEVTEN_CMDCMPLTEN |
2376                         DWC3_DEVTEN_ERRTICERREN |
2377                         DWC3_DEVTEN_WKUPEVTEN |
2378                         DWC3_DEVTEN_ULSTCNGEN |
2379                         DWC3_DEVTEN_CONNECTDONEEN |
2380                         DWC3_DEVTEN_USBRSTEN |
2381                         DWC3_DEVTEN_DISCONNEVTEN);
2382         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
2383
2384         ret = device_register(&dwc->gadget.dev);
2385         if (ret) {
2386                 dev_err(dwc->dev, "failed to register gadget device\n");
2387                 put_device(&dwc->gadget.dev);
2388                 goto err6;
2389         }
2390
2391         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2392         if (ret) {
2393                 dev_err(dwc->dev, "failed to register udc\n");
2394                 goto err7;
2395         }
2396
2397         return 0;
2398
2399 err7:
2400         device_unregister(&dwc->gadget.dev);
2401
2402 err6:
2403         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2404         free_irq(irq, dwc);
2405
2406 err5:
2407         dwc3_gadget_free_endpoints(dwc);
2408
2409 err4:
2410         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2411                         dwc->ep0_bounce_addr);
2412
2413 err3:
2414         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2415                         dwc->setup_buf, dwc->setup_buf_addr);
2416
2417 err2:
2418         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2419                         dwc->ep0_trb, dwc->ep0_trb_addr);
2420
2421 err1:
2422         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2423                         dwc->ctrl_req, dwc->ctrl_req_addr);
2424
2425 err0:
2426         return ret;
2427 }
2428
2429 void dwc3_gadget_exit(struct dwc3 *dwc)
2430 {
2431         int                     irq;
2432
2433         usb_del_gadget_udc(&dwc->gadget);
2434         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
2435
2436         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
2437         free_irq(irq, dwc);
2438
2439         dwc3_gadget_free_endpoints(dwc);
2440
2441         dma_free_coherent(dwc->dev, 512, dwc->ep0_bounce,
2442                         dwc->ep0_bounce_addr);
2443
2444         dma_free_coherent(dwc->dev, sizeof(*dwc->setup_buf) * 2,
2445                         dwc->setup_buf, dwc->setup_buf_addr);
2446
2447         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2448                         dwc->ep0_trb, dwc->ep0_trb_addr);
2449
2450         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2451                         dwc->ctrl_req, dwc->ctrl_req_addr);
2452
2453         device_unregister(&dwc->gadget.dev);
2454 }