drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 150  * @dwc: pointer to our context structure
 151  *
 152  * This function will a best effort FIFO allocation in order
 153  * to improve FIFO usage and throughput, while still allowing
 154  * us to enable as many endpoints as possible.
 155  *
 156  * Keep in mind that this operation will be highly dependent
 157  * on the configured size for RAM1 - which contains TxFifo -,
 158  * the amount of endpoints enabled on coreConsultant tool, and
 159  * the width of the Master Bus.
 160  *
 161  * In the ideal world, we would always be able to satisfy the
 162  * following equation:
 163  *
 164  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 165  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 166  *
 167  * Unfortunately, due to many variables that's not always the case.
 168  */
 169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 170 {
 171         int             last_fifo_depth = 0;
 172         int             ram1_depth;
 173         int             fifo_size;
 174         int             mdwidth;
 175         int             num;
 176
 177         if (!dwc->needs_fifo_resize)
 178                 return 0;
 179
 180         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 181         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 182
 183         /* MDWIDTH is represented in bits, we need it in bytes */
 184         mdwidth >>= 3;
 185
 186         /*
 187          * FIXME For now we will only allocate 1 wMaxPacketSize space
 188          * for each enabled endpoint, later patches will come to
 189          * improve this algorithm so that we better use the internal
 190          * FIFO space
 191          */
 192         for (num = 0; num < dwc->num_in_eps; num++) {
 193                 /* bit0 indicates direction; 1 means IN ep */
 194                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 195                 int             mult = 1;
 196                 int             tmp;
 197
 198                 if (!(dep->flags & DWC3_EP_ENABLED))
 199                         continue;
 200
 201                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 202                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 203                         mult = 3;
 204
 205                 /*
 206                  * REVISIT: the following assumes we will always have enough
 207                  * space available on the FIFO RAM for all possible use cases.
 208                  * Make sure that's true somehow and change FIFO allocation
 209                  * accordingly.
 210                  *
 211                  * If we have Bulk or Isochronous endpoints, we want
 212                  * them to be able to be very, very fast. So we're giving
 213                  * those endpoints a fifo_size which is enough for 3 full
 214                  * packets
 215                  */
 216                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 217                 tmp += mdwidth;
 218
 219                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 220
 221                 fifo_size |= (last_fifo_depth << 16);
 222
 223                 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
 224                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 225
 226                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 227
 228                 last_fifo_depth += (fifo_size & 0xffff);
 229         }
 230
 231         return 0;
 232 }
 233
 234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 235                 int status)
 236 {
 237         struct dwc3                     *dwc = dep->dwc;
 238         int                             i;
 239
 240         if (req->queued) {
 241                 i = 0;
 242                 do {
 243                         dep->busy_slot++;
 244                         /*
 245                          * Skip LINK TRB. We can't use req->trb and check for
 246                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 247                          * just completed (not the LINK TRB).
 248                          */
 249                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 250                                 DWC3_TRB_NUM- 1) &&
 251                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 252                                 dep->busy_slot++;
 253                 } while(++i < req->request.num_mapped_sgs);
 254                 req->queued = false;
 255         }
 256         list_del(&req->list);
 257         req->trb = NULL;
 258
 259         if (req->request.status == -EINPROGRESS)
 260                 req->request.status = status;
 261
 262         if (dwc->ep0_bounced && dep->number == 0)
 263                 dwc->ep0_bounced = false;
 264         else
 265                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 266                                 req->direction);
 267
 268         trace_dwc3_gadget_giveback(req);
 269
 270         spin_unlock(&dwc->lock);
 271         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 272         spin_lock(&dwc->lock);
 273 }
 274
 275 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 276 {
 277         u32             timeout = 500;
 278         u32             reg;
 279
 280         trace_dwc3_gadget_generic_cmd(cmd, param);
 281
 282         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 283         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 284
 285         do {
 286                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 287                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 288                         dwc3_trace(trace_dwc3_gadget,
 289                                         "Command Complete --> %d",
 290                                         DWC3_DGCMD_STATUS(reg));
 291                         if (DWC3_DGCMD_STATUS(reg))
 292                                 return -EINVAL;
 293                         return 0;
 294                 }
 295
 296                 /*
 297                  * We can't sleep here, because it's also called from
 298                  * interrupt context.
 299                  */
 300                 timeout--;
 301                 if (!timeout) {
 302                         dwc3_trace(trace_dwc3_gadget,
 303                                         "Command Timed Out");
 304                         return -ETIMEDOUT;
 305                 }
 306                 udelay(1);
 307         } while (1);
 308 }
 309
 310 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 311                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 312 {
 313         struct dwc3_ep          *dep = dwc->eps[ep];
 314         u32                     timeout = 500;
 315         u32                     reg;
 316
 317         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 318
 319         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 320         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 321         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 322
 323         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 324         do {
 325                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 326                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 327                         dwc3_trace(trace_dwc3_gadget,
 328                                         "Command Complete --> %d",
 329                                         DWC3_DEPCMD_STATUS(reg));
 330                         if (DWC3_DEPCMD_STATUS(reg))
 331                                 return -EINVAL;
 332                         return 0;
 333                 }
 334
 335                 /*
 336                  * We can't sleep here, because it is also called from
 337                  * interrupt context.
 338                  */
 339                 timeout--;
 340                 if (!timeout) {
 341                         dwc3_trace(trace_dwc3_gadget,
 342                                         "Command Timed Out");
 343                         return -ETIMEDOUT;
 344                 }
 345
 346                 udelay(1);
 347         } while (1);
 348 }
 349
 350 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 351                 struct dwc3_trb *trb)
 352 {
 353         u32             offset = (char *) trb - (char *) dep->trb_pool;
 354
 355         return dep->trb_pool_dma + offset;
 356 }
 357
 358 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 359 {
 360         struct dwc3             *dwc = dep->dwc;
 361
 362         if (dep->trb_pool)
 363                 return 0;
 364
 365         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 366                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 367                         &dep->trb_pool_dma, GFP_KERNEL);
 368         if (!dep->trb_pool) {
 369                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 370                                 dep->name);
 371                 return -ENOMEM;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 378 {
 379         struct dwc3             *dwc = dep->dwc;
 380
 381         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 382                         dep->trb_pool, dep->trb_pool_dma);
 383
 384         dep->trb_pool = NULL;
 385         dep->trb_pool_dma = 0;
 386 }
 387
 388 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 389
 390 /**
 391  * dwc3_gadget_start_config - Configure EP resources
 392  * @dwc: pointer to our controller context structure
 393  * @dep: endpoint that is being enabled
 394  *
 395  * The assignment of transfer resources cannot perfectly follow the
 396  * data book due to the fact that the controller driver does not have
 397  * all knowledge of the configuration in advance. It is given this
 398  * information piecemeal by the composite gadget framework after every
 399  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 400  * programming model in this scenario can cause errors. For two
 401  * reasons:
 402  *
 403  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 404  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 405  * multiple interfaces.
 406  *
 407  * 2) The databook does not mention doing more DEPXFERCFG for new
 408  * endpoint on alt setting (8.1.6).
 409  *
 410  * The following simplified method is used instead:
 411  *
 412  * All hardware endpoints can be assigned a transfer resource and this
 413  * setting will stay persistent until either a core reset or
 414  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 415  * do DEPXFERCFG for every hardware endpoint as well. We are
 416  * guaranteed that there are as many transfer resources as endpoints.
 417  *
 418  * This function is called for each endpoint when it is being enabled
 419  * but is triggered only when called for EP0-out, which always happens
 420  * first, and which should only happen in one of the above conditions.
 421  */
 422 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 423 {
 424         struct dwc3_gadget_ep_cmd_params params;
 425         u32                     cmd;
 426         int                     i;
 427         int                     ret;
 428
 429         if (dep->number)
 430                 return 0;
 431
 432         memset(&params, 0x00, sizeof(params));
 433         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 434
 435         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 436         if (ret)
 437                 return ret;
 438
 439         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 440                 struct dwc3_ep *dep = dwc->eps[i];
 441
 442                 if (!dep)
 443                         continue;
 444
 445                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 446                 if (ret)
 447                         return ret;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 454                 const struct usb_endpoint_descriptor *desc,
 455                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 456                 bool ignore, bool restore)
 457 {
 458         struct dwc3_gadget_ep_cmd_params params;
 459
 460         memset(&params, 0x00, sizeof(params));
 461
 462         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 463                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 464
 465         /* Burst size is only needed in SuperSpeed mode */
 466         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 467                 u32 burst = dep->endpoint.maxburst - 1;
 468
 469                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 470         }
 471
 472         if (ignore)
 473                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 474
 475         if (restore) {
 476                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 477                 params.param2 |= dep->saved_state;
 478         }
 479
 480         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 481                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 482
 483         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 484                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 485                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 486                 dep->stream_capable = true;
 487         }
 488
 489         if (!usb_endpoint_xfer_control(desc))
 490                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 491
 492         /*
 493          * We are doing 1:1 mapping for endpoints, meaning
 494          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 495          * so on. We consider the direction bit as part of the physical
 496          * endpoint number. So USB endpoint 0x81 is 0x03.
 497          */
 498         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 499
 500         /*
 501          * We must use the lower 16 TX FIFOs even though
 502          * HW might have more
 503          */
 504         if (dep->direction)
 505                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 506
 507         if (desc->bInterval) {
 508                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 509                 dep->interval = 1 << (desc->bInterval - 1);
 510         }
 511
 512         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 513                         DWC3_DEPCMD_SETEPCONFIG, &params);
 514 }
 515
 516 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519
 520         memset(&params, 0x00, sizeof(params));
 521
 522         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 523
 524         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 525                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 526 }
 527
 528 /**
 529  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 530  * @dep: endpoint to be initialized
 531  * @desc: USB Endpoint Descriptor
 532  *
 533  * Caller should take care of locking
 534  */
 535 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 536                 const struct usb_endpoint_descriptor *desc,
 537                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 538                 bool ignore, bool restore)
 539 {
 540         struct dwc3             *dwc = dep->dwc;
 541         u32                     reg;
 542         int                     ret;
 543
 544         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 545
 546         if (!(dep->flags & DWC3_EP_ENABLED)) {
 547                 ret = dwc3_gadget_start_config(dwc, dep);
 548                 if (ret)
 549                         return ret;
 550         }
 551
 552         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 553                         restore);
 554         if (ret)
 555                 return ret;
 556
 557         if (!(dep->flags & DWC3_EP_ENABLED)) {
 558                 struct dwc3_trb *trb_st_hw;
 559                 struct dwc3_trb *trb_link;
 560
 561                 dep->endpoint.desc = desc;
 562                 dep->comp_desc = comp_desc;
 563                 dep->type = usb_endpoint_type(desc);
 564                 dep->flags |= DWC3_EP_ENABLED;
 565
 566                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 567                 reg |= DWC3_DALEPENA_EP(dep->number);
 568                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 569
 570                 if (!usb_endpoint_xfer_isoc(desc))
 571                         return 0;
 572
 573                 /* Link TRB for ISOC. The HWO bit is never reset */
 574                 trb_st_hw = &dep->trb_pool[0];
 575
 576                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 577                 memset(trb_link, 0, sizeof(*trb_link));
 578
 579                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 580                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 581                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 582                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 583         }
 584
 585         switch (usb_endpoint_type(desc)) {
 586         case USB_ENDPOINT_XFER_CONTROL:
 587                 strlcat(dep->name, "-control", sizeof(dep->name));
 588                 break;
 589         case USB_ENDPOINT_XFER_ISOC:
 590                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 591                 break;
 592         case USB_ENDPOINT_XFER_BULK:
 593                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 594                 break;
 595         case USB_ENDPOINT_XFER_INT:
 596                 strlcat(dep->name, "-int", sizeof(dep->name));
 597                 break;
 598         default:
 599                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 606 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 607 {
 608         struct dwc3_request             *req;
 609
 610         if (!list_empty(&dep->req_queued)) {
 611                 dwc3_stop_active_transfer(dwc, dep->number, true);
 612
 613                 /* - giveback all requests to gadget driver */
 614                 while (!list_empty(&dep->req_queued)) {
 615                         req = next_request(&dep->req_queued);
 616
 617                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 618                 }
 619         }
 620
 621         while (!list_empty(&dep->request_list)) {
 622                 req = next_request(&dep->request_list);
 623
 624                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 625         }
 626 }
 627
 628 /**
 629  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 630  * @dep: the endpoint to disable
 631  *
 632  * This function also removes requests which are currently processed ny the
 633  * hardware and those which are not yet scheduled.
 634  * Caller should take care of locking.
 635  */
 636 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 637 {
 638         struct dwc3             *dwc = dep->dwc;
 639         u32                     reg;
 640
 641         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 642
 643         dwc3_remove_requests(dwc, dep);
 644
 645         /* make sure HW endpoint isn't stalled */
 646         if (dep->flags & DWC3_EP_STALL)
 647                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 648
 649         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 650         reg &= ~DWC3_DALEPENA_EP(dep->number);
 651         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 652
 653         dep->stream_capable = false;
 654         dep->endpoint.desc = NULL;
 655         dep->comp_desc = NULL;
 656         dep->type = 0;
 657         dep->flags = 0;
 658
 659         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 660                         dep->number >> 1,
 661                         (dep->number & 1) ? "in" : "out");
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         trace_dwc3_alloc_request(req);
 755
 756         return &req->request;
 757 }
 758
 759 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 760                 struct usb_request *request)
 761 {
 762         struct dwc3_request             *req = to_dwc3_request(request);
 763
 764         trace_dwc3_free_request(req);
 765         kfree(req);
 766 }
 767
 768 /**
 769  * dwc3_prepare_one_trb - setup one TRB from one request
 770  * @dep: endpoint for which this request is prepared
 771  * @req: dwc3_request pointer
 772  */
 773 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 774                 struct dwc3_request *req, dma_addr_t dma,
 775                 unsigned length, unsigned last, unsigned chain, unsigned node)
 776 {
 777         struct dwc3_trb         *trb;
 778
 779         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 780                         dep->name, req, (unsigned long long) dma,
 781                         length, last ? " last" : "",
 782                         chain ? " chain" : "");
 783
 784
 785         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 786
 787         if (!req->trb) {
 788                 dwc3_gadget_move_request_queued(req);
 789                 req->trb = trb;
 790                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 791                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 792         }
 793
 794         dep->free_slot++;
 795         /* Skip the LINK-TRB on ISOC */
 796         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 797                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 798                 dep->free_slot++;
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814                 break;
 815
 816         case USB_ENDPOINT_XFER_BULK:
 817         case USB_ENDPOINT_XFER_INT:
 818                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 819                 break;
 820         default:
 821                 /*
 822                  * This is only possible with faulty memory because we
 823                  * checked it already :)
 824                  */
 825                 BUG();
 826         }
 827
 828         if (!req->request.no_interrupt && !chain)
 829                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 830
 831         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 832                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 833                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 834         } else if (last) {
 835                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 836         }
 837
 838         if (chain)
 839                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 840
 841         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 842                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 843
 844         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 845
 846         trace_dwc3_prepare_trb(dep, trb);
 847 }
 848
 849 /*
 850  * dwc3_prepare_trbs - setup TRBs from requests
 851  * @dep: endpoint for which requests are being prepared
 852  * @starting: true if the endpoint is idle and no requests are queued.
 853  *
 854  * The function goes through the requests list and sets up TRBs for the
 855  * transfers. The function returns once there are no more TRBs available or
 856  * it runs out of requests.
 857  */
 858 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 859 {
 860         struct dwc3_request     *req, *n;
 861         u32                     trbs_left;
 862         u32                     max;
 863         unsigned int            last_one = 0;
 864
 865         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 866
 867         /* the first request must not be queued */
 868         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 869
 870         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 871         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 872                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 873                 if (trbs_left > max)
 874                         trbs_left = max;
 875         }
 876
 877         /*
 878          * If busy & slot are equal than it is either full or empty. If we are
 879          * starting to process requests then we are empty. Otherwise we are
 880          * full and don't do anything
 881          */
 882         if (!trbs_left) {
 883                 if (!starting)
 884                         return;
 885                 trbs_left = DWC3_TRB_NUM;
 886                 /*
 887                  * In case we start from scratch, we queue the ISOC requests
 888                  * starting from slot 1. This is done because we use ring
 889                  * buffer and have no LST bit to stop us. Instead, we place
 890                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 891                  * after the first request so we start at slot 1 and have
 892                  * 7 requests proceed before we hit the first IOC.
 893                  * Other transfer types don't use the ring buffer and are
 894                  * processed from the first TRB until the last one. Since we
 895                  * don't wrap around we have to start at the beginning.
 896                  */
 897                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 898                         dep->busy_slot = 1;
 899                         dep->free_slot = 1;
 900                 } else {
 901                         dep->busy_slot = 0;
 902                         dep->free_slot = 0;
 903                 }
 904         }
 905
 906         /* The last TRB is a link TRB, not used for xfer */
 907         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 908                 return;
 909
 910         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 911                 unsigned        length;
 912                 dma_addr_t      dma;
 913                 last_one = false;
 914
 915                 if (req->request.num_mapped_sgs > 0) {
 916                         struct usb_request *request = &req->request;
 917                         struct scatterlist *sg = request->sg;
 918                         struct scatterlist *s;
 919                         int             i;
 920
 921                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 922                                 unsigned chain = true;
 923
 924                                 length = sg_dma_len(s);
 925                                 dma = sg_dma_address(s);
 926
 927                                 if (i == (request->num_mapped_sgs - 1) ||
 928                                                 sg_is_last(s)) {
 929                                         if (list_empty(&dep->request_list))
 930                                                 last_one = true;
 931                                         chain = false;
 932                                 }
 933
 934                                 trbs_left--;
 935                                 if (!trbs_left)
 936                                         last_one = true;
 937
 938                                 if (last_one)
 939                                         chain = false;
 940
 941                                 dwc3_prepare_one_trb(dep, req, dma, length,
 942                                                 last_one, chain, i);
 943
 944                                 if (last_one)
 945                                         break;
 946                         }
 947
 948                         if (last_one)
 949                                 break;
 950                 } else {
 951                         dma = req->request.dma;
 952                         length = req->request.length;
 953                         trbs_left--;
 954
 955                         if (!trbs_left)
 956                                 last_one = 1;
 957
 958                         /* Is this the last request? */
 959                         if (list_is_last(&req->list, &dep->request_list))
 960                                 last_one = 1;
 961
 962                         dwc3_prepare_one_trb(dep, req, dma, length,
 963                                         last_one, false, 0);
 964
 965                         if (last_one)
 966                                 break;
 967                 }
 968         }
 969 }
 970
 971 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 972                 int start_new)
 973 {
 974         struct dwc3_gadget_ep_cmd_params params;
 975         struct dwc3_request             *req;
 976         struct dwc3                     *dwc = dep->dwc;
 977         int                             ret;
 978         u32                             cmd;
 979
 980         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 981                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 982                 return -EBUSY;
 983         }
 984
 985         /*
 986          * If we are getting here after a short-out-packet we don't enqueue any
 987          * new requests as we try to set the IOC bit only on the last request.
 988          */
 989         if (start_new) {
 990                 if (list_empty(&dep->req_queued))
 991                         dwc3_prepare_trbs(dep, start_new);
 992
 993                 /* req points to the first request which will be sent */
 994                 req = next_request(&dep->req_queued);
 995         } else {
 996                 dwc3_prepare_trbs(dep, start_new);
 997
 998                 /*
 999                  * req points to the first request where HWO changed from 0 to 1
1000                  */
1001                 req = next_request(&dep->req_queued);
1002         }
1003         if (!req) {
1004                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1005                 return 0;
1006         }
1007
1008         memset(&params, 0, sizeof(params));
1009
1010         if (start_new) {
1011                 params.param0 = upper_32_bits(req->trb_dma);
1012                 params.param1 = lower_32_bits(req->trb_dma);
1013                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1014         } else {
1015                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1016         }
1017
1018         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1020         if (ret < 0) {
1021                 /*
1022                  * FIXME we need to iterate over the list of requests
1023                  * here and stop, unmap, free and del each of the linked
1024                  * requests instead of what we do now.
1025                  */
1026                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1027                                 req->direction);
1028                 list_del(&req->list);
1029                 return ret;
1030         }
1031
1032         dep->flags |= DWC3_EP_BUSY;
1033
1034         if (start_new) {
1035                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1036                                 dep->number);
1037                 WARN_ON_ONCE(!dep->resource_index);
1038         }
1039
1040         return 0;
1041 }
1042
1043 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044                 struct dwc3_ep *dep, u32 cur_uf)
1045 {
1046         u32 uf;
1047
1048         if (list_empty(&dep->request_list)) {
1049                 dwc3_trace(trace_dwc3_gadget,
1050                                 "ISOC ep %s run out for requests",
1051                                 dep->name);
1052                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1053                 return;
1054         }
1055
1056         /* 4 micro frames in the future */
1057         uf = cur_uf + dep->interval * 4;
1058
1059         __dwc3_gadget_kick_transfer(dep, uf, 1);
1060 }
1061
1062 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1064 {
1065         u32 cur_uf, mask;
1066
1067         mask = ~(dep->interval - 1);
1068         cur_uf = event->parameters & mask;
1069
1070         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1071 }
1072
1073 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1074 {
1075         struct dwc3             *dwc = dep->dwc;
1076         int                     ret;
1077
1078         if (!dep->endpoint.desc) {
1079                 dwc3_trace(trace_dwc3_gadget,
1080                                 "trying to queue request %p to disabled %s\n",
1081                                 &req->request, dep->endpoint.name);
1082                 return -ESHUTDOWN;
1083         }
1084
1085         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086                                 &req->request, req->dep->name)) {
1087                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088                                 &req->request, req->dep->name);
1089                 return -EINVAL;
1090         }
1091
1092         req->request.actual     = 0;
1093         req->request.status     = -EINPROGRESS;
1094         req->direction          = dep->direction;
1095         req->epnum              = dep->number;
1096
1097         trace_dwc3_ep_queue(req);
1098
1099         /*
1100          * Per databook, the total size of buffer must be a multiple
1101          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1102          * configed for endpoints in dwc3_gadget_set_ep_config(),
1103          * set to usb_endpoint_descriptor->wMaxPacketSize.
1104          */
1105         if (dep->direction == 0 &&
1106             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1107                 req->request.length = roundup(req->request.length,
1108                                         dep->endpoint.desc->wMaxPacketSize);
1109
1110         /*
1111          * We only add to our list of requests now and
1112          * start consuming the list once we get XferNotReady
1113          * IRQ.
1114          *
1115          * That way, we avoid doing anything that we don't need
1116          * to do now and defer it until the point we receive a
1117          * particular token from the Host side.
1118          *
1119          * This will also avoid Host cancelling URBs due to too
1120          * many NAKs.
1121          */
1122         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1123                         dep->direction);
1124         if (ret)
1125                 return ret;
1126
1127         list_add_tail(&req->list, &dep->request_list);
1128
1129         /*
1130          * If there are no pending requests and the endpoint isn't already
1131          * busy, we will just start the request straight away.
1132          *
1133          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1134          * little bit faster.
1135          */
1136         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1137                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1138                         !(dep->flags & DWC3_EP_BUSY)) {
1139                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1140                 goto out;
1141         }
1142
1143         /*
1144          * There are a few special cases:
1145          *
1146          * 1. XferNotReady with empty list of requests. We need to kick the
1147          *    transfer here in that situation, otherwise we will be NAKing
1148          *    forever. If we get XferNotReady before gadget driver has a
1149          *    chance to queue a request, we will ACK the IRQ but won't be
1150          *    able to receive the data until the next request is queued.
1151          *    The following code is handling exactly that.
1152          *
1153          */
1154         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1155                 /*
1156                  * If xfernotready is already elapsed and it is a case
1157                  * of isoc transfer, then issue END TRANSFER, so that
1158                  * you can receive xfernotready again and can have
1159                  * notion of current microframe.
1160                  */
1161                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1162                         if (list_empty(&dep->req_queued)) {
1163                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1164                                 dep->flags = DWC3_EP_ENABLED;
1165                         }
1166                         return 0;
1167                 }
1168
1169                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1170                 if (!ret)
1171                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1172
1173                 goto out;
1174         }
1175
1176         /*
1177          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1178          *    kick the transfer here after queuing a request, otherwise the
1179          *    core may not see the modified TRB(s).
1180          */
1181         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1182                         (dep->flags & DWC3_EP_BUSY) &&
1183                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1184                 WARN_ON_ONCE(!dep->resource_index);
1185                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1186                                 false);
1187                 goto out;
1188         }
1189
1190         /*
1191          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1192          * right away, otherwise host will not know we have streams to be
1193          * handled.
1194          */
1195         if (dep->stream_capable)
1196                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1197
1198 out:
1199         if (ret && ret != -EBUSY)
1200                 dwc3_trace(trace_dwc3_gadget,
1201                                 "%s: failed to kick transfers\n",
1202                                 dep->name);
1203         if (ret == -EBUSY)
1204                 ret = 0;
1205
1206         return ret;
1207 }
1208
1209 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1210                 struct usb_request *request)
1211 {
1212         dwc3_gadget_ep_free_request(ep, request);
1213 }
1214
1215 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1216 {
1217         struct dwc3_request             *req;
1218         struct usb_request              *request;
1219         struct usb_ep                   *ep = &dep->endpoint;
1220
1221         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1222         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1223         if (!request)
1224                 return -ENOMEM;
1225
1226         request->length = 0;
1227         request->buf = dwc->zlp_buf;
1228         request->complete = __dwc3_gadget_ep_zlp_complete;
1229
1230         req = to_dwc3_request(request);
1231
1232         return __dwc3_gadget_ep_queue(dep, req);
1233 }
1234
1235 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1236         gfp_t gfp_flags)
1237 {
1238         struct dwc3_request             *req = to_dwc3_request(request);
1239         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1240         struct dwc3                     *dwc = dep->dwc;
1241
1242         unsigned long                   flags;
1243
1244         int                             ret;
1245
1246         spin_lock_irqsave(&dwc->lock, flags);
1247         ret = __dwc3_gadget_ep_queue(dep, req);
1248
1249         /*
1250          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1251          * setting request->zero, instead of doing magic, we will just queue an
1252          * extra usb_request ourselves so that it gets handled the same way as
1253          * any other request.
1254          */
1255         if (ret == 0 && request->zero && request->length &&
1256             (request->length % ep->desc->wMaxPacketSize == 0))
1257                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1258
1259         spin_unlock_irqrestore(&dwc->lock, flags);
1260
1261         return ret;
1262 }
1263
1264 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1265                 struct usb_request *request)
1266 {
1267         struct dwc3_request             *req = to_dwc3_request(request);
1268         struct dwc3_request             *r = NULL;
1269
1270         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1271         struct dwc3                     *dwc = dep->dwc;
1272
1273         unsigned long                   flags;
1274         int                             ret = 0;
1275
1276         trace_dwc3_ep_dequeue(req);
1277
1278         spin_lock_irqsave(&dwc->lock, flags);
1279
1280         list_for_each_entry(r, &dep->request_list, list) {
1281                 if (r == req)
1282                         break;
1283         }
1284
1285         if (r != req) {
1286                 list_for_each_entry(r, &dep->req_queued, list) {
1287                         if (r == req)
1288                                 break;
1289                 }
1290                 if (r == req) {
1291                         /* wait until it is processed */
1292                         dwc3_stop_active_transfer(dwc, dep->number, true);
1293                         goto out1;
1294                 }
1295                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1296                                 request, ep->name);
1297                 ret = -EINVAL;
1298                 goto out0;
1299         }
1300
1301 out1:
1302         /* giveback the request */
1303         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1304
1305 out0:
1306         spin_unlock_irqrestore(&dwc->lock, flags);
1307
1308         return ret;
1309 }
1310
1311 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1312 {
1313         struct dwc3_gadget_ep_cmd_params        params;
1314         struct dwc3                             *dwc = dep->dwc;
1315         int                                     ret;
1316
1317         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1318                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1319                 return -EINVAL;
1320         }
1321
1322         memset(&params, 0x00, sizeof(params));
1323
1324         if (value) {
1325                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1326                                 (!list_empty(&dep->req_queued) ||
1327                                  !list_empty(&dep->request_list)))) {
1328                         dwc3_trace(trace_dwc3_gadget,
1329                                         "%s: pending request, cannot halt\n",
1330                                         dep->name);
1331                         return -EAGAIN;
1332                 }
1333
1334                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1335                         DWC3_DEPCMD_SETSTALL, &params);
1336                 if (ret)
1337                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1338                                         dep->name);
1339                 else
1340                         dep->flags |= DWC3_EP_STALL;
1341         } else {
1342                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1343                         DWC3_DEPCMD_CLEARSTALL, &params);
1344                 if (ret)
1345                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1346                                         dep->name);
1347                 else
1348                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1349         }
1350
1351         return ret;
1352 }
1353
1354 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1355 {
1356         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1357         struct dwc3                     *dwc = dep->dwc;
1358
1359         unsigned long                   flags;
1360
1361         int                             ret;
1362
1363         spin_lock_irqsave(&dwc->lock, flags);
1364         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1365         spin_unlock_irqrestore(&dwc->lock, flags);
1366
1367         return ret;
1368 }
1369
1370 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1371 {
1372         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1373         struct dwc3                     *dwc = dep->dwc;
1374         unsigned long                   flags;
1375         int                             ret;
1376
1377         spin_lock_irqsave(&dwc->lock, flags);
1378         dep->flags |= DWC3_EP_WEDGE;
1379
1380         if (dep->number == 0 || dep->number == 1)
1381                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1382         else
1383                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1384         spin_unlock_irqrestore(&dwc->lock, flags);
1385
1386         return ret;
1387 }
1388
1389 /* -------------------------------------------------------------------------- */
1390
1391 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1392         .bLength        = USB_DT_ENDPOINT_SIZE,
1393         .bDescriptorType = USB_DT_ENDPOINT,
1394         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1395 };
1396
1397 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1398         .enable         = dwc3_gadget_ep0_enable,
1399         .disable        = dwc3_gadget_ep0_disable,
1400         .alloc_request  = dwc3_gadget_ep_alloc_request,
1401         .free_request   = dwc3_gadget_ep_free_request,
1402         .queue          = dwc3_gadget_ep0_queue,
1403         .dequeue        = dwc3_gadget_ep_dequeue,
1404         .set_halt       = dwc3_gadget_ep0_set_halt,
1405         .set_wedge      = dwc3_gadget_ep_set_wedge,
1406 };
1407
1408 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1409         .enable         = dwc3_gadget_ep_enable,
1410         .disable        = dwc3_gadget_ep_disable,
1411         .alloc_request  = dwc3_gadget_ep_alloc_request,
1412         .free_request   = dwc3_gadget_ep_free_request,
1413         .queue          = dwc3_gadget_ep_queue,
1414         .dequeue        = dwc3_gadget_ep_dequeue,
1415         .set_halt       = dwc3_gadget_ep_set_halt,
1416         .set_wedge      = dwc3_gadget_ep_set_wedge,
1417 };
1418
1419 /* -------------------------------------------------------------------------- */
1420
1421 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1422 {
1423         struct dwc3             *dwc = gadget_to_dwc(g);
1424         u32                     reg;
1425
1426         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1427         return DWC3_DSTS_SOFFN(reg);
1428 }
1429
1430 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1431 {
1432         struct dwc3             *dwc = gadget_to_dwc(g);
1433
1434         unsigned long           timeout;
1435         unsigned long           flags;
1436
1437         u32                     reg;
1438
1439         int                     ret = 0;
1440
1441         u8                      link_state;
1442         u8                      speed;
1443
1444         spin_lock_irqsave(&dwc->lock, flags);
1445
1446         /*
1447          * According to the Databook Remote wakeup request should
1448          * be issued only when the device is in early suspend state.
1449          *
1450          * We can check that via USB Link State bits in DSTS register.
1451          */
1452         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1453
1454         speed = reg & DWC3_DSTS_CONNECTSPD;
1455         if (speed == DWC3_DSTS_SUPERSPEED) {
1456                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1457                 ret = -EINVAL;
1458                 goto out;
1459         }
1460
1461         link_state = DWC3_DSTS_USBLNKST(reg);
1462
1463         switch (link_state) {
1464         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1465         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1466                 break;
1467         default:
1468                 dwc3_trace(trace_dwc3_gadget,
1469                                 "can't wakeup from '%s'\n",
1470                                 dwc3_gadget_link_string(link_state));
1471                 ret = -EINVAL;
1472                 goto out;
1473         }
1474
1475         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1476         if (ret < 0) {
1477                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1478                 goto out;
1479         }
1480
1481         /* Recent versions do this automatically */
1482         if (dwc->revision < DWC3_REVISION_194A) {
1483                 /* write zeroes to Link Change Request */
1484                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1485                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1486                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1487         }
1488
1489         /* poll until Link State changes to ON */
1490         timeout = jiffies + msecs_to_jiffies(100);
1491
1492         while (!time_after(jiffies, timeout)) {
1493                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1494
1495                 /* in HS, means ON */
1496                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1497                         break;
1498         }
1499
1500         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1501                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1502                 ret = -EINVAL;
1503         }
1504
1505 out:
1506         spin_unlock_irqrestore(&dwc->lock, flags);
1507
1508         return ret;
1509 }
1510
1511 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1512                 int is_selfpowered)
1513 {
1514         struct dwc3             *dwc = gadget_to_dwc(g);
1515         unsigned long           flags;
1516
1517         spin_lock_irqsave(&dwc->lock, flags);
1518         g->is_selfpowered = !!is_selfpowered;
1519         spin_unlock_irqrestore(&dwc->lock, flags);
1520
1521         return 0;
1522 }
1523
1524 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1525 {
1526         u32                     reg;
1527         u32                     timeout = 500;
1528
1529         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1530         if (is_on) {
1531                 if (dwc->revision <= DWC3_REVISION_187A) {
1532                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1533                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1534                 }
1535
1536                 if (dwc->revision >= DWC3_REVISION_194A)
1537                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1538                 reg |= DWC3_DCTL_RUN_STOP;
1539
1540                 if (dwc->has_hibernation)
1541                         reg |= DWC3_DCTL_KEEP_CONNECT;
1542
1543                 dwc->pullups_connected = true;
1544         } else {
1545                 reg &= ~DWC3_DCTL_RUN_STOP;
1546
1547                 if (dwc->has_hibernation && !suspend)
1548                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1549
1550                 dwc->pullups_connected = false;
1551         }
1552
1553         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1554
1555         do {
1556                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1557                 if (is_on) {
1558                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1559                                 break;
1560                 } else {
1561                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1562                                 break;
1563                 }
1564                 timeout--;
1565                 if (!timeout)
1566                         return -ETIMEDOUT;
1567                 udelay(1);
1568         } while (1);
1569
1570         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1571                         dwc->gadget_driver
1572                         ? dwc->gadget_driver->function : "no-function",
1573                         is_on ? "connect" : "disconnect");
1574
1575         return 0;
1576 }
1577
1578 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1579 {
1580         struct dwc3             *dwc = gadget_to_dwc(g);
1581         unsigned long           flags;
1582         int                     ret = 0;
1583         u32                     reg;
1584
1585         is_on = !!is_on;
1586
1587         spin_lock_irqsave(&dwc->lock, flags);
1588
1589         dwc->enabled = is_on;
1590
1591         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1592
1593         if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE)
1594                 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1595
1596         spin_unlock_irqrestore(&dwc->lock, flags);
1597
1598         return ret;
1599 }
1600
1601 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1602 {
1603         u32                     reg;
1604
1605         /* Enable all but Start and End of Frame IRQs */
1606         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1607                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1608                         DWC3_DEVTEN_CMDCMPLTEN |
1609                         DWC3_DEVTEN_ERRTICERREN |
1610                         DWC3_DEVTEN_WKUPEVTEN |
1611                         DWC3_DEVTEN_ULSTCNGEN |
1612                         DWC3_DEVTEN_CONNECTDONEEN |
1613                         DWC3_DEVTEN_USBRSTEN |
1614                         DWC3_DEVTEN_DISCONNEVTEN);
1615
1616         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1617 }
1618
1619 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1620 {
1621         /* mask all interrupts */
1622         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1623 }
1624
1625 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1626 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1627
1628 static int dwc3_gadget_start(struct usb_gadget *g,
1629                 struct usb_gadget_driver *driver)
1630 {
1631         struct dwc3             *dwc = gadget_to_dwc(g);
1632         struct dwc3_ep          *dep;
1633         unsigned long           flags;
1634         int                     ret = 0;
1635         int                     irq;
1636         u32                     reg;
1637
1638         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1639         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1640                         IRQF_SHARED, "dwc3", dwc);
1641         if (ret) {
1642                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1643                                 irq, ret);
1644                 goto err0;
1645         }
1646
1647         spin_lock_irqsave(&dwc->lock, flags);
1648
1649         if (dwc->gadget_driver) {
1650                 dev_err(dwc->dev, "%s is already bound to %s\n",
1651                                 dwc->gadget.name,
1652                                 dwc->gadget_driver->driver.name);
1653                 ret = -EBUSY;
1654                 goto err1;
1655         }
1656
1657         dwc->gadget_driver      = driver;
1658
1659         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1660         if (DWC3_GCTL_PRTCAP(reg) != DWC3_GCTL_PRTCAP_DEVICE)
1661                 goto mode_mismatch;
1662
1663         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1664         reg &= ~(DWC3_DCFG_SPEED_MASK);
1665
1666         /**
1667          * WORKAROUND: DWC3 revision < 2.20a have an issue
1668          * which would cause metastability state on Run/Stop
1669          * bit if we try to force the IP to USB2-only mode.
1670          *
1671          * Because of that, we cannot configure the IP to any
1672          * speed other than the SuperSpeed
1673          *
1674          * Refers to:
1675          *
1676          * STAR#9000525659: Clock Domain Crossing on DCTL in
1677          * USB 2.0 Mode
1678          */
1679         if (dwc->revision < DWC3_REVISION_220A) {
1680                 reg |= DWC3_DCFG_SUPERSPEED;
1681         } else {
1682                 switch (dwc->maximum_speed) {
1683                 case USB_SPEED_LOW:
1684                         reg |= DWC3_DSTS_LOWSPEED;
1685                         break;
1686                 case USB_SPEED_FULL:
1687                         reg |= DWC3_DSTS_FULLSPEED1;
1688                         break;
1689                 case USB_SPEED_HIGH:
1690                         reg |= DWC3_DSTS_HIGHSPEED;
1691                         break;
1692                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1693                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1694                 default:
1695                         reg |= DWC3_DSTS_SUPERSPEED;
1696                 }
1697         }
1698         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1699
1700         /* Start with SuperSpeed Default */
1701         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1702
1703         dep = dwc->eps[0];
1704         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1705                         false);
1706         if (ret) {
1707                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1708                 goto err2;
1709         }
1710
1711         dep = dwc->eps[1];
1712         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1713                         false);
1714         if (ret) {
1715                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1716                 goto err3;
1717         }
1718
1719         /* begin to receive SETUP packets */
1720         dwc->ep0state = EP0_SETUP_PHASE;
1721         dwc3_ep0_out_start(dwc);
1722
1723         dwc3_gadget_enable_irq(dwc);
1724
1725 mode_mismatch:
1726         spin_unlock_irqrestore(&dwc->lock, flags);
1727
1728         return 0;
1729
1730 err3:
1731         __dwc3_gadget_ep_disable(dwc->eps[0]);
1732
1733 err2:
1734         dwc->gadget_driver = NULL;
1735
1736 err1:
1737         spin_unlock_irqrestore(&dwc->lock, flags);
1738
1739         free_irq(irq, dwc);
1740
1741 err0:
1742         return ret;
1743 }
1744
1745 static int dwc3_gadget_stop(struct usb_gadget *g)
1746 {
1747         struct dwc3             *dwc = gadget_to_dwc(g);
1748         unsigned long           flags;
1749         int                     irq;
1750         u32                     reg;
1751
1752         spin_lock_irqsave(&dwc->lock, flags);
1753
1754         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1755
1756         if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE) {
1757                 dwc3_gadget_disable_irq(dwc);
1758                 __dwc3_gadget_ep_disable(dwc->eps[0]);
1759                 __dwc3_gadget_ep_disable(dwc->eps[1]);
1760         }
1761
1762         dwc->gadget_driver      = NULL;
1763
1764         spin_unlock_irqrestore(&dwc->lock, flags);
1765
1766         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1767         free_irq(irq, dwc);
1768
1769         return 0;
1770 }
1771
1772 static const struct usb_gadget_ops dwc3_gadget_ops = {
1773         .get_frame              = dwc3_gadget_get_frame,
1774         .wakeup                 = dwc3_gadget_wakeup,
1775         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1776         .pullup                 = dwc3_gadget_pullup,
1777         .udc_start              = dwc3_gadget_start,
1778         .udc_stop               = dwc3_gadget_stop,
1779 };
1780
1781 /* -------------------------------------------------------------------------- */
1782
1783 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1784                 u8 num, u32 direction)
1785 {
1786         struct dwc3_ep                  *dep;
1787         u8                              i;
1788
1789         for (i = 0; i < num; i++) {
1790                 u8 epnum = (i << 1) | (!!direction);
1791
1792                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1793                 if (!dep)
1794                         return -ENOMEM;
1795
1796                 dep->dwc = dwc;
1797                 dep->number = epnum;
1798                 dep->direction = !!direction;
1799                 dwc->eps[epnum] = dep;
1800
1801                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1802                                 (epnum & 1) ? "in" : "out");
1803
1804                 dep->endpoint.name = dep->name;
1805
1806                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1807
1808                 if (epnum == 0 || epnum == 1) {
1809                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1810                         dep->endpoint.maxburst = 1;
1811                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1812                         if (!epnum)
1813                                 dwc->gadget.ep0 = &dep->endpoint;
1814                 } else {
1815                         int             ret;
1816
1817                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1818                         dep->endpoint.max_streams = 15;
1819                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1820                         list_add_tail(&dep->endpoint.ep_list,
1821                                         &dwc->gadget.ep_list);
1822
1823                         ret = dwc3_alloc_trb_pool(dep);
1824                         if (ret)
1825                                 return ret;
1826                 }
1827
1828                 if (epnum == 0 || epnum == 1) {
1829                         dep->endpoint.caps.type_control = true;
1830                 } else {
1831                         dep->endpoint.caps.type_iso = true;
1832                         dep->endpoint.caps.type_bulk = true;
1833                         dep->endpoint.caps.type_int = true;
1834                 }
1835
1836                 dep->endpoint.caps.dir_in = !!direction;
1837                 dep->endpoint.caps.dir_out = !direction;
1838
1839                 INIT_LIST_HEAD(&dep->request_list);
1840                 INIT_LIST_HEAD(&dep->req_queued);
1841         }
1842
1843         return 0;
1844 }
1845
1846 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1847 {
1848         int                             ret;
1849
1850         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1851
1852         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1853         if (ret < 0) {
1854                 dwc3_trace(trace_dwc3_gadget,
1855                                 "failed to allocate OUT endpoints");
1856                 return ret;
1857         }
1858
1859         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1860         if (ret < 0) {
1861                 dwc3_trace(trace_dwc3_gadget,
1862                                 "failed to allocate IN endpoints");
1863                 return ret;
1864         }
1865
1866         return 0;
1867 }
1868
1869 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1870 {
1871         struct dwc3_ep                  *dep;
1872         u8                              epnum;
1873
1874         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1875                 dep = dwc->eps[epnum];
1876                 if (!dep)
1877                         continue;
1878                 /*
1879                  * Physical endpoints 0 and 1 are special; they form the
1880                  * bi-directional USB endpoint 0.
1881                  *
1882                  * For those two physical endpoints, we don't allocate a TRB
1883                  * pool nor do we add them the endpoints list. Due to that, we
1884                  * shouldn't do these two operations otherwise we would end up
1885                  * with all sorts of bugs when removing dwc3.ko.
1886                  */
1887                 if (epnum != 0 && epnum != 1) {
1888                         dwc3_free_trb_pool(dep);
1889                         list_del(&dep->endpoint.ep_list);
1890                 }
1891
1892                 kfree(dep);
1893         }
1894 }
1895
1896 /* -------------------------------------------------------------------------- */
1897
1898 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1899                 struct dwc3_request *req, struct dwc3_trb *trb,
1900                 const struct dwc3_event_depevt *event, int status)
1901 {
1902         unsigned int            count;
1903         unsigned int            s_pkt = 0;
1904         unsigned int            trb_status;
1905
1906         trace_dwc3_complete_trb(dep, trb);
1907
1908         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1909                 /*
1910                  * We continue despite the error. There is not much we
1911                  * can do. If we don't clean it up we loop forever. If
1912                  * we skip the TRB then it gets overwritten after a
1913                  * while since we use them in a ring buffer. A BUG()
1914                  * would help. Lets hope that if this occurs, someone
1915                  * fixes the root cause instead of looking away :)
1916                  */
1917                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1918                                 dep->name, trb);
1919         count = trb->size & DWC3_TRB_SIZE_MASK;
1920
1921         if (dep->direction) {
1922                 if (count) {
1923                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1924                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1925                                 dwc3_trace(trace_dwc3_gadget,
1926                                                 "%s: incomplete IN transfer\n",
1927                                                 dep->name);
1928                                 /*
1929                                  * If missed isoc occurred and there is
1930                                  * no request queued then issue END
1931                                  * TRANSFER, so that core generates
1932                                  * next xfernotready and we will issue
1933                                  * a fresh START TRANSFER.
1934                                  * If there are still queued request
1935                                  * then wait, do not issue either END
1936                                  * or UPDATE TRANSFER, just attach next
1937                                  * request in request_list during
1938                                  * giveback.If any future queued request
1939                                  * is successfully transferred then we
1940                                  * will issue UPDATE TRANSFER for all
1941                                  * request in the request_list.
1942                                  */
1943                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1944                         } else {
1945                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1946                                                 dep->name);
1947                                 status = -ECONNRESET;
1948                         }
1949                 } else {
1950                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1951                 }
1952         } else {
1953                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1954                         s_pkt = 1;
1955         }
1956
1957         /*
1958          * We assume here we will always receive the entire data block
1959          * which we should receive. Meaning, if we program RX to
1960          * receive 4K but we receive only 2K, we assume that's all we
1961          * should receive and we simply bounce the request back to the
1962          * gadget driver for further processing.
1963          */
1964         req->request.actual += req->request.length - count;
1965         if (s_pkt)
1966                 return 1;
1967         if ((event->status & DEPEVT_STATUS_LST) &&
1968                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1969                                 DWC3_TRB_CTRL_HWO)))
1970                 return 1;
1971         if ((event->status & DEPEVT_STATUS_IOC) &&
1972                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1973                 return 1;
1974         return 0;
1975 }
1976
1977 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1978                 const struct dwc3_event_depevt *event, int status)
1979 {
1980         struct dwc3_request     *req;
1981         struct dwc3_trb         *trb;
1982         unsigned int            slot;
1983         unsigned int            i;
1984         int                     ret;
1985
1986         do {
1987                 req = next_request(&dep->req_queued);
1988                 if (WARN_ON_ONCE(!req))
1989                         return 1;
1990
1991                 i = 0;
1992                 do {
1993                         slot = req->start_slot + i;
1994                         if ((slot == DWC3_TRB_NUM - 1) &&
1995                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1996                                 slot++;
1997                         slot %= DWC3_TRB_NUM;
1998                         trb = &dep->trb_pool[slot];
1999
2000                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2001                                         event, status);
2002                         if (ret)
2003                                 break;
2004                 } while (++i < req->request.num_mapped_sgs);
2005
2006                 dwc3_gadget_giveback(dep, req, status);
2007
2008                 if (ret)
2009                         break;
2010         } while (1);
2011
2012         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2013                         list_empty(&dep->req_queued)) {
2014                 if (list_empty(&dep->request_list)) {
2015                         /*
2016                          * If there is no entry in request list then do
2017                          * not issue END TRANSFER now. Just set PENDING
2018                          * flag, so that END TRANSFER is issued when an
2019                          * entry is added into request list.
2020                          */
2021                         dep->flags = DWC3_EP_PENDING_REQUEST;
2022                 } else {
2023                         dwc3_stop_active_transfer(dwc, dep->number, true);
2024                         dep->flags = DWC3_EP_ENABLED;
2025                 }
2026                 return 1;
2027         }
2028
2029         return 1;
2030 }
2031
2032 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2033                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2034 {
2035         unsigned                status = 0;
2036         int                     clean_busy;
2037         u32                     is_xfer_complete;
2038
2039         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2040
2041         if (event->status & DEPEVT_STATUS_BUSERR)
2042                 status = -ECONNRESET;
2043
2044         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2045         if (clean_busy && (is_xfer_complete ||
2046                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2047                 dep->flags &= ~DWC3_EP_BUSY;
2048
2049         /*
2050          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2051          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2052          */
2053         if (dwc->revision < DWC3_REVISION_183A) {
2054                 u32             reg;
2055                 int             i;
2056
2057                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2058                         dep = dwc->eps[i];
2059
2060                         if (!(dep->flags & DWC3_EP_ENABLED))
2061                                 continue;
2062
2063                         if (!list_empty(&dep->req_queued))
2064                                 return;
2065                 }
2066
2067                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2068                 reg |= dwc->u1u2;
2069                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2070
2071                 dwc->u1u2 = 0;
2072         }
2073
2074         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2075                 int ret;
2076
2077                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2078                 if (!ret || ret == -EBUSY)
2079                         return;
2080         }
2081 }
2082
2083 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2084                 const struct dwc3_event_depevt *event)
2085 {
2086         struct dwc3_ep          *dep;
2087         u8                      epnum = event->endpoint_number;
2088
2089         dep = dwc->eps[epnum];
2090
2091         if (!(dep->flags & DWC3_EP_ENABLED))
2092                 return;
2093
2094         if (epnum == 0 || epnum == 1) {
2095                 dwc3_ep0_interrupt(dwc, event);
2096                 return;
2097         }
2098
2099         switch (event->endpoint_event) {
2100         case DWC3_DEPEVT_XFERCOMPLETE:
2101                 dep->resource_index = 0;
2102
2103                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2104                         dwc3_trace(trace_dwc3_gadget,
2105                                         "%s is an Isochronous endpoint\n",
2106                                         dep->name);
2107                         return;
2108                 }
2109
2110                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2111                 break;
2112         case DWC3_DEPEVT_XFERINPROGRESS:
2113                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2114                 break;
2115         case DWC3_DEPEVT_XFERNOTREADY:
2116                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2117                         dwc3_gadget_start_isoc(dwc, dep, event);
2118                 } else {
2119                         int active;
2120                         int ret;
2121
2122                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2123
2124                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2125                                         dep->name, active ? "Transfer Active"
2126                                         : "Transfer Not Active");
2127
2128                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2129                         if (!ret || ret == -EBUSY)
2130                                 return;
2131
2132                         dwc3_trace(trace_dwc3_gadget,
2133                                         "%s: failed to kick transfers\n",
2134                                         dep->name);
2135                 }
2136
2137                 break;
2138         case DWC3_DEPEVT_STREAMEVT:
2139                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2140                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2141                                         dep->name);
2142                         return;
2143                 }
2144
2145                 switch (event->status) {
2146                 case DEPEVT_STREAMEVT_FOUND:
2147                         dwc3_trace(trace_dwc3_gadget,
2148                                         "Stream %d found and started",
2149                                         event->parameters);
2150
2151                         break;
2152                 case DEPEVT_STREAMEVT_NOTFOUND:
2153                         /* FALLTHROUGH */
2154                 default:
2155                         dwc3_trace(trace_dwc3_gadget,
2156                                         "unable to find suitable stream\n");
2157                 }
2158                 break;
2159         case DWC3_DEPEVT_RXTXFIFOEVT:
2160                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2161                 break;
2162         case DWC3_DEPEVT_EPCMDCMPLT:
2163                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2164                 break;
2165         }
2166 }
2167
2168 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2169 {
2170         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2171                 spin_unlock(&dwc->lock);
2172                 dwc->gadget_driver->disconnect(&dwc->gadget);
2173                 spin_lock(&dwc->lock);
2174         }
2175 }
2176
2177 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2178 {
2179         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2180                 spin_unlock(&dwc->lock);
2181                 dwc->gadget_driver->suspend(&dwc->gadget);
2182                 spin_lock(&dwc->lock);
2183         }
2184 }
2185
2186 static void dwc3_resume_gadget(struct dwc3 *dwc)
2187 {
2188         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2189                 spin_unlock(&dwc->lock);
2190                 dwc->gadget_driver->resume(&dwc->gadget);
2191                 spin_lock(&dwc->lock);
2192         }
2193 }
2194
2195 static void dwc3_reset_gadget(struct dwc3 *dwc)
2196 {
2197         if (!dwc->gadget_driver)
2198                 return;
2199
2200         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2201                 spin_unlock(&dwc->lock);
2202                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2203                 spin_lock(&dwc->lock);
2204         }
2205 }
2206
2207 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2208 {
2209         struct dwc3_ep *dep;
2210         struct dwc3_gadget_ep_cmd_params params;
2211         u32 cmd;
2212         int ret;
2213
2214         dep = dwc->eps[epnum];
2215
2216         if (!dep->resource_index)
2217                 return;
2218
2219         /*
2220          * NOTICE: We are violating what the Databook says about the
2221          * EndTransfer command. Ideally we would _always_ wait for the
2222          * EndTransfer Command Completion IRQ, but that's causing too
2223          * much trouble synchronizing between us and gadget driver.
2224          *
2225          * We have discussed this with the IP Provider and it was
2226          * suggested to giveback all requests here, but give HW some
2227          * extra time to synchronize with the interconnect. We're using
2228          * an arbitrary 100us delay for that.
2229          *
2230          * Note also that a similar handling was tested by Synopsys
2231          * (thanks a lot Paul) and nothing bad has come out of it.
2232          * In short, what we're doing is:
2233          *
2234          * - Issue EndTransfer WITH CMDIOC bit set
2235          * - Wait 100us
2236          */
2237
2238         cmd = DWC3_DEPCMD_ENDTRANSFER;
2239         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2240         cmd |= DWC3_DEPCMD_CMDIOC;
2241         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2242         memset(&params, 0, sizeof(params));
2243         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2244         WARN_ON_ONCE(ret);
2245         dep->resource_index = 0;
2246         dep->flags &= ~DWC3_EP_BUSY;
2247         udelay(100);
2248 }
2249
2250 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2251 {
2252         u32 epnum;
2253
2254         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2255                 struct dwc3_ep *dep;
2256
2257                 dep = dwc->eps[epnum];
2258                 if (!dep)
2259                         continue;
2260
2261                 if (!(dep->flags & DWC3_EP_ENABLED))
2262                         continue;
2263
2264                 dwc3_remove_requests(dwc, dep);
2265         }
2266 }
2267
2268 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2269 {
2270         u32 epnum;
2271
2272         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2273                 struct dwc3_ep *dep;
2274                 struct dwc3_gadget_ep_cmd_params params;
2275                 int ret;
2276
2277                 dep = dwc->eps[epnum];
2278                 if (!dep)
2279                         continue;
2280
2281                 if (!(dep->flags & DWC3_EP_STALL))
2282                         continue;
2283
2284                 dep->flags &= ~DWC3_EP_STALL;
2285
2286                 memset(&params, 0, sizeof(params));
2287                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2288                                 DWC3_DEPCMD_CLEARSTALL, &params);
2289                 WARN_ON_ONCE(ret);
2290         }
2291 }
2292
2293 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2294 {
2295         int                     reg;
2296
2297         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2298         reg &= ~DWC3_DCTL_INITU1ENA;
2299         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2300
2301         reg &= ~DWC3_DCTL_INITU2ENA;
2302         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2303
2304         dwc3_disconnect_gadget(dwc);
2305
2306         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2307         dwc->setup_packet_pending = false;
2308         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2309 }
2310
2311 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2312 {
2313         u32                     reg;
2314
2315         /*
2316          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2317          * would cause a missing Disconnect Event if there's a
2318          * pending Setup Packet in the FIFO.
2319          *
2320          * There's no suggested workaround on the official Bug
2321          * report, which states that "unless the driver/application
2322          * is doing any special handling of a disconnect event,
2323          * there is no functional issue".
2324          *
2325          * Unfortunately, it turns out that we _do_ some special
2326          * handling of a disconnect event, namely complete all
2327          * pending transfers, notify gadget driver of the
2328          * disconnection, and so on.
2329          *
2330          * Our suggested workaround is to follow the Disconnect
2331          * Event steps here, instead, based on a setup_packet_pending
2332          * flag. Such flag gets set whenever we have a SETUP_PENDING
2333          * status for EP0 TRBs and gets cleared on XferComplete for the
2334          * same endpoint.
2335          *
2336          * Refers to:
2337          *
2338          * STAR#9000466709: RTL: Device : Disconnect event not
2339          * generated if setup packet pending in FIFO
2340          */
2341         if (dwc->revision < DWC3_REVISION_188A) {
2342                 if (dwc->setup_packet_pending)
2343                         dwc3_gadget_disconnect_interrupt(dwc);
2344         }
2345
2346         dwc3_reset_gadget(dwc);
2347
2348         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2349         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2350         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2351         dwc->test_mode = false;
2352
2353         dwc3_stop_active_transfers(dwc);
2354         dwc3_clear_stall_all_ep(dwc);
2355
2356         /* Reset device address to zero */
2357         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2358         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2359         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2360 }
2361
2362 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2363 {
2364         u32 reg;
2365         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2366
2367         /*
2368          * We change the clock only at SS but I dunno why I would want to do
2369          * this. Maybe it becomes part of the power saving plan.
2370          */
2371
2372         if (speed != DWC3_DSTS_SUPERSPEED)
2373                 return;
2374
2375         /*
2376          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2377          * each time on Connect Done.
2378          */
2379         if (!usb30_clock)
2380                 return;
2381
2382         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2383         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2384         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2385 }
2386
2387 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2388 {
2389         struct dwc3_ep          *dep;
2390         int                     ret;
2391         u32                     reg;
2392         u8                      speed;
2393
2394         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2395         speed = reg & DWC3_DSTS_CONNECTSPD;
2396         dwc->speed = speed;
2397
2398         dwc3_update_ram_clk_sel(dwc, speed);
2399
2400         switch (speed) {
2401         case DWC3_DCFG_SUPERSPEED:
2402                 /*
2403                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2404                  * would cause a missing USB3 Reset event.
2405                  *
2406                  * In such situations, we should force a USB3 Reset
2407                  * event by calling our dwc3_gadget_reset_interrupt()
2408                  * routine.
2409                  *
2410                  * Refers to:
2411                  *
2412                  * STAR#9000483510: RTL: SS : USB3 reset event may
2413                  * not be generated always when the link enters poll
2414                  */
2415                 if (dwc->revision < DWC3_REVISION_190A)
2416                         dwc3_gadget_reset_interrupt(dwc);
2417
2418                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2419                 dwc->gadget.ep0->maxpacket = 512;
2420                 dwc->gadget.speed = USB_SPEED_SUPER;
2421                 break;
2422         case DWC3_DCFG_HIGHSPEED:
2423                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2424                 dwc->gadget.ep0->maxpacket = 64;
2425                 dwc->gadget.speed = USB_SPEED_HIGH;
2426                 break;
2427         case DWC3_DCFG_FULLSPEED2:
2428         case DWC3_DCFG_FULLSPEED1:
2429                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2430                 dwc->gadget.ep0->maxpacket = 64;
2431                 dwc->gadget.speed = USB_SPEED_FULL;
2432                 break;
2433         case DWC3_DCFG_LOWSPEED:
2434                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2435                 dwc->gadget.ep0->maxpacket = 8;
2436                 dwc->gadget.speed = USB_SPEED_LOW;
2437                 break;
2438         }
2439
2440         /* Enable USB2 LPM Capability */
2441
2442         if ((dwc->revision > DWC3_REVISION_194A)
2443                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2444                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2445                 reg |= DWC3_DCFG_LPM_CAP;
2446                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2447
2448                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2449                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2450
2451                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2452
2453                 /*
2454                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2455                  * DCFG.LPMCap is set, core responses with an ACK and the
2456                  * BESL value in the LPM token is less than or equal to LPM
2457                  * NYET threshold.
2458                  */
2459                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2460                                 && dwc->has_lpm_erratum,
2461                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2462
2463                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2464                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2465
2466                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2467         } else {
2468                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2469                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2470                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2471         }
2472
2473         dep = dwc->eps[0];
2474         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2475                         false);
2476         if (ret) {
2477                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2478                 return;
2479         }
2480
2481         dep = dwc->eps[1];
2482         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2483                         false);
2484         if (ret) {
2485                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2486                 return;
2487         }
2488
2489         /*
2490          * Configure PHY via GUSB3PIPECTLn if required.
2491          *
2492          * Update GTXFIFOSIZn
2493          *
2494          * In both cases reset values should be sufficient.
2495          */
2496 }
2497
2498 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2499 {
2500         /*
2501          * TODO take core out of low power mode when that's
2502          * implemented.
2503          */
2504
2505         dwc->gadget_driver->resume(&dwc->gadget);
2506 }
2507
2508 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2509                 unsigned int evtinfo)
2510 {
2511         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2512         unsigned int            pwropt;
2513
2514         /*
2515          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2516          * Hibernation mode enabled which would show up when device detects
2517          * host-initiated U3 exit.
2518          *
2519          * In that case, device will generate a Link State Change Interrupt
2520          * from U3 to RESUME which is only necessary if Hibernation is
2521          * configured in.
2522          *
2523          * There are no functional changes due to such spurious event and we
2524          * just need to ignore it.
2525          *
2526          * Refers to:
2527          *
2528          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2529          * operational mode
2530          */
2531         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2532         if ((dwc->revision < DWC3_REVISION_250A) &&
2533                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2534                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2535                                 (next == DWC3_LINK_STATE_RESUME)) {
2536                         dwc3_trace(trace_dwc3_gadget,
2537                                         "ignoring transition U3 -> Resume");
2538                         return;
2539                 }
2540         }
2541
2542         /*
2543          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2544          * on the link partner, the USB session might do multiple entry/exit
2545          * of low power states before a transfer takes place.
2546          *
2547          * Due to this problem, we might experience lower throughput. The
2548          * suggested workaround is to disable DCTL[12:9] bits if we're
2549          * transitioning from U1/U2 to U0 and enable those bits again
2550          * after a transfer completes and there are no pending transfers
2551          * on any of the enabled endpoints.
2552          *
2553          * This is the first half of that workaround.
2554          *
2555          * Refers to:
2556          *
2557          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2558          * core send LGO_Ux entering U0
2559          */
2560         if (dwc->revision < DWC3_REVISION_183A) {
2561                 if (next == DWC3_LINK_STATE_U0) {
2562                         u32     u1u2;
2563                         u32     reg;
2564
2565                         switch (dwc->link_state) {
2566                         case DWC3_LINK_STATE_U1:
2567                         case DWC3_LINK_STATE_U2:
2568                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2569                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2570                                                 | DWC3_DCTL_ACCEPTU2ENA
2571                                                 | DWC3_DCTL_INITU1ENA
2572                                                 | DWC3_DCTL_ACCEPTU1ENA);
2573
2574                                 if (!dwc->u1u2)
2575                                         dwc->u1u2 = reg & u1u2;
2576
2577                                 reg &= ~u1u2;
2578
2579                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2580                                 break;
2581                         default:
2582                                 /* do nothing */
2583                                 break;
2584                         }
2585                 }
2586         }
2587
2588         switch (next) {
2589         case DWC3_LINK_STATE_U1:
2590                 if (dwc->speed == USB_SPEED_SUPER)
2591                         dwc3_suspend_gadget(dwc);
2592                 break;
2593         case DWC3_LINK_STATE_U2:
2594         case DWC3_LINK_STATE_U3:
2595                 dwc3_suspend_gadget(dwc);
2596                 break;
2597         case DWC3_LINK_STATE_RESUME:
2598                 dwc3_resume_gadget(dwc);
2599                 break;
2600         default:
2601                 /* do nothing */
2602                 break;
2603         }
2604
2605         dwc->link_state = next;
2606 }
2607
2608 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2609                 unsigned int evtinfo)
2610 {
2611         unsigned int is_ss = evtinfo & BIT(4);
2612
2613         /**
2614          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2615          * have a known issue which can cause USB CV TD.9.23 to fail
2616          * randomly.
2617          *
2618          * Because of this issue, core could generate bogus hibernation
2619          * events which SW needs to ignore.
2620          *
2621          * Refers to:
2622          *
2623          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2624          * Device Fallback from SuperSpeed
2625          */
2626         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2627                 return;
2628
2629         /* enter hibernation here */
2630 }
2631
2632 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2633                 const struct dwc3_event_devt *event)
2634 {
2635         switch (event->type) {
2636         case DWC3_DEVICE_EVENT_DISCONNECT:
2637                 dwc3_gadget_disconnect_interrupt(dwc);
2638                 break;
2639         case DWC3_DEVICE_EVENT_RESET:
2640                 dwc3_gadget_reset_interrupt(dwc);
2641                 break;
2642         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2643                 dwc3_gadget_conndone_interrupt(dwc);
2644                 break;
2645         case DWC3_DEVICE_EVENT_WAKEUP:
2646                 dwc3_gadget_wakeup_interrupt(dwc);
2647                 break;
2648         case DWC3_DEVICE_EVENT_HIBER_REQ:
2649                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2650                                         "unexpected hibernation event\n"))
2651                         break;
2652
2653                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2654                 break;
2655         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2656                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2657                 break;
2658         case DWC3_DEVICE_EVENT_EOPF:
2659                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2660                 break;
2661         case DWC3_DEVICE_EVENT_SOF:
2662                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2663                 break;
2664         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2665                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2666                 break;
2667         case DWC3_DEVICE_EVENT_CMD_CMPL:
2668                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2669                 break;
2670         case DWC3_DEVICE_EVENT_OVERFLOW:
2671                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2672                 break;
2673         default:
2674                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2675         }
2676 }
2677
2678 static void dwc3_process_event_entry(struct dwc3 *dwc,
2679                 const union dwc3_event *event)
2680 {
2681         trace_dwc3_event(event->raw);
2682
2683         /* Endpoint IRQ, handle it and return early */
2684         if (event->type.is_devspec == 0) {
2685                 /* depevt */
2686                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2687         }
2688
2689         switch (event->type.type) {
2690         case DWC3_EVENT_TYPE_DEV:
2691                 dwc3_gadget_interrupt(dwc, &event->devt);
2692                 break;
2693         /* REVISIT what to do with Carkit and I2C events ? */
2694         default:
2695                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2696         }
2697 }
2698
2699 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2700 {
2701         struct dwc3_event_buffer *evt;
2702         irqreturn_t ret = IRQ_NONE;
2703         int left;
2704         u32 reg;
2705
2706         evt = dwc->ev_buffs[buf];
2707         left = evt->count;
2708
2709         if (!(evt->flags & DWC3_EVENT_PENDING))
2710                 return IRQ_NONE;
2711
2712         while (left > 0) {
2713                 union dwc3_event event;
2714
2715                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2716
2717                 dwc3_process_event_entry(dwc, &event);
2718
2719                 /*
2720                  * FIXME we wrap around correctly to the next entry as
2721                  * almost all entries are 4 bytes in size. There is one
2722                  * entry which has 12 bytes which is a regular entry
2723                  * followed by 8 bytes data. ATM I don't know how
2724                  * things are organized if we get next to the a
2725                  * boundary so I worry about that once we try to handle
2726                  * that.
2727                  */
2728                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2729                 left -= 4;
2730
2731                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2732         }
2733
2734         evt->count = 0;
2735         evt->flags &= ~DWC3_EVENT_PENDING;
2736         ret = IRQ_HANDLED;
2737
2738         /* Unmask interrupt */
2739         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2740         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2741         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2742
2743         return ret;
2744 }
2745
2746 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2747 {
2748         struct dwc3 *dwc = _dwc;
2749         unsigned long flags;
2750         irqreturn_t ret = IRQ_NONE;
2751         int i;
2752
2753         spin_lock_irqsave(&dwc->lock, flags);
2754
2755         for (i = 0; i < dwc->num_event_buffers; i++)
2756                 ret |= dwc3_process_event_buf(dwc, i);
2757
2758         spin_unlock_irqrestore(&dwc->lock, flags);
2759
2760         return ret;
2761 }
2762
2763 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2764 {
2765         struct dwc3_event_buffer *evt;
2766         u32 count;
2767         u32 reg;
2768
2769         evt = dwc->ev_buffs[buf];
2770
2771         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2772         count &= DWC3_GEVNTCOUNT_MASK;
2773         if (!count)
2774                 return IRQ_NONE;
2775
2776         evt->count = count;
2777         evt->flags |= DWC3_EVENT_PENDING;
2778
2779         /* Mask interrupt */
2780         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2781         reg |= DWC3_GEVNTSIZ_INTMASK;
2782         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2783
2784         return IRQ_WAKE_THREAD;
2785 }
2786
2787 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2788 {
2789         struct dwc3                     *dwc = _dwc;
2790         int                             i;
2791         irqreturn_t                     ret = IRQ_NONE;
2792
2793         for (i = 0; i < dwc->num_event_buffers; i++) {
2794                 irqreturn_t status;
2795
2796                 status = dwc3_check_event_buf(dwc, i);
2797                 if (status == IRQ_WAKE_THREAD)
2798                         ret = status;
2799         }
2800
2801         return ret;
2802 }
2803
2804 /**
2805  * dwc3_gadget_init - Initializes gadget related registers
2806  * @dwc: pointer to our controller context structure
2807  *
2808  * Returns 0 on success otherwise negative errno.
2809  */
2810 int dwc3_gadget_init(struct dwc3 *dwc)
2811 {
2812         int                                     ret;
2813
2814         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2815                         &dwc->ctrl_req_addr, GFP_KERNEL);
2816         if (!dwc->ctrl_req) {
2817                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2818                 ret = -ENOMEM;
2819                 goto err0;
2820         }
2821
2822         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2823                         &dwc->ep0_trb_addr, GFP_KERNEL);
2824         if (!dwc->ep0_trb) {
2825                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2826                 ret = -ENOMEM;
2827                 goto err1;
2828         }
2829
2830         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2831         if (!dwc->setup_buf) {
2832                 ret = -ENOMEM;
2833                 goto err2;
2834         }
2835
2836         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2837                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2838                         GFP_KERNEL);
2839         if (!dwc->ep0_bounce) {
2840                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2841                 ret = -ENOMEM;
2842                 goto err3;
2843         }
2844
2845         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2846         if (!dwc->zlp_buf) {
2847                 ret = -ENOMEM;
2848                 goto err4;
2849         }
2850
2851         dwc->gadget.ops                 = &dwc3_gadget_ops;
2852         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2853         dwc->gadget.sg_supported        = true;
2854         dwc->gadget.name                = "dwc3-gadget";
2855         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2856
2857         /*
2858          * FIXME We might be setting max_speed to <SUPER, however versions
2859          * <2.20a of dwc3 have an issue with metastability (documented
2860          * elsewhere in this driver) which tells us we can't set max speed to
2861          * anything lower than SUPER.
2862          *
2863          * Because gadget.max_speed is only used by composite.c and function
2864          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2865          * to happen so we avoid sending SuperSpeed Capability descriptor
2866          * together with our BOS descriptor as that could confuse host into
2867          * thinking we can handle super speed.
2868          *
2869          * Note that, in fact, we won't even support GetBOS requests when speed
2870          * is less than super speed because we don't have means, yet, to tell
2871          * composite.c that we are USB 2.0 + LPM ECN.
2872          */
2873         if (dwc->revision < DWC3_REVISION_220A)
2874                 dwc3_trace(trace_dwc3_gadget,
2875                                 "Changing max_speed on rev %08x\n",
2876                                 dwc->revision);
2877
2878         dwc->gadget.max_speed           = dwc->maximum_speed;
2879
2880         /*
2881          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2882          * on ep out.
2883          */
2884         dwc->gadget.quirk_ep_out_aligned_size = true;
2885
2886         /*
2887          * REVISIT: Here we should clear all pending IRQs to be
2888          * sure we're starting from a well known location.
2889          */
2890
2891         ret = dwc3_gadget_init_endpoints(dwc);
2892         if (ret)
2893                 goto err5;
2894
2895         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2896         if (ret) {
2897                 dev_err(dwc->dev, "failed to register udc\n");
2898                 goto err5;
2899         }
2900
2901         return 0;
2902
2903 err5:
2904         kfree(dwc->zlp_buf);
2905
2906 err4:
2907         dwc3_gadget_free_endpoints(dwc);
2908         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2909                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2910
2911 err3:
2912         kfree(dwc->setup_buf);
2913
2914 err2:
2915         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2916                         dwc->ep0_trb, dwc->ep0_trb_addr);
2917
2918 err1:
2919         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2920                         dwc->ctrl_req, dwc->ctrl_req_addr);
2921
2922 err0:
2923         return ret;
2924 }
2925
2926 /* -------------------------------------------------------------------------- */
2927
2928 void dwc3_gadget_exit(struct dwc3 *dwc)
2929 {
2930         usb_del_gadget_udc(&dwc->gadget);
2931
2932         dwc3_gadget_free_endpoints(dwc);
2933
2934         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2935                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2936
2937         kfree(dwc->setup_buf);
2938         kfree(dwc->zlp_buf);
2939
2940         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2941                         dwc->ep0_trb, dwc->ep0_trb_addr);
2942
2943         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2944                         dwc->ctrl_req, dwc->ctrl_req_addr);
2945 }
2946
2947 int dwc3_gadget_suspend(struct dwc3 *dwc)
2948 {
2949         if (dwc->pullups_connected) {
2950                 dwc3_gadget_disable_irq(dwc);
2951                 dwc3_gadget_run_stop(dwc, true, true);
2952         }
2953
2954         __dwc3_gadget_ep_disable(dwc->eps[0]);
2955         __dwc3_gadget_ep_disable(dwc->eps[1]);
2956
2957         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2958
2959         return 0;
2960 }
2961
2962 int dwc3_gadget_resume(struct dwc3 *dwc)
2963 {
2964         struct dwc3_ep          *dep;
2965         int                     ret;
2966
2967         /* Start with SuperSpeed Default */
2968         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2969
2970         dep = dwc->eps[0];
2971         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2972                         false);
2973         if (ret)
2974                 goto err0;
2975
2976         dep = dwc->eps[1];
2977         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2978                         false);
2979         if (ret)
2980                 goto err1;
2981
2982         /* begin to receive SETUP packets */
2983         dwc->ep0state = EP0_SETUP_PHASE;
2984         dwc3_ep0_out_start(dwc);
2985
2986         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2987
2988         if (dwc->pullups_connected) {
2989                 dwc3_gadget_enable_irq(dwc);
2990                 dwc3_gadget_run_stop(dwc, true, false);
2991         }
2992
2993         return 0;
2994
2995 err1:
2996         __dwc3_gadget_ep_disable(dwc->eps[0]);
2997
2998 err0:
2999         return ret;
3000 }
3001
3002 static int dwc3_gadget_reinit(struct dwc3 *dwc)
3003 {
3004         u32                     hwparams4 = dwc->hwparams.hwparams4;
3005         u32                     reg;
3006         int                     ret;
3007         struct dwc3_ep          *dep = NULL;
3008
3009         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
3010         /* This should read as U3 followed by revision number */
3011         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
3012                 /* Detected DWC_usb3 IP */
3013                 dwc->revision = reg;
3014         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
3015                 /* Detected DWC_usb31 IP */
3016                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
3017                 dwc->revision |= DWC3_REVISION_IS_DWC31;
3018         } else {
3019                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
3020                 ret = -ENODEV;
3021                 goto err0;
3022         }
3023
3024         /*
3025          * Write Linux Version Code to our GUID register so it's easy to figure
3026          * out which kernel version a bug was found.
3027          */
3028         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
3029
3030         /* Handle USB2.0-only core configuration */
3031         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
3032                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
3033                 if (dwc->maximum_speed == USB_SPEED_SUPER)
3034                         dwc->maximum_speed = USB_SPEED_HIGH;
3035         }
3036
3037         /* issue device SoftReset too */
3038         ret = dwc3_soft_reset(dwc);
3039         if (ret)
3040                 goto err0;
3041
3042         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3043         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
3044
3045         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
3046         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
3047                 /**
3048                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
3049                  * issue which would cause xHCI compliance tests to fail.
3050                  *
3051                  * Because of that we cannot enable clock gating on such
3052                  * configurations.
3053                  *
3054                  * Refers to:
3055                  *
3056                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
3057                  * SOF/ITP Mode Used
3058                  */
3059                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
3060                      dwc->dr_mode == USB_DR_MODE_OTG) &&
3061                      (dwc->revision >= DWC3_REVISION_210A &&
3062                      dwc->revision <= DWC3_REVISION_250A))
3063                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
3064                 else
3065                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
3066                 break;
3067         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
3068                 /* enable hibernation here */
3069                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
3070
3071                 /*
3072                  * REVISIT Enabling this bit so that host-mode hibernation
3073                  * will work. Device-mode hibernation is not yet implemented.
3074                  */
3075                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
3076                 break;
3077         default:
3078                 dwc3_trace(trace_dwc3_core,
3079                            "No power optimization available\n");
3080         }
3081
3082         /* check if current dwc3 is on simulation board */
3083         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
3084                 dwc3_trace(trace_dwc3_core,
3085                            "running on FPGA platform\n");
3086                 dwc->is_fpga = true;
3087         }
3088
3089         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
3090                   "disable_scramble cannot be used on non-FPGA builds\n");
3091
3092         if (dwc->disable_scramble_quirk && dwc->is_fpga)
3093                 reg |= DWC3_GCTL_DISSCRAMBLE;
3094         else
3095                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
3096
3097         if (dwc->u2exit_lfps_quirk)
3098                 reg |= DWC3_GCTL_U2EXIT_LFPS;
3099
3100         /*
3101          * WORKAROUND: DWC3 revisions <1.90a have a bug
3102          * where the device can fail to connect at SuperSpeed
3103          * and falls back to high-speed mode which causes
3104          * the device to enter a Connect/Disconnect loop
3105          */
3106         if (dwc->revision < DWC3_REVISION_190A)
3107                 reg |= DWC3_GCTL_U2RSTECN;
3108         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
3109
3110         ret = dwc3_event_buffers_setup(dwc);
3111
3112         if (ret) {
3113                 dev_err(dwc->dev, "failed to setup event buffers\n");
3114                 goto err1;
3115         }
3116
3117         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3118         reg |= DWC3_DCFG_LPM_CAP;
3119         reg &= ~(DWC3_DCFG_SPEED_MASK);
3120
3121         /**
3122          * WORKAROUND: DWC3 revision < 2.20a have an issue
3123          * which would cause metastability state on Run/Stop
3124          * bit if we try to force the IP to USB2-only mode.
3125          *
3126          * Because of that, we cannot configure the IP to any
3127          * speed other than the SuperSpeed
3128          *
3129          * Refers to:
3130          *
3131          * STAR#9000525659: Clock Domain Crossing on DCTL in
3132          * USB 2.0 Mode
3133          */
3134         if (dwc->revision < DWC3_REVISION_220A) {
3135                 reg |= DWC3_DCFG_SUPERSPEED;
3136         } else {
3137                 switch (dwc->maximum_speed) {
3138                 case USB_SPEED_LOW:
3139                         reg |= DWC3_DSTS_LOWSPEED;
3140                         break;
3141                 case USB_SPEED_FULL:
3142                         reg |= DWC3_DSTS_FULLSPEED1;
3143                         break;
3144                 case USB_SPEED_HIGH:
3145                         reg |= DWC3_DSTS_HIGHSPEED;
3146                         break;
3147                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
3148                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
3149                 default:
3150                         reg |= DWC3_DSTS_SUPERSPEED;
3151                 }
3152         }
3153         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3154
3155         /* Start with SuperSpeed Default */
3156         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3157
3158         dep = dwc->eps[0];
3159         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
3160                                       false);
3161         if (ret) {
3162                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3163                 goto err1;
3164         }
3165
3166         dep = dwc->eps[1];
3167         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
3168                                       false);
3169         if (ret) {
3170                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3171                 goto err2;
3172         }
3173
3174         /* begin to receive SETUP packets */
3175         dwc->ep0state = EP0_SETUP_PHASE;
3176         dwc3_ep0_out_start(dwc);
3177
3178         return 0;
3179 err2:
3180         __dwc3_gadget_ep_disable(dwc->eps[0]);
3181 err1:
3182         dwc3_event_buffers_cleanup(dwc);
3183 err0:
3184         return ret;
3185 }
3186
3187 int dwc3_gadget_restart(struct dwc3 *dwc, bool start)
3188 {
3189         struct dwc3_event_buffer        *evt;
3190         int                             ret = 0;
3191         int                             i;
3192         u32                             reg;
3193
3194         if (start) {
3195                 ret = dwc3_gadget_reinit(dwc);
3196                 if (ret < 0) {
3197                         dev_err(dwc->dev,
3198                                 "dwc3 gadget reinit error = %d\n", ret);
3199                         goto err;
3200                 }
3201
3202                 if (dwc->enabled) {
3203                         ret = dwc3_gadget_run_stop(dwc, start, false);
3204                         if (ret < 0) {
3205                                 dev_err(dwc->dev,
3206                                         "dwc3 gadget run stop err = %d\n", ret);
3207                                 goto err;
3208                         }
3209                 }
3210                 dwc3_gadget_enable_irq(dwc);
3211         } else {
3212                 /*
3213                  * Per databook, DEVCTRLHLT bit setting requires
3214                  * interrupts to be acknowledged. so acknowledge
3215                  * the events that are generated (by writing to
3216                  * GEVNTCOUNTn) first. And we also mask interrupts
3217                  * and clear SW states to avoid generating other
3218                  * interrupts after do gadget disconnnect operation.
3219                  */
3220                 dwc3_gadget_disable_irq(dwc);
3221
3222                 for (i = 0; i < dwc->num_event_buffers; i++) {
3223                         evt = dwc->ev_buffs[i];
3224                         evt->count = 0;
3225                         evt->flags &= ~DWC3_EVENT_PENDING;
3226                         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(i));
3227                         reg |= DWC3_GEVNTSIZ_INTMASK;
3228                         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(i), reg);
3229                         reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(i));
3230                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), reg);
3231                 }
3232
3233                 /*
3234                  * DEVCTRLHLT bit sometimes does not get set
3235                  * even when GEVNTCOUNT is acked so do not
3236                  * care run stop function return value.
3237                  */
3238                 dwc3_gadget_run_stop(dwc, start, false);
3239
3240                 if (dwc->gadget.state != USB_STATE_NOTATTACHED)
3241                         dwc3_gadget_disconnect_interrupt(dwc);
3242
3243                 __dwc3_gadget_ep_disable(dwc->eps[0]);
3244                 __dwc3_gadget_ep_disable(dwc->eps[1]);
3245         }
3246
3247 err:
3248         return ret;
3249 }