drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions, and the following disclaimer,
  14  *    without modification.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. The names of the above-listed copyright holders may not be used
  19  *    to endorse or promote products derived from this software without
  20  *    specific prior written permission.
  21  *
  22  * ALTERNATIVELY, this software may be distributed under the terms of the
  23  * GNU General Public License ("GPL") version 2, as published by the Free
  24  * Software Foundation.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  27  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  28  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  29  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  30  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  31  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  32  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  34  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  35  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  36  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  37  */
  38
  39 #include <linux/kernel.h>
  40 #include <linux/delay.h>
  41 #include <linux/slab.h>
  42 #include <linux/spinlock.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/io.h>
  47 #include <linux/list.h>
  48 #include <linux/dma-mapping.h>
  49
  50 #include <linux/usb/ch9.h>
  51 #include <linux/usb/gadget.h>
  52
  53 #include "core.h"
  54 #include "gadget.h"
  55 #include "io.h"
  56
  57 /**
  58  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  59  * @dwc: pointer to our context structure
  60  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  61  *
  62  * Caller should take care of locking. This function will
  63  * return 0 on success or -EINVAL if wrong Test Selector
  64  * is passed
  65  */
  66 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  67 {
  68         u32             reg;
  69
  70         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  71         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  72
  73         switch (mode) {
  74         case TEST_J:
  75         case TEST_K:
  76         case TEST_SE0_NAK:
  77         case TEST_PACKET:
  78         case TEST_FORCE_EN:
  79                 reg |= mode << 1;
  80                 break;
  81         default:
  82                 return -EINVAL;
  83         }
  84
  85         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  86
  87         return 0;
  88 }
  89
  90 /**
  91  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  92  * @dwc: pointer to our context structure
  93  * @state: the state to put link into
  94  *
  95  * Caller should take care of locking. This function will
  96  * return 0 on success or -ETIMEDOUT.
  97  */
  98 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  99 {
 100         int             retries = 10000;
 101         u32             reg;
 102
 103         /*
 104          * Wait until device controller is ready. Only applies to 1.94a and
 105          * later RTL.
 106          */
 107         if (dwc->revision >= DWC3_REVISION_194A) {
 108                 while (--retries) {
 109                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 110                         if (reg & DWC3_DSTS_DCNRD)
 111                                 udelay(5);
 112                         else
 113                                 break;
 114                 }
 115
 116                 if (retries <= 0)
 117                         return -ETIMEDOUT;
 118         }
 119
 120         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 122
 123         /* set requested state */
 124         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 125         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 126
 127         /*
 128          * The following code is racy when called from dwc3_gadget_wakeup,
 129          * and is not needed, at least on newer versions
 130          */
 131         if (dwc->revision >= DWC3_REVISION_194A)
 132                 return 0;
 133
 134         /* wait for a change in DSTS */
 135         retries = 10000;
 136         while (--retries) {
 137                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 138
 139                 if (DWC3_DSTS_USBLNKST(reg) == state)
 140                         return 0;
 141
 142                 udelay(5);
 143         }
 144
 145         dev_vdbg(dwc->dev, "link state change request timed out\n");
 146
 147         return -ETIMEDOUT;
 148 }
 149
 150 /**
 151  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 152  * @dwc: pointer to our context structure
 153  *
 154  * This function will a best effort FIFO allocation in order
 155  * to improve FIFO usage and throughput, while still allowing
 156  * us to enable as many endpoints as possible.
 157  *
 158  * Keep in mind that this operation will be highly dependent
 159  * on the configured size for RAM1 - which contains TxFifo -,
 160  * the amount of endpoints enabled on coreConsultant tool, and
 161  * the width of the Master Bus.
 162  *
 163  * In the ideal world, we would always be able to satisfy the
 164  * following equation:
 165  *
 166  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 167  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 168  *
 169  * Unfortunately, due to many variables that's not always the case.
 170  */
 171 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 172 {
 173         int             last_fifo_depth = 0;
 174         int             ram1_depth;
 175         int             fifo_size;
 176         int             mdwidth;
 177         int             num;
 178
 179         if (!dwc->needs_fifo_resize)
 180                 return 0;
 181
 182         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 183         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 184
 185         /* MDWIDTH is represented in bits, we need it in bytes */
 186         mdwidth >>= 3;
 187
 188         /*
 189          * FIXME For now we will only allocate 1 wMaxPacketSize space
 190          * for each enabled endpoint, later patches will come to
 191          * improve this algorithm so that we better use the internal
 192          * FIFO space
 193          */
 194         for (num = 0; num < DWC3_ENDPOINTS_NUM; num++) {
 195                 struct dwc3_ep  *dep = dwc->eps[num];
 196                 int             fifo_number = dep->number >> 1;
 197                 int             mult = 1;
 198                 int             tmp;
 199
 200                 if (!(dep->number & 1))
 201                         continue;
 202
 203                 if (!(dep->flags & DWC3_EP_ENABLED))
 204                         continue;
 205
 206                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 207                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 208                         mult = 3;
 209
 210                 /*
 211                  * REVISIT: the following assumes we will always have enough
 212                  * space available on the FIFO RAM for all possible use cases.
 213                  * Make sure that's true somehow and change FIFO allocation
 214                  * accordingly.
 215                  *
 216                  * If we have Bulk or Isochronous endpoints, we want
 217                  * them to be able to be very, very fast. So we're giving
 218                  * those endpoints a fifo_size which is enough for 3 full
 219                  * packets
 220                  */
 221                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 222                 tmp += mdwidth;
 223
 224                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 225
 226                 fifo_size |= (last_fifo_depth << 16);
 227
 228                 dev_vdbg(dwc->dev, "%s: Fifo Addr %04x Size %d\n",
 229                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 230
 231                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(fifo_number),
 232                                 fifo_size);
 233
 234                 last_fifo_depth += (fifo_size & 0xffff);
 235         }
 236
 237         return 0;
 238 }
 239
 240 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 241                 int status)
 242 {
 243         struct dwc3                     *dwc = dep->dwc;
 244         int                             i;
 245
 246         if (req->queued) {
 247                 i = 0;
 248                 do {
 249                         dep->busy_slot++;
 250                         /*
 251                          * Skip LINK TRB. We can't use req->trb and check for
 252                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 253                          * just completed (not the LINK TRB).
 254                          */
 255                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 256                                 DWC3_TRB_NUM- 1) &&
 257                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 258                                 dep->busy_slot++;
 259                 } while(++i < req->request.num_mapped_sgs);
 260                 req->queued = false;
 261         }
 262         list_del(&req->list);
 263         req->trb = NULL;
 264
 265         if (req->request.status == -EINPROGRESS)
 266                 req->request.status = status;
 267
 268         if (dwc->ep0_bounced && dep->number == 0)
 269                 dwc->ep0_bounced = false;
 270         else
 271                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 272                                 req->direction);
 273
 274         dev_dbg(dwc->dev, "request %p from %s completed %d/%d ===> %d\n",
 275                         req, dep->name, req->request.actual,
 276                         req->request.length, status);
 277
 278         spin_unlock(&dwc->lock);
 279         req->request.complete(&dep->endpoint, &req->request);
 280         spin_lock(&dwc->lock);
 281 }
 282
 283 static const char *dwc3_gadget_ep_cmd_string(u8 cmd)
 284 {
 285         switch (cmd) {
 286         case DWC3_DEPCMD_DEPSTARTCFG:
 287                 return "Start New Configuration";
 288         case DWC3_DEPCMD_ENDTRANSFER:
 289                 return "End Transfer";
 290         case DWC3_DEPCMD_UPDATETRANSFER:
 291                 return "Update Transfer";
 292         case DWC3_DEPCMD_STARTTRANSFER:
 293                 return "Start Transfer";
 294         case DWC3_DEPCMD_CLEARSTALL:
 295                 return "Clear Stall";
 296         case DWC3_DEPCMD_SETSTALL:
 297                 return "Set Stall";
 298         case DWC3_DEPCMD_GETEPSTATE:
 299                 return "Get Endpoint State";
 300         case DWC3_DEPCMD_SETTRANSFRESOURCE:
 301                 return "Set Endpoint Transfer Resource";
 302         case DWC3_DEPCMD_SETEPCONFIG:
 303                 return "Set Endpoint Configuration";
 304         default:
 305                 return "UNKNOWN command";
 306         }
 307 }
 308
 309 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param)
 310 {
 311         u32             timeout = 500;
 312         u32             reg;
 313
 314         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 315         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 316
 317         do {
 318                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 319                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 320                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 321                                         DWC3_DGCMD_STATUS(reg));
 322                         return 0;
 323                 }
 324
 325                 /*
 326                  * We can't sleep here, because it's also called from
 327                  * interrupt context.
 328                  */
 329                 timeout--;
 330                 if (!timeout)
 331                         return -ETIMEDOUT;
 332                 udelay(1);
 333         } while (1);
 334 }
 335
 336 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 337                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 338 {
 339         struct dwc3_ep          *dep = dwc->eps[ep];
 340         u32                     timeout = 500;
 341         u32                     reg;
 342
 343         dev_vdbg(dwc->dev, "%s: cmd '%s' params %08x %08x %08x\n",
 344                         dep->name,
 345                         dwc3_gadget_ep_cmd_string(cmd), params->param0,
 346                         params->param1, params->param2);
 347
 348         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 349         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 350         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 351
 352         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 353         do {
 354                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 355                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 356                         dev_vdbg(dwc->dev, "Command Complete --> %d\n",
 357                                         DWC3_DEPCMD_STATUS(reg));
 358                         return 0;
 359                 }
 360
 361                 /*
 362                  * We can't sleep here, because it is also called from
 363                  * interrupt context.
 364                  */
 365                 timeout--;
 366                 if (!timeout)
 367                         return -ETIMEDOUT;
 368
 369                 udelay(1);
 370         } while (1);
 371 }
 372
 373 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 374                 struct dwc3_trb *trb)
 375 {
 376         u32             offset = (char *) trb - (char *) dep->trb_pool;
 377
 378         return dep->trb_pool_dma + offset;
 379 }
 380
 381 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 382 {
 383         struct dwc3             *dwc = dep->dwc;
 384
 385         if (dep->trb_pool)
 386                 return 0;
 387
 388         if (dep->number == 0 || dep->number == 1)
 389                 return 0;
 390
 391         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 392                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 393                         &dep->trb_pool_dma, GFP_KERNEL);
 394         if (!dep->trb_pool) {
 395                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 396                                 dep->name);
 397                 return -ENOMEM;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 404 {
 405         struct dwc3             *dwc = dep->dwc;
 406
 407         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 408                         dep->trb_pool, dep->trb_pool_dma);
 409
 410         dep->trb_pool = NULL;
 411         dep->trb_pool_dma = 0;
 412 }
 413
 414 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 415 {
 416         struct dwc3_gadget_ep_cmd_params params;
 417         u32                     cmd;
 418
 419         memset(&params, 0x00, sizeof(params));
 420
 421         if (dep->number != 1) {
 422                 cmd = DWC3_DEPCMD_DEPSTARTCFG;
 423                 /* XferRscIdx == 0 for ep0 and 2 for the remaining */
 424                 if (dep->number > 1) {
 425                         if (dwc->start_config_issued)
 426                                 return 0;
 427                         dwc->start_config_issued = true;
 428                         cmd |= DWC3_DEPCMD_PARAM(2);
 429                 }
 430
 431                 return dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 438                 const struct usb_endpoint_descriptor *desc,
 439                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 440                 bool ignore)
 441 {
 442         struct dwc3_gadget_ep_cmd_params params;
 443
 444         memset(&params, 0x00, sizeof(params));
 445
 446         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 447                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 448
 449         /* Burst size is only needed in SuperSpeed mode */
 450         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 451                 u32 burst = dep->endpoint.maxburst - 1;
 452
 453                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 454         }
 455
 456         if (ignore)
 457                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 458
 459         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 460                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 461
 462         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 463                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 464                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 465                 dep->stream_capable = true;
 466         }
 467
 468         if (usb_endpoint_xfer_isoc(desc))
 469                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 470
 471         /*
 472          * We are doing 1:1 mapping for endpoints, meaning
 473          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 474          * so on. We consider the direction bit as part of the physical
 475          * endpoint number. So USB endpoint 0x81 is 0x03.
 476          */
 477         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 478
 479         /*
 480          * We must use the lower 16 TX FIFOs even though
 481          * HW might have more
 482          */
 483         if (dep->direction)
 484                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 485
 486         if (desc->bInterval) {
 487                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 488                 dep->interval = 1 << (desc->bInterval - 1);
 489         }
 490
 491         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 492                         DWC3_DEPCMD_SETEPCONFIG, &params);
 493 }
 494
 495 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 496 {
 497         struct dwc3_gadget_ep_cmd_params params;
 498
 499         memset(&params, 0x00, sizeof(params));
 500
 501         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 502
 503         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 504                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 505 }
 506
 507 /**
 508  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 509  * @dep: endpoint to be initialized
 510  * @desc: USB Endpoint Descriptor
 511  *
 512  * Caller should take care of locking
 513  */
 514 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 515                 const struct usb_endpoint_descriptor *desc,
 516                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 517                 bool ignore)
 518 {
 519         struct dwc3             *dwc = dep->dwc;
 520         u32                     reg;
 521         int                     ret = -ENOMEM;
 522
 523         if (!(dep->flags & DWC3_EP_ENABLED)) {
 524                 ret = dwc3_gadget_start_config(dwc, dep);
 525                 if (ret)
 526                         return ret;
 527         }
 528
 529         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore);
 530         if (ret)
 531                 return ret;
 532
 533         if (!(dep->flags & DWC3_EP_ENABLED)) {
 534                 struct dwc3_trb *trb_st_hw;
 535                 struct dwc3_trb *trb_link;
 536
 537                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 538                 if (ret)
 539                         return ret;
 540
 541                 dep->endpoint.desc = desc;
 542                 dep->comp_desc = comp_desc;
 543                 dep->type = usb_endpoint_type(desc);
 544                 dep->flags |= DWC3_EP_ENABLED;
 545
 546                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 547                 reg |= DWC3_DALEPENA_EP(dep->number);
 548                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 549
 550                 if (!usb_endpoint_xfer_isoc(desc))
 551                         return 0;
 552
 553                 /* Link TRB for ISOC. The HWO bit is never reset */
 554                 trb_st_hw = &dep->trb_pool[0];
 555
 556                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 557                 memset(trb_link, 0, sizeof(*trb_link));
 558
 559                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 560                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 561                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 562                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 563         }
 564
 565         return 0;
 566 }
 567
 568 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum);
 569 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 570 {
 571         struct dwc3_request             *req;
 572
 573         if (!list_empty(&dep->req_queued)) {
 574                 dwc3_stop_active_transfer(dwc, dep->number);
 575
 576                 /* - giveback all requests to gadget driver */
 577                 while (!list_empty(&dep->req_queued)) {
 578                         req = next_request(&dep->req_queued);
 579
 580                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 581                 }
 582         }
 583
 584         while (!list_empty(&dep->request_list)) {
 585                 req = next_request(&dep->request_list);
 586
 587                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 588         }
 589 }
 590
 591 /**
 592  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 593  * @dep: the endpoint to disable
 594  *
 595  * This function also removes requests which are currently processed ny the
 596  * hardware and those which are not yet scheduled.
 597  * Caller should take care of locking.
 598  */
 599 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 600 {
 601         struct dwc3             *dwc = dep->dwc;
 602         u32                     reg;
 603
 604         dwc3_remove_requests(dwc, dep);
 605
 606         /* make sure HW endpoint isn't stalled */
 607         if (dep->flags & DWC3_EP_STALL)
 608                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 609
 610         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 611         reg &= ~DWC3_DALEPENA_EP(dep->number);
 612         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 613
 614         dep->stream_capable = false;
 615         dep->endpoint.desc = NULL;
 616         dep->comp_desc = NULL;
 617         dep->type = 0;
 618         dep->flags = 0;
 619
 620         return 0;
 621 }
 622
 623 /* -------------------------------------------------------------------------- */
 624
 625 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 626                 const struct usb_endpoint_descriptor *desc)
 627 {
 628         return -EINVAL;
 629 }
 630
 631 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 632 {
 633         return -EINVAL;
 634 }
 635
 636 /* -------------------------------------------------------------------------- */
 637
 638 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 639                 const struct usb_endpoint_descriptor *desc)
 640 {
 641         struct dwc3_ep                  *dep;
 642         struct dwc3                     *dwc;
 643         unsigned long                   flags;
 644         int                             ret;
 645
 646         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 647                 pr_debug("dwc3: invalid parameters\n");
 648                 return -EINVAL;
 649         }
 650
 651         if (!desc->wMaxPacketSize) {
 652                 pr_debug("dwc3: missing wMaxPacketSize\n");
 653                 return -EINVAL;
 654         }
 655
 656         dep = to_dwc3_ep(ep);
 657         dwc = dep->dwc;
 658
 659         if (dep->flags & DWC3_EP_ENABLED) {
 660                 dev_WARN_ONCE(dwc->dev, true, "%s is already enabled\n",
 661                                 dep->name);
 662                 return 0;
 663         }
 664
 665         switch (usb_endpoint_type(desc)) {
 666         case USB_ENDPOINT_XFER_CONTROL:
 667                 strlcat(dep->name, "-control", sizeof(dep->name));
 668                 break;
 669         case USB_ENDPOINT_XFER_ISOC:
 670                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 671                 break;
 672         case USB_ENDPOINT_XFER_BULK:
 673                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 674                 break;
 675         case USB_ENDPOINT_XFER_INT:
 676                 strlcat(dep->name, "-int", sizeof(dep->name));
 677                 break;
 678         default:
 679                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 680         }
 681
 682         dev_vdbg(dwc->dev, "Enabling %s\n", dep->name);
 683
 684         spin_lock_irqsave(&dwc->lock, flags);
 685         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false);
 686         spin_unlock_irqrestore(&dwc->lock, flags);
 687
 688         return ret;
 689 }
 690
 691 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 692 {
 693         struct dwc3_ep                  *dep;
 694         struct dwc3                     *dwc;
 695         unsigned long                   flags;
 696         int                             ret;
 697
 698         if (!ep) {
 699                 pr_debug("dwc3: invalid parameters\n");
 700                 return -EINVAL;
 701         }
 702
 703         dep = to_dwc3_ep(ep);
 704         dwc = dep->dwc;
 705
 706         if (!(dep->flags & DWC3_EP_ENABLED)) {
 707                 dev_WARN_ONCE(dwc->dev, true, "%s is already disabled\n",
 708                                 dep->name);
 709                 return 0;
 710         }
 711
 712         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 713                         dep->number >> 1,
 714                         (dep->number & 1) ? "in" : "out");
 715
 716         spin_lock_irqsave(&dwc->lock, flags);
 717         ret = __dwc3_gadget_ep_disable(dep);
 718         spin_unlock_irqrestore(&dwc->lock, flags);
 719
 720         return ret;
 721 }
 722
 723 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 724         gfp_t gfp_flags)
 725 {
 726         struct dwc3_request             *req;
 727         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 728         struct dwc3                     *dwc = dep->dwc;
 729
 730         req = kzalloc(sizeof(*req), gfp_flags);
 731         if (!req) {
 732                 dev_err(dwc->dev, "not enough memory\n");
 733                 return NULL;
 734         }
 735
 736         req->epnum      = dep->number;
 737         req->dep        = dep;
 738
 739         return &req->request;
 740 }
 741
 742 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 743                 struct usb_request *request)
 744 {
 745         struct dwc3_request             *req = to_dwc3_request(request);
 746
 747         kfree(req);
 748 }
 749
 750 /**
 751  * dwc3_prepare_one_trb - setup one TRB from one request
 752  * @dep: endpoint for which this request is prepared
 753  * @req: dwc3_request pointer
 754  */
 755 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 756                 struct dwc3_request *req, dma_addr_t dma,
 757                 unsigned length, unsigned last, unsigned chain, unsigned node)
 758 {
 759         struct dwc3             *dwc = dep->dwc;
 760         struct dwc3_trb         *trb;
 761
 762         dev_vdbg(dwc->dev, "%s: req %p dma %08llx length %d%s%s\n",
 763                         dep->name, req, (unsigned long long) dma,
 764                         length, last ? " last" : "",
 765                         chain ? " chain" : "");
 766
 767         /* Skip the LINK-TRB on ISOC */
 768         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 769                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 770                 dep->free_slot++;
 771
 772         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 773
 774         if (!req->trb) {
 775                 dwc3_gadget_move_request_queued(req);
 776                 req->trb = trb;
 777                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 778                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 779         }
 780
 781         dep->free_slot++;
 782
 783         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 784         trb->bpl = lower_32_bits(dma);
 785         trb->bph = upper_32_bits(dma);
 786
 787         switch (usb_endpoint_type(dep->endpoint.desc)) {
 788         case USB_ENDPOINT_XFER_CONTROL:
 789                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 790                 break;
 791
 792         case USB_ENDPOINT_XFER_ISOC:
 793                 if (!node)
 794                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 795                 else
 796                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 797
 798                 if (!req->request.no_interrupt && !chain)
 799                         trb->ctrl |= DWC3_TRB_CTRL_IOC;
 800                 break;
 801
 802         case USB_ENDPOINT_XFER_BULK:
 803         case USB_ENDPOINT_XFER_INT:
 804                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 805                 break;
 806         default:
 807                 /*
 808                  * This is only possible with faulty memory because we
 809                  * checked it already :)
 810                  */
 811                 BUG();
 812         }
 813
 814         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 815                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 816                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 817         } else if (last) {
 818                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 819         }
 820
 821         if (chain)
 822                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 823
 824         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 825                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 826
 827         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 828 }
 829
 830 /*
 831  * dwc3_prepare_trbs - setup TRBs from requests
 832  * @dep: endpoint for which requests are being prepared
 833  * @starting: true if the endpoint is idle and no requests are queued.
 834  *
 835  * The function goes through the requests list and sets up TRBs for the
 836  * transfers. The function returns once there are no more TRBs available or
 837  * it runs out of requests.
 838  */
 839 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 840 {
 841         struct dwc3_request     *req, *n;
 842         u32                     trbs_left;
 843         u32                     max;
 844         unsigned int            last_one = 0;
 845
 846         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 847
 848         /* the first request must not be queued */
 849         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 850
 851         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 852         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 853                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 854                 if (trbs_left > max)
 855                         trbs_left = max;
 856         }
 857
 858         /*
 859          * If busy & slot are equal than it is either full or empty. If we are
 860          * starting to process requests then we are empty. Otherwise we are
 861          * full and don't do anything
 862          */
 863         if (!trbs_left) {
 864                 if (!starting)
 865                         return;
 866                 trbs_left = DWC3_TRB_NUM;
 867                 /*
 868                  * In case we start from scratch, we queue the ISOC requests
 869                  * starting from slot 1. This is done because we use ring
 870                  * buffer and have no LST bit to stop us. Instead, we place
 871                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 872                  * after the first request so we start at slot 1 and have
 873                  * 7 requests proceed before we hit the first IOC.
 874                  * Other transfer types don't use the ring buffer and are
 875                  * processed from the first TRB until the last one. Since we
 876                  * don't wrap around we have to start at the beginning.
 877                  */
 878                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 879                         dep->busy_slot = 1;
 880                         dep->free_slot = 1;
 881                 } else {
 882                         dep->busy_slot = 0;
 883                         dep->free_slot = 0;
 884                 }
 885         }
 886
 887         /* The last TRB is a link TRB, not used for xfer */
 888         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 889                 return;
 890
 891         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 892                 unsigned        length;
 893                 dma_addr_t      dma;
 894                 last_one = false;
 895
 896                 if (req->request.num_mapped_sgs > 0) {
 897                         struct usb_request *request = &req->request;
 898                         struct scatterlist *sg = request->sg;
 899                         struct scatterlist *s;
 900                         int             i;
 901
 902                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 903                                 unsigned chain = true;
 904
 905                                 length = sg_dma_len(s);
 906                                 dma = sg_dma_address(s);
 907
 908                                 if (i == (request->num_mapped_sgs - 1) ||
 909                                                 sg_is_last(s)) {
 910                                         if (list_empty(&dep->request_list))
 911                                                 last_one = true;
 912                                         chain = false;
 913                                 }
 914
 915                                 trbs_left--;
 916                                 if (!trbs_left)
 917                                         last_one = true;
 918
 919                                 if (last_one)
 920                                         chain = false;
 921
 922                                 dwc3_prepare_one_trb(dep, req, dma, length,
 923                                                 last_one, chain, i);
 924
 925                                 if (last_one)
 926                                         break;
 927                         }
 928
 929                         if (last_one)
 930                                 break;
 931                 } else {
 932                         dma = req->request.dma;
 933                         length = req->request.length;
 934                         trbs_left--;
 935
 936                         if (!trbs_left)
 937                                 last_one = 1;
 938
 939                         /* Is this the last request? */
 940                         if (list_is_last(&req->list, &dep->request_list))
 941                                 last_one = 1;
 942
 943                         dwc3_prepare_one_trb(dep, req, dma, length,
 944                                         last_one, false, 0);
 945
 946                         if (last_one)
 947                                 break;
 948                 }
 949         }
 950 }
 951
 952 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 953                 int start_new)
 954 {
 955         struct dwc3_gadget_ep_cmd_params params;
 956         struct dwc3_request             *req;
 957         struct dwc3                     *dwc = dep->dwc;
 958         int                             ret;
 959         u32                             cmd;
 960
 961         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 962                 dev_vdbg(dwc->dev, "%s: endpoint busy\n", dep->name);
 963                 return -EBUSY;
 964         }
 965         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
 966
 967         /*
 968          * If we are getting here after a short-out-packet we don't enqueue any
 969          * new requests as we try to set the IOC bit only on the last request.
 970          */
 971         if (start_new) {
 972                 if (list_empty(&dep->req_queued))
 973                         dwc3_prepare_trbs(dep, start_new);
 974
 975                 /* req points to the first request which will be sent */
 976                 req = next_request(&dep->req_queued);
 977         } else {
 978                 dwc3_prepare_trbs(dep, start_new);
 979
 980                 /*
 981                  * req points to the first request where HWO changed from 0 to 1
 982                  */
 983                 req = next_request(&dep->req_queued);
 984         }
 985         if (!req) {
 986                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 987                 return 0;
 988         }
 989
 990         memset(&params, 0, sizeof(params));
 991
 992         if (start_new) {
 993                 params.param0 = upper_32_bits(req->trb_dma);
 994                 params.param1 = lower_32_bits(req->trb_dma);
 995                 cmd = DWC3_DEPCMD_STARTTRANSFER;
 996         } else {
 997                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
 998         }
 999
1000         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1001         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1002         if (ret < 0) {
1003                 dev_dbg(dwc->dev, "failed to send STARTTRANSFER command\n");
1004
1005                 /*
1006                  * FIXME we need to iterate over the list of requests
1007                  * here and stop, unmap, free and del each of the linked
1008                  * requests instead of what we do now.
1009                  */
1010                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1011                                 req->direction);
1012                 list_del(&req->list);
1013                 return ret;
1014         }
1015
1016         dep->flags |= DWC3_EP_BUSY;
1017
1018         if (start_new) {
1019                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1020                                 dep->number);
1021                 WARN_ON_ONCE(!dep->resource_index);
1022         }
1023
1024         return 0;
1025 }
1026
1027 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1028                 struct dwc3_ep *dep, u32 cur_uf)
1029 {
1030         u32 uf;
1031
1032         if (list_empty(&dep->request_list)) {
1033                 dev_vdbg(dwc->dev, "ISOC ep %s run out for requests.\n",
1034                         dep->name);
1035                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1036                 return;
1037         }
1038
1039         /* 4 micro frames in the future */
1040         uf = cur_uf + dep->interval * 4;
1041
1042         __dwc3_gadget_kick_transfer(dep, uf, 1);
1043 }
1044
1045 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1046                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1047 {
1048         u32 cur_uf, mask;
1049
1050         mask = ~(dep->interval - 1);
1051         cur_uf = event->parameters & mask;
1052
1053         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1054 }
1055
1056 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1057 {
1058         struct dwc3             *dwc = dep->dwc;
1059         int                     ret;
1060
1061         req->request.actual     = 0;
1062         req->request.status     = -EINPROGRESS;
1063         req->direction          = dep->direction;
1064         req->epnum              = dep->number;
1065
1066         /*
1067          * We only add to our list of requests now and
1068          * start consuming the list once we get XferNotReady
1069          * IRQ.
1070          *
1071          * That way, we avoid doing anything that we don't need
1072          * to do now and defer it until the point we receive a
1073          * particular token from the Host side.
1074          *
1075          * This will also avoid Host cancelling URBs due to too
1076          * many NAKs.
1077          */
1078         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1079                         dep->direction);
1080         if (ret)
1081                 return ret;
1082
1083         list_add_tail(&req->list, &dep->request_list);
1084
1085         /*
1086          * There are a few special cases:
1087          *
1088          * 1. XferNotReady with empty list of requests. We need to kick the
1089          *    transfer here in that situation, otherwise we will be NAKing
1090          *    forever. If we get XferNotReady before gadget driver has a
1091          *    chance to queue a request, we will ACK the IRQ but won't be
1092          *    able to receive the data until the next request is queued.
1093          *    The following code is handling exactly that.
1094          *
1095          */
1096         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1097                 /*
1098                  * If xfernotready is already elapsed and it is a case
1099                  * of isoc transfer, then issue END TRANSFER, so that
1100                  * you can receive xfernotready again and can have
1101                  * notion of current microframe.
1102                  */
1103                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1104                         if (list_empty(&dep->req_queued)) {
1105                                 dwc3_stop_active_transfer(dwc, dep->number);
1106                                 dep->flags = DWC3_EP_ENABLED;
1107                         }
1108                         return 0;
1109                 }
1110
1111                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1112                 if (ret && ret != -EBUSY)
1113                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1114                                         dep->name);
1115                 return ret;
1116         }
1117
1118         /*
1119          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1120          *    kick the transfer here after queuing a request, otherwise the
1121          *    core may not see the modified TRB(s).
1122          */
1123         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1124                         (dep->flags & DWC3_EP_BUSY) &&
1125                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1126                 WARN_ON_ONCE(!dep->resource_index);
1127                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1128                                 false);
1129                 if (ret && ret != -EBUSY)
1130                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1131                                         dep->name);
1132                 return ret;
1133         }
1134
1135         return 0;
1136 }
1137
1138 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1139         gfp_t gfp_flags)
1140 {
1141         struct dwc3_request             *req = to_dwc3_request(request);
1142         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1143         struct dwc3                     *dwc = dep->dwc;
1144
1145         unsigned long                   flags;
1146
1147         int                             ret;
1148
1149         if (!dep->endpoint.desc) {
1150                 dev_dbg(dwc->dev, "trying to queue request %p to disabled %s\n",
1151                                 request, ep->name);
1152                 return -ESHUTDOWN;
1153         }
1154
1155         dev_vdbg(dwc->dev, "queing request %p to %s length %d\n",
1156                         request, ep->name, request->length);
1157
1158         spin_lock_irqsave(&dwc->lock, flags);
1159         ret = __dwc3_gadget_ep_queue(dep, req);
1160         spin_unlock_irqrestore(&dwc->lock, flags);
1161
1162         return ret;
1163 }
1164
1165 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1166                 struct usb_request *request)
1167 {
1168         struct dwc3_request             *req = to_dwc3_request(request);
1169         struct dwc3_request             *r = NULL;
1170
1171         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1172         struct dwc3                     *dwc = dep->dwc;
1173
1174         unsigned long                   flags;
1175         int                             ret = 0;
1176
1177         spin_lock_irqsave(&dwc->lock, flags);
1178
1179         list_for_each_entry(r, &dep->request_list, list) {
1180                 if (r == req)
1181                         break;
1182         }
1183
1184         if (r != req) {
1185                 list_for_each_entry(r, &dep->req_queued, list) {
1186                         if (r == req)
1187                                 break;
1188                 }
1189                 if (r == req) {
1190                         /* wait until it is processed */
1191                         dwc3_stop_active_transfer(dwc, dep->number);
1192                         goto out1;
1193                 }
1194                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1195                                 request, ep->name);
1196                 ret = -EINVAL;
1197                 goto out0;
1198         }
1199
1200 out1:
1201         /* giveback the request */
1202         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1203
1204 out0:
1205         spin_unlock_irqrestore(&dwc->lock, flags);
1206
1207         return ret;
1208 }
1209
1210 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1211 {
1212         struct dwc3_gadget_ep_cmd_params        params;
1213         struct dwc3                             *dwc = dep->dwc;
1214         int                                     ret;
1215
1216         memset(&params, 0x00, sizeof(params));
1217
1218         if (value) {
1219                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1220                                 (!list_empty(&dep->req_queued) ||
1221                                  !list_empty(&dep->request_list)))) {
1222                         dev_dbg(dwc->dev, "%s: pending request, cannot halt\n",
1223                                         dep->name);
1224                         return -EAGAIN;
1225                 }
1226
1227                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1228                         DWC3_DEPCMD_SETSTALL, &params);
1229                 if (ret)
1230                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1231                                         value ? "set" : "clear",
1232                                         dep->name);
1233                 else
1234                         dep->flags |= DWC3_EP_STALL;
1235         } else {
1236                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1237                         DWC3_DEPCMD_CLEARSTALL, &params);
1238                 if (ret)
1239                         dev_err(dwc->dev, "failed to %s STALL on %s\n",
1240                                         value ? "set" : "clear",
1241                                         dep->name);
1242                 else
1243                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1244         }
1245
1246         return ret;
1247 }
1248
1249 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1250 {
1251         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1252         struct dwc3                     *dwc = dep->dwc;
1253
1254         unsigned long                   flags;
1255
1256         int                             ret;
1257
1258         spin_lock_irqsave(&dwc->lock, flags);
1259
1260         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1261                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1262                 ret = -EINVAL;
1263                 goto out;
1264         }
1265
1266         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1267 out:
1268         spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270         return ret;
1271 }
1272
1273 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1274 {
1275         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1276         struct dwc3                     *dwc = dep->dwc;
1277         unsigned long                   flags;
1278
1279         spin_lock_irqsave(&dwc->lock, flags);
1280         dep->flags |= DWC3_EP_WEDGE;
1281         spin_unlock_irqrestore(&dwc->lock, flags);
1282
1283         if (dep->number == 0 || dep->number == 1)
1284                 return dwc3_gadget_ep0_set_halt(ep, 1);
1285         else
1286                 return __dwc3_gadget_ep_set_halt(dep, 1, false);
1287 }
1288
1289 /* -------------------------------------------------------------------------- */
1290
1291 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1292         .bLength        = USB_DT_ENDPOINT_SIZE,
1293         .bDescriptorType = USB_DT_ENDPOINT,
1294         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1295 };
1296
1297 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1298         .enable         = dwc3_gadget_ep0_enable,
1299         .disable        = dwc3_gadget_ep0_disable,
1300         .alloc_request  = dwc3_gadget_ep_alloc_request,
1301         .free_request   = dwc3_gadget_ep_free_request,
1302         .queue          = dwc3_gadget_ep0_queue,
1303         .dequeue        = dwc3_gadget_ep_dequeue,
1304         .set_halt       = dwc3_gadget_ep0_set_halt,
1305         .set_wedge      = dwc3_gadget_ep_set_wedge,
1306 };
1307
1308 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1309         .enable         = dwc3_gadget_ep_enable,
1310         .disable        = dwc3_gadget_ep_disable,
1311         .alloc_request  = dwc3_gadget_ep_alloc_request,
1312         .free_request   = dwc3_gadget_ep_free_request,
1313         .queue          = dwc3_gadget_ep_queue,
1314         .dequeue        = dwc3_gadget_ep_dequeue,
1315         .set_halt       = dwc3_gadget_ep_set_halt,
1316         .set_wedge      = dwc3_gadget_ep_set_wedge,
1317 };
1318
1319 /* -------------------------------------------------------------------------- */
1320
1321 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1322 {
1323         struct dwc3             *dwc = gadget_to_dwc(g);
1324         u32                     reg;
1325
1326         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1327         return DWC3_DSTS_SOFFN(reg);
1328 }
1329
1330 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1331 {
1332         struct dwc3             *dwc = gadget_to_dwc(g);
1333
1334         unsigned long           timeout;
1335         unsigned long           flags;
1336
1337         u32                     reg;
1338
1339         int                     ret = 0;
1340
1341         u8                      link_state;
1342         u8                      speed;
1343
1344         spin_lock_irqsave(&dwc->lock, flags);
1345
1346         /*
1347          * According to the Databook Remote wakeup request should
1348          * be issued only when the device is in early suspend state.
1349          *
1350          * We can check that via USB Link State bits in DSTS register.
1351          */
1352         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1353
1354         speed = reg & DWC3_DSTS_CONNECTSPD;
1355         if (speed == DWC3_DSTS_SUPERSPEED) {
1356                 dev_dbg(dwc->dev, "no wakeup on SuperSpeed\n");
1357                 ret = -EINVAL;
1358                 goto out;
1359         }
1360
1361         link_state = DWC3_DSTS_USBLNKST(reg);
1362
1363         switch (link_state) {
1364         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1365         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1366                 break;
1367         default:
1368                 dev_dbg(dwc->dev, "can't wakeup from link state %d\n",
1369                                 link_state);
1370                 ret = -EINVAL;
1371                 goto out;
1372         }
1373
1374         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1375         if (ret < 0) {
1376                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1377                 goto out;
1378         }
1379
1380         /* Recent versions do this automatically */
1381         if (dwc->revision < DWC3_REVISION_194A) {
1382                 /* write zeroes to Link Change Request */
1383                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1384                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1385                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1386         }
1387
1388         /* poll until Link State changes to ON */
1389         timeout = jiffies + msecs_to_jiffies(100);
1390
1391         while (!time_after(jiffies, timeout)) {
1392                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1393
1394                 /* in HS, means ON */
1395                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1396                         break;
1397         }
1398
1399         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1400                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1401                 ret = -EINVAL;
1402         }
1403
1404 out:
1405         spin_unlock_irqrestore(&dwc->lock, flags);
1406
1407         return ret;
1408 }
1409
1410 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1411                 int is_selfpowered)
1412 {
1413         struct dwc3             *dwc = gadget_to_dwc(g);
1414         unsigned long           flags;
1415
1416         spin_lock_irqsave(&dwc->lock, flags);
1417         dwc->is_selfpowered = !!is_selfpowered;
1418         spin_unlock_irqrestore(&dwc->lock, flags);
1419
1420         return 0;
1421 }
1422
1423 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on)
1424 {
1425         u32                     reg;
1426         u32                     timeout = 500;
1427
1428         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1429         if (is_on) {
1430                 if (dwc->revision <= DWC3_REVISION_187A) {
1431                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1432                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1433                 }
1434
1435                 if (dwc->revision >= DWC3_REVISION_194A)
1436                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1437                 reg |= DWC3_DCTL_RUN_STOP;
1438                 dwc->pullups_connected = true;
1439         } else {
1440                 reg &= ~DWC3_DCTL_RUN_STOP;
1441                 dwc->pullups_connected = false;
1442         }
1443
1444         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1445
1446         do {
1447                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1448                 if (is_on) {
1449                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1450                                 break;
1451                 } else {
1452                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1453                                 break;
1454                 }
1455                 timeout--;
1456                 if (!timeout)
1457                         return -ETIMEDOUT;
1458                 udelay(1);
1459         } while (1);
1460
1461         dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
1462                         dwc->gadget_driver
1463                         ? dwc->gadget_driver->function : "no-function",
1464                         is_on ? "connect" : "disconnect");
1465
1466         return 0;
1467 }
1468
1469 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1470 {
1471         struct dwc3             *dwc = gadget_to_dwc(g);
1472         unsigned long           flags;
1473         int                     ret;
1474
1475         is_on = !!is_on;
1476
1477         spin_lock_irqsave(&dwc->lock, flags);
1478         ret = dwc3_gadget_run_stop(dwc, is_on);
1479         spin_unlock_irqrestore(&dwc->lock, flags);
1480
1481         return ret;
1482 }
1483
1484 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1485 {
1486         u32                     reg;
1487
1488         /* Enable all but Start and End of Frame IRQs */
1489         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1490                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1491                         DWC3_DEVTEN_CMDCMPLTEN |
1492                         DWC3_DEVTEN_ERRTICERREN |
1493                         DWC3_DEVTEN_WKUPEVTEN |
1494                         DWC3_DEVTEN_ULSTCNGEN |
1495                         DWC3_DEVTEN_CONNECTDONEEN |
1496                         DWC3_DEVTEN_USBRSTEN |
1497                         DWC3_DEVTEN_DISCONNEVTEN);
1498
1499         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1500 }
1501
1502 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1503 {
1504         /* mask all interrupts */
1505         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1506 }
1507
1508 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1509 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1510
1511 static int dwc3_gadget_start(struct usb_gadget *g,
1512                 struct usb_gadget_driver *driver)
1513 {
1514         struct dwc3             *dwc = gadget_to_dwc(g);
1515         struct dwc3_ep          *dep;
1516         unsigned long           flags;
1517         int                     ret = 0;
1518         int                     irq;
1519         u32                     reg;
1520
1521         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1522         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1523                         IRQF_SHARED | IRQF_ONESHOT, "dwc3", dwc);
1524         if (ret) {
1525                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1526                                 irq, ret);
1527                 goto err0;
1528         }
1529
1530         spin_lock_irqsave(&dwc->lock, flags);
1531
1532         if (dwc->gadget_driver) {
1533                 dev_err(dwc->dev, "%s is already bound to %s\n",
1534                                 dwc->gadget.name,
1535                                 dwc->gadget_driver->driver.name);
1536                 ret = -EBUSY;
1537                 goto err1;
1538         }
1539
1540         dwc->gadget_driver      = driver;
1541
1542         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1543         reg &= ~(DWC3_DCFG_SPEED_MASK);
1544
1545         /**
1546          * WORKAROUND: DWC3 revision < 2.20a have an issue
1547          * which would cause metastability state on Run/Stop
1548          * bit if we try to force the IP to USB2-only mode.
1549          *
1550          * Because of that, we cannot configure the IP to any
1551          * speed other than the SuperSpeed
1552          *
1553          * Refers to:
1554          *
1555          * STAR#9000525659: Clock Domain Crossing on DCTL in
1556          * USB 2.0 Mode
1557          */
1558         if (dwc->revision < DWC3_REVISION_220A)
1559                 reg |= DWC3_DCFG_SUPERSPEED;
1560         else
1561                 reg |= dwc->maximum_speed;
1562         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1563
1564         dwc->start_config_issued = false;
1565
1566         /* Start with SuperSpeed Default */
1567         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1568
1569         dep = dwc->eps[0];
1570         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1571         if (ret) {
1572                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1573                 goto err2;
1574         }
1575
1576         dep = dwc->eps[1];
1577         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
1578         if (ret) {
1579                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1580                 goto err3;
1581         }
1582
1583         /* begin to receive SETUP packets */
1584         dwc->ep0state = EP0_SETUP_PHASE;
1585         dwc3_ep0_out_start(dwc);
1586
1587         dwc3_gadget_enable_irq(dwc);
1588
1589         spin_unlock_irqrestore(&dwc->lock, flags);
1590
1591         return 0;
1592
1593 err3:
1594         __dwc3_gadget_ep_disable(dwc->eps[0]);
1595
1596 err2:
1597         dwc->gadget_driver = NULL;
1598
1599 err1:
1600         spin_unlock_irqrestore(&dwc->lock, flags);
1601
1602         free_irq(irq, dwc);
1603
1604 err0:
1605         return ret;
1606 }
1607
1608 static int dwc3_gadget_stop(struct usb_gadget *g,
1609                 struct usb_gadget_driver *driver)
1610 {
1611         struct dwc3             *dwc = gadget_to_dwc(g);
1612         unsigned long           flags;
1613         int                     irq;
1614
1615         spin_lock_irqsave(&dwc->lock, flags);
1616
1617         dwc3_gadget_disable_irq(dwc);
1618         __dwc3_gadget_ep_disable(dwc->eps[0]);
1619         __dwc3_gadget_ep_disable(dwc->eps[1]);
1620
1621         dwc->gadget_driver      = NULL;
1622
1623         spin_unlock_irqrestore(&dwc->lock, flags);
1624
1625         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1626         free_irq(irq, dwc);
1627
1628         return 0;
1629 }
1630
1631 static const struct usb_gadget_ops dwc3_gadget_ops = {
1632         .get_frame              = dwc3_gadget_get_frame,
1633         .wakeup                 = dwc3_gadget_wakeup,
1634         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1635         .pullup                 = dwc3_gadget_pullup,
1636         .udc_start              = dwc3_gadget_start,
1637         .udc_stop               = dwc3_gadget_stop,
1638 };
1639
1640 /* -------------------------------------------------------------------------- */
1641
1642 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1643                 u8 num, u32 direction)
1644 {
1645         struct dwc3_ep                  *dep;
1646         u8                              i;
1647
1648         for (i = 0; i < num; i++) {
1649                 u8 epnum = (i << 1) | (!!direction);
1650
1651                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1652                 if (!dep) {
1653                         dev_err(dwc->dev, "can't allocate endpoint %d\n",
1654                                         epnum);
1655                         return -ENOMEM;
1656                 }
1657
1658                 dep->dwc = dwc;
1659                 dep->number = epnum;
1660                 dwc->eps[epnum] = dep;
1661
1662                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1663                                 (epnum & 1) ? "in" : "out");
1664
1665                 dep->endpoint.name = dep->name;
1666                 dep->direction = (epnum & 1);
1667
1668                 if (epnum == 0 || epnum == 1) {
1669                         dep->endpoint.maxpacket = 512;
1670                         dep->endpoint.maxburst = 1;
1671                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1672                         if (!epnum)
1673                                 dwc->gadget.ep0 = &dep->endpoint;
1674                 } else {
1675                         int             ret;
1676
1677                         dep->endpoint.maxpacket = 1024;
1678                         dep->endpoint.max_streams = 15;
1679                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1680                         list_add_tail(&dep->endpoint.ep_list,
1681                                         &dwc->gadget.ep_list);
1682
1683                         ret = dwc3_alloc_trb_pool(dep);
1684                         if (ret)
1685                                 return ret;
1686                 }
1687
1688                 INIT_LIST_HEAD(&dep->request_list);
1689                 INIT_LIST_HEAD(&dep->req_queued);
1690         }
1691
1692         return 0;
1693 }
1694
1695 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1696 {
1697         int                             ret;
1698
1699         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1700
1701         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1702         if (ret < 0) {
1703                 dev_vdbg(dwc->dev, "failed to allocate OUT endpoints\n");
1704                 return ret;
1705         }
1706
1707         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1708         if (ret < 0) {
1709                 dev_vdbg(dwc->dev, "failed to allocate IN endpoints\n");
1710                 return ret;
1711         }
1712
1713         return 0;
1714 }
1715
1716 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1717 {
1718         struct dwc3_ep                  *dep;
1719         u8                              epnum;
1720
1721         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1722                 dep = dwc->eps[epnum];
1723                 if (!dep)
1724                         continue;
1725                 /*
1726                  * Physical endpoints 0 and 1 are special; they form the
1727                  * bi-directional USB endpoint 0.
1728                  *
1729                  * For those two physical endpoints, we don't allocate a TRB
1730                  * pool nor do we add them the endpoints list. Due to that, we
1731                  * shouldn't do these two operations otherwise we would end up
1732                  * with all sorts of bugs when removing dwc3.ko.
1733                  */
1734                 if (epnum != 0 && epnum != 1) {
1735                         dwc3_free_trb_pool(dep);
1736                         list_del(&dep->endpoint.ep_list);
1737                 }
1738
1739                 kfree(dep);
1740         }
1741 }
1742
1743 /* -------------------------------------------------------------------------- */
1744
1745 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1746                 struct dwc3_request *req, struct dwc3_trb *trb,
1747                 const struct dwc3_event_depevt *event, int status)
1748 {
1749         unsigned int            count;
1750         unsigned int            s_pkt = 0;
1751         unsigned int            trb_status;
1752
1753         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1754                 /*
1755                  * We continue despite the error. There is not much we
1756                  * can do. If we don't clean it up we loop forever. If
1757                  * we skip the TRB then it gets overwritten after a
1758                  * while since we use them in a ring buffer. A BUG()
1759                  * would help. Lets hope that if this occurs, someone
1760                  * fixes the root cause instead of looking away :)
1761                  */
1762                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1763                                 dep->name, trb);
1764         count = trb->size & DWC3_TRB_SIZE_MASK;
1765
1766         if (dep->direction) {
1767                 if (count) {
1768                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1769                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1770                                 dev_dbg(dwc->dev, "incomplete IN transfer %s\n",
1771                                                 dep->name);
1772                                 /*
1773                                  * If missed isoc occurred and there is
1774                                  * no request queued then issue END
1775                                  * TRANSFER, so that core generates
1776                                  * next xfernotready and we will issue
1777                                  * a fresh START TRANSFER.
1778                                  * If there are still queued request
1779                                  * then wait, do not issue either END
1780                                  * or UPDATE TRANSFER, just attach next
1781                                  * request in request_list during
1782                                  * giveback.If any future queued request
1783                                  * is successfully transferred then we
1784                                  * will issue UPDATE TRANSFER for all
1785                                  * request in the request_list.
1786                                  */
1787                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1788                         } else {
1789                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1790                                                 dep->name);
1791                                 status = -ECONNRESET;
1792                         }
1793                 } else {
1794                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1795                 }
1796         } else {
1797                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1798                         s_pkt = 1;
1799         }
1800
1801         /*
1802          * We assume here we will always receive the entire data block
1803          * which we should receive. Meaning, if we program RX to
1804          * receive 4K but we receive only 2K, we assume that's all we
1805          * should receive and we simply bounce the request back to the
1806          * gadget driver for further processing.
1807          */
1808         req->request.actual += req->request.length - count;
1809         if (s_pkt)
1810                 return 1;
1811         if ((event->status & DEPEVT_STATUS_LST) &&
1812                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1813                                 DWC3_TRB_CTRL_HWO)))
1814                 return 1;
1815         if ((event->status & DEPEVT_STATUS_IOC) &&
1816                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1817                 return 1;
1818         return 0;
1819 }
1820
1821 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1822                 const struct dwc3_event_depevt *event, int status)
1823 {
1824         struct dwc3_request     *req;
1825         struct dwc3_trb         *trb;
1826         unsigned int            slot;
1827         unsigned int            i;
1828         int                     ret;
1829
1830         do {
1831                 req = next_request(&dep->req_queued);
1832                 if (!req) {
1833                         WARN_ON_ONCE(1);
1834                         return 1;
1835                 }
1836                 i = 0;
1837                 do {
1838                         slot = req->start_slot + i;
1839                         if ((slot == DWC3_TRB_NUM - 1) &&
1840                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1841                                 slot++;
1842                         slot %= DWC3_TRB_NUM;
1843                         trb = &dep->trb_pool[slot];
1844
1845                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1846                                         event, status);
1847                         if (ret)
1848                                 break;
1849                 }while (++i < req->request.num_mapped_sgs);
1850
1851                 dwc3_gadget_giveback(dep, req, status);
1852
1853                 if (ret)
1854                         break;
1855         } while (1);
1856
1857         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1858                         list_empty(&dep->req_queued)) {
1859                 if (list_empty(&dep->request_list)) {
1860                         /*
1861                          * If there is no entry in request list then do
1862                          * not issue END TRANSFER now. Just set PENDING
1863                          * flag, so that END TRANSFER is issued when an
1864                          * entry is added into request list.
1865                          */
1866                         dep->flags = DWC3_EP_PENDING_REQUEST;
1867                 } else {
1868                         dwc3_stop_active_transfer(dwc, dep->number);
1869                         dep->flags = DWC3_EP_ENABLED;
1870                 }
1871                 return 1;
1872         }
1873
1874         if ((event->status & DEPEVT_STATUS_IOC) &&
1875                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1876                 return 0;
1877         return 1;
1878 }
1879
1880 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
1881                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event,
1882                 int start_new)
1883 {
1884         unsigned                status = 0;
1885         int                     clean_busy;
1886
1887         if (event->status & DEPEVT_STATUS_BUSERR)
1888                 status = -ECONNRESET;
1889
1890         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
1891         if (clean_busy)
1892                 dep->flags &= ~DWC3_EP_BUSY;
1893
1894         /*
1895          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
1896          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
1897          */
1898         if (dwc->revision < DWC3_REVISION_183A) {
1899                 u32             reg;
1900                 int             i;
1901
1902                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
1903                         dep = dwc->eps[i];
1904
1905                         if (!(dep->flags & DWC3_EP_ENABLED))
1906                                 continue;
1907
1908                         if (!list_empty(&dep->req_queued))
1909                                 return;
1910                 }
1911
1912                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1913                 reg |= dwc->u1u2;
1914                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1915
1916                 dwc->u1u2 = 0;
1917         }
1918 }
1919
1920 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
1921                 const struct dwc3_event_depevt *event)
1922 {
1923         struct dwc3_ep          *dep;
1924         u8                      epnum = event->endpoint_number;
1925
1926         dep = dwc->eps[epnum];
1927
1928         if (!(dep->flags & DWC3_EP_ENABLED))
1929                 return;
1930
1931         dev_vdbg(dwc->dev, "%s: %s\n", dep->name,
1932                         dwc3_ep_event_string(event->endpoint_event));
1933
1934         if (epnum == 0 || epnum == 1) {
1935                 dwc3_ep0_interrupt(dwc, event);
1936                 return;
1937         }
1938
1939         switch (event->endpoint_event) {
1940         case DWC3_DEPEVT_XFERCOMPLETE:
1941                 dep->resource_index = 0;
1942
1943                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1944                         dev_dbg(dwc->dev, "%s is an Isochronous endpoint\n",
1945                                         dep->name);
1946                         return;
1947                 }
1948
1949                 dwc3_endpoint_transfer_complete(dwc, dep, event, 1);
1950                 break;
1951         case DWC3_DEPEVT_XFERINPROGRESS:
1952                 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1953                         dev_dbg(dwc->dev, "%s is not an Isochronous endpoint\n",
1954                                         dep->name);
1955                         return;
1956                 }
1957
1958                 dwc3_endpoint_transfer_complete(dwc, dep, event, 0);
1959                 break;
1960         case DWC3_DEPEVT_XFERNOTREADY:
1961                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1962                         dwc3_gadget_start_isoc(dwc, dep, event);
1963                 } else {
1964                         int ret;
1965
1966                         dev_vdbg(dwc->dev, "%s: reason %s\n",
1967                                         dep->name, event->status &
1968                                         DEPEVT_STATUS_TRANSFER_ACTIVE
1969                                         ? "Transfer Active"
1970                                         : "Transfer Not Active");
1971
1972                         ret = __dwc3_gadget_kick_transfer(dep, 0, 1);
1973                         if (!ret || ret == -EBUSY)
1974                                 return;
1975
1976                         dev_dbg(dwc->dev, "%s: failed to kick transfers\n",
1977                                         dep->name);
1978                 }
1979
1980                 break;
1981         case DWC3_DEPEVT_STREAMEVT:
1982                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
1983                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
1984                                         dep->name);
1985                         return;
1986                 }
1987
1988                 switch (event->status) {
1989                 case DEPEVT_STREAMEVT_FOUND:
1990                         dev_vdbg(dwc->dev, "Stream %d found and started\n",
1991                                         event->parameters);
1992
1993                         break;
1994                 case DEPEVT_STREAMEVT_NOTFOUND:
1995                         /* FALLTHROUGH */
1996                 default:
1997                         dev_dbg(dwc->dev, "Couldn't find suitable stream\n");
1998                 }
1999                 break;
2000         case DWC3_DEPEVT_RXTXFIFOEVT:
2001                 dev_dbg(dwc->dev, "%s FIFO Overrun\n", dep->name);
2002                 break;
2003         case DWC3_DEPEVT_EPCMDCMPLT:
2004                 dev_vdbg(dwc->dev, "Endpoint Command Complete\n");
2005                 break;
2006         }
2007 }
2008
2009 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2010 {
2011         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2012                 spin_unlock(&dwc->lock);
2013                 dwc->gadget_driver->disconnect(&dwc->gadget);
2014                 spin_lock(&dwc->lock);
2015         }
2016 }
2017
2018 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum)
2019 {
2020         struct dwc3_ep *dep;
2021         struct dwc3_gadget_ep_cmd_params params;
2022         u32 cmd;
2023         int ret;
2024
2025         dep = dwc->eps[epnum];
2026
2027         if (!dep->resource_index)
2028                 return;
2029
2030         /*
2031          * NOTICE: We are violating what the Databook says about the
2032          * EndTransfer command. Ideally we would _always_ wait for the
2033          * EndTransfer Command Completion IRQ, but that's causing too
2034          * much trouble synchronizing between us and gadget driver.
2035          *
2036          * We have discussed this with the IP Provider and it was
2037          * suggested to giveback all requests here, but give HW some
2038          * extra time to synchronize with the interconnect. We're using
2039          * an arbitraty 100us delay for that.
2040          *
2041          * Note also that a similar handling was tested by Synopsys
2042          * (thanks a lot Paul) and nothing bad has come out of it.
2043          * In short, what we're doing is:
2044          *
2045          * - Issue EndTransfer WITH CMDIOC bit set
2046          * - Wait 100us
2047          */
2048
2049         cmd = DWC3_DEPCMD_ENDTRANSFER;
2050         cmd |= DWC3_DEPCMD_HIPRI_FORCERM | DWC3_DEPCMD_CMDIOC;
2051         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2052         memset(&params, 0, sizeof(params));
2053         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2054         WARN_ON_ONCE(ret);
2055         dep->resource_index = 0;
2056         dep->flags &= ~DWC3_EP_BUSY;
2057         udelay(100);
2058 }
2059
2060 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2061 {
2062         u32 epnum;
2063
2064         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2065                 struct dwc3_ep *dep;
2066
2067                 dep = dwc->eps[epnum];
2068                 if (!dep)
2069                         continue;
2070
2071                 if (!(dep->flags & DWC3_EP_ENABLED))
2072                         continue;
2073
2074                 dwc3_remove_requests(dwc, dep);
2075         }
2076 }
2077
2078 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2079 {
2080         u32 epnum;
2081
2082         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2083                 struct dwc3_ep *dep;
2084                 struct dwc3_gadget_ep_cmd_params params;
2085                 int ret;
2086
2087                 dep = dwc->eps[epnum];
2088                 if (!dep)
2089                         continue;
2090
2091                 if (!(dep->flags & DWC3_EP_STALL))
2092                         continue;
2093
2094                 dep->flags &= ~DWC3_EP_STALL;
2095
2096                 memset(&params, 0, sizeof(params));
2097                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2098                                 DWC3_DEPCMD_CLEARSTALL, &params);
2099                 WARN_ON_ONCE(ret);
2100         }
2101 }
2102
2103 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2104 {
2105         int                     reg;
2106
2107         dev_vdbg(dwc->dev, "%s\n", __func__);
2108
2109         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2110         reg &= ~DWC3_DCTL_INITU1ENA;
2111         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2112
2113         reg &= ~DWC3_DCTL_INITU2ENA;
2114         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2115
2116         dwc3_disconnect_gadget(dwc);
2117         dwc->start_config_issued = false;
2118
2119         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2120         dwc->setup_packet_pending = false;
2121 }
2122
2123 static void dwc3_gadget_usb3_phy_suspend(struct dwc3 *dwc, int suspend)
2124 {
2125         u32                     reg;
2126
2127         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
2128
2129         if (suspend)
2130                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
2131         else
2132                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
2133
2134         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
2135 }
2136
2137 static void dwc3_gadget_usb2_phy_suspend(struct dwc3 *dwc, int suspend)
2138 {
2139         u32                     reg;
2140
2141         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2142
2143         if (suspend)
2144                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
2145         else
2146                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2147
2148         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2149 }
2150
2151 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2152 {
2153         u32                     reg;
2154
2155         dev_vdbg(dwc->dev, "%s\n", __func__);
2156
2157         /*
2158          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2159          * would cause a missing Disconnect Event if there's a
2160          * pending Setup Packet in the FIFO.
2161          *
2162          * There's no suggested workaround on the official Bug
2163          * report, which states that "unless the driver/application
2164          * is doing any special handling of a disconnect event,
2165          * there is no functional issue".
2166          *
2167          * Unfortunately, it turns out that we _do_ some special
2168          * handling of a disconnect event, namely complete all
2169          * pending transfers, notify gadget driver of the
2170          * disconnection, and so on.
2171          *
2172          * Our suggested workaround is to follow the Disconnect
2173          * Event steps here, instead, based on a setup_packet_pending
2174          * flag. Such flag gets set whenever we have a XferNotReady
2175          * event on EP0 and gets cleared on XferComplete for the
2176          * same endpoint.
2177          *
2178          * Refers to:
2179          *
2180          * STAR#9000466709: RTL: Device : Disconnect event not
2181          * generated if setup packet pending in FIFO
2182          */
2183         if (dwc->revision < DWC3_REVISION_188A) {
2184                 if (dwc->setup_packet_pending)
2185                         dwc3_gadget_disconnect_interrupt(dwc);
2186         }
2187
2188         /* after reset -> Default State */
2189         usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
2190
2191         /* Recent versions support automatic phy suspend and don't need this */
2192         if (dwc->revision < DWC3_REVISION_194A) {
2193                 /* Resume PHYs */
2194                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2195                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2196         }
2197
2198         if (dwc->gadget.speed != USB_SPEED_UNKNOWN)
2199                 dwc3_disconnect_gadget(dwc);
2200
2201         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2202         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2203         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2204         dwc->test_mode = false;
2205
2206         dwc3_stop_active_transfers(dwc);
2207         dwc3_clear_stall_all_ep(dwc);
2208         dwc->start_config_issued = false;
2209
2210         /* Reset device address to zero */
2211         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2212         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2213         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2214 }
2215
2216 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2217 {
2218         u32 reg;
2219         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2220
2221         /*
2222          * We change the clock only at SS but I dunno why I would want to do
2223          * this. Maybe it becomes part of the power saving plan.
2224          */
2225
2226         if (speed != DWC3_DSTS_SUPERSPEED)
2227                 return;
2228
2229         /*
2230          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2231          * each time on Connect Done.
2232          */
2233         if (!usb30_clock)
2234                 return;
2235
2236         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2237         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2238         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2239 }
2240
2241 static void dwc3_gadget_phy_suspend(struct dwc3 *dwc, u8 speed)
2242 {
2243         switch (speed) {
2244         case USB_SPEED_SUPER:
2245                 dwc3_gadget_usb2_phy_suspend(dwc, true);
2246                 break;
2247         case USB_SPEED_HIGH:
2248         case USB_SPEED_FULL:
2249         case USB_SPEED_LOW:
2250                 dwc3_gadget_usb3_phy_suspend(dwc, true);
2251                 break;
2252         }
2253 }
2254
2255 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2256 {
2257         struct dwc3_ep          *dep;
2258         int                     ret;
2259         u32                     reg;
2260         u8                      speed;
2261
2262         dev_vdbg(dwc->dev, "%s\n", __func__);
2263
2264         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2265         speed = reg & DWC3_DSTS_CONNECTSPD;
2266         dwc->speed = speed;
2267
2268         dwc3_update_ram_clk_sel(dwc, speed);
2269
2270         switch (speed) {
2271         case DWC3_DCFG_SUPERSPEED:
2272                 /*
2273                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2274                  * would cause a missing USB3 Reset event.
2275                  *
2276                  * In such situations, we should force a USB3 Reset
2277                  * event by calling our dwc3_gadget_reset_interrupt()
2278                  * routine.
2279                  *
2280                  * Refers to:
2281                  *
2282                  * STAR#9000483510: RTL: SS : USB3 reset event may
2283                  * not be generated always when the link enters poll
2284                  */
2285                 if (dwc->revision < DWC3_REVISION_190A)
2286                         dwc3_gadget_reset_interrupt(dwc);
2287
2288                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2289                 dwc->gadget.ep0->maxpacket = 512;
2290                 dwc->gadget.speed = USB_SPEED_SUPER;
2291                 break;
2292         case DWC3_DCFG_HIGHSPEED:
2293                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2294                 dwc->gadget.ep0->maxpacket = 64;
2295                 dwc->gadget.speed = USB_SPEED_HIGH;
2296                 break;
2297         case DWC3_DCFG_FULLSPEED2:
2298         case DWC3_DCFG_FULLSPEED1:
2299                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2300                 dwc->gadget.ep0->maxpacket = 64;
2301                 dwc->gadget.speed = USB_SPEED_FULL;
2302                 break;
2303         case DWC3_DCFG_LOWSPEED:
2304                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2305                 dwc->gadget.ep0->maxpacket = 8;
2306                 dwc->gadget.speed = USB_SPEED_LOW;
2307                 break;
2308         }
2309
2310         /* Enable USB2 LPM Capability */
2311
2312         if ((dwc->revision > DWC3_REVISION_194A)
2313                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2314                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2315                 reg |= DWC3_DCFG_LPM_CAP;
2316                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2317
2318                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2319                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2320
2321                 /*
2322                  * TODO: This should be configurable. For now using
2323                  * maximum allowed HIRD threshold value of 0b1100
2324                  */
2325                 reg |= DWC3_DCTL_HIRD_THRES(12);
2326
2327                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2328         }
2329
2330         /* Recent versions support automatic phy suspend and don't need this */
2331         if (dwc->revision < DWC3_REVISION_194A) {
2332                 /* Suspend unneeded PHY */
2333                 dwc3_gadget_phy_suspend(dwc, dwc->gadget.speed);
2334         }
2335
2336         dep = dwc->eps[0];
2337         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2338         if (ret) {
2339                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2340                 return;
2341         }
2342
2343         dep = dwc->eps[1];
2344         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true);
2345         if (ret) {
2346                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2347                 return;
2348         }
2349
2350         /*
2351          * Configure PHY via GUSB3PIPECTLn if required.
2352          *
2353          * Update GTXFIFOSIZn
2354          *
2355          * In both cases reset values should be sufficient.
2356          */
2357 }
2358
2359 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2360 {
2361         dev_vdbg(dwc->dev, "%s\n", __func__);
2362
2363         /*
2364          * TODO take core out of low power mode when that's
2365          * implemented.
2366          */
2367
2368         dwc->gadget_driver->resume(&dwc->gadget);
2369 }
2370
2371 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2372                 unsigned int evtinfo)
2373 {
2374         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2375         unsigned int            pwropt;
2376
2377         /*
2378          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2379          * Hibernation mode enabled which would show up when device detects
2380          * host-initiated U3 exit.
2381          *
2382          * In that case, device will generate a Link State Change Interrupt
2383          * from U3 to RESUME which is only necessary if Hibernation is
2384          * configured in.
2385          *
2386          * There are no functional changes due to such spurious event and we
2387          * just need to ignore it.
2388          *
2389          * Refers to:
2390          *
2391          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2392          * operational mode
2393          */
2394         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2395         if ((dwc->revision < DWC3_REVISION_250A) &&
2396                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2397                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2398                                 (next == DWC3_LINK_STATE_RESUME)) {
2399                         dev_vdbg(dwc->dev, "ignoring transition U3 -> Resume\n");
2400                         return;
2401                 }
2402         }
2403
2404         /*
2405          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2406          * on the link partner, the USB session might do multiple entry/exit
2407          * of low power states before a transfer takes place.
2408          *
2409          * Due to this problem, we might experience lower throughput. The
2410          * suggested workaround is to disable DCTL[12:9] bits if we're
2411          * transitioning from U1/U2 to U0 and enable those bits again
2412          * after a transfer completes and there are no pending transfers
2413          * on any of the enabled endpoints.
2414          *
2415          * This is the first half of that workaround.
2416          *
2417          * Refers to:
2418          *
2419          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2420          * core send LGO_Ux entering U0
2421          */
2422         if (dwc->revision < DWC3_REVISION_183A) {
2423                 if (next == DWC3_LINK_STATE_U0) {
2424                         u32     u1u2;
2425                         u32     reg;
2426
2427                         switch (dwc->link_state) {
2428                         case DWC3_LINK_STATE_U1:
2429                         case DWC3_LINK_STATE_U2:
2430                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2431                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2432                                                 | DWC3_DCTL_ACCEPTU2ENA
2433                                                 | DWC3_DCTL_INITU1ENA
2434                                                 | DWC3_DCTL_ACCEPTU1ENA);
2435
2436                                 if (!dwc->u1u2)
2437                                         dwc->u1u2 = reg & u1u2;
2438
2439                                 reg &= ~u1u2;
2440
2441                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2442                                 break;
2443                         default:
2444                                 /* do nothing */
2445                                 break;
2446                         }
2447                 }
2448         }
2449
2450         dwc->link_state = next;
2451
2452         dev_vdbg(dwc->dev, "%s link %d\n", __func__, dwc->link_state);
2453 }
2454
2455 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2456                 const struct dwc3_event_devt *event)
2457 {
2458         switch (event->type) {
2459         case DWC3_DEVICE_EVENT_DISCONNECT:
2460                 dwc3_gadget_disconnect_interrupt(dwc);
2461                 break;
2462         case DWC3_DEVICE_EVENT_RESET:
2463                 dwc3_gadget_reset_interrupt(dwc);
2464                 break;
2465         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2466                 dwc3_gadget_conndone_interrupt(dwc);
2467                 break;
2468         case DWC3_DEVICE_EVENT_WAKEUP:
2469                 dwc3_gadget_wakeup_interrupt(dwc);
2470                 break;
2471         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2472                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2473                 break;
2474         case DWC3_DEVICE_EVENT_EOPF:
2475                 dev_vdbg(dwc->dev, "End of Periodic Frame\n");
2476                 break;
2477         case DWC3_DEVICE_EVENT_SOF:
2478                 dev_vdbg(dwc->dev, "Start of Periodic Frame\n");
2479                 break;
2480         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2481                 dev_vdbg(dwc->dev, "Erratic Error\n");
2482                 break;
2483         case DWC3_DEVICE_EVENT_CMD_CMPL:
2484                 dev_vdbg(dwc->dev, "Command Complete\n");
2485                 break;
2486         case DWC3_DEVICE_EVENT_OVERFLOW:
2487                 dev_vdbg(dwc->dev, "Overflow\n");
2488                 break;
2489         default:
2490                 dev_dbg(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2491         }
2492 }
2493
2494 static void dwc3_process_event_entry(struct dwc3 *dwc,
2495                 const union dwc3_event *event)
2496 {
2497         /* Endpoint IRQ, handle it and return early */
2498         if (event->type.is_devspec == 0) {
2499                 /* depevt */
2500                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2501         }
2502
2503         switch (event->type.type) {
2504         case DWC3_EVENT_TYPE_DEV:
2505                 dwc3_gadget_interrupt(dwc, &event->devt);
2506                 break;
2507         /* REVISIT what to do with Carkit and I2C events ? */
2508         default:
2509                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2510         }
2511 }
2512
2513 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2514 {
2515         struct dwc3 *dwc = _dwc;
2516         unsigned long flags;
2517         irqreturn_t ret = IRQ_NONE;
2518         int i;
2519
2520         spin_lock_irqsave(&dwc->lock, flags);
2521
2522         for (i = 0; i < dwc->num_event_buffers; i++) {
2523                 struct dwc3_event_buffer *evt;
2524                 int                     left;
2525
2526                 evt = dwc->ev_buffs[i];
2527                 left = evt->count;
2528
2529                 if (!(evt->flags & DWC3_EVENT_PENDING))
2530                         continue;
2531
2532                 while (left > 0) {
2533                         union dwc3_event event;
2534
2535                         event.raw = *(u32 *) (evt->buf + evt->lpos);
2536
2537                         dwc3_process_event_entry(dwc, &event);
2538
2539                         /*
2540                          * FIXME we wrap around correctly to the next entry as
2541                          * almost all entries are 4 bytes in size. There is one
2542                          * entry which has 12 bytes which is a regular entry
2543                          * followed by 8 bytes data. ATM I don't know how
2544                          * things are organized if we get next to the a
2545                          * boundary so I worry about that once we try to handle
2546                          * that.
2547                          */
2548                         evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2549                         left -= 4;
2550
2551                         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), 4);
2552                 }
2553
2554                 evt->count = 0;
2555                 evt->flags &= ~DWC3_EVENT_PENDING;
2556                 ret = IRQ_HANDLED;
2557         }
2558
2559         spin_unlock_irqrestore(&dwc->lock, flags);
2560
2561         return ret;
2562 }
2563
2564 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2565 {
2566         struct dwc3_event_buffer *evt;
2567         u32 count;
2568
2569         evt = dwc->ev_buffs[buf];
2570
2571         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2572         count &= DWC3_GEVNTCOUNT_MASK;
2573         if (!count)
2574                 return IRQ_NONE;
2575
2576         evt->count = count;
2577         evt->flags |= DWC3_EVENT_PENDING;
2578
2579         return IRQ_WAKE_THREAD;
2580 }
2581
2582 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2583 {
2584         struct dwc3                     *dwc = _dwc;
2585         int                             i;
2586         irqreturn_t                     ret = IRQ_NONE;
2587
2588         spin_lock(&dwc->lock);
2589
2590         for (i = 0; i < dwc->num_event_buffers; i++) {
2591                 irqreturn_t status;
2592
2593                 status = dwc3_process_event_buf(dwc, i);
2594                 if (status == IRQ_WAKE_THREAD)
2595                         ret = status;
2596         }
2597
2598         spin_unlock(&dwc->lock);
2599
2600         return ret;
2601 }
2602
2603 /**
2604  * dwc3_gadget_init - Initializes gadget related registers
2605  * @dwc: pointer to our controller context structure
2606  *
2607  * Returns 0 on success otherwise negative errno.
2608  */
2609 int dwc3_gadget_init(struct dwc3 *dwc)
2610 {
2611         u32                                     reg;
2612         int                                     ret;
2613
2614         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2615                         &dwc->ctrl_req_addr, GFP_KERNEL);
2616         if (!dwc->ctrl_req) {
2617                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2618                 ret = -ENOMEM;
2619                 goto err0;
2620         }
2621
2622         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2623                         &dwc->ep0_trb_addr, GFP_KERNEL);
2624         if (!dwc->ep0_trb) {
2625                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2626                 ret = -ENOMEM;
2627                 goto err1;
2628         }
2629
2630         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2631         if (!dwc->setup_buf) {
2632                 dev_err(dwc->dev, "failed to allocate setup buffer\n");
2633                 ret = -ENOMEM;
2634                 goto err2;
2635         }
2636
2637         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2638                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2639                         GFP_KERNEL);
2640         if (!dwc->ep0_bounce) {
2641                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2642                 ret = -ENOMEM;
2643                 goto err3;
2644         }
2645
2646         dwc->gadget.ops                 = &dwc3_gadget_ops;
2647         dwc->gadget.max_speed           = USB_SPEED_SUPER;
2648         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2649         dwc->gadget.sg_supported        = true;
2650         dwc->gadget.name                = "dwc3-gadget";
2651
2652         /*
2653          * REVISIT: Here we should clear all pending IRQs to be
2654          * sure we're starting from a well known location.
2655          */
2656
2657         ret = dwc3_gadget_init_endpoints(dwc);
2658         if (ret)
2659                 goto err4;
2660
2661         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2662         reg |= DWC3_DCFG_LPM_CAP;
2663         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2664
2665         /* Enable USB2 LPM and automatic phy suspend only on recent versions */
2666         if (dwc->revision >= DWC3_REVISION_194A) {
2667                 dwc3_gadget_usb2_phy_suspend(dwc, false);
2668                 dwc3_gadget_usb3_phy_suspend(dwc, false);
2669         }
2670
2671         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2672         if (ret) {
2673                 dev_err(dwc->dev, "failed to register udc\n");
2674                 goto err5;
2675         }
2676
2677         return 0;
2678
2679 err5:
2680         dwc3_gadget_free_endpoints(dwc);
2681
2682 err4:
2683         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2684                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2685
2686 err3:
2687         kfree(dwc->setup_buf);
2688
2689 err2:
2690         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2691                         dwc->ep0_trb, dwc->ep0_trb_addr);
2692
2693 err1:
2694         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2695                         dwc->ctrl_req, dwc->ctrl_req_addr);
2696
2697 err0:
2698         return ret;
2699 }
2700
2701 /* -------------------------------------------------------------------------- */
2702
2703 void dwc3_gadget_exit(struct dwc3 *dwc)
2704 {
2705         usb_del_gadget_udc(&dwc->gadget);
2706
2707         dwc3_gadget_free_endpoints(dwc);
2708
2709         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2710                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2711
2712         kfree(dwc->setup_buf);
2713
2714         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2715                         dwc->ep0_trb, dwc->ep0_trb_addr);
2716
2717         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2718                         dwc->ctrl_req, dwc->ctrl_req_addr);
2719 }
2720
2721 int dwc3_gadget_prepare(struct dwc3 *dwc)
2722 {
2723         if (dwc->pullups_connected)
2724                 dwc3_gadget_disable_irq(dwc);
2725
2726         return 0;
2727 }
2728
2729 void dwc3_gadget_complete(struct dwc3 *dwc)
2730 {
2731         if (dwc->pullups_connected) {
2732                 dwc3_gadget_enable_irq(dwc);
2733                 dwc3_gadget_run_stop(dwc, true);
2734         }
2735 }
2736
2737 int dwc3_gadget_suspend(struct dwc3 *dwc)
2738 {
2739         __dwc3_gadget_ep_disable(dwc->eps[0]);
2740         __dwc3_gadget_ep_disable(dwc->eps[1]);
2741
2742         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2743
2744         return 0;
2745 }
2746
2747 int dwc3_gadget_resume(struct dwc3 *dwc)
2748 {
2749         struct dwc3_ep          *dep;
2750         int                     ret;
2751
2752         /* Start with SuperSpeed Default */
2753         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2754
2755         dep = dwc->eps[0];
2756         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2757         if (ret)
2758                 goto err0;
2759
2760         dep = dwc->eps[1];
2761         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false);
2762         if (ret)
2763                 goto err1;
2764
2765         /* begin to receive SETUP packets */
2766         dwc->ep0state = EP0_SETUP_PHASE;
2767         dwc3_ep0_out_start(dwc);
2768
2769         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2770
2771         return 0;
2772
2773 err1:
2774         __dwc3_gadget_ep_disable(dwc->eps[0]);
2775
2776 err0:
2777         return ret;
2778 }