drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_ep_inc_trb() - Increment a TRB index.
 150  * @index - Pointer to the TRB index to increment.
 151  *
 152  * The index should never point to the link TRB. After incrementing,
 153  * if it is point to the link TRB, wrap around to the beginning. The
 154  * link TRB is always at the last TRB entry.
 155  */
 156 static void dwc3_ep_inc_trb(u8 *index)
 157 {
 158         (*index)++;
 159         if (*index == (DWC3_TRB_NUM - 1))
 160                 *index = 0;
 161 }
 162
 163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 164 {
 165         dwc3_ep_inc_trb(&dep->trb_enqueue);
 166 }
 167
 168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 169 {
 170         dwc3_ep_inc_trb(&dep->trb_dequeue);
 171 }
 172
 173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 174                 int status)
 175 {
 176         struct dwc3                     *dwc = dep->dwc;
 177         int                             i;
 178
 179         if (req->started) {
 180                 i = 0;
 181                 do {
 182                         dwc3_ep_inc_deq(dep);
 183                 } while(++i < req->request.num_mapped_sgs);
 184                 req->started = false;
 185         }
 186         list_del(&req->list);
 187         req->trb = NULL;
 188
 189         if (req->request.status == -EINPROGRESS)
 190                 req->request.status = status;
 191
 192         if (dwc->ep0_bounced && dep->number == 0)
 193                 dwc->ep0_bounced = false;
 194         else
 195                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 196                                 req->direction);
 197
 198         trace_dwc3_gadget_giveback(req);
 199
 200         spin_unlock(&dwc->lock);
 201         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 202         spin_lock(&dwc->lock);
 203
 204         if (dep->number > 1)
 205                 pm_runtime_put(dwc->dev);
 206 }
 207
 208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 209 {
 210         u32             timeout = 500;
 211         int             status = 0;
 212         int             ret = 0;
 213         u32             reg;
 214
 215         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 216         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 217
 218         do {
 219                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 220                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 221                         status = DWC3_DGCMD_STATUS(reg);
 222                         if (status)
 223                                 ret = -EINVAL;
 224                         break;
 225                 }
 226         } while (timeout--);
 227
 228         if (!timeout) {
 229                 ret = -ETIMEDOUT;
 230                 status = -ETIMEDOUT;
 231         }
 232
 233         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 234
 235         return ret;
 236 }
 237
 238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 239
 240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 241                 struct dwc3_gadget_ep_cmd_params *params)
 242 {
 243         struct dwc3             *dwc = dep->dwc;
 244         u32                     timeout = 500;
 245         u32                     reg;
 246
 247         int                     cmd_status = 0;
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         /*
 252          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 253          * we're issuing an endpoint command, we must check if
 254          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 255          *
 256          * We will also set SUSPHY bit to what it was before returning as stated
 257          * by the same section on Synopsys databook.
 258          */
 259         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 260                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 261                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 262                         susphy = true;
 263                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 264                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 265                 }
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 283         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 285
 286         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         switch (cmd_status) {
 293                         case 0:
 294                                 ret = 0;
 295                                 break;
 296                         case DEPEVT_TRANSFER_NO_RESOURCE:
 297                                 ret = -EINVAL;
 298                                 break;
 299                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 300                                 /*
 301                                  * SW issues START TRANSFER command to
 302                                  * isochronous ep with future frame interval. If
 303                                  * future interval time has already passed when
 304                                  * core receives the command, it will respond
 305                                  * with an error status of 'Bus Expiry'.
 306                                  *
 307                                  * Instead of always returning -EINVAL, let's
 308                                  * give a hint to the gadget driver that this is
 309                                  * the case by returning -EAGAIN.
 310                                  */
 311                                 ret = -EAGAIN;
 312                                 break;
 313                         default:
 314                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 315                         }
 316
 317                         break;
 318                 }
 319         } while (--timeout);
 320
 321         if (timeout == 0) {
 322                 ret = -ETIMEDOUT;
 323                 cmd_status = -ETIMEDOUT;
 324         }
 325
 326         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 327
 328         if (unlikely(susphy)) {
 329                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 330                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 331                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 338 {
 339         struct dwc3 *dwc = dep->dwc;
 340         struct dwc3_gadget_ep_cmd_params params;
 341         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 342
 343         /*
 344          * As of core revision 2.60a the recommended programming model
 345          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 346          * command for IN endpoints. This is to prevent an issue where
 347          * some (non-compliant) hosts may not send ACK TPs for pending
 348          * IN transfers due to a mishandled error condition. Synopsys
 349          * STAR 9000614252.
 350          */
 351         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 352                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 353
 354         memset(&params, 0, sizeof(params));
 355
 356         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 357 }
 358
 359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 360                 struct dwc3_trb *trb)
 361 {
 362         u32             offset = (char *) trb - (char *) dep->trb_pool;
 363
 364         return dep->trb_pool_dma + offset;
 365 }
 366
 367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 368 {
 369         struct dwc3             *dwc = dep->dwc;
 370
 371         if (dep->trb_pool)
 372                 return 0;
 373
 374         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 375                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 376                         &dep->trb_pool_dma, GFP_KERNEL);
 377         if (!dep->trb_pool) {
 378                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 379                                 dep->name);
 380                 return -ENOMEM;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 387 {
 388         struct dwc3             *dwc = dep->dwc;
 389
 390         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         dep->trb_pool, dep->trb_pool_dma);
 392
 393         dep->trb_pool = NULL;
 394         dep->trb_pool_dma = 0;
 395 }
 396
 397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 398
 399 /**
 400  * dwc3_gadget_start_config - Configure EP resources
 401  * @dwc: pointer to our controller context structure
 402  * @dep: endpoint that is being enabled
 403  *
 404  * The assignment of transfer resources cannot perfectly follow the
 405  * data book due to the fact that the controller driver does not have
 406  * all knowledge of the configuration in advance. It is given this
 407  * information piecemeal by the composite gadget framework after every
 408  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 409  * programming model in this scenario can cause errors. For two
 410  * reasons:
 411  *
 412  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 413  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 414  * multiple interfaces.
 415  *
 416  * 2) The databook does not mention doing more DEPXFERCFG for new
 417  * endpoint on alt setting (8.1.6).
 418  *
 419  * The following simplified method is used instead:
 420  *
 421  * All hardware endpoints can be assigned a transfer resource and this
 422  * setting will stay persistent until either a core reset or
 423  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 424  * do DEPXFERCFG for every hardware endpoint as well. We are
 425  * guaranteed that there are as many transfer resources as endpoints.
 426  *
 427  * This function is called for each endpoint when it is being enabled
 428  * but is triggered only when called for EP0-out, which always happens
 429  * first, and which should only happen in one of the above conditions.
 430  */
 431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 432 {
 433         struct dwc3_gadget_ep_cmd_params params;
 434         u32                     cmd;
 435         int                     i;
 436         int                     ret;
 437
 438         if (dep->number)
 439                 return 0;
 440
 441         memset(&params, 0x00, sizeof(params));
 442         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 443
 444         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 445         if (ret)
 446                 return ret;
 447
 448         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 449                 struct dwc3_ep *dep = dwc->eps[i];
 450
 451                 if (!dep)
 452                         continue;
 453
 454                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 463                 const struct usb_endpoint_descriptor *desc,
 464                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 465                 bool ignore, bool restore)
 466 {
 467         struct dwc3_gadget_ep_cmd_params params;
 468
 469         memset(&params, 0x00, sizeof(params));
 470
 471         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 472                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 473
 474         /* Burst size is only needed in SuperSpeed mode */
 475         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 476                 u32 burst = dep->endpoint.maxburst;
 477                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 478         }
 479
 480         if (ignore)
 481                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 482
 483         if (restore) {
 484                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 485                 params.param2 |= dep->saved_state;
 486         }
 487
 488         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 489
 490         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 491                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 492
 493         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 494                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 495                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 496                 dep->stream_capable = true;
 497         }
 498
 499         if (!usb_endpoint_xfer_control(desc))
 500                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 501
 502         /*
 503          * We are doing 1:1 mapping for endpoints, meaning
 504          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 505          * so on. We consider the direction bit as part of the physical
 506          * endpoint number. So USB endpoint 0x81 is 0x03.
 507          */
 508         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 509
 510         /*
 511          * We must use the lower 16 TX FIFOs even though
 512          * HW might have more
 513          */
 514         if (dep->direction)
 515                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 516
 517         if (desc->bInterval) {
 518                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 519                 dep->interval = 1 << (desc->bInterval - 1);
 520         }
 521
 522         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 523 }
 524
 525 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 526 {
 527         struct dwc3_gadget_ep_cmd_params params;
 528
 529         memset(&params, 0x00, sizeof(params));
 530
 531         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 532
 533         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 534                         &params);
 535 }
 536
 537 /**
 538  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 539  * @dep: endpoint to be initialized
 540  * @desc: USB Endpoint Descriptor
 541  *
 542  * Caller should take care of locking
 543  */
 544 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 545                 const struct usb_endpoint_descriptor *desc,
 546                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 547                 bool ignore, bool restore)
 548 {
 549         struct dwc3             *dwc = dep->dwc;
 550         u32                     reg;
 551         int                     ret;
 552
 553         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 554
 555         if (!(dep->flags & DWC3_EP_ENABLED)) {
 556                 ret = dwc3_gadget_start_config(dwc, dep);
 557                 if (ret)
 558                         return ret;
 559         }
 560
 561         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 562                         restore);
 563         if (ret)
 564                 return ret;
 565
 566         if (!(dep->flags & DWC3_EP_ENABLED)) {
 567                 struct dwc3_trb *trb_st_hw;
 568                 struct dwc3_trb *trb_link;
 569
 570                 dep->endpoint.desc = desc;
 571                 dep->comp_desc = comp_desc;
 572                 dep->type = usb_endpoint_type(desc);
 573                 dep->flags |= DWC3_EP_ENABLED;
 574
 575                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 576                 reg |= DWC3_DALEPENA_EP(dep->number);
 577                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 578
 579                 if (usb_endpoint_xfer_control(desc))
 580                         return 0;
 581
 582                 /* Initialize the TRB ring */
 583                 dep->trb_dequeue = 0;
 584                 dep->trb_enqueue = 0;
 585                 memset(dep->trb_pool, 0,
 586                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 587
 588                 /* Link TRB. The HWO bit is never reset */
 589                 trb_st_hw = &dep->trb_pool[0];
 590
 591                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 592                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 593                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 594                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 595                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 602 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 603 {
 604         struct dwc3_request             *req;
 605         struct dwc3_trb                 *current_trb;
 606         unsigned                        transfer_in_flight;
 607
 608         if (dep->number > 1)
 609                 current_trb = &dep->trb_pool[dep->trb_enqueue];
 610         else
 611                 current_trb = &dwc->ep0_trb[dep->trb_enqueue];
 612         transfer_in_flight = current_trb->ctrl & DWC3_TRB_CTRL_HWO;
 613
 614         if (transfer_in_flight && !list_empty(&dep->started_list)) {
 615                 dwc3_stop_active_transfer(dwc, dep->number, true);
 616
 617                 /* - giveback all requests to gadget driver */
 618                 while (!list_empty(&dep->started_list)) {
 619                         req = next_request(&dep->started_list);
 620
 621                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 622                 }
 623         }
 624
 625         while (!list_empty(&dep->pending_list)) {
 626                 req = next_request(&dep->pending_list);
 627
 628                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 629         }
 630 }
 631
 632 /**
 633  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 634  * @dep: the endpoint to disable
 635  *
 636  * This function also removes requests which are currently processed ny the
 637  * hardware and those which are not yet scheduled.
 638  * Caller should take care of locking.
 639  */
 640 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 641 {
 642         struct dwc3             *dwc = dep->dwc;
 643         u32                     reg;
 644
 645         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 646
 647         dwc3_remove_requests(dwc, dep);
 648
 649         /* make sure HW endpoint isn't stalled */
 650         if (dep->flags & DWC3_EP_STALL)
 651                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 652
 653         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 654         reg &= ~DWC3_DALEPENA_EP(dep->number);
 655         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 656
 657         dep->stream_capable = false;
 658         dep->endpoint.desc = NULL;
 659         dep->comp_desc = NULL;
 660         dep->type = 0;
 661         dep->flags = 0;
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         dep->allocated_requests++;
 755
 756         trace_dwc3_alloc_request(req);
 757
 758         return &req->request;
 759 }
 760
 761 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 762                 struct usb_request *request)
 763 {
 764         struct dwc3_request             *req = to_dwc3_request(request);
 765         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 766
 767         dep->allocated_requests--;
 768         trace_dwc3_free_request(req);
 769         kfree(req);
 770 }
 771
 772 /**
 773  * dwc3_prepare_one_trb - setup one TRB from one request
 774  * @dep: endpoint for which this request is prepared
 775  * @req: dwc3_request pointer
 776  */
 777 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 778                 struct dwc3_request *req, dma_addr_t dma,
 779                 unsigned length, unsigned last, unsigned chain, unsigned node)
 780 {
 781         struct dwc3_trb         *trb;
 782
 783         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 784                         dep->name, req, (unsigned long long) dma,
 785                         length, last ? " last" : "",
 786                         chain ? " chain" : "");
 787
 788
 789         trb = &dep->trb_pool[dep->trb_enqueue];
 790
 791         if (!req->trb) {
 792                 dwc3_gadget_move_started_request(req);
 793                 req->trb = trb;
 794                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 795                 req->first_trb_index = dep->trb_enqueue;
 796         }
 797
 798         dwc3_ep_inc_enq(dep);
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814
 815                 /* always enable Interrupt on Missed ISOC */
 816                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 817                 break;
 818
 819         case USB_ENDPOINT_XFER_BULK:
 820         case USB_ENDPOINT_XFER_INT:
 821                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 822                 break;
 823         default:
 824                 /*
 825                  * This is only possible with faulty memory because we
 826                  * checked it already :)
 827                  */
 828                 BUG();
 829         }
 830
 831         /* always enable Continue on Short Packet */
 832         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 833
 834         if (!req->request.no_interrupt && !chain)
 835                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 836
 837         if (last)
 838                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 839
 840         if (chain)
 841                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 842
 843         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 844                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 845
 846         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 847
 848         dep->queued_requests++;
 849
 850         trace_dwc3_prepare_trb(dep, trb);
 851 }
 852
 853 /**
 854  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 855  * @dep: The endpoint with the TRB ring
 856  * @index: The index of the current TRB in the ring
 857  *
 858  * Returns the TRB prior to the one pointed to by the index. If the
 859  * index is 0, we will wrap backwards, skip the link TRB, and return
 860  * the one just before that.
 861  */
 862 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 863 {
 864         if (!index)
 865                 index = DWC3_TRB_NUM - 2;
 866         else
 867                 index = dep->trb_enqueue - 1;
 868
 869         return &dep->trb_pool[index];
 870 }
 871
 872 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 873 {
 874         struct dwc3_trb         *tmp;
 875         u8                      trbs_left;
 876
 877         /*
 878          * If enqueue & dequeue are equal than it is either full or empty.
 879          *
 880          * One way to know for sure is if the TRB right before us has HWO bit
 881          * set or not. If it has, then we're definitely full and can't fit any
 882          * more transfers in our ring.
 883          */
 884         if (dep->trb_enqueue == dep->trb_dequeue) {
 885                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 886                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 887                         return 0;
 888
 889                 return DWC3_TRB_NUM - 1;
 890         }
 891
 892         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 893         trbs_left &= (DWC3_TRB_NUM - 1);
 894
 895         if (dep->trb_dequeue < dep->trb_enqueue)
 896                 trbs_left--;
 897
 898         return trbs_left;
 899 }
 900
 901 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 902                 struct dwc3_request *req, unsigned int trbs_left,
 903                 unsigned int more_coming)
 904 {
 905         struct usb_request *request = &req->request;
 906         struct scatterlist *sg = request->sg;
 907         struct scatterlist *s;
 908         unsigned int    last = false;
 909         unsigned int    length;
 910         dma_addr_t      dma;
 911         int             i;
 912
 913         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 914                 unsigned chain = true;
 915
 916                 length = sg_dma_len(s);
 917                 dma = sg_dma_address(s);
 918
 919                 if (sg_is_last(s)) {
 920                         if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
 921                                 !more_coming)
 922                                 last = true;
 923
 924                         chain = false;
 925                 }
 926
 927                 if (!trbs_left)
 928                         last = true;
 929
 930                 if (last)
 931                         chain = false;
 932
 933                 dwc3_prepare_one_trb(dep, req, dma, length,
 934                                 last, chain, i);
 935
 936                 if (last)
 937                         break;
 938         }
 939 }
 940
 941 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 942                 struct dwc3_request *req, unsigned int trbs_left,
 943                 unsigned int more_coming)
 944 {
 945         unsigned int    last = false;
 946         unsigned int    length;
 947         dma_addr_t      dma;
 948
 949         dma = req->request.dma;
 950         length = req->request.length;
 951
 952         if (!trbs_left)
 953                 last = true;
 954
 955         /* Is this the last request? */
 956         if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
 957                 last = true;
 958
 959         dwc3_prepare_one_trb(dep, req, dma, length,
 960                         last, false, 0);
 961 }
 962
 963 /*
 964  * dwc3_prepare_trbs - setup TRBs from requests
 965  * @dep: endpoint for which requests are being prepared
 966  *
 967  * The function goes through the requests list and sets up TRBs for the
 968  * transfers. The function returns once there are no more TRBs available or
 969  * it runs out of requests.
 970  */
 971 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 972 {
 973         struct dwc3_request     *req, *n;
 974         unsigned int            more_coming;
 975         u32                     trbs_left;
 976
 977         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 978
 979         trbs_left = dwc3_calc_trbs_left(dep);
 980         if (!trbs_left)
 981                 return;
 982
 983         more_coming = dep->allocated_requests - dep->queued_requests;
 984
 985         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 986                 if (req->request.num_mapped_sgs > 0)
 987                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
 988                                         more_coming);
 989                 else
 990                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
 991                                         more_coming);
 992
 993                 if (!trbs_left)
 994                         return;
 995         }
 996 }
 997
 998 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 999 {
1000         struct dwc3_gadget_ep_cmd_params params;
1001         struct dwc3_request             *req;
1002         struct dwc3                     *dwc = dep->dwc;
1003         int                             starting;
1004         int                             ret;
1005         u32                             cmd;
1006
1007         starting = !(dep->flags & DWC3_EP_BUSY);
1008
1009         dwc3_prepare_trbs(dep);
1010         req = next_request(&dep->started_list);
1011         if (!req) {
1012                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1013                 return 0;
1014         }
1015
1016         memset(&params, 0, sizeof(params));
1017
1018         if (starting) {
1019                 params.param0 = upper_32_bits(req->trb_dma);
1020                 params.param1 = lower_32_bits(req->trb_dma);
1021                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1022                         DWC3_DEPCMD_PARAM(cmd_param);
1023         } else {
1024                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1025                         DWC3_DEPCMD_PARAM(dep->resource_index);
1026         }
1027
1028         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1029         if (ret < 0) {
1030                 /*
1031                  * FIXME we need to iterate over the list of requests
1032                  * here and stop, unmap, free and del each of the linked
1033                  * requests instead of what we do now.
1034                  */
1035                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1036                                 req->direction);
1037                 list_del(&req->list);
1038                 return ret;
1039         }
1040
1041         dep->flags |= DWC3_EP_BUSY;
1042
1043         if (starting) {
1044                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1045                 WARN_ON_ONCE(!dep->resource_index);
1046         }
1047
1048         return 0;
1049 }
1050
1051 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1052                 struct dwc3_ep *dep, u32 cur_uf)
1053 {
1054         u32 uf;
1055
1056         if (list_empty(&dep->pending_list)) {
1057                 dwc3_trace(trace_dwc3_gadget,
1058                                 "ISOC ep %s run out for requests",
1059                                 dep->name);
1060                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1061                 return;
1062         }
1063
1064         /* 4 micro frames in the future */
1065         uf = cur_uf + dep->interval * 4;
1066
1067         __dwc3_gadget_kick_transfer(dep, uf);
1068 }
1069
1070 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1071                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1072 {
1073         u32 cur_uf, mask;
1074
1075         mask = ~(dep->interval - 1);
1076         cur_uf = event->parameters & mask;
1077
1078         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1079 }
1080
1081 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1082 {
1083         struct dwc3             *dwc = dep->dwc;
1084         int                     ret;
1085
1086         if (!dep->endpoint.desc) {
1087                 dwc3_trace(trace_dwc3_gadget,
1088                                 "trying to queue request %p to disabled %s",
1089                                 &req->request, dep->endpoint.name);
1090                 return -ESHUTDOWN;
1091         }
1092
1093         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1094                                 &req->request, req->dep->name)) {
1095                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1096                                 &req->request, req->dep->name);
1097                 return -EINVAL;
1098         }
1099
1100         pm_runtime_get(dwc->dev);
1101
1102         req->request.actual     = 0;
1103         req->request.status     = -EINPROGRESS;
1104         req->direction          = dep->direction;
1105         req->epnum              = dep->number;
1106
1107         trace_dwc3_ep_queue(req);
1108
1109         /*
1110          * Per databook, the total size of buffer must be a multiple
1111          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1112          * configed for endpoints in dwc3_gadget_set_ep_config(),
1113          * set to usb_endpoint_descriptor->wMaxPacketSize.
1114          */
1115         if (dep->direction == 0 &&
1116             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1117                 req->request.length = roundup(req->request.length,
1118                                         dep->endpoint.desc->wMaxPacketSize);
1119
1120         /*
1121          * We only add to our list of requests now and
1122          * start consuming the list once we get XferNotReady
1123          * IRQ.
1124          *
1125          * That way, we avoid doing anything that we don't need
1126          * to do now and defer it until the point we receive a
1127          * particular token from the Host side.
1128          *
1129          * This will also avoid Host cancelling URBs due to too
1130          * many NAKs.
1131          */
1132         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1133                         dep->direction);
1134         if (ret)
1135                 return ret;
1136
1137         list_add_tail(&req->list, &dep->pending_list);
1138
1139         /*
1140          * If there are no pending requests and the endpoint isn't already
1141          * busy, we will just start the request straight away.
1142          *
1143          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1144          * little bit faster.
1145          */
1146         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1147                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1148                         !(dep->flags & DWC3_EP_BUSY)) {
1149                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1150                 goto out;
1151         }
1152
1153         /*
1154          * There are a few special cases:
1155          *
1156          * 1. XferNotReady with empty list of requests. We need to kick the
1157          *    transfer here in that situation, otherwise we will be NAKing
1158          *    forever. If we get XferNotReady before gadget driver has a
1159          *    chance to queue a request, we will ACK the IRQ but won't be
1160          *    able to receive the data until the next request is queued.
1161          *    The following code is handling exactly that.
1162          *
1163          */
1164         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1165                 /*
1166                  * If xfernotready is already elapsed and it is a case
1167                  * of isoc transfer, then issue END TRANSFER, so that
1168                  * you can receive xfernotready again and can have
1169                  * notion of current microframe.
1170                  */
1171                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1172                         if (list_empty(&dep->started_list)) {
1173                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1174                                 dep->flags = DWC3_EP_ENABLED;
1175                         }
1176                         return 0;
1177                 }
1178
1179                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1180                 if (!ret)
1181                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1182
1183                 goto out;
1184         }
1185
1186         /*
1187          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1188          *    kick the transfer here after queuing a request, otherwise the
1189          *    core may not see the modified TRB(s).
1190          */
1191         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1192                         (dep->flags & DWC3_EP_BUSY) &&
1193                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1194                 WARN_ON_ONCE(!dep->resource_index);
1195                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1196                 goto out;
1197         }
1198
1199         /*
1200          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1201          * right away, otherwise host will not know we have streams to be
1202          * handled.
1203          */
1204         if (dep->stream_capable)
1205                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1206
1207 out:
1208         if (ret && ret != -EBUSY)
1209                 dwc3_trace(trace_dwc3_gadget,
1210                                 "%s: failed to kick transfers",
1211                                 dep->name);
1212         if (ret == -EBUSY)
1213                 ret = 0;
1214
1215         return ret;
1216 }
1217
1218 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1219                 struct usb_request *request)
1220 {
1221         dwc3_gadget_ep_free_request(ep, request);
1222 }
1223
1224 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1225 {
1226         struct dwc3_request             *req;
1227         struct usb_request              *request;
1228         struct usb_ep                   *ep = &dep->endpoint;
1229
1230         dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1231         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1232         if (!request)
1233                 return -ENOMEM;
1234
1235         request->length = 0;
1236         request->buf = dwc->zlp_buf;
1237         request->complete = __dwc3_gadget_ep_zlp_complete;
1238
1239         req = to_dwc3_request(request);
1240
1241         return __dwc3_gadget_ep_queue(dep, req);
1242 }
1243
1244 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1245         gfp_t gfp_flags)
1246 {
1247         struct dwc3_request             *req = to_dwc3_request(request);
1248         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1249         struct dwc3                     *dwc = dep->dwc;
1250
1251         unsigned long                   flags;
1252
1253         int                             ret;
1254
1255         spin_lock_irqsave(&dwc->lock, flags);
1256         ret = __dwc3_gadget_ep_queue(dep, req);
1257
1258         /*
1259          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1260          * setting request->zero, instead of doing magic, we will just queue an
1261          * extra usb_request ourselves so that it gets handled the same way as
1262          * any other request.
1263          */
1264         if (ret == 0 && request->zero && request->length &&
1265             (request->length % ep->desc->wMaxPacketSize == 0))
1266                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1267
1268         spin_unlock_irqrestore(&dwc->lock, flags);
1269
1270         return ret;
1271 }
1272
1273 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1274                 struct usb_request *request)
1275 {
1276         struct dwc3_request             *req = to_dwc3_request(request);
1277         struct dwc3_request             *r = NULL;
1278
1279         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1280         struct dwc3                     *dwc = dep->dwc;
1281
1282         unsigned long                   flags;
1283         int                             ret = 0;
1284
1285         trace_dwc3_ep_dequeue(req);
1286
1287         spin_lock_irqsave(&dwc->lock, flags);
1288
1289         list_for_each_entry(r, &dep->pending_list, list) {
1290                 if (r == req)
1291                         break;
1292         }
1293
1294         if (r != req) {
1295                 list_for_each_entry(r, &dep->started_list, list) {
1296                         if (r == req)
1297                                 break;
1298                 }
1299                 if (r == req) {
1300                         /* wait until it is processed */
1301                         dwc3_stop_active_transfer(dwc, dep->number, true);
1302                         goto out1;
1303                 }
1304                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1305                                 request, ep->name);
1306                 ret = -EINVAL;
1307                 goto out0;
1308         }
1309
1310 out1:
1311         /* giveback the request */
1312         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1313
1314 out0:
1315         spin_unlock_irqrestore(&dwc->lock, flags);
1316
1317         return ret;
1318 }
1319
1320 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1321 {
1322         struct dwc3_gadget_ep_cmd_params        params;
1323         struct dwc3                             *dwc = dep->dwc;
1324         int                                     ret;
1325
1326         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1327                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1328                 return -EINVAL;
1329         }
1330
1331         memset(&params, 0x00, sizeof(params));
1332
1333         if (value) {
1334                 struct dwc3_trb *trb;
1335
1336                 unsigned transfer_in_flight;
1337                 unsigned started;
1338
1339                 if (dep->number > 1)
1340                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1341                 else
1342                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1343
1344                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1345                 started = !list_empty(&dep->started_list);
1346
1347                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1348                                 (!dep->direction && started))) {
1349                         dwc3_trace(trace_dwc3_gadget,
1350                                         "%s: pending request, cannot halt",
1351                                         dep->name);
1352                         return -EAGAIN;
1353                 }
1354
1355                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1356                                 &params);
1357                 if (ret)
1358                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1359                                         dep->name);
1360                 else
1361                         dep->flags |= DWC3_EP_STALL;
1362         } else {
1363
1364                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1365                 if (ret)
1366                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1367                                         dep->name);
1368                 else
1369                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1370         }
1371
1372         return ret;
1373 }
1374
1375 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1376 {
1377         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1378         struct dwc3                     *dwc = dep->dwc;
1379
1380         unsigned long                   flags;
1381
1382         int                             ret;
1383
1384         spin_lock_irqsave(&dwc->lock, flags);
1385         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1386         spin_unlock_irqrestore(&dwc->lock, flags);
1387
1388         return ret;
1389 }
1390
1391 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1392 {
1393         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1394         struct dwc3                     *dwc = dep->dwc;
1395         unsigned long                   flags;
1396         int                             ret;
1397
1398         spin_lock_irqsave(&dwc->lock, flags);
1399         dep->flags |= DWC3_EP_WEDGE;
1400
1401         if (dep->number == 0 || dep->number == 1)
1402                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1403         else
1404                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1405         spin_unlock_irqrestore(&dwc->lock, flags);
1406
1407         return ret;
1408 }
1409
1410 /* -------------------------------------------------------------------------- */
1411
1412 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1413         .bLength        = USB_DT_ENDPOINT_SIZE,
1414         .bDescriptorType = USB_DT_ENDPOINT,
1415         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1416 };
1417
1418 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1419         .enable         = dwc3_gadget_ep0_enable,
1420         .disable        = dwc3_gadget_ep0_disable,
1421         .alloc_request  = dwc3_gadget_ep_alloc_request,
1422         .free_request   = dwc3_gadget_ep_free_request,
1423         .queue          = dwc3_gadget_ep0_queue,
1424         .dequeue        = dwc3_gadget_ep_dequeue,
1425         .set_halt       = dwc3_gadget_ep0_set_halt,
1426         .set_wedge      = dwc3_gadget_ep_set_wedge,
1427 };
1428
1429 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1430         .enable         = dwc3_gadget_ep_enable,
1431         .disable        = dwc3_gadget_ep_disable,
1432         .alloc_request  = dwc3_gadget_ep_alloc_request,
1433         .free_request   = dwc3_gadget_ep_free_request,
1434         .queue          = dwc3_gadget_ep_queue,
1435         .dequeue        = dwc3_gadget_ep_dequeue,
1436         .set_halt       = dwc3_gadget_ep_set_halt,
1437         .set_wedge      = dwc3_gadget_ep_set_wedge,
1438 };
1439
1440 /* -------------------------------------------------------------------------- */
1441
1442 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1443 {
1444         struct dwc3             *dwc = gadget_to_dwc(g);
1445         u32                     reg;
1446
1447         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1448         return DWC3_DSTS_SOFFN(reg);
1449 }
1450
1451 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1452 {
1453         unsigned long           timeout;
1454
1455         int                     ret;
1456         u32                     reg;
1457
1458         u8                      link_state;
1459         u8                      speed;
1460
1461         /*
1462          * According to the Databook Remote wakeup request should
1463          * be issued only when the device is in early suspend state.
1464          *
1465          * We can check that via USB Link State bits in DSTS register.
1466          */
1467         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1468
1469         speed = reg & DWC3_DSTS_CONNECTSPD;
1470         if (speed == DWC3_DSTS_SUPERSPEED) {
1471                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1472                 return 0;
1473         }
1474
1475         link_state = DWC3_DSTS_USBLNKST(reg);
1476
1477         switch (link_state) {
1478         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1479         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1480                 break;
1481         default:
1482                 dwc3_trace(trace_dwc3_gadget,
1483                                 "can't wakeup from '%s'",
1484                                 dwc3_gadget_link_string(link_state));
1485                 return -EINVAL;
1486         }
1487
1488         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1489         if (ret < 0) {
1490                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1491                 return ret;
1492         }
1493
1494         /* Recent versions do this automatically */
1495         if (dwc->revision < DWC3_REVISION_194A) {
1496                 /* write zeroes to Link Change Request */
1497                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1498                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1499                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1500         }
1501
1502         /* poll until Link State changes to ON */
1503         timeout = jiffies + msecs_to_jiffies(100);
1504
1505         while (!time_after(jiffies, timeout)) {
1506                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1507
1508                 /* in HS, means ON */
1509                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1510                         break;
1511         }
1512
1513         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1514                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1515                 return -EINVAL;
1516         }
1517
1518         return 0;
1519 }
1520
1521 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1522 {
1523         struct dwc3             *dwc = gadget_to_dwc(g);
1524         unsigned long           flags;
1525         int                     ret;
1526
1527         spin_lock_irqsave(&dwc->lock, flags);
1528         ret = __dwc3_gadget_wakeup(dwc);
1529         spin_unlock_irqrestore(&dwc->lock, flags);
1530
1531         return ret;
1532 }
1533
1534 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1535                 int is_selfpowered)
1536 {
1537         struct dwc3             *dwc = gadget_to_dwc(g);
1538         unsigned long           flags;
1539
1540         spin_lock_irqsave(&dwc->lock, flags);
1541         g->is_selfpowered = !!is_selfpowered;
1542         spin_unlock_irqrestore(&dwc->lock, flags);
1543
1544         return 0;
1545 }
1546
1547 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1548 {
1549         u32                     reg;
1550         u32                     timeout = 500;
1551
1552         if (pm_runtime_suspended(dwc->dev))
1553                 return 0;
1554
1555         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1556         if (is_on) {
1557                 if (dwc->revision <= DWC3_REVISION_187A) {
1558                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1559                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1560                 }
1561
1562                 if (dwc->revision >= DWC3_REVISION_194A)
1563                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1564                 reg |= DWC3_DCTL_RUN_STOP;
1565
1566                 if (dwc->has_hibernation)
1567                         reg |= DWC3_DCTL_KEEP_CONNECT;
1568
1569                 dwc->pullups_connected = true;
1570         } else {
1571                 reg &= ~DWC3_DCTL_RUN_STOP;
1572
1573                 if (dwc->has_hibernation && !suspend)
1574                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1575
1576                 dwc->pullups_connected = false;
1577         }
1578
1579         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1580
1581         do {
1582                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1583                 if (is_on) {
1584                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1585                                 break;
1586                 } else {
1587                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1588                                 break;
1589                 }
1590                 timeout--;
1591                 if (!timeout)
1592                         return -ETIMEDOUT;
1593                 udelay(1);
1594         } while (1);
1595
1596         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1597                         dwc->gadget_driver
1598                         ? dwc->gadget_driver->function : "no-function",
1599                         is_on ? "connect" : "disconnect");
1600
1601         return 0;
1602 }
1603
1604 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1605 {
1606         struct dwc3             *dwc = gadget_to_dwc(g);
1607         unsigned long           flags;
1608         int                     ret;
1609
1610         is_on = !!is_on;
1611
1612         spin_lock_irqsave(&dwc->lock, flags);
1613         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1614         spin_unlock_irqrestore(&dwc->lock, flags);
1615
1616         return ret;
1617 }
1618
1619 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1620 {
1621         u32                     reg;
1622
1623         /* Enable all but Start and End of Frame IRQs */
1624         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1625                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1626                         DWC3_DEVTEN_CMDCMPLTEN |
1627                         DWC3_DEVTEN_ERRTICERREN |
1628                         DWC3_DEVTEN_WKUPEVTEN |
1629                         DWC3_DEVTEN_ULSTCNGEN |
1630                         DWC3_DEVTEN_CONNECTDONEEN |
1631                         DWC3_DEVTEN_USBRSTEN |
1632                         DWC3_DEVTEN_DISCONNEVTEN);
1633
1634         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1635 }
1636
1637 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1638 {
1639         /* mask all interrupts */
1640         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1641 }
1642
1643 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1644 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1645
1646 /**
1647  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1648  * dwc: pointer to our context structure
1649  *
1650  * The following looks like complex but it's actually very simple. In order to
1651  * calculate the number of packets we can burst at once on OUT transfers, we're
1652  * gonna use RxFIFO size.
1653  *
1654  * To calculate RxFIFO size we need two numbers:
1655  * MDWIDTH = size, in bits, of the internal memory bus
1656  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1657  *
1658  * Given these two numbers, the formula is simple:
1659  *
1660  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1661  *
1662  * 24 bytes is for 3x SETUP packets
1663  * 16 bytes is a clock domain crossing tolerance
1664  *
1665  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1666  */
1667 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1668 {
1669         u32 ram2_depth;
1670         u32 mdwidth;
1671         u32 nump;
1672         u32 reg;
1673
1674         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1675         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1676
1677         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1678         nump = min_t(u32, nump, 16);
1679
1680         /* update NumP */
1681         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1682         reg &= ~DWC3_DCFG_NUMP_MASK;
1683         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1684         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1685 }
1686
1687 static int __dwc3_gadget_start(struct dwc3 *dwc)
1688 {
1689         struct dwc3_ep          *dep;
1690         int                     ret = 0;
1691         u32                     reg;
1692
1693         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1694         reg &= ~(DWC3_DCFG_SPEED_MASK);
1695
1696         /**
1697          * WORKAROUND: DWC3 revision < 2.20a have an issue
1698          * which would cause metastability state on Run/Stop
1699          * bit if we try to force the IP to USB2-only mode.
1700          *
1701          * Because of that, we cannot configure the IP to any
1702          * speed other than the SuperSpeed
1703          *
1704          * Refers to:
1705          *
1706          * STAR#9000525659: Clock Domain Crossing on DCTL in
1707          * USB 2.0 Mode
1708          */
1709         if (dwc->revision < DWC3_REVISION_220A) {
1710                 reg |= DWC3_DCFG_SUPERSPEED;
1711         } else {
1712                 switch (dwc->maximum_speed) {
1713                 case USB_SPEED_LOW:
1714                         reg |= DWC3_DCFG_LOWSPEED;
1715                         break;
1716                 case USB_SPEED_FULL:
1717                         reg |= DWC3_DCFG_FULLSPEED1;
1718                         break;
1719                 case USB_SPEED_HIGH:
1720                         reg |= DWC3_DCFG_HIGHSPEED;
1721                         break;
1722                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1723                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1724                 default:
1725                         reg |= DWC3_DCFG_SUPERSPEED;
1726                 }
1727         }
1728         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1729
1730         /*
1731          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1732          * field instead of letting dwc3 itself calculate that automatically.
1733          *
1734          * This way, we maximize the chances that we'll be able to get several
1735          * bursts of data without going through any sort of endpoint throttling.
1736          */
1737         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1738         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1739         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1740
1741         dwc3_gadget_setup_nump(dwc);
1742
1743         /* Start with SuperSpeed Default */
1744         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1745
1746         dep = dwc->eps[0];
1747         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1748                         false);
1749         if (ret) {
1750                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1751                 goto err0;
1752         }
1753
1754         dep = dwc->eps[1];
1755         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1756                         false);
1757         if (ret) {
1758                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1759                 goto err1;
1760         }
1761
1762         /* begin to receive SETUP packets */
1763         dwc->ep0state = EP0_SETUP_PHASE;
1764         dwc3_ep0_out_start(dwc);
1765
1766         dwc3_gadget_enable_irq(dwc);
1767
1768         return 0;
1769
1770 err1:
1771         __dwc3_gadget_ep_disable(dwc->eps[0]);
1772
1773 err0:
1774         return ret;
1775 }
1776
1777 static int dwc3_gadget_start(struct usb_gadget *g,
1778                 struct usb_gadget_driver *driver)
1779 {
1780         struct dwc3             *dwc = gadget_to_dwc(g);
1781         unsigned long           flags;
1782         int                     ret = 0;
1783         int                     irq;
1784
1785         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1786         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1787                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1788         if (ret) {
1789                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1790                                 irq, ret);
1791                 goto err0;
1792         }
1793         dwc->irq_gadget = irq;
1794
1795         spin_lock_irqsave(&dwc->lock, flags);
1796         if (dwc->gadget_driver) {
1797                 dev_err(dwc->dev, "%s is already bound to %s\n",
1798                                 dwc->gadget.name,
1799                                 dwc->gadget_driver->driver.name);
1800                 ret = -EBUSY;
1801                 goto err1;
1802         }
1803
1804         dwc->gadget_driver      = driver;
1805
1806         if (pm_runtime_active(dwc->dev))
1807                 __dwc3_gadget_start(dwc);
1808
1809         spin_unlock_irqrestore(&dwc->lock, flags);
1810
1811         return 0;
1812
1813 err1:
1814         spin_unlock_irqrestore(&dwc->lock, flags);
1815         free_irq(irq, dwc);
1816
1817 err0:
1818         return ret;
1819 }
1820
1821 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1822 {
1823         dwc3_gadget_disable_irq(dwc);
1824         __dwc3_gadget_ep_disable(dwc->eps[0]);
1825         __dwc3_gadget_ep_disable(dwc->eps[1]);
1826 }
1827
1828 static int dwc3_gadget_stop(struct usb_gadget *g)
1829 {
1830         struct dwc3             *dwc = gadget_to_dwc(g);
1831         unsigned long           flags;
1832
1833         spin_lock_irqsave(&dwc->lock, flags);
1834         __dwc3_gadget_stop(dwc);
1835         dwc->gadget_driver      = NULL;
1836         spin_unlock_irqrestore(&dwc->lock, flags);
1837
1838         free_irq(dwc->irq_gadget, dwc->ev_buf);
1839
1840         return 0;
1841 }
1842
1843 static const struct usb_gadget_ops dwc3_gadget_ops = {
1844         .get_frame              = dwc3_gadget_get_frame,
1845         .wakeup                 = dwc3_gadget_wakeup,
1846         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1847         .pullup                 = dwc3_gadget_pullup,
1848         .udc_start              = dwc3_gadget_start,
1849         .udc_stop               = dwc3_gadget_stop,
1850 };
1851
1852 /* -------------------------------------------------------------------------- */
1853
1854 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1855                 u8 num, u32 direction)
1856 {
1857         struct dwc3_ep                  *dep;
1858         u8                              i;
1859
1860         for (i = 0; i < num; i++) {
1861                 u8 epnum = (i << 1) | (direction ? 1 : 0);
1862
1863                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1864                 if (!dep)
1865                         return -ENOMEM;
1866
1867                 dep->dwc = dwc;
1868                 dep->number = epnum;
1869                 dep->direction = !!direction;
1870                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1871                 dwc->eps[epnum] = dep;
1872
1873                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1874                                 (epnum & 1) ? "in" : "out");
1875
1876                 dep->endpoint.name = dep->name;
1877                 spin_lock_init(&dep->lock);
1878
1879                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1880
1881                 if (epnum == 0 || epnum == 1) {
1882                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1883                         dep->endpoint.maxburst = 1;
1884                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1885                         if (!epnum)
1886                                 dwc->gadget.ep0 = &dep->endpoint;
1887                 } else {
1888                         int             ret;
1889
1890                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1891                         dep->endpoint.max_streams = 15;
1892                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1893                         list_add_tail(&dep->endpoint.ep_list,
1894                                         &dwc->gadget.ep_list);
1895
1896                         ret = dwc3_alloc_trb_pool(dep);
1897                         if (ret)
1898                                 return ret;
1899                 }
1900
1901                 if (epnum == 0 || epnum == 1) {
1902                         dep->endpoint.caps.type_control = true;
1903                 } else {
1904                         dep->endpoint.caps.type_iso = true;
1905                         dep->endpoint.caps.type_bulk = true;
1906                         dep->endpoint.caps.type_int = true;
1907                 }
1908
1909                 dep->endpoint.caps.dir_in = !!direction;
1910                 dep->endpoint.caps.dir_out = !direction;
1911
1912                 INIT_LIST_HEAD(&dep->pending_list);
1913                 INIT_LIST_HEAD(&dep->started_list);
1914         }
1915
1916         return 0;
1917 }
1918
1919 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1920 {
1921         int                             ret;
1922
1923         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1924
1925         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1926         if (ret < 0) {
1927                 dwc3_trace(trace_dwc3_gadget,
1928                                 "failed to allocate OUT endpoints");
1929                 return ret;
1930         }
1931
1932         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1933         if (ret < 0) {
1934                 dwc3_trace(trace_dwc3_gadget,
1935                                 "failed to allocate IN endpoints");
1936                 return ret;
1937         }
1938
1939         return 0;
1940 }
1941
1942 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1943 {
1944         struct dwc3_ep                  *dep;
1945         u8                              epnum;
1946
1947         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1948                 dep = dwc->eps[epnum];
1949                 if (!dep)
1950                         continue;
1951                 /*
1952                  * Physical endpoints 0 and 1 are special; they form the
1953                  * bi-directional USB endpoint 0.
1954                  *
1955                  * For those two physical endpoints, we don't allocate a TRB
1956                  * pool nor do we add them the endpoints list. Due to that, we
1957                  * shouldn't do these two operations otherwise we would end up
1958                  * with all sorts of bugs when removing dwc3.ko.
1959                  */
1960                 if (epnum != 0 && epnum != 1) {
1961                         dwc3_free_trb_pool(dep);
1962                         list_del(&dep->endpoint.ep_list);
1963                 }
1964
1965                 kfree(dep);
1966         }
1967 }
1968
1969 /* -------------------------------------------------------------------------- */
1970
1971 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1972                 struct dwc3_request *req, struct dwc3_trb *trb,
1973                 const struct dwc3_event_depevt *event, int status)
1974 {
1975         unsigned int            count;
1976         unsigned int            s_pkt = 0;
1977         unsigned int            trb_status;
1978
1979         dep->queued_requests--;
1980         trace_dwc3_complete_trb(dep, trb);
1981
1982         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1983                 /*
1984                  * We continue despite the error. There is not much we
1985                  * can do. If we don't clean it up we loop forever. If
1986                  * we skip the TRB then it gets overwritten after a
1987                  * while since we use them in a ring buffer. A BUG()
1988                  * would help. Lets hope that if this occurs, someone
1989                  * fixes the root cause instead of looking away :)
1990                  */
1991                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1992                                 dep->name, trb);
1993         count = trb->size & DWC3_TRB_SIZE_MASK;
1994
1995         if (dep->direction) {
1996                 if (count) {
1997                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1998                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1999                                 dwc3_trace(trace_dwc3_gadget,
2000                                                 "%s: incomplete IN transfer",
2001                                                 dep->name);
2002                                 /*
2003                                  * If missed isoc occurred and there is
2004                                  * no request queued then issue END
2005                                  * TRANSFER, so that core generates
2006                                  * next xfernotready and we will issue
2007                                  * a fresh START TRANSFER.
2008                                  * If there are still queued request
2009                                  * then wait, do not issue either END
2010                                  * or UPDATE TRANSFER, just attach next
2011                                  * request in pending_list during
2012                                  * giveback.If any future queued request
2013                                  * is successfully transferred then we
2014                                  * will issue UPDATE TRANSFER for all
2015                                  * request in the pending_list.
2016                                  */
2017                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2018                         } else {
2019                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2020                                                 dep->name);
2021                                 status = -ECONNRESET;
2022                         }
2023                 } else {
2024                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2025                 }
2026         } else {
2027                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2028                         s_pkt = 1;
2029         }
2030
2031         /*
2032          * We assume here we will always receive the entire data block
2033          * which we should receive. Meaning, if we program RX to
2034          * receive 4K but we receive only 2K, we assume that's all we
2035          * should receive and we simply bounce the request back to the
2036          * gadget driver for further processing.
2037          */
2038         req->request.actual += req->request.length - count;
2039         if (s_pkt)
2040                 return 1;
2041         if ((event->status & DEPEVT_STATUS_LST) &&
2042                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2043                                 DWC3_TRB_CTRL_HWO)))
2044                 return 1;
2045         if ((event->status & DEPEVT_STATUS_IOC) &&
2046                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2047                 return 1;
2048         return 0;
2049 }
2050
2051 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2052                 const struct dwc3_event_depevt *event, int status)
2053 {
2054         struct dwc3_request     *req;
2055         struct dwc3_trb         *trb;
2056         unsigned int            slot;
2057         unsigned int            i;
2058         int                     ret;
2059
2060         do {
2061                 req = next_request(&dep->started_list);
2062                 if (WARN_ON_ONCE(!req))
2063                         return 1;
2064
2065                 i = 0;
2066                 do {
2067                         slot = req->first_trb_index + i;
2068                         if (slot == DWC3_TRB_NUM - 1)
2069                                 slot++;
2070                         slot %= DWC3_TRB_NUM;
2071                         trb = &dep->trb_pool[slot];
2072
2073                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2074                                         event, status);
2075                         if (ret)
2076                                 break;
2077                 } while (++i < req->request.num_mapped_sgs);
2078
2079                 dwc3_gadget_giveback(dep, req, status);
2080
2081                 if (ret)
2082                         break;
2083         } while (1);
2084
2085         /*
2086          * Our endpoint might get disabled by another thread during
2087          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2088          * early on so DWC3_EP_BUSY flag gets cleared
2089          */
2090         if (!dep->endpoint.desc)
2091                 return 1;
2092
2093         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2094                         list_empty(&dep->started_list)) {
2095                 if (list_empty(&dep->pending_list)) {
2096                         /*
2097                          * If there is no entry in request list then do
2098                          * not issue END TRANSFER now. Just set PENDING
2099                          * flag, so that END TRANSFER is issued when an
2100                          * entry is added into request list.
2101                          */
2102                         dep->flags = DWC3_EP_PENDING_REQUEST;
2103                 } else {
2104                         dwc3_stop_active_transfer(dwc, dep->number, true);
2105                         dep->flags = DWC3_EP_ENABLED;
2106                 }
2107                 return 1;
2108         }
2109
2110         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2111                 if ((event->status & DEPEVT_STATUS_IOC) &&
2112                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2113                         return 0;
2114         return 1;
2115 }
2116
2117 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2118                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2119 {
2120         unsigned                status = 0;
2121         int                     clean_busy;
2122         u32                     is_xfer_complete;
2123
2124         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2125
2126         if (event->status & DEPEVT_STATUS_BUSERR)
2127                 status = -ECONNRESET;
2128
2129         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2130         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2131                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2132                 dep->flags &= ~DWC3_EP_BUSY;
2133
2134         /*
2135          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2136          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2137          */
2138         if (dwc->revision < DWC3_REVISION_183A) {
2139                 u32             reg;
2140                 int             i;
2141
2142                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2143                         dep = dwc->eps[i];
2144
2145                         if (!(dep->flags & DWC3_EP_ENABLED))
2146                                 continue;
2147
2148                         if (!list_empty(&dep->started_list))
2149                                 return;
2150                 }
2151
2152                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2153                 reg |= dwc->u1u2;
2154                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2155
2156                 dwc->u1u2 = 0;
2157         }
2158
2159         /*
2160          * Our endpoint might get disabled by another thread during
2161          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2162          * early on so DWC3_EP_BUSY flag gets cleared
2163          */
2164         if (!dep->endpoint.desc)
2165                 return;
2166
2167         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2168                 int ret;
2169
2170                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2171                 if (!ret || ret == -EBUSY)
2172                         return;
2173         }
2174 }
2175
2176 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2177                 const struct dwc3_event_depevt *event)
2178 {
2179         struct dwc3_ep          *dep;
2180         u8                      epnum = event->endpoint_number;
2181
2182         dep = dwc->eps[epnum];
2183
2184         if (!(dep->flags & DWC3_EP_ENABLED))
2185                 return;
2186
2187         if (epnum == 0 || epnum == 1) {
2188                 dwc3_ep0_interrupt(dwc, event);
2189                 return;
2190         }
2191
2192         switch (event->endpoint_event) {
2193         case DWC3_DEPEVT_XFERCOMPLETE:
2194                 dep->resource_index = 0;
2195
2196                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2197                         dwc3_trace(trace_dwc3_gadget,
2198                                         "%s is an Isochronous endpoint",
2199                                         dep->name);
2200                         return;
2201                 }
2202
2203                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2204                 break;
2205         case DWC3_DEPEVT_XFERINPROGRESS:
2206                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2207                 break;
2208         case DWC3_DEPEVT_XFERNOTREADY:
2209                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2210                         dwc3_gadget_start_isoc(dwc, dep, event);
2211                 } else {
2212                         int active;
2213                         int ret;
2214
2215                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2216
2217                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2218                                         dep->name, active ? "Transfer Active"
2219                                         : "Transfer Not Active");
2220
2221                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2222                         if (!ret || ret == -EBUSY)
2223                                 return;
2224
2225                         dwc3_trace(trace_dwc3_gadget,
2226                                         "%s: failed to kick transfers",
2227                                         dep->name);
2228                 }
2229
2230                 break;
2231         case DWC3_DEPEVT_STREAMEVT:
2232                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2233                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2234                                         dep->name);
2235                         return;
2236                 }
2237
2238                 switch (event->status) {
2239                 case DEPEVT_STREAMEVT_FOUND:
2240                         dwc3_trace(trace_dwc3_gadget,
2241                                         "Stream %d found and started",
2242                                         event->parameters);
2243
2244                         break;
2245                 case DEPEVT_STREAMEVT_NOTFOUND:
2246                         /* FALLTHROUGH */
2247                 default:
2248                         dwc3_trace(trace_dwc3_gadget,
2249                                         "unable to find suitable stream");
2250                 }
2251                 break;
2252         case DWC3_DEPEVT_RXTXFIFOEVT:
2253                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2254                 break;
2255         case DWC3_DEPEVT_EPCMDCMPLT:
2256                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2257                 break;
2258         }
2259 }
2260
2261 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2262 {
2263         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2264                 spin_unlock(&dwc->lock);
2265                 dwc->gadget_driver->disconnect(&dwc->gadget);
2266                 spin_lock(&dwc->lock);
2267         }
2268 }
2269
2270 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2271 {
2272         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2273                 spin_unlock(&dwc->lock);
2274                 dwc->gadget_driver->suspend(&dwc->gadget);
2275                 spin_lock(&dwc->lock);
2276         }
2277 }
2278
2279 static void dwc3_resume_gadget(struct dwc3 *dwc)
2280 {
2281         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2282                 spin_unlock(&dwc->lock);
2283                 dwc->gadget_driver->resume(&dwc->gadget);
2284                 spin_lock(&dwc->lock);
2285         }
2286 }
2287
2288 static void dwc3_reset_gadget(struct dwc3 *dwc)
2289 {
2290         if (!dwc->gadget_driver)
2291                 return;
2292
2293         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2294                 spin_unlock(&dwc->lock);
2295                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2296                 spin_lock(&dwc->lock);
2297         }
2298 }
2299
2300 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2301 {
2302         struct dwc3_ep *dep;
2303         struct dwc3_gadget_ep_cmd_params params;
2304         u32 cmd;
2305         int ret;
2306
2307         dep = dwc->eps[epnum];
2308
2309         if (!dep->resource_index)
2310                 return;
2311
2312         /*
2313          * NOTICE: We are violating what the Databook says about the
2314          * EndTransfer command. Ideally we would _always_ wait for the
2315          * EndTransfer Command Completion IRQ, but that's causing too
2316          * much trouble synchronizing between us and gadget driver.
2317          *
2318          * We have discussed this with the IP Provider and it was
2319          * suggested to giveback all requests here, but give HW some
2320          * extra time to synchronize with the interconnect. We're using
2321          * an arbitrary 100us delay for that.
2322          *
2323          * Note also that a similar handling was tested by Synopsys
2324          * (thanks a lot Paul) and nothing bad has come out of it.
2325          * In short, what we're doing is:
2326          *
2327          * - Issue EndTransfer WITH CMDIOC bit set
2328          * - Wait 100us
2329          */
2330
2331         cmd = DWC3_DEPCMD_ENDTRANSFER;
2332         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2333         cmd |= DWC3_DEPCMD_CMDIOC;
2334         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2335         memset(&params, 0, sizeof(params));
2336         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2337         WARN_ON_ONCE(ret);
2338         dep->resource_index = 0;
2339         dep->flags &= ~DWC3_EP_BUSY;
2340         udelay(100);
2341 }
2342
2343 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2344 {
2345         u32 epnum;
2346
2347         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2348                 struct dwc3_ep *dep;
2349
2350                 dep = dwc->eps[epnum];
2351                 if (!dep)
2352                         continue;
2353
2354                 if (!(dep->flags & DWC3_EP_ENABLED))
2355                         continue;
2356
2357                 dwc3_remove_requests(dwc, dep);
2358         }
2359 }
2360
2361 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2362 {
2363         u32 epnum;
2364
2365         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2366                 struct dwc3_ep *dep;
2367                 int ret;
2368
2369                 dep = dwc->eps[epnum];
2370                 if (!dep)
2371                         continue;
2372
2373                 if (!(dep->flags & DWC3_EP_STALL))
2374                         continue;
2375
2376                 dep->flags &= ~DWC3_EP_STALL;
2377
2378                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2379                 WARN_ON_ONCE(ret);
2380         }
2381 }
2382
2383 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2384 {
2385         int                     reg;
2386
2387         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2388         reg &= ~DWC3_DCTL_INITU1ENA;
2389         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2390
2391         reg &= ~DWC3_DCTL_INITU2ENA;
2392         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2393
2394         dwc3_disconnect_gadget(dwc);
2395
2396         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2397         dwc->setup_packet_pending = false;
2398         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2399
2400         dwc->connected = false;
2401 }
2402
2403 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2404 {
2405         u32                     reg;
2406
2407         dwc->connected = true;
2408
2409         /*
2410          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2411          * would cause a missing Disconnect Event if there's a
2412          * pending Setup Packet in the FIFO.
2413          *
2414          * There's no suggested workaround on the official Bug
2415          * report, which states that "unless the driver/application
2416          * is doing any special handling of a disconnect event,
2417          * there is no functional issue".
2418          *
2419          * Unfortunately, it turns out that we _do_ some special
2420          * handling of a disconnect event, namely complete all
2421          * pending transfers, notify gadget driver of the
2422          * disconnection, and so on.
2423          *
2424          * Our suggested workaround is to follow the Disconnect
2425          * Event steps here, instead, based on a setup_packet_pending
2426          * flag. Such flag gets set whenever we have a SETUP_PENDING
2427          * status for EP0 TRBs and gets cleared on XferComplete for the
2428          * same endpoint.
2429          *
2430          * Refers to:
2431          *
2432          * STAR#9000466709: RTL: Device : Disconnect event not
2433          * generated if setup packet pending in FIFO
2434          */
2435         if (dwc->revision < DWC3_REVISION_188A) {
2436                 if (dwc->setup_packet_pending)
2437                         dwc3_gadget_disconnect_interrupt(dwc);
2438         }
2439
2440         dwc3_reset_gadget(dwc);
2441
2442         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2443         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2444         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2445         dwc->test_mode = false;
2446
2447         dwc3_stop_active_transfers(dwc);
2448         dwc3_clear_stall_all_ep(dwc);
2449
2450         /* Reset device address to zero */
2451         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2452         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2453         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2454 }
2455
2456 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2457 {
2458         u32 reg;
2459         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2460
2461         /*
2462          * We change the clock only at SS but I dunno why I would want to do
2463          * this. Maybe it becomes part of the power saving plan.
2464          */
2465
2466         if (speed != DWC3_DSTS_SUPERSPEED)
2467                 return;
2468
2469         /*
2470          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2471          * each time on Connect Done.
2472          */
2473         if (!usb30_clock)
2474                 return;
2475
2476         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2477         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2478         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2479 }
2480
2481 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2482 {
2483         struct dwc3_ep          *dep;
2484         int                     ret;
2485         u32                     reg;
2486         u8                      speed;
2487
2488         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2489         speed = reg & DWC3_DSTS_CONNECTSPD;
2490         dwc->speed = speed;
2491
2492         dwc3_update_ram_clk_sel(dwc, speed);
2493
2494         switch (speed) {
2495         case DWC3_DSTS_SUPERSPEED:
2496                 /*
2497                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2498                  * would cause a missing USB3 Reset event.
2499                  *
2500                  * In such situations, we should force a USB3 Reset
2501                  * event by calling our dwc3_gadget_reset_interrupt()
2502                  * routine.
2503                  *
2504                  * Refers to:
2505                  *
2506                  * STAR#9000483510: RTL: SS : USB3 reset event may
2507                  * not be generated always when the link enters poll
2508                  */
2509                 if (dwc->revision < DWC3_REVISION_190A)
2510                         dwc3_gadget_reset_interrupt(dwc);
2511
2512                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2513                 dwc->gadget.ep0->maxpacket = 512;
2514                 dwc->gadget.speed = USB_SPEED_SUPER;
2515                 break;
2516         case DWC3_DSTS_HIGHSPEED:
2517                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2518                 dwc->gadget.ep0->maxpacket = 64;
2519                 dwc->gadget.speed = USB_SPEED_HIGH;
2520                 break;
2521         case DWC3_DSTS_FULLSPEED2:
2522         case DWC3_DSTS_FULLSPEED1:
2523                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2524                 dwc->gadget.ep0->maxpacket = 64;
2525                 dwc->gadget.speed = USB_SPEED_FULL;
2526                 break;
2527         case DWC3_DSTS_LOWSPEED:
2528                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2529                 dwc->gadget.ep0->maxpacket = 8;
2530                 dwc->gadget.speed = USB_SPEED_LOW;
2531                 break;
2532         }
2533
2534         /* Enable USB2 LPM Capability */
2535
2536         if ((dwc->revision > DWC3_REVISION_194A) &&
2537             (speed != DWC3_DSTS_SUPERSPEED)) {
2538                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2539                 reg |= DWC3_DCFG_LPM_CAP;
2540                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2541
2542                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2543                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2544
2545                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2546
2547                 /*
2548                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2549                  * DCFG.LPMCap is set, core responses with an ACK and the
2550                  * BESL value in the LPM token is less than or equal to LPM
2551                  * NYET threshold.
2552                  */
2553                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2554                                 && dwc->has_lpm_erratum,
2555                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2556
2557                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2558                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2559
2560                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2561         } else {
2562                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2563                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2564                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2565         }
2566
2567         dep = dwc->eps[0];
2568         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2569                         false);
2570         if (ret) {
2571                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2572                 return;
2573         }
2574
2575         dep = dwc->eps[1];
2576         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2577                         false);
2578         if (ret) {
2579                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2580                 return;
2581         }
2582
2583         /*
2584          * Configure PHY via GUSB3PIPECTLn if required.
2585          *
2586          * Update GTXFIFOSIZn
2587          *
2588          * In both cases reset values should be sufficient.
2589          */
2590 }
2591
2592 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2593 {
2594         /*
2595          * TODO take core out of low power mode when that's
2596          * implemented.
2597          */
2598
2599         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2600                 spin_unlock(&dwc->lock);
2601                 dwc->gadget_driver->resume(&dwc->gadget);
2602                 spin_lock(&dwc->lock);
2603         }
2604 }
2605
2606 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2607                 unsigned int evtinfo)
2608 {
2609         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2610         unsigned int            pwropt;
2611
2612         /*
2613          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2614          * Hibernation mode enabled which would show up when device detects
2615          * host-initiated U3 exit.
2616          *
2617          * In that case, device will generate a Link State Change Interrupt
2618          * from U3 to RESUME which is only necessary if Hibernation is
2619          * configured in.
2620          *
2621          * There are no functional changes due to such spurious event and we
2622          * just need to ignore it.
2623          *
2624          * Refers to:
2625          *
2626          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2627          * operational mode
2628          */
2629         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2630         if ((dwc->revision < DWC3_REVISION_250A) &&
2631                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2632                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2633                                 (next == DWC3_LINK_STATE_RESUME)) {
2634                         dwc3_trace(trace_dwc3_gadget,
2635                                         "ignoring transition U3 -> Resume");
2636                         return;
2637                 }
2638         }
2639
2640         /*
2641          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2642          * on the link partner, the USB session might do multiple entry/exit
2643          * of low power states before a transfer takes place.
2644          *
2645          * Due to this problem, we might experience lower throughput. The
2646          * suggested workaround is to disable DCTL[12:9] bits if we're
2647          * transitioning from U1/U2 to U0 and enable those bits again
2648          * after a transfer completes and there are no pending transfers
2649          * on any of the enabled endpoints.
2650          *
2651          * This is the first half of that workaround.
2652          *
2653          * Refers to:
2654          *
2655          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2656          * core send LGO_Ux entering U0
2657          */
2658         if (dwc->revision < DWC3_REVISION_183A) {
2659                 if (next == DWC3_LINK_STATE_U0) {
2660                         u32     u1u2;
2661                         u32     reg;
2662
2663                         switch (dwc->link_state) {
2664                         case DWC3_LINK_STATE_U1:
2665                         case DWC3_LINK_STATE_U2:
2666                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2667                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2668                                                 | DWC3_DCTL_ACCEPTU2ENA
2669                                                 | DWC3_DCTL_INITU1ENA
2670                                                 | DWC3_DCTL_ACCEPTU1ENA);
2671
2672                                 if (!dwc->u1u2)
2673                                         dwc->u1u2 = reg & u1u2;
2674
2675                                 reg &= ~u1u2;
2676
2677                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2678                                 break;
2679                         default:
2680                                 /* do nothing */
2681                                 break;
2682                         }
2683                 }
2684         }
2685
2686         switch (next) {
2687         case DWC3_LINK_STATE_U1:
2688                 if (dwc->speed == USB_SPEED_SUPER)
2689                         dwc3_suspend_gadget(dwc);
2690                 break;
2691         case DWC3_LINK_STATE_U2:
2692         case DWC3_LINK_STATE_U3:
2693                 dwc3_suspend_gadget(dwc);
2694                 break;
2695         case DWC3_LINK_STATE_RESUME:
2696                 dwc3_resume_gadget(dwc);
2697                 break;
2698         default:
2699                 /* do nothing */
2700                 break;
2701         }
2702
2703         dwc->link_state = next;
2704 }
2705
2706 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2707                 unsigned int evtinfo)
2708 {
2709         unsigned int is_ss = evtinfo & BIT(4);
2710
2711         /**
2712          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2713          * have a known issue which can cause USB CV TD.9.23 to fail
2714          * randomly.
2715          *
2716          * Because of this issue, core could generate bogus hibernation
2717          * events which SW needs to ignore.
2718          *
2719          * Refers to:
2720          *
2721          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2722          * Device Fallback from SuperSpeed
2723          */
2724         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2725                 return;
2726
2727         /* enter hibernation here */
2728 }
2729
2730 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2731                 const struct dwc3_event_devt *event)
2732 {
2733         switch (event->type) {
2734         case DWC3_DEVICE_EVENT_DISCONNECT:
2735                 dwc3_gadget_disconnect_interrupt(dwc);
2736                 break;
2737         case DWC3_DEVICE_EVENT_RESET:
2738                 dwc3_gadget_reset_interrupt(dwc);
2739                 break;
2740         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2741                 dwc3_gadget_conndone_interrupt(dwc);
2742                 break;
2743         case DWC3_DEVICE_EVENT_WAKEUP:
2744                 dwc3_gadget_wakeup_interrupt(dwc);
2745                 break;
2746         case DWC3_DEVICE_EVENT_HIBER_REQ:
2747                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2748                                         "unexpected hibernation event\n"))
2749                         break;
2750
2751                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2752                 break;
2753         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2754                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2755                 break;
2756         case DWC3_DEVICE_EVENT_EOPF:
2757                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2758                 break;
2759         case DWC3_DEVICE_EVENT_SOF:
2760                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2761                 break;
2762         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2763                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2764                 break;
2765         case DWC3_DEVICE_EVENT_CMD_CMPL:
2766                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2767                 break;
2768         case DWC3_DEVICE_EVENT_OVERFLOW:
2769                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2770                 break;
2771         default:
2772                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2773         }
2774 }
2775
2776 static void dwc3_process_event_entry(struct dwc3 *dwc,
2777                 const union dwc3_event *event)
2778 {
2779         trace_dwc3_event(event->raw);
2780
2781         /* Endpoint IRQ, handle it and return early */
2782         if (event->type.is_devspec == 0) {
2783                 /* depevt */
2784                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2785         }
2786
2787         switch (event->type.type) {
2788         case DWC3_EVENT_TYPE_DEV:
2789                 dwc3_gadget_interrupt(dwc, &event->devt);
2790                 break;
2791         /* REVISIT what to do with Carkit and I2C events ? */
2792         default:
2793                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2794         }
2795 }
2796
2797 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2798 {
2799         struct dwc3 *dwc = evt->dwc;
2800         irqreturn_t ret = IRQ_NONE;
2801         int left;
2802         u32 reg;
2803
2804         left = evt->count;
2805
2806         if (!(evt->flags & DWC3_EVENT_PENDING))
2807                 return IRQ_NONE;
2808
2809         while (left > 0) {
2810                 union dwc3_event event;
2811
2812                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2813
2814                 dwc3_process_event_entry(dwc, &event);
2815
2816                 /*
2817                  * FIXME we wrap around correctly to the next entry as
2818                  * almost all entries are 4 bytes in size. There is one
2819                  * entry which has 12 bytes which is a regular entry
2820                  * followed by 8 bytes data. ATM I don't know how
2821                  * things are organized if we get next to the a
2822                  * boundary so I worry about that once we try to handle
2823                  * that.
2824                  */
2825                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2826                 left -= 4;
2827
2828                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2829         }
2830
2831         evt->count = 0;
2832         evt->flags &= ~DWC3_EVENT_PENDING;
2833         ret = IRQ_HANDLED;
2834
2835         /* Unmask interrupt */
2836         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2837         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2838         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2839
2840         return ret;
2841 }
2842
2843 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2844 {
2845         struct dwc3_event_buffer *evt = _evt;
2846         struct dwc3 *dwc = evt->dwc;
2847         unsigned long flags;
2848         irqreturn_t ret = IRQ_NONE;
2849
2850         spin_lock_irqsave(&dwc->lock, flags);
2851         ret = dwc3_process_event_buf(evt);
2852         spin_unlock_irqrestore(&dwc->lock, flags);
2853
2854         return ret;
2855 }
2856
2857 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2858 {
2859         struct dwc3 *dwc = evt->dwc;
2860         u32 count;
2861         u32 reg;
2862
2863         if (pm_runtime_suspended(dwc->dev)) {
2864                 pm_runtime_get(dwc->dev);
2865                 disable_irq_nosync(dwc->irq_gadget);
2866                 dwc->pending_events = true;
2867                 return IRQ_HANDLED;
2868         }
2869
2870         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2871         count &= DWC3_GEVNTCOUNT_MASK;
2872         if (!count)
2873                 return IRQ_NONE;
2874
2875         evt->count = count;
2876         evt->flags |= DWC3_EVENT_PENDING;
2877
2878         /* Mask interrupt */
2879         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2880         reg |= DWC3_GEVNTSIZ_INTMASK;
2881         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2882
2883         return IRQ_WAKE_THREAD;
2884 }
2885
2886 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2887 {
2888         struct dwc3_event_buffer        *evt = _evt;
2889
2890         return dwc3_check_event_buf(evt);
2891 }
2892
2893 /**
2894  * dwc3_gadget_init - Initializes gadget related registers
2895  * @dwc: pointer to our controller context structure
2896  *
2897  * Returns 0 on success otherwise negative errno.
2898  */
2899 int dwc3_gadget_init(struct dwc3 *dwc)
2900 {
2901         int                                     ret;
2902
2903         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2904                         &dwc->ctrl_req_addr, GFP_KERNEL);
2905         if (!dwc->ctrl_req) {
2906                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2907                 ret = -ENOMEM;
2908                 goto err0;
2909         }
2910
2911         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2912                         &dwc->ep0_trb_addr, GFP_KERNEL);
2913         if (!dwc->ep0_trb) {
2914                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2915                 ret = -ENOMEM;
2916                 goto err1;
2917         }
2918
2919         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2920         if (!dwc->setup_buf) {
2921                 ret = -ENOMEM;
2922                 goto err2;
2923         }
2924
2925         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2926                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2927                         GFP_KERNEL);
2928         if (!dwc->ep0_bounce) {
2929                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2930                 ret = -ENOMEM;
2931                 goto err3;
2932         }
2933
2934         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2935         if (!dwc->zlp_buf) {
2936                 ret = -ENOMEM;
2937                 goto err4;
2938         }
2939
2940         dwc->gadget.ops                 = &dwc3_gadget_ops;
2941         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2942         dwc->gadget.sg_supported        = true;
2943         dwc->gadget.name                = "dwc3-gadget";
2944         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2945
2946         /*
2947          * FIXME We might be setting max_speed to <SUPER, however versions
2948          * <2.20a of dwc3 have an issue with metastability (documented
2949          * elsewhere in this driver) which tells us we can't set max speed to
2950          * anything lower than SUPER.
2951          *
2952          * Because gadget.max_speed is only used by composite.c and function
2953          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2954          * to happen so we avoid sending SuperSpeed Capability descriptor
2955          * together with our BOS descriptor as that could confuse host into
2956          * thinking we can handle super speed.
2957          *
2958          * Note that, in fact, we won't even support GetBOS requests when speed
2959          * is less than super speed because we don't have means, yet, to tell
2960          * composite.c that we are USB 2.0 + LPM ECN.
2961          */
2962         if (dwc->revision < DWC3_REVISION_220A)
2963                 dwc3_trace(trace_dwc3_gadget,
2964                                 "Changing max_speed on rev %08x",
2965                                 dwc->revision);
2966
2967         dwc->gadget.max_speed           = dwc->maximum_speed;
2968
2969         /*
2970          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2971          * on ep out.
2972          */
2973         dwc->gadget.quirk_ep_out_aligned_size = true;
2974
2975         /*
2976          * REVISIT: Here we should clear all pending IRQs to be
2977          * sure we're starting from a well known location.
2978          */
2979
2980         ret = dwc3_gadget_init_endpoints(dwc);
2981         if (ret)
2982                 goto err5;
2983
2984         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2985         if (ret) {
2986                 dev_err(dwc->dev, "failed to register udc\n");
2987                 goto err5;
2988         }
2989
2990         return 0;
2991
2992 err5:
2993         kfree(dwc->zlp_buf);
2994
2995 err4:
2996         dwc3_gadget_free_endpoints(dwc);
2997         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2998                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2999
3000 err3:
3001         kfree(dwc->setup_buf);
3002
3003 err2:
3004         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3005                         dwc->ep0_trb, dwc->ep0_trb_addr);
3006
3007 err1:
3008         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3009                         dwc->ctrl_req, dwc->ctrl_req_addr);
3010
3011 err0:
3012         return ret;
3013 }
3014
3015 /* -------------------------------------------------------------------------- */
3016
3017 void dwc3_gadget_exit(struct dwc3 *dwc)
3018 {
3019         usb_del_gadget_udc(&dwc->gadget);
3020
3021         dwc3_gadget_free_endpoints(dwc);
3022
3023         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3024                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3025
3026         kfree(dwc->setup_buf);
3027         kfree(dwc->zlp_buf);
3028
3029         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3030                         dwc->ep0_trb, dwc->ep0_trb_addr);
3031
3032         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3033                         dwc->ctrl_req, dwc->ctrl_req_addr);
3034 }
3035
3036 int dwc3_gadget_suspend(struct dwc3 *dwc)
3037 {
3038         int ret;
3039
3040         if (!dwc->gadget_driver)
3041                 return 0;
3042
3043         ret = dwc3_gadget_run_stop(dwc, false, false);
3044         if (ret < 0)
3045                 return ret;
3046
3047         dwc3_disconnect_gadget(dwc);
3048         __dwc3_gadget_stop(dwc);
3049
3050         return 0;
3051 }
3052
3053 int dwc3_gadget_resume(struct dwc3 *dwc)
3054 {
3055         int                     ret;
3056
3057         if (!dwc->gadget_driver)
3058                 return 0;
3059
3060         ret = __dwc3_gadget_start(dwc);
3061         if (ret < 0)
3062                 goto err0;
3063
3064         ret = dwc3_gadget_run_stop(dwc, true, false);
3065         if (ret < 0)
3066                 goto err1;
3067
3068         return 0;
3069
3070 err1:
3071         __dwc3_gadget_stop(dwc);
3072
3073 err0:
3074         return ret;
3075 }
3076
3077 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3078 {
3079         if (dwc->pending_events) {
3080                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3081                 dwc->pending_events = false;
3082                 enable_irq(dwc->irq_gadget);
3083         }
3084 }