drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_ep_inc_trb() - Increment a TRB index.
 150  * @index - Pointer to the TRB index to increment.
 151  *
 152  * The index should never point to the link TRB. After incrementing,
 153  * if it is point to the link TRB, wrap around to the beginning. The
 154  * link TRB is always at the last TRB entry.
 155  */
 156 static void dwc3_ep_inc_trb(u8 *index)
 157 {
 158         (*index)++;
 159         if (*index == (DWC3_TRB_NUM - 1))
 160                 *index = 0;
 161 }
 162
 163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 164 {
 165         dwc3_ep_inc_trb(&dep->trb_enqueue);
 166 }
 167
 168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 169 {
 170         dwc3_ep_inc_trb(&dep->trb_dequeue);
 171 }
 172
 173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 174                 int status)
 175 {
 176         struct dwc3                     *dwc = dep->dwc;
 177         int                             i;
 178
 179         if (req->started) {
 180                 i = 0;
 181                 do {
 182                         dwc3_ep_inc_deq(dep);
 183                 } while(++i < req->request.num_mapped_sgs);
 184                 req->started = false;
 185         }
 186         list_del(&req->list);
 187         req->trb = NULL;
 188
 189         if (req->request.status == -EINPROGRESS)
 190                 req->request.status = status;
 191
 192         if (dwc->ep0_bounced && dep->number == 0)
 193                 dwc->ep0_bounced = false;
 194         else
 195                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 196                                 req->direction);
 197
 198         trace_dwc3_gadget_giveback(req);
 199
 200         spin_unlock(&dwc->lock);
 201         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 202         spin_lock(&dwc->lock);
 203
 204         if (dep->number > 1)
 205                 pm_runtime_put(dwc->dev);
 206 }
 207
 208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 209 {
 210         u32             timeout = 500;
 211         int             status = 0;
 212         int             ret = 0;
 213         u32             reg;
 214
 215         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 216         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 217
 218         do {
 219                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 220                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 221                         status = DWC3_DGCMD_STATUS(reg);
 222                         if (status)
 223                                 ret = -EINVAL;
 224                         break;
 225                 }
 226         } while (timeout--);
 227
 228         if (!timeout) {
 229                 ret = -ETIMEDOUT;
 230                 status = -ETIMEDOUT;
 231         }
 232
 233         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 234
 235         return ret;
 236 }
 237
 238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 239
 240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 241                 struct dwc3_gadget_ep_cmd_params *params)
 242 {
 243         struct dwc3             *dwc = dep->dwc;
 244         u32                     timeout = 500;
 245         u32                     reg;
 246
 247         int                     cmd_status = 0;
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         /*
 252          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 253          * we're issuing an endpoint command, we must check if
 254          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 255          *
 256          * We will also set SUSPHY bit to what it was before returning as stated
 257          * by the same section on Synopsys databook.
 258          */
 259         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 260                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 261                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 262                         susphy = true;
 263                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 264                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 265                 }
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 283         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 285
 286         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         switch (cmd_status) {
 293                         case 0:
 294                                 ret = 0;
 295                                 break;
 296                         case DEPEVT_TRANSFER_NO_RESOURCE:
 297                                 ret = -EINVAL;
 298                                 break;
 299                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 300                                 /*
 301                                  * SW issues START TRANSFER command to
 302                                  * isochronous ep with future frame interval. If
 303                                  * future interval time has already passed when
 304                                  * core receives the command, it will respond
 305                                  * with an error status of 'Bus Expiry'.
 306                                  *
 307                                  * Instead of always returning -EINVAL, let's
 308                                  * give a hint to the gadget driver that this is
 309                                  * the case by returning -EAGAIN.
 310                                  */
 311                                 ret = -EAGAIN;
 312                                 break;
 313                         default:
 314                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 315                         }
 316
 317                         break;
 318                 }
 319         } while (--timeout);
 320
 321         if (timeout == 0) {
 322                 ret = -ETIMEDOUT;
 323                 cmd_status = -ETIMEDOUT;
 324         }
 325
 326         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 327
 328         if (unlikely(susphy)) {
 329                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 330                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 331                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 338 {
 339         struct dwc3 *dwc = dep->dwc;
 340         struct dwc3_gadget_ep_cmd_params params;
 341         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 342
 343         /*
 344          * As of core revision 2.60a the recommended programming model
 345          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 346          * command for IN endpoints. This is to prevent an issue where
 347          * some (non-compliant) hosts may not send ACK TPs for pending
 348          * IN transfers due to a mishandled error condition. Synopsys
 349          * STAR 9000614252.
 350          */
 351         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 352                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 353
 354         memset(&params, 0, sizeof(params));
 355
 356         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 357 }
 358
 359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 360                 struct dwc3_trb *trb)
 361 {
 362         u32             offset = (char *) trb - (char *) dep->trb_pool;
 363
 364         return dep->trb_pool_dma + offset;
 365 }
 366
 367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 368 {
 369         struct dwc3             *dwc = dep->dwc;
 370
 371         if (dep->trb_pool)
 372                 return 0;
 373
 374         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 375                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 376                         &dep->trb_pool_dma, GFP_KERNEL);
 377         if (!dep->trb_pool) {
 378                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 379                                 dep->name);
 380                 return -ENOMEM;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 387 {
 388         struct dwc3             *dwc = dep->dwc;
 389
 390         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         dep->trb_pool, dep->trb_pool_dma);
 392
 393         dep->trb_pool = NULL;
 394         dep->trb_pool_dma = 0;
 395 }
 396
 397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 398
 399 /**
 400  * dwc3_gadget_start_config - Configure EP resources
 401  * @dwc: pointer to our controller context structure
 402  * @dep: endpoint that is being enabled
 403  *
 404  * The assignment of transfer resources cannot perfectly follow the
 405  * data book due to the fact that the controller driver does not have
 406  * all knowledge of the configuration in advance. It is given this
 407  * information piecemeal by the composite gadget framework after every
 408  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 409  * programming model in this scenario can cause errors. For two
 410  * reasons:
 411  *
 412  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 413  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 414  * multiple interfaces.
 415  *
 416  * 2) The databook does not mention doing more DEPXFERCFG for new
 417  * endpoint on alt setting (8.1.6).
 418  *
 419  * The following simplified method is used instead:
 420  *
 421  * All hardware endpoints can be assigned a transfer resource and this
 422  * setting will stay persistent until either a core reset or
 423  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 424  * do DEPXFERCFG for every hardware endpoint as well. We are
 425  * guaranteed that there are as many transfer resources as endpoints.
 426  *
 427  * This function is called for each endpoint when it is being enabled
 428  * but is triggered only when called for EP0-out, which always happens
 429  * first, and which should only happen in one of the above conditions.
 430  */
 431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 432 {
 433         struct dwc3_gadget_ep_cmd_params params;
 434         u32                     cmd;
 435         int                     i;
 436         int                     ret;
 437
 438         if (dep->number)
 439                 return 0;
 440
 441         memset(&params, 0x00, sizeof(params));
 442         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 443
 444         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 445         if (ret)
 446                 return ret;
 447
 448         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 449                 struct dwc3_ep *dep = dwc->eps[i];
 450
 451                 if (!dep)
 452                         continue;
 453
 454                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 463                 const struct usb_endpoint_descriptor *desc,
 464                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 465                 bool modify, bool restore)
 466 {
 467         struct dwc3_gadget_ep_cmd_params params;
 468
 469         if (dev_WARN_ONCE(dwc->dev, modify && restore,
 470                                         "Can't modify and restore\n"))
 471                 return -EINVAL;
 472
 473         memset(&params, 0x00, sizeof(params));
 474
 475         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 476                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 477
 478         /* Burst size is only needed in SuperSpeed mode */
 479         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 480                 u32 burst = dep->endpoint.maxburst;
 481                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 482         }
 483
 484         if (modify) {
 485                 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
 486         } else if (restore) {
 487                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 488                 params.param2 |= dep->saved_state;
 489         } else {
 490                 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
 491         }
 492
 493         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 494
 495         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 496                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 497
 498         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 499                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 500                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 501                 dep->stream_capable = true;
 502         }
 503
 504         if (!usb_endpoint_xfer_control(desc))
 505                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 506
 507         /*
 508          * We are doing 1:1 mapping for endpoints, meaning
 509          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 510          * so on. We consider the direction bit as part of the physical
 511          * endpoint number. So USB endpoint 0x81 is 0x03.
 512          */
 513         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 514
 515         /*
 516          * We must use the lower 16 TX FIFOs even though
 517          * HW might have more
 518          */
 519         if (dep->direction)
 520                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 521
 522         if (desc->bInterval) {
 523                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 524                 dep->interval = 1 << (desc->bInterval - 1);
 525         }
 526
 527         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 528 }
 529
 530 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 531 {
 532         struct dwc3_gadget_ep_cmd_params params;
 533
 534         memset(&params, 0x00, sizeof(params));
 535
 536         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 537
 538         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 539                         &params);
 540 }
 541
 542 /**
 543  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 544  * @dep: endpoint to be initialized
 545  * @desc: USB Endpoint Descriptor
 546  *
 547  * Caller should take care of locking
 548  */
 549 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 550                 const struct usb_endpoint_descriptor *desc,
 551                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 552                 bool modify, bool restore)
 553 {
 554         struct dwc3             *dwc = dep->dwc;
 555         u32                     reg;
 556         int                     ret;
 557
 558         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 559
 560         if (!(dep->flags & DWC3_EP_ENABLED)) {
 561                 ret = dwc3_gadget_start_config(dwc, dep);
 562                 if (ret)
 563                         return ret;
 564         }
 565
 566         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, modify,
 567                         restore);
 568         if (ret)
 569                 return ret;
 570
 571         if (!(dep->flags & DWC3_EP_ENABLED)) {
 572                 struct dwc3_trb *trb_st_hw;
 573                 struct dwc3_trb *trb_link;
 574
 575                 dep->endpoint.desc = desc;
 576                 dep->comp_desc = comp_desc;
 577                 dep->type = usb_endpoint_type(desc);
 578                 dep->flags |= DWC3_EP_ENABLED;
 579
 580                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 581                 reg |= DWC3_DALEPENA_EP(dep->number);
 582                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 583
 584                 if (usb_endpoint_xfer_control(desc))
 585                         return 0;
 586
 587                 /* Initialize the TRB ring */
 588                 dep->trb_dequeue = 0;
 589                 dep->trb_enqueue = 0;
 590                 memset(dep->trb_pool, 0,
 591                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 592
 593                 /* Link TRB. The HWO bit is never reset */
 594                 trb_st_hw = &dep->trb_pool[0];
 595
 596                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 597                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 598                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 599                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 600                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 601         }
 602
 603         return 0;
 604 }
 605
 606 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 607 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 608 {
 609         struct dwc3_request             *req;
 610         struct dwc3_trb                 *current_trb;
 611         unsigned                        transfer_in_flight;
 612
 613         if (dep->number > 1)
 614                 current_trb = &dep->trb_pool[dep->trb_enqueue];
 615         else
 616                 current_trb = &dwc->ep0_trb[dep->trb_enqueue];
 617         transfer_in_flight = current_trb->ctrl & DWC3_TRB_CTRL_HWO;
 618
 619         if (transfer_in_flight && !list_empty(&dep->started_list)) {
 620                 dwc3_stop_active_transfer(dwc, dep->number, true);
 621
 622                 /* - giveback all requests to gadget driver */
 623                 while (!list_empty(&dep->started_list)) {
 624                         req = next_request(&dep->started_list);
 625
 626                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 627                 }
 628         }
 629
 630         while (!list_empty(&dep->pending_list)) {
 631                 req = next_request(&dep->pending_list);
 632
 633                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 634         }
 635 }
 636
 637 /**
 638  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 639  * @dep: the endpoint to disable
 640  *
 641  * This function also removes requests which are currently processed ny the
 642  * hardware and those which are not yet scheduled.
 643  * Caller should take care of locking.
 644  */
 645 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 646 {
 647         struct dwc3             *dwc = dep->dwc;
 648         u32                     reg;
 649
 650         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 651
 652         dwc3_remove_requests(dwc, dep);
 653
 654         /* make sure HW endpoint isn't stalled */
 655         if (dep->flags & DWC3_EP_STALL)
 656                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 657
 658         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 659         reg &= ~DWC3_DALEPENA_EP(dep->number);
 660         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 661
 662         dep->stream_capable = false;
 663         dep->endpoint.desc = NULL;
 664         dep->comp_desc = NULL;
 665         dep->type = 0;
 666         dep->flags = 0;
 667
 668         return 0;
 669 }
 670
 671 /* -------------------------------------------------------------------------- */
 672
 673 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 674                 const struct usb_endpoint_descriptor *desc)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 680 {
 681         return -EINVAL;
 682 }
 683
 684 /* -------------------------------------------------------------------------- */
 685
 686 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 687                 const struct usb_endpoint_descriptor *desc)
 688 {
 689         struct dwc3_ep                  *dep;
 690         struct dwc3                     *dwc;
 691         unsigned long                   flags;
 692         int                             ret;
 693
 694         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 695                 pr_debug("dwc3: invalid parameters\n");
 696                 return -EINVAL;
 697         }
 698
 699         if (!desc->wMaxPacketSize) {
 700                 pr_debug("dwc3: missing wMaxPacketSize\n");
 701                 return -EINVAL;
 702         }
 703
 704         dep = to_dwc3_ep(ep);
 705         dwc = dep->dwc;
 706
 707         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 708                                         "%s is already enabled\n",
 709                                         dep->name))
 710                 return 0;
 711
 712         spin_lock_irqsave(&dwc->lock, flags);
 713         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 714         spin_unlock_irqrestore(&dwc->lock, flags);
 715
 716         return ret;
 717 }
 718
 719 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 720 {
 721         struct dwc3_ep                  *dep;
 722         struct dwc3                     *dwc;
 723         unsigned long                   flags;
 724         int                             ret;
 725
 726         if (!ep) {
 727                 pr_debug("dwc3: invalid parameters\n");
 728                 return -EINVAL;
 729         }
 730
 731         dep = to_dwc3_ep(ep);
 732         dwc = dep->dwc;
 733
 734         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 735                                         "%s is already disabled\n",
 736                                         dep->name))
 737                 return 0;
 738
 739         spin_lock_irqsave(&dwc->lock, flags);
 740         ret = __dwc3_gadget_ep_disable(dep);
 741         spin_unlock_irqrestore(&dwc->lock, flags);
 742
 743         return ret;
 744 }
 745
 746 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 747         gfp_t gfp_flags)
 748 {
 749         struct dwc3_request             *req;
 750         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 751
 752         req = kzalloc(sizeof(*req), gfp_flags);
 753         if (!req)
 754                 return NULL;
 755
 756         req->epnum      = dep->number;
 757         req->dep        = dep;
 758
 759         dep->allocated_requests++;
 760
 761         trace_dwc3_alloc_request(req);
 762
 763         return &req->request;
 764 }
 765
 766 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 767                 struct usb_request *request)
 768 {
 769         struct dwc3_request             *req = to_dwc3_request(request);
 770         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 771
 772         dep->allocated_requests--;
 773         trace_dwc3_free_request(req);
 774         kfree(req);
 775 }
 776
 777 /**
 778  * dwc3_prepare_one_trb - setup one TRB from one request
 779  * @dep: endpoint for which this request is prepared
 780  * @req: dwc3_request pointer
 781  */
 782 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 783                 struct dwc3_request *req, dma_addr_t dma,
 784                 unsigned length, unsigned last, unsigned chain, unsigned node)
 785 {
 786         struct dwc3_trb         *trb;
 787
 788         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 789                         dep->name, req, (unsigned long long) dma,
 790                         length, last ? " last" : "",
 791                         chain ? " chain" : "");
 792
 793
 794         trb = &dep->trb_pool[dep->trb_enqueue];
 795
 796         if (!req->trb) {
 797                 dwc3_gadget_move_started_request(req);
 798                 req->trb = trb;
 799                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 800                 req->first_trb_index = dep->trb_enqueue;
 801         }
 802
 803         dwc3_ep_inc_enq(dep);
 804
 805         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 806         trb->bpl = lower_32_bits(dma);
 807         trb->bph = upper_32_bits(dma);
 808
 809         switch (usb_endpoint_type(dep->endpoint.desc)) {
 810         case USB_ENDPOINT_XFER_CONTROL:
 811                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 812                 break;
 813
 814         case USB_ENDPOINT_XFER_ISOC:
 815                 if (!node)
 816                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 817                 else
 818                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 819
 820                 /* always enable Interrupt on Missed ISOC */
 821                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 822                 break;
 823
 824         case USB_ENDPOINT_XFER_BULK:
 825         case USB_ENDPOINT_XFER_INT:
 826                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 827                 break;
 828         default:
 829                 /*
 830                  * This is only possible with faulty memory because we
 831                  * checked it already :)
 832                  */
 833                 BUG();
 834         }
 835
 836         /* always enable Continue on Short Packet */
 837         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 838
 839         if (!req->request.no_interrupt && !chain)
 840                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 841
 842         if (last)
 843                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 844
 845         if (chain)
 846                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 847
 848         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 849                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 850
 851         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 852
 853         dep->queued_requests++;
 854
 855         trace_dwc3_prepare_trb(dep, trb);
 856 }
 857
 858 /**
 859  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 860  * @dep: The endpoint with the TRB ring
 861  * @index: The index of the current TRB in the ring
 862  *
 863  * Returns the TRB prior to the one pointed to by the index. If the
 864  * index is 0, we will wrap backwards, skip the link TRB, and return
 865  * the one just before that.
 866  */
 867 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 868 {
 869         if (!index)
 870                 index = DWC3_TRB_NUM - 2;
 871         else
 872                 index = dep->trb_enqueue - 1;
 873
 874         return &dep->trb_pool[index];
 875 }
 876
 877 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 878 {
 879         struct dwc3_trb         *tmp;
 880         u8                      trbs_left;
 881
 882         /*
 883          * If enqueue & dequeue are equal than it is either full or empty.
 884          *
 885          * One way to know for sure is if the TRB right before us has HWO bit
 886          * set or not. If it has, then we're definitely full and can't fit any
 887          * more transfers in our ring.
 888          */
 889         if (dep->trb_enqueue == dep->trb_dequeue) {
 890                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 891                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 892                         return 0;
 893
 894                 return DWC3_TRB_NUM - 1;
 895         }
 896
 897         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 898         trbs_left &= (DWC3_TRB_NUM - 1);
 899
 900         if (dep->trb_dequeue < dep->trb_enqueue)
 901                 trbs_left--;
 902
 903         return trbs_left;
 904 }
 905
 906 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 907                 struct dwc3_request *req, unsigned int trbs_left,
 908                 unsigned int more_coming)
 909 {
 910         struct usb_request *request = &req->request;
 911         struct scatterlist *sg = request->sg;
 912         struct scatterlist *s;
 913         unsigned int    last = false;
 914         unsigned int    length;
 915         dma_addr_t      dma;
 916         int             i;
 917
 918         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 919                 unsigned chain = true;
 920
 921                 length = sg_dma_len(s);
 922                 dma = sg_dma_address(s);
 923
 924                 if (sg_is_last(s)) {
 925                         if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
 926                                 !more_coming)
 927                                 last = true;
 928
 929                         chain = false;
 930                 }
 931
 932                 if (!trbs_left--)
 933                         last = true;
 934
 935                 if (last)
 936                         chain = false;
 937
 938                 dwc3_prepare_one_trb(dep, req, dma, length,
 939                                 last, chain, i);
 940
 941                 if (last)
 942                         break;
 943         }
 944 }
 945
 946 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 947                 struct dwc3_request *req, unsigned int trbs_left,
 948                 unsigned int more_coming)
 949 {
 950         unsigned int    last = false;
 951         unsigned int    length;
 952         dma_addr_t      dma;
 953
 954         dma = req->request.dma;
 955         length = req->request.length;
 956
 957         if (!trbs_left)
 958                 last = true;
 959
 960         /* Is this the last request? */
 961         if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
 962                 last = true;
 963
 964         dwc3_prepare_one_trb(dep, req, dma, length,
 965                         last, false, 0);
 966 }
 967
 968 /*
 969  * dwc3_prepare_trbs - setup TRBs from requests
 970  * @dep: endpoint for which requests are being prepared
 971  *
 972  * The function goes through the requests list and sets up TRBs for the
 973  * transfers. The function returns once there are no more TRBs available or
 974  * it runs out of requests.
 975  */
 976 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 977 {
 978         struct dwc3_request     *req, *n;
 979         unsigned int            more_coming;
 980         u32                     trbs_left;
 981
 982         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 983
 984         trbs_left = dwc3_calc_trbs_left(dep);
 985         if (!trbs_left)
 986                 return;
 987
 988         more_coming = dep->allocated_requests - dep->queued_requests;
 989
 990         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 991                 if (req->request.num_mapped_sgs > 0)
 992                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
 993                                         more_coming);
 994                 else
 995                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
 996                                         more_coming);
 997
 998                 if (!trbs_left)
 999                         return;
1000         }
1001 }
1002
1003 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1004 {
1005         struct dwc3_gadget_ep_cmd_params params;
1006         struct dwc3_request             *req;
1007         struct dwc3                     *dwc = dep->dwc;
1008         int                             starting;
1009         int                             ret;
1010         u32                             cmd;
1011
1012         starting = !(dep->flags & DWC3_EP_BUSY);
1013
1014         dwc3_prepare_trbs(dep);
1015         req = next_request(&dep->started_list);
1016         if (!req) {
1017                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1018                 return 0;
1019         }
1020
1021         memset(&params, 0, sizeof(params));
1022
1023         if (starting) {
1024                 params.param0 = upper_32_bits(req->trb_dma);
1025                 params.param1 = lower_32_bits(req->trb_dma);
1026                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1027                         DWC3_DEPCMD_PARAM(cmd_param);
1028         } else {
1029                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1030                         DWC3_DEPCMD_PARAM(dep->resource_index);
1031         }
1032
1033         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1034         if (ret < 0) {
1035                 /*
1036                  * FIXME we need to iterate over the list of requests
1037                  * here and stop, unmap, free and del each of the linked
1038                  * requests instead of what we do now.
1039                  */
1040                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1041                                 req->direction);
1042                 list_del(&req->list);
1043                 return ret;
1044         }
1045
1046         dep->flags |= DWC3_EP_BUSY;
1047
1048         if (starting) {
1049                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1050                 WARN_ON_ONCE(!dep->resource_index);
1051         }
1052
1053         return 0;
1054 }
1055
1056 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1057                 struct dwc3_ep *dep, u32 cur_uf)
1058 {
1059         u32 uf;
1060
1061         if (list_empty(&dep->pending_list)) {
1062                 dwc3_trace(trace_dwc3_gadget,
1063                                 "ISOC ep %s run out for requests",
1064                                 dep->name);
1065                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1066                 return;
1067         }
1068
1069         /* 4 micro frames in the future */
1070         uf = cur_uf + dep->interval * 4;
1071
1072         __dwc3_gadget_kick_transfer(dep, uf);
1073 }
1074
1075 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1076                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1077 {
1078         u32 cur_uf, mask;
1079
1080         mask = ~(dep->interval - 1);
1081         cur_uf = event->parameters & mask;
1082
1083         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1084 }
1085
1086 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1087 {
1088         struct dwc3             *dwc = dep->dwc;
1089         int                     ret;
1090
1091         if (!dep->endpoint.desc) {
1092                 dwc3_trace(trace_dwc3_gadget,
1093                                 "trying to queue request %p to disabled %s",
1094                                 &req->request, dep->endpoint.name);
1095                 return -ESHUTDOWN;
1096         }
1097
1098         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1099                                 &req->request, req->dep->name)) {
1100                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1101                                 &req->request, req->dep->name);
1102                 return -EINVAL;
1103         }
1104
1105         pm_runtime_get(dwc->dev);
1106
1107         req->request.actual     = 0;
1108         req->request.status     = -EINPROGRESS;
1109         req->direction          = dep->direction;
1110         req->epnum              = dep->number;
1111
1112         trace_dwc3_ep_queue(req);
1113
1114         /*
1115          * Per databook, the total size of buffer must be a multiple
1116          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1117          * configed for endpoints in dwc3_gadget_set_ep_config(),
1118          * set to usb_endpoint_descriptor->wMaxPacketSize.
1119          */
1120         if (dep->direction == 0 &&
1121             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1122                 req->request.length = roundup(req->request.length,
1123                                         dep->endpoint.desc->wMaxPacketSize);
1124
1125         /*
1126          * We only add to our list of requests now and
1127          * start consuming the list once we get XferNotReady
1128          * IRQ.
1129          *
1130          * That way, we avoid doing anything that we don't need
1131          * to do now and defer it until the point we receive a
1132          * particular token from the Host side.
1133          *
1134          * This will also avoid Host cancelling URBs due to too
1135          * many NAKs.
1136          */
1137         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1138                         dep->direction);
1139         if (ret)
1140                 return ret;
1141
1142         list_add_tail(&req->list, &dep->pending_list);
1143
1144         /*
1145          * If there are no pending requests and the endpoint isn't already
1146          * busy, we will just start the request straight away.
1147          *
1148          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1149          * little bit faster.
1150          */
1151         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1152                         !usb_endpoint_xfer_int(dep->endpoint.desc)) {
1153                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1154                 goto out;
1155         }
1156
1157         /*
1158          * There are a few special cases:
1159          *
1160          * 1. XferNotReady with empty list of requests. We need to kick the
1161          *    transfer here in that situation, otherwise we will be NAKing
1162          *    forever. If we get XferNotReady before gadget driver has a
1163          *    chance to queue a request, we will ACK the IRQ but won't be
1164          *    able to receive the data until the next request is queued.
1165          *    The following code is handling exactly that.
1166          *
1167          */
1168         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1169                 /*
1170                  * If xfernotready is already elapsed and it is a case
1171                  * of isoc transfer, then issue END TRANSFER, so that
1172                  * you can receive xfernotready again and can have
1173                  * notion of current microframe.
1174                  */
1175                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1176                         if (list_empty(&dep->started_list)) {
1177                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1178                                 dep->flags = DWC3_EP_ENABLED;
1179                         }
1180                         return 0;
1181                 }
1182
1183                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1184                 if (!ret)
1185                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1186
1187                 goto out;
1188         }
1189
1190         /*
1191          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1192          *    kick the transfer here after queuing a request, otherwise the
1193          *    core may not see the modified TRB(s).
1194          */
1195         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1196                         (dep->flags & DWC3_EP_BUSY) &&
1197                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1198                 WARN_ON_ONCE(!dep->resource_index);
1199                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1200                 goto out;
1201         }
1202
1203         /*
1204          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1205          * right away, otherwise host will not know we have streams to be
1206          * handled.
1207          */
1208         if (dep->stream_capable)
1209                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1210
1211 out:
1212         if (ret && ret != -EBUSY)
1213                 dwc3_trace(trace_dwc3_gadget,
1214                                 "%s: failed to kick transfers",
1215                                 dep->name);
1216         if (ret == -EBUSY)
1217                 ret = 0;
1218
1219         return ret;
1220 }
1221
1222 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1223                 struct usb_request *request)
1224 {
1225         dwc3_gadget_ep_free_request(ep, request);
1226 }
1227
1228 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1229 {
1230         struct dwc3_request             *req;
1231         struct usb_request              *request;
1232         struct usb_ep                   *ep = &dep->endpoint;
1233
1234         dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1235         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1236         if (!request)
1237                 return -ENOMEM;
1238
1239         request->length = 0;
1240         request->buf = dwc->zlp_buf;
1241         request->complete = __dwc3_gadget_ep_zlp_complete;
1242
1243         req = to_dwc3_request(request);
1244
1245         return __dwc3_gadget_ep_queue(dep, req);
1246 }
1247
1248 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1249         gfp_t gfp_flags)
1250 {
1251         struct dwc3_request             *req = to_dwc3_request(request);
1252         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1253         struct dwc3                     *dwc = dep->dwc;
1254
1255         unsigned long                   flags;
1256
1257         int                             ret;
1258
1259         spin_lock_irqsave(&dwc->lock, flags);
1260         ret = __dwc3_gadget_ep_queue(dep, req);
1261
1262         /*
1263          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1264          * setting request->zero, instead of doing magic, we will just queue an
1265          * extra usb_request ourselves so that it gets handled the same way as
1266          * any other request.
1267          */
1268         if (ret == 0 && request->zero && request->length &&
1269             (request->length % ep->desc->wMaxPacketSize == 0))
1270                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1271
1272         spin_unlock_irqrestore(&dwc->lock, flags);
1273
1274         return ret;
1275 }
1276
1277 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1278                 struct usb_request *request)
1279 {
1280         struct dwc3_request             *req = to_dwc3_request(request);
1281         struct dwc3_request             *r = NULL;
1282
1283         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1284         struct dwc3                     *dwc = dep->dwc;
1285
1286         unsigned long                   flags;
1287         int                             ret = 0;
1288
1289         trace_dwc3_ep_dequeue(req);
1290
1291         spin_lock_irqsave(&dwc->lock, flags);
1292
1293         list_for_each_entry(r, &dep->pending_list, list) {
1294                 if (r == req)
1295                         break;
1296         }
1297
1298         if (r != req) {
1299                 list_for_each_entry(r, &dep->started_list, list) {
1300                         if (r == req)
1301                                 break;
1302                 }
1303                 if (r == req) {
1304                         /* wait until it is processed */
1305                         dwc3_stop_active_transfer(dwc, dep->number, true);
1306                         goto out1;
1307                 }
1308                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1309                                 request, ep->name);
1310                 ret = -EINVAL;
1311                 goto out0;
1312         }
1313
1314 out1:
1315         /* giveback the request */
1316         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1317
1318 out0:
1319         spin_unlock_irqrestore(&dwc->lock, flags);
1320
1321         return ret;
1322 }
1323
1324 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1325 {
1326         struct dwc3_gadget_ep_cmd_params        params;
1327         struct dwc3                             *dwc = dep->dwc;
1328         int                                     ret;
1329
1330         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1331                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1332                 return -EINVAL;
1333         }
1334
1335         memset(&params, 0x00, sizeof(params));
1336
1337         if (value) {
1338                 struct dwc3_trb *trb;
1339
1340                 unsigned transfer_in_flight;
1341                 unsigned started;
1342
1343                 if (dep->number > 1)
1344                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1345                 else
1346                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1347
1348                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1349                 started = !list_empty(&dep->started_list);
1350
1351                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1352                                 (!dep->direction && started))) {
1353                         dwc3_trace(trace_dwc3_gadget,
1354                                         "%s: pending request, cannot halt",
1355                                         dep->name);
1356                         return -EAGAIN;
1357                 }
1358
1359                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1360                                 &params);
1361                 if (ret)
1362                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1363                                         dep->name);
1364                 else
1365                         dep->flags |= DWC3_EP_STALL;
1366         } else {
1367
1368                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1369                 if (ret)
1370                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1371                                         dep->name);
1372                 else
1373                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1374         }
1375
1376         return ret;
1377 }
1378
1379 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1380 {
1381         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1382         struct dwc3                     *dwc = dep->dwc;
1383
1384         unsigned long                   flags;
1385
1386         int                             ret;
1387
1388         spin_lock_irqsave(&dwc->lock, flags);
1389         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1390         spin_unlock_irqrestore(&dwc->lock, flags);
1391
1392         return ret;
1393 }
1394
1395 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1396 {
1397         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1398         struct dwc3                     *dwc = dep->dwc;
1399         unsigned long                   flags;
1400         int                             ret;
1401
1402         spin_lock_irqsave(&dwc->lock, flags);
1403         dep->flags |= DWC3_EP_WEDGE;
1404
1405         if (dep->number == 0 || dep->number == 1)
1406                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1407         else
1408                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1409         spin_unlock_irqrestore(&dwc->lock, flags);
1410
1411         return ret;
1412 }
1413
1414 /* -------------------------------------------------------------------------- */
1415
1416 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1417         .bLength        = USB_DT_ENDPOINT_SIZE,
1418         .bDescriptorType = USB_DT_ENDPOINT,
1419         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1420 };
1421
1422 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1423         .enable         = dwc3_gadget_ep0_enable,
1424         .disable        = dwc3_gadget_ep0_disable,
1425         .alloc_request  = dwc3_gadget_ep_alloc_request,
1426         .free_request   = dwc3_gadget_ep_free_request,
1427         .queue          = dwc3_gadget_ep0_queue,
1428         .dequeue        = dwc3_gadget_ep_dequeue,
1429         .set_halt       = dwc3_gadget_ep0_set_halt,
1430         .set_wedge      = dwc3_gadget_ep_set_wedge,
1431 };
1432
1433 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1434         .enable         = dwc3_gadget_ep_enable,
1435         .disable        = dwc3_gadget_ep_disable,
1436         .alloc_request  = dwc3_gadget_ep_alloc_request,
1437         .free_request   = dwc3_gadget_ep_free_request,
1438         .queue          = dwc3_gadget_ep_queue,
1439         .dequeue        = dwc3_gadget_ep_dequeue,
1440         .set_halt       = dwc3_gadget_ep_set_halt,
1441         .set_wedge      = dwc3_gadget_ep_set_wedge,
1442 };
1443
1444 /* -------------------------------------------------------------------------- */
1445
1446 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1447 {
1448         struct dwc3             *dwc = gadget_to_dwc(g);
1449         u32                     reg;
1450
1451         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1452         return DWC3_DSTS_SOFFN(reg);
1453 }
1454
1455 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1456 {
1457         unsigned long           timeout;
1458
1459         int                     ret;
1460         u32                     reg;
1461
1462         u8                      link_state;
1463         u8                      speed;
1464
1465         /*
1466          * According to the Databook Remote wakeup request should
1467          * be issued only when the device is in early suspend state.
1468          *
1469          * We can check that via USB Link State bits in DSTS register.
1470          */
1471         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1472
1473         speed = reg & DWC3_DSTS_CONNECTSPD;
1474         if (speed == DWC3_DSTS_SUPERSPEED) {
1475                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1476                 return 0;
1477         }
1478
1479         link_state = DWC3_DSTS_USBLNKST(reg);
1480
1481         switch (link_state) {
1482         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1483         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1484                 break;
1485         default:
1486                 dwc3_trace(trace_dwc3_gadget,
1487                                 "can't wakeup from '%s'",
1488                                 dwc3_gadget_link_string(link_state));
1489                 return -EINVAL;
1490         }
1491
1492         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1493         if (ret < 0) {
1494                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1495                 return ret;
1496         }
1497
1498         /* Recent versions do this automatically */
1499         if (dwc->revision < DWC3_REVISION_194A) {
1500                 /* write zeroes to Link Change Request */
1501                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1502                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1503                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1504         }
1505
1506         /* poll until Link State changes to ON */
1507         timeout = jiffies + msecs_to_jiffies(100);
1508
1509         while (!time_after(jiffies, timeout)) {
1510                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1511
1512                 /* in HS, means ON */
1513                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1514                         break;
1515         }
1516
1517         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1518                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1519                 return -EINVAL;
1520         }
1521
1522         return 0;
1523 }
1524
1525 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1526 {
1527         struct dwc3             *dwc = gadget_to_dwc(g);
1528         unsigned long           flags;
1529         int                     ret;
1530
1531         spin_lock_irqsave(&dwc->lock, flags);
1532         ret = __dwc3_gadget_wakeup(dwc);
1533         spin_unlock_irqrestore(&dwc->lock, flags);
1534
1535         return ret;
1536 }
1537
1538 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1539                 int is_selfpowered)
1540 {
1541         struct dwc3             *dwc = gadget_to_dwc(g);
1542         unsigned long           flags;
1543
1544         spin_lock_irqsave(&dwc->lock, flags);
1545         g->is_selfpowered = !!is_selfpowered;
1546         spin_unlock_irqrestore(&dwc->lock, flags);
1547
1548         return 0;
1549 }
1550
1551 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1552 {
1553         u32                     reg;
1554         u32                     timeout = 500;
1555
1556         if (pm_runtime_suspended(dwc->dev))
1557                 return 0;
1558
1559         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1560         if (is_on) {
1561                 if (dwc->revision <= DWC3_REVISION_187A) {
1562                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1563                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1564                 }
1565
1566                 if (dwc->revision >= DWC3_REVISION_194A)
1567                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1568                 reg |= DWC3_DCTL_RUN_STOP;
1569
1570                 if (dwc->has_hibernation)
1571                         reg |= DWC3_DCTL_KEEP_CONNECT;
1572
1573                 dwc->pullups_connected = true;
1574         } else {
1575                 reg &= ~DWC3_DCTL_RUN_STOP;
1576
1577                 if (dwc->has_hibernation && !suspend)
1578                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1579
1580                 dwc->pullups_connected = false;
1581         }
1582
1583         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1584
1585         do {
1586                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1587                 if (is_on) {
1588                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1589                                 break;
1590                 } else {
1591                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1592                                 break;
1593                 }
1594                 timeout--;
1595                 if (!timeout)
1596                         return -ETIMEDOUT;
1597                 udelay(1);
1598         } while (1);
1599
1600         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1601                         dwc->gadget_driver
1602                         ? dwc->gadget_driver->function : "no-function",
1603                         is_on ? "connect" : "disconnect");
1604
1605         return 0;
1606 }
1607
1608 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1609 {
1610         struct dwc3             *dwc = gadget_to_dwc(g);
1611         unsigned long           flags;
1612         int                     ret;
1613
1614         is_on = !!is_on;
1615
1616         spin_lock_irqsave(&dwc->lock, flags);
1617         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1618         spin_unlock_irqrestore(&dwc->lock, flags);
1619
1620         return ret;
1621 }
1622
1623 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1624 {
1625         u32                     reg;
1626
1627         /* Enable all but Start and End of Frame IRQs */
1628         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1629                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1630                         DWC3_DEVTEN_CMDCMPLTEN |
1631                         DWC3_DEVTEN_ERRTICERREN |
1632                         DWC3_DEVTEN_WKUPEVTEN |
1633                         DWC3_DEVTEN_ULSTCNGEN |
1634                         DWC3_DEVTEN_CONNECTDONEEN |
1635                         DWC3_DEVTEN_USBRSTEN |
1636                         DWC3_DEVTEN_DISCONNEVTEN);
1637
1638         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1639 }
1640
1641 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1642 {
1643         /* mask all interrupts */
1644         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1645 }
1646
1647 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1648 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1649
1650 /**
1651  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1652  * dwc: pointer to our context structure
1653  *
1654  * The following looks like complex but it's actually very simple. In order to
1655  * calculate the number of packets we can burst at once on OUT transfers, we're
1656  * gonna use RxFIFO size.
1657  *
1658  * To calculate RxFIFO size we need two numbers:
1659  * MDWIDTH = size, in bits, of the internal memory bus
1660  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1661  *
1662  * Given these two numbers, the formula is simple:
1663  *
1664  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1665  *
1666  * 24 bytes is for 3x SETUP packets
1667  * 16 bytes is a clock domain crossing tolerance
1668  *
1669  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1670  */
1671 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1672 {
1673         u32 ram2_depth;
1674         u32 mdwidth;
1675         u32 nump;
1676         u32 reg;
1677
1678         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1679         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1680
1681         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1682         nump = min_t(u32, nump, 16);
1683
1684         /* update NumP */
1685         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1686         reg &= ~DWC3_DCFG_NUMP_MASK;
1687         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1688         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1689 }
1690
1691 static int __dwc3_gadget_start(struct dwc3 *dwc)
1692 {
1693         struct dwc3_ep          *dep;
1694         int                     ret = 0;
1695         u32                     reg;
1696
1697         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1698         reg &= ~(DWC3_DCFG_SPEED_MASK);
1699
1700         /**
1701          * WORKAROUND: DWC3 revision < 2.20a have an issue
1702          * which would cause metastability state on Run/Stop
1703          * bit if we try to force the IP to USB2-only mode.
1704          *
1705          * Because of that, we cannot configure the IP to any
1706          * speed other than the SuperSpeed
1707          *
1708          * Refers to:
1709          *
1710          * STAR#9000525659: Clock Domain Crossing on DCTL in
1711          * USB 2.0 Mode
1712          */
1713         if (dwc->revision < DWC3_REVISION_220A) {
1714                 reg |= DWC3_DCFG_SUPERSPEED;
1715         } else {
1716                 switch (dwc->maximum_speed) {
1717                 case USB_SPEED_LOW:
1718                         reg |= DWC3_DCFG_LOWSPEED;
1719                         break;
1720                 case USB_SPEED_FULL:
1721                         reg |= DWC3_DCFG_FULLSPEED1;
1722                         break;
1723                 case USB_SPEED_HIGH:
1724                         reg |= DWC3_DCFG_HIGHSPEED;
1725                         break;
1726                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1727                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1728                 default:
1729                         reg |= DWC3_DCFG_SUPERSPEED;
1730                 }
1731         }
1732         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1733
1734         /*
1735          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1736          * field instead of letting dwc3 itself calculate that automatically.
1737          *
1738          * This way, we maximize the chances that we'll be able to get several
1739          * bursts of data without going through any sort of endpoint throttling.
1740          */
1741         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1742         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1743         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1744
1745         dwc3_gadget_setup_nump(dwc);
1746
1747         /* Start with SuperSpeed Default */
1748         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1749
1750         dep = dwc->eps[0];
1751         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1752                         false);
1753         if (ret) {
1754                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1755                 goto err0;
1756         }
1757
1758         dep = dwc->eps[1];
1759         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1760                         false);
1761         if (ret) {
1762                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1763                 goto err1;
1764         }
1765
1766         /* begin to receive SETUP packets */
1767         dwc->ep0state = EP0_SETUP_PHASE;
1768         dwc3_ep0_out_start(dwc);
1769
1770         dwc3_gadget_enable_irq(dwc);
1771
1772         return 0;
1773
1774 err1:
1775         __dwc3_gadget_ep_disable(dwc->eps[0]);
1776
1777 err0:
1778         return ret;
1779 }
1780
1781 static int dwc3_gadget_start(struct usb_gadget *g,
1782                 struct usb_gadget_driver *driver)
1783 {
1784         struct dwc3             *dwc = gadget_to_dwc(g);
1785         unsigned long           flags;
1786         int                     ret = 0;
1787         int                     irq;
1788
1789         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1790         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1791                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1792         if (ret) {
1793                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1794                                 irq, ret);
1795                 goto err0;
1796         }
1797         dwc->irq_gadget = irq;
1798
1799         spin_lock_irqsave(&dwc->lock, flags);
1800         if (dwc->gadget_driver) {
1801                 dev_err(dwc->dev, "%s is already bound to %s\n",
1802                                 dwc->gadget.name,
1803                                 dwc->gadget_driver->driver.name);
1804                 ret = -EBUSY;
1805                 goto err1;
1806         }
1807
1808         dwc->gadget_driver      = driver;
1809
1810         if (pm_runtime_active(dwc->dev))
1811                 __dwc3_gadget_start(dwc);
1812
1813         spin_unlock_irqrestore(&dwc->lock, flags);
1814
1815         return 0;
1816
1817 err1:
1818         spin_unlock_irqrestore(&dwc->lock, flags);
1819         free_irq(irq, dwc);
1820
1821 err0:
1822         return ret;
1823 }
1824
1825 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1826 {
1827         dwc3_gadget_disable_irq(dwc);
1828         __dwc3_gadget_ep_disable(dwc->eps[0]);
1829         __dwc3_gadget_ep_disable(dwc->eps[1]);
1830 }
1831
1832 static int dwc3_gadget_stop(struct usb_gadget *g)
1833 {
1834         struct dwc3             *dwc = gadget_to_dwc(g);
1835         unsigned long           flags;
1836
1837         spin_lock_irqsave(&dwc->lock, flags);
1838         __dwc3_gadget_stop(dwc);
1839         dwc->gadget_driver      = NULL;
1840         spin_unlock_irqrestore(&dwc->lock, flags);
1841
1842         free_irq(dwc->irq_gadget, dwc->ev_buf);
1843
1844         return 0;
1845 }
1846
1847 static const struct usb_gadget_ops dwc3_gadget_ops = {
1848         .get_frame              = dwc3_gadget_get_frame,
1849         .wakeup                 = dwc3_gadget_wakeup,
1850         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1851         .pullup                 = dwc3_gadget_pullup,
1852         .udc_start              = dwc3_gadget_start,
1853         .udc_stop               = dwc3_gadget_stop,
1854 };
1855
1856 /* -------------------------------------------------------------------------- */
1857
1858 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1859                 u8 num, u32 direction)
1860 {
1861         struct dwc3_ep                  *dep;
1862         u8                              i;
1863
1864         for (i = 0; i < num; i++) {
1865                 u8 epnum = (i << 1) | (direction ? 1 : 0);
1866
1867                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1868                 if (!dep)
1869                         return -ENOMEM;
1870
1871                 dep->dwc = dwc;
1872                 dep->number = epnum;
1873                 dep->direction = !!direction;
1874                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1875                 dwc->eps[epnum] = dep;
1876
1877                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1878                                 (epnum & 1) ? "in" : "out");
1879
1880                 dep->endpoint.name = dep->name;
1881                 spin_lock_init(&dep->lock);
1882
1883                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1884
1885                 if (epnum == 0 || epnum == 1) {
1886                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1887                         dep->endpoint.maxburst = 1;
1888                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1889                         if (!epnum)
1890                                 dwc->gadget.ep0 = &dep->endpoint;
1891                 } else {
1892                         int             ret;
1893
1894                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1895                         dep->endpoint.max_streams = 15;
1896                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1897                         list_add_tail(&dep->endpoint.ep_list,
1898                                         &dwc->gadget.ep_list);
1899
1900                         ret = dwc3_alloc_trb_pool(dep);
1901                         if (ret)
1902                                 return ret;
1903                 }
1904
1905                 if (epnum == 0 || epnum == 1) {
1906                         dep->endpoint.caps.type_control = true;
1907                 } else {
1908                         dep->endpoint.caps.type_iso = true;
1909                         dep->endpoint.caps.type_bulk = true;
1910                         dep->endpoint.caps.type_int = true;
1911                 }
1912
1913                 dep->endpoint.caps.dir_in = !!direction;
1914                 dep->endpoint.caps.dir_out = !direction;
1915
1916                 INIT_LIST_HEAD(&dep->pending_list);
1917                 INIT_LIST_HEAD(&dep->started_list);
1918         }
1919
1920         return 0;
1921 }
1922
1923 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1924 {
1925         int                             ret;
1926
1927         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1928
1929         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1930         if (ret < 0) {
1931                 dwc3_trace(trace_dwc3_gadget,
1932                                 "failed to allocate OUT endpoints");
1933                 return ret;
1934         }
1935
1936         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1937         if (ret < 0) {
1938                 dwc3_trace(trace_dwc3_gadget,
1939                                 "failed to allocate IN endpoints");
1940                 return ret;
1941         }
1942
1943         return 0;
1944 }
1945
1946 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1947 {
1948         struct dwc3_ep                  *dep;
1949         u8                              epnum;
1950
1951         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1952                 dep = dwc->eps[epnum];
1953                 if (!dep)
1954                         continue;
1955                 /*
1956                  * Physical endpoints 0 and 1 are special; they form the
1957                  * bi-directional USB endpoint 0.
1958                  *
1959                  * For those two physical endpoints, we don't allocate a TRB
1960                  * pool nor do we add them the endpoints list. Due to that, we
1961                  * shouldn't do these two operations otherwise we would end up
1962                  * with all sorts of bugs when removing dwc3.ko.
1963                  */
1964                 if (epnum != 0 && epnum != 1) {
1965                         dwc3_free_trb_pool(dep);
1966                         list_del(&dep->endpoint.ep_list);
1967                 }
1968
1969                 kfree(dep);
1970         }
1971 }
1972
1973 /* -------------------------------------------------------------------------- */
1974
1975 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1976                 struct dwc3_request *req, struct dwc3_trb *trb,
1977                 const struct dwc3_event_depevt *event, int status)
1978 {
1979         unsigned int            count;
1980         unsigned int            s_pkt = 0;
1981         unsigned int            trb_status;
1982
1983         dep->queued_requests--;
1984         trace_dwc3_complete_trb(dep, trb);
1985
1986         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1987                 /*
1988                  * We continue despite the error. There is not much we
1989                  * can do. If we don't clean it up we loop forever. If
1990                  * we skip the TRB then it gets overwritten after a
1991                  * while since we use them in a ring buffer. A BUG()
1992                  * would help. Lets hope that if this occurs, someone
1993                  * fixes the root cause instead of looking away :)
1994                  */
1995                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1996                                 dep->name, trb);
1997         count = trb->size & DWC3_TRB_SIZE_MASK;
1998
1999         if (dep->direction) {
2000                 if (count) {
2001                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2002                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2003                                 dwc3_trace(trace_dwc3_gadget,
2004                                                 "%s: incomplete IN transfer",
2005                                                 dep->name);
2006                                 /*
2007                                  * If missed isoc occurred and there is
2008                                  * no request queued then issue END
2009                                  * TRANSFER, so that core generates
2010                                  * next xfernotready and we will issue
2011                                  * a fresh START TRANSFER.
2012                                  * If there are still queued request
2013                                  * then wait, do not issue either END
2014                                  * or UPDATE TRANSFER, just attach next
2015                                  * request in pending_list during
2016                                  * giveback.If any future queued request
2017                                  * is successfully transferred then we
2018                                  * will issue UPDATE TRANSFER for all
2019                                  * request in the pending_list.
2020                                  */
2021                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2022                         } else {
2023                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2024                                                 dep->name);
2025                                 status = -ECONNRESET;
2026                         }
2027                 } else {
2028                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2029                 }
2030         } else {
2031                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2032                         s_pkt = 1;
2033         }
2034
2035         /*
2036          * We assume here we will always receive the entire data block
2037          * which we should receive. Meaning, if we program RX to
2038          * receive 4K but we receive only 2K, we assume that's all we
2039          * should receive and we simply bounce the request back to the
2040          * gadget driver for further processing.
2041          */
2042         req->request.actual += req->request.length - count;
2043         if (s_pkt)
2044                 return 1;
2045         if ((event->status & DEPEVT_STATUS_LST) &&
2046                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2047                                 DWC3_TRB_CTRL_HWO)))
2048                 return 1;
2049         if ((event->status & DEPEVT_STATUS_IOC) &&
2050                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2051                 return 1;
2052         return 0;
2053 }
2054
2055 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2056                 const struct dwc3_event_depevt *event, int status)
2057 {
2058         struct dwc3_request     *req;
2059         struct dwc3_trb         *trb;
2060         unsigned int            slot;
2061         unsigned int            i;
2062         int                     ret;
2063
2064         do {
2065                 req = next_request(&dep->started_list);
2066                 if (WARN_ON_ONCE(!req))
2067                         return 1;
2068
2069                 i = 0;
2070                 do {
2071                         slot = req->first_trb_index + i;
2072                         if (slot == DWC3_TRB_NUM - 1)
2073                                 slot++;
2074                         slot %= DWC3_TRB_NUM;
2075                         trb = &dep->trb_pool[slot];
2076
2077                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2078                                         event, status);
2079                         if (ret)
2080                                 break;
2081                 } while (++i < req->request.num_mapped_sgs);
2082
2083                 dwc3_gadget_giveback(dep, req, status);
2084
2085                 if (ret)
2086                         break;
2087         } while (1);
2088
2089         /*
2090          * Our endpoint might get disabled by another thread during
2091          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2092          * early on so DWC3_EP_BUSY flag gets cleared
2093          */
2094         if (!dep->endpoint.desc)
2095                 return 1;
2096
2097         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2098                         list_empty(&dep->started_list)) {
2099                 if (list_empty(&dep->pending_list)) {
2100                         /*
2101                          * If there is no entry in request list then do
2102                          * not issue END TRANSFER now. Just set PENDING
2103                          * flag, so that END TRANSFER is issued when an
2104                          * entry is added into request list.
2105                          */
2106                         dep->flags = DWC3_EP_PENDING_REQUEST;
2107                 } else {
2108                         dwc3_stop_active_transfer(dwc, dep->number, true);
2109                         dep->flags = DWC3_EP_ENABLED;
2110                 }
2111                 return 1;
2112         }
2113
2114         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2115                 if ((event->status & DEPEVT_STATUS_IOC) &&
2116                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2117                         return 0;
2118         return 1;
2119 }
2120
2121 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2122                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2123 {
2124         unsigned                status = 0;
2125         int                     clean_busy;
2126         u32                     is_xfer_complete;
2127
2128         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2129
2130         if (event->status & DEPEVT_STATUS_BUSERR)
2131                 status = -ECONNRESET;
2132
2133         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2134         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2135                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2136                 dep->flags &= ~DWC3_EP_BUSY;
2137
2138         /*
2139          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2140          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2141          */
2142         if (dwc->revision < DWC3_REVISION_183A) {
2143                 u32             reg;
2144                 int             i;
2145
2146                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2147                         dep = dwc->eps[i];
2148
2149                         if (!(dep->flags & DWC3_EP_ENABLED))
2150                                 continue;
2151
2152                         if (!list_empty(&dep->started_list))
2153                                 return;
2154                 }
2155
2156                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2157                 reg |= dwc->u1u2;
2158                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2159
2160                 dwc->u1u2 = 0;
2161         }
2162
2163         /*
2164          * Our endpoint might get disabled by another thread during
2165          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2166          * early on so DWC3_EP_BUSY flag gets cleared
2167          */
2168         if (!dep->endpoint.desc)
2169                 return;
2170
2171         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2172                 int ret;
2173
2174                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2175                 if (!ret || ret == -EBUSY)
2176                         return;
2177         }
2178 }
2179
2180 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2181                 const struct dwc3_event_depevt *event)
2182 {
2183         struct dwc3_ep          *dep;
2184         u8                      epnum = event->endpoint_number;
2185
2186         dep = dwc->eps[epnum];
2187
2188         if (!(dep->flags & DWC3_EP_ENABLED))
2189                 return;
2190
2191         if (epnum == 0 || epnum == 1) {
2192                 dwc3_ep0_interrupt(dwc, event);
2193                 return;
2194         }
2195
2196         switch (event->endpoint_event) {
2197         case DWC3_DEPEVT_XFERCOMPLETE:
2198                 dep->resource_index = 0;
2199
2200                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2201                         dwc3_trace(trace_dwc3_gadget,
2202                                         "%s is an Isochronous endpoint",
2203                                         dep->name);
2204                         return;
2205                 }
2206
2207                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2208                 break;
2209         case DWC3_DEPEVT_XFERINPROGRESS:
2210                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2211                 break;
2212         case DWC3_DEPEVT_XFERNOTREADY:
2213                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2214                         dwc3_gadget_start_isoc(dwc, dep, event);
2215                 } else {
2216                         int active;
2217                         int ret;
2218
2219                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2220
2221                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2222                                         dep->name, active ? "Transfer Active"
2223                                         : "Transfer Not Active");
2224
2225                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2226                         if (!ret || ret == -EBUSY)
2227                                 return;
2228
2229                         dwc3_trace(trace_dwc3_gadget,
2230                                         "%s: failed to kick transfers",
2231                                         dep->name);
2232                 }
2233
2234                 break;
2235         case DWC3_DEPEVT_STREAMEVT:
2236                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2237                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2238                                         dep->name);
2239                         return;
2240                 }
2241
2242                 switch (event->status) {
2243                 case DEPEVT_STREAMEVT_FOUND:
2244                         dwc3_trace(trace_dwc3_gadget,
2245                                         "Stream %d found and started",
2246                                         event->parameters);
2247
2248                         break;
2249                 case DEPEVT_STREAMEVT_NOTFOUND:
2250                         /* FALLTHROUGH */
2251                 default:
2252                         dwc3_trace(trace_dwc3_gadget,
2253                                         "unable to find suitable stream");
2254                 }
2255                 break;
2256         case DWC3_DEPEVT_RXTXFIFOEVT:
2257                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2258                 break;
2259         case DWC3_DEPEVT_EPCMDCMPLT:
2260                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2261                 break;
2262         }
2263 }
2264
2265 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2266 {
2267         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2268                 spin_unlock(&dwc->lock);
2269                 dwc->gadget_driver->disconnect(&dwc->gadget);
2270                 spin_lock(&dwc->lock);
2271         }
2272 }
2273
2274 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2275 {
2276         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2277                 spin_unlock(&dwc->lock);
2278                 dwc->gadget_driver->suspend(&dwc->gadget);
2279                 spin_lock(&dwc->lock);
2280         }
2281 }
2282
2283 static void dwc3_resume_gadget(struct dwc3 *dwc)
2284 {
2285         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2286                 spin_unlock(&dwc->lock);
2287                 dwc->gadget_driver->resume(&dwc->gadget);
2288                 spin_lock(&dwc->lock);
2289         }
2290 }
2291
2292 static void dwc3_reset_gadget(struct dwc3 *dwc)
2293 {
2294         if (!dwc->gadget_driver)
2295                 return;
2296
2297         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2298                 spin_unlock(&dwc->lock);
2299                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2300                 spin_lock(&dwc->lock);
2301         }
2302 }
2303
2304 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2305 {
2306         struct dwc3_ep *dep;
2307         struct dwc3_gadget_ep_cmd_params params;
2308         u32 cmd;
2309         int ret;
2310
2311         dep = dwc->eps[epnum];
2312
2313         if (!dep->resource_index)
2314                 return;
2315
2316         /*
2317          * NOTICE: We are violating what the Databook says about the
2318          * EndTransfer command. Ideally we would _always_ wait for the
2319          * EndTransfer Command Completion IRQ, but that's causing too
2320          * much trouble synchronizing between us and gadget driver.
2321          *
2322          * We have discussed this with the IP Provider and it was
2323          * suggested to giveback all requests here, but give HW some
2324          * extra time to synchronize with the interconnect. We're using
2325          * an arbitrary 100us delay for that.
2326          *
2327          * Note also that a similar handling was tested by Synopsys
2328          * (thanks a lot Paul) and nothing bad has come out of it.
2329          * In short, what we're doing is:
2330          *
2331          * - Issue EndTransfer WITH CMDIOC bit set
2332          * - Wait 100us
2333          */
2334
2335         cmd = DWC3_DEPCMD_ENDTRANSFER;
2336         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2337         cmd |= DWC3_DEPCMD_CMDIOC;
2338         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2339         memset(&params, 0, sizeof(params));
2340         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2341         WARN_ON_ONCE(ret);
2342         dep->resource_index = 0;
2343         dep->flags &= ~DWC3_EP_BUSY;
2344         udelay(100);
2345 }
2346
2347 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2348 {
2349         u32 epnum;
2350
2351         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2352                 struct dwc3_ep *dep;
2353
2354                 dep = dwc->eps[epnum];
2355                 if (!dep)
2356                         continue;
2357
2358                 if (!(dep->flags & DWC3_EP_ENABLED))
2359                         continue;
2360
2361                 dwc3_remove_requests(dwc, dep);
2362         }
2363 }
2364
2365 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2366 {
2367         u32 epnum;
2368
2369         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2370                 struct dwc3_ep *dep;
2371                 int ret;
2372
2373                 dep = dwc->eps[epnum];
2374                 if (!dep)
2375                         continue;
2376
2377                 if (!(dep->flags & DWC3_EP_STALL))
2378                         continue;
2379
2380                 dep->flags &= ~DWC3_EP_STALL;
2381
2382                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2383                 WARN_ON_ONCE(ret);
2384         }
2385 }
2386
2387 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2388 {
2389         int                     reg;
2390
2391         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2392         reg &= ~DWC3_DCTL_INITU1ENA;
2393         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2394
2395         reg &= ~DWC3_DCTL_INITU2ENA;
2396         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2397
2398         dwc3_disconnect_gadget(dwc);
2399
2400         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2401         dwc->setup_packet_pending = false;
2402         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2403
2404         dwc->connected = false;
2405 }
2406
2407 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2408 {
2409         u32                     reg;
2410
2411         dwc->connected = true;
2412
2413         /*
2414          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2415          * would cause a missing Disconnect Event if there's a
2416          * pending Setup Packet in the FIFO.
2417          *
2418          * There's no suggested workaround on the official Bug
2419          * report, which states that "unless the driver/application
2420          * is doing any special handling of a disconnect event,
2421          * there is no functional issue".
2422          *
2423          * Unfortunately, it turns out that we _do_ some special
2424          * handling of a disconnect event, namely complete all
2425          * pending transfers, notify gadget driver of the
2426          * disconnection, and so on.
2427          *
2428          * Our suggested workaround is to follow the Disconnect
2429          * Event steps here, instead, based on a setup_packet_pending
2430          * flag. Such flag gets set whenever we have a SETUP_PENDING
2431          * status for EP0 TRBs and gets cleared on XferComplete for the
2432          * same endpoint.
2433          *
2434          * Refers to:
2435          *
2436          * STAR#9000466709: RTL: Device : Disconnect event not
2437          * generated if setup packet pending in FIFO
2438          */
2439         if (dwc->revision < DWC3_REVISION_188A) {
2440                 if (dwc->setup_packet_pending)
2441                         dwc3_gadget_disconnect_interrupt(dwc);
2442         }
2443
2444         dwc3_reset_gadget(dwc);
2445
2446         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2447         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2448         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2449         dwc->test_mode = false;
2450
2451         dwc3_stop_active_transfers(dwc);
2452         dwc3_clear_stall_all_ep(dwc);
2453
2454         /* Reset device address to zero */
2455         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2456         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2457         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2458 }
2459
2460 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2461 {
2462         u32 reg;
2463         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2464
2465         /*
2466          * We change the clock only at SS but I dunno why I would want to do
2467          * this. Maybe it becomes part of the power saving plan.
2468          */
2469
2470         if (speed != DWC3_DSTS_SUPERSPEED)
2471                 return;
2472
2473         /*
2474          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2475          * each time on Connect Done.
2476          */
2477         if (!usb30_clock)
2478                 return;
2479
2480         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2481         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2482         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2483 }
2484
2485 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2486 {
2487         struct dwc3_ep          *dep;
2488         int                     ret;
2489         u32                     reg;
2490         u8                      speed;
2491
2492         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2493         speed = reg & DWC3_DSTS_CONNECTSPD;
2494         dwc->speed = speed;
2495
2496         dwc3_update_ram_clk_sel(dwc, speed);
2497
2498         switch (speed) {
2499         case DWC3_DSTS_SUPERSPEED:
2500                 /*
2501                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2502                  * would cause a missing USB3 Reset event.
2503                  *
2504                  * In such situations, we should force a USB3 Reset
2505                  * event by calling our dwc3_gadget_reset_interrupt()
2506                  * routine.
2507                  *
2508                  * Refers to:
2509                  *
2510                  * STAR#9000483510: RTL: SS : USB3 reset event may
2511                  * not be generated always when the link enters poll
2512                  */
2513                 if (dwc->revision < DWC3_REVISION_190A)
2514                         dwc3_gadget_reset_interrupt(dwc);
2515
2516                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2517                 dwc->gadget.ep0->maxpacket = 512;
2518                 dwc->gadget.speed = USB_SPEED_SUPER;
2519                 break;
2520         case DWC3_DSTS_HIGHSPEED:
2521                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2522                 dwc->gadget.ep0->maxpacket = 64;
2523                 dwc->gadget.speed = USB_SPEED_HIGH;
2524                 break;
2525         case DWC3_DSTS_FULLSPEED2:
2526         case DWC3_DSTS_FULLSPEED1:
2527                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2528                 dwc->gadget.ep0->maxpacket = 64;
2529                 dwc->gadget.speed = USB_SPEED_FULL;
2530                 break;
2531         case DWC3_DSTS_LOWSPEED:
2532                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2533                 dwc->gadget.ep0->maxpacket = 8;
2534                 dwc->gadget.speed = USB_SPEED_LOW;
2535                 break;
2536         }
2537
2538         /* Enable USB2 LPM Capability */
2539
2540         if ((dwc->revision > DWC3_REVISION_194A) &&
2541             (speed != DWC3_DSTS_SUPERSPEED)) {
2542                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2543                 reg |= DWC3_DCFG_LPM_CAP;
2544                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2545
2546                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2547                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2548
2549                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2550
2551                 /*
2552                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2553                  * DCFG.LPMCap is set, core responses with an ACK and the
2554                  * BESL value in the LPM token is less than or equal to LPM
2555                  * NYET threshold.
2556                  */
2557                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2558                                 && dwc->has_lpm_erratum,
2559                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2560
2561                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2562                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2563
2564                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2565         } else {
2566                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2567                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2568                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2569         }
2570
2571         dep = dwc->eps[0];
2572         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2573                         false);
2574         if (ret) {
2575                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2576                 return;
2577         }
2578
2579         dep = dwc->eps[1];
2580         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2581                         false);
2582         if (ret) {
2583                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2584                 return;
2585         }
2586
2587         /*
2588          * Configure PHY via GUSB3PIPECTLn if required.
2589          *
2590          * Update GTXFIFOSIZn
2591          *
2592          * In both cases reset values should be sufficient.
2593          */
2594 }
2595
2596 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2597 {
2598         /*
2599          * TODO take core out of low power mode when that's
2600          * implemented.
2601          */
2602
2603         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2604                 spin_unlock(&dwc->lock);
2605                 dwc->gadget_driver->resume(&dwc->gadget);
2606                 spin_lock(&dwc->lock);
2607         }
2608 }
2609
2610 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2611                 unsigned int evtinfo)
2612 {
2613         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2614         unsigned int            pwropt;
2615
2616         /*
2617          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2618          * Hibernation mode enabled which would show up when device detects
2619          * host-initiated U3 exit.
2620          *
2621          * In that case, device will generate a Link State Change Interrupt
2622          * from U3 to RESUME which is only necessary if Hibernation is
2623          * configured in.
2624          *
2625          * There are no functional changes due to such spurious event and we
2626          * just need to ignore it.
2627          *
2628          * Refers to:
2629          *
2630          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2631          * operational mode
2632          */
2633         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2634         if ((dwc->revision < DWC3_REVISION_250A) &&
2635                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2636                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2637                                 (next == DWC3_LINK_STATE_RESUME)) {
2638                         dwc3_trace(trace_dwc3_gadget,
2639                                         "ignoring transition U3 -> Resume");
2640                         return;
2641                 }
2642         }
2643
2644         /*
2645          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2646          * on the link partner, the USB session might do multiple entry/exit
2647          * of low power states before a transfer takes place.
2648          *
2649          * Due to this problem, we might experience lower throughput. The
2650          * suggested workaround is to disable DCTL[12:9] bits if we're
2651          * transitioning from U1/U2 to U0 and enable those bits again
2652          * after a transfer completes and there are no pending transfers
2653          * on any of the enabled endpoints.
2654          *
2655          * This is the first half of that workaround.
2656          *
2657          * Refers to:
2658          *
2659          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2660          * core send LGO_Ux entering U0
2661          */
2662         if (dwc->revision < DWC3_REVISION_183A) {
2663                 if (next == DWC3_LINK_STATE_U0) {
2664                         u32     u1u2;
2665                         u32     reg;
2666
2667                         switch (dwc->link_state) {
2668                         case DWC3_LINK_STATE_U1:
2669                         case DWC3_LINK_STATE_U2:
2670                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2671                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2672                                                 | DWC3_DCTL_ACCEPTU2ENA
2673                                                 | DWC3_DCTL_INITU1ENA
2674                                                 | DWC3_DCTL_ACCEPTU1ENA);
2675
2676                                 if (!dwc->u1u2)
2677                                         dwc->u1u2 = reg & u1u2;
2678
2679                                 reg &= ~u1u2;
2680
2681                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2682                                 break;
2683                         default:
2684                                 /* do nothing */
2685                                 break;
2686                         }
2687                 }
2688         }
2689
2690         switch (next) {
2691         case DWC3_LINK_STATE_U1:
2692                 if (dwc->speed == USB_SPEED_SUPER)
2693                         dwc3_suspend_gadget(dwc);
2694                 break;
2695         case DWC3_LINK_STATE_U2:
2696         case DWC3_LINK_STATE_U3:
2697                 dwc3_suspend_gadget(dwc);
2698                 break;
2699         case DWC3_LINK_STATE_RESUME:
2700                 dwc3_resume_gadget(dwc);
2701                 break;
2702         default:
2703                 /* do nothing */
2704                 break;
2705         }
2706
2707         dwc->link_state = next;
2708 }
2709
2710 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2711                 unsigned int evtinfo)
2712 {
2713         unsigned int is_ss = evtinfo & BIT(4);
2714
2715         /**
2716          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2717          * have a known issue which can cause USB CV TD.9.23 to fail
2718          * randomly.
2719          *
2720          * Because of this issue, core could generate bogus hibernation
2721          * events which SW needs to ignore.
2722          *
2723          * Refers to:
2724          *
2725          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2726          * Device Fallback from SuperSpeed
2727          */
2728         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2729                 return;
2730
2731         /* enter hibernation here */
2732 }
2733
2734 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2735                 const struct dwc3_event_devt *event)
2736 {
2737         switch (event->type) {
2738         case DWC3_DEVICE_EVENT_DISCONNECT:
2739                 dwc3_gadget_disconnect_interrupt(dwc);
2740                 break;
2741         case DWC3_DEVICE_EVENT_RESET:
2742                 dwc3_gadget_reset_interrupt(dwc);
2743                 break;
2744         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2745                 dwc3_gadget_conndone_interrupt(dwc);
2746                 break;
2747         case DWC3_DEVICE_EVENT_WAKEUP:
2748                 dwc3_gadget_wakeup_interrupt(dwc);
2749                 break;
2750         case DWC3_DEVICE_EVENT_HIBER_REQ:
2751                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2752                                         "unexpected hibernation event\n"))
2753                         break;
2754
2755                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2756                 break;
2757         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2758                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2759                 break;
2760         case DWC3_DEVICE_EVENT_EOPF:
2761                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2762                 break;
2763         case DWC3_DEVICE_EVENT_SOF:
2764                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2765                 break;
2766         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2767                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2768                 break;
2769         case DWC3_DEVICE_EVENT_CMD_CMPL:
2770                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2771                 break;
2772         case DWC3_DEVICE_EVENT_OVERFLOW:
2773                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2774                 break;
2775         default:
2776                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2777         }
2778 }
2779
2780 static void dwc3_process_event_entry(struct dwc3 *dwc,
2781                 const union dwc3_event *event)
2782 {
2783         trace_dwc3_event(event->raw);
2784
2785         /* Endpoint IRQ, handle it and return early */
2786         if (event->type.is_devspec == 0) {
2787                 /* depevt */
2788                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2789         }
2790
2791         switch (event->type.type) {
2792         case DWC3_EVENT_TYPE_DEV:
2793                 dwc3_gadget_interrupt(dwc, &event->devt);
2794                 break;
2795         /* REVISIT what to do with Carkit and I2C events ? */
2796         default:
2797                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2798         }
2799 }
2800
2801 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2802 {
2803         struct dwc3 *dwc = evt->dwc;
2804         irqreturn_t ret = IRQ_NONE;
2805         int left;
2806         u32 reg;
2807
2808         left = evt->count;
2809
2810         if (!(evt->flags & DWC3_EVENT_PENDING))
2811                 return IRQ_NONE;
2812
2813         while (left > 0) {
2814                 union dwc3_event event;
2815
2816                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2817
2818                 dwc3_process_event_entry(dwc, &event);
2819
2820                 /*
2821                  * FIXME we wrap around correctly to the next entry as
2822                  * almost all entries are 4 bytes in size. There is one
2823                  * entry which has 12 bytes which is a regular entry
2824                  * followed by 8 bytes data. ATM I don't know how
2825                  * things are organized if we get next to the a
2826                  * boundary so I worry about that once we try to handle
2827                  * that.
2828                  */
2829                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2830                 left -= 4;
2831
2832                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2833         }
2834
2835         evt->count = 0;
2836         evt->flags &= ~DWC3_EVENT_PENDING;
2837         ret = IRQ_HANDLED;
2838
2839         /* Unmask interrupt */
2840         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2841         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2842         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2843
2844         return ret;
2845 }
2846
2847 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2848 {
2849         struct dwc3_event_buffer *evt = _evt;
2850         struct dwc3 *dwc = evt->dwc;
2851         unsigned long flags;
2852         irqreturn_t ret = IRQ_NONE;
2853
2854         spin_lock_irqsave(&dwc->lock, flags);
2855         ret = dwc3_process_event_buf(evt);
2856         spin_unlock_irqrestore(&dwc->lock, flags);
2857
2858         return ret;
2859 }
2860
2861 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2862 {
2863         struct dwc3 *dwc = evt->dwc;
2864         u32 count;
2865         u32 reg;
2866
2867         if (pm_runtime_suspended(dwc->dev)) {
2868                 pm_runtime_get(dwc->dev);
2869                 disable_irq_nosync(dwc->irq_gadget);
2870                 dwc->pending_events = true;
2871                 return IRQ_HANDLED;
2872         }
2873
2874         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2875         count &= DWC3_GEVNTCOUNT_MASK;
2876         if (!count)
2877                 return IRQ_NONE;
2878
2879         evt->count = count;
2880         evt->flags |= DWC3_EVENT_PENDING;
2881
2882         /* Mask interrupt */
2883         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2884         reg |= DWC3_GEVNTSIZ_INTMASK;
2885         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2886
2887         return IRQ_WAKE_THREAD;
2888 }
2889
2890 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2891 {
2892         struct dwc3_event_buffer        *evt = _evt;
2893
2894         return dwc3_check_event_buf(evt);
2895 }
2896
2897 /**
2898  * dwc3_gadget_init - Initializes gadget related registers
2899  * @dwc: pointer to our controller context structure
2900  *
2901  * Returns 0 on success otherwise negative errno.
2902  */
2903 int dwc3_gadget_init(struct dwc3 *dwc)
2904 {
2905         int                                     ret;
2906
2907         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2908                         &dwc->ctrl_req_addr, GFP_KERNEL);
2909         if (!dwc->ctrl_req) {
2910                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2911                 ret = -ENOMEM;
2912                 goto err0;
2913         }
2914
2915         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2916                         &dwc->ep0_trb_addr, GFP_KERNEL);
2917         if (!dwc->ep0_trb) {
2918                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2919                 ret = -ENOMEM;
2920                 goto err1;
2921         }
2922
2923         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2924         if (!dwc->setup_buf) {
2925                 ret = -ENOMEM;
2926                 goto err2;
2927         }
2928
2929         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2930                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2931                         GFP_KERNEL);
2932         if (!dwc->ep0_bounce) {
2933                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2934                 ret = -ENOMEM;
2935                 goto err3;
2936         }
2937
2938         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2939         if (!dwc->zlp_buf) {
2940                 ret = -ENOMEM;
2941                 goto err4;
2942         }
2943
2944         dwc->gadget.ops                 = &dwc3_gadget_ops;
2945         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2946         dwc->gadget.sg_supported        = true;
2947         dwc->gadget.name                = "dwc3-gadget";
2948         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2949
2950         /*
2951          * FIXME We might be setting max_speed to <SUPER, however versions
2952          * <2.20a of dwc3 have an issue with metastability (documented
2953          * elsewhere in this driver) which tells us we can't set max speed to
2954          * anything lower than SUPER.
2955          *
2956          * Because gadget.max_speed is only used by composite.c and function
2957          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2958          * to happen so we avoid sending SuperSpeed Capability descriptor
2959          * together with our BOS descriptor as that could confuse host into
2960          * thinking we can handle super speed.
2961          *
2962          * Note that, in fact, we won't even support GetBOS requests when speed
2963          * is less than super speed because we don't have means, yet, to tell
2964          * composite.c that we are USB 2.0 + LPM ECN.
2965          */
2966         if (dwc->revision < DWC3_REVISION_220A)
2967                 dwc3_trace(trace_dwc3_gadget,
2968                                 "Changing max_speed on rev %08x",
2969                                 dwc->revision);
2970
2971         dwc->gadget.max_speed           = dwc->maximum_speed;
2972
2973         /*
2974          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2975          * on ep out.
2976          */
2977         dwc->gadget.quirk_ep_out_aligned_size = true;
2978
2979         /*
2980          * REVISIT: Here we should clear all pending IRQs to be
2981          * sure we're starting from a well known location.
2982          */
2983
2984         ret = dwc3_gadget_init_endpoints(dwc);
2985         if (ret)
2986                 goto err5;
2987
2988         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2989         if (ret) {
2990                 dev_err(dwc->dev, "failed to register udc\n");
2991                 goto err5;
2992         }
2993
2994         return 0;
2995
2996 err5:
2997         kfree(dwc->zlp_buf);
2998
2999 err4:
3000         dwc3_gadget_free_endpoints(dwc);
3001         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3002                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3003
3004 err3:
3005         kfree(dwc->setup_buf);
3006
3007 err2:
3008         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3009                         dwc->ep0_trb, dwc->ep0_trb_addr);
3010
3011 err1:
3012         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3013                         dwc->ctrl_req, dwc->ctrl_req_addr);
3014
3015 err0:
3016         return ret;
3017 }
3018
3019 /* -------------------------------------------------------------------------- */
3020
3021 void dwc3_gadget_exit(struct dwc3 *dwc)
3022 {
3023         usb_del_gadget_udc(&dwc->gadget);
3024
3025         dwc3_gadget_free_endpoints(dwc);
3026
3027         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3028                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3029
3030         kfree(dwc->setup_buf);
3031         kfree(dwc->zlp_buf);
3032
3033         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3034                         dwc->ep0_trb, dwc->ep0_trb_addr);
3035
3036         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3037                         dwc->ctrl_req, dwc->ctrl_req_addr);
3038 }
3039
3040 int dwc3_gadget_suspend(struct dwc3 *dwc)
3041 {
3042         int ret;
3043
3044         if (!dwc->gadget_driver)
3045                 return 0;
3046
3047         ret = dwc3_gadget_run_stop(dwc, false, false);
3048         if (ret < 0)
3049                 return ret;
3050
3051         dwc3_disconnect_gadget(dwc);
3052         __dwc3_gadget_stop(dwc);
3053
3054         return 0;
3055 }
3056
3057 int dwc3_gadget_resume(struct dwc3 *dwc)
3058 {
3059         int                     ret;
3060
3061         if (!dwc->gadget_driver)
3062                 return 0;
3063
3064         ret = __dwc3_gadget_start(dwc);
3065         if (ret < 0)
3066                 goto err0;
3067
3068         ret = dwc3_gadget_run_stop(dwc, true, false);
3069         if (ret < 0)
3070                 goto err1;
3071
3072         return 0;
3073
3074 err1:
3075         __dwc3_gadget_stop(dwc);
3076
3077 err0:
3078         return ret;
3079 }
3080
3081 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3082 {
3083         if (dwc->pending_events) {
3084                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3085                 dwc->pending_events = false;
3086                 enable_irq(dwc->irq_gadget);
3087         }
3088 }