2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will
44 * return 0 on success or -EINVAL if wrong Test Selector
47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
51 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
52 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
66 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
72 * dwc3_gadget_get_link_state - Gets current state of USB Link
73 * @dwc: pointer to our context structure
75 * Caller should take care of locking. This function will
76 * return the link state on success (>= 0) or -ETIMEDOUT.
78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
82 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
84 return DWC3_DSTS_USBLNKST(reg);
88 * dwc3_gadget_set_link_state - Sets USB Link to a particular State
89 * @dwc: pointer to our context structure
90 * @state: the state to put link into
92 * Caller should take care of locking. This function will
93 * return 0 on success or -ETIMEDOUT.
95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
101 * Wait until device controller is ready. Only applies to 1.94a and
104 if (dwc->revision >= DWC3_REVISION_194A) {
106 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
107 if (reg & DWC3_DSTS_DCNRD)
117 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
118 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
120 /* set requested state */
121 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
122 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
125 * The following code is racy when called from dwc3_gadget_wakeup,
126 * and is not needed, at least on newer versions
128 if (dwc->revision >= DWC3_REVISION_194A)
131 /* wait for a change in DSTS */
134 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
136 if (DWC3_DSTS_USBLNKST(reg) == state)
142 dwc3_trace(trace_dwc3_gadget,
143 "link state change request timed out");
149 * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
150 * @dwc: pointer to our context structure
152 * This function will a best effort FIFO allocation in order
153 * to improve FIFO usage and throughput, while still allowing
154 * us to enable as many endpoints as possible.
156 * Keep in mind that this operation will be highly dependent
157 * on the configured size for RAM1 - which contains TxFifo -,
158 * the amount of endpoints enabled on coreConsultant tool, and
159 * the width of the Master Bus.
161 * In the ideal world, we would always be able to satisfy the
162 * following equation:
164 * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
165 * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
167 * Unfortunately, due to many variables that's not always the case.
169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
171 int last_fifo_depth = 0;
177 if (!dwc->needs_fifo_resize)
180 ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
181 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
183 /* MDWIDTH is represented in bits, we need it in bytes */
187 * FIXME For now we will only allocate 1 wMaxPacketSize space
188 * for each enabled endpoint, later patches will come to
189 * improve this algorithm so that we better use the internal
192 for (num = 0; num < dwc->num_in_eps; num++) {
193 /* bit0 indicates direction; 1 means IN ep */
194 struct dwc3_ep *dep = dwc->eps[(num << 1) | 1];
198 if (!(dep->flags & DWC3_EP_ENABLED))
201 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
202 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
206 * REVISIT: the following assumes we will always have enough
207 * space available on the FIFO RAM for all possible use cases.
208 * Make sure that's true somehow and change FIFO allocation
211 * If we have Bulk or Isochronous endpoints, we want
212 * them to be able to be very, very fast. So we're giving
213 * those endpoints a fifo_size which is enough for 3 full
216 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
219 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
221 fifo_size |= (last_fifo_depth << 16);
223 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
224 dep->name, last_fifo_depth, fifo_size & 0xffff);
226 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
228 last_fifo_depth += (fifo_size & 0xffff);
234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
237 struct dwc3 *dwc = dep->dwc;
245 * Skip LINK TRB. We can't use req->trb and check for
246 * DWC3_TRBCTL_LINK_TRB because it points the TRB we
247 * just completed (not the LINK TRB).
249 if (((dep->busy_slot & DWC3_TRB_MASK) ==
251 usb_endpoint_xfer_isoc(dep->endpoint.desc))
253 } while(++i < req->request.num_mapped_sgs);
256 list_del(&req->list);
259 if (req->request.status == -EINPROGRESS)
260 req->request.status = status;
262 if (dwc->ep0_bounced && dep->number == 0)
263 dwc->ep0_bounced = false;
265 usb_gadget_unmap_request(&dwc->gadget, &req->request,
268 trace_dwc3_gadget_giveback(req);
270 spin_unlock(&dwc->lock);
271 usb_gadget_giveback_request(&dep->endpoint, &req->request);
272 spin_lock(&dwc->lock);
275 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
280 trace_dwc3_gadget_generic_cmd(cmd, param);
282 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
283 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
286 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
287 if (!(reg & DWC3_DGCMD_CMDACT)) {
288 dwc3_trace(trace_dwc3_gadget,
289 "Command Complete --> %d",
290 DWC3_DGCMD_STATUS(reg));
291 if (DWC3_DGCMD_STATUS(reg))
297 * We can't sleep here, because it's also called from
302 dwc3_trace(trace_dwc3_gadget,
303 "Command Timed Out");
310 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
311 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
313 struct dwc3_ep *dep = dwc->eps[ep];
317 trace_dwc3_gadget_ep_cmd(dep, cmd, params);
319 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
320 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
321 dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
323 dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
325 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
326 if (!(reg & DWC3_DEPCMD_CMDACT)) {
327 dwc3_trace(trace_dwc3_gadget,
328 "Command Complete --> %d",
329 DWC3_DEPCMD_STATUS(reg));
330 if (DWC3_DEPCMD_STATUS(reg))
336 * We can't sleep here, because it is also called from
341 dwc3_trace(trace_dwc3_gadget,
342 "Command Timed Out");
350 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
351 struct dwc3_trb *trb)
353 u32 offset = (char *) trb - (char *) dep->trb_pool;
355 return dep->trb_pool_dma + offset;
358 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
360 struct dwc3 *dwc = dep->dwc;
365 dep->trb_pool = dma_alloc_coherent(dwc->dev,
366 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
367 &dep->trb_pool_dma, GFP_KERNEL);
368 if (!dep->trb_pool) {
369 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
377 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
379 struct dwc3 *dwc = dep->dwc;
381 dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
382 dep->trb_pool, dep->trb_pool_dma);
384 dep->trb_pool = NULL;
385 dep->trb_pool_dma = 0;
388 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
391 * dwc3_gadget_start_config - Configure EP resources
392 * @dwc: pointer to our controller context structure
393 * @dep: endpoint that is being enabled
395 * The assignment of transfer resources cannot perfectly follow the
396 * data book due to the fact that the controller driver does not have
397 * all knowledge of the configuration in advance. It is given this
398 * information piecemeal by the composite gadget framework after every
399 * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
400 * programming model in this scenario can cause errors. For two
403 * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
404 * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
405 * multiple interfaces.
407 * 2) The databook does not mention doing more DEPXFERCFG for new
408 * endpoint on alt setting (8.1.6).
410 * The following simplified method is used instead:
412 * All hardware endpoints can be assigned a transfer resource and this
413 * setting will stay persistent until either a core reset or
414 * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
415 * do DEPXFERCFG for every hardware endpoint as well. We are
416 * guaranteed that there are as many transfer resources as endpoints.
418 * This function is called for each endpoint when it is being enabled
419 * but is triggered only when called for EP0-out, which always happens
420 * first, and which should only happen in one of the above conditions.
422 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
424 struct dwc3_gadget_ep_cmd_params params;
432 memset(¶ms, 0x00, sizeof(params));
433 cmd = DWC3_DEPCMD_DEPSTARTCFG;
435 ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, ¶ms);
439 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
440 struct dwc3_ep *dep = dwc->eps[i];
445 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
453 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
454 const struct usb_endpoint_descriptor *desc,
455 const struct usb_ss_ep_comp_descriptor *comp_desc,
456 bool ignore, bool restore)
458 struct dwc3_gadget_ep_cmd_params params;
460 memset(¶ms, 0x00, sizeof(params));
462 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
463 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
465 /* Burst size is only needed in SuperSpeed mode */
466 if (dwc->gadget.speed == USB_SPEED_SUPER) {
467 u32 burst = dep->endpoint.maxburst - 1;
469 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
473 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
476 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
477 params.param2 |= dep->saved_state;
480 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
481 | DWC3_DEPCFG_XFER_NOT_READY_EN;
483 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
484 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
485 | DWC3_DEPCFG_STREAM_EVENT_EN;
486 dep->stream_capable = true;
489 if (!usb_endpoint_xfer_control(desc))
490 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
493 * We are doing 1:1 mapping for endpoints, meaning
494 * Physical Endpoints 2 maps to Logical Endpoint 2 and
495 * so on. We consider the direction bit as part of the physical
496 * endpoint number. So USB endpoint 0x81 is 0x03.
498 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
501 * We must use the lower 16 TX FIFOs even though
505 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
507 if (desc->bInterval) {
508 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
509 dep->interval = 1 << (desc->bInterval - 1);
512 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
513 DWC3_DEPCMD_SETEPCONFIG, ¶ms);
516 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
518 struct dwc3_gadget_ep_cmd_params params;
520 memset(¶ms, 0x00, sizeof(params));
522 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
524 return dwc3_send_gadget_ep_cmd(dwc, dep->number,
525 DWC3_DEPCMD_SETTRANSFRESOURCE, ¶ms);
529 * __dwc3_gadget_ep_enable - Initializes a HW endpoint
530 * @dep: endpoint to be initialized
531 * @desc: USB Endpoint Descriptor
533 * Caller should take care of locking
535 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
536 const struct usb_endpoint_descriptor *desc,
537 const struct usb_ss_ep_comp_descriptor *comp_desc,
538 bool ignore, bool restore)
540 struct dwc3 *dwc = dep->dwc;
544 dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
546 if (!(dep->flags & DWC3_EP_ENABLED)) {
547 ret = dwc3_gadget_start_config(dwc, dep);
552 ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
557 if (!(dep->flags & DWC3_EP_ENABLED)) {
558 struct dwc3_trb *trb_st_hw;
559 struct dwc3_trb *trb_link;
561 dep->endpoint.desc = desc;
562 dep->comp_desc = comp_desc;
563 dep->type = usb_endpoint_type(desc);
564 dep->flags |= DWC3_EP_ENABLED;
566 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
567 reg |= DWC3_DALEPENA_EP(dep->number);
568 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
570 if (!usb_endpoint_xfer_isoc(desc))
573 /* Link TRB for ISOC. The HWO bit is never reset */
574 trb_st_hw = &dep->trb_pool[0];
576 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
577 memset(trb_link, 0, sizeof(*trb_link));
579 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
580 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
581 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
582 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
585 switch (usb_endpoint_type(desc)) {
586 case USB_ENDPOINT_XFER_CONTROL:
587 strlcat(dep->name, "-control", sizeof(dep->name));
589 case USB_ENDPOINT_XFER_ISOC:
590 strlcat(dep->name, "-isoc", sizeof(dep->name));
592 case USB_ENDPOINT_XFER_BULK:
593 strlcat(dep->name, "-bulk", sizeof(dep->name));
595 case USB_ENDPOINT_XFER_INT:
596 strlcat(dep->name, "-int", sizeof(dep->name));
599 dev_err(dwc->dev, "invalid endpoint transfer type\n");
605 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
606 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
608 struct dwc3_request *req;
610 if (!list_empty(&dep->req_queued)) {
611 dwc3_stop_active_transfer(dwc, dep->number, true);
613 /* - giveback all requests to gadget driver */
614 while (!list_empty(&dep->req_queued)) {
615 req = next_request(&dep->req_queued);
617 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
621 while (!list_empty(&dep->request_list)) {
622 req = next_request(&dep->request_list);
624 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
629 * __dwc3_gadget_ep_disable - Disables a HW endpoint
630 * @dep: the endpoint to disable
632 * This function also removes requests which are currently processed ny the
633 * hardware and those which are not yet scheduled.
634 * Caller should take care of locking.
636 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
638 struct dwc3 *dwc = dep->dwc;
641 dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
643 dwc3_remove_requests(dwc, dep);
645 /* make sure HW endpoint isn't stalled */
646 if (dep->flags & DWC3_EP_STALL)
647 __dwc3_gadget_ep_set_halt(dep, 0, false);
649 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
650 reg &= ~DWC3_DALEPENA_EP(dep->number);
651 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
653 dep->stream_capable = false;
654 dep->endpoint.desc = NULL;
655 dep->comp_desc = NULL;
659 snprintf(dep->name, sizeof(dep->name), "ep%d%s",
661 (dep->number & 1) ? "in" : "out");
666 /* -------------------------------------------------------------------------- */
668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
669 const struct usb_endpoint_descriptor *desc)
674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
679 /* -------------------------------------------------------------------------- */
681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
682 const struct usb_endpoint_descriptor *desc)
689 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
690 pr_debug("dwc3: invalid parameters\n");
694 if (!desc->wMaxPacketSize) {
695 pr_debug("dwc3: missing wMaxPacketSize\n");
699 dep = to_dwc3_ep(ep);
702 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
703 "%s is already enabled\n",
707 spin_lock_irqsave(&dwc->lock, flags);
708 ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
709 spin_unlock_irqrestore(&dwc->lock, flags);
714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
722 pr_debug("dwc3: invalid parameters\n");
726 dep = to_dwc3_ep(ep);
729 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
730 "%s is already disabled\n",
734 spin_lock_irqsave(&dwc->lock, flags);
735 ret = __dwc3_gadget_ep_disable(dep);
736 spin_unlock_irqrestore(&dwc->lock, flags);
741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
744 struct dwc3_request *req;
745 struct dwc3_ep *dep = to_dwc3_ep(ep);
747 req = kzalloc(sizeof(*req), gfp_flags);
751 req->epnum = dep->number;
754 trace_dwc3_alloc_request(req);
756 return &req->request;
759 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
760 struct usb_request *request)
762 struct dwc3_request *req = to_dwc3_request(request);
764 trace_dwc3_free_request(req);
769 * dwc3_prepare_one_trb - setup one TRB from one request
770 * @dep: endpoint for which this request is prepared
771 * @req: dwc3_request pointer
773 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
774 struct dwc3_request *req, dma_addr_t dma,
775 unsigned length, unsigned last, unsigned chain, unsigned node)
777 struct dwc3_trb *trb;
779 dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
780 dep->name, req, (unsigned long long) dma,
781 length, last ? " last" : "",
782 chain ? " chain" : "");
785 trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
788 dwc3_gadget_move_request_queued(req);
790 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
791 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
795 /* Skip the LINK-TRB on ISOC */
796 if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
797 usb_endpoint_xfer_isoc(dep->endpoint.desc))
800 trb->size = DWC3_TRB_SIZE_LENGTH(length);
801 trb->bpl = lower_32_bits(dma);
802 trb->bph = upper_32_bits(dma);
804 switch (usb_endpoint_type(dep->endpoint.desc)) {
805 case USB_ENDPOINT_XFER_CONTROL:
806 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
809 case USB_ENDPOINT_XFER_ISOC:
811 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
813 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
816 case USB_ENDPOINT_XFER_BULK:
817 case USB_ENDPOINT_XFER_INT:
818 trb->ctrl = DWC3_TRBCTL_NORMAL;
822 * This is only possible with faulty memory because we
823 * checked it already :)
828 if (!req->request.no_interrupt && !chain)
829 trb->ctrl |= DWC3_TRB_CTRL_IOC;
831 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
832 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
833 trb->ctrl |= DWC3_TRB_CTRL_CSP;
835 trb->ctrl |= DWC3_TRB_CTRL_LST;
839 trb->ctrl |= DWC3_TRB_CTRL_CHN;
841 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
842 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
844 trb->ctrl |= DWC3_TRB_CTRL_HWO;
846 trace_dwc3_prepare_trb(dep, trb);
850 * dwc3_prepare_trbs - setup TRBs from requests
851 * @dep: endpoint for which requests are being prepared
852 * @starting: true if the endpoint is idle and no requests are queued.
854 * The function goes through the requests list and sets up TRBs for the
855 * transfers. The function returns once there are no more TRBs available or
856 * it runs out of requests.
858 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
860 struct dwc3_request *req, *n;
863 unsigned int last_one = 0;
865 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
867 /* the first request must not be queued */
868 trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
870 /* Can't wrap around on a non-isoc EP since there's no link TRB */
871 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
872 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
878 * If busy & slot are equal than it is either full or empty. If we are
879 * starting to process requests then we are empty. Otherwise we are
880 * full and don't do anything
885 trbs_left = DWC3_TRB_NUM;
887 * In case we start from scratch, we queue the ISOC requests
888 * starting from slot 1. This is done because we use ring
889 * buffer and have no LST bit to stop us. Instead, we place
890 * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
891 * after the first request so we start at slot 1 and have
892 * 7 requests proceed before we hit the first IOC.
893 * Other transfer types don't use the ring buffer and are
894 * processed from the first TRB until the last one. Since we
895 * don't wrap around we have to start at the beginning.
897 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
906 /* The last TRB is a link TRB, not used for xfer */
907 if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
910 list_for_each_entry_safe(req, n, &dep->request_list, list) {
915 if (req->request.num_mapped_sgs > 0) {
916 struct usb_request *request = &req->request;
917 struct scatterlist *sg = request->sg;
918 struct scatterlist *s;
921 for_each_sg(sg, s, request->num_mapped_sgs, i) {
922 unsigned chain = true;
924 length = sg_dma_len(s);
925 dma = sg_dma_address(s);
927 if (i == (request->num_mapped_sgs - 1) ||
929 if (list_empty(&dep->request_list))
941 dwc3_prepare_one_trb(dep, req, dma, length,
951 dma = req->request.dma;
952 length = req->request.length;
958 /* Is this the last request? */
959 if (list_is_last(&req->list, &dep->request_list))
962 dwc3_prepare_one_trb(dep, req, dma, length,
971 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
974 struct dwc3_gadget_ep_cmd_params params;
975 struct dwc3_request *req;
976 struct dwc3 *dwc = dep->dwc;
980 if (start_new && (dep->flags & DWC3_EP_BUSY)) {
981 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
986 * If we are getting here after a short-out-packet we don't enqueue any
987 * new requests as we try to set the IOC bit only on the last request.
990 if (list_empty(&dep->req_queued))
991 dwc3_prepare_trbs(dep, start_new);
993 /* req points to the first request which will be sent */
994 req = next_request(&dep->req_queued);
996 dwc3_prepare_trbs(dep, start_new);
999 * req points to the first request where HWO changed from 0 to 1
1001 req = next_request(&dep->req_queued);
1004 dep->flags |= DWC3_EP_PENDING_REQUEST;
1008 memset(¶ms, 0, sizeof(params));
1011 params.param0 = upper_32_bits(req->trb_dma);
1012 params.param1 = lower_32_bits(req->trb_dma);
1013 cmd = DWC3_DEPCMD_STARTTRANSFER;
1015 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1018 cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
1022 * FIXME we need to iterate over the list of requests
1023 * here and stop, unmap, free and del each of the linked
1024 * requests instead of what we do now.
1026 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1028 list_del(&req->list);
1032 dep->flags |= DWC3_EP_BUSY;
1035 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1037 WARN_ON_ONCE(!dep->resource_index);
1043 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044 struct dwc3_ep *dep, u32 cur_uf)
1048 if (list_empty(&dep->request_list)) {
1049 dwc3_trace(trace_dwc3_gadget,
1050 "ISOC ep %s run out for requests",
1052 dep->flags |= DWC3_EP_PENDING_REQUEST;
1056 /* 4 micro frames in the future */
1057 uf = cur_uf + dep->interval * 4;
1059 __dwc3_gadget_kick_transfer(dep, uf, 1);
1062 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1067 mask = ~(dep->interval - 1);
1068 cur_uf = event->parameters & mask;
1070 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1073 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1075 struct dwc3 *dwc = dep->dwc;
1078 if (!dep->endpoint.desc) {
1079 dwc3_trace(trace_dwc3_gadget,
1080 "trying to queue request %p to disabled %s\n",
1081 &req->request, dep->endpoint.name);
1085 if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086 &req->request, req->dep->name)) {
1087 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088 &req->request, req->dep->name);
1092 req->request.actual = 0;
1093 req->request.status = -EINPROGRESS;
1094 req->direction = dep->direction;
1095 req->epnum = dep->number;
1097 trace_dwc3_ep_queue(req);
1100 * We only add to our list of requests now and
1101 * start consuming the list once we get XferNotReady
1104 * That way, we avoid doing anything that we don't need
1105 * to do now and defer it until the point we receive a
1106 * particular token from the Host side.
1108 * This will also avoid Host cancelling URBs due to too
1111 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1116 list_add_tail(&req->list, &dep->request_list);
1119 * If there are no pending requests and the endpoint isn't already
1120 * busy, we will just start the request straight away.
1122 * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1123 * little bit faster.
1125 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1126 !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1127 !(dep->flags & DWC3_EP_BUSY)) {
1128 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1133 * There are a few special cases:
1135 * 1. XferNotReady with empty list of requests. We need to kick the
1136 * transfer here in that situation, otherwise we will be NAKing
1137 * forever. If we get XferNotReady before gadget driver has a
1138 * chance to queue a request, we will ACK the IRQ but won't be
1139 * able to receive the data until the next request is queued.
1140 * The following code is handling exactly that.
1143 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1145 * If xfernotready is already elapsed and it is a case
1146 * of isoc transfer, then issue END TRANSFER, so that
1147 * you can receive xfernotready again and can have
1148 * notion of current microframe.
1150 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1151 if (list_empty(&dep->req_queued)) {
1152 dwc3_stop_active_transfer(dwc, dep->number, true);
1153 dep->flags = DWC3_EP_ENABLED;
1158 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1160 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1166 * 2. XferInProgress on Isoc EP with an active transfer. We need to
1167 * kick the transfer here after queuing a request, otherwise the
1168 * core may not see the modified TRB(s).
1170 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1171 (dep->flags & DWC3_EP_BUSY) &&
1172 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1173 WARN_ON_ONCE(!dep->resource_index);
1174 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1180 * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1181 * right away, otherwise host will not know we have streams to be
1184 if (dep->stream_capable)
1185 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1188 if (ret && ret != -EBUSY)
1189 dwc3_trace(trace_dwc3_gadget,
1190 "%s: failed to kick transfers\n",
1198 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1199 struct usb_request *request)
1201 dwc3_gadget_ep_free_request(ep, request);
1204 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1206 struct dwc3_request *req;
1207 struct usb_request *request;
1208 struct usb_ep *ep = &dep->endpoint;
1210 dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1211 request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1215 request->length = 0;
1216 request->buf = dwc->zlp_buf;
1217 request->complete = __dwc3_gadget_ep_zlp_complete;
1219 req = to_dwc3_request(request);
1221 return __dwc3_gadget_ep_queue(dep, req);
1224 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1227 struct dwc3_request *req = to_dwc3_request(request);
1228 struct dwc3_ep *dep = to_dwc3_ep(ep);
1229 struct dwc3 *dwc = dep->dwc;
1231 unsigned long flags;
1235 spin_lock_irqsave(&dwc->lock, flags);
1236 ret = __dwc3_gadget_ep_queue(dep, req);
1239 * Okay, here's the thing, if gadget driver has requested for a ZLP by
1240 * setting request->zero, instead of doing magic, we will just queue an
1241 * extra usb_request ourselves so that it gets handled the same way as
1242 * any other request.
1244 if (ret == 0 && request->zero && request->length &&
1245 (request->length % ep->maxpacket == 0))
1246 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1248 spin_unlock_irqrestore(&dwc->lock, flags);
1253 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1254 struct usb_request *request)
1256 struct dwc3_request *req = to_dwc3_request(request);
1257 struct dwc3_request *r = NULL;
1259 struct dwc3_ep *dep = to_dwc3_ep(ep);
1260 struct dwc3 *dwc = dep->dwc;
1262 unsigned long flags;
1265 trace_dwc3_ep_dequeue(req);
1267 spin_lock_irqsave(&dwc->lock, flags);
1269 list_for_each_entry(r, &dep->request_list, list) {
1275 list_for_each_entry(r, &dep->req_queued, list) {
1280 /* wait until it is processed */
1281 dwc3_stop_active_transfer(dwc, dep->number, true);
1284 dev_err(dwc->dev, "request %p was not queued to %s\n",
1291 /* giveback the request */
1292 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1295 spin_unlock_irqrestore(&dwc->lock, flags);
1300 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1302 struct dwc3_gadget_ep_cmd_params params;
1303 struct dwc3 *dwc = dep->dwc;
1306 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1307 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1311 memset(¶ms, 0x00, sizeof(params));
1314 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1315 (!list_empty(&dep->req_queued) ||
1316 !list_empty(&dep->request_list)))) {
1317 dwc3_trace(trace_dwc3_gadget,
1318 "%s: pending request, cannot halt\n",
1323 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1324 DWC3_DEPCMD_SETSTALL, ¶ms);
1326 dev_err(dwc->dev, "failed to set STALL on %s\n",
1329 dep->flags |= DWC3_EP_STALL;
1331 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1332 DWC3_DEPCMD_CLEARSTALL, ¶ms);
1334 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1337 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1343 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1345 struct dwc3_ep *dep = to_dwc3_ep(ep);
1346 struct dwc3 *dwc = dep->dwc;
1348 unsigned long flags;
1352 spin_lock_irqsave(&dwc->lock, flags);
1353 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1354 spin_unlock_irqrestore(&dwc->lock, flags);
1359 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1361 struct dwc3_ep *dep = to_dwc3_ep(ep);
1362 struct dwc3 *dwc = dep->dwc;
1363 unsigned long flags;
1366 spin_lock_irqsave(&dwc->lock, flags);
1367 dep->flags |= DWC3_EP_WEDGE;
1369 if (dep->number == 0 || dep->number == 1)
1370 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1372 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1373 spin_unlock_irqrestore(&dwc->lock, flags);
1378 /* -------------------------------------------------------------------------- */
1380 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1381 .bLength = USB_DT_ENDPOINT_SIZE,
1382 .bDescriptorType = USB_DT_ENDPOINT,
1383 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1386 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1387 .enable = dwc3_gadget_ep0_enable,
1388 .disable = dwc3_gadget_ep0_disable,
1389 .alloc_request = dwc3_gadget_ep_alloc_request,
1390 .free_request = dwc3_gadget_ep_free_request,
1391 .queue = dwc3_gadget_ep0_queue,
1392 .dequeue = dwc3_gadget_ep_dequeue,
1393 .set_halt = dwc3_gadget_ep0_set_halt,
1394 .set_wedge = dwc3_gadget_ep_set_wedge,
1397 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1398 .enable = dwc3_gadget_ep_enable,
1399 .disable = dwc3_gadget_ep_disable,
1400 .alloc_request = dwc3_gadget_ep_alloc_request,
1401 .free_request = dwc3_gadget_ep_free_request,
1402 .queue = dwc3_gadget_ep_queue,
1403 .dequeue = dwc3_gadget_ep_dequeue,
1404 .set_halt = dwc3_gadget_ep_set_halt,
1405 .set_wedge = dwc3_gadget_ep_set_wedge,
1408 /* -------------------------------------------------------------------------- */
1410 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1412 struct dwc3 *dwc = gadget_to_dwc(g);
1415 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1416 return DWC3_DSTS_SOFFN(reg);
1419 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1421 struct dwc3 *dwc = gadget_to_dwc(g);
1423 unsigned long timeout;
1424 unsigned long flags;
1433 spin_lock_irqsave(&dwc->lock, flags);
1436 * According to the Databook Remote wakeup request should
1437 * be issued only when the device is in early suspend state.
1439 * We can check that via USB Link State bits in DSTS register.
1441 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1443 speed = reg & DWC3_DSTS_CONNECTSPD;
1444 if (speed == DWC3_DSTS_SUPERSPEED) {
1445 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1450 link_state = DWC3_DSTS_USBLNKST(reg);
1452 switch (link_state) {
1453 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1454 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1457 dwc3_trace(trace_dwc3_gadget,
1458 "can't wakeup from '%s'\n",
1459 dwc3_gadget_link_string(link_state));
1464 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1466 dev_err(dwc->dev, "failed to put link in Recovery\n");
1470 /* Recent versions do this automatically */
1471 if (dwc->revision < DWC3_REVISION_194A) {
1472 /* write zeroes to Link Change Request */
1473 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1474 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1475 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1478 /* poll until Link State changes to ON */
1479 timeout = jiffies + msecs_to_jiffies(100);
1481 while (!time_after(jiffies, timeout)) {
1482 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1484 /* in HS, means ON */
1485 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1489 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1490 dev_err(dwc->dev, "failed to send remote wakeup\n");
1495 spin_unlock_irqrestore(&dwc->lock, flags);
1500 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1503 struct dwc3 *dwc = gadget_to_dwc(g);
1504 unsigned long flags;
1506 spin_lock_irqsave(&dwc->lock, flags);
1507 g->is_selfpowered = !!is_selfpowered;
1508 spin_unlock_irqrestore(&dwc->lock, flags);
1513 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1518 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1520 if (dwc->revision <= DWC3_REVISION_187A) {
1521 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1522 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1525 if (dwc->revision >= DWC3_REVISION_194A)
1526 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1527 reg |= DWC3_DCTL_RUN_STOP;
1529 if (dwc->has_hibernation)
1530 reg |= DWC3_DCTL_KEEP_CONNECT;
1532 dwc->pullups_connected = true;
1534 reg &= ~DWC3_DCTL_RUN_STOP;
1536 if (dwc->has_hibernation && !suspend)
1537 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1539 dwc->pullups_connected = false;
1542 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1545 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1547 if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1550 if (reg & DWC3_DSTS_DEVCTRLHLT)
1559 dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1561 ? dwc->gadget_driver->function : "no-function",
1562 is_on ? "connect" : "disconnect");
1567 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1569 struct dwc3 *dwc = gadget_to_dwc(g);
1570 unsigned long flags;
1576 spin_lock_irqsave(&dwc->lock, flags);
1578 dwc->enabled = is_on;
1580 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1582 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE)
1583 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1585 spin_unlock_irqrestore(&dwc->lock, flags);
1590 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1594 /* Enable all but Start and End of Frame IRQs */
1595 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1596 DWC3_DEVTEN_EVNTOVERFLOWEN |
1597 DWC3_DEVTEN_CMDCMPLTEN |
1598 DWC3_DEVTEN_ERRTICERREN |
1599 DWC3_DEVTEN_WKUPEVTEN |
1600 DWC3_DEVTEN_ULSTCNGEN |
1601 DWC3_DEVTEN_CONNECTDONEEN |
1602 DWC3_DEVTEN_USBRSTEN |
1603 DWC3_DEVTEN_DISCONNEVTEN);
1605 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1608 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1610 /* mask all interrupts */
1611 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1614 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1615 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1617 static int dwc3_gadget_start(struct usb_gadget *g,
1618 struct usb_gadget_driver *driver)
1620 struct dwc3 *dwc = gadget_to_dwc(g);
1621 struct dwc3_ep *dep;
1622 unsigned long flags;
1627 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1628 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1629 IRQF_SHARED, "dwc3", dwc);
1631 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1636 spin_lock_irqsave(&dwc->lock, flags);
1638 if (dwc->gadget_driver) {
1639 dev_err(dwc->dev, "%s is already bound to %s\n",
1641 dwc->gadget_driver->driver.name);
1646 dwc->gadget_driver = driver;
1648 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1649 if (DWC3_GCTL_PRTCAP(reg) != DWC3_GCTL_PRTCAP_DEVICE)
1652 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1653 reg &= ~(DWC3_DCFG_SPEED_MASK);
1656 * WORKAROUND: DWC3 revision < 2.20a have an issue
1657 * which would cause metastability state on Run/Stop
1658 * bit if we try to force the IP to USB2-only mode.
1660 * Because of that, we cannot configure the IP to any
1661 * speed other than the SuperSpeed
1665 * STAR#9000525659: Clock Domain Crossing on DCTL in
1668 if (dwc->revision < DWC3_REVISION_220A) {
1669 reg |= DWC3_DCFG_SUPERSPEED;
1671 switch (dwc->maximum_speed) {
1673 reg |= DWC3_DSTS_LOWSPEED;
1675 case USB_SPEED_FULL:
1676 reg |= DWC3_DSTS_FULLSPEED1;
1678 case USB_SPEED_HIGH:
1679 reg |= DWC3_DSTS_HIGHSPEED;
1681 case USB_SPEED_SUPER: /* FALLTHROUGH */
1682 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1684 reg |= DWC3_DSTS_SUPERSPEED;
1687 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1689 /* Start with SuperSpeed Default */
1690 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1693 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1696 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1701 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1704 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1708 /* begin to receive SETUP packets */
1709 dwc->ep0state = EP0_SETUP_PHASE;
1710 dwc3_ep0_out_start(dwc);
1712 dwc3_gadget_enable_irq(dwc);
1715 spin_unlock_irqrestore(&dwc->lock, flags);
1720 __dwc3_gadget_ep_disable(dwc->eps[0]);
1723 dwc->gadget_driver = NULL;
1726 spin_unlock_irqrestore(&dwc->lock, flags);
1734 static int dwc3_gadget_stop(struct usb_gadget *g)
1736 struct dwc3 *dwc = gadget_to_dwc(g);
1737 unsigned long flags;
1741 spin_lock_irqsave(&dwc->lock, flags);
1743 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1745 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE) {
1746 dwc3_gadget_disable_irq(dwc);
1747 __dwc3_gadget_ep_disable(dwc->eps[0]);
1748 __dwc3_gadget_ep_disable(dwc->eps[1]);
1751 dwc->gadget_driver = NULL;
1753 spin_unlock_irqrestore(&dwc->lock, flags);
1755 irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1761 static const struct usb_gadget_ops dwc3_gadget_ops = {
1762 .get_frame = dwc3_gadget_get_frame,
1763 .wakeup = dwc3_gadget_wakeup,
1764 .set_selfpowered = dwc3_gadget_set_selfpowered,
1765 .pullup = dwc3_gadget_pullup,
1766 .udc_start = dwc3_gadget_start,
1767 .udc_stop = dwc3_gadget_stop,
1770 /* -------------------------------------------------------------------------- */
1772 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1773 u8 num, u32 direction)
1775 struct dwc3_ep *dep;
1778 for (i = 0; i < num; i++) {
1779 u8 epnum = (i << 1) | (!!direction);
1781 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1786 dep->number = epnum;
1787 dep->direction = !!direction;
1788 dwc->eps[epnum] = dep;
1790 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1791 (epnum & 1) ? "in" : "out");
1793 dep->endpoint.name = dep->name;
1795 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1797 if (epnum == 0 || epnum == 1) {
1798 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1799 dep->endpoint.maxburst = 1;
1800 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1802 dwc->gadget.ep0 = &dep->endpoint;
1806 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1807 dep->endpoint.max_streams = 15;
1808 dep->endpoint.ops = &dwc3_gadget_ep_ops;
1809 list_add_tail(&dep->endpoint.ep_list,
1810 &dwc->gadget.ep_list);
1812 ret = dwc3_alloc_trb_pool(dep);
1817 if (epnum == 0 || epnum == 1) {
1818 dep->endpoint.caps.type_control = true;
1820 dep->endpoint.caps.type_iso = true;
1821 dep->endpoint.caps.type_bulk = true;
1822 dep->endpoint.caps.type_int = true;
1825 dep->endpoint.caps.dir_in = !!direction;
1826 dep->endpoint.caps.dir_out = !direction;
1828 INIT_LIST_HEAD(&dep->request_list);
1829 INIT_LIST_HEAD(&dep->req_queued);
1835 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1839 INIT_LIST_HEAD(&dwc->gadget.ep_list);
1841 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1843 dwc3_trace(trace_dwc3_gadget,
1844 "failed to allocate OUT endpoints");
1848 ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1850 dwc3_trace(trace_dwc3_gadget,
1851 "failed to allocate IN endpoints");
1858 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1860 struct dwc3_ep *dep;
1863 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1864 dep = dwc->eps[epnum];
1868 * Physical endpoints 0 and 1 are special; they form the
1869 * bi-directional USB endpoint 0.
1871 * For those two physical endpoints, we don't allocate a TRB
1872 * pool nor do we add them the endpoints list. Due to that, we
1873 * shouldn't do these two operations otherwise we would end up
1874 * with all sorts of bugs when removing dwc3.ko.
1876 if (epnum != 0 && epnum != 1) {
1877 dwc3_free_trb_pool(dep);
1878 list_del(&dep->endpoint.ep_list);
1885 /* -------------------------------------------------------------------------- */
1887 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1888 struct dwc3_request *req, struct dwc3_trb *trb,
1889 const struct dwc3_event_depevt *event, int status)
1892 unsigned int s_pkt = 0;
1893 unsigned int trb_status;
1895 trace_dwc3_complete_trb(dep, trb);
1897 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1899 * We continue despite the error. There is not much we
1900 * can do. If we don't clean it up we loop forever. If
1901 * we skip the TRB then it gets overwritten after a
1902 * while since we use them in a ring buffer. A BUG()
1903 * would help. Lets hope that if this occurs, someone
1904 * fixes the root cause instead of looking away :)
1906 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1908 count = trb->size & DWC3_TRB_SIZE_MASK;
1910 if (dep->direction) {
1912 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1913 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1914 dwc3_trace(trace_dwc3_gadget,
1915 "%s: incomplete IN transfer\n",
1918 * If missed isoc occurred and there is
1919 * no request queued then issue END
1920 * TRANSFER, so that core generates
1921 * next xfernotready and we will issue
1922 * a fresh START TRANSFER.
1923 * If there are still queued request
1924 * then wait, do not issue either END
1925 * or UPDATE TRANSFER, just attach next
1926 * request in request_list during
1927 * giveback.If any future queued request
1928 * is successfully transferred then we
1929 * will issue UPDATE TRANSFER for all
1930 * request in the request_list.
1932 dep->flags |= DWC3_EP_MISSED_ISOC;
1934 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1936 status = -ECONNRESET;
1939 dep->flags &= ~DWC3_EP_MISSED_ISOC;
1942 if (count && (event->status & DEPEVT_STATUS_SHORT))
1947 * We assume here we will always receive the entire data block
1948 * which we should receive. Meaning, if we program RX to
1949 * receive 4K but we receive only 2K, we assume that's all we
1950 * should receive and we simply bounce the request back to the
1951 * gadget driver for further processing.
1953 req->request.actual += req->request.length - count;
1956 if ((event->status & DEPEVT_STATUS_LST) &&
1957 (trb->ctrl & (DWC3_TRB_CTRL_LST |
1958 DWC3_TRB_CTRL_HWO)))
1960 if ((event->status & DEPEVT_STATUS_IOC) &&
1961 (trb->ctrl & DWC3_TRB_CTRL_IOC))
1966 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1967 const struct dwc3_event_depevt *event, int status)
1969 struct dwc3_request *req;
1970 struct dwc3_trb *trb;
1976 req = next_request(&dep->req_queued);
1977 if (WARN_ON_ONCE(!req))
1982 slot = req->start_slot + i;
1983 if ((slot == DWC3_TRB_NUM - 1) &&
1984 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1986 slot %= DWC3_TRB_NUM;
1987 trb = &dep->trb_pool[slot];
1989 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1993 } while (++i < req->request.num_mapped_sgs);
1995 dwc3_gadget_giveback(dep, req, status);
2001 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2002 list_empty(&dep->req_queued)) {
2003 if (list_empty(&dep->request_list)) {
2005 * If there is no entry in request list then do
2006 * not issue END TRANSFER now. Just set PENDING
2007 * flag, so that END TRANSFER is issued when an
2008 * entry is added into request list.
2010 dep->flags = DWC3_EP_PENDING_REQUEST;
2012 dwc3_stop_active_transfer(dwc, dep->number, true);
2013 dep->flags = DWC3_EP_ENABLED;
2021 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2022 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2024 unsigned status = 0;
2026 u32 is_xfer_complete;
2028 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2030 if (event->status & DEPEVT_STATUS_BUSERR)
2031 status = -ECONNRESET;
2033 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2034 if (clean_busy && (is_xfer_complete ||
2035 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2036 dep->flags &= ~DWC3_EP_BUSY;
2039 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2040 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2042 if (dwc->revision < DWC3_REVISION_183A) {
2046 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2049 if (!(dep->flags & DWC3_EP_ENABLED))
2052 if (!list_empty(&dep->req_queued))
2056 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2058 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2063 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2066 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2067 if (!ret || ret == -EBUSY)
2072 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2073 const struct dwc3_event_depevt *event)
2075 struct dwc3_ep *dep;
2076 u8 epnum = event->endpoint_number;
2078 dep = dwc->eps[epnum];
2080 if (!(dep->flags & DWC3_EP_ENABLED))
2083 if (epnum == 0 || epnum == 1) {
2084 dwc3_ep0_interrupt(dwc, event);
2088 switch (event->endpoint_event) {
2089 case DWC3_DEPEVT_XFERCOMPLETE:
2090 dep->resource_index = 0;
2092 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2093 dwc3_trace(trace_dwc3_gadget,
2094 "%s is an Isochronous endpoint\n",
2099 dwc3_endpoint_transfer_complete(dwc, dep, event);
2101 case DWC3_DEPEVT_XFERINPROGRESS:
2102 dwc3_endpoint_transfer_complete(dwc, dep, event);
2104 case DWC3_DEPEVT_XFERNOTREADY:
2105 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2106 dwc3_gadget_start_isoc(dwc, dep, event);
2111 active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2113 dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2114 dep->name, active ? "Transfer Active"
2115 : "Transfer Not Active");
2117 ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2118 if (!ret || ret == -EBUSY)
2121 dwc3_trace(trace_dwc3_gadget,
2122 "%s: failed to kick transfers\n",
2127 case DWC3_DEPEVT_STREAMEVT:
2128 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2129 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2134 switch (event->status) {
2135 case DEPEVT_STREAMEVT_FOUND:
2136 dwc3_trace(trace_dwc3_gadget,
2137 "Stream %d found and started",
2141 case DEPEVT_STREAMEVT_NOTFOUND:
2144 dwc3_trace(trace_dwc3_gadget,
2145 "unable to find suitable stream\n");
2148 case DWC3_DEPEVT_RXTXFIFOEVT:
2149 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2151 case DWC3_DEPEVT_EPCMDCMPLT:
2152 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2157 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2159 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2160 spin_unlock(&dwc->lock);
2161 dwc->gadget_driver->disconnect(&dwc->gadget);
2162 spin_lock(&dwc->lock);
2166 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2168 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2169 spin_unlock(&dwc->lock);
2170 dwc->gadget_driver->suspend(&dwc->gadget);
2171 spin_lock(&dwc->lock);
2175 static void dwc3_resume_gadget(struct dwc3 *dwc)
2177 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2178 spin_unlock(&dwc->lock);
2179 dwc->gadget_driver->resume(&dwc->gadget);
2180 spin_lock(&dwc->lock);
2184 static void dwc3_reset_gadget(struct dwc3 *dwc)
2186 if (!dwc->gadget_driver)
2189 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2190 spin_unlock(&dwc->lock);
2191 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2192 spin_lock(&dwc->lock);
2196 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2198 struct dwc3_ep *dep;
2199 struct dwc3_gadget_ep_cmd_params params;
2203 dep = dwc->eps[epnum];
2205 if (!dep->resource_index)
2209 * NOTICE: We are violating what the Databook says about the
2210 * EndTransfer command. Ideally we would _always_ wait for the
2211 * EndTransfer Command Completion IRQ, but that's causing too
2212 * much trouble synchronizing between us and gadget driver.
2214 * We have discussed this with the IP Provider and it was
2215 * suggested to giveback all requests here, but give HW some
2216 * extra time to synchronize with the interconnect. We're using
2217 * an arbitrary 100us delay for that.
2219 * Note also that a similar handling was tested by Synopsys
2220 * (thanks a lot Paul) and nothing bad has come out of it.
2221 * In short, what we're doing is:
2223 * - Issue EndTransfer WITH CMDIOC bit set
2227 cmd = DWC3_DEPCMD_ENDTRANSFER;
2228 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2229 cmd |= DWC3_DEPCMD_CMDIOC;
2230 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2231 memset(¶ms, 0, sizeof(params));
2232 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
2234 dep->resource_index = 0;
2235 dep->flags &= ~DWC3_EP_BUSY;
2239 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2243 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2244 struct dwc3_ep *dep;
2246 dep = dwc->eps[epnum];
2250 if (!(dep->flags & DWC3_EP_ENABLED))
2253 dwc3_remove_requests(dwc, dep);
2257 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2261 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2262 struct dwc3_ep *dep;
2263 struct dwc3_gadget_ep_cmd_params params;
2266 dep = dwc->eps[epnum];
2270 if (!(dep->flags & DWC3_EP_STALL))
2273 dep->flags &= ~DWC3_EP_STALL;
2275 memset(¶ms, 0, sizeof(params));
2276 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2277 DWC3_DEPCMD_CLEARSTALL, ¶ms);
2282 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2286 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2287 reg &= ~DWC3_DCTL_INITU1ENA;
2288 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2290 reg &= ~DWC3_DCTL_INITU2ENA;
2291 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2293 dwc3_disconnect_gadget(dwc);
2295 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2296 dwc->setup_packet_pending = false;
2297 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2300 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2305 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2306 * would cause a missing Disconnect Event if there's a
2307 * pending Setup Packet in the FIFO.
2309 * There's no suggested workaround on the official Bug
2310 * report, which states that "unless the driver/application
2311 * is doing any special handling of a disconnect event,
2312 * there is no functional issue".
2314 * Unfortunately, it turns out that we _do_ some special
2315 * handling of a disconnect event, namely complete all
2316 * pending transfers, notify gadget driver of the
2317 * disconnection, and so on.
2319 * Our suggested workaround is to follow the Disconnect
2320 * Event steps here, instead, based on a setup_packet_pending
2321 * flag. Such flag gets set whenever we have a SETUP_PENDING
2322 * status for EP0 TRBs and gets cleared on XferComplete for the
2327 * STAR#9000466709: RTL: Device : Disconnect event not
2328 * generated if setup packet pending in FIFO
2330 if (dwc->revision < DWC3_REVISION_188A) {
2331 if (dwc->setup_packet_pending)
2332 dwc3_gadget_disconnect_interrupt(dwc);
2335 dwc3_reset_gadget(dwc);
2337 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2338 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2339 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2340 dwc->test_mode = false;
2342 dwc3_stop_active_transfers(dwc);
2343 dwc3_clear_stall_all_ep(dwc);
2345 /* Reset device address to zero */
2346 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2347 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2348 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2351 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2354 u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2357 * We change the clock only at SS but I dunno why I would want to do
2358 * this. Maybe it becomes part of the power saving plan.
2361 if (speed != DWC3_DSTS_SUPERSPEED)
2365 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2366 * each time on Connect Done.
2371 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2372 reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2373 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2376 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2378 struct dwc3_ep *dep;
2383 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2384 speed = reg & DWC3_DSTS_CONNECTSPD;
2387 dwc3_update_ram_clk_sel(dwc, speed);
2390 case DWC3_DCFG_SUPERSPEED:
2392 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2393 * would cause a missing USB3 Reset event.
2395 * In such situations, we should force a USB3 Reset
2396 * event by calling our dwc3_gadget_reset_interrupt()
2401 * STAR#9000483510: RTL: SS : USB3 reset event may
2402 * not be generated always when the link enters poll
2404 if (dwc->revision < DWC3_REVISION_190A)
2405 dwc3_gadget_reset_interrupt(dwc);
2407 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2408 dwc->gadget.ep0->maxpacket = 512;
2409 dwc->gadget.speed = USB_SPEED_SUPER;
2411 case DWC3_DCFG_HIGHSPEED:
2412 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2413 dwc->gadget.ep0->maxpacket = 64;
2414 dwc->gadget.speed = USB_SPEED_HIGH;
2416 case DWC3_DCFG_FULLSPEED2:
2417 case DWC3_DCFG_FULLSPEED1:
2418 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2419 dwc->gadget.ep0->maxpacket = 64;
2420 dwc->gadget.speed = USB_SPEED_FULL;
2422 case DWC3_DCFG_LOWSPEED:
2423 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2424 dwc->gadget.ep0->maxpacket = 8;
2425 dwc->gadget.speed = USB_SPEED_LOW;
2429 /* Enable USB2 LPM Capability */
2431 if ((dwc->revision > DWC3_REVISION_194A)
2432 && (speed != DWC3_DCFG_SUPERSPEED)) {
2433 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2434 reg |= DWC3_DCFG_LPM_CAP;
2435 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2437 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2438 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2440 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2443 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2444 * DCFG.LPMCap is set, core responses with an ACK and the
2445 * BESL value in the LPM token is less than or equal to LPM
2448 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2449 && dwc->has_lpm_erratum,
2450 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2452 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2453 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2455 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2457 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2458 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2459 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2463 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2466 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2471 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2474 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2479 * Configure PHY via GUSB3PIPECTLn if required.
2481 * Update GTXFIFOSIZn
2483 * In both cases reset values should be sufficient.
2487 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2490 * TODO take core out of low power mode when that's
2494 dwc->gadget_driver->resume(&dwc->gadget);
2497 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2498 unsigned int evtinfo)
2500 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2501 unsigned int pwropt;
2504 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2505 * Hibernation mode enabled which would show up when device detects
2506 * host-initiated U3 exit.
2508 * In that case, device will generate a Link State Change Interrupt
2509 * from U3 to RESUME which is only necessary if Hibernation is
2512 * There are no functional changes due to such spurious event and we
2513 * just need to ignore it.
2517 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2520 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2521 if ((dwc->revision < DWC3_REVISION_250A) &&
2522 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2523 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2524 (next == DWC3_LINK_STATE_RESUME)) {
2525 dwc3_trace(trace_dwc3_gadget,
2526 "ignoring transition U3 -> Resume");
2532 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2533 * on the link partner, the USB session might do multiple entry/exit
2534 * of low power states before a transfer takes place.
2536 * Due to this problem, we might experience lower throughput. The
2537 * suggested workaround is to disable DCTL[12:9] bits if we're
2538 * transitioning from U1/U2 to U0 and enable those bits again
2539 * after a transfer completes and there are no pending transfers
2540 * on any of the enabled endpoints.
2542 * This is the first half of that workaround.
2546 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2547 * core send LGO_Ux entering U0
2549 if (dwc->revision < DWC3_REVISION_183A) {
2550 if (next == DWC3_LINK_STATE_U0) {
2554 switch (dwc->link_state) {
2555 case DWC3_LINK_STATE_U1:
2556 case DWC3_LINK_STATE_U2:
2557 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2558 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2559 | DWC3_DCTL_ACCEPTU2ENA
2560 | DWC3_DCTL_INITU1ENA
2561 | DWC3_DCTL_ACCEPTU1ENA);
2564 dwc->u1u2 = reg & u1u2;
2568 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2578 case DWC3_LINK_STATE_U1:
2579 if (dwc->speed == USB_SPEED_SUPER)
2580 dwc3_suspend_gadget(dwc);
2582 case DWC3_LINK_STATE_U2:
2583 case DWC3_LINK_STATE_U3:
2584 dwc3_suspend_gadget(dwc);
2586 case DWC3_LINK_STATE_RESUME:
2587 dwc3_resume_gadget(dwc);
2594 dwc->link_state = next;
2597 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2598 unsigned int evtinfo)
2600 unsigned int is_ss = evtinfo & BIT(4);
2603 * WORKAROUND: DWC3 revison 2.20a with hibernation support
2604 * have a known issue which can cause USB CV TD.9.23 to fail
2607 * Because of this issue, core could generate bogus hibernation
2608 * events which SW needs to ignore.
2612 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2613 * Device Fallback from SuperSpeed
2615 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2618 /* enter hibernation here */
2621 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2622 const struct dwc3_event_devt *event)
2624 switch (event->type) {
2625 case DWC3_DEVICE_EVENT_DISCONNECT:
2626 dwc3_gadget_disconnect_interrupt(dwc);
2628 case DWC3_DEVICE_EVENT_RESET:
2629 dwc3_gadget_reset_interrupt(dwc);
2631 case DWC3_DEVICE_EVENT_CONNECT_DONE:
2632 dwc3_gadget_conndone_interrupt(dwc);
2634 case DWC3_DEVICE_EVENT_WAKEUP:
2635 dwc3_gadget_wakeup_interrupt(dwc);
2637 case DWC3_DEVICE_EVENT_HIBER_REQ:
2638 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2639 "unexpected hibernation event\n"))
2642 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2644 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2645 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2647 case DWC3_DEVICE_EVENT_EOPF:
2648 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2650 case DWC3_DEVICE_EVENT_SOF:
2651 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2653 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2654 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2656 case DWC3_DEVICE_EVENT_CMD_CMPL:
2657 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2659 case DWC3_DEVICE_EVENT_OVERFLOW:
2660 dwc3_trace(trace_dwc3_gadget, "Overflow");
2663 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2667 static void dwc3_process_event_entry(struct dwc3 *dwc,
2668 const union dwc3_event *event)
2670 trace_dwc3_event(event->raw);
2672 /* Endpoint IRQ, handle it and return early */
2673 if (event->type.is_devspec == 0) {
2675 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2678 switch (event->type.type) {
2679 case DWC3_EVENT_TYPE_DEV:
2680 dwc3_gadget_interrupt(dwc, &event->devt);
2682 /* REVISIT what to do with Carkit and I2C events ? */
2684 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2688 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2690 struct dwc3_event_buffer *evt;
2691 irqreturn_t ret = IRQ_NONE;
2695 evt = dwc->ev_buffs[buf];
2698 if (!(evt->flags & DWC3_EVENT_PENDING))
2702 union dwc3_event event;
2704 event.raw = *(u32 *) (evt->buf + evt->lpos);
2706 dwc3_process_event_entry(dwc, &event);
2709 * FIXME we wrap around correctly to the next entry as
2710 * almost all entries are 4 bytes in size. There is one
2711 * entry which has 12 bytes which is a regular entry
2712 * followed by 8 bytes data. ATM I don't know how
2713 * things are organized if we get next to the a
2714 * boundary so I worry about that once we try to handle
2717 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2720 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2724 evt->flags &= ~DWC3_EVENT_PENDING;
2727 /* Unmask interrupt */
2728 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2729 reg &= ~DWC3_GEVNTSIZ_INTMASK;
2730 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2735 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2737 struct dwc3 *dwc = _dwc;
2738 unsigned long flags;
2739 irqreturn_t ret = IRQ_NONE;
2742 spin_lock_irqsave(&dwc->lock, flags);
2744 for (i = 0; i < dwc->num_event_buffers; i++)
2745 ret |= dwc3_process_event_buf(dwc, i);
2747 spin_unlock_irqrestore(&dwc->lock, flags);
2752 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2754 struct dwc3_event_buffer *evt;
2758 evt = dwc->ev_buffs[buf];
2760 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2761 count &= DWC3_GEVNTCOUNT_MASK;
2766 evt->flags |= DWC3_EVENT_PENDING;
2768 /* Mask interrupt */
2769 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2770 reg |= DWC3_GEVNTSIZ_INTMASK;
2771 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2773 return IRQ_WAKE_THREAD;
2776 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2778 struct dwc3 *dwc = _dwc;
2780 irqreturn_t ret = IRQ_NONE;
2782 for (i = 0; i < dwc->num_event_buffers; i++) {
2785 status = dwc3_check_event_buf(dwc, i);
2786 if (status == IRQ_WAKE_THREAD)
2794 * dwc3_gadget_init - Initializes gadget related registers
2795 * @dwc: pointer to our controller context structure
2797 * Returns 0 on success otherwise negative errno.
2799 int dwc3_gadget_init(struct dwc3 *dwc)
2803 dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2804 &dwc->ctrl_req_addr, GFP_KERNEL);
2805 if (!dwc->ctrl_req) {
2806 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2811 dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2812 &dwc->ep0_trb_addr, GFP_KERNEL);
2813 if (!dwc->ep0_trb) {
2814 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2819 dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2820 if (!dwc->setup_buf) {
2825 dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2826 DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2828 if (!dwc->ep0_bounce) {
2829 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2834 dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2835 if (!dwc->zlp_buf) {
2840 dwc->gadget.ops = &dwc3_gadget_ops;
2841 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2842 dwc->gadget.sg_supported = true;
2843 dwc->gadget.name = "dwc3-gadget";
2844 dwc->gadget.is_otg = dwc->dr_mode == USB_DR_MODE_OTG;
2847 * FIXME We might be setting max_speed to <SUPER, however versions
2848 * <2.20a of dwc3 have an issue with metastability (documented
2849 * elsewhere in this driver) which tells us we can't set max speed to
2850 * anything lower than SUPER.
2852 * Because gadget.max_speed is only used by composite.c and function
2853 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2854 * to happen so we avoid sending SuperSpeed Capability descriptor
2855 * together with our BOS descriptor as that could confuse host into
2856 * thinking we can handle super speed.
2858 * Note that, in fact, we won't even support GetBOS requests when speed
2859 * is less than super speed because we don't have means, yet, to tell
2860 * composite.c that we are USB 2.0 + LPM ECN.
2862 if (dwc->revision < DWC3_REVISION_220A)
2863 dwc3_trace(trace_dwc3_gadget,
2864 "Changing max_speed on rev %08x\n",
2867 dwc->gadget.max_speed = dwc->maximum_speed;
2870 * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2873 dwc->gadget.quirk_ep_out_aligned_size = true;
2876 * REVISIT: Here we should clear all pending IRQs to be
2877 * sure we're starting from a well known location.
2880 ret = dwc3_gadget_init_endpoints(dwc);
2884 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2886 dev_err(dwc->dev, "failed to register udc\n");
2893 kfree(dwc->zlp_buf);
2896 dwc3_gadget_free_endpoints(dwc);
2897 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2898 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2901 kfree(dwc->setup_buf);
2904 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2905 dwc->ep0_trb, dwc->ep0_trb_addr);
2908 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2909 dwc->ctrl_req, dwc->ctrl_req_addr);
2915 /* -------------------------------------------------------------------------- */
2917 void dwc3_gadget_exit(struct dwc3 *dwc)
2919 usb_del_gadget_udc(&dwc->gadget);
2921 dwc3_gadget_free_endpoints(dwc);
2923 dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2924 dwc->ep0_bounce, dwc->ep0_bounce_addr);
2926 kfree(dwc->setup_buf);
2927 kfree(dwc->zlp_buf);
2929 dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2930 dwc->ep0_trb, dwc->ep0_trb_addr);
2932 dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2933 dwc->ctrl_req, dwc->ctrl_req_addr);
2936 int dwc3_gadget_suspend(struct dwc3 *dwc)
2938 if (dwc->pullups_connected) {
2939 dwc3_gadget_disable_irq(dwc);
2940 dwc3_gadget_run_stop(dwc, true, true);
2943 __dwc3_gadget_ep_disable(dwc->eps[0]);
2944 __dwc3_gadget_ep_disable(dwc->eps[1]);
2946 dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2951 int dwc3_gadget_resume(struct dwc3 *dwc)
2953 struct dwc3_ep *dep;
2956 /* Start with SuperSpeed Default */
2957 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2960 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2966 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2971 /* begin to receive SETUP packets */
2972 dwc->ep0state = EP0_SETUP_PHASE;
2973 dwc3_ep0_out_start(dwc);
2975 dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2977 if (dwc->pullups_connected) {
2978 dwc3_gadget_enable_irq(dwc);
2979 dwc3_gadget_run_stop(dwc, true, false);
2985 __dwc3_gadget_ep_disable(dwc->eps[0]);
2991 static int dwc3_gadget_reinit(struct dwc3 *dwc)
2993 u32 hwparams4 = dwc->hwparams.hwparams4;
2996 struct dwc3_ep *dep = NULL;
2998 reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
2999 /* This should read as U3 followed by revision number */
3000 if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
3001 /* Detected DWC_usb3 IP */
3002 dwc->revision = reg;
3003 } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
3004 /* Detected DWC_usb31 IP */
3005 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
3006 dwc->revision |= DWC3_REVISION_IS_DWC31;
3008 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
3014 * Write Linux Version Code to our GUID register so it's easy to figure
3015 * out which kernel version a bug was found.
3017 dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
3019 /* Handle USB2.0-only core configuration */
3020 if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
3021 DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
3022 if (dwc->maximum_speed == USB_SPEED_SUPER)
3023 dwc->maximum_speed = USB_SPEED_HIGH;
3026 /* issue device SoftReset too */
3027 ret = dwc3_soft_reset(dwc);
3031 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
3032 reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
3034 switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
3035 case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
3037 * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
3038 * issue which would cause xHCI compliance tests to fail.
3040 * Because of that we cannot enable clock gating on such
3045 * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
3048 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
3049 dwc->dr_mode == USB_DR_MODE_OTG) &&
3050 (dwc->revision >= DWC3_REVISION_210A &&
3051 dwc->revision <= DWC3_REVISION_250A))
3052 reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
3054 reg &= ~DWC3_GCTL_DSBLCLKGTNG;
3056 case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
3057 /* enable hibernation here */
3058 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
3061 * REVISIT Enabling this bit so that host-mode hibernation
3062 * will work. Device-mode hibernation is not yet implemented.
3064 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
3067 dwc3_trace(trace_dwc3_core,
3068 "No power optimization available\n");
3071 /* check if current dwc3 is on simulation board */
3072 if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
3073 dwc3_trace(trace_dwc3_core,
3074 "running on FPGA platform\n");
3075 dwc->is_fpga = true;
3078 WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
3079 "disable_scramble cannot be used on non-FPGA builds\n");
3081 if (dwc->disable_scramble_quirk && dwc->is_fpga)
3082 reg |= DWC3_GCTL_DISSCRAMBLE;
3084 reg &= ~DWC3_GCTL_DISSCRAMBLE;
3086 if (dwc->u2exit_lfps_quirk)
3087 reg |= DWC3_GCTL_U2EXIT_LFPS;
3090 * WORKAROUND: DWC3 revisions <1.90a have a bug
3091 * where the device can fail to connect at SuperSpeed
3092 * and falls back to high-speed mode which causes
3093 * the device to enter a Connect/Disconnect loop
3095 if (dwc->revision < DWC3_REVISION_190A)
3096 reg |= DWC3_GCTL_U2RSTECN;
3097 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
3099 ret = dwc3_event_buffers_setup(dwc);
3102 dev_err(dwc->dev, "failed to setup event buffers\n");
3106 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
3107 reg |= DWC3_DCFG_LPM_CAP;
3108 reg &= ~(DWC3_DCFG_SPEED_MASK);
3111 * WORKAROUND: DWC3 revision < 2.20a have an issue
3112 * which would cause metastability state on Run/Stop
3113 * bit if we try to force the IP to USB2-only mode.
3115 * Because of that, we cannot configure the IP to any
3116 * speed other than the SuperSpeed
3120 * STAR#9000525659: Clock Domain Crossing on DCTL in
3123 if (dwc->revision < DWC3_REVISION_220A) {
3124 reg |= DWC3_DCFG_SUPERSPEED;
3126 switch (dwc->maximum_speed) {
3128 reg |= DWC3_DSTS_LOWSPEED;
3130 case USB_SPEED_FULL:
3131 reg |= DWC3_DSTS_FULLSPEED1;
3133 case USB_SPEED_HIGH:
3134 reg |= DWC3_DSTS_HIGHSPEED;
3136 case USB_SPEED_SUPER: /* FALLTHROUGH */
3137 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
3139 reg |= DWC3_DSTS_SUPERSPEED;
3142 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
3144 /* Start with SuperSpeed Default */
3145 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
3148 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
3151 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3156 ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
3159 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
3163 /* begin to receive SETUP packets */
3164 dwc->ep0state = EP0_SETUP_PHASE;
3165 dwc3_ep0_out_start(dwc);
3169 __dwc3_gadget_ep_disable(dwc->eps[0]);
3171 dwc3_event_buffers_cleanup(dwc);
3176 int dwc3_gadget_restart(struct dwc3 *dwc, bool start)
3178 struct dwc3_event_buffer *evt;
3184 ret = dwc3_gadget_reinit(dwc);
3187 "dwc3 gadget reinit error = %d\n", ret);
3192 ret = dwc3_gadget_run_stop(dwc, start, false);
3195 "dwc3 gadget run stop err = %d\n", ret);
3199 dwc3_gadget_enable_irq(dwc);
3202 * Per databook, DEVCTRLHLT bit setting requires
3203 * interrupts to be acknowledged. so acknowledge
3204 * the events that are generated (by writing to
3205 * GEVNTCOUNTn) first. And we also mask interrupts
3206 * and clear SW states to avoid generating other
3207 * interrupts after do gadget disconnnect operation.
3209 dwc3_gadget_disable_irq(dwc);
3211 for (i = 0; i < dwc->num_event_buffers; i++) {
3212 evt = dwc->ev_buffs[i];
3214 evt->flags &= ~DWC3_EVENT_PENDING;
3215 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(i));
3216 reg |= DWC3_GEVNTSIZ_INTMASK;
3217 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(i), reg);
3218 reg = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(i));
3219 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(i), reg);
3223 * DEVCTRLHLT bit sometimes does not get set
3224 * even when GEVNTCOUNT is acked so do not
3225 * care run stop function return value.
3227 dwc3_gadget_run_stop(dwc, start, false);
3229 if (dwc->gadget.state != USB_STATE_NOTATTACHED)
3230 dwc3_gadget_disconnect_interrupt(dwc);
3232 __dwc3_gadget_ep_disable(dwc->eps[0]);
3233 __dwc3_gadget_ep_disable(dwc->eps[1]);