drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 149 {
 150         dep->trb_enqueue++;
 151         dep->trb_enqueue %= DWC3_TRB_NUM;
 152 }
 153
 154 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 155 {
 156         dep->trb_dequeue++;
 157         dep->trb_dequeue %= DWC3_TRB_NUM;
 158 }
 159
 160 static int dwc3_ep_is_last_trb(unsigned int index)
 161 {
 162         return index == DWC3_TRB_NUM - 1;
 163 }
 164
 165 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 166                 int status)
 167 {
 168         struct dwc3                     *dwc = dep->dwc;
 169         int                             i;
 170
 171         if (req->started) {
 172                 i = 0;
 173                 do {
 174                         dwc3_ep_inc_deq(dep);
 175                         /*
 176                          * Skip LINK TRB. We can't use req->trb and check for
 177                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 178                          * just completed (not the LINK TRB).
 179                          */
 180                         if (dwc3_ep_is_last_trb(dep->trb_dequeue))
 181                                 dwc3_ep_inc_deq(dep);
 182                 } while(++i < req->request.num_mapped_sgs);
 183                 req->started = false;
 184         }
 185         list_del(&req->list);
 186         req->trb = NULL;
 187
 188         if (req->request.status == -EINPROGRESS)
 189                 req->request.status = status;
 190
 191         if (dwc->ep0_bounced && dep->number == 0)
 192                 dwc->ep0_bounced = false;
 193         else
 194                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 195                                 req->direction);
 196
 197         trace_dwc3_gadget_giveback(req);
 198
 199         spin_unlock(&dwc->lock);
 200         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 201         spin_lock(&dwc->lock);
 202 }
 203
 204 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 205 {
 206         u32             timeout = 500;
 207         u32             reg;
 208
 209         trace_dwc3_gadget_generic_cmd(cmd, param);
 210
 211         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 212         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 213
 214         do {
 215                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 216                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 217                         dwc3_trace(trace_dwc3_gadget,
 218                                         "Command Complete --> %d",
 219                                         DWC3_DGCMD_STATUS(reg));
 220                         if (DWC3_DGCMD_STATUS(reg))
 221                                 return -EINVAL;
 222                         return 0;
 223                 }
 224
 225                 /*
 226                  * We can't sleep here, because it's also called from
 227                  * interrupt context.
 228                  */
 229                 timeout--;
 230                 if (!timeout) {
 231                         dwc3_trace(trace_dwc3_gadget,
 232                                         "Command Timed Out");
 233                         return -ETIMEDOUT;
 234                 }
 235                 udelay(1);
 236         } while (1);
 237 }
 238
 239 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 240
 241 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 242                 struct dwc3_gadget_ep_cmd_params *params)
 243 {
 244         struct dwc3             *dwc = dep->dwc;
 245         u32                     timeout = 500;
 246         u32                     reg;
 247
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 252
 253         /*
 254          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 255          * we're issuing an endpoint command, we must check if
 256          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 257          *
 258          * We will also set SUSPHY bit to what it was before returning as stated
 259          * by the same section on Synopsys databook.
 260          */
 261         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 262                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 263                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 264                         susphy = true;
 265                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 266                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 267                 }
 268         }
 269
 270         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 271                 int             needs_wakeup;
 272
 273                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 274                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 275                                 dwc->link_state == DWC3_LINK_STATE_U3);
 276
 277                 if (unlikely(needs_wakeup)) {
 278                         ret = __dwc3_gadget_wakeup(dwc);
 279                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 280                                         ret);
 281                 }
 282         }
 283
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 285         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 286         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 287
 288         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 289         do {
 290                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 291                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 292                         int cmd_status = DWC3_DEPCMD_STATUS(reg);
 293
 294                         dwc3_trace(trace_dwc3_gadget,
 295                                         "Command Complete --> %d",
 296                                         cmd_status);
 297
 298                         switch (cmd_status) {
 299                         case 0:
 300                                 ret = 0;
 301                                 break;
 302                         case DEPEVT_TRANSFER_NO_RESOURCE:
 303                                 dwc3_trace(trace_dwc3_gadget, "%s: no resource available");
 304                                 ret = -EINVAL;
 305                                 break;
 306                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 307                                 /*
 308                                  * SW issues START TRANSFER command to
 309                                  * isochronous ep with future frame interval. If
 310                                  * future interval time has already passed when
 311                                  * core receives the command, it will respond
 312                                  * with an error status of 'Bus Expiry'.
 313                                  *
 314                                  * Instead of always returning -EINVAL, let's
 315                                  * give a hint to the gadget driver that this is
 316                                  * the case by returning -EAGAIN.
 317                                  */
 318                                 dwc3_trace(trace_dwc3_gadget, "%s: bus expiry");
 319                                 ret = -EAGAIN;
 320                                 break;
 321                         default:
 322                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 323                         }
 324
 325                         break;
 326                 }
 327
 328                 /*
 329                  * We can't sleep here, because it is also called from
 330                  * interrupt context.
 331                  */
 332                 timeout--;
 333                 if (!timeout) {
 334                         dwc3_trace(trace_dwc3_gadget,
 335                                         "Command Timed Out");
 336                         ret = -ETIMEDOUT;
 337                         break;
 338                 }
 339         } while (1);
 340
 341         if (unlikely(susphy)) {
 342                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 343                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 344                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 345         }
 346
 347         return ret;
 348 }
 349
 350 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 351 {
 352         struct dwc3 *dwc = dep->dwc;
 353         struct dwc3_gadget_ep_cmd_params params;
 354         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 355
 356         /*
 357          * As of core revision 2.60a the recommended programming model
 358          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 359          * command for IN endpoints. This is to prevent an issue where
 360          * some (non-compliant) hosts may not send ACK TPs for pending
 361          * IN transfers due to a mishandled error condition. Synopsys
 362          * STAR 9000614252.
 363          */
 364         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 365                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 366
 367         memset(&params, 0, sizeof(params));
 368
 369         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 370 }
 371
 372 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 373                 struct dwc3_trb *trb)
 374 {
 375         u32             offset = (char *) trb - (char *) dep->trb_pool;
 376
 377         return dep->trb_pool_dma + offset;
 378 }
 379
 380 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 381 {
 382         struct dwc3             *dwc = dep->dwc;
 383
 384         if (dep->trb_pool)
 385                 return 0;
 386
 387         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 388                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 389                         &dep->trb_pool_dma, GFP_KERNEL);
 390         if (!dep->trb_pool) {
 391                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 392                                 dep->name);
 393                 return -ENOMEM;
 394         }
 395
 396         return 0;
 397 }
 398
 399 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 400 {
 401         struct dwc3             *dwc = dep->dwc;
 402
 403         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 404                         dep->trb_pool, dep->trb_pool_dma);
 405
 406         dep->trb_pool = NULL;
 407         dep->trb_pool_dma = 0;
 408 }
 409
 410 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 411
 412 /**
 413  * dwc3_gadget_start_config - Configure EP resources
 414  * @dwc: pointer to our controller context structure
 415  * @dep: endpoint that is being enabled
 416  *
 417  * The assignment of transfer resources cannot perfectly follow the
 418  * data book due to the fact that the controller driver does not have
 419  * all knowledge of the configuration in advance. It is given this
 420  * information piecemeal by the composite gadget framework after every
 421  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 422  * programming model in this scenario can cause errors. For two
 423  * reasons:
 424  *
 425  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 426  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 427  * multiple interfaces.
 428  *
 429  * 2) The databook does not mention doing more DEPXFERCFG for new
 430  * endpoint on alt setting (8.1.6).
 431  *
 432  * The following simplified method is used instead:
 433  *
 434  * All hardware endpoints can be assigned a transfer resource and this
 435  * setting will stay persistent until either a core reset or
 436  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 437  * do DEPXFERCFG for every hardware endpoint as well. We are
 438  * guaranteed that there are as many transfer resources as endpoints.
 439  *
 440  * This function is called for each endpoint when it is being enabled
 441  * but is triggered only when called for EP0-out, which always happens
 442  * first, and which should only happen in one of the above conditions.
 443  */
 444 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 445 {
 446         struct dwc3_gadget_ep_cmd_params params;
 447         u32                     cmd;
 448         int                     i;
 449         int                     ret;
 450
 451         if (dep->number)
 452                 return 0;
 453
 454         memset(&params, 0x00, sizeof(params));
 455         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 456
 457         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 458         if (ret)
 459                 return ret;
 460
 461         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 462                 struct dwc3_ep *dep = dwc->eps[i];
 463
 464                 if (!dep)
 465                         continue;
 466
 467                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 476                 const struct usb_endpoint_descriptor *desc,
 477                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 478                 bool ignore, bool restore)
 479 {
 480         struct dwc3_gadget_ep_cmd_params params;
 481
 482         memset(&params, 0x00, sizeof(params));
 483
 484         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 485                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 486
 487         /* Burst size is only needed in SuperSpeed mode */
 488         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 489                 u32 burst = dep->endpoint.maxburst;
 490                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 491         }
 492
 493         if (ignore)
 494                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 495
 496         if (restore) {
 497                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 498                 params.param2 |= dep->saved_state;
 499         }
 500
 501         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 502                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 503
 504         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 505                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 506                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 507                 dep->stream_capable = true;
 508         }
 509
 510         if (!usb_endpoint_xfer_control(desc))
 511                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 512
 513         /*
 514          * We are doing 1:1 mapping for endpoints, meaning
 515          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 516          * so on. We consider the direction bit as part of the physical
 517          * endpoint number. So USB endpoint 0x81 is 0x03.
 518          */
 519         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 520
 521         /*
 522          * We must use the lower 16 TX FIFOs even though
 523          * HW might have more
 524          */
 525         if (dep->direction)
 526                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 527
 528         if (desc->bInterval) {
 529                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 530                 dep->interval = 1 << (desc->bInterval - 1);
 531         }
 532
 533         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 534 }
 535
 536 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 537 {
 538         struct dwc3_gadget_ep_cmd_params params;
 539
 540         memset(&params, 0x00, sizeof(params));
 541
 542         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 543
 544         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 545                         &params);
 546 }
 547
 548 /**
 549  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 550  * @dep: endpoint to be initialized
 551  * @desc: USB Endpoint Descriptor
 552  *
 553  * Caller should take care of locking
 554  */
 555 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 556                 const struct usb_endpoint_descriptor *desc,
 557                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 558                 bool ignore, bool restore)
 559 {
 560         struct dwc3             *dwc = dep->dwc;
 561         u32                     reg;
 562         int                     ret;
 563
 564         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 565
 566         if (!(dep->flags & DWC3_EP_ENABLED)) {
 567                 ret = dwc3_gadget_start_config(dwc, dep);
 568                 if (ret)
 569                         return ret;
 570         }
 571
 572         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 573                         restore);
 574         if (ret)
 575                 return ret;
 576
 577         if (!(dep->flags & DWC3_EP_ENABLED)) {
 578                 struct dwc3_trb *trb_st_hw;
 579                 struct dwc3_trb *trb_link;
 580
 581                 dep->endpoint.desc = desc;
 582                 dep->comp_desc = comp_desc;
 583                 dep->type = usb_endpoint_type(desc);
 584                 dep->flags |= DWC3_EP_ENABLED;
 585
 586                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 587                 reg |= DWC3_DALEPENA_EP(dep->number);
 588                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 589
 590                 if (usb_endpoint_xfer_control(desc))
 591                         goto out;
 592
 593                 /* Link TRB. The HWO bit is never reset */
 594                 trb_st_hw = &dep->trb_pool[0];
 595
 596                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 597                 memset(trb_link, 0, sizeof(*trb_link));
 598
 599                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 600                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 601                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 602                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 603         }
 604
 605 out:
 606         switch (usb_endpoint_type(desc)) {
 607         case USB_ENDPOINT_XFER_CONTROL:
 608                 /* don't change name */
 609                 break;
 610         case USB_ENDPOINT_XFER_ISOC:
 611                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 612                 break;
 613         case USB_ENDPOINT_XFER_BULK:
 614                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 615                 break;
 616         case USB_ENDPOINT_XFER_INT:
 617                 strlcat(dep->name, "-int", sizeof(dep->name));
 618                 break;
 619         default:
 620                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 621         }
 622
 623         return 0;
 624 }
 625
 626 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 627 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 628 {
 629         struct dwc3_request             *req;
 630
 631         if (!list_empty(&dep->started_list)) {
 632                 dwc3_stop_active_transfer(dwc, dep->number, true);
 633
 634                 /* - giveback all requests to gadget driver */
 635                 while (!list_empty(&dep->started_list)) {
 636                         req = next_request(&dep->started_list);
 637
 638                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 639                 }
 640         }
 641
 642         while (!list_empty(&dep->pending_list)) {
 643                 req = next_request(&dep->pending_list);
 644
 645                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 646         }
 647 }
 648
 649 /**
 650  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 651  * @dep: the endpoint to disable
 652  *
 653  * This function also removes requests which are currently processed ny the
 654  * hardware and those which are not yet scheduled.
 655  * Caller should take care of locking.
 656  */
 657 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 658 {
 659         struct dwc3             *dwc = dep->dwc;
 660         u32                     reg;
 661
 662         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 663
 664         dwc3_remove_requests(dwc, dep);
 665
 666         /* make sure HW endpoint isn't stalled */
 667         if (dep->flags & DWC3_EP_STALL)
 668                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 669
 670         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 671         reg &= ~DWC3_DALEPENA_EP(dep->number);
 672         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 673
 674         dep->stream_capable = false;
 675         dep->endpoint.desc = NULL;
 676         dep->comp_desc = NULL;
 677         dep->type = 0;
 678         dep->flags = 0;
 679
 680         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 681                         dep->number >> 1,
 682                         (dep->number & 1) ? "in" : "out");
 683
 684         return 0;
 685 }
 686
 687 /* -------------------------------------------------------------------------- */
 688
 689 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 690                 const struct usb_endpoint_descriptor *desc)
 691 {
 692         return -EINVAL;
 693 }
 694
 695 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 696 {
 697         return -EINVAL;
 698 }
 699
 700 /* -------------------------------------------------------------------------- */
 701
 702 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 703                 const struct usb_endpoint_descriptor *desc)
 704 {
 705         struct dwc3_ep                  *dep;
 706         struct dwc3                     *dwc;
 707         unsigned long                   flags;
 708         int                             ret;
 709
 710         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 711                 pr_debug("dwc3: invalid parameters\n");
 712                 return -EINVAL;
 713         }
 714
 715         if (!desc->wMaxPacketSize) {
 716                 pr_debug("dwc3: missing wMaxPacketSize\n");
 717                 return -EINVAL;
 718         }
 719
 720         dep = to_dwc3_ep(ep);
 721         dwc = dep->dwc;
 722
 723         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 724                                         "%s is already enabled\n",
 725                                         dep->name))
 726                 return 0;
 727
 728         spin_lock_irqsave(&dwc->lock, flags);
 729         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 730         spin_unlock_irqrestore(&dwc->lock, flags);
 731
 732         return ret;
 733 }
 734
 735 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 736 {
 737         struct dwc3_ep                  *dep;
 738         struct dwc3                     *dwc;
 739         unsigned long                   flags;
 740         int                             ret;
 741
 742         if (!ep) {
 743                 pr_debug("dwc3: invalid parameters\n");
 744                 return -EINVAL;
 745         }
 746
 747         dep = to_dwc3_ep(ep);
 748         dwc = dep->dwc;
 749
 750         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 751                                         "%s is already disabled\n",
 752                                         dep->name))
 753                 return 0;
 754
 755         spin_lock_irqsave(&dwc->lock, flags);
 756         ret = __dwc3_gadget_ep_disable(dep);
 757         spin_unlock_irqrestore(&dwc->lock, flags);
 758
 759         return ret;
 760 }
 761
 762 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 763         gfp_t gfp_flags)
 764 {
 765         struct dwc3_request             *req;
 766         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 767
 768         req = kzalloc(sizeof(*req), gfp_flags);
 769         if (!req)
 770                 return NULL;
 771
 772         req->epnum      = dep->number;
 773         req->dep        = dep;
 774
 775         trace_dwc3_alloc_request(req);
 776
 777         return &req->request;
 778 }
 779
 780 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 781                 struct usb_request *request)
 782 {
 783         struct dwc3_request             *req = to_dwc3_request(request);
 784
 785         trace_dwc3_free_request(req);
 786         kfree(req);
 787 }
 788
 789 /**
 790  * dwc3_prepare_one_trb - setup one TRB from one request
 791  * @dep: endpoint for which this request is prepared
 792  * @req: dwc3_request pointer
 793  */
 794 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 795                 struct dwc3_request *req, dma_addr_t dma,
 796                 unsigned length, unsigned last, unsigned chain, unsigned node)
 797 {
 798         struct dwc3_trb         *trb;
 799
 800         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 801                         dep->name, req, (unsigned long long) dma,
 802                         length, last ? " last" : "",
 803                         chain ? " chain" : "");
 804
 805
 806         trb = &dep->trb_pool[dep->trb_enqueue];
 807
 808         if (!req->trb) {
 809                 dwc3_gadget_move_started_request(req);
 810                 req->trb = trb;
 811                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 812                 req->first_trb_index = dep->trb_enqueue;
 813         }
 814
 815         dwc3_ep_inc_enq(dep);
 816         /* Skip the LINK-TRB */
 817         if (dwc3_ep_is_last_trb(dep->trb_enqueue))
 818                 dwc3_ep_inc_enq(dep);
 819
 820         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 821         trb->bpl = lower_32_bits(dma);
 822         trb->bph = upper_32_bits(dma);
 823
 824         switch (usb_endpoint_type(dep->endpoint.desc)) {
 825         case USB_ENDPOINT_XFER_CONTROL:
 826                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 827                 break;
 828
 829         case USB_ENDPOINT_XFER_ISOC:
 830                 if (!node)
 831                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 832                 else
 833                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 834
 835                 /* always enable Interrupt on Missed ISOC */
 836                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 837                 break;
 838
 839         case USB_ENDPOINT_XFER_BULK:
 840         case USB_ENDPOINT_XFER_INT:
 841                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 842                 break;
 843         default:
 844                 /*
 845                  * This is only possible with faulty memory because we
 846                  * checked it already :)
 847                  */
 848                 BUG();
 849         }
 850
 851         /* always enable Continue on Short Packet */
 852         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 853
 854         if (!req->request.no_interrupt && !chain)
 855                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 856
 857         if (last)
 858                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 859
 860         if (chain)
 861                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 862
 863         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 864                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 865
 866         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 867
 868         trace_dwc3_prepare_trb(dep, trb);
 869 }
 870
 871 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 872 {
 873         struct dwc3_trb         *tmp;
 874
 875         /*
 876          * If enqueue & dequeue are equal than it is either full or empty.
 877          *
 878          * One way to know for sure is if the TRB right before us has HWO bit
 879          * set or not. If it has, then we're definitely full and can't fit any
 880          * more transfers in our ring.
 881          */
 882         if (dep->trb_enqueue == dep->trb_dequeue) {
 883                 /* If we're full, enqueue/dequeue are > 0 */
 884                 if (dep->trb_enqueue) {
 885                         tmp = &dep->trb_pool[dep->trb_enqueue - 1];
 886                         if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 887                                 return 0;
 888                 }
 889
 890                 return DWC3_TRB_NUM - 1;
 891         }
 892
 893         return dep->trb_dequeue - dep->trb_enqueue;
 894 }
 895
 896 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 897                 struct dwc3_request *req, unsigned int trbs_left)
 898 {
 899         struct usb_request *request = &req->request;
 900         struct scatterlist *sg = request->sg;
 901         struct scatterlist *s;
 902         unsigned int    last = false;
 903         unsigned int    length;
 904         dma_addr_t      dma;
 905         int             i;
 906
 907         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 908                 unsigned chain = true;
 909
 910                 length = sg_dma_len(s);
 911                 dma = sg_dma_address(s);
 912
 913                 if (sg_is_last(s)) {
 914                         if (list_is_last(&req->list, &dep->pending_list))
 915                                 last = true;
 916
 917                         chain = false;
 918                 }
 919
 920                 if (!trbs_left)
 921                         last = true;
 922
 923                 if (last)
 924                         chain = false;
 925
 926                 dwc3_prepare_one_trb(dep, req, dma, length,
 927                                 last, chain, i);
 928
 929                 if (last)
 930                         break;
 931         }
 932 }
 933
 934 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 935                 struct dwc3_request *req, unsigned int trbs_left)
 936 {
 937         unsigned int    last = false;
 938         unsigned int    length;
 939         dma_addr_t      dma;
 940
 941         dma = req->request.dma;
 942         length = req->request.length;
 943
 944         if (!trbs_left)
 945                 last = true;
 946
 947         /* Is this the last request? */
 948         if (list_is_last(&req->list, &dep->pending_list))
 949                 last = true;
 950
 951         dwc3_prepare_one_trb(dep, req, dma, length,
 952                         last, false, 0);
 953 }
 954
 955 /*
 956  * dwc3_prepare_trbs - setup TRBs from requests
 957  * @dep: endpoint for which requests are being prepared
 958  *
 959  * The function goes through the requests list and sets up TRBs for the
 960  * transfers. The function returns once there are no more TRBs available or
 961  * it runs out of requests.
 962  */
 963 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 964 {
 965         struct dwc3_request     *req, *n;
 966         u32                     trbs_left;
 967
 968         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 969
 970         trbs_left = dwc3_calc_trbs_left(dep);
 971
 972         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 973                 if (req->request.num_mapped_sgs > 0)
 974                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--);
 975                 else
 976                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--);
 977
 978                 if (!trbs_left)
 979                         return;
 980         }
 981 }
 982
 983 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 984 {
 985         struct dwc3_gadget_ep_cmd_params params;
 986         struct dwc3_request             *req;
 987         struct dwc3                     *dwc = dep->dwc;
 988         int                             starting;
 989         int                             ret;
 990         u32                             cmd;
 991
 992         starting = !(dep->flags & DWC3_EP_BUSY);
 993
 994         dwc3_prepare_trbs(dep);
 995         req = next_request(&dep->started_list);
 996         if (!req) {
 997                 dep->flags |= DWC3_EP_PENDING_REQUEST;
 998                 return 0;
 999         }
1000
1001         memset(&params, 0, sizeof(params));
1002
1003         if (starting) {
1004                 params.param0 = upper_32_bits(req->trb_dma);
1005                 params.param1 = lower_32_bits(req->trb_dma);
1006                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1007         } else {
1008                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1009         }
1010
1011         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1012         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1013         if (ret < 0) {
1014                 /*
1015                  * FIXME we need to iterate over the list of requests
1016                  * here and stop, unmap, free and del each of the linked
1017                  * requests instead of what we do now.
1018                  */
1019                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1020                                 req->direction);
1021                 list_del(&req->list);
1022                 return ret;
1023         }
1024
1025         dep->flags |= DWC3_EP_BUSY;
1026
1027         if (starting) {
1028                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1029                 WARN_ON_ONCE(!dep->resource_index);
1030         }
1031
1032         return 0;
1033 }
1034
1035 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1036                 struct dwc3_ep *dep, u32 cur_uf)
1037 {
1038         u32 uf;
1039
1040         if (list_empty(&dep->pending_list)) {
1041                 dwc3_trace(trace_dwc3_gadget,
1042                                 "ISOC ep %s run out for requests",
1043                                 dep->name);
1044                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1045                 return;
1046         }
1047
1048         /* 4 micro frames in the future */
1049         uf = cur_uf + dep->interval * 4;
1050
1051         __dwc3_gadget_kick_transfer(dep, uf);
1052 }
1053
1054 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1055                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1056 {
1057         u32 cur_uf, mask;
1058
1059         mask = ~(dep->interval - 1);
1060         cur_uf = event->parameters & mask;
1061
1062         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1063 }
1064
1065 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1066 {
1067         struct dwc3             *dwc = dep->dwc;
1068         int                     ret;
1069
1070         if (!dep->endpoint.desc) {
1071                 dwc3_trace(trace_dwc3_gadget,
1072                                 "trying to queue request %p to disabled %s\n",
1073                                 &req->request, dep->endpoint.name);
1074                 return -ESHUTDOWN;
1075         }
1076
1077         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1078                                 &req->request, req->dep->name)) {
1079                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1080                                 &req->request, req->dep->name);
1081                 return -EINVAL;
1082         }
1083
1084         req->request.actual     = 0;
1085         req->request.status     = -EINPROGRESS;
1086         req->direction          = dep->direction;
1087         req->epnum              = dep->number;
1088
1089         trace_dwc3_ep_queue(req);
1090
1091         /*
1092          * Per databook, the total size of buffer must be a multiple
1093          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1094          * configed for endpoints in dwc3_gadget_set_ep_config(),
1095          * set to usb_endpoint_descriptor->wMaxPacketSize.
1096          */
1097         if (dep->direction == 0 &&
1098             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1099                 req->request.length = roundup(req->request.length,
1100                                         dep->endpoint.desc->wMaxPacketSize);
1101
1102         /*
1103          * We only add to our list of requests now and
1104          * start consuming the list once we get XferNotReady
1105          * IRQ.
1106          *
1107          * That way, we avoid doing anything that we don't need
1108          * to do now and defer it until the point we receive a
1109          * particular token from the Host side.
1110          *
1111          * This will also avoid Host cancelling URBs due to too
1112          * many NAKs.
1113          */
1114         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1115                         dep->direction);
1116         if (ret)
1117                 return ret;
1118
1119         list_add_tail(&req->list, &dep->pending_list);
1120
1121         /*
1122          * If there are no pending requests and the endpoint isn't already
1123          * busy, we will just start the request straight away.
1124          *
1125          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1126          * little bit faster.
1127          */
1128         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1129                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1130                         !(dep->flags & DWC3_EP_BUSY)) {
1131                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1132                 goto out;
1133         }
1134
1135         /*
1136          * There are a few special cases:
1137          *
1138          * 1. XferNotReady with empty list of requests. We need to kick the
1139          *    transfer here in that situation, otherwise we will be NAKing
1140          *    forever. If we get XferNotReady before gadget driver has a
1141          *    chance to queue a request, we will ACK the IRQ but won't be
1142          *    able to receive the data until the next request is queued.
1143          *    The following code is handling exactly that.
1144          *
1145          */
1146         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1147                 /*
1148                  * If xfernotready is already elapsed and it is a case
1149                  * of isoc transfer, then issue END TRANSFER, so that
1150                  * you can receive xfernotready again and can have
1151                  * notion of current microframe.
1152                  */
1153                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1154                         if (list_empty(&dep->started_list)) {
1155                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1156                                 dep->flags = DWC3_EP_ENABLED;
1157                         }
1158                         return 0;
1159                 }
1160
1161                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1162                 if (!ret)
1163                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1164
1165                 goto out;
1166         }
1167
1168         /*
1169          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1170          *    kick the transfer here after queuing a request, otherwise the
1171          *    core may not see the modified TRB(s).
1172          */
1173         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1174                         (dep->flags & DWC3_EP_BUSY) &&
1175                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1176                 WARN_ON_ONCE(!dep->resource_index);
1177                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1178                 goto out;
1179         }
1180
1181         /*
1182          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1183          * right away, otherwise host will not know we have streams to be
1184          * handled.
1185          */
1186         if (dep->stream_capable)
1187                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1188
1189 out:
1190         if (ret && ret != -EBUSY)
1191                 dwc3_trace(trace_dwc3_gadget,
1192                                 "%s: failed to kick transfers\n",
1193                                 dep->name);
1194         if (ret == -EBUSY)
1195                 ret = 0;
1196
1197         return ret;
1198 }
1199
1200 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1201                 struct usb_request *request)
1202 {
1203         dwc3_gadget_ep_free_request(ep, request);
1204 }
1205
1206 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1207 {
1208         struct dwc3_request             *req;
1209         struct usb_request              *request;
1210         struct usb_ep                   *ep = &dep->endpoint;
1211
1212         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1213         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1214         if (!request)
1215                 return -ENOMEM;
1216
1217         request->length = 0;
1218         request->buf = dwc->zlp_buf;
1219         request->complete = __dwc3_gadget_ep_zlp_complete;
1220
1221         req = to_dwc3_request(request);
1222
1223         return __dwc3_gadget_ep_queue(dep, req);
1224 }
1225
1226 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1227         gfp_t gfp_flags)
1228 {
1229         struct dwc3_request             *req = to_dwc3_request(request);
1230         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1231         struct dwc3                     *dwc = dep->dwc;
1232
1233         unsigned long                   flags;
1234
1235         int                             ret;
1236
1237         spin_lock_irqsave(&dwc->lock, flags);
1238         ret = __dwc3_gadget_ep_queue(dep, req);
1239
1240         /*
1241          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1242          * setting request->zero, instead of doing magic, we will just queue an
1243          * extra usb_request ourselves so that it gets handled the same way as
1244          * any other request.
1245          */
1246         if (ret == 0 && request->zero && request->length &&
1247             (request->length % ep->desc->wMaxPacketSize == 0))
1248                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1249
1250         spin_unlock_irqrestore(&dwc->lock, flags);
1251
1252         return ret;
1253 }
1254
1255 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1256                 struct usb_request *request)
1257 {
1258         struct dwc3_request             *req = to_dwc3_request(request);
1259         struct dwc3_request             *r = NULL;
1260
1261         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1262         struct dwc3                     *dwc = dep->dwc;
1263
1264         unsigned long                   flags;
1265         int                             ret = 0;
1266
1267         trace_dwc3_ep_dequeue(req);
1268
1269         spin_lock_irqsave(&dwc->lock, flags);
1270
1271         list_for_each_entry(r, &dep->pending_list, list) {
1272                 if (r == req)
1273                         break;
1274         }
1275
1276         if (r != req) {
1277                 list_for_each_entry(r, &dep->started_list, list) {
1278                         if (r == req)
1279                                 break;
1280                 }
1281                 if (r == req) {
1282                         /* wait until it is processed */
1283                         dwc3_stop_active_transfer(dwc, dep->number, true);
1284                         goto out1;
1285                 }
1286                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1287                                 request, ep->name);
1288                 ret = -EINVAL;
1289                 goto out0;
1290         }
1291
1292 out1:
1293         /* giveback the request */
1294         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1295
1296 out0:
1297         spin_unlock_irqrestore(&dwc->lock, flags);
1298
1299         return ret;
1300 }
1301
1302 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1303 {
1304         struct dwc3_gadget_ep_cmd_params        params;
1305         struct dwc3                             *dwc = dep->dwc;
1306         int                                     ret;
1307
1308         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1309                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1310                 return -EINVAL;
1311         }
1312
1313         memset(&params, 0x00, sizeof(params));
1314
1315         if (value) {
1316                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1317                                 (!list_empty(&dep->started_list) ||
1318                                  !list_empty(&dep->pending_list)))) {
1319                         dwc3_trace(trace_dwc3_gadget,
1320                                         "%s: pending request, cannot halt",
1321                                         dep->name);
1322                         return -EAGAIN;
1323                 }
1324
1325                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1326                                 &params);
1327                 if (ret)
1328                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1329                                         dep->name);
1330                 else
1331                         dep->flags |= DWC3_EP_STALL;
1332         } else {
1333
1334                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1335                 if (ret)
1336                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1337                                         dep->name);
1338                 else
1339                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1340         }
1341
1342         return ret;
1343 }
1344
1345 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1346 {
1347         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1348         struct dwc3                     *dwc = dep->dwc;
1349
1350         unsigned long                   flags;
1351
1352         int                             ret;
1353
1354         spin_lock_irqsave(&dwc->lock, flags);
1355         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1356         spin_unlock_irqrestore(&dwc->lock, flags);
1357
1358         return ret;
1359 }
1360
1361 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1362 {
1363         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1364         struct dwc3                     *dwc = dep->dwc;
1365         unsigned long                   flags;
1366         int                             ret;
1367
1368         spin_lock_irqsave(&dwc->lock, flags);
1369         dep->flags |= DWC3_EP_WEDGE;
1370
1371         if (dep->number == 0 || dep->number == 1)
1372                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1373         else
1374                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1375         spin_unlock_irqrestore(&dwc->lock, flags);
1376
1377         return ret;
1378 }
1379
1380 /* -------------------------------------------------------------------------- */
1381
1382 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1383         .bLength        = USB_DT_ENDPOINT_SIZE,
1384         .bDescriptorType = USB_DT_ENDPOINT,
1385         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1386 };
1387
1388 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1389         .enable         = dwc3_gadget_ep0_enable,
1390         .disable        = dwc3_gadget_ep0_disable,
1391         .alloc_request  = dwc3_gadget_ep_alloc_request,
1392         .free_request   = dwc3_gadget_ep_free_request,
1393         .queue          = dwc3_gadget_ep0_queue,
1394         .dequeue        = dwc3_gadget_ep_dequeue,
1395         .set_halt       = dwc3_gadget_ep0_set_halt,
1396         .set_wedge      = dwc3_gadget_ep_set_wedge,
1397 };
1398
1399 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1400         .enable         = dwc3_gadget_ep_enable,
1401         .disable        = dwc3_gadget_ep_disable,
1402         .alloc_request  = dwc3_gadget_ep_alloc_request,
1403         .free_request   = dwc3_gadget_ep_free_request,
1404         .queue          = dwc3_gadget_ep_queue,
1405         .dequeue        = dwc3_gadget_ep_dequeue,
1406         .set_halt       = dwc3_gadget_ep_set_halt,
1407         .set_wedge      = dwc3_gadget_ep_set_wedge,
1408 };
1409
1410 /* -------------------------------------------------------------------------- */
1411
1412 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1413 {
1414         struct dwc3             *dwc = gadget_to_dwc(g);
1415         u32                     reg;
1416
1417         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1418         return DWC3_DSTS_SOFFN(reg);
1419 }
1420
1421 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1422 {
1423         unsigned long           timeout;
1424
1425         int                     ret;
1426         u32                     reg;
1427
1428         u8                      link_state;
1429         u8                      speed;
1430
1431         /*
1432          * According to the Databook Remote wakeup request should
1433          * be issued only when the device is in early suspend state.
1434          *
1435          * We can check that via USB Link State bits in DSTS register.
1436          */
1437         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1438
1439         speed = reg & DWC3_DSTS_CONNECTSPD;
1440         if (speed == DWC3_DSTS_SUPERSPEED) {
1441                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1442                 return 0;
1443         }
1444
1445         link_state = DWC3_DSTS_USBLNKST(reg);
1446
1447         switch (link_state) {
1448         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1449         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1450                 break;
1451         default:
1452                 dwc3_trace(trace_dwc3_gadget,
1453                                 "can't wakeup from '%s'\n",
1454                                 dwc3_gadget_link_string(link_state));
1455                 return -EINVAL;
1456         }
1457
1458         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1459         if (ret < 0) {
1460                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1461                 return ret;
1462         }
1463
1464         /* Recent versions do this automatically */
1465         if (dwc->revision < DWC3_REVISION_194A) {
1466                 /* write zeroes to Link Change Request */
1467                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1468                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1469                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1470         }
1471
1472         /* poll until Link State changes to ON */
1473         timeout = jiffies + msecs_to_jiffies(100);
1474
1475         while (!time_after(jiffies, timeout)) {
1476                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1477
1478                 /* in HS, means ON */
1479                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1480                         break;
1481         }
1482
1483         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1484                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1485                 return -EINVAL;
1486         }
1487
1488         return 0;
1489 }
1490
1491 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1492 {
1493         struct dwc3             *dwc = gadget_to_dwc(g);
1494         unsigned long           flags;
1495         int                     ret;
1496
1497         spin_lock_irqsave(&dwc->lock, flags);
1498         ret = __dwc3_gadget_wakeup(dwc);
1499         spin_unlock_irqrestore(&dwc->lock, flags);
1500
1501         return ret;
1502 }
1503
1504 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1505                 int is_selfpowered)
1506 {
1507         struct dwc3             *dwc = gadget_to_dwc(g);
1508         unsigned long           flags;
1509
1510         spin_lock_irqsave(&dwc->lock, flags);
1511         g->is_selfpowered = !!is_selfpowered;
1512         spin_unlock_irqrestore(&dwc->lock, flags);
1513
1514         return 0;
1515 }
1516
1517 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1518 {
1519         u32                     reg;
1520         u32                     timeout = 500;
1521
1522         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1523         if (is_on) {
1524                 if (dwc->revision <= DWC3_REVISION_187A) {
1525                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1526                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1527                 }
1528
1529                 if (dwc->revision >= DWC3_REVISION_194A)
1530                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1531                 reg |= DWC3_DCTL_RUN_STOP;
1532
1533                 if (dwc->has_hibernation)
1534                         reg |= DWC3_DCTL_KEEP_CONNECT;
1535
1536                 dwc->pullups_connected = true;
1537         } else {
1538                 reg &= ~DWC3_DCTL_RUN_STOP;
1539
1540                 if (dwc->has_hibernation && !suspend)
1541                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1542
1543                 dwc->pullups_connected = false;
1544         }
1545
1546         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1547
1548         do {
1549                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1550                 if (is_on) {
1551                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1552                                 break;
1553                 } else {
1554                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1555                                 break;
1556                 }
1557                 timeout--;
1558                 if (!timeout)
1559                         return -ETIMEDOUT;
1560                 udelay(1);
1561         } while (1);
1562
1563         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1564                         dwc->gadget_driver
1565                         ? dwc->gadget_driver->function : "no-function",
1566                         is_on ? "connect" : "disconnect");
1567
1568         return 0;
1569 }
1570
1571 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1572 {
1573         struct dwc3             *dwc = gadget_to_dwc(g);
1574         unsigned long           flags;
1575         int                     ret;
1576
1577         is_on = !!is_on;
1578
1579         spin_lock_irqsave(&dwc->lock, flags);
1580         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1581         spin_unlock_irqrestore(&dwc->lock, flags);
1582
1583         return ret;
1584 }
1585
1586 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1587 {
1588         u32                     reg;
1589
1590         /* Enable all but Start and End of Frame IRQs */
1591         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1592                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1593                         DWC3_DEVTEN_CMDCMPLTEN |
1594                         DWC3_DEVTEN_ERRTICERREN |
1595                         DWC3_DEVTEN_WKUPEVTEN |
1596                         DWC3_DEVTEN_ULSTCNGEN |
1597                         DWC3_DEVTEN_CONNECTDONEEN |
1598                         DWC3_DEVTEN_USBRSTEN |
1599                         DWC3_DEVTEN_DISCONNEVTEN);
1600
1601         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1602 }
1603
1604 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1605 {
1606         /* mask all interrupts */
1607         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1608 }
1609
1610 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1611 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1612
1613 /**
1614  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1615  * dwc: pointer to our context structure
1616  *
1617  * The following looks like complex but it's actually very simple. In order to
1618  * calculate the number of packets we can burst at once on OUT transfers, we're
1619  * gonna use RxFIFO size.
1620  *
1621  * To calculate RxFIFO size we need two numbers:
1622  * MDWIDTH = size, in bits, of the internal memory bus
1623  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1624  *
1625  * Given these two numbers, the formula is simple:
1626  *
1627  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1628  *
1629  * 24 bytes is for 3x SETUP packets
1630  * 16 bytes is a clock domain crossing tolerance
1631  *
1632  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1633  */
1634 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1635 {
1636         u32 ram2_depth;
1637         u32 mdwidth;
1638         u32 nump;
1639         u32 reg;
1640
1641         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1642         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1643
1644         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1645         nump = min_t(u32, nump, 16);
1646
1647         /* update NumP */
1648         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1649         reg &= ~DWC3_DCFG_NUMP_MASK;
1650         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1651         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1652 }
1653
1654 static int __dwc3_gadget_start(struct dwc3 *dwc)
1655 {
1656         struct dwc3_ep          *dep;
1657         int                     ret = 0;
1658         u32                     reg;
1659
1660         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1661         reg &= ~(DWC3_DCFG_SPEED_MASK);
1662
1663         /**
1664          * WORKAROUND: DWC3 revision < 2.20a have an issue
1665          * which would cause metastability state on Run/Stop
1666          * bit if we try to force the IP to USB2-only mode.
1667          *
1668          * Because of that, we cannot configure the IP to any
1669          * speed other than the SuperSpeed
1670          *
1671          * Refers to:
1672          *
1673          * STAR#9000525659: Clock Domain Crossing on DCTL in
1674          * USB 2.0 Mode
1675          */
1676         if (dwc->revision < DWC3_REVISION_220A) {
1677                 reg |= DWC3_DCFG_SUPERSPEED;
1678         } else {
1679                 switch (dwc->maximum_speed) {
1680                 case USB_SPEED_LOW:
1681                         reg |= DWC3_DSTS_LOWSPEED;
1682                         break;
1683                 case USB_SPEED_FULL:
1684                         reg |= DWC3_DSTS_FULLSPEED1;
1685                         break;
1686                 case USB_SPEED_HIGH:
1687                         reg |= DWC3_DSTS_HIGHSPEED;
1688                         break;
1689                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1690                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1691                 default:
1692                         reg |= DWC3_DSTS_SUPERSPEED;
1693                 }
1694         }
1695         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1696
1697         /*
1698          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1699          * field instead of letting dwc3 itself calculate that automatically.
1700          *
1701          * This way, we maximize the chances that we'll be able to get several
1702          * bursts of data without going through any sort of endpoint throttling.
1703          */
1704         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1705         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1706         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1707
1708         dwc3_gadget_setup_nump(dwc);
1709
1710         /* Start with SuperSpeed Default */
1711         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1712
1713         dep = dwc->eps[0];
1714         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1715                         false);
1716         if (ret) {
1717                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1718                 goto err0;
1719         }
1720
1721         dep = dwc->eps[1];
1722         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1723                         false);
1724         if (ret) {
1725                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1726                 goto err1;
1727         }
1728
1729         /* begin to receive SETUP packets */
1730         dwc->ep0state = EP0_SETUP_PHASE;
1731         dwc3_ep0_out_start(dwc);
1732
1733         dwc3_gadget_enable_irq(dwc);
1734
1735         return 0;
1736
1737 err1:
1738         __dwc3_gadget_ep_disable(dwc->eps[0]);
1739
1740 err0:
1741         return ret;
1742 }
1743
1744 static int dwc3_gadget_start(struct usb_gadget *g,
1745                 struct usb_gadget_driver *driver)
1746 {
1747         struct dwc3             *dwc = gadget_to_dwc(g);
1748         unsigned long           flags;
1749         int                     ret = 0;
1750         int                     irq;
1751
1752         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1753         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1754                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1755         if (ret) {
1756                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1757                                 irq, ret);
1758                 goto err0;
1759         }
1760         dwc->irq_gadget = irq;
1761
1762         spin_lock_irqsave(&dwc->lock, flags);
1763         if (dwc->gadget_driver) {
1764                 dev_err(dwc->dev, "%s is already bound to %s\n",
1765                                 dwc->gadget.name,
1766                                 dwc->gadget_driver->driver.name);
1767                 ret = -EBUSY;
1768                 goto err1;
1769         }
1770
1771         dwc->gadget_driver      = driver;
1772
1773         __dwc3_gadget_start(dwc);
1774         spin_unlock_irqrestore(&dwc->lock, flags);
1775
1776         return 0;
1777
1778 err1:
1779         spin_unlock_irqrestore(&dwc->lock, flags);
1780         free_irq(irq, dwc);
1781
1782 err0:
1783         return ret;
1784 }
1785
1786 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1787 {
1788         dwc3_gadget_disable_irq(dwc);
1789         __dwc3_gadget_ep_disable(dwc->eps[0]);
1790         __dwc3_gadget_ep_disable(dwc->eps[1]);
1791 }
1792
1793 static int dwc3_gadget_stop(struct usb_gadget *g)
1794 {
1795         struct dwc3             *dwc = gadget_to_dwc(g);
1796         unsigned long           flags;
1797
1798         spin_lock_irqsave(&dwc->lock, flags);
1799         __dwc3_gadget_stop(dwc);
1800         dwc->gadget_driver      = NULL;
1801         spin_unlock_irqrestore(&dwc->lock, flags);
1802
1803         free_irq(dwc->irq_gadget, dwc->ev_buf);
1804
1805         return 0;
1806 }
1807
1808 static const struct usb_gadget_ops dwc3_gadget_ops = {
1809         .get_frame              = dwc3_gadget_get_frame,
1810         .wakeup                 = dwc3_gadget_wakeup,
1811         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1812         .pullup                 = dwc3_gadget_pullup,
1813         .udc_start              = dwc3_gadget_start,
1814         .udc_stop               = dwc3_gadget_stop,
1815 };
1816
1817 /* -------------------------------------------------------------------------- */
1818
1819 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1820                 u8 num, u32 direction)
1821 {
1822         struct dwc3_ep                  *dep;
1823         u8                              i;
1824
1825         for (i = 0; i < num; i++) {
1826                 u8 epnum = (i << 1) | (!!direction);
1827
1828                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1829                 if (!dep)
1830                         return -ENOMEM;
1831
1832                 dep->dwc = dwc;
1833                 dep->number = epnum;
1834                 dep->direction = !!direction;
1835                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1836                 dwc->eps[epnum] = dep;
1837
1838                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1839                                 (epnum & 1) ? "in" : "out");
1840
1841                 dep->endpoint.name = dep->name;
1842
1843                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1844
1845                 if (epnum == 0 || epnum == 1) {
1846                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1847                         dep->endpoint.maxburst = 1;
1848                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1849                         if (!epnum)
1850                                 dwc->gadget.ep0 = &dep->endpoint;
1851                 } else {
1852                         int             ret;
1853
1854                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1855                         dep->endpoint.max_streams = 15;
1856                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1857                         list_add_tail(&dep->endpoint.ep_list,
1858                                         &dwc->gadget.ep_list);
1859
1860                         ret = dwc3_alloc_trb_pool(dep);
1861                         if (ret)
1862                                 return ret;
1863                 }
1864
1865                 if (epnum == 0 || epnum == 1) {
1866                         dep->endpoint.caps.type_control = true;
1867                 } else {
1868                         dep->endpoint.caps.type_iso = true;
1869                         dep->endpoint.caps.type_bulk = true;
1870                         dep->endpoint.caps.type_int = true;
1871                 }
1872
1873                 dep->endpoint.caps.dir_in = !!direction;
1874                 dep->endpoint.caps.dir_out = !direction;
1875
1876                 INIT_LIST_HEAD(&dep->pending_list);
1877                 INIT_LIST_HEAD(&dep->started_list);
1878         }
1879
1880         return 0;
1881 }
1882
1883 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1884 {
1885         int                             ret;
1886
1887         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1888
1889         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1890         if (ret < 0) {
1891                 dwc3_trace(trace_dwc3_gadget,
1892                                 "failed to allocate OUT endpoints");
1893                 return ret;
1894         }
1895
1896         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1897         if (ret < 0) {
1898                 dwc3_trace(trace_dwc3_gadget,
1899                                 "failed to allocate IN endpoints");
1900                 return ret;
1901         }
1902
1903         return 0;
1904 }
1905
1906 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1907 {
1908         struct dwc3_ep                  *dep;
1909         u8                              epnum;
1910
1911         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1912                 dep = dwc->eps[epnum];
1913                 if (!dep)
1914                         continue;
1915                 /*
1916                  * Physical endpoints 0 and 1 are special; they form the
1917                  * bi-directional USB endpoint 0.
1918                  *
1919                  * For those two physical endpoints, we don't allocate a TRB
1920                  * pool nor do we add them the endpoints list. Due to that, we
1921                  * shouldn't do these two operations otherwise we would end up
1922                  * with all sorts of bugs when removing dwc3.ko.
1923                  */
1924                 if (epnum != 0 && epnum != 1) {
1925                         dwc3_free_trb_pool(dep);
1926                         list_del(&dep->endpoint.ep_list);
1927                 }
1928
1929                 kfree(dep);
1930         }
1931 }
1932
1933 /* -------------------------------------------------------------------------- */
1934
1935 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1936                 struct dwc3_request *req, struct dwc3_trb *trb,
1937                 const struct dwc3_event_depevt *event, int status)
1938 {
1939         unsigned int            count;
1940         unsigned int            s_pkt = 0;
1941         unsigned int            trb_status;
1942
1943         trace_dwc3_complete_trb(dep, trb);
1944
1945         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1946                 /*
1947                  * We continue despite the error. There is not much we
1948                  * can do. If we don't clean it up we loop forever. If
1949                  * we skip the TRB then it gets overwritten after a
1950                  * while since we use them in a ring buffer. A BUG()
1951                  * would help. Lets hope that if this occurs, someone
1952                  * fixes the root cause instead of looking away :)
1953                  */
1954                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1955                                 dep->name, trb);
1956         count = trb->size & DWC3_TRB_SIZE_MASK;
1957
1958         if (dep->direction) {
1959                 if (count) {
1960                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1961                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1962                                 dwc3_trace(trace_dwc3_gadget,
1963                                                 "%s: incomplete IN transfer\n",
1964                                                 dep->name);
1965                                 /*
1966                                  * If missed isoc occurred and there is
1967                                  * no request queued then issue END
1968                                  * TRANSFER, so that core generates
1969                                  * next xfernotready and we will issue
1970                                  * a fresh START TRANSFER.
1971                                  * If there are still queued request
1972                                  * then wait, do not issue either END
1973                                  * or UPDATE TRANSFER, just attach next
1974                                  * request in pending_list during
1975                                  * giveback.If any future queued request
1976                                  * is successfully transferred then we
1977                                  * will issue UPDATE TRANSFER for all
1978                                  * request in the pending_list.
1979                                  */
1980                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1981                         } else {
1982                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1983                                                 dep->name);
1984                                 status = -ECONNRESET;
1985                         }
1986                 } else {
1987                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1988                 }
1989         } else {
1990                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1991                         s_pkt = 1;
1992         }
1993
1994         /*
1995          * We assume here we will always receive the entire data block
1996          * which we should receive. Meaning, if we program RX to
1997          * receive 4K but we receive only 2K, we assume that's all we
1998          * should receive and we simply bounce the request back to the
1999          * gadget driver for further processing.
2000          */
2001         req->request.actual += req->request.length - count;
2002         if (s_pkt)
2003                 return 1;
2004         if ((event->status & DEPEVT_STATUS_LST) &&
2005                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2006                                 DWC3_TRB_CTRL_HWO)))
2007                 return 1;
2008         if ((event->status & DEPEVT_STATUS_IOC) &&
2009                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2010                 return 1;
2011         return 0;
2012 }
2013
2014 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2015                 const struct dwc3_event_depevt *event, int status)
2016 {
2017         struct dwc3_request     *req;
2018         struct dwc3_trb         *trb;
2019         unsigned int            slot;
2020         unsigned int            i;
2021         int                     ret;
2022
2023         do {
2024                 req = next_request(&dep->started_list);
2025                 if (WARN_ON_ONCE(!req))
2026                         return 1;
2027
2028                 i = 0;
2029                 do {
2030                         slot = req->first_trb_index + i;
2031                         if (slot == DWC3_TRB_NUM - 1)
2032                                 slot++;
2033                         slot %= DWC3_TRB_NUM;
2034                         trb = &dep->trb_pool[slot];
2035
2036                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2037                                         event, status);
2038                         if (ret)
2039                                 break;
2040                 } while (++i < req->request.num_mapped_sgs);
2041
2042                 dwc3_gadget_giveback(dep, req, status);
2043
2044                 if (ret)
2045                         break;
2046         } while (1);
2047
2048         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2049                         list_empty(&dep->started_list)) {
2050                 if (list_empty(&dep->pending_list)) {
2051                         /*
2052                          * If there is no entry in request list then do
2053                          * not issue END TRANSFER now. Just set PENDING
2054                          * flag, so that END TRANSFER is issued when an
2055                          * entry is added into request list.
2056                          */
2057                         dep->flags = DWC3_EP_PENDING_REQUEST;
2058                 } else {
2059                         dwc3_stop_active_transfer(dwc, dep->number, true);
2060                         dep->flags = DWC3_EP_ENABLED;
2061                 }
2062                 return 1;
2063         }
2064
2065         return 1;
2066 }
2067
2068 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2069                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2070 {
2071         unsigned                status = 0;
2072         int                     clean_busy;
2073         u32                     is_xfer_complete;
2074
2075         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2076
2077         if (event->status & DEPEVT_STATUS_BUSERR)
2078                 status = -ECONNRESET;
2079
2080         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2081         if (clean_busy && (is_xfer_complete ||
2082                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2083                 dep->flags &= ~DWC3_EP_BUSY;
2084
2085         /*
2086          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2087          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2088          */
2089         if (dwc->revision < DWC3_REVISION_183A) {
2090                 u32             reg;
2091                 int             i;
2092
2093                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2094                         dep = dwc->eps[i];
2095
2096                         if (!(dep->flags & DWC3_EP_ENABLED))
2097                                 continue;
2098
2099                         if (!list_empty(&dep->started_list))
2100                                 return;
2101                 }
2102
2103                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2104                 reg |= dwc->u1u2;
2105                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2106
2107                 dwc->u1u2 = 0;
2108         }
2109
2110         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2111                 int ret;
2112
2113                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2114                 if (!ret || ret == -EBUSY)
2115                         return;
2116         }
2117 }
2118
2119 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2120                 const struct dwc3_event_depevt *event)
2121 {
2122         struct dwc3_ep          *dep;
2123         u8                      epnum = event->endpoint_number;
2124
2125         dep = dwc->eps[epnum];
2126
2127         if (!(dep->flags & DWC3_EP_ENABLED))
2128                 return;
2129
2130         if (epnum == 0 || epnum == 1) {
2131                 dwc3_ep0_interrupt(dwc, event);
2132                 return;
2133         }
2134
2135         switch (event->endpoint_event) {
2136         case DWC3_DEPEVT_XFERCOMPLETE:
2137                 dep->resource_index = 0;
2138
2139                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2140                         dwc3_trace(trace_dwc3_gadget,
2141                                         "%s is an Isochronous endpoint\n",
2142                                         dep->name);
2143                         return;
2144                 }
2145
2146                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2147                 break;
2148         case DWC3_DEPEVT_XFERINPROGRESS:
2149                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2150                 break;
2151         case DWC3_DEPEVT_XFERNOTREADY:
2152                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2153                         dwc3_gadget_start_isoc(dwc, dep, event);
2154                 } else {
2155                         int active;
2156                         int ret;
2157
2158                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2159
2160                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2161                                         dep->name, active ? "Transfer Active"
2162                                         : "Transfer Not Active");
2163
2164                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2165                         if (!ret || ret == -EBUSY)
2166                                 return;
2167
2168                         dwc3_trace(trace_dwc3_gadget,
2169                                         "%s: failed to kick transfers\n",
2170                                         dep->name);
2171                 }
2172
2173                 break;
2174         case DWC3_DEPEVT_STREAMEVT:
2175                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2176                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2177                                         dep->name);
2178                         return;
2179                 }
2180
2181                 switch (event->status) {
2182                 case DEPEVT_STREAMEVT_FOUND:
2183                         dwc3_trace(trace_dwc3_gadget,
2184                                         "Stream %d found and started",
2185                                         event->parameters);
2186
2187                         break;
2188                 case DEPEVT_STREAMEVT_NOTFOUND:
2189                         /* FALLTHROUGH */
2190                 default:
2191                         dwc3_trace(trace_dwc3_gadget,
2192                                         "unable to find suitable stream\n");
2193                 }
2194                 break;
2195         case DWC3_DEPEVT_RXTXFIFOEVT:
2196                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2197                 break;
2198         case DWC3_DEPEVT_EPCMDCMPLT:
2199                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2200                 break;
2201         }
2202 }
2203
2204 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2205 {
2206         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2207                 spin_unlock(&dwc->lock);
2208                 dwc->gadget_driver->disconnect(&dwc->gadget);
2209                 spin_lock(&dwc->lock);
2210         }
2211 }
2212
2213 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2214 {
2215         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2216                 spin_unlock(&dwc->lock);
2217                 dwc->gadget_driver->suspend(&dwc->gadget);
2218                 spin_lock(&dwc->lock);
2219         }
2220 }
2221
2222 static void dwc3_resume_gadget(struct dwc3 *dwc)
2223 {
2224         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2225                 spin_unlock(&dwc->lock);
2226                 dwc->gadget_driver->resume(&dwc->gadget);
2227                 spin_lock(&dwc->lock);
2228         }
2229 }
2230
2231 static void dwc3_reset_gadget(struct dwc3 *dwc)
2232 {
2233         if (!dwc->gadget_driver)
2234                 return;
2235
2236         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2237                 spin_unlock(&dwc->lock);
2238                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2239                 spin_lock(&dwc->lock);
2240         }
2241 }
2242
2243 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2244 {
2245         struct dwc3_ep *dep;
2246         struct dwc3_gadget_ep_cmd_params params;
2247         u32 cmd;
2248         int ret;
2249
2250         dep = dwc->eps[epnum];
2251
2252         if (!dep->resource_index)
2253                 return;
2254
2255         /*
2256          * NOTICE: We are violating what the Databook says about the
2257          * EndTransfer command. Ideally we would _always_ wait for the
2258          * EndTransfer Command Completion IRQ, but that's causing too
2259          * much trouble synchronizing between us and gadget driver.
2260          *
2261          * We have discussed this with the IP Provider and it was
2262          * suggested to giveback all requests here, but give HW some
2263          * extra time to synchronize with the interconnect. We're using
2264          * an arbitrary 100us delay for that.
2265          *
2266          * Note also that a similar handling was tested by Synopsys
2267          * (thanks a lot Paul) and nothing bad has come out of it.
2268          * In short, what we're doing is:
2269          *
2270          * - Issue EndTransfer WITH CMDIOC bit set
2271          * - Wait 100us
2272          */
2273
2274         cmd = DWC3_DEPCMD_ENDTRANSFER;
2275         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2276         cmd |= DWC3_DEPCMD_CMDIOC;
2277         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2278         memset(&params, 0, sizeof(params));
2279         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2280         WARN_ON_ONCE(ret);
2281         dep->resource_index = 0;
2282         dep->flags &= ~DWC3_EP_BUSY;
2283         udelay(100);
2284 }
2285
2286 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2287 {
2288         u32 epnum;
2289
2290         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2291                 struct dwc3_ep *dep;
2292
2293                 dep = dwc->eps[epnum];
2294                 if (!dep)
2295                         continue;
2296
2297                 if (!(dep->flags & DWC3_EP_ENABLED))
2298                         continue;
2299
2300                 dwc3_remove_requests(dwc, dep);
2301         }
2302 }
2303
2304 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2305 {
2306         u32 epnum;
2307
2308         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2309                 struct dwc3_ep *dep;
2310                 int ret;
2311
2312                 dep = dwc->eps[epnum];
2313                 if (!dep)
2314                         continue;
2315
2316                 if (!(dep->flags & DWC3_EP_STALL))
2317                         continue;
2318
2319                 dep->flags &= ~DWC3_EP_STALL;
2320
2321                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2322                 WARN_ON_ONCE(ret);
2323         }
2324 }
2325
2326 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2327 {
2328         int                     reg;
2329
2330         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2331         reg &= ~DWC3_DCTL_INITU1ENA;
2332         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2333
2334         reg &= ~DWC3_DCTL_INITU2ENA;
2335         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2336
2337         dwc3_disconnect_gadget(dwc);
2338
2339         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2340         dwc->setup_packet_pending = false;
2341         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2342 }
2343
2344 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2345 {
2346         u32                     reg;
2347
2348         /*
2349          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2350          * would cause a missing Disconnect Event if there's a
2351          * pending Setup Packet in the FIFO.
2352          *
2353          * There's no suggested workaround on the official Bug
2354          * report, which states that "unless the driver/application
2355          * is doing any special handling of a disconnect event,
2356          * there is no functional issue".
2357          *
2358          * Unfortunately, it turns out that we _do_ some special
2359          * handling of a disconnect event, namely complete all
2360          * pending transfers, notify gadget driver of the
2361          * disconnection, and so on.
2362          *
2363          * Our suggested workaround is to follow the Disconnect
2364          * Event steps here, instead, based on a setup_packet_pending
2365          * flag. Such flag gets set whenever we have a SETUP_PENDING
2366          * status for EP0 TRBs and gets cleared on XferComplete for the
2367          * same endpoint.
2368          *
2369          * Refers to:
2370          *
2371          * STAR#9000466709: RTL: Device : Disconnect event not
2372          * generated if setup packet pending in FIFO
2373          */
2374         if (dwc->revision < DWC3_REVISION_188A) {
2375                 if (dwc->setup_packet_pending)
2376                         dwc3_gadget_disconnect_interrupt(dwc);
2377         }
2378
2379         dwc3_reset_gadget(dwc);
2380
2381         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2382         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2383         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2384         dwc->test_mode = false;
2385
2386         dwc3_stop_active_transfers(dwc);
2387         dwc3_clear_stall_all_ep(dwc);
2388
2389         /* Reset device address to zero */
2390         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2391         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2392         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2393 }
2394
2395 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2396 {
2397         u32 reg;
2398         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2399
2400         /*
2401          * We change the clock only at SS but I dunno why I would want to do
2402          * this. Maybe it becomes part of the power saving plan.
2403          */
2404
2405         if (speed != DWC3_DSTS_SUPERSPEED)
2406                 return;
2407
2408         /*
2409          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2410          * each time on Connect Done.
2411          */
2412         if (!usb30_clock)
2413                 return;
2414
2415         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2416         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2417         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2418 }
2419
2420 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2421 {
2422         struct dwc3_ep          *dep;
2423         int                     ret;
2424         u32                     reg;
2425         u8                      speed;
2426
2427         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2428         speed = reg & DWC3_DSTS_CONNECTSPD;
2429         dwc->speed = speed;
2430
2431         dwc3_update_ram_clk_sel(dwc, speed);
2432
2433         switch (speed) {
2434         case DWC3_DCFG_SUPERSPEED:
2435                 /*
2436                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2437                  * would cause a missing USB3 Reset event.
2438                  *
2439                  * In such situations, we should force a USB3 Reset
2440                  * event by calling our dwc3_gadget_reset_interrupt()
2441                  * routine.
2442                  *
2443                  * Refers to:
2444                  *
2445                  * STAR#9000483510: RTL: SS : USB3 reset event may
2446                  * not be generated always when the link enters poll
2447                  */
2448                 if (dwc->revision < DWC3_REVISION_190A)
2449                         dwc3_gadget_reset_interrupt(dwc);
2450
2451                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2452                 dwc->gadget.ep0->maxpacket = 512;
2453                 dwc->gadget.speed = USB_SPEED_SUPER;
2454                 break;
2455         case DWC3_DCFG_HIGHSPEED:
2456                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2457                 dwc->gadget.ep0->maxpacket = 64;
2458                 dwc->gadget.speed = USB_SPEED_HIGH;
2459                 break;
2460         case DWC3_DCFG_FULLSPEED2:
2461         case DWC3_DCFG_FULLSPEED1:
2462                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2463                 dwc->gadget.ep0->maxpacket = 64;
2464                 dwc->gadget.speed = USB_SPEED_FULL;
2465                 break;
2466         case DWC3_DCFG_LOWSPEED:
2467                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2468                 dwc->gadget.ep0->maxpacket = 8;
2469                 dwc->gadget.speed = USB_SPEED_LOW;
2470                 break;
2471         }
2472
2473         /* Enable USB2 LPM Capability */
2474
2475         if ((dwc->revision > DWC3_REVISION_194A)
2476                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2477                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2478                 reg |= DWC3_DCFG_LPM_CAP;
2479                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2480
2481                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2482                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2483
2484                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2485
2486                 /*
2487                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2488                  * DCFG.LPMCap is set, core responses with an ACK and the
2489                  * BESL value in the LPM token is less than or equal to LPM
2490                  * NYET threshold.
2491                  */
2492                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2493                                 && dwc->has_lpm_erratum,
2494                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2495
2496                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2497                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2498
2499                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2500         } else {
2501                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2502                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2503                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2504         }
2505
2506         dep = dwc->eps[0];
2507         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2508                         false);
2509         if (ret) {
2510                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2511                 return;
2512         }
2513
2514         dep = dwc->eps[1];
2515         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2516                         false);
2517         if (ret) {
2518                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2519                 return;
2520         }
2521
2522         /*
2523          * Configure PHY via GUSB3PIPECTLn if required.
2524          *
2525          * Update GTXFIFOSIZn
2526          *
2527          * In both cases reset values should be sufficient.
2528          */
2529 }
2530
2531 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2532 {
2533         /*
2534          * TODO take core out of low power mode when that's
2535          * implemented.
2536          */
2537
2538         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2539                 spin_unlock(&dwc->lock);
2540                 dwc->gadget_driver->resume(&dwc->gadget);
2541                 spin_lock(&dwc->lock);
2542         }
2543 }
2544
2545 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2546                 unsigned int evtinfo)
2547 {
2548         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2549         unsigned int            pwropt;
2550
2551         /*
2552          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2553          * Hibernation mode enabled which would show up when device detects
2554          * host-initiated U3 exit.
2555          *
2556          * In that case, device will generate a Link State Change Interrupt
2557          * from U3 to RESUME which is only necessary if Hibernation is
2558          * configured in.
2559          *
2560          * There are no functional changes due to such spurious event and we
2561          * just need to ignore it.
2562          *
2563          * Refers to:
2564          *
2565          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2566          * operational mode
2567          */
2568         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2569         if ((dwc->revision < DWC3_REVISION_250A) &&
2570                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2571                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2572                                 (next == DWC3_LINK_STATE_RESUME)) {
2573                         dwc3_trace(trace_dwc3_gadget,
2574                                         "ignoring transition U3 -> Resume");
2575                         return;
2576                 }
2577         }
2578
2579         /*
2580          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2581          * on the link partner, the USB session might do multiple entry/exit
2582          * of low power states before a transfer takes place.
2583          *
2584          * Due to this problem, we might experience lower throughput. The
2585          * suggested workaround is to disable DCTL[12:9] bits if we're
2586          * transitioning from U1/U2 to U0 and enable those bits again
2587          * after a transfer completes and there are no pending transfers
2588          * on any of the enabled endpoints.
2589          *
2590          * This is the first half of that workaround.
2591          *
2592          * Refers to:
2593          *
2594          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2595          * core send LGO_Ux entering U0
2596          */
2597         if (dwc->revision < DWC3_REVISION_183A) {
2598                 if (next == DWC3_LINK_STATE_U0) {
2599                         u32     u1u2;
2600                         u32     reg;
2601
2602                         switch (dwc->link_state) {
2603                         case DWC3_LINK_STATE_U1:
2604                         case DWC3_LINK_STATE_U2:
2605                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2606                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2607                                                 | DWC3_DCTL_ACCEPTU2ENA
2608                                                 | DWC3_DCTL_INITU1ENA
2609                                                 | DWC3_DCTL_ACCEPTU1ENA);
2610
2611                                 if (!dwc->u1u2)
2612                                         dwc->u1u2 = reg & u1u2;
2613
2614                                 reg &= ~u1u2;
2615
2616                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2617                                 break;
2618                         default:
2619                                 /* do nothing */
2620                                 break;
2621                         }
2622                 }
2623         }
2624
2625         switch (next) {
2626         case DWC3_LINK_STATE_U1:
2627                 if (dwc->speed == USB_SPEED_SUPER)
2628                         dwc3_suspend_gadget(dwc);
2629                 break;
2630         case DWC3_LINK_STATE_U2:
2631         case DWC3_LINK_STATE_U3:
2632                 dwc3_suspend_gadget(dwc);
2633                 break;
2634         case DWC3_LINK_STATE_RESUME:
2635                 dwc3_resume_gadget(dwc);
2636                 break;
2637         default:
2638                 /* do nothing */
2639                 break;
2640         }
2641
2642         dwc->link_state = next;
2643 }
2644
2645 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2646                 unsigned int evtinfo)
2647 {
2648         unsigned int is_ss = evtinfo & BIT(4);
2649
2650         /**
2651          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2652          * have a known issue which can cause USB CV TD.9.23 to fail
2653          * randomly.
2654          *
2655          * Because of this issue, core could generate bogus hibernation
2656          * events which SW needs to ignore.
2657          *
2658          * Refers to:
2659          *
2660          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2661          * Device Fallback from SuperSpeed
2662          */
2663         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2664                 return;
2665
2666         /* enter hibernation here */
2667 }
2668
2669 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2670                 const struct dwc3_event_devt *event)
2671 {
2672         switch (event->type) {
2673         case DWC3_DEVICE_EVENT_DISCONNECT:
2674                 dwc3_gadget_disconnect_interrupt(dwc);
2675                 break;
2676         case DWC3_DEVICE_EVENT_RESET:
2677                 dwc3_gadget_reset_interrupt(dwc);
2678                 break;
2679         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2680                 dwc3_gadget_conndone_interrupt(dwc);
2681                 break;
2682         case DWC3_DEVICE_EVENT_WAKEUP:
2683                 dwc3_gadget_wakeup_interrupt(dwc);
2684                 break;
2685         case DWC3_DEVICE_EVENT_HIBER_REQ:
2686                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2687                                         "unexpected hibernation event\n"))
2688                         break;
2689
2690                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2691                 break;
2692         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2693                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2694                 break;
2695         case DWC3_DEVICE_EVENT_EOPF:
2696                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2697                 break;
2698         case DWC3_DEVICE_EVENT_SOF:
2699                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2700                 break;
2701         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2702                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2703                 break;
2704         case DWC3_DEVICE_EVENT_CMD_CMPL:
2705                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2706                 break;
2707         case DWC3_DEVICE_EVENT_OVERFLOW:
2708                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2709                 break;
2710         default:
2711                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2712         }
2713 }
2714
2715 static void dwc3_process_event_entry(struct dwc3 *dwc,
2716                 const union dwc3_event *event)
2717 {
2718         trace_dwc3_event(event->raw);
2719
2720         /* Endpoint IRQ, handle it and return early */
2721         if (event->type.is_devspec == 0) {
2722                 /* depevt */
2723                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2724         }
2725
2726         switch (event->type.type) {
2727         case DWC3_EVENT_TYPE_DEV:
2728                 dwc3_gadget_interrupt(dwc, &event->devt);
2729                 break;
2730         /* REVISIT what to do with Carkit and I2C events ? */
2731         default:
2732                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2733         }
2734 }
2735
2736 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2737 {
2738         struct dwc3 *dwc = evt->dwc;
2739         irqreturn_t ret = IRQ_NONE;
2740         int left;
2741         u32 reg;
2742
2743         left = evt->count;
2744
2745         if (!(evt->flags & DWC3_EVENT_PENDING))
2746                 return IRQ_NONE;
2747
2748         while (left > 0) {
2749                 union dwc3_event event;
2750
2751                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2752
2753                 dwc3_process_event_entry(dwc, &event);
2754
2755                 /*
2756                  * FIXME we wrap around correctly to the next entry as
2757                  * almost all entries are 4 bytes in size. There is one
2758                  * entry which has 12 bytes which is a regular entry
2759                  * followed by 8 bytes data. ATM I don't know how
2760                  * things are organized if we get next to the a
2761                  * boundary so I worry about that once we try to handle
2762                  * that.
2763                  */
2764                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2765                 left -= 4;
2766
2767                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2768         }
2769
2770         evt->count = 0;
2771         evt->flags &= ~DWC3_EVENT_PENDING;
2772         ret = IRQ_HANDLED;
2773
2774         /* Unmask interrupt */
2775         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2776         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2777         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2778
2779         return ret;
2780 }
2781
2782 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2783 {
2784         struct dwc3_event_buffer *evt = _evt;
2785         struct dwc3 *dwc = evt->dwc;
2786         unsigned long flags;
2787         irqreturn_t ret = IRQ_NONE;
2788
2789         spin_lock_irqsave(&dwc->lock, flags);
2790         ret = dwc3_process_event_buf(evt);
2791         spin_unlock_irqrestore(&dwc->lock, flags);
2792
2793         return ret;
2794 }
2795
2796 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2797 {
2798         struct dwc3 *dwc = evt->dwc;
2799         u32 count;
2800         u32 reg;
2801
2802         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2803         count &= DWC3_GEVNTCOUNT_MASK;
2804         if (!count)
2805                 return IRQ_NONE;
2806
2807         evt->count = count;
2808         evt->flags |= DWC3_EVENT_PENDING;
2809
2810         /* Mask interrupt */
2811         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2812         reg |= DWC3_GEVNTSIZ_INTMASK;
2813         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2814
2815         return IRQ_WAKE_THREAD;
2816 }
2817
2818 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2819 {
2820         struct dwc3_event_buffer        *evt = _evt;
2821
2822         return dwc3_check_event_buf(evt);
2823 }
2824
2825 /**
2826  * dwc3_gadget_init - Initializes gadget related registers
2827  * @dwc: pointer to our controller context structure
2828  *
2829  * Returns 0 on success otherwise negative errno.
2830  */
2831 int dwc3_gadget_init(struct dwc3 *dwc)
2832 {
2833         int                                     ret;
2834
2835         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2836                         &dwc->ctrl_req_addr, GFP_KERNEL);
2837         if (!dwc->ctrl_req) {
2838                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2839                 ret = -ENOMEM;
2840                 goto err0;
2841         }
2842
2843         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2844                         &dwc->ep0_trb_addr, GFP_KERNEL);
2845         if (!dwc->ep0_trb) {
2846                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2847                 ret = -ENOMEM;
2848                 goto err1;
2849         }
2850
2851         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2852         if (!dwc->setup_buf) {
2853                 ret = -ENOMEM;
2854                 goto err2;
2855         }
2856
2857         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2858                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2859                         GFP_KERNEL);
2860         if (!dwc->ep0_bounce) {
2861                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2862                 ret = -ENOMEM;
2863                 goto err3;
2864         }
2865
2866         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2867         if (!dwc->zlp_buf) {
2868                 ret = -ENOMEM;
2869                 goto err4;
2870         }
2871
2872         dwc->gadget.ops                 = &dwc3_gadget_ops;
2873         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2874         dwc->gadget.sg_supported        = true;
2875         dwc->gadget.name                = "dwc3-gadget";
2876         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2877
2878         /*
2879          * FIXME We might be setting max_speed to <SUPER, however versions
2880          * <2.20a of dwc3 have an issue with metastability (documented
2881          * elsewhere in this driver) which tells us we can't set max speed to
2882          * anything lower than SUPER.
2883          *
2884          * Because gadget.max_speed is only used by composite.c and function
2885          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2886          * to happen so we avoid sending SuperSpeed Capability descriptor
2887          * together with our BOS descriptor as that could confuse host into
2888          * thinking we can handle super speed.
2889          *
2890          * Note that, in fact, we won't even support GetBOS requests when speed
2891          * is less than super speed because we don't have means, yet, to tell
2892          * composite.c that we are USB 2.0 + LPM ECN.
2893          */
2894         if (dwc->revision < DWC3_REVISION_220A)
2895                 dwc3_trace(trace_dwc3_gadget,
2896                                 "Changing max_speed on rev %08x\n",
2897                                 dwc->revision);
2898
2899         dwc->gadget.max_speed           = dwc->maximum_speed;
2900
2901         /*
2902          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2903          * on ep out.
2904          */
2905         dwc->gadget.quirk_ep_out_aligned_size = true;
2906
2907         /*
2908          * REVISIT: Here we should clear all pending IRQs to be
2909          * sure we're starting from a well known location.
2910          */
2911
2912         ret = dwc3_gadget_init_endpoints(dwc);
2913         if (ret)
2914                 goto err5;
2915
2916         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2917         if (ret) {
2918                 dev_err(dwc->dev, "failed to register udc\n");
2919                 goto err5;
2920         }
2921
2922         return 0;
2923
2924 err5:
2925         kfree(dwc->zlp_buf);
2926
2927 err4:
2928         dwc3_gadget_free_endpoints(dwc);
2929         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2930                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2931
2932 err3:
2933         kfree(dwc->setup_buf);
2934
2935 err2:
2936         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2937                         dwc->ep0_trb, dwc->ep0_trb_addr);
2938
2939 err1:
2940         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2941                         dwc->ctrl_req, dwc->ctrl_req_addr);
2942
2943 err0:
2944         return ret;
2945 }
2946
2947 /* -------------------------------------------------------------------------- */
2948
2949 void dwc3_gadget_exit(struct dwc3 *dwc)
2950 {
2951         usb_del_gadget_udc(&dwc->gadget);
2952
2953         dwc3_gadget_free_endpoints(dwc);
2954
2955         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2956                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2957
2958         kfree(dwc->setup_buf);
2959         kfree(dwc->zlp_buf);
2960
2961         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2962                         dwc->ep0_trb, dwc->ep0_trb_addr);
2963
2964         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2965                         dwc->ctrl_req, dwc->ctrl_req_addr);
2966 }
2967
2968 int dwc3_gadget_suspend(struct dwc3 *dwc)
2969 {
2970         int ret;
2971
2972         if (!dwc->gadget_driver)
2973                 return 0;
2974
2975         ret = dwc3_gadget_run_stop(dwc, false, false);
2976         if (ret < 0)
2977                 return ret;
2978
2979         dwc3_disconnect_gadget(dwc);
2980         __dwc3_gadget_stop(dwc);
2981
2982         return 0;
2983 }
2984
2985 int dwc3_gadget_resume(struct dwc3 *dwc)
2986 {
2987         int                     ret;
2988
2989         if (!dwc->gadget_driver)
2990                 return 0;
2991
2992         ret = __dwc3_gadget_start(dwc);
2993         if (ret < 0)
2994                 goto err0;
2995
2996         ret = dwc3_gadget_run_stop(dwc, true, false);
2997         if (ret < 0)
2998                 goto err1;
2999
3000         return 0;
3001
3002 err1:
3003         __dwc3_gadget_stop(dwc);
3004
3005 err0:
3006         return ret;
3007 }