drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_gadget_resize_tx_fifos - reallocate fifo spaces for current use-case
 150  * @dwc: pointer to our context structure
 151  *
 152  * This function will a best effort FIFO allocation in order
 153  * to improve FIFO usage and throughput, while still allowing
 154  * us to enable as many endpoints as possible.
 155  *
 156  * Keep in mind that this operation will be highly dependent
 157  * on the configured size for RAM1 - which contains TxFifo -,
 158  * the amount of endpoints enabled on coreConsultant tool, and
 159  * the width of the Master Bus.
 160  *
 161  * In the ideal world, we would always be able to satisfy the
 162  * following equation:
 163  *
 164  * ((512 + 2 * MDWIDTH-Bytes) + (Number of IN Endpoints - 1) * \
 165  * (3 * (1024 + MDWIDTH-Bytes) + MDWIDTH-Bytes)) / MDWIDTH-Bytes
 166  *
 167  * Unfortunately, due to many variables that's not always the case.
 168  */
 169 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc)
 170 {
 171         int             last_fifo_depth = 0;
 172         int             ram1_depth;
 173         int             fifo_size;
 174         int             mdwidth;
 175         int             num;
 176
 177         if (!dwc->needs_fifo_resize)
 178                 return 0;
 179
 180         ram1_depth = DWC3_RAM1_DEPTH(dwc->hwparams.hwparams7);
 181         mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
 182
 183         /* MDWIDTH is represented in bits, we need it in bytes */
 184         mdwidth >>= 3;
 185
 186         /*
 187          * FIXME For now we will only allocate 1 wMaxPacketSize space
 188          * for each enabled endpoint, later patches will come to
 189          * improve this algorithm so that we better use the internal
 190          * FIFO space
 191          */
 192         for (num = 0; num < dwc->num_in_eps; num++) {
 193                 /* bit0 indicates direction; 1 means IN ep */
 194                 struct dwc3_ep  *dep = dwc->eps[(num << 1) | 1];
 195                 int             mult = 1;
 196                 int             tmp;
 197
 198                 if (!(dep->flags & DWC3_EP_ENABLED))
 199                         continue;
 200
 201                 if (usb_endpoint_xfer_bulk(dep->endpoint.desc)
 202                                 || usb_endpoint_xfer_isoc(dep->endpoint.desc))
 203                         mult = 3;
 204
 205                 /*
 206                  * REVISIT: the following assumes we will always have enough
 207                  * space available on the FIFO RAM for all possible use cases.
 208                  * Make sure that's true somehow and change FIFO allocation
 209                  * accordingly.
 210                  *
 211                  * If we have Bulk or Isochronous endpoints, we want
 212                  * them to be able to be very, very fast. So we're giving
 213                  * those endpoints a fifo_size which is enough for 3 full
 214                  * packets
 215                  */
 216                 tmp = mult * (dep->endpoint.maxpacket + mdwidth);
 217                 tmp += mdwidth;
 218
 219                 fifo_size = DIV_ROUND_UP(tmp, mdwidth);
 220
 221                 fifo_size |= (last_fifo_depth << 16);
 222
 223                 dwc3_trace(trace_dwc3_gadget, "%s: Fifo Addr %04x Size %d",
 224                                 dep->name, last_fifo_depth, fifo_size & 0xffff);
 225
 226                 dwc3_writel(dwc->regs, DWC3_GTXFIFOSIZ(num), fifo_size);
 227
 228                 last_fifo_depth += (fifo_size & 0xffff);
 229         }
 230
 231         return 0;
 232 }
 233
 234 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 235                 int status)
 236 {
 237         struct dwc3                     *dwc = dep->dwc;
 238         int                             i;
 239
 240         if (req->queued) {
 241                 i = 0;
 242                 do {
 243                         dep->busy_slot++;
 244                         /*
 245                          * Skip LINK TRB. We can't use req->trb and check for
 246                          * DWC3_TRBCTL_LINK_TRB because it points the TRB we
 247                          * just completed (not the LINK TRB).
 248                          */
 249                         if (((dep->busy_slot & DWC3_TRB_MASK) ==
 250                                 DWC3_TRB_NUM- 1) &&
 251                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
 252                                 dep->busy_slot++;
 253                 } while(++i < req->request.num_mapped_sgs);
 254                 req->queued = false;
 255         }
 256         list_del(&req->list);
 257         req->trb = NULL;
 258
 259         if (req->request.status == -EINPROGRESS)
 260                 req->request.status = status;
 261
 262         if (dwc->ep0_bounced && dep->number == 0)
 263                 dwc->ep0_bounced = false;
 264         else
 265                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 266                                 req->direction);
 267
 268         trace_dwc3_gadget_giveback(req);
 269
 270         spin_unlock(&dwc->lock);
 271         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 272         spin_lock(&dwc->lock);
 273 }
 274
 275 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 276 {
 277         u32             timeout = 500;
 278         u32             reg;
 279
 280         trace_dwc3_gadget_generic_cmd(cmd, param);
 281
 282         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 283         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 284
 285         do {
 286                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 287                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 288                         dwc3_trace(trace_dwc3_gadget,
 289                                         "Command Complete --> %d",
 290                                         DWC3_DGCMD_STATUS(reg));
 291                         if (DWC3_DGCMD_STATUS(reg))
 292                                 return -EINVAL;
 293                         return 0;
 294                 }
 295
 296                 /*
 297                  * We can't sleep here, because it's also called from
 298                  * interrupt context.
 299                  */
 300                 timeout--;
 301                 if (!timeout) {
 302                         dwc3_trace(trace_dwc3_gadget,
 303                                         "Command Timed Out");
 304                         return -ETIMEDOUT;
 305                 }
 306                 udelay(1);
 307         } while (1);
 308 }
 309
 310 int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
 311                 unsigned cmd, struct dwc3_gadget_ep_cmd_params *params)
 312 {
 313         struct dwc3_ep          *dep = dwc->eps[ep];
 314         u32                     timeout = 500;
 315         u32                     reg;
 316
 317         trace_dwc3_gadget_ep_cmd(dep, cmd, params);
 318
 319         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR0(ep), params->param0);
 320         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR1(ep), params->param1);
 321         dwc3_writel(dwc->regs, DWC3_DEPCMDPAR2(ep), params->param2);
 322
 323         dwc3_writel(dwc->regs, DWC3_DEPCMD(ep), cmd | DWC3_DEPCMD_CMDACT);
 324         do {
 325                 reg = dwc3_readl(dwc->regs, DWC3_DEPCMD(ep));
 326                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 327                         dwc3_trace(trace_dwc3_gadget,
 328                                         "Command Complete --> %d",
 329                                         DWC3_DEPCMD_STATUS(reg));
 330                         if (DWC3_DEPCMD_STATUS(reg))
 331                                 return -EINVAL;
 332                         return 0;
 333                 }
 334
 335                 /*
 336                  * We can't sleep here, because it is also called from
 337                  * interrupt context.
 338                  */
 339                 timeout--;
 340                 if (!timeout) {
 341                         dwc3_trace(trace_dwc3_gadget,
 342                                         "Command Timed Out");
 343                         return -ETIMEDOUT;
 344                 }
 345
 346                 udelay(1);
 347         } while (1);
 348 }
 349
 350 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 351                 struct dwc3_trb *trb)
 352 {
 353         u32             offset = (char *) trb - (char *) dep->trb_pool;
 354
 355         return dep->trb_pool_dma + offset;
 356 }
 357
 358 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 359 {
 360         struct dwc3             *dwc = dep->dwc;
 361
 362         if (dep->trb_pool)
 363                 return 0;
 364
 365         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 366                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 367                         &dep->trb_pool_dma, GFP_KERNEL);
 368         if (!dep->trb_pool) {
 369                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 370                                 dep->name);
 371                 return -ENOMEM;
 372         }
 373
 374         return 0;
 375 }
 376
 377 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 378 {
 379         struct dwc3             *dwc = dep->dwc;
 380
 381         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 382                         dep->trb_pool, dep->trb_pool_dma);
 383
 384         dep->trb_pool = NULL;
 385         dep->trb_pool_dma = 0;
 386 }
 387
 388 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 389
 390 /**
 391  * dwc3_gadget_start_config - Configure EP resources
 392  * @dwc: pointer to our controller context structure
 393  * @dep: endpoint that is being enabled
 394  *
 395  * The assignment of transfer resources cannot perfectly follow the
 396  * data book due to the fact that the controller driver does not have
 397  * all knowledge of the configuration in advance. It is given this
 398  * information piecemeal by the composite gadget framework after every
 399  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 400  * programming model in this scenario can cause errors. For two
 401  * reasons:
 402  *
 403  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 404  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 405  * multiple interfaces.
 406  *
 407  * 2) The databook does not mention doing more DEPXFERCFG for new
 408  * endpoint on alt setting (8.1.6).
 409  *
 410  * The following simplified method is used instead:
 411  *
 412  * All hardware endpoints can be assigned a transfer resource and this
 413  * setting will stay persistent until either a core reset or
 414  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 415  * do DEPXFERCFG for every hardware endpoint as well. We are
 416  * guaranteed that there are as many transfer resources as endpoints.
 417  *
 418  * This function is called for each endpoint when it is being enabled
 419  * but is triggered only when called for EP0-out, which always happens
 420  * first, and which should only happen in one of the above conditions.
 421  */
 422 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 423 {
 424         struct dwc3_gadget_ep_cmd_params params;
 425         u32                     cmd;
 426         int                     i;
 427         int                     ret;
 428
 429         if (dep->number)
 430                 return 0;
 431
 432         memset(&params, 0x00, sizeof(params));
 433         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 434
 435         ret = dwc3_send_gadget_ep_cmd(dwc, 0, cmd, &params);
 436         if (ret)
 437                 return ret;
 438
 439         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 440                 struct dwc3_ep *dep = dwc->eps[i];
 441
 442                 if (!dep)
 443                         continue;
 444
 445                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 446                 if (ret)
 447                         return ret;
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 454                 const struct usb_endpoint_descriptor *desc,
 455                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 456                 bool ignore, bool restore)
 457 {
 458         struct dwc3_gadget_ep_cmd_params params;
 459
 460         memset(&params, 0x00, sizeof(params));
 461
 462         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 463                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 464
 465         /* Burst size is only needed in SuperSpeed mode */
 466         if (dwc->gadget.speed == USB_SPEED_SUPER) {
 467                 u32 burst = dep->endpoint.maxburst - 1;
 468
 469                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst);
 470         }
 471
 472         if (ignore)
 473                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 474
 475         if (restore) {
 476                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 477                 params.param2 |= dep->saved_state;
 478         }
 479
 480         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN
 481                 | DWC3_DEPCFG_XFER_NOT_READY_EN;
 482
 483         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 484                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 485                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 486                 dep->stream_capable = true;
 487         }
 488
 489         if (!usb_endpoint_xfer_control(desc))
 490                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 491
 492         /*
 493          * We are doing 1:1 mapping for endpoints, meaning
 494          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 495          * so on. We consider the direction bit as part of the physical
 496          * endpoint number. So USB endpoint 0x81 is 0x03.
 497          */
 498         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 499
 500         /*
 501          * We must use the lower 16 TX FIFOs even though
 502          * HW might have more
 503          */
 504         if (dep->direction)
 505                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 506
 507         if (desc->bInterval) {
 508                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 509                 dep->interval = 1 << (desc->bInterval - 1);
 510         }
 511
 512         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 513                         DWC3_DEPCMD_SETEPCONFIG, &params);
 514 }
 515
 516 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 517 {
 518         struct dwc3_gadget_ep_cmd_params params;
 519
 520         memset(&params, 0x00, sizeof(params));
 521
 522         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 523
 524         return dwc3_send_gadget_ep_cmd(dwc, dep->number,
 525                         DWC3_DEPCMD_SETTRANSFRESOURCE, &params);
 526 }
 527
 528 /**
 529  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 530  * @dep: endpoint to be initialized
 531  * @desc: USB Endpoint Descriptor
 532  *
 533  * Caller should take care of locking
 534  */
 535 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 536                 const struct usb_endpoint_descriptor *desc,
 537                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 538                 bool ignore, bool restore)
 539 {
 540         struct dwc3             *dwc = dep->dwc;
 541         u32                     reg;
 542         int                     ret;
 543
 544         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 545
 546         if (!(dep->flags & DWC3_EP_ENABLED)) {
 547                 ret = dwc3_gadget_start_config(dwc, dep);
 548                 if (ret)
 549                         return ret;
 550         }
 551
 552         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 553                         restore);
 554         if (ret)
 555                 return ret;
 556
 557         if (!(dep->flags & DWC3_EP_ENABLED)) {
 558                 struct dwc3_trb *trb_st_hw;
 559                 struct dwc3_trb *trb_link;
 560
 561                 dep->endpoint.desc = desc;
 562                 dep->comp_desc = comp_desc;
 563                 dep->type = usb_endpoint_type(desc);
 564                 dep->flags |= DWC3_EP_ENABLED;
 565
 566                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 567                 reg |= DWC3_DALEPENA_EP(dep->number);
 568                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 569
 570                 if (!usb_endpoint_xfer_isoc(desc))
 571                         return 0;
 572
 573                 /* Link TRB for ISOC. The HWO bit is never reset */
 574                 trb_st_hw = &dep->trb_pool[0];
 575
 576                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 577                 memset(trb_link, 0, sizeof(*trb_link));
 578
 579                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 580                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 581                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 582                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 583         }
 584
 585         switch (usb_endpoint_type(desc)) {
 586         case USB_ENDPOINT_XFER_CONTROL:
 587                 strlcat(dep->name, "-control", sizeof(dep->name));
 588                 break;
 589         case USB_ENDPOINT_XFER_ISOC:
 590                 strlcat(dep->name, "-isoc", sizeof(dep->name));
 591                 break;
 592         case USB_ENDPOINT_XFER_BULK:
 593                 strlcat(dep->name, "-bulk", sizeof(dep->name));
 594                 break;
 595         case USB_ENDPOINT_XFER_INT:
 596                 strlcat(dep->name, "-int", sizeof(dep->name));
 597                 break;
 598         default:
 599                 dev_err(dwc->dev, "invalid endpoint transfer type\n");
 600         }
 601
 602         return 0;
 603 }
 604
 605 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 606 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 607 {
 608         struct dwc3_request             *req;
 609
 610         if (!list_empty(&dep->req_queued)) {
 611                 dwc3_stop_active_transfer(dwc, dep->number, true);
 612
 613                 /* - giveback all requests to gadget driver */
 614                 while (!list_empty(&dep->req_queued)) {
 615                         req = next_request(&dep->req_queued);
 616
 617                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 618                 }
 619         }
 620
 621         while (!list_empty(&dep->request_list)) {
 622                 req = next_request(&dep->request_list);
 623
 624                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 625         }
 626 }
 627
 628 /**
 629  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 630  * @dep: the endpoint to disable
 631  *
 632  * This function also removes requests which are currently processed ny the
 633  * hardware and those which are not yet scheduled.
 634  * Caller should take care of locking.
 635  */
 636 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 637 {
 638         struct dwc3             *dwc = dep->dwc;
 639         u32                     reg;
 640
 641         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 642
 643         dwc3_remove_requests(dwc, dep);
 644
 645         /* make sure HW endpoint isn't stalled */
 646         if (dep->flags & DWC3_EP_STALL)
 647                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 648
 649         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 650         reg &= ~DWC3_DALEPENA_EP(dep->number);
 651         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 652
 653         dep->stream_capable = false;
 654         dep->endpoint.desc = NULL;
 655         dep->comp_desc = NULL;
 656         dep->type = 0;
 657         dep->flags = 0;
 658
 659         snprintf(dep->name, sizeof(dep->name), "ep%d%s",
 660                         dep->number >> 1,
 661                         (dep->number & 1) ? "in" : "out");
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         trace_dwc3_alloc_request(req);
 755
 756         return &req->request;
 757 }
 758
 759 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 760                 struct usb_request *request)
 761 {
 762         struct dwc3_request             *req = to_dwc3_request(request);
 763
 764         trace_dwc3_free_request(req);
 765         kfree(req);
 766 }
 767
 768 /**
 769  * dwc3_prepare_one_trb - setup one TRB from one request
 770  * @dep: endpoint for which this request is prepared
 771  * @req: dwc3_request pointer
 772  */
 773 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 774                 struct dwc3_request *req, dma_addr_t dma,
 775                 unsigned length, unsigned last, unsigned chain, unsigned node)
 776 {
 777         struct dwc3_trb         *trb;
 778
 779         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 780                         dep->name, req, (unsigned long long) dma,
 781                         length, last ? " last" : "",
 782                         chain ? " chain" : "");
 783
 784
 785         trb = &dep->trb_pool[dep->free_slot & DWC3_TRB_MASK];
 786
 787         if (!req->trb) {
 788                 dwc3_gadget_move_request_queued(req);
 789                 req->trb = trb;
 790                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 791                 req->start_slot = dep->free_slot & DWC3_TRB_MASK;
 792         }
 793
 794         dep->free_slot++;
 795         /* Skip the LINK-TRB on ISOC */
 796         if (((dep->free_slot & DWC3_TRB_MASK) == DWC3_TRB_NUM - 1) &&
 797                         usb_endpoint_xfer_isoc(dep->endpoint.desc))
 798                 dep->free_slot++;
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814                 break;
 815
 816         case USB_ENDPOINT_XFER_BULK:
 817         case USB_ENDPOINT_XFER_INT:
 818                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 819                 break;
 820         default:
 821                 /*
 822                  * This is only possible with faulty memory because we
 823                  * checked it already :)
 824                  */
 825                 BUG();
 826         }
 827
 828         if (!req->request.no_interrupt && !chain)
 829                 trb->ctrl |= DWC3_TRB_CTRL_IOC;
 830
 831         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 832                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 833                 trb->ctrl |= DWC3_TRB_CTRL_CSP;
 834         } else if (last) {
 835                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 836         }
 837
 838         if (chain)
 839                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 840
 841         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 842                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 843
 844         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 845
 846         trace_dwc3_prepare_trb(dep, trb);
 847 }
 848
 849 /*
 850  * dwc3_prepare_trbs - setup TRBs from requests
 851  * @dep: endpoint for which requests are being prepared
 852  * @starting: true if the endpoint is idle and no requests are queued.
 853  *
 854  * The function goes through the requests list and sets up TRBs for the
 855  * transfers. The function returns once there are no more TRBs available or
 856  * it runs out of requests.
 857  */
 858 static void dwc3_prepare_trbs(struct dwc3_ep *dep, bool starting)
 859 {
 860         struct dwc3_request     *req, *n;
 861         u32                     trbs_left;
 862         u32                     max;
 863         unsigned int            last_one = 0;
 864
 865         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 866
 867         /* the first request must not be queued */
 868         trbs_left = (dep->busy_slot - dep->free_slot) & DWC3_TRB_MASK;
 869
 870         /* Can't wrap around on a non-isoc EP since there's no link TRB */
 871         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 872                 max = DWC3_TRB_NUM - (dep->free_slot & DWC3_TRB_MASK);
 873                 if (trbs_left > max)
 874                         trbs_left = max;
 875         }
 876
 877         /*
 878          * If busy & slot are equal than it is either full or empty. If we are
 879          * starting to process requests then we are empty. Otherwise we are
 880          * full and don't do anything
 881          */
 882         if (!trbs_left) {
 883                 if (!starting)
 884                         return;
 885                 trbs_left = DWC3_TRB_NUM;
 886                 /*
 887                  * In case we start from scratch, we queue the ISOC requests
 888                  * starting from slot 1. This is done because we use ring
 889                  * buffer and have no LST bit to stop us. Instead, we place
 890                  * IOC bit every TRB_NUM/4. We try to avoid having an interrupt
 891                  * after the first request so we start at slot 1 and have
 892                  * 7 requests proceed before we hit the first IOC.
 893                  * Other transfer types don't use the ring buffer and are
 894                  * processed from the first TRB until the last one. Since we
 895                  * don't wrap around we have to start at the beginning.
 896                  */
 897                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
 898                         dep->busy_slot = 1;
 899                         dep->free_slot = 1;
 900                 } else {
 901                         dep->busy_slot = 0;
 902                         dep->free_slot = 0;
 903                 }
 904         }
 905
 906         /* The last TRB is a link TRB, not used for xfer */
 907         if ((trbs_left <= 1) && usb_endpoint_xfer_isoc(dep->endpoint.desc))
 908                 return;
 909
 910         list_for_each_entry_safe(req, n, &dep->request_list, list) {
 911                 unsigned        length;
 912                 dma_addr_t      dma;
 913                 last_one = false;
 914
 915                 if (req->request.num_mapped_sgs > 0) {
 916                         struct usb_request *request = &req->request;
 917                         struct scatterlist *sg = request->sg;
 918                         struct scatterlist *s;
 919                         int             i;
 920
 921                         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 922                                 unsigned chain = true;
 923
 924                                 length = sg_dma_len(s);
 925                                 dma = sg_dma_address(s);
 926
 927                                 if (i == (request->num_mapped_sgs - 1) ||
 928                                                 sg_is_last(s)) {
 929                                         if (list_empty(&dep->request_list))
 930                                                 last_one = true;
 931                                         chain = false;
 932                                 }
 933
 934                                 trbs_left--;
 935                                 if (!trbs_left)
 936                                         last_one = true;
 937
 938                                 if (last_one)
 939                                         chain = false;
 940
 941                                 dwc3_prepare_one_trb(dep, req, dma, length,
 942                                                 last_one, chain, i);
 943
 944                                 if (last_one)
 945                                         break;
 946                         }
 947
 948                         if (last_one)
 949                                 break;
 950                 } else {
 951                         dma = req->request.dma;
 952                         length = req->request.length;
 953                         trbs_left--;
 954
 955                         if (!trbs_left)
 956                                 last_one = 1;
 957
 958                         /* Is this the last request? */
 959                         if (list_is_last(&req->list, &dep->request_list))
 960                                 last_one = 1;
 961
 962                         dwc3_prepare_one_trb(dep, req, dma, length,
 963                                         last_one, false, 0);
 964
 965                         if (last_one)
 966                                 break;
 967                 }
 968         }
 969 }
 970
 971 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param,
 972                 int start_new)
 973 {
 974         struct dwc3_gadget_ep_cmd_params params;
 975         struct dwc3_request             *req;
 976         struct dwc3                     *dwc = dep->dwc;
 977         int                             ret;
 978         u32                             cmd;
 979
 980         if (start_new && (dep->flags & DWC3_EP_BUSY)) {
 981                 dwc3_trace(trace_dwc3_gadget, "%s: endpoint busy", dep->name);
 982                 return -EBUSY;
 983         }
 984
 985         /*
 986          * If we are getting here after a short-out-packet we don't enqueue any
 987          * new requests as we try to set the IOC bit only on the last request.
 988          */
 989         if (start_new) {
 990                 if (list_empty(&dep->req_queued))
 991                         dwc3_prepare_trbs(dep, start_new);
 992
 993                 /* req points to the first request which will be sent */
 994                 req = next_request(&dep->req_queued);
 995         } else {
 996                 dwc3_prepare_trbs(dep, start_new);
 997
 998                 /*
 999                  * req points to the first request where HWO changed from 0 to 1
1000                  */
1001                 req = next_request(&dep->req_queued);
1002         }
1003         if (!req) {
1004                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1005                 return 0;
1006         }
1007
1008         memset(&params, 0, sizeof(params));
1009
1010         if (start_new) {
1011                 params.param0 = upper_32_bits(req->trb_dma);
1012                 params.param1 = lower_32_bits(req->trb_dma);
1013                 cmd = DWC3_DEPCMD_STARTTRANSFER;
1014         } else {
1015                 cmd = DWC3_DEPCMD_UPDATETRANSFER;
1016         }
1017
1018         cmd |= DWC3_DEPCMD_PARAM(cmd_param);
1019         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
1020         if (ret < 0) {
1021                 /*
1022                  * FIXME we need to iterate over the list of requests
1023                  * here and stop, unmap, free and del each of the linked
1024                  * requests instead of what we do now.
1025                  */
1026                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1027                                 req->direction);
1028                 list_del(&req->list);
1029                 return ret;
1030         }
1031
1032         dep->flags |= DWC3_EP_BUSY;
1033
1034         if (start_new) {
1035                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
1036                                 dep->number);
1037                 WARN_ON_ONCE(!dep->resource_index);
1038         }
1039
1040         return 0;
1041 }
1042
1043 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1044                 struct dwc3_ep *dep, u32 cur_uf)
1045 {
1046         u32 uf;
1047
1048         if (list_empty(&dep->request_list)) {
1049                 dwc3_trace(trace_dwc3_gadget,
1050                                 "ISOC ep %s run out for requests",
1051                                 dep->name);
1052                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1053                 return;
1054         }
1055
1056         /* 4 micro frames in the future */
1057         uf = cur_uf + dep->interval * 4;
1058
1059         __dwc3_gadget_kick_transfer(dep, uf, 1);
1060 }
1061
1062 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1063                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1064 {
1065         u32 cur_uf, mask;
1066
1067         mask = ~(dep->interval - 1);
1068         cur_uf = event->parameters & mask;
1069
1070         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1071 }
1072
1073 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1074 {
1075         struct dwc3             *dwc = dep->dwc;
1076         int                     ret;
1077
1078         if (!dep->endpoint.desc) {
1079                 dwc3_trace(trace_dwc3_gadget,
1080                                 "trying to queue request %p to disabled %s\n",
1081                                 &req->request, dep->endpoint.name);
1082                 return -ESHUTDOWN;
1083         }
1084
1085         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1086                                 &req->request, req->dep->name)) {
1087                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'\n",
1088                                 &req->request, req->dep->name);
1089                 return -EINVAL;
1090         }
1091
1092         req->request.actual     = 0;
1093         req->request.status     = -EINPROGRESS;
1094         req->direction          = dep->direction;
1095         req->epnum              = dep->number;
1096
1097         trace_dwc3_ep_queue(req);
1098
1099         /*
1100          * We only add to our list of requests now and
1101          * start consuming the list once we get XferNotReady
1102          * IRQ.
1103          *
1104          * That way, we avoid doing anything that we don't need
1105          * to do now and defer it until the point we receive a
1106          * particular token from the Host side.
1107          *
1108          * This will also avoid Host cancelling URBs due to too
1109          * many NAKs.
1110          */
1111         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1112                         dep->direction);
1113         if (ret)
1114                 return ret;
1115
1116         list_add_tail(&req->list, &dep->request_list);
1117
1118         /*
1119          * If there are no pending requests and the endpoint isn't already
1120          * busy, we will just start the request straight away.
1121          *
1122          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1123          * little bit faster.
1124          */
1125         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1126                         !usb_endpoint_xfer_int(dep->endpoint.desc) &&
1127                         !(dep->flags & DWC3_EP_BUSY)) {
1128                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1129                 goto out;
1130         }
1131
1132         /*
1133          * There are a few special cases:
1134          *
1135          * 1. XferNotReady with empty list of requests. We need to kick the
1136          *    transfer here in that situation, otherwise we will be NAKing
1137          *    forever. If we get XferNotReady before gadget driver has a
1138          *    chance to queue a request, we will ACK the IRQ but won't be
1139          *    able to receive the data until the next request is queued.
1140          *    The following code is handling exactly that.
1141          *
1142          */
1143         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1144                 /*
1145                  * If xfernotready is already elapsed and it is a case
1146                  * of isoc transfer, then issue END TRANSFER, so that
1147                  * you can receive xfernotready again and can have
1148                  * notion of current microframe.
1149                  */
1150                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1151                         if (list_empty(&dep->req_queued)) {
1152                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1153                                 dep->flags = DWC3_EP_ENABLED;
1154                         }
1155                         return 0;
1156                 }
1157
1158                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1159                 if (!ret)
1160                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1161
1162                 goto out;
1163         }
1164
1165         /*
1166          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1167          *    kick the transfer here after queuing a request, otherwise the
1168          *    core may not see the modified TRB(s).
1169          */
1170         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1171                         (dep->flags & DWC3_EP_BUSY) &&
1172                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1173                 WARN_ON_ONCE(!dep->resource_index);
1174                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index,
1175                                 false);
1176                 goto out;
1177         }
1178
1179         /*
1180          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1181          * right away, otherwise host will not know we have streams to be
1182          * handled.
1183          */
1184         if (dep->stream_capable)
1185                 ret = __dwc3_gadget_kick_transfer(dep, 0, true);
1186
1187 out:
1188         if (ret && ret != -EBUSY)
1189                 dwc3_trace(trace_dwc3_gadget,
1190                                 "%s: failed to kick transfers\n",
1191                                 dep->name);
1192         if (ret == -EBUSY)
1193                 ret = 0;
1194
1195         return ret;
1196 }
1197
1198 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1199                 struct usb_request *request)
1200 {
1201         dwc3_gadget_ep_free_request(ep, request);
1202 }
1203
1204 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1205 {
1206         struct dwc3_request             *req;
1207         struct usb_request              *request;
1208         struct usb_ep                   *ep = &dep->endpoint;
1209
1210         dwc3_trace(trace_dwc3_gadget, "queueing ZLP\n");
1211         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1212         if (!request)
1213                 return -ENOMEM;
1214
1215         request->length = 0;
1216         request->buf = dwc->zlp_buf;
1217         request->complete = __dwc3_gadget_ep_zlp_complete;
1218
1219         req = to_dwc3_request(request);
1220
1221         return __dwc3_gadget_ep_queue(dep, req);
1222 }
1223
1224 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1225         gfp_t gfp_flags)
1226 {
1227         struct dwc3_request             *req = to_dwc3_request(request);
1228         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1229         struct dwc3                     *dwc = dep->dwc;
1230
1231         unsigned long                   flags;
1232
1233         int                             ret;
1234
1235         spin_lock_irqsave(&dwc->lock, flags);
1236         ret = __dwc3_gadget_ep_queue(dep, req);
1237
1238         /*
1239          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1240          * setting request->zero, instead of doing magic, we will just queue an
1241          * extra usb_request ourselves so that it gets handled the same way as
1242          * any other request.
1243          */
1244         if (ret == 0 && request->zero && request->length &&
1245             (request->length % ep->maxpacket == 0))
1246                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1247
1248         spin_unlock_irqrestore(&dwc->lock, flags);
1249
1250         return ret;
1251 }
1252
1253 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1254                 struct usb_request *request)
1255 {
1256         struct dwc3_request             *req = to_dwc3_request(request);
1257         struct dwc3_request             *r = NULL;
1258
1259         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1260         struct dwc3                     *dwc = dep->dwc;
1261
1262         unsigned long                   flags;
1263         int                             ret = 0;
1264
1265         trace_dwc3_ep_dequeue(req);
1266
1267         spin_lock_irqsave(&dwc->lock, flags);
1268
1269         list_for_each_entry(r, &dep->request_list, list) {
1270                 if (r == req)
1271                         break;
1272         }
1273
1274         if (r != req) {
1275                 list_for_each_entry(r, &dep->req_queued, list) {
1276                         if (r == req)
1277                                 break;
1278                 }
1279                 if (r == req) {
1280                         /* wait until it is processed */
1281                         dwc3_stop_active_transfer(dwc, dep->number, true);
1282                         goto out1;
1283                 }
1284                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1285                                 request, ep->name);
1286                 ret = -EINVAL;
1287                 goto out0;
1288         }
1289
1290 out1:
1291         /* giveback the request */
1292         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1293
1294 out0:
1295         spin_unlock_irqrestore(&dwc->lock, flags);
1296
1297         return ret;
1298 }
1299
1300 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1301 {
1302         struct dwc3_gadget_ep_cmd_params        params;
1303         struct dwc3                             *dwc = dep->dwc;
1304         int                                     ret;
1305
1306         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1307                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1308                 return -EINVAL;
1309         }
1310
1311         memset(&params, 0x00, sizeof(params));
1312
1313         if (value) {
1314                 if (!protocol && ((dep->direction && dep->flags & DWC3_EP_BUSY) ||
1315                                 (!list_empty(&dep->req_queued) ||
1316                                  !list_empty(&dep->request_list)))) {
1317                         dwc3_trace(trace_dwc3_gadget,
1318                                         "%s: pending request, cannot halt\n",
1319                                         dep->name);
1320                         return -EAGAIN;
1321                 }
1322
1323                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1324                         DWC3_DEPCMD_SETSTALL, &params);
1325                 if (ret)
1326                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1327                                         dep->name);
1328                 else
1329                         dep->flags |= DWC3_EP_STALL;
1330         } else {
1331                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
1332                         DWC3_DEPCMD_CLEARSTALL, &params);
1333                 if (ret)
1334                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1335                                         dep->name);
1336                 else
1337                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1338         }
1339
1340         return ret;
1341 }
1342
1343 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1344 {
1345         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1346         struct dwc3                     *dwc = dep->dwc;
1347
1348         unsigned long                   flags;
1349
1350         int                             ret;
1351
1352         spin_lock_irqsave(&dwc->lock, flags);
1353         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1354         spin_unlock_irqrestore(&dwc->lock, flags);
1355
1356         return ret;
1357 }
1358
1359 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1360 {
1361         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1362         struct dwc3                     *dwc = dep->dwc;
1363         unsigned long                   flags;
1364         int                             ret;
1365
1366         spin_lock_irqsave(&dwc->lock, flags);
1367         dep->flags |= DWC3_EP_WEDGE;
1368
1369         if (dep->number == 0 || dep->number == 1)
1370                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1371         else
1372                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1373         spin_unlock_irqrestore(&dwc->lock, flags);
1374
1375         return ret;
1376 }
1377
1378 /* -------------------------------------------------------------------------- */
1379
1380 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1381         .bLength        = USB_DT_ENDPOINT_SIZE,
1382         .bDescriptorType = USB_DT_ENDPOINT,
1383         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1384 };
1385
1386 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1387         .enable         = dwc3_gadget_ep0_enable,
1388         .disable        = dwc3_gadget_ep0_disable,
1389         .alloc_request  = dwc3_gadget_ep_alloc_request,
1390         .free_request   = dwc3_gadget_ep_free_request,
1391         .queue          = dwc3_gadget_ep0_queue,
1392         .dequeue        = dwc3_gadget_ep_dequeue,
1393         .set_halt       = dwc3_gadget_ep0_set_halt,
1394         .set_wedge      = dwc3_gadget_ep_set_wedge,
1395 };
1396
1397 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1398         .enable         = dwc3_gadget_ep_enable,
1399         .disable        = dwc3_gadget_ep_disable,
1400         .alloc_request  = dwc3_gadget_ep_alloc_request,
1401         .free_request   = dwc3_gadget_ep_free_request,
1402         .queue          = dwc3_gadget_ep_queue,
1403         .dequeue        = dwc3_gadget_ep_dequeue,
1404         .set_halt       = dwc3_gadget_ep_set_halt,
1405         .set_wedge      = dwc3_gadget_ep_set_wedge,
1406 };
1407
1408 /* -------------------------------------------------------------------------- */
1409
1410 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1411 {
1412         struct dwc3             *dwc = gadget_to_dwc(g);
1413         u32                     reg;
1414
1415         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1416         return DWC3_DSTS_SOFFN(reg);
1417 }
1418
1419 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1420 {
1421         struct dwc3             *dwc = gadget_to_dwc(g);
1422
1423         unsigned long           timeout;
1424         unsigned long           flags;
1425
1426         u32                     reg;
1427
1428         int                     ret = 0;
1429
1430         u8                      link_state;
1431         u8                      speed;
1432
1433         spin_lock_irqsave(&dwc->lock, flags);
1434
1435         /*
1436          * According to the Databook Remote wakeup request should
1437          * be issued only when the device is in early suspend state.
1438          *
1439          * We can check that via USB Link State bits in DSTS register.
1440          */
1441         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1442
1443         speed = reg & DWC3_DSTS_CONNECTSPD;
1444         if (speed == DWC3_DSTS_SUPERSPEED) {
1445                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed\n");
1446                 ret = -EINVAL;
1447                 goto out;
1448         }
1449
1450         link_state = DWC3_DSTS_USBLNKST(reg);
1451
1452         switch (link_state) {
1453         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1454         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1455                 break;
1456         default:
1457                 dwc3_trace(trace_dwc3_gadget,
1458                                 "can't wakeup from '%s'\n",
1459                                 dwc3_gadget_link_string(link_state));
1460                 ret = -EINVAL;
1461                 goto out;
1462         }
1463
1464         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1465         if (ret < 0) {
1466                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1467                 goto out;
1468         }
1469
1470         /* Recent versions do this automatically */
1471         if (dwc->revision < DWC3_REVISION_194A) {
1472                 /* write zeroes to Link Change Request */
1473                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1474                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1475                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1476         }
1477
1478         /* poll until Link State changes to ON */
1479         timeout = jiffies + msecs_to_jiffies(100);
1480
1481         while (!time_after(jiffies, timeout)) {
1482                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1483
1484                 /* in HS, means ON */
1485                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1486                         break;
1487         }
1488
1489         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1490                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1491                 ret = -EINVAL;
1492         }
1493
1494 out:
1495         spin_unlock_irqrestore(&dwc->lock, flags);
1496
1497         return ret;
1498 }
1499
1500 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1501                 int is_selfpowered)
1502 {
1503         struct dwc3             *dwc = gadget_to_dwc(g);
1504         unsigned long           flags;
1505
1506         spin_lock_irqsave(&dwc->lock, flags);
1507         g->is_selfpowered = !!is_selfpowered;
1508         spin_unlock_irqrestore(&dwc->lock, flags);
1509
1510         return 0;
1511 }
1512
1513 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1514 {
1515         u32                     reg;
1516         u32                     timeout = 500;
1517
1518         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1519         if (is_on) {
1520                 if (dwc->revision <= DWC3_REVISION_187A) {
1521                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1522                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1523                 }
1524
1525                 if (dwc->revision >= DWC3_REVISION_194A)
1526                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1527                 reg |= DWC3_DCTL_RUN_STOP;
1528
1529                 if (dwc->has_hibernation)
1530                         reg |= DWC3_DCTL_KEEP_CONNECT;
1531
1532                 dwc->pullups_connected = true;
1533         } else {
1534                 reg &= ~DWC3_DCTL_RUN_STOP;
1535
1536                 if (dwc->has_hibernation && !suspend)
1537                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1538
1539                 dwc->pullups_connected = false;
1540         }
1541
1542         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1543
1544         do {
1545                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1546                 if (is_on) {
1547                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1548                                 break;
1549                 } else {
1550                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1551                                 break;
1552                 }
1553                 timeout--;
1554                 if (!timeout)
1555                         return -ETIMEDOUT;
1556                 udelay(1);
1557         } while (1);
1558
1559         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1560                         dwc->gadget_driver
1561                         ? dwc->gadget_driver->function : "no-function",
1562                         is_on ? "connect" : "disconnect");
1563
1564         return 0;
1565 }
1566
1567 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1568 {
1569         struct dwc3             *dwc = gadget_to_dwc(g);
1570         unsigned long           flags;
1571         int                     ret;
1572
1573         is_on = !!is_on;
1574
1575         spin_lock_irqsave(&dwc->lock, flags);
1576         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1577         spin_unlock_irqrestore(&dwc->lock, flags);
1578
1579         return ret;
1580 }
1581
1582 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1583 {
1584         u32                     reg;
1585
1586         /* Enable all but Start and End of Frame IRQs */
1587         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1588                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1589                         DWC3_DEVTEN_CMDCMPLTEN |
1590                         DWC3_DEVTEN_ERRTICERREN |
1591                         DWC3_DEVTEN_WKUPEVTEN |
1592                         DWC3_DEVTEN_ULSTCNGEN |
1593                         DWC3_DEVTEN_CONNECTDONEEN |
1594                         DWC3_DEVTEN_USBRSTEN |
1595                         DWC3_DEVTEN_DISCONNEVTEN);
1596
1597         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1598 }
1599
1600 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1601 {
1602         /* mask all interrupts */
1603         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1604 }
1605
1606 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1607 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1608
1609 static int dwc3_gadget_start(struct usb_gadget *g,
1610                 struct usb_gadget_driver *driver)
1611 {
1612         struct dwc3             *dwc = gadget_to_dwc(g);
1613         struct dwc3_ep          *dep;
1614         unsigned long           flags;
1615         int                     ret = 0;
1616         int                     irq;
1617         u32                     reg;
1618
1619         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1620         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1621                         IRQF_SHARED, "dwc3", dwc);
1622         if (ret) {
1623                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1624                                 irq, ret);
1625                 goto err0;
1626         }
1627
1628         spin_lock_irqsave(&dwc->lock, flags);
1629
1630         if (dwc->gadget_driver) {
1631                 dev_err(dwc->dev, "%s is already bound to %s\n",
1632                                 dwc->gadget.name,
1633                                 dwc->gadget_driver->driver.name);
1634                 ret = -EBUSY;
1635                 goto err1;
1636         }
1637
1638         dwc->gadget_driver      = driver;
1639
1640         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1641         reg &= ~(DWC3_DCFG_SPEED_MASK);
1642
1643         /**
1644          * WORKAROUND: DWC3 revision < 2.20a have an issue
1645          * which would cause metastability state on Run/Stop
1646          * bit if we try to force the IP to USB2-only mode.
1647          *
1648          * Because of that, we cannot configure the IP to any
1649          * speed other than the SuperSpeed
1650          *
1651          * Refers to:
1652          *
1653          * STAR#9000525659: Clock Domain Crossing on DCTL in
1654          * USB 2.0 Mode
1655          */
1656         if (dwc->revision < DWC3_REVISION_220A) {
1657                 reg |= DWC3_DCFG_SUPERSPEED;
1658         } else {
1659                 switch (dwc->maximum_speed) {
1660                 case USB_SPEED_LOW:
1661                         reg |= DWC3_DSTS_LOWSPEED;
1662                         break;
1663                 case USB_SPEED_FULL:
1664                         reg |= DWC3_DSTS_FULLSPEED1;
1665                         break;
1666                 case USB_SPEED_HIGH:
1667                         reg |= DWC3_DSTS_HIGHSPEED;
1668                         break;
1669                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1670                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1671                 default:
1672                         reg |= DWC3_DSTS_SUPERSPEED;
1673                 }
1674         }
1675         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1676
1677         /* Start with SuperSpeed Default */
1678         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1679
1680         dep = dwc->eps[0];
1681         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1682                         false);
1683         if (ret) {
1684                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1685                 goto err2;
1686         }
1687
1688         dep = dwc->eps[1];
1689         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1690                         false);
1691         if (ret) {
1692                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1693                 goto err3;
1694         }
1695
1696         /* begin to receive SETUP packets */
1697         dwc->ep0state = EP0_SETUP_PHASE;
1698         dwc3_ep0_out_start(dwc);
1699
1700         dwc3_gadget_enable_irq(dwc);
1701
1702         spin_unlock_irqrestore(&dwc->lock, flags);
1703
1704         return 0;
1705
1706 err3:
1707         __dwc3_gadget_ep_disable(dwc->eps[0]);
1708
1709 err2:
1710         dwc->gadget_driver = NULL;
1711
1712 err1:
1713         spin_unlock_irqrestore(&dwc->lock, flags);
1714
1715         free_irq(irq, dwc);
1716
1717 err0:
1718         return ret;
1719 }
1720
1721 static int dwc3_gadget_stop(struct usb_gadget *g)
1722 {
1723         struct dwc3             *dwc = gadget_to_dwc(g);
1724         unsigned long           flags;
1725         int                     irq;
1726
1727         spin_lock_irqsave(&dwc->lock, flags);
1728
1729         dwc3_gadget_disable_irq(dwc);
1730         __dwc3_gadget_ep_disable(dwc->eps[0]);
1731         __dwc3_gadget_ep_disable(dwc->eps[1]);
1732
1733         dwc->gadget_driver      = NULL;
1734
1735         spin_unlock_irqrestore(&dwc->lock, flags);
1736
1737         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1738         free_irq(irq, dwc);
1739
1740         return 0;
1741 }
1742
1743 static const struct usb_gadget_ops dwc3_gadget_ops = {
1744         .get_frame              = dwc3_gadget_get_frame,
1745         .wakeup                 = dwc3_gadget_wakeup,
1746         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1747         .pullup                 = dwc3_gadget_pullup,
1748         .udc_start              = dwc3_gadget_start,
1749         .udc_stop               = dwc3_gadget_stop,
1750 };
1751
1752 /* -------------------------------------------------------------------------- */
1753
1754 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1755                 u8 num, u32 direction)
1756 {
1757         struct dwc3_ep                  *dep;
1758         u8                              i;
1759
1760         for (i = 0; i < num; i++) {
1761                 u8 epnum = (i << 1) | (!!direction);
1762
1763                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1764                 if (!dep)
1765                         return -ENOMEM;
1766
1767                 dep->dwc = dwc;
1768                 dep->number = epnum;
1769                 dep->direction = !!direction;
1770                 dwc->eps[epnum] = dep;
1771
1772                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1773                                 (epnum & 1) ? "in" : "out");
1774
1775                 dep->endpoint.name = dep->name;
1776
1777                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1778
1779                 if (epnum == 0 || epnum == 1) {
1780                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1781                         dep->endpoint.maxburst = 1;
1782                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1783                         if (!epnum)
1784                                 dwc->gadget.ep0 = &dep->endpoint;
1785                 } else {
1786                         int             ret;
1787
1788                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1789                         dep->endpoint.max_streams = 15;
1790                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1791                         list_add_tail(&dep->endpoint.ep_list,
1792                                         &dwc->gadget.ep_list);
1793
1794                         ret = dwc3_alloc_trb_pool(dep);
1795                         if (ret)
1796                                 return ret;
1797                 }
1798
1799                 if (epnum == 0 || epnum == 1) {
1800                         dep->endpoint.caps.type_control = true;
1801                 } else {
1802                         dep->endpoint.caps.type_iso = true;
1803                         dep->endpoint.caps.type_bulk = true;
1804                         dep->endpoint.caps.type_int = true;
1805                 }
1806
1807                 dep->endpoint.caps.dir_in = !!direction;
1808                 dep->endpoint.caps.dir_out = !direction;
1809
1810                 INIT_LIST_HEAD(&dep->request_list);
1811                 INIT_LIST_HEAD(&dep->req_queued);
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1818 {
1819         int                             ret;
1820
1821         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1822
1823         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1824         if (ret < 0) {
1825                 dwc3_trace(trace_dwc3_gadget,
1826                                 "failed to allocate OUT endpoints");
1827                 return ret;
1828         }
1829
1830         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1831         if (ret < 0) {
1832                 dwc3_trace(trace_dwc3_gadget,
1833                                 "failed to allocate IN endpoints");
1834                 return ret;
1835         }
1836
1837         return 0;
1838 }
1839
1840 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1841 {
1842         struct dwc3_ep                  *dep;
1843         u8                              epnum;
1844
1845         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1846                 dep = dwc->eps[epnum];
1847                 if (!dep)
1848                         continue;
1849                 /*
1850                  * Physical endpoints 0 and 1 are special; they form the
1851                  * bi-directional USB endpoint 0.
1852                  *
1853                  * For those two physical endpoints, we don't allocate a TRB
1854                  * pool nor do we add them the endpoints list. Due to that, we
1855                  * shouldn't do these two operations otherwise we would end up
1856                  * with all sorts of bugs when removing dwc3.ko.
1857                  */
1858                 if (epnum != 0 && epnum != 1) {
1859                         dwc3_free_trb_pool(dep);
1860                         list_del(&dep->endpoint.ep_list);
1861                 }
1862
1863                 kfree(dep);
1864         }
1865 }
1866
1867 /* -------------------------------------------------------------------------- */
1868
1869 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1870                 struct dwc3_request *req, struct dwc3_trb *trb,
1871                 const struct dwc3_event_depevt *event, int status)
1872 {
1873         unsigned int            count;
1874         unsigned int            s_pkt = 0;
1875         unsigned int            trb_status;
1876
1877         trace_dwc3_complete_trb(dep, trb);
1878
1879         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1880                 /*
1881                  * We continue despite the error. There is not much we
1882                  * can do. If we don't clean it up we loop forever. If
1883                  * we skip the TRB then it gets overwritten after a
1884                  * while since we use them in a ring buffer. A BUG()
1885                  * would help. Lets hope that if this occurs, someone
1886                  * fixes the root cause instead of looking away :)
1887                  */
1888                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1889                                 dep->name, trb);
1890         count = trb->size & DWC3_TRB_SIZE_MASK;
1891
1892         if (dep->direction) {
1893                 if (count) {
1894                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1895                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1896                                 dwc3_trace(trace_dwc3_gadget,
1897                                                 "%s: incomplete IN transfer\n",
1898                                                 dep->name);
1899                                 /*
1900                                  * If missed isoc occurred and there is
1901                                  * no request queued then issue END
1902                                  * TRANSFER, so that core generates
1903                                  * next xfernotready and we will issue
1904                                  * a fresh START TRANSFER.
1905                                  * If there are still queued request
1906                                  * then wait, do not issue either END
1907                                  * or UPDATE TRANSFER, just attach next
1908                                  * request in request_list during
1909                                  * giveback.If any future queued request
1910                                  * is successfully transferred then we
1911                                  * will issue UPDATE TRANSFER for all
1912                                  * request in the request_list.
1913                                  */
1914                                 dep->flags |= DWC3_EP_MISSED_ISOC;
1915                         } else {
1916                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
1917                                                 dep->name);
1918                                 status = -ECONNRESET;
1919                         }
1920                 } else {
1921                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
1922                 }
1923         } else {
1924                 if (count && (event->status & DEPEVT_STATUS_SHORT))
1925                         s_pkt = 1;
1926         }
1927
1928         /*
1929          * We assume here we will always receive the entire data block
1930          * which we should receive. Meaning, if we program RX to
1931          * receive 4K but we receive only 2K, we assume that's all we
1932          * should receive and we simply bounce the request back to the
1933          * gadget driver for further processing.
1934          */
1935         req->request.actual += req->request.length - count;
1936         if (s_pkt)
1937                 return 1;
1938         if ((event->status & DEPEVT_STATUS_LST) &&
1939                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
1940                                 DWC3_TRB_CTRL_HWO)))
1941                 return 1;
1942         if ((event->status & DEPEVT_STATUS_IOC) &&
1943                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
1944                 return 1;
1945         return 0;
1946 }
1947
1948 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
1949                 const struct dwc3_event_depevt *event, int status)
1950 {
1951         struct dwc3_request     *req;
1952         struct dwc3_trb         *trb;
1953         unsigned int            slot;
1954         unsigned int            i;
1955         int                     ret;
1956
1957         do {
1958                 req = next_request(&dep->req_queued);
1959                 if (WARN_ON_ONCE(!req))
1960                         return 1;
1961
1962                 i = 0;
1963                 do {
1964                         slot = req->start_slot + i;
1965                         if ((slot == DWC3_TRB_NUM - 1) &&
1966                                 usb_endpoint_xfer_isoc(dep->endpoint.desc))
1967                                 slot++;
1968                         slot %= DWC3_TRB_NUM;
1969                         trb = &dep->trb_pool[slot];
1970
1971                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
1972                                         event, status);
1973                         if (ret)
1974                                 break;
1975                 } while (++i < req->request.num_mapped_sgs);
1976
1977                 dwc3_gadget_giveback(dep, req, status);
1978
1979                 if (ret)
1980                         break;
1981         } while (1);
1982
1983         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1984                         list_empty(&dep->req_queued)) {
1985                 if (list_empty(&dep->request_list)) {
1986                         /*
1987                          * If there is no entry in request list then do
1988                          * not issue END TRANSFER now. Just set PENDING
1989                          * flag, so that END TRANSFER is issued when an
1990                          * entry is added into request list.
1991                          */
1992                         dep->flags = DWC3_EP_PENDING_REQUEST;
1993                 } else {
1994                         dwc3_stop_active_transfer(dwc, dep->number, true);
1995                         dep->flags = DWC3_EP_ENABLED;
1996                 }
1997                 return 1;
1998         }
1999
2000         return 1;
2001 }
2002
2003 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2004                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2005 {
2006         unsigned                status = 0;
2007         int                     clean_busy;
2008         u32                     is_xfer_complete;
2009
2010         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2011
2012         if (event->status & DEPEVT_STATUS_BUSERR)
2013                 status = -ECONNRESET;
2014
2015         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2016         if (clean_busy && (is_xfer_complete ||
2017                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2018                 dep->flags &= ~DWC3_EP_BUSY;
2019
2020         /*
2021          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2022          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2023          */
2024         if (dwc->revision < DWC3_REVISION_183A) {
2025                 u32             reg;
2026                 int             i;
2027
2028                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2029                         dep = dwc->eps[i];
2030
2031                         if (!(dep->flags & DWC3_EP_ENABLED))
2032                                 continue;
2033
2034                         if (!list_empty(&dep->req_queued))
2035                                 return;
2036                 }
2037
2038                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2039                 reg |= dwc->u1u2;
2040                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2041
2042                 dwc->u1u2 = 0;
2043         }
2044
2045         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2046                 int ret;
2047
2048                 ret = __dwc3_gadget_kick_transfer(dep, 0, is_xfer_complete);
2049                 if (!ret || ret == -EBUSY)
2050                         return;
2051         }
2052 }
2053
2054 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2055                 const struct dwc3_event_depevt *event)
2056 {
2057         struct dwc3_ep          *dep;
2058         u8                      epnum = event->endpoint_number;
2059
2060         dep = dwc->eps[epnum];
2061
2062         if (!(dep->flags & DWC3_EP_ENABLED))
2063                 return;
2064
2065         if (epnum == 0 || epnum == 1) {
2066                 dwc3_ep0_interrupt(dwc, event);
2067                 return;
2068         }
2069
2070         switch (event->endpoint_event) {
2071         case DWC3_DEPEVT_XFERCOMPLETE:
2072                 dep->resource_index = 0;
2073
2074                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2075                         dwc3_trace(trace_dwc3_gadget,
2076                                         "%s is an Isochronous endpoint\n",
2077                                         dep->name);
2078                         return;
2079                 }
2080
2081                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2082                 break;
2083         case DWC3_DEPEVT_XFERINPROGRESS:
2084                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2085                 break;
2086         case DWC3_DEPEVT_XFERNOTREADY:
2087                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2088                         dwc3_gadget_start_isoc(dwc, dep, event);
2089                 } else {
2090                         int active;
2091                         int ret;
2092
2093                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2094
2095                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2096                                         dep->name, active ? "Transfer Active"
2097                                         : "Transfer Not Active");
2098
2099                         ret = __dwc3_gadget_kick_transfer(dep, 0, !active);
2100                         if (!ret || ret == -EBUSY)
2101                                 return;
2102
2103                         dwc3_trace(trace_dwc3_gadget,
2104                                         "%s: failed to kick transfers\n",
2105                                         dep->name);
2106                 }
2107
2108                 break;
2109         case DWC3_DEPEVT_STREAMEVT:
2110                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2111                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2112                                         dep->name);
2113                         return;
2114                 }
2115
2116                 switch (event->status) {
2117                 case DEPEVT_STREAMEVT_FOUND:
2118                         dwc3_trace(trace_dwc3_gadget,
2119                                         "Stream %d found and started",
2120                                         event->parameters);
2121
2122                         break;
2123                 case DEPEVT_STREAMEVT_NOTFOUND:
2124                         /* FALLTHROUGH */
2125                 default:
2126                         dwc3_trace(trace_dwc3_gadget,
2127                                         "unable to find suitable stream\n");
2128                 }
2129                 break;
2130         case DWC3_DEPEVT_RXTXFIFOEVT:
2131                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun\n", dep->name);
2132                 break;
2133         case DWC3_DEPEVT_EPCMDCMPLT:
2134                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2135                 break;
2136         }
2137 }
2138
2139 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2140 {
2141         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2142                 spin_unlock(&dwc->lock);
2143                 dwc->gadget_driver->disconnect(&dwc->gadget);
2144                 spin_lock(&dwc->lock);
2145         }
2146 }
2147
2148 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2149 {
2150         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2151                 spin_unlock(&dwc->lock);
2152                 dwc->gadget_driver->suspend(&dwc->gadget);
2153                 spin_lock(&dwc->lock);
2154         }
2155 }
2156
2157 static void dwc3_resume_gadget(struct dwc3 *dwc)
2158 {
2159         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2160                 spin_unlock(&dwc->lock);
2161                 dwc->gadget_driver->resume(&dwc->gadget);
2162                 spin_lock(&dwc->lock);
2163         }
2164 }
2165
2166 static void dwc3_reset_gadget(struct dwc3 *dwc)
2167 {
2168         if (!dwc->gadget_driver)
2169                 return;
2170
2171         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2172                 spin_unlock(&dwc->lock);
2173                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2174                 spin_lock(&dwc->lock);
2175         }
2176 }
2177
2178 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2179 {
2180         struct dwc3_ep *dep;
2181         struct dwc3_gadget_ep_cmd_params params;
2182         u32 cmd;
2183         int ret;
2184
2185         dep = dwc->eps[epnum];
2186
2187         if (!dep->resource_index)
2188                 return;
2189
2190         /*
2191          * NOTICE: We are violating what the Databook says about the
2192          * EndTransfer command. Ideally we would _always_ wait for the
2193          * EndTransfer Command Completion IRQ, but that's causing too
2194          * much trouble synchronizing between us and gadget driver.
2195          *
2196          * We have discussed this with the IP Provider and it was
2197          * suggested to giveback all requests here, but give HW some
2198          * extra time to synchronize with the interconnect. We're using
2199          * an arbitrary 100us delay for that.
2200          *
2201          * Note also that a similar handling was tested by Synopsys
2202          * (thanks a lot Paul) and nothing bad has come out of it.
2203          * In short, what we're doing is:
2204          *
2205          * - Issue EndTransfer WITH CMDIOC bit set
2206          * - Wait 100us
2207          */
2208
2209         cmd = DWC3_DEPCMD_ENDTRANSFER;
2210         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2211         cmd |= DWC3_DEPCMD_CMDIOC;
2212         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2213         memset(&params, 0, sizeof(params));
2214         ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, &params);
2215         WARN_ON_ONCE(ret);
2216         dep->resource_index = 0;
2217         dep->flags &= ~DWC3_EP_BUSY;
2218         udelay(100);
2219 }
2220
2221 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2222 {
2223         u32 epnum;
2224
2225         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2226                 struct dwc3_ep *dep;
2227
2228                 dep = dwc->eps[epnum];
2229                 if (!dep)
2230                         continue;
2231
2232                 if (!(dep->flags & DWC3_EP_ENABLED))
2233                         continue;
2234
2235                 dwc3_remove_requests(dwc, dep);
2236         }
2237 }
2238
2239 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2240 {
2241         u32 epnum;
2242
2243         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2244                 struct dwc3_ep *dep;
2245                 struct dwc3_gadget_ep_cmd_params params;
2246                 int ret;
2247
2248                 dep = dwc->eps[epnum];
2249                 if (!dep)
2250                         continue;
2251
2252                 if (!(dep->flags & DWC3_EP_STALL))
2253                         continue;
2254
2255                 dep->flags &= ~DWC3_EP_STALL;
2256
2257                 memset(&params, 0, sizeof(params));
2258                 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
2259                                 DWC3_DEPCMD_CLEARSTALL, &params);
2260                 WARN_ON_ONCE(ret);
2261         }
2262 }
2263
2264 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2265 {
2266         int                     reg;
2267
2268         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2269         reg &= ~DWC3_DCTL_INITU1ENA;
2270         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2271
2272         reg &= ~DWC3_DCTL_INITU2ENA;
2273         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2274
2275         dwc3_disconnect_gadget(dwc);
2276
2277         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2278         dwc->setup_packet_pending = false;
2279         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2280 }
2281
2282 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2283 {
2284         u32                     reg;
2285
2286         /*
2287          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2288          * would cause a missing Disconnect Event if there's a
2289          * pending Setup Packet in the FIFO.
2290          *
2291          * There's no suggested workaround on the official Bug
2292          * report, which states that "unless the driver/application
2293          * is doing any special handling of a disconnect event,
2294          * there is no functional issue".
2295          *
2296          * Unfortunately, it turns out that we _do_ some special
2297          * handling of a disconnect event, namely complete all
2298          * pending transfers, notify gadget driver of the
2299          * disconnection, and so on.
2300          *
2301          * Our suggested workaround is to follow the Disconnect
2302          * Event steps here, instead, based on a setup_packet_pending
2303          * flag. Such flag gets set whenever we have a SETUP_PENDING
2304          * status for EP0 TRBs and gets cleared on XferComplete for the
2305          * same endpoint.
2306          *
2307          * Refers to:
2308          *
2309          * STAR#9000466709: RTL: Device : Disconnect event not
2310          * generated if setup packet pending in FIFO
2311          */
2312         if (dwc->revision < DWC3_REVISION_188A) {
2313                 if (dwc->setup_packet_pending)
2314                         dwc3_gadget_disconnect_interrupt(dwc);
2315         }
2316
2317         dwc3_reset_gadget(dwc);
2318
2319         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2320         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2321         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2322         dwc->test_mode = false;
2323
2324         dwc3_stop_active_transfers(dwc);
2325         dwc3_clear_stall_all_ep(dwc);
2326
2327         /* Reset device address to zero */
2328         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2329         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2330         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2331 }
2332
2333 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2334 {
2335         u32 reg;
2336         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2337
2338         /*
2339          * We change the clock only at SS but I dunno why I would want to do
2340          * this. Maybe it becomes part of the power saving plan.
2341          */
2342
2343         if (speed != DWC3_DSTS_SUPERSPEED)
2344                 return;
2345
2346         /*
2347          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2348          * each time on Connect Done.
2349          */
2350         if (!usb30_clock)
2351                 return;
2352
2353         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2354         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2355         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2356 }
2357
2358 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2359 {
2360         struct dwc3_ep          *dep;
2361         int                     ret;
2362         u32                     reg;
2363         u8                      speed;
2364
2365         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2366         speed = reg & DWC3_DSTS_CONNECTSPD;
2367         dwc->speed = speed;
2368
2369         dwc3_update_ram_clk_sel(dwc, speed);
2370
2371         switch (speed) {
2372         case DWC3_DCFG_SUPERSPEED:
2373                 /*
2374                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2375                  * would cause a missing USB3 Reset event.
2376                  *
2377                  * In such situations, we should force a USB3 Reset
2378                  * event by calling our dwc3_gadget_reset_interrupt()
2379                  * routine.
2380                  *
2381                  * Refers to:
2382                  *
2383                  * STAR#9000483510: RTL: SS : USB3 reset event may
2384                  * not be generated always when the link enters poll
2385                  */
2386                 if (dwc->revision < DWC3_REVISION_190A)
2387                         dwc3_gadget_reset_interrupt(dwc);
2388
2389                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2390                 dwc->gadget.ep0->maxpacket = 512;
2391                 dwc->gadget.speed = USB_SPEED_SUPER;
2392                 break;
2393         case DWC3_DCFG_HIGHSPEED:
2394                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2395                 dwc->gadget.ep0->maxpacket = 64;
2396                 dwc->gadget.speed = USB_SPEED_HIGH;
2397                 break;
2398         case DWC3_DCFG_FULLSPEED2:
2399         case DWC3_DCFG_FULLSPEED1:
2400                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2401                 dwc->gadget.ep0->maxpacket = 64;
2402                 dwc->gadget.speed = USB_SPEED_FULL;
2403                 break;
2404         case DWC3_DCFG_LOWSPEED:
2405                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2406                 dwc->gadget.ep0->maxpacket = 8;
2407                 dwc->gadget.speed = USB_SPEED_LOW;
2408                 break;
2409         }
2410
2411         /* Enable USB2 LPM Capability */
2412
2413         if ((dwc->revision > DWC3_REVISION_194A)
2414                         && (speed != DWC3_DCFG_SUPERSPEED)) {
2415                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2416                 reg |= DWC3_DCFG_LPM_CAP;
2417                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2418
2419                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2420                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2421
2422                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2423
2424                 /*
2425                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2426                  * DCFG.LPMCap is set, core responses with an ACK and the
2427                  * BESL value in the LPM token is less than or equal to LPM
2428                  * NYET threshold.
2429                  */
2430                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2431                                 && dwc->has_lpm_erratum,
2432                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2433
2434                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2435                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2436
2437                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2438         } else {
2439                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2440                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2441                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2442         }
2443
2444         dep = dwc->eps[0];
2445         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2446                         false);
2447         if (ret) {
2448                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2449                 return;
2450         }
2451
2452         dep = dwc->eps[1];
2453         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2454                         false);
2455         if (ret) {
2456                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2457                 return;
2458         }
2459
2460         /*
2461          * Configure PHY via GUSB3PIPECTLn if required.
2462          *
2463          * Update GTXFIFOSIZn
2464          *
2465          * In both cases reset values should be sufficient.
2466          */
2467 }
2468
2469 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2470 {
2471         /*
2472          * TODO take core out of low power mode when that's
2473          * implemented.
2474          */
2475
2476         dwc->gadget_driver->resume(&dwc->gadget);
2477 }
2478
2479 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2480                 unsigned int evtinfo)
2481 {
2482         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2483         unsigned int            pwropt;
2484
2485         /*
2486          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2487          * Hibernation mode enabled which would show up when device detects
2488          * host-initiated U3 exit.
2489          *
2490          * In that case, device will generate a Link State Change Interrupt
2491          * from U3 to RESUME which is only necessary if Hibernation is
2492          * configured in.
2493          *
2494          * There are no functional changes due to such spurious event and we
2495          * just need to ignore it.
2496          *
2497          * Refers to:
2498          *
2499          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2500          * operational mode
2501          */
2502         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2503         if ((dwc->revision < DWC3_REVISION_250A) &&
2504                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2505                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2506                                 (next == DWC3_LINK_STATE_RESUME)) {
2507                         dwc3_trace(trace_dwc3_gadget,
2508                                         "ignoring transition U3 -> Resume");
2509                         return;
2510                 }
2511         }
2512
2513         /*
2514          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2515          * on the link partner, the USB session might do multiple entry/exit
2516          * of low power states before a transfer takes place.
2517          *
2518          * Due to this problem, we might experience lower throughput. The
2519          * suggested workaround is to disable DCTL[12:9] bits if we're
2520          * transitioning from U1/U2 to U0 and enable those bits again
2521          * after a transfer completes and there are no pending transfers
2522          * on any of the enabled endpoints.
2523          *
2524          * This is the first half of that workaround.
2525          *
2526          * Refers to:
2527          *
2528          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2529          * core send LGO_Ux entering U0
2530          */
2531         if (dwc->revision < DWC3_REVISION_183A) {
2532                 if (next == DWC3_LINK_STATE_U0) {
2533                         u32     u1u2;
2534                         u32     reg;
2535
2536                         switch (dwc->link_state) {
2537                         case DWC3_LINK_STATE_U1:
2538                         case DWC3_LINK_STATE_U2:
2539                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2540                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2541                                                 | DWC3_DCTL_ACCEPTU2ENA
2542                                                 | DWC3_DCTL_INITU1ENA
2543                                                 | DWC3_DCTL_ACCEPTU1ENA);
2544
2545                                 if (!dwc->u1u2)
2546                                         dwc->u1u2 = reg & u1u2;
2547
2548                                 reg &= ~u1u2;
2549
2550                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2551                                 break;
2552                         default:
2553                                 /* do nothing */
2554                                 break;
2555                         }
2556                 }
2557         }
2558
2559         switch (next) {
2560         case DWC3_LINK_STATE_U1:
2561                 if (dwc->speed == USB_SPEED_SUPER)
2562                         dwc3_suspend_gadget(dwc);
2563                 break;
2564         case DWC3_LINK_STATE_U2:
2565         case DWC3_LINK_STATE_U3:
2566                 dwc3_suspend_gadget(dwc);
2567                 break;
2568         case DWC3_LINK_STATE_RESUME:
2569                 dwc3_resume_gadget(dwc);
2570                 break;
2571         default:
2572                 /* do nothing */
2573                 break;
2574         }
2575
2576         dwc->link_state = next;
2577 }
2578
2579 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2580                 unsigned int evtinfo)
2581 {
2582         unsigned int is_ss = evtinfo & BIT(4);
2583
2584         /**
2585          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2586          * have a known issue which can cause USB CV TD.9.23 to fail
2587          * randomly.
2588          *
2589          * Because of this issue, core could generate bogus hibernation
2590          * events which SW needs to ignore.
2591          *
2592          * Refers to:
2593          *
2594          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2595          * Device Fallback from SuperSpeed
2596          */
2597         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2598                 return;
2599
2600         /* enter hibernation here */
2601 }
2602
2603 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2604                 const struct dwc3_event_devt *event)
2605 {
2606         switch (event->type) {
2607         case DWC3_DEVICE_EVENT_DISCONNECT:
2608                 dwc3_gadget_disconnect_interrupt(dwc);
2609                 break;
2610         case DWC3_DEVICE_EVENT_RESET:
2611                 dwc3_gadget_reset_interrupt(dwc);
2612                 break;
2613         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2614                 dwc3_gadget_conndone_interrupt(dwc);
2615                 break;
2616         case DWC3_DEVICE_EVENT_WAKEUP:
2617                 dwc3_gadget_wakeup_interrupt(dwc);
2618                 break;
2619         case DWC3_DEVICE_EVENT_HIBER_REQ:
2620                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2621                                         "unexpected hibernation event\n"))
2622                         break;
2623
2624                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2625                 break;
2626         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2627                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2628                 break;
2629         case DWC3_DEVICE_EVENT_EOPF:
2630                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2631                 break;
2632         case DWC3_DEVICE_EVENT_SOF:
2633                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2634                 break;
2635         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2636                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2637                 break;
2638         case DWC3_DEVICE_EVENT_CMD_CMPL:
2639                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2640                 break;
2641         case DWC3_DEVICE_EVENT_OVERFLOW:
2642                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2643                 break;
2644         default:
2645                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2646         }
2647 }
2648
2649 static void dwc3_process_event_entry(struct dwc3 *dwc,
2650                 const union dwc3_event *event)
2651 {
2652         trace_dwc3_event(event->raw);
2653
2654         /* Endpoint IRQ, handle it and return early */
2655         if (event->type.is_devspec == 0) {
2656                 /* depevt */
2657                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2658         }
2659
2660         switch (event->type.type) {
2661         case DWC3_EVENT_TYPE_DEV:
2662                 dwc3_gadget_interrupt(dwc, &event->devt);
2663                 break;
2664         /* REVISIT what to do with Carkit and I2C events ? */
2665         default:
2666                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2667         }
2668 }
2669
2670 static irqreturn_t dwc3_process_event_buf(struct dwc3 *dwc, u32 buf)
2671 {
2672         struct dwc3_event_buffer *evt;
2673         irqreturn_t ret = IRQ_NONE;
2674         int left;
2675         u32 reg;
2676
2677         evt = dwc->ev_buffs[buf];
2678         left = evt->count;
2679
2680         if (!(evt->flags & DWC3_EVENT_PENDING))
2681                 return IRQ_NONE;
2682
2683         while (left > 0) {
2684                 union dwc3_event event;
2685
2686                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2687
2688                 dwc3_process_event_entry(dwc, &event);
2689
2690                 /*
2691                  * FIXME we wrap around correctly to the next entry as
2692                  * almost all entries are 4 bytes in size. There is one
2693                  * entry which has 12 bytes which is a regular entry
2694                  * followed by 8 bytes data. ATM I don't know how
2695                  * things are organized if we get next to the a
2696                  * boundary so I worry about that once we try to handle
2697                  * that.
2698                  */
2699                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2700                 left -= 4;
2701
2702                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(buf), 4);
2703         }
2704
2705         evt->count = 0;
2706         evt->flags &= ~DWC3_EVENT_PENDING;
2707         ret = IRQ_HANDLED;
2708
2709         /* Unmask interrupt */
2710         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2711         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2712         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2713
2714         return ret;
2715 }
2716
2717 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc)
2718 {
2719         struct dwc3 *dwc = _dwc;
2720         unsigned long flags;
2721         irqreturn_t ret = IRQ_NONE;
2722         int i;
2723
2724         spin_lock_irqsave(&dwc->lock, flags);
2725
2726         for (i = 0; i < dwc->num_event_buffers; i++)
2727                 ret |= dwc3_process_event_buf(dwc, i);
2728
2729         spin_unlock_irqrestore(&dwc->lock, flags);
2730
2731         return ret;
2732 }
2733
2734 static irqreturn_t dwc3_check_event_buf(struct dwc3 *dwc, u32 buf)
2735 {
2736         struct dwc3_event_buffer *evt;
2737         u32 count;
2738         u32 reg;
2739
2740         evt = dwc->ev_buffs[buf];
2741
2742         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(buf));
2743         count &= DWC3_GEVNTCOUNT_MASK;
2744         if (!count)
2745                 return IRQ_NONE;
2746
2747         evt->count = count;
2748         evt->flags |= DWC3_EVENT_PENDING;
2749
2750         /* Mask interrupt */
2751         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(buf));
2752         reg |= DWC3_GEVNTSIZ_INTMASK;
2753         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(buf), reg);
2754
2755         return IRQ_WAKE_THREAD;
2756 }
2757
2758 static irqreturn_t dwc3_interrupt(int irq, void *_dwc)
2759 {
2760         struct dwc3                     *dwc = _dwc;
2761         int                             i;
2762         irqreturn_t                     ret = IRQ_NONE;
2763
2764         for (i = 0; i < dwc->num_event_buffers; i++) {
2765                 irqreturn_t status;
2766
2767                 status = dwc3_check_event_buf(dwc, i);
2768                 if (status == IRQ_WAKE_THREAD)
2769                         ret = status;
2770         }
2771
2772         return ret;
2773 }
2774
2775 /**
2776  * dwc3_gadget_init - Initializes gadget related registers
2777  * @dwc: pointer to our controller context structure
2778  *
2779  * Returns 0 on success otherwise negative errno.
2780  */
2781 int dwc3_gadget_init(struct dwc3 *dwc)
2782 {
2783         int                                     ret;
2784
2785         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2786                         &dwc->ctrl_req_addr, GFP_KERNEL);
2787         if (!dwc->ctrl_req) {
2788                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2789                 ret = -ENOMEM;
2790                 goto err0;
2791         }
2792
2793         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2794                         &dwc->ep0_trb_addr, GFP_KERNEL);
2795         if (!dwc->ep0_trb) {
2796                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2797                 ret = -ENOMEM;
2798                 goto err1;
2799         }
2800
2801         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2802         if (!dwc->setup_buf) {
2803                 ret = -ENOMEM;
2804                 goto err2;
2805         }
2806
2807         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2808                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2809                         GFP_KERNEL);
2810         if (!dwc->ep0_bounce) {
2811                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2812                 ret = -ENOMEM;
2813                 goto err3;
2814         }
2815
2816         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2817         if (!dwc->zlp_buf) {
2818                 ret = -ENOMEM;
2819                 goto err4;
2820         }
2821
2822         dwc->gadget.ops                 = &dwc3_gadget_ops;
2823         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2824         dwc->gadget.sg_supported        = true;
2825         dwc->gadget.name                = "dwc3-gadget";
2826         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2827
2828         /*
2829          * FIXME We might be setting max_speed to <SUPER, however versions
2830          * <2.20a of dwc3 have an issue with metastability (documented
2831          * elsewhere in this driver) which tells us we can't set max speed to
2832          * anything lower than SUPER.
2833          *
2834          * Because gadget.max_speed is only used by composite.c and function
2835          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2836          * to happen so we avoid sending SuperSpeed Capability descriptor
2837          * together with our BOS descriptor as that could confuse host into
2838          * thinking we can handle super speed.
2839          *
2840          * Note that, in fact, we won't even support GetBOS requests when speed
2841          * is less than super speed because we don't have means, yet, to tell
2842          * composite.c that we are USB 2.0 + LPM ECN.
2843          */
2844         if (dwc->revision < DWC3_REVISION_220A)
2845                 dwc3_trace(trace_dwc3_gadget,
2846                                 "Changing max_speed on rev %08x\n",
2847                                 dwc->revision);
2848
2849         dwc->gadget.max_speed           = dwc->maximum_speed;
2850
2851         /*
2852          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2853          * on ep out.
2854          */
2855         dwc->gadget.quirk_ep_out_aligned_size = true;
2856
2857         /*
2858          * REVISIT: Here we should clear all pending IRQs to be
2859          * sure we're starting from a well known location.
2860          */
2861
2862         ret = dwc3_gadget_init_endpoints(dwc);
2863         if (ret)
2864                 goto err5;
2865
2866         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2867         if (ret) {
2868                 dev_err(dwc->dev, "failed to register udc\n");
2869                 goto err5;
2870         }
2871
2872         return 0;
2873
2874 err5:
2875         kfree(dwc->zlp_buf);
2876
2877 err4:
2878         dwc3_gadget_free_endpoints(dwc);
2879         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2880                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2881
2882 err3:
2883         kfree(dwc->setup_buf);
2884
2885 err2:
2886         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2887                         dwc->ep0_trb, dwc->ep0_trb_addr);
2888
2889 err1:
2890         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2891                         dwc->ctrl_req, dwc->ctrl_req_addr);
2892
2893 err0:
2894         return ret;
2895 }
2896
2897 /* -------------------------------------------------------------------------- */
2898
2899 void dwc3_gadget_exit(struct dwc3 *dwc)
2900 {
2901         usb_del_gadget_udc(&dwc->gadget);
2902
2903         dwc3_gadget_free_endpoints(dwc);
2904
2905         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2906                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2907
2908         kfree(dwc->setup_buf);
2909         kfree(dwc->zlp_buf);
2910
2911         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
2912                         dwc->ep0_trb, dwc->ep0_trb_addr);
2913
2914         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2915                         dwc->ctrl_req, dwc->ctrl_req_addr);
2916 }
2917
2918 int dwc3_gadget_suspend(struct dwc3 *dwc)
2919 {
2920         if (dwc->pullups_connected) {
2921                 dwc3_gadget_disable_irq(dwc);
2922                 dwc3_gadget_run_stop(dwc, true, true);
2923         }
2924
2925         __dwc3_gadget_ep_disable(dwc->eps[0]);
2926         __dwc3_gadget_ep_disable(dwc->eps[1]);
2927
2928         dwc->dcfg = dwc3_readl(dwc->regs, DWC3_DCFG);
2929
2930         return 0;
2931 }
2932
2933 int dwc3_gadget_resume(struct dwc3 *dwc)
2934 {
2935         struct dwc3_ep          *dep;
2936         int                     ret;
2937
2938         /* Start with SuperSpeed Default */
2939         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2940
2941         dep = dwc->eps[0];
2942         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2943                         false);
2944         if (ret)
2945                 goto err0;
2946
2947         dep = dwc->eps[1];
2948         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
2949                         false);
2950         if (ret)
2951                 goto err1;
2952
2953         /* begin to receive SETUP packets */
2954         dwc->ep0state = EP0_SETUP_PHASE;
2955         dwc3_ep0_out_start(dwc);
2956
2957         dwc3_writel(dwc->regs, DWC3_DCFG, dwc->dcfg);
2958
2959         if (dwc->pullups_connected) {
2960                 dwc3_gadget_enable_irq(dwc);
2961                 dwc3_gadget_run_stop(dwc, true, false);
2962         }
2963
2964         return 0;
2965
2966 err1:
2967         __dwc3_gadget_ep_disable(dwc->eps[0]);
2968
2969 err0:
2970         return ret;
2971 }