drivers/usb/dwc3/gadget.c

   1 /**
   2  * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/pm_runtime.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/io.h>
  27 #include <linux/list.h>
  28 #include <linux/dma-mapping.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32
  33 #include "debug.h"
  34 #include "core.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 /**
  39  * dwc3_gadget_set_test_mode - Enables USB2 Test Modes
  40  * @dwc: pointer to our context structure
  41  * @mode: the mode to set (J, K SE0 NAK, Force Enable)
  42  *
  43  * Caller should take care of locking. This function will
  44  * return 0 on success or -EINVAL if wrong Test Selector
  45  * is passed
  46  */
  47 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
  48 {
  49         u32             reg;
  50
  51         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  52         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
  53
  54         switch (mode) {
  55         case TEST_J:
  56         case TEST_K:
  57         case TEST_SE0_NAK:
  58         case TEST_PACKET:
  59         case TEST_FORCE_EN:
  60                 reg |= mode << 1;
  61                 break;
  62         default:
  63                 return -EINVAL;
  64         }
  65
  66         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  67
  68         return 0;
  69 }
  70
  71 /**
  72  * dwc3_gadget_get_link_state - Gets current state of USB Link
  73  * @dwc: pointer to our context structure
  74  *
  75  * Caller should take care of locking. This function will
  76  * return the link state on success (>= 0) or -ETIMEDOUT.
  77  */
  78 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
  79 {
  80         u32             reg;
  81
  82         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
  83
  84         return DWC3_DSTS_USBLNKST(reg);
  85 }
  86
  87 /**
  88  * dwc3_gadget_set_link_state - Sets USB Link to a particular State
  89  * @dwc: pointer to our context structure
  90  * @state: the state to put link into
  91  *
  92  * Caller should take care of locking. This function will
  93  * return 0 on success or -ETIMEDOUT.
  94  */
  95 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
  96 {
  97         int             retries = 10000;
  98         u32             reg;
  99
 100         /*
 101          * Wait until device controller is ready. Only applies to 1.94a and
 102          * later RTL.
 103          */
 104         if (dwc->revision >= DWC3_REVISION_194A) {
 105                 while (--retries) {
 106                         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 107                         if (reg & DWC3_DSTS_DCNRD)
 108                                 udelay(5);
 109                         else
 110                                 break;
 111                 }
 112
 113                 if (retries <= 0)
 114                         return -ETIMEDOUT;
 115         }
 116
 117         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 118         reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
 119
 120         /* set requested state */
 121         reg |= DWC3_DCTL_ULSTCHNGREQ(state);
 122         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 123
 124         /*
 125          * The following code is racy when called from dwc3_gadget_wakeup,
 126          * and is not needed, at least on newer versions
 127          */
 128         if (dwc->revision >= DWC3_REVISION_194A)
 129                 return 0;
 130
 131         /* wait for a change in DSTS */
 132         retries = 10000;
 133         while (--retries) {
 134                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
 135
 136                 if (DWC3_DSTS_USBLNKST(reg) == state)
 137                         return 0;
 138
 139                 udelay(5);
 140         }
 141
 142         dwc3_trace(trace_dwc3_gadget,
 143                         "link state change request timed out");
 144
 145         return -ETIMEDOUT;
 146 }
 147
 148 /**
 149  * dwc3_ep_inc_trb() - Increment a TRB index.
 150  * @index - Pointer to the TRB index to increment.
 151  *
 152  * The index should never point to the link TRB. After incrementing,
 153  * if it is point to the link TRB, wrap around to the beginning. The
 154  * link TRB is always at the last TRB entry.
 155  */
 156 static void dwc3_ep_inc_trb(u8 *index)
 157 {
 158         (*index)++;
 159         if (*index == (DWC3_TRB_NUM - 1))
 160                 *index = 0;
 161 }
 162
 163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
 164 {
 165         dwc3_ep_inc_trb(&dep->trb_enqueue);
 166 }
 167
 168 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
 169 {
 170         dwc3_ep_inc_trb(&dep->trb_dequeue);
 171 }
 172
 173 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
 174                 int status)
 175 {
 176         struct dwc3                     *dwc = dep->dwc;
 177         int                             i;
 178
 179         if (req->started) {
 180                 i = 0;
 181                 do {
 182                         dwc3_ep_inc_deq(dep);
 183                 } while(++i < req->request.num_mapped_sgs);
 184                 req->started = false;
 185         }
 186         list_del(&req->list);
 187         req->trb = NULL;
 188
 189         if (req->request.status == -EINPROGRESS)
 190                 req->request.status = status;
 191
 192         if (dwc->ep0_bounced && dep->number == 0)
 193                 dwc->ep0_bounced = false;
 194         else
 195                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
 196                                 req->direction);
 197
 198         trace_dwc3_gadget_giveback(req);
 199
 200         spin_unlock(&dwc->lock);
 201         usb_gadget_giveback_request(&dep->endpoint, &req->request);
 202         spin_lock(&dwc->lock);
 203
 204         if (dep->number > 1)
 205                 pm_runtime_put(dwc->dev);
 206 }
 207
 208 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
 209 {
 210         u32             timeout = 500;
 211         int             status = 0;
 212         int             ret = 0;
 213         u32             reg;
 214
 215         dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
 216         dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
 217
 218         do {
 219                 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
 220                 if (!(reg & DWC3_DGCMD_CMDACT)) {
 221                         status = DWC3_DGCMD_STATUS(reg);
 222                         if (status)
 223                                 ret = -EINVAL;
 224                         break;
 225                 }
 226         } while (timeout--);
 227
 228         if (!timeout) {
 229                 ret = -ETIMEDOUT;
 230                 status = -ETIMEDOUT;
 231         }
 232
 233         trace_dwc3_gadget_generic_cmd(cmd, param, status);
 234
 235         return ret;
 236 }
 237
 238 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
 239
 240 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
 241                 struct dwc3_gadget_ep_cmd_params *params)
 242 {
 243         struct dwc3             *dwc = dep->dwc;
 244         u32                     timeout = 500;
 245         u32                     reg;
 246
 247         int                     cmd_status = 0;
 248         int                     susphy = false;
 249         int                     ret = -EINVAL;
 250
 251         /*
 252          * Synopsys Databook 2.60a states, on section 6.3.2.5.[1-8], that if
 253          * we're issuing an endpoint command, we must check if
 254          * GUSB2PHYCFG.SUSPHY bit is set. If it is, then we need to clear it.
 255          *
 256          * We will also set SUSPHY bit to what it was before returning as stated
 257          * by the same section on Synopsys databook.
 258          */
 259         if (dwc->gadget.speed <= USB_SPEED_HIGH) {
 260                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 261                 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
 262                         susphy = true;
 263                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 264                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 265                 }
 266         }
 267
 268         if (cmd == DWC3_DEPCMD_STARTTRANSFER) {
 269                 int             needs_wakeup;
 270
 271                 needs_wakeup = (dwc->link_state == DWC3_LINK_STATE_U1 ||
 272                                 dwc->link_state == DWC3_LINK_STATE_U2 ||
 273                                 dwc->link_state == DWC3_LINK_STATE_U3);
 274
 275                 if (unlikely(needs_wakeup)) {
 276                         ret = __dwc3_gadget_wakeup(dwc);
 277                         dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
 278                                         ret);
 279                 }
 280         }
 281
 282         dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
 283         dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
 284         dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
 285
 286         dwc3_writel(dep->regs, DWC3_DEPCMD, cmd | DWC3_DEPCMD_CMDACT);
 287         do {
 288                 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
 289                 if (!(reg & DWC3_DEPCMD_CMDACT)) {
 290                         cmd_status = DWC3_DEPCMD_STATUS(reg);
 291
 292                         switch (cmd_status) {
 293                         case 0:
 294                                 ret = 0;
 295                                 break;
 296                         case DEPEVT_TRANSFER_NO_RESOURCE:
 297                                 ret = -EINVAL;
 298                                 break;
 299                         case DEPEVT_TRANSFER_BUS_EXPIRY:
 300                                 /*
 301                                  * SW issues START TRANSFER command to
 302                                  * isochronous ep with future frame interval. If
 303                                  * future interval time has already passed when
 304                                  * core receives the command, it will respond
 305                                  * with an error status of 'Bus Expiry'.
 306                                  *
 307                                  * Instead of always returning -EINVAL, let's
 308                                  * give a hint to the gadget driver that this is
 309                                  * the case by returning -EAGAIN.
 310                                  */
 311                                 ret = -EAGAIN;
 312                                 break;
 313                         default:
 314                                 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
 315                         }
 316
 317                         break;
 318                 }
 319         } while (--timeout);
 320
 321         if (timeout == 0) {
 322                 ret = -ETIMEDOUT;
 323                 cmd_status = -ETIMEDOUT;
 324         }
 325
 326         trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
 327
 328         if (unlikely(susphy)) {
 329                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 330                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 331                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 332         }
 333
 334         return ret;
 335 }
 336
 337 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
 338 {
 339         struct dwc3 *dwc = dep->dwc;
 340         struct dwc3_gadget_ep_cmd_params params;
 341         u32 cmd = DWC3_DEPCMD_CLEARSTALL;
 342
 343         /*
 344          * As of core revision 2.60a the recommended programming model
 345          * is to set the ClearPendIN bit when issuing a Clear Stall EP
 346          * command for IN endpoints. This is to prevent an issue where
 347          * some (non-compliant) hosts may not send ACK TPs for pending
 348          * IN transfers due to a mishandled error condition. Synopsys
 349          * STAR 9000614252.
 350          */
 351         if (dep->direction && (dwc->revision >= DWC3_REVISION_260A))
 352                 cmd |= DWC3_DEPCMD_CLEARPENDIN;
 353
 354         memset(&params, 0, sizeof(params));
 355
 356         return dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 357 }
 358
 359 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
 360                 struct dwc3_trb *trb)
 361 {
 362         u32             offset = (char *) trb - (char *) dep->trb_pool;
 363
 364         return dep->trb_pool_dma + offset;
 365 }
 366
 367 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
 368 {
 369         struct dwc3             *dwc = dep->dwc;
 370
 371         if (dep->trb_pool)
 372                 return 0;
 373
 374         dep->trb_pool = dma_alloc_coherent(dwc->dev,
 375                         sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 376                         &dep->trb_pool_dma, GFP_KERNEL);
 377         if (!dep->trb_pool) {
 378                 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
 379                                 dep->name);
 380                 return -ENOMEM;
 381         }
 382
 383         return 0;
 384 }
 385
 386 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
 387 {
 388         struct dwc3             *dwc = dep->dwc;
 389
 390         dma_free_coherent(dwc->dev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
 391                         dep->trb_pool, dep->trb_pool_dma);
 392
 393         dep->trb_pool = NULL;
 394         dep->trb_pool_dma = 0;
 395 }
 396
 397 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
 398
 399 /**
 400  * dwc3_gadget_start_config - Configure EP resources
 401  * @dwc: pointer to our controller context structure
 402  * @dep: endpoint that is being enabled
 403  *
 404  * The assignment of transfer resources cannot perfectly follow the
 405  * data book due to the fact that the controller driver does not have
 406  * all knowledge of the configuration in advance. It is given this
 407  * information piecemeal by the composite gadget framework after every
 408  * SET_CONFIGURATION and SET_INTERFACE. Trying to follow the databook
 409  * programming model in this scenario can cause errors. For two
 410  * reasons:
 411  *
 412  * 1) The databook says to do DEPSTARTCFG for every SET_CONFIGURATION
 413  * and SET_INTERFACE (8.1.5). This is incorrect in the scenario of
 414  * multiple interfaces.
 415  *
 416  * 2) The databook does not mention doing more DEPXFERCFG for new
 417  * endpoint on alt setting (8.1.6).
 418  *
 419  * The following simplified method is used instead:
 420  *
 421  * All hardware endpoints can be assigned a transfer resource and this
 422  * setting will stay persistent until either a core reset or
 423  * hibernation. So whenever we do a DEPSTARTCFG(0) we can go ahead and
 424  * do DEPXFERCFG for every hardware endpoint as well. We are
 425  * guaranteed that there are as many transfer resources as endpoints.
 426  *
 427  * This function is called for each endpoint when it is being enabled
 428  * but is triggered only when called for EP0-out, which always happens
 429  * first, and which should only happen in one of the above conditions.
 430  */
 431 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
 432 {
 433         struct dwc3_gadget_ep_cmd_params params;
 434         u32                     cmd;
 435         int                     i;
 436         int                     ret;
 437
 438         if (dep->number)
 439                 return 0;
 440
 441         memset(&params, 0x00, sizeof(params));
 442         cmd = DWC3_DEPCMD_DEPSTARTCFG;
 443
 444         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
 445         if (ret)
 446                 return ret;
 447
 448         for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
 449                 struct dwc3_ep *dep = dwc->eps[i];
 450
 451                 if (!dep)
 452                         continue;
 453
 454                 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
 455                 if (ret)
 456                         return ret;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
 463                 const struct usb_endpoint_descriptor *desc,
 464                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 465                 bool ignore, bool restore)
 466 {
 467         struct dwc3_gadget_ep_cmd_params params;
 468
 469         memset(&params, 0x00, sizeof(params));
 470
 471         params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
 472                 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
 473
 474         /* Burst size is only needed in SuperSpeed mode */
 475         if (dwc->gadget.speed >= USB_SPEED_SUPER) {
 476                 u32 burst = dep->endpoint.maxburst;
 477                 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
 478         }
 479
 480         if (ignore)
 481                 params.param0 |= DWC3_DEPCFG_IGN_SEQ_NUM;
 482
 483         if (restore) {
 484                 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
 485                 params.param2 |= dep->saved_state;
 486         }
 487
 488         params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
 489
 490         if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
 491                 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
 492
 493         if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
 494                 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
 495                         | DWC3_DEPCFG_STREAM_EVENT_EN;
 496                 dep->stream_capable = true;
 497         }
 498
 499         if (!usb_endpoint_xfer_control(desc))
 500                 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
 501
 502         /*
 503          * We are doing 1:1 mapping for endpoints, meaning
 504          * Physical Endpoints 2 maps to Logical Endpoint 2 and
 505          * so on. We consider the direction bit as part of the physical
 506          * endpoint number. So USB endpoint 0x81 is 0x03.
 507          */
 508         params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
 509
 510         /*
 511          * We must use the lower 16 TX FIFOs even though
 512          * HW might have more
 513          */
 514         if (dep->direction)
 515                 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
 516
 517         if (desc->bInterval) {
 518                 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(desc->bInterval - 1);
 519                 dep->interval = 1 << (desc->bInterval - 1);
 520         }
 521
 522         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, &params);
 523 }
 524
 525 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
 526 {
 527         struct dwc3_gadget_ep_cmd_params params;
 528
 529         memset(&params, 0x00, sizeof(params));
 530
 531         params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
 532
 533         return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
 534                         &params);
 535 }
 536
 537 /**
 538  * __dwc3_gadget_ep_enable - Initializes a HW endpoint
 539  * @dep: endpoint to be initialized
 540  * @desc: USB Endpoint Descriptor
 541  *
 542  * Caller should take care of locking
 543  */
 544 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
 545                 const struct usb_endpoint_descriptor *desc,
 546                 const struct usb_ss_ep_comp_descriptor *comp_desc,
 547                 bool ignore, bool restore)
 548 {
 549         struct dwc3             *dwc = dep->dwc;
 550         u32                     reg;
 551         int                     ret;
 552
 553         dwc3_trace(trace_dwc3_gadget, "Enabling %s", dep->name);
 554
 555         if (!(dep->flags & DWC3_EP_ENABLED)) {
 556                 ret = dwc3_gadget_start_config(dwc, dep);
 557                 if (ret)
 558                         return ret;
 559         }
 560
 561         ret = dwc3_gadget_set_ep_config(dwc, dep, desc, comp_desc, ignore,
 562                         restore);
 563         if (ret)
 564                 return ret;
 565
 566         if (!(dep->flags & DWC3_EP_ENABLED)) {
 567                 struct dwc3_trb *trb_st_hw;
 568                 struct dwc3_trb *trb_link;
 569
 570                 dep->endpoint.desc = desc;
 571                 dep->comp_desc = comp_desc;
 572                 dep->type = usb_endpoint_type(desc);
 573                 dep->flags |= DWC3_EP_ENABLED;
 574
 575                 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 576                 reg |= DWC3_DALEPENA_EP(dep->number);
 577                 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 578
 579                 if (usb_endpoint_xfer_control(desc))
 580                         return 0;
 581
 582                 /* Initialize the TRB ring */
 583                 dep->trb_dequeue = 0;
 584                 dep->trb_enqueue = 0;
 585                 memset(dep->trb_pool, 0,
 586                        sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
 587
 588                 /* Link TRB. The HWO bit is never reset */
 589                 trb_st_hw = &dep->trb_pool[0];
 590
 591                 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
 592                 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 593                 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
 594                 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
 595                 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
 602 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
 603 {
 604         struct dwc3_request             *req;
 605         struct dwc3_trb                 *current_trb;
 606         unsigned                        transfer_in_flight;
 607
 608         if (dep->number > 1)
 609                 current_trb = &dep->trb_pool[dep->trb_enqueue];
 610         else
 611                 current_trb = &dwc->ep0_trb[dep->trb_enqueue];
 612         transfer_in_flight = current_trb->ctrl & DWC3_TRB_CTRL_HWO;
 613
 614         if (transfer_in_flight && !list_empty(&dep->started_list)) {
 615                 dwc3_stop_active_transfer(dwc, dep->number, true);
 616
 617                 /* - giveback all requests to gadget driver */
 618                 while (!list_empty(&dep->started_list)) {
 619                         req = next_request(&dep->started_list);
 620
 621                         dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 622                 }
 623         }
 624
 625         while (!list_empty(&dep->pending_list)) {
 626                 req = next_request(&dep->pending_list);
 627
 628                 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
 629         }
 630 }
 631
 632 /**
 633  * __dwc3_gadget_ep_disable - Disables a HW endpoint
 634  * @dep: the endpoint to disable
 635  *
 636  * This function also removes requests which are currently processed ny the
 637  * hardware and those which are not yet scheduled.
 638  * Caller should take care of locking.
 639  */
 640 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
 641 {
 642         struct dwc3             *dwc = dep->dwc;
 643         u32                     reg;
 644
 645         dwc3_trace(trace_dwc3_gadget, "Disabling %s", dep->name);
 646
 647         dwc3_remove_requests(dwc, dep);
 648
 649         /* make sure HW endpoint isn't stalled */
 650         if (dep->flags & DWC3_EP_STALL)
 651                 __dwc3_gadget_ep_set_halt(dep, 0, false);
 652
 653         reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
 654         reg &= ~DWC3_DALEPENA_EP(dep->number);
 655         dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
 656
 657         dep->stream_capable = false;
 658         dep->endpoint.desc = NULL;
 659         dep->comp_desc = NULL;
 660         dep->type = 0;
 661         dep->flags = 0;
 662
 663         return 0;
 664 }
 665
 666 /* -------------------------------------------------------------------------- */
 667
 668 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
 669                 const struct usb_endpoint_descriptor *desc)
 670 {
 671         return -EINVAL;
 672 }
 673
 674 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
 675 {
 676         return -EINVAL;
 677 }
 678
 679 /* -------------------------------------------------------------------------- */
 680
 681 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
 682                 const struct usb_endpoint_descriptor *desc)
 683 {
 684         struct dwc3_ep                  *dep;
 685         struct dwc3                     *dwc;
 686         unsigned long                   flags;
 687         int                             ret;
 688
 689         if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
 690                 pr_debug("dwc3: invalid parameters\n");
 691                 return -EINVAL;
 692         }
 693
 694         if (!desc->wMaxPacketSize) {
 695                 pr_debug("dwc3: missing wMaxPacketSize\n");
 696                 return -EINVAL;
 697         }
 698
 699         dep = to_dwc3_ep(ep);
 700         dwc = dep->dwc;
 701
 702         if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
 703                                         "%s is already enabled\n",
 704                                         dep->name))
 705                 return 0;
 706
 707         spin_lock_irqsave(&dwc->lock, flags);
 708         ret = __dwc3_gadget_ep_enable(dep, desc, ep->comp_desc, false, false);
 709         spin_unlock_irqrestore(&dwc->lock, flags);
 710
 711         return ret;
 712 }
 713
 714 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
 715 {
 716         struct dwc3_ep                  *dep;
 717         struct dwc3                     *dwc;
 718         unsigned long                   flags;
 719         int                             ret;
 720
 721         if (!ep) {
 722                 pr_debug("dwc3: invalid parameters\n");
 723                 return -EINVAL;
 724         }
 725
 726         dep = to_dwc3_ep(ep);
 727         dwc = dep->dwc;
 728
 729         if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
 730                                         "%s is already disabled\n",
 731                                         dep->name))
 732                 return 0;
 733
 734         spin_lock_irqsave(&dwc->lock, flags);
 735         ret = __dwc3_gadget_ep_disable(dep);
 736         spin_unlock_irqrestore(&dwc->lock, flags);
 737
 738         return ret;
 739 }
 740
 741 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
 742         gfp_t gfp_flags)
 743 {
 744         struct dwc3_request             *req;
 745         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 746
 747         req = kzalloc(sizeof(*req), gfp_flags);
 748         if (!req)
 749                 return NULL;
 750
 751         req->epnum      = dep->number;
 752         req->dep        = dep;
 753
 754         dep->allocated_requests++;
 755
 756         trace_dwc3_alloc_request(req);
 757
 758         return &req->request;
 759 }
 760
 761 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
 762                 struct usb_request *request)
 763 {
 764         struct dwc3_request             *req = to_dwc3_request(request);
 765         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 766
 767         dep->allocated_requests--;
 768         trace_dwc3_free_request(req);
 769         kfree(req);
 770 }
 771
 772 /**
 773  * dwc3_prepare_one_trb - setup one TRB from one request
 774  * @dep: endpoint for which this request is prepared
 775  * @req: dwc3_request pointer
 776  */
 777 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
 778                 struct dwc3_request *req, dma_addr_t dma,
 779                 unsigned length, unsigned last, unsigned chain, unsigned node)
 780 {
 781         struct dwc3_trb         *trb;
 782
 783         dwc3_trace(trace_dwc3_gadget, "%s: req %p dma %08llx length %d%s%s",
 784                         dep->name, req, (unsigned long long) dma,
 785                         length, last ? " last" : "",
 786                         chain ? " chain" : "");
 787
 788
 789         trb = &dep->trb_pool[dep->trb_enqueue];
 790
 791         if (!req->trb) {
 792                 dwc3_gadget_move_started_request(req);
 793                 req->trb = trb;
 794                 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
 795                 req->first_trb_index = dep->trb_enqueue;
 796         }
 797
 798         dwc3_ep_inc_enq(dep);
 799
 800         trb->size = DWC3_TRB_SIZE_LENGTH(length);
 801         trb->bpl = lower_32_bits(dma);
 802         trb->bph = upper_32_bits(dma);
 803
 804         switch (usb_endpoint_type(dep->endpoint.desc)) {
 805         case USB_ENDPOINT_XFER_CONTROL:
 806                 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
 807                 break;
 808
 809         case USB_ENDPOINT_XFER_ISOC:
 810                 if (!node)
 811                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
 812                 else
 813                         trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
 814
 815                 /* always enable Interrupt on Missed ISOC */
 816                 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
 817                 break;
 818
 819         case USB_ENDPOINT_XFER_BULK:
 820         case USB_ENDPOINT_XFER_INT:
 821                 trb->ctrl = DWC3_TRBCTL_NORMAL;
 822                 break;
 823         default:
 824                 /*
 825                  * This is only possible with faulty memory because we
 826                  * checked it already :)
 827                  */
 828                 BUG();
 829         }
 830
 831         /* always enable Continue on Short Packet */
 832         trb->ctrl |= DWC3_TRB_CTRL_CSP;
 833
 834         if (!req->request.no_interrupt && !chain)
 835                 trb->ctrl |= DWC3_TRB_CTRL_IOC | DWC3_TRB_CTRL_ISP_IMI;
 836
 837         if (last)
 838                 trb->ctrl |= DWC3_TRB_CTRL_LST;
 839
 840         if (chain)
 841                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
 842
 843         if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
 844                 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(req->request.stream_id);
 845
 846         trb->ctrl |= DWC3_TRB_CTRL_HWO;
 847
 848         dep->queued_requests++;
 849
 850         trace_dwc3_prepare_trb(dep, trb);
 851 }
 852
 853 /**
 854  * dwc3_ep_prev_trb() - Returns the previous TRB in the ring
 855  * @dep: The endpoint with the TRB ring
 856  * @index: The index of the current TRB in the ring
 857  *
 858  * Returns the TRB prior to the one pointed to by the index. If the
 859  * index is 0, we will wrap backwards, skip the link TRB, and return
 860  * the one just before that.
 861  */
 862 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
 863 {
 864         if (!index)
 865                 index = DWC3_TRB_NUM - 2;
 866         else
 867                 index = dep->trb_enqueue - 1;
 868
 869         return &dep->trb_pool[index];
 870 }
 871
 872 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
 873 {
 874         struct dwc3_trb         *tmp;
 875         u8                      trbs_left;
 876
 877         /*
 878          * If enqueue & dequeue are equal than it is either full or empty.
 879          *
 880          * One way to know for sure is if the TRB right before us has HWO bit
 881          * set or not. If it has, then we're definitely full and can't fit any
 882          * more transfers in our ring.
 883          */
 884         if (dep->trb_enqueue == dep->trb_dequeue) {
 885                 tmp = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
 886                 if (tmp->ctrl & DWC3_TRB_CTRL_HWO)
 887                         return 0;
 888
 889                 return DWC3_TRB_NUM - 1;
 890         }
 891
 892         trbs_left = dep->trb_dequeue - dep->trb_enqueue;
 893         trbs_left &= (DWC3_TRB_NUM - 1);
 894
 895         if (dep->trb_dequeue < dep->trb_enqueue)
 896                 trbs_left--;
 897
 898         return trbs_left;
 899 }
 900
 901 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
 902                 struct dwc3_request *req, unsigned int trbs_left,
 903                 unsigned int more_coming)
 904 {
 905         struct usb_request *request = &req->request;
 906         struct scatterlist *sg = request->sg;
 907         struct scatterlist *s;
 908         unsigned int    last = false;
 909         unsigned int    length;
 910         dma_addr_t      dma;
 911         int             i;
 912
 913         for_each_sg(sg, s, request->num_mapped_sgs, i) {
 914                 unsigned chain = true;
 915
 916                 length = sg_dma_len(s);
 917                 dma = sg_dma_address(s);
 918
 919                 if (sg_is_last(s)) {
 920                         if (usb_endpoint_xfer_int(dep->endpoint.desc) ||
 921                                 !more_coming)
 922                                 last = true;
 923
 924                         chain = false;
 925                 }
 926
 927                 if (!trbs_left)
 928                         last = true;
 929
 930                 if (last)
 931                         chain = false;
 932
 933                 dwc3_prepare_one_trb(dep, req, dma, length,
 934                                 last, chain, i);
 935
 936                 if (last)
 937                         break;
 938         }
 939 }
 940
 941 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
 942                 struct dwc3_request *req, unsigned int trbs_left,
 943                 unsigned int more_coming)
 944 {
 945         unsigned int    last = false;
 946         unsigned int    length;
 947         dma_addr_t      dma;
 948
 949         dma = req->request.dma;
 950         length = req->request.length;
 951
 952         if (!trbs_left)
 953                 last = true;
 954
 955         /* Is this the last request? */
 956         if (usb_endpoint_xfer_int(dep->endpoint.desc) || !more_coming)
 957                 last = true;
 958
 959         dwc3_prepare_one_trb(dep, req, dma, length,
 960                         last, false, 0);
 961 }
 962
 963 /*
 964  * dwc3_prepare_trbs - setup TRBs from requests
 965  * @dep: endpoint for which requests are being prepared
 966  *
 967  * The function goes through the requests list and sets up TRBs for the
 968  * transfers. The function returns once there are no more TRBs available or
 969  * it runs out of requests.
 970  */
 971 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
 972 {
 973         struct dwc3_request     *req, *n;
 974         unsigned int            more_coming;
 975         u32                     trbs_left;
 976
 977         BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
 978
 979         trbs_left = dwc3_calc_trbs_left(dep);
 980         if (!trbs_left)
 981                 return;
 982
 983         more_coming = dep->allocated_requests - dep->queued_requests;
 984
 985         list_for_each_entry_safe(req, n, &dep->pending_list, list) {
 986                 if (req->request.num_mapped_sgs > 0)
 987                         dwc3_prepare_one_trb_sg(dep, req, trbs_left--,
 988                                         more_coming);
 989                 else
 990                         dwc3_prepare_one_trb_linear(dep, req, trbs_left--,
 991                                         more_coming);
 992
 993                 if (!trbs_left)
 994                         return;
 995         }
 996 }
 997
 998 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
 999 {
1000         struct dwc3_gadget_ep_cmd_params params;
1001         struct dwc3_request             *req;
1002         struct dwc3                     *dwc = dep->dwc;
1003         int                             starting;
1004         int                             ret;
1005         u32                             cmd;
1006
1007         starting = !(dep->flags & DWC3_EP_BUSY);
1008
1009         dwc3_prepare_trbs(dep);
1010         req = next_request(&dep->started_list);
1011         if (!req) {
1012                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1013                 return 0;
1014         }
1015
1016         memset(&params, 0, sizeof(params));
1017
1018         if (starting) {
1019                 params.param0 = upper_32_bits(req->trb_dma);
1020                 params.param1 = lower_32_bits(req->trb_dma);
1021                 cmd = DWC3_DEPCMD_STARTTRANSFER |
1022                         DWC3_DEPCMD_PARAM(cmd_param);
1023         } else {
1024                 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1025                         DWC3_DEPCMD_PARAM(dep->resource_index);
1026         }
1027
1028         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1029         if (ret < 0) {
1030                 /*
1031                  * FIXME we need to iterate over the list of requests
1032                  * here and stop, unmap, free and del each of the linked
1033                  * requests instead of what we do now.
1034                  */
1035                 usb_gadget_unmap_request(&dwc->gadget, &req->request,
1036                                 req->direction);
1037                 list_del(&req->list);
1038                 return ret;
1039         }
1040
1041         dep->flags |= DWC3_EP_BUSY;
1042
1043         if (starting) {
1044                 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1045                 WARN_ON_ONCE(!dep->resource_index);
1046         }
1047
1048         return 0;
1049 }
1050
1051 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1052                 struct dwc3_ep *dep, u32 cur_uf)
1053 {
1054         u32 uf;
1055
1056         if (list_empty(&dep->pending_list)) {
1057                 dwc3_trace(trace_dwc3_gadget,
1058                                 "ISOC ep %s run out for requests",
1059                                 dep->name);
1060                 dep->flags |= DWC3_EP_PENDING_REQUEST;
1061                 return;
1062         }
1063
1064         /* 4 micro frames in the future */
1065         uf = cur_uf + dep->interval * 4;
1066
1067         __dwc3_gadget_kick_transfer(dep, uf);
1068 }
1069
1070 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1071                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1072 {
1073         u32 cur_uf, mask;
1074
1075         mask = ~(dep->interval - 1);
1076         cur_uf = event->parameters & mask;
1077
1078         __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1079 }
1080
1081 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1082 {
1083         struct dwc3             *dwc = dep->dwc;
1084         int                     ret;
1085
1086         if (!dep->endpoint.desc) {
1087                 dwc3_trace(trace_dwc3_gadget,
1088                                 "trying to queue request %p to disabled %s",
1089                                 &req->request, dep->endpoint.name);
1090                 return -ESHUTDOWN;
1091         }
1092
1093         if (WARN(req->dep != dep, "request %p belongs to '%s'\n",
1094                                 &req->request, req->dep->name)) {
1095                 dwc3_trace(trace_dwc3_gadget, "request %p belongs to '%s'",
1096                                 &req->request, req->dep->name);
1097                 return -EINVAL;
1098         }
1099
1100         pm_runtime_get(dwc->dev);
1101
1102         req->request.actual     = 0;
1103         req->request.status     = -EINPROGRESS;
1104         req->direction          = dep->direction;
1105         req->epnum              = dep->number;
1106
1107         trace_dwc3_ep_queue(req);
1108
1109         /*
1110          * Per databook, the total size of buffer must be a multiple
1111          * of MaxPacketSize for OUT endpoints. And MaxPacketSize is
1112          * configed for endpoints in dwc3_gadget_set_ep_config(),
1113          * set to usb_endpoint_descriptor->wMaxPacketSize.
1114          */
1115         if (dep->direction == 0 &&
1116             req->request.length % dep->endpoint.desc->wMaxPacketSize)
1117                 req->request.length = roundup(req->request.length,
1118                                         dep->endpoint.desc->wMaxPacketSize);
1119
1120         /*
1121          * We only add to our list of requests now and
1122          * start consuming the list once we get XferNotReady
1123          * IRQ.
1124          *
1125          * That way, we avoid doing anything that we don't need
1126          * to do now and defer it until the point we receive a
1127          * particular token from the Host side.
1128          *
1129          * This will also avoid Host cancelling URBs due to too
1130          * many NAKs.
1131          */
1132         ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1133                         dep->direction);
1134         if (ret)
1135                 return ret;
1136
1137         list_add_tail(&req->list, &dep->pending_list);
1138
1139         /*
1140          * If there are no pending requests and the endpoint isn't already
1141          * busy, we will just start the request straight away.
1142          *
1143          * This will save one IRQ (XFER_NOT_READY) and possibly make it a
1144          * little bit faster.
1145          */
1146         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1147                         !usb_endpoint_xfer_int(dep->endpoint.desc)) {
1148                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1149                 goto out;
1150         }
1151
1152         /*
1153          * There are a few special cases:
1154          *
1155          * 1. XferNotReady with empty list of requests. We need to kick the
1156          *    transfer here in that situation, otherwise we will be NAKing
1157          *    forever. If we get XferNotReady before gadget driver has a
1158          *    chance to queue a request, we will ACK the IRQ but won't be
1159          *    able to receive the data until the next request is queued.
1160          *    The following code is handling exactly that.
1161          *
1162          */
1163         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
1164                 /*
1165                  * If xfernotready is already elapsed and it is a case
1166                  * of isoc transfer, then issue END TRANSFER, so that
1167                  * you can receive xfernotready again and can have
1168                  * notion of current microframe.
1169                  */
1170                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1171                         if (list_empty(&dep->started_list)) {
1172                                 dwc3_stop_active_transfer(dwc, dep->number, true);
1173                                 dep->flags = DWC3_EP_ENABLED;
1174                         }
1175                         return 0;
1176                 }
1177
1178                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1179                 if (!ret)
1180                         dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1181
1182                 goto out;
1183         }
1184
1185         /*
1186          * 2. XferInProgress on Isoc EP with an active transfer. We need to
1187          *    kick the transfer here after queuing a request, otherwise the
1188          *    core may not see the modified TRB(s).
1189          */
1190         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
1191                         (dep->flags & DWC3_EP_BUSY) &&
1192                         !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1193                 WARN_ON_ONCE(!dep->resource_index);
1194                 ret = __dwc3_gadget_kick_transfer(dep, dep->resource_index);
1195                 goto out;
1196         }
1197
1198         /*
1199          * 4. Stream Capable Bulk Endpoints. We need to start the transfer
1200          * right away, otherwise host will not know we have streams to be
1201          * handled.
1202          */
1203         if (dep->stream_capable)
1204                 ret = __dwc3_gadget_kick_transfer(dep, 0);
1205
1206 out:
1207         if (ret && ret != -EBUSY)
1208                 dwc3_trace(trace_dwc3_gadget,
1209                                 "%s: failed to kick transfers",
1210                                 dep->name);
1211         if (ret == -EBUSY)
1212                 ret = 0;
1213
1214         return ret;
1215 }
1216
1217 static void __dwc3_gadget_ep_zlp_complete(struct usb_ep *ep,
1218                 struct usb_request *request)
1219 {
1220         dwc3_gadget_ep_free_request(ep, request);
1221 }
1222
1223 static int __dwc3_gadget_ep_queue_zlp(struct dwc3 *dwc, struct dwc3_ep *dep)
1224 {
1225         struct dwc3_request             *req;
1226         struct usb_request              *request;
1227         struct usb_ep                   *ep = &dep->endpoint;
1228
1229         dwc3_trace(trace_dwc3_gadget, "queueing ZLP");
1230         request = dwc3_gadget_ep_alloc_request(ep, GFP_ATOMIC);
1231         if (!request)
1232                 return -ENOMEM;
1233
1234         request->length = 0;
1235         request->buf = dwc->zlp_buf;
1236         request->complete = __dwc3_gadget_ep_zlp_complete;
1237
1238         req = to_dwc3_request(request);
1239
1240         return __dwc3_gadget_ep_queue(dep, req);
1241 }
1242
1243 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1244         gfp_t gfp_flags)
1245 {
1246         struct dwc3_request             *req = to_dwc3_request(request);
1247         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1248         struct dwc3                     *dwc = dep->dwc;
1249
1250         unsigned long                   flags;
1251
1252         int                             ret;
1253
1254         spin_lock_irqsave(&dwc->lock, flags);
1255         ret = __dwc3_gadget_ep_queue(dep, req);
1256
1257         /*
1258          * Okay, here's the thing, if gadget driver has requested for a ZLP by
1259          * setting request->zero, instead of doing magic, we will just queue an
1260          * extra usb_request ourselves so that it gets handled the same way as
1261          * any other request.
1262          */
1263         if (ret == 0 && request->zero && request->length &&
1264             (request->length % ep->desc->wMaxPacketSize == 0))
1265                 ret = __dwc3_gadget_ep_queue_zlp(dwc, dep);
1266
1267         spin_unlock_irqrestore(&dwc->lock, flags);
1268
1269         return ret;
1270 }
1271
1272 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1273                 struct usb_request *request)
1274 {
1275         struct dwc3_request             *req = to_dwc3_request(request);
1276         struct dwc3_request             *r = NULL;
1277
1278         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1279         struct dwc3                     *dwc = dep->dwc;
1280
1281         unsigned long                   flags;
1282         int                             ret = 0;
1283
1284         trace_dwc3_ep_dequeue(req);
1285
1286         spin_lock_irqsave(&dwc->lock, flags);
1287
1288         list_for_each_entry(r, &dep->pending_list, list) {
1289                 if (r == req)
1290                         break;
1291         }
1292
1293         if (r != req) {
1294                 list_for_each_entry(r, &dep->started_list, list) {
1295                         if (r == req)
1296                                 break;
1297                 }
1298                 if (r == req) {
1299                         /* wait until it is processed */
1300                         dwc3_stop_active_transfer(dwc, dep->number, true);
1301                         goto out1;
1302                 }
1303                 dev_err(dwc->dev, "request %p was not queued to %s\n",
1304                                 request, ep->name);
1305                 ret = -EINVAL;
1306                 goto out0;
1307         }
1308
1309 out1:
1310         /* giveback the request */
1311         dwc3_gadget_giveback(dep, req, -ECONNRESET);
1312
1313 out0:
1314         spin_unlock_irqrestore(&dwc->lock, flags);
1315
1316         return ret;
1317 }
1318
1319 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1320 {
1321         struct dwc3_gadget_ep_cmd_params        params;
1322         struct dwc3                             *dwc = dep->dwc;
1323         int                                     ret;
1324
1325         if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1326                 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1327                 return -EINVAL;
1328         }
1329
1330         memset(&params, 0x00, sizeof(params));
1331
1332         if (value) {
1333                 struct dwc3_trb *trb;
1334
1335                 unsigned transfer_in_flight;
1336                 unsigned started;
1337
1338                 if (dep->number > 1)
1339                         trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1340                 else
1341                         trb = &dwc->ep0_trb[dep->trb_enqueue];
1342
1343                 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1344                 started = !list_empty(&dep->started_list);
1345
1346                 if (!protocol && ((dep->direction && transfer_in_flight) ||
1347                                 (!dep->direction && started))) {
1348                         dwc3_trace(trace_dwc3_gadget,
1349                                         "%s: pending request, cannot halt",
1350                                         dep->name);
1351                         return -EAGAIN;
1352                 }
1353
1354                 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1355                                 &params);
1356                 if (ret)
1357                         dev_err(dwc->dev, "failed to set STALL on %s\n",
1358                                         dep->name);
1359                 else
1360                         dep->flags |= DWC3_EP_STALL;
1361         } else {
1362
1363                 ret = dwc3_send_clear_stall_ep_cmd(dep);
1364                 if (ret)
1365                         dev_err(dwc->dev, "failed to clear STALL on %s\n",
1366                                         dep->name);
1367                 else
1368                         dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1369         }
1370
1371         return ret;
1372 }
1373
1374 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1375 {
1376         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1377         struct dwc3                     *dwc = dep->dwc;
1378
1379         unsigned long                   flags;
1380
1381         int                             ret;
1382
1383         spin_lock_irqsave(&dwc->lock, flags);
1384         ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1385         spin_unlock_irqrestore(&dwc->lock, flags);
1386
1387         return ret;
1388 }
1389
1390 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1391 {
1392         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
1393         struct dwc3                     *dwc = dep->dwc;
1394         unsigned long                   flags;
1395         int                             ret;
1396
1397         spin_lock_irqsave(&dwc->lock, flags);
1398         dep->flags |= DWC3_EP_WEDGE;
1399
1400         if (dep->number == 0 || dep->number == 1)
1401                 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1402         else
1403                 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1404         spin_unlock_irqrestore(&dwc->lock, flags);
1405
1406         return ret;
1407 }
1408
1409 /* -------------------------------------------------------------------------- */
1410
1411 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1412         .bLength        = USB_DT_ENDPOINT_SIZE,
1413         .bDescriptorType = USB_DT_ENDPOINT,
1414         .bmAttributes   = USB_ENDPOINT_XFER_CONTROL,
1415 };
1416
1417 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1418         .enable         = dwc3_gadget_ep0_enable,
1419         .disable        = dwc3_gadget_ep0_disable,
1420         .alloc_request  = dwc3_gadget_ep_alloc_request,
1421         .free_request   = dwc3_gadget_ep_free_request,
1422         .queue          = dwc3_gadget_ep0_queue,
1423         .dequeue        = dwc3_gadget_ep_dequeue,
1424         .set_halt       = dwc3_gadget_ep0_set_halt,
1425         .set_wedge      = dwc3_gadget_ep_set_wedge,
1426 };
1427
1428 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1429         .enable         = dwc3_gadget_ep_enable,
1430         .disable        = dwc3_gadget_ep_disable,
1431         .alloc_request  = dwc3_gadget_ep_alloc_request,
1432         .free_request   = dwc3_gadget_ep_free_request,
1433         .queue          = dwc3_gadget_ep_queue,
1434         .dequeue        = dwc3_gadget_ep_dequeue,
1435         .set_halt       = dwc3_gadget_ep_set_halt,
1436         .set_wedge      = dwc3_gadget_ep_set_wedge,
1437 };
1438
1439 /* -------------------------------------------------------------------------- */
1440
1441 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1442 {
1443         struct dwc3             *dwc = gadget_to_dwc(g);
1444         u32                     reg;
1445
1446         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1447         return DWC3_DSTS_SOFFN(reg);
1448 }
1449
1450 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1451 {
1452         unsigned long           timeout;
1453
1454         int                     ret;
1455         u32                     reg;
1456
1457         u8                      link_state;
1458         u8                      speed;
1459
1460         /*
1461          * According to the Databook Remote wakeup request should
1462          * be issued only when the device is in early suspend state.
1463          *
1464          * We can check that via USB Link State bits in DSTS register.
1465          */
1466         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1467
1468         speed = reg & DWC3_DSTS_CONNECTSPD;
1469         if (speed == DWC3_DSTS_SUPERSPEED) {
1470                 dwc3_trace(trace_dwc3_gadget, "no wakeup on SuperSpeed");
1471                 return 0;
1472         }
1473
1474         link_state = DWC3_DSTS_USBLNKST(reg);
1475
1476         switch (link_state) {
1477         case DWC3_LINK_STATE_RX_DET:    /* in HS, means Early Suspend */
1478         case DWC3_LINK_STATE_U3:        /* in HS, means SUSPEND */
1479                 break;
1480         default:
1481                 dwc3_trace(trace_dwc3_gadget,
1482                                 "can't wakeup from '%s'",
1483                                 dwc3_gadget_link_string(link_state));
1484                 return -EINVAL;
1485         }
1486
1487         ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1488         if (ret < 0) {
1489                 dev_err(dwc->dev, "failed to put link in Recovery\n");
1490                 return ret;
1491         }
1492
1493         /* Recent versions do this automatically */
1494         if (dwc->revision < DWC3_REVISION_194A) {
1495                 /* write zeroes to Link Change Request */
1496                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1497                 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1498                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1499         }
1500
1501         /* poll until Link State changes to ON */
1502         timeout = jiffies + msecs_to_jiffies(100);
1503
1504         while (!time_after(jiffies, timeout)) {
1505                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1506
1507                 /* in HS, means ON */
1508                 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1509                         break;
1510         }
1511
1512         if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1513                 dev_err(dwc->dev, "failed to send remote wakeup\n");
1514                 return -EINVAL;
1515         }
1516
1517         return 0;
1518 }
1519
1520 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1521 {
1522         struct dwc3             *dwc = gadget_to_dwc(g);
1523         unsigned long           flags;
1524         int                     ret;
1525
1526         spin_lock_irqsave(&dwc->lock, flags);
1527         ret = __dwc3_gadget_wakeup(dwc);
1528         spin_unlock_irqrestore(&dwc->lock, flags);
1529
1530         return ret;
1531 }
1532
1533 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1534                 int is_selfpowered)
1535 {
1536         struct dwc3             *dwc = gadget_to_dwc(g);
1537         unsigned long           flags;
1538
1539         spin_lock_irqsave(&dwc->lock, flags);
1540         g->is_selfpowered = !!is_selfpowered;
1541         spin_unlock_irqrestore(&dwc->lock, flags);
1542
1543         return 0;
1544 }
1545
1546 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1547 {
1548         u32                     reg;
1549         u32                     timeout = 500;
1550
1551         if (pm_runtime_suspended(dwc->dev))
1552                 return 0;
1553
1554         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1555         if (is_on) {
1556                 if (dwc->revision <= DWC3_REVISION_187A) {
1557                         reg &= ~DWC3_DCTL_TRGTULST_MASK;
1558                         reg |= DWC3_DCTL_TRGTULST_RX_DET;
1559                 }
1560
1561                 if (dwc->revision >= DWC3_REVISION_194A)
1562                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1563                 reg |= DWC3_DCTL_RUN_STOP;
1564
1565                 if (dwc->has_hibernation)
1566                         reg |= DWC3_DCTL_KEEP_CONNECT;
1567
1568                 dwc->pullups_connected = true;
1569         } else {
1570                 reg &= ~DWC3_DCTL_RUN_STOP;
1571
1572                 if (dwc->has_hibernation && !suspend)
1573                         reg &= ~DWC3_DCTL_KEEP_CONNECT;
1574
1575                 dwc->pullups_connected = false;
1576         }
1577
1578         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1579
1580         do {
1581                 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1582                 if (is_on) {
1583                         if (!(reg & DWC3_DSTS_DEVCTRLHLT))
1584                                 break;
1585                 } else {
1586                         if (reg & DWC3_DSTS_DEVCTRLHLT)
1587                                 break;
1588                 }
1589                 timeout--;
1590                 if (!timeout)
1591                         return -ETIMEDOUT;
1592                 udelay(1);
1593         } while (1);
1594
1595         dwc3_trace(trace_dwc3_gadget, "gadget %s data soft-%s",
1596                         dwc->gadget_driver
1597                         ? dwc->gadget_driver->function : "no-function",
1598                         is_on ? "connect" : "disconnect");
1599
1600         return 0;
1601 }
1602
1603 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1604 {
1605         struct dwc3             *dwc = gadget_to_dwc(g);
1606         unsigned long           flags;
1607         int                     ret;
1608
1609         is_on = !!is_on;
1610
1611         spin_lock_irqsave(&dwc->lock, flags);
1612         ret = dwc3_gadget_run_stop(dwc, is_on, false);
1613         spin_unlock_irqrestore(&dwc->lock, flags);
1614
1615         return ret;
1616 }
1617
1618 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1619 {
1620         u32                     reg;
1621
1622         /* Enable all but Start and End of Frame IRQs */
1623         reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1624                         DWC3_DEVTEN_EVNTOVERFLOWEN |
1625                         DWC3_DEVTEN_CMDCMPLTEN |
1626                         DWC3_DEVTEN_ERRTICERREN |
1627                         DWC3_DEVTEN_WKUPEVTEN |
1628                         DWC3_DEVTEN_ULSTCNGEN |
1629                         DWC3_DEVTEN_CONNECTDONEEN |
1630                         DWC3_DEVTEN_USBRSTEN |
1631                         DWC3_DEVTEN_DISCONNEVTEN);
1632
1633         dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1634 }
1635
1636 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1637 {
1638         /* mask all interrupts */
1639         dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1640 }
1641
1642 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1643 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1644
1645 /**
1646  * dwc3_gadget_setup_nump - Calculate and initialize NUMP field of DCFG
1647  * dwc: pointer to our context structure
1648  *
1649  * The following looks like complex but it's actually very simple. In order to
1650  * calculate the number of packets we can burst at once on OUT transfers, we're
1651  * gonna use RxFIFO size.
1652  *
1653  * To calculate RxFIFO size we need two numbers:
1654  * MDWIDTH = size, in bits, of the internal memory bus
1655  * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1656  *
1657  * Given these two numbers, the formula is simple:
1658  *
1659  * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1660  *
1661  * 24 bytes is for 3x SETUP packets
1662  * 16 bytes is a clock domain crossing tolerance
1663  *
1664  * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1665  */
1666 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1667 {
1668         u32 ram2_depth;
1669         u32 mdwidth;
1670         u32 nump;
1671         u32 reg;
1672
1673         ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1674         mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1675
1676         nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1677         nump = min_t(u32, nump, 16);
1678
1679         /* update NumP */
1680         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1681         reg &= ~DWC3_DCFG_NUMP_MASK;
1682         reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1683         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1684 }
1685
1686 static int __dwc3_gadget_start(struct dwc3 *dwc)
1687 {
1688         struct dwc3_ep          *dep;
1689         int                     ret = 0;
1690         u32                     reg;
1691
1692         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1693         reg &= ~(DWC3_DCFG_SPEED_MASK);
1694
1695         /**
1696          * WORKAROUND: DWC3 revision < 2.20a have an issue
1697          * which would cause metastability state on Run/Stop
1698          * bit if we try to force the IP to USB2-only mode.
1699          *
1700          * Because of that, we cannot configure the IP to any
1701          * speed other than the SuperSpeed
1702          *
1703          * Refers to:
1704          *
1705          * STAR#9000525659: Clock Domain Crossing on DCTL in
1706          * USB 2.0 Mode
1707          */
1708         if (dwc->revision < DWC3_REVISION_220A) {
1709                 reg |= DWC3_DCFG_SUPERSPEED;
1710         } else {
1711                 switch (dwc->maximum_speed) {
1712                 case USB_SPEED_LOW:
1713                         reg |= DWC3_DCFG_LOWSPEED;
1714                         break;
1715                 case USB_SPEED_FULL:
1716                         reg |= DWC3_DCFG_FULLSPEED1;
1717                         break;
1718                 case USB_SPEED_HIGH:
1719                         reg |= DWC3_DCFG_HIGHSPEED;
1720                         break;
1721                 case USB_SPEED_SUPER:   /* FALLTHROUGH */
1722                 case USB_SPEED_UNKNOWN: /* FALTHROUGH */
1723                 default:
1724                         reg |= DWC3_DCFG_SUPERSPEED;
1725                 }
1726         }
1727         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1728
1729         /*
1730          * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1731          * field instead of letting dwc3 itself calculate that automatically.
1732          *
1733          * This way, we maximize the chances that we'll be able to get several
1734          * bursts of data without going through any sort of endpoint throttling.
1735          */
1736         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1737         reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1738         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1739
1740         dwc3_gadget_setup_nump(dwc);
1741
1742         /* Start with SuperSpeed Default */
1743         dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1744
1745         dep = dwc->eps[0];
1746         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1747                         false);
1748         if (ret) {
1749                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1750                 goto err0;
1751         }
1752
1753         dep = dwc->eps[1];
1754         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, false,
1755                         false);
1756         if (ret) {
1757                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1758                 goto err1;
1759         }
1760
1761         /* begin to receive SETUP packets */
1762         dwc->ep0state = EP0_SETUP_PHASE;
1763         dwc3_ep0_out_start(dwc);
1764
1765         dwc3_gadget_enable_irq(dwc);
1766
1767         return 0;
1768
1769 err1:
1770         __dwc3_gadget_ep_disable(dwc->eps[0]);
1771
1772 err0:
1773         return ret;
1774 }
1775
1776 static int dwc3_gadget_start(struct usb_gadget *g,
1777                 struct usb_gadget_driver *driver)
1778 {
1779         struct dwc3             *dwc = gadget_to_dwc(g);
1780         unsigned long           flags;
1781         int                     ret = 0;
1782         int                     irq;
1783
1784         irq = platform_get_irq(to_platform_device(dwc->dev), 0);
1785         ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1786                         IRQF_SHARED, "dwc3", dwc->ev_buf);
1787         if (ret) {
1788                 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1789                                 irq, ret);
1790                 goto err0;
1791         }
1792         dwc->irq_gadget = irq;
1793
1794         spin_lock_irqsave(&dwc->lock, flags);
1795         if (dwc->gadget_driver) {
1796                 dev_err(dwc->dev, "%s is already bound to %s\n",
1797                                 dwc->gadget.name,
1798                                 dwc->gadget_driver->driver.name);
1799                 ret = -EBUSY;
1800                 goto err1;
1801         }
1802
1803         dwc->gadget_driver      = driver;
1804
1805         if (pm_runtime_active(dwc->dev))
1806                 __dwc3_gadget_start(dwc);
1807
1808         spin_unlock_irqrestore(&dwc->lock, flags);
1809
1810         return 0;
1811
1812 err1:
1813         spin_unlock_irqrestore(&dwc->lock, flags);
1814         free_irq(irq, dwc);
1815
1816 err0:
1817         return ret;
1818 }
1819
1820 static void __dwc3_gadget_stop(struct dwc3 *dwc)
1821 {
1822         dwc3_gadget_disable_irq(dwc);
1823         __dwc3_gadget_ep_disable(dwc->eps[0]);
1824         __dwc3_gadget_ep_disable(dwc->eps[1]);
1825 }
1826
1827 static int dwc3_gadget_stop(struct usb_gadget *g)
1828 {
1829         struct dwc3             *dwc = gadget_to_dwc(g);
1830         unsigned long           flags;
1831
1832         spin_lock_irqsave(&dwc->lock, flags);
1833         __dwc3_gadget_stop(dwc);
1834         dwc->gadget_driver      = NULL;
1835         spin_unlock_irqrestore(&dwc->lock, flags);
1836
1837         free_irq(dwc->irq_gadget, dwc->ev_buf);
1838
1839         return 0;
1840 }
1841
1842 static const struct usb_gadget_ops dwc3_gadget_ops = {
1843         .get_frame              = dwc3_gadget_get_frame,
1844         .wakeup                 = dwc3_gadget_wakeup,
1845         .set_selfpowered        = dwc3_gadget_set_selfpowered,
1846         .pullup                 = dwc3_gadget_pullup,
1847         .udc_start              = dwc3_gadget_start,
1848         .udc_stop               = dwc3_gadget_stop,
1849 };
1850
1851 /* -------------------------------------------------------------------------- */
1852
1853 static int dwc3_gadget_init_hw_endpoints(struct dwc3 *dwc,
1854                 u8 num, u32 direction)
1855 {
1856         struct dwc3_ep                  *dep;
1857         u8                              i;
1858
1859         for (i = 0; i < num; i++) {
1860                 u8 epnum = (i << 1) | (direction ? 1 : 0);
1861
1862                 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
1863                 if (!dep)
1864                         return -ENOMEM;
1865
1866                 dep->dwc = dwc;
1867                 dep->number = epnum;
1868                 dep->direction = !!direction;
1869                 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
1870                 dwc->eps[epnum] = dep;
1871
1872                 snprintf(dep->name, sizeof(dep->name), "ep%d%s", epnum >> 1,
1873                                 (epnum & 1) ? "in" : "out");
1874
1875                 dep->endpoint.name = dep->name;
1876                 spin_lock_init(&dep->lock);
1877
1878                 dwc3_trace(trace_dwc3_gadget, "initializing %s", dep->name);
1879
1880                 if (epnum == 0 || epnum == 1) {
1881                         usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
1882                         dep->endpoint.maxburst = 1;
1883                         dep->endpoint.ops = &dwc3_gadget_ep0_ops;
1884                         if (!epnum)
1885                                 dwc->gadget.ep0 = &dep->endpoint;
1886                 } else {
1887                         int             ret;
1888
1889                         usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
1890                         dep->endpoint.max_streams = 15;
1891                         dep->endpoint.ops = &dwc3_gadget_ep_ops;
1892                         list_add_tail(&dep->endpoint.ep_list,
1893                                         &dwc->gadget.ep_list);
1894
1895                         ret = dwc3_alloc_trb_pool(dep);
1896                         if (ret)
1897                                 return ret;
1898                 }
1899
1900                 if (epnum == 0 || epnum == 1) {
1901                         dep->endpoint.caps.type_control = true;
1902                 } else {
1903                         dep->endpoint.caps.type_iso = true;
1904                         dep->endpoint.caps.type_bulk = true;
1905                         dep->endpoint.caps.type_int = true;
1906                 }
1907
1908                 dep->endpoint.caps.dir_in = !!direction;
1909                 dep->endpoint.caps.dir_out = !direction;
1910
1911                 INIT_LIST_HEAD(&dep->pending_list);
1912                 INIT_LIST_HEAD(&dep->started_list);
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc)
1919 {
1920         int                             ret;
1921
1922         INIT_LIST_HEAD(&dwc->gadget.ep_list);
1923
1924         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_out_eps, 0);
1925         if (ret < 0) {
1926                 dwc3_trace(trace_dwc3_gadget,
1927                                 "failed to allocate OUT endpoints");
1928                 return ret;
1929         }
1930
1931         ret = dwc3_gadget_init_hw_endpoints(dwc, dwc->num_in_eps, 1);
1932         if (ret < 0) {
1933                 dwc3_trace(trace_dwc3_gadget,
1934                                 "failed to allocate IN endpoints");
1935                 return ret;
1936         }
1937
1938         return 0;
1939 }
1940
1941 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
1942 {
1943         struct dwc3_ep                  *dep;
1944         u8                              epnum;
1945
1946         for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
1947                 dep = dwc->eps[epnum];
1948                 if (!dep)
1949                         continue;
1950                 /*
1951                  * Physical endpoints 0 and 1 are special; they form the
1952                  * bi-directional USB endpoint 0.
1953                  *
1954                  * For those two physical endpoints, we don't allocate a TRB
1955                  * pool nor do we add them the endpoints list. Due to that, we
1956                  * shouldn't do these two operations otherwise we would end up
1957                  * with all sorts of bugs when removing dwc3.ko.
1958                  */
1959                 if (epnum != 0 && epnum != 1) {
1960                         dwc3_free_trb_pool(dep);
1961                         list_del(&dep->endpoint.ep_list);
1962                 }
1963
1964                 kfree(dep);
1965         }
1966 }
1967
1968 /* -------------------------------------------------------------------------- */
1969
1970 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
1971                 struct dwc3_request *req, struct dwc3_trb *trb,
1972                 const struct dwc3_event_depevt *event, int status)
1973 {
1974         unsigned int            count;
1975         unsigned int            s_pkt = 0;
1976         unsigned int            trb_status;
1977
1978         dep->queued_requests--;
1979         trace_dwc3_complete_trb(dep, trb);
1980
1981         if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
1982                 /*
1983                  * We continue despite the error. There is not much we
1984                  * can do. If we don't clean it up we loop forever. If
1985                  * we skip the TRB then it gets overwritten after a
1986                  * while since we use them in a ring buffer. A BUG()
1987                  * would help. Lets hope that if this occurs, someone
1988                  * fixes the root cause instead of looking away :)
1989                  */
1990                 dev_err(dwc->dev, "%s's TRB (%p) still owned by HW\n",
1991                                 dep->name, trb);
1992         count = trb->size & DWC3_TRB_SIZE_MASK;
1993
1994         if (dep->direction) {
1995                 if (count) {
1996                         trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
1997                         if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
1998                                 dwc3_trace(trace_dwc3_gadget,
1999                                                 "%s: incomplete IN transfer",
2000                                                 dep->name);
2001                                 /*
2002                                  * If missed isoc occurred and there is
2003                                  * no request queued then issue END
2004                                  * TRANSFER, so that core generates
2005                                  * next xfernotready and we will issue
2006                                  * a fresh START TRANSFER.
2007                                  * If there are still queued request
2008                                  * then wait, do not issue either END
2009                                  * or UPDATE TRANSFER, just attach next
2010                                  * request in pending_list during
2011                                  * giveback.If any future queued request
2012                                  * is successfully transferred then we
2013                                  * will issue UPDATE TRANSFER for all
2014                                  * request in the pending_list.
2015                                  */
2016                                 dep->flags |= DWC3_EP_MISSED_ISOC;
2017                         } else {
2018                                 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2019                                                 dep->name);
2020                                 status = -ECONNRESET;
2021                         }
2022                 } else {
2023                         dep->flags &= ~DWC3_EP_MISSED_ISOC;
2024                 }
2025         } else {
2026                 if (count && (event->status & DEPEVT_STATUS_SHORT))
2027                         s_pkt = 1;
2028         }
2029
2030         /*
2031          * We assume here we will always receive the entire data block
2032          * which we should receive. Meaning, if we program RX to
2033          * receive 4K but we receive only 2K, we assume that's all we
2034          * should receive and we simply bounce the request back to the
2035          * gadget driver for further processing.
2036          */
2037         req->request.actual += req->request.length - count;
2038         if (s_pkt)
2039                 return 1;
2040         if ((event->status & DEPEVT_STATUS_LST) &&
2041                         (trb->ctrl & (DWC3_TRB_CTRL_LST |
2042                                 DWC3_TRB_CTRL_HWO)))
2043                 return 1;
2044         if ((event->status & DEPEVT_STATUS_IOC) &&
2045                         (trb->ctrl & DWC3_TRB_CTRL_IOC))
2046                 return 1;
2047         return 0;
2048 }
2049
2050 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2051                 const struct dwc3_event_depevt *event, int status)
2052 {
2053         struct dwc3_request     *req;
2054         struct dwc3_trb         *trb;
2055         unsigned int            slot;
2056         unsigned int            i;
2057         int                     ret;
2058
2059         do {
2060                 req = next_request(&dep->started_list);
2061                 if (WARN_ON_ONCE(!req))
2062                         return 1;
2063
2064                 i = 0;
2065                 do {
2066                         slot = req->first_trb_index + i;
2067                         if (slot == DWC3_TRB_NUM - 1)
2068                                 slot++;
2069                         slot %= DWC3_TRB_NUM;
2070                         trb = &dep->trb_pool[slot];
2071
2072                         ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2073                                         event, status);
2074                         if (ret)
2075                                 break;
2076                 } while (++i < req->request.num_mapped_sgs);
2077
2078                 dwc3_gadget_giveback(dep, req, status);
2079
2080                 if (ret)
2081                         break;
2082         } while (1);
2083
2084         /*
2085          * Our endpoint might get disabled by another thread during
2086          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2087          * early on so DWC3_EP_BUSY flag gets cleared
2088          */
2089         if (!dep->endpoint.desc)
2090                 return 1;
2091
2092         if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2093                         list_empty(&dep->started_list)) {
2094                 if (list_empty(&dep->pending_list)) {
2095                         /*
2096                          * If there is no entry in request list then do
2097                          * not issue END TRANSFER now. Just set PENDING
2098                          * flag, so that END TRANSFER is issued when an
2099                          * entry is added into request list.
2100                          */
2101                         dep->flags = DWC3_EP_PENDING_REQUEST;
2102                 } else {
2103                         dwc3_stop_active_transfer(dwc, dep->number, true);
2104                         dep->flags = DWC3_EP_ENABLED;
2105                 }
2106                 return 1;
2107         }
2108
2109         if (usb_endpoint_xfer_isoc(dep->endpoint.desc))
2110                 if ((event->status & DEPEVT_STATUS_IOC) &&
2111                                 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2112                         return 0;
2113         return 1;
2114 }
2115
2116 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2117                 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2118 {
2119         unsigned                status = 0;
2120         int                     clean_busy;
2121         u32                     is_xfer_complete;
2122
2123         is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2124
2125         if (event->status & DEPEVT_STATUS_BUSERR)
2126                 status = -ECONNRESET;
2127
2128         clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2129         if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2130                                 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2131                 dep->flags &= ~DWC3_EP_BUSY;
2132
2133         /*
2134          * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2135          * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2136          */
2137         if (dwc->revision < DWC3_REVISION_183A) {
2138                 u32             reg;
2139                 int             i;
2140
2141                 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2142                         dep = dwc->eps[i];
2143
2144                         if (!(dep->flags & DWC3_EP_ENABLED))
2145                                 continue;
2146
2147                         if (!list_empty(&dep->started_list))
2148                                 return;
2149                 }
2150
2151                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2152                 reg |= dwc->u1u2;
2153                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2154
2155                 dwc->u1u2 = 0;
2156         }
2157
2158         /*
2159          * Our endpoint might get disabled by another thread during
2160          * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2161          * early on so DWC3_EP_BUSY flag gets cleared
2162          */
2163         if (!dep->endpoint.desc)
2164                 return;
2165
2166         if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2167                 int ret;
2168
2169                 ret = __dwc3_gadget_kick_transfer(dep, 0);
2170                 if (!ret || ret == -EBUSY)
2171                         return;
2172         }
2173 }
2174
2175 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2176                 const struct dwc3_event_depevt *event)
2177 {
2178         struct dwc3_ep          *dep;
2179         u8                      epnum = event->endpoint_number;
2180
2181         dep = dwc->eps[epnum];
2182
2183         if (!(dep->flags & DWC3_EP_ENABLED))
2184                 return;
2185
2186         if (epnum == 0 || epnum == 1) {
2187                 dwc3_ep0_interrupt(dwc, event);
2188                 return;
2189         }
2190
2191         switch (event->endpoint_event) {
2192         case DWC3_DEPEVT_XFERCOMPLETE:
2193                 dep->resource_index = 0;
2194
2195                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2196                         dwc3_trace(trace_dwc3_gadget,
2197                                         "%s is an Isochronous endpoint",
2198                                         dep->name);
2199                         return;
2200                 }
2201
2202                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2203                 break;
2204         case DWC3_DEPEVT_XFERINPROGRESS:
2205                 dwc3_endpoint_transfer_complete(dwc, dep, event);
2206                 break;
2207         case DWC3_DEPEVT_XFERNOTREADY:
2208                 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2209                         dwc3_gadget_start_isoc(dwc, dep, event);
2210                 } else {
2211                         int active;
2212                         int ret;
2213
2214                         active = event->status & DEPEVT_STATUS_TRANSFER_ACTIVE;
2215
2216                         dwc3_trace(trace_dwc3_gadget, "%s: reason %s",
2217                                         dep->name, active ? "Transfer Active"
2218                                         : "Transfer Not Active");
2219
2220                         ret = __dwc3_gadget_kick_transfer(dep, 0);
2221                         if (!ret || ret == -EBUSY)
2222                                 return;
2223
2224                         dwc3_trace(trace_dwc3_gadget,
2225                                         "%s: failed to kick transfers",
2226                                         dep->name);
2227                 }
2228
2229                 break;
2230         case DWC3_DEPEVT_STREAMEVT:
2231                 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2232                         dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2233                                         dep->name);
2234                         return;
2235                 }
2236
2237                 switch (event->status) {
2238                 case DEPEVT_STREAMEVT_FOUND:
2239                         dwc3_trace(trace_dwc3_gadget,
2240                                         "Stream %d found and started",
2241                                         event->parameters);
2242
2243                         break;
2244                 case DEPEVT_STREAMEVT_NOTFOUND:
2245                         /* FALLTHROUGH */
2246                 default:
2247                         dwc3_trace(trace_dwc3_gadget,
2248                                         "unable to find suitable stream");
2249                 }
2250                 break;
2251         case DWC3_DEPEVT_RXTXFIFOEVT:
2252                 dwc3_trace(trace_dwc3_gadget, "%s FIFO Overrun", dep->name);
2253                 break;
2254         case DWC3_DEPEVT_EPCMDCMPLT:
2255                 dwc3_trace(trace_dwc3_gadget, "Endpoint Command Complete");
2256                 break;
2257         }
2258 }
2259
2260 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2261 {
2262         if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2263                 spin_unlock(&dwc->lock);
2264                 dwc->gadget_driver->disconnect(&dwc->gadget);
2265                 spin_lock(&dwc->lock);
2266         }
2267 }
2268
2269 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2270 {
2271         if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2272                 spin_unlock(&dwc->lock);
2273                 dwc->gadget_driver->suspend(&dwc->gadget);
2274                 spin_lock(&dwc->lock);
2275         }
2276 }
2277
2278 static void dwc3_resume_gadget(struct dwc3 *dwc)
2279 {
2280         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2281                 spin_unlock(&dwc->lock);
2282                 dwc->gadget_driver->resume(&dwc->gadget);
2283                 spin_lock(&dwc->lock);
2284         }
2285 }
2286
2287 static void dwc3_reset_gadget(struct dwc3 *dwc)
2288 {
2289         if (!dwc->gadget_driver)
2290                 return;
2291
2292         if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2293                 spin_unlock(&dwc->lock);
2294                 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2295                 spin_lock(&dwc->lock);
2296         }
2297 }
2298
2299 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2300 {
2301         struct dwc3_ep *dep;
2302         struct dwc3_gadget_ep_cmd_params params;
2303         u32 cmd;
2304         int ret;
2305
2306         dep = dwc->eps[epnum];
2307
2308         if (!dep->resource_index)
2309                 return;
2310
2311         /*
2312          * NOTICE: We are violating what the Databook says about the
2313          * EndTransfer command. Ideally we would _always_ wait for the
2314          * EndTransfer Command Completion IRQ, but that's causing too
2315          * much trouble synchronizing between us and gadget driver.
2316          *
2317          * We have discussed this with the IP Provider and it was
2318          * suggested to giveback all requests here, but give HW some
2319          * extra time to synchronize with the interconnect. We're using
2320          * an arbitrary 100us delay for that.
2321          *
2322          * Note also that a similar handling was tested by Synopsys
2323          * (thanks a lot Paul) and nothing bad has come out of it.
2324          * In short, what we're doing is:
2325          *
2326          * - Issue EndTransfer WITH CMDIOC bit set
2327          * - Wait 100us
2328          */
2329
2330         cmd = DWC3_DEPCMD_ENDTRANSFER;
2331         cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2332         cmd |= DWC3_DEPCMD_CMDIOC;
2333         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2334         memset(&params, 0, sizeof(params));
2335         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
2336         WARN_ON_ONCE(ret);
2337         dep->resource_index = 0;
2338         dep->flags &= ~DWC3_EP_BUSY;
2339         udelay(100);
2340 }
2341
2342 static void dwc3_stop_active_transfers(struct dwc3 *dwc)
2343 {
2344         u32 epnum;
2345
2346         for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2347                 struct dwc3_ep *dep;
2348
2349                 dep = dwc->eps[epnum];
2350                 if (!dep)
2351                         continue;
2352
2353                 if (!(dep->flags & DWC3_EP_ENABLED))
2354                         continue;
2355
2356                 dwc3_remove_requests(dwc, dep);
2357         }
2358 }
2359
2360 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2361 {
2362         u32 epnum;
2363
2364         for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2365                 struct dwc3_ep *dep;
2366                 int ret;
2367
2368                 dep = dwc->eps[epnum];
2369                 if (!dep)
2370                         continue;
2371
2372                 if (!(dep->flags & DWC3_EP_STALL))
2373                         continue;
2374
2375                 dep->flags &= ~DWC3_EP_STALL;
2376
2377                 ret = dwc3_send_clear_stall_ep_cmd(dep);
2378                 WARN_ON_ONCE(ret);
2379         }
2380 }
2381
2382 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2383 {
2384         int                     reg;
2385
2386         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2387         reg &= ~DWC3_DCTL_INITU1ENA;
2388         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2389
2390         reg &= ~DWC3_DCTL_INITU2ENA;
2391         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2392
2393         dwc3_disconnect_gadget(dwc);
2394
2395         dwc->gadget.speed = USB_SPEED_UNKNOWN;
2396         dwc->setup_packet_pending = false;
2397         usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2398
2399         dwc->connected = false;
2400 }
2401
2402 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2403 {
2404         u32                     reg;
2405
2406         dwc->connected = true;
2407
2408         /*
2409          * WORKAROUND: DWC3 revisions <1.88a have an issue which
2410          * would cause a missing Disconnect Event if there's a
2411          * pending Setup Packet in the FIFO.
2412          *
2413          * There's no suggested workaround on the official Bug
2414          * report, which states that "unless the driver/application
2415          * is doing any special handling of a disconnect event,
2416          * there is no functional issue".
2417          *
2418          * Unfortunately, it turns out that we _do_ some special
2419          * handling of a disconnect event, namely complete all
2420          * pending transfers, notify gadget driver of the
2421          * disconnection, and so on.
2422          *
2423          * Our suggested workaround is to follow the Disconnect
2424          * Event steps here, instead, based on a setup_packet_pending
2425          * flag. Such flag gets set whenever we have a SETUP_PENDING
2426          * status for EP0 TRBs and gets cleared on XferComplete for the
2427          * same endpoint.
2428          *
2429          * Refers to:
2430          *
2431          * STAR#9000466709: RTL: Device : Disconnect event not
2432          * generated if setup packet pending in FIFO
2433          */
2434         if (dwc->revision < DWC3_REVISION_188A) {
2435                 if (dwc->setup_packet_pending)
2436                         dwc3_gadget_disconnect_interrupt(dwc);
2437         }
2438
2439         dwc3_reset_gadget(dwc);
2440
2441         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2442         reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2443         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2444         dwc->test_mode = false;
2445
2446         dwc3_stop_active_transfers(dwc);
2447         dwc3_clear_stall_all_ep(dwc);
2448
2449         /* Reset device address to zero */
2450         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2451         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2452         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2453 }
2454
2455 static void dwc3_update_ram_clk_sel(struct dwc3 *dwc, u32 speed)
2456 {
2457         u32 reg;
2458         u32 usb30_clock = DWC3_GCTL_CLK_BUS;
2459
2460         /*
2461          * We change the clock only at SS but I dunno why I would want to do
2462          * this. Maybe it becomes part of the power saving plan.
2463          */
2464
2465         if (speed != DWC3_DSTS_SUPERSPEED)
2466                 return;
2467
2468         /*
2469          * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2470          * each time on Connect Done.
2471          */
2472         if (!usb30_clock)
2473                 return;
2474
2475         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
2476         reg |= DWC3_GCTL_RAMCLKSEL(usb30_clock);
2477         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
2478 }
2479
2480 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2481 {
2482         struct dwc3_ep          *dep;
2483         int                     ret;
2484         u32                     reg;
2485         u8                      speed;
2486
2487         reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2488         speed = reg & DWC3_DSTS_CONNECTSPD;
2489         dwc->speed = speed;
2490
2491         dwc3_update_ram_clk_sel(dwc, speed);
2492
2493         switch (speed) {
2494         case DWC3_DSTS_SUPERSPEED:
2495                 /*
2496                  * WORKAROUND: DWC3 revisions <1.90a have an issue which
2497                  * would cause a missing USB3 Reset event.
2498                  *
2499                  * In such situations, we should force a USB3 Reset
2500                  * event by calling our dwc3_gadget_reset_interrupt()
2501                  * routine.
2502                  *
2503                  * Refers to:
2504                  *
2505                  * STAR#9000483510: RTL: SS : USB3 reset event may
2506                  * not be generated always when the link enters poll
2507                  */
2508                 if (dwc->revision < DWC3_REVISION_190A)
2509                         dwc3_gadget_reset_interrupt(dwc);
2510
2511                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2512                 dwc->gadget.ep0->maxpacket = 512;
2513                 dwc->gadget.speed = USB_SPEED_SUPER;
2514                 break;
2515         case DWC3_DSTS_HIGHSPEED:
2516                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2517                 dwc->gadget.ep0->maxpacket = 64;
2518                 dwc->gadget.speed = USB_SPEED_HIGH;
2519                 break;
2520         case DWC3_DSTS_FULLSPEED2:
2521         case DWC3_DSTS_FULLSPEED1:
2522                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2523                 dwc->gadget.ep0->maxpacket = 64;
2524                 dwc->gadget.speed = USB_SPEED_FULL;
2525                 break;
2526         case DWC3_DSTS_LOWSPEED:
2527                 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2528                 dwc->gadget.ep0->maxpacket = 8;
2529                 dwc->gadget.speed = USB_SPEED_LOW;
2530                 break;
2531         }
2532
2533         /* Enable USB2 LPM Capability */
2534
2535         if ((dwc->revision > DWC3_REVISION_194A) &&
2536             (speed != DWC3_DSTS_SUPERSPEED)) {
2537                 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2538                 reg |= DWC3_DCFG_LPM_CAP;
2539                 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2540
2541                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2542                 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2543
2544                 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2545
2546                 /*
2547                  * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2548                  * DCFG.LPMCap is set, core responses with an ACK and the
2549                  * BESL value in the LPM token is less than or equal to LPM
2550                  * NYET threshold.
2551                  */
2552                 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2553                                 && dwc->has_lpm_erratum,
2554                                 "LPM Erratum not available on dwc3 revisisions < 2.40a\n");
2555
2556                 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2557                         reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2558
2559                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2560         } else {
2561                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2562                 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2563                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2564         }
2565
2566         dep = dwc->eps[0];
2567         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2568                         false);
2569         if (ret) {
2570                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2571                 return;
2572         }
2573
2574         dep = dwc->eps[1];
2575         ret = __dwc3_gadget_ep_enable(dep, &dwc3_gadget_ep0_desc, NULL, true,
2576                         false);
2577         if (ret) {
2578                 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2579                 return;
2580         }
2581
2582         /*
2583          * Configure PHY via GUSB3PIPECTLn if required.
2584          *
2585          * Update GTXFIFOSIZn
2586          *
2587          * In both cases reset values should be sufficient.
2588          */
2589 }
2590
2591 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2592 {
2593         /*
2594          * TODO take core out of low power mode when that's
2595          * implemented.
2596          */
2597
2598         if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2599                 spin_unlock(&dwc->lock);
2600                 dwc->gadget_driver->resume(&dwc->gadget);
2601                 spin_lock(&dwc->lock);
2602         }
2603 }
2604
2605 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2606                 unsigned int evtinfo)
2607 {
2608         enum dwc3_link_state    next = evtinfo & DWC3_LINK_STATE_MASK;
2609         unsigned int            pwropt;
2610
2611         /*
2612          * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2613          * Hibernation mode enabled which would show up when device detects
2614          * host-initiated U3 exit.
2615          *
2616          * In that case, device will generate a Link State Change Interrupt
2617          * from U3 to RESUME which is only necessary if Hibernation is
2618          * configured in.
2619          *
2620          * There are no functional changes due to such spurious event and we
2621          * just need to ignore it.
2622          *
2623          * Refers to:
2624          *
2625          * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2626          * operational mode
2627          */
2628         pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2629         if ((dwc->revision < DWC3_REVISION_250A) &&
2630                         (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2631                 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2632                                 (next == DWC3_LINK_STATE_RESUME)) {
2633                         dwc3_trace(trace_dwc3_gadget,
2634                                         "ignoring transition U3 -> Resume");
2635                         return;
2636                 }
2637         }
2638
2639         /*
2640          * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2641          * on the link partner, the USB session might do multiple entry/exit
2642          * of low power states before a transfer takes place.
2643          *
2644          * Due to this problem, we might experience lower throughput. The
2645          * suggested workaround is to disable DCTL[12:9] bits if we're
2646          * transitioning from U1/U2 to U0 and enable those bits again
2647          * after a transfer completes and there are no pending transfers
2648          * on any of the enabled endpoints.
2649          *
2650          * This is the first half of that workaround.
2651          *
2652          * Refers to:
2653          *
2654          * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2655          * core send LGO_Ux entering U0
2656          */
2657         if (dwc->revision < DWC3_REVISION_183A) {
2658                 if (next == DWC3_LINK_STATE_U0) {
2659                         u32     u1u2;
2660                         u32     reg;
2661
2662                         switch (dwc->link_state) {
2663                         case DWC3_LINK_STATE_U1:
2664                         case DWC3_LINK_STATE_U2:
2665                                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2666                                 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2667                                                 | DWC3_DCTL_ACCEPTU2ENA
2668                                                 | DWC3_DCTL_INITU1ENA
2669                                                 | DWC3_DCTL_ACCEPTU1ENA);
2670
2671                                 if (!dwc->u1u2)
2672                                         dwc->u1u2 = reg & u1u2;
2673
2674                                 reg &= ~u1u2;
2675
2676                                 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2677                                 break;
2678                         default:
2679                                 /* do nothing */
2680                                 break;
2681                         }
2682                 }
2683         }
2684
2685         switch (next) {
2686         case DWC3_LINK_STATE_U1:
2687                 if (dwc->speed == USB_SPEED_SUPER)
2688                         dwc3_suspend_gadget(dwc);
2689                 break;
2690         case DWC3_LINK_STATE_U2:
2691         case DWC3_LINK_STATE_U3:
2692                 dwc3_suspend_gadget(dwc);
2693                 break;
2694         case DWC3_LINK_STATE_RESUME:
2695                 dwc3_resume_gadget(dwc);
2696                 break;
2697         default:
2698                 /* do nothing */
2699                 break;
2700         }
2701
2702         dwc->link_state = next;
2703 }
2704
2705 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
2706                 unsigned int evtinfo)
2707 {
2708         unsigned int is_ss = evtinfo & BIT(4);
2709
2710         /**
2711          * WORKAROUND: DWC3 revison 2.20a with hibernation support
2712          * have a known issue which can cause USB CV TD.9.23 to fail
2713          * randomly.
2714          *
2715          * Because of this issue, core could generate bogus hibernation
2716          * events which SW needs to ignore.
2717          *
2718          * Refers to:
2719          *
2720          * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
2721          * Device Fallback from SuperSpeed
2722          */
2723         if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
2724                 return;
2725
2726         /* enter hibernation here */
2727 }
2728
2729 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
2730                 const struct dwc3_event_devt *event)
2731 {
2732         switch (event->type) {
2733         case DWC3_DEVICE_EVENT_DISCONNECT:
2734                 dwc3_gadget_disconnect_interrupt(dwc);
2735                 break;
2736         case DWC3_DEVICE_EVENT_RESET:
2737                 dwc3_gadget_reset_interrupt(dwc);
2738                 break;
2739         case DWC3_DEVICE_EVENT_CONNECT_DONE:
2740                 dwc3_gadget_conndone_interrupt(dwc);
2741                 break;
2742         case DWC3_DEVICE_EVENT_WAKEUP:
2743                 dwc3_gadget_wakeup_interrupt(dwc);
2744                 break;
2745         case DWC3_DEVICE_EVENT_HIBER_REQ:
2746                 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
2747                                         "unexpected hibernation event\n"))
2748                         break;
2749
2750                 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
2751                 break;
2752         case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
2753                 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
2754                 break;
2755         case DWC3_DEVICE_EVENT_EOPF:
2756                 dwc3_trace(trace_dwc3_gadget, "End of Periodic Frame");
2757                 break;
2758         case DWC3_DEVICE_EVENT_SOF:
2759                 dwc3_trace(trace_dwc3_gadget, "Start of Periodic Frame");
2760                 break;
2761         case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
2762                 dwc3_trace(trace_dwc3_gadget, "Erratic Error");
2763                 break;
2764         case DWC3_DEVICE_EVENT_CMD_CMPL:
2765                 dwc3_trace(trace_dwc3_gadget, "Command Complete");
2766                 break;
2767         case DWC3_DEVICE_EVENT_OVERFLOW:
2768                 dwc3_trace(trace_dwc3_gadget, "Overflow");
2769                 break;
2770         default:
2771                 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
2772         }
2773 }
2774
2775 static void dwc3_process_event_entry(struct dwc3 *dwc,
2776                 const union dwc3_event *event)
2777 {
2778         trace_dwc3_event(event->raw);
2779
2780         /* Endpoint IRQ, handle it and return early */
2781         if (event->type.is_devspec == 0) {
2782                 /* depevt */
2783                 return dwc3_endpoint_interrupt(dwc, &event->depevt);
2784         }
2785
2786         switch (event->type.type) {
2787         case DWC3_EVENT_TYPE_DEV:
2788                 dwc3_gadget_interrupt(dwc, &event->devt);
2789                 break;
2790         /* REVISIT what to do with Carkit and I2C events ? */
2791         default:
2792                 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
2793         }
2794 }
2795
2796 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
2797 {
2798         struct dwc3 *dwc = evt->dwc;
2799         irqreturn_t ret = IRQ_NONE;
2800         int left;
2801         u32 reg;
2802
2803         left = evt->count;
2804
2805         if (!(evt->flags & DWC3_EVENT_PENDING))
2806                 return IRQ_NONE;
2807
2808         while (left > 0) {
2809                 union dwc3_event event;
2810
2811                 event.raw = *(u32 *) (evt->buf + evt->lpos);
2812
2813                 dwc3_process_event_entry(dwc, &event);
2814
2815                 /*
2816                  * FIXME we wrap around correctly to the next entry as
2817                  * almost all entries are 4 bytes in size. There is one
2818                  * entry which has 12 bytes which is a regular entry
2819                  * followed by 8 bytes data. ATM I don't know how
2820                  * things are organized if we get next to the a
2821                  * boundary so I worry about that once we try to handle
2822                  * that.
2823                  */
2824                 evt->lpos = (evt->lpos + 4) % DWC3_EVENT_BUFFERS_SIZE;
2825                 left -= 4;
2826
2827                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 4);
2828         }
2829
2830         evt->count = 0;
2831         evt->flags &= ~DWC3_EVENT_PENDING;
2832         ret = IRQ_HANDLED;
2833
2834         /* Unmask interrupt */
2835         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2836         reg &= ~DWC3_GEVNTSIZ_INTMASK;
2837         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2838
2839         return ret;
2840 }
2841
2842 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
2843 {
2844         struct dwc3_event_buffer *evt = _evt;
2845         struct dwc3 *dwc = evt->dwc;
2846         unsigned long flags;
2847         irqreturn_t ret = IRQ_NONE;
2848
2849         spin_lock_irqsave(&dwc->lock, flags);
2850         ret = dwc3_process_event_buf(evt);
2851         spin_unlock_irqrestore(&dwc->lock, flags);
2852
2853         return ret;
2854 }
2855
2856 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
2857 {
2858         struct dwc3 *dwc = evt->dwc;
2859         u32 count;
2860         u32 reg;
2861
2862         if (pm_runtime_suspended(dwc->dev)) {
2863                 pm_runtime_get(dwc->dev);
2864                 disable_irq_nosync(dwc->irq_gadget);
2865                 dwc->pending_events = true;
2866                 return IRQ_HANDLED;
2867         }
2868
2869         count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
2870         count &= DWC3_GEVNTCOUNT_MASK;
2871         if (!count)
2872                 return IRQ_NONE;
2873
2874         evt->count = count;
2875         evt->flags |= DWC3_EVENT_PENDING;
2876
2877         /* Mask interrupt */
2878         reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
2879         reg |= DWC3_GEVNTSIZ_INTMASK;
2880         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
2881
2882         return IRQ_WAKE_THREAD;
2883 }
2884
2885 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
2886 {
2887         struct dwc3_event_buffer        *evt = _evt;
2888
2889         return dwc3_check_event_buf(evt);
2890 }
2891
2892 /**
2893  * dwc3_gadget_init - Initializes gadget related registers
2894  * @dwc: pointer to our controller context structure
2895  *
2896  * Returns 0 on success otherwise negative errno.
2897  */
2898 int dwc3_gadget_init(struct dwc3 *dwc)
2899 {
2900         int                                     ret;
2901
2902         dwc->ctrl_req = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
2903                         &dwc->ctrl_req_addr, GFP_KERNEL);
2904         if (!dwc->ctrl_req) {
2905                 dev_err(dwc->dev, "failed to allocate ctrl request\n");
2906                 ret = -ENOMEM;
2907                 goto err0;
2908         }
2909
2910         dwc->ep0_trb = dma_alloc_coherent(dwc->dev, sizeof(*dwc->ep0_trb) * 2,
2911                         &dwc->ep0_trb_addr, GFP_KERNEL);
2912         if (!dwc->ep0_trb) {
2913                 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
2914                 ret = -ENOMEM;
2915                 goto err1;
2916         }
2917
2918         dwc->setup_buf = kzalloc(DWC3_EP0_BOUNCE_SIZE, GFP_KERNEL);
2919         if (!dwc->setup_buf) {
2920                 ret = -ENOMEM;
2921                 goto err2;
2922         }
2923
2924         dwc->ep0_bounce = dma_alloc_coherent(dwc->dev,
2925                         DWC3_EP0_BOUNCE_SIZE, &dwc->ep0_bounce_addr,
2926                         GFP_KERNEL);
2927         if (!dwc->ep0_bounce) {
2928                 dev_err(dwc->dev, "failed to allocate ep0 bounce buffer\n");
2929                 ret = -ENOMEM;
2930                 goto err3;
2931         }
2932
2933         dwc->zlp_buf = kzalloc(DWC3_ZLP_BUF_SIZE, GFP_KERNEL);
2934         if (!dwc->zlp_buf) {
2935                 ret = -ENOMEM;
2936                 goto err4;
2937         }
2938
2939         dwc->gadget.ops                 = &dwc3_gadget_ops;
2940         dwc->gadget.speed               = USB_SPEED_UNKNOWN;
2941         dwc->gadget.sg_supported        = true;
2942         dwc->gadget.name                = "dwc3-gadget";
2943         dwc->gadget.is_otg              = dwc->dr_mode == USB_DR_MODE_OTG;
2944
2945         /*
2946          * FIXME We might be setting max_speed to <SUPER, however versions
2947          * <2.20a of dwc3 have an issue with metastability (documented
2948          * elsewhere in this driver) which tells us we can't set max speed to
2949          * anything lower than SUPER.
2950          *
2951          * Because gadget.max_speed is only used by composite.c and function
2952          * drivers (i.e. it won't go into dwc3's registers) we are allowing this
2953          * to happen so we avoid sending SuperSpeed Capability descriptor
2954          * together with our BOS descriptor as that could confuse host into
2955          * thinking we can handle super speed.
2956          *
2957          * Note that, in fact, we won't even support GetBOS requests when speed
2958          * is less than super speed because we don't have means, yet, to tell
2959          * composite.c that we are USB 2.0 + LPM ECN.
2960          */
2961         if (dwc->revision < DWC3_REVISION_220A)
2962                 dwc3_trace(trace_dwc3_gadget,
2963                                 "Changing max_speed on rev %08x",
2964                                 dwc->revision);
2965
2966         dwc->gadget.max_speed           = dwc->maximum_speed;
2967
2968         /*
2969          * Per databook, DWC3 needs buffer size to be aligned to MaxPacketSize
2970          * on ep out.
2971          */
2972         dwc->gadget.quirk_ep_out_aligned_size = true;
2973
2974         /*
2975          * REVISIT: Here we should clear all pending IRQs to be
2976          * sure we're starting from a well known location.
2977          */
2978
2979         ret = dwc3_gadget_init_endpoints(dwc);
2980         if (ret)
2981                 goto err5;
2982
2983         ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
2984         if (ret) {
2985                 dev_err(dwc->dev, "failed to register udc\n");
2986                 goto err5;
2987         }
2988
2989         return 0;
2990
2991 err5:
2992         kfree(dwc->zlp_buf);
2993
2994 err4:
2995         dwc3_gadget_free_endpoints(dwc);
2996         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
2997                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
2998
2999 err3:
3000         kfree(dwc->setup_buf);
3001
3002 err2:
3003         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3004                         dwc->ep0_trb, dwc->ep0_trb_addr);
3005
3006 err1:
3007         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3008                         dwc->ctrl_req, dwc->ctrl_req_addr);
3009
3010 err0:
3011         return ret;
3012 }
3013
3014 /* -------------------------------------------------------------------------- */
3015
3016 void dwc3_gadget_exit(struct dwc3 *dwc)
3017 {
3018         usb_del_gadget_udc(&dwc->gadget);
3019
3020         dwc3_gadget_free_endpoints(dwc);
3021
3022         dma_free_coherent(dwc->dev, DWC3_EP0_BOUNCE_SIZE,
3023                         dwc->ep0_bounce, dwc->ep0_bounce_addr);
3024
3025         kfree(dwc->setup_buf);
3026         kfree(dwc->zlp_buf);
3027
3028         dma_free_coherent(dwc->dev, sizeof(*dwc->ep0_trb),
3029                         dwc->ep0_trb, dwc->ep0_trb_addr);
3030
3031         dma_free_coherent(dwc->dev, sizeof(*dwc->ctrl_req),
3032                         dwc->ctrl_req, dwc->ctrl_req_addr);
3033 }
3034
3035 int dwc3_gadget_suspend(struct dwc3 *dwc)
3036 {
3037         int ret;
3038
3039         if (!dwc->gadget_driver)
3040                 return 0;
3041
3042         ret = dwc3_gadget_run_stop(dwc, false, false);
3043         if (ret < 0)
3044                 return ret;
3045
3046         dwc3_disconnect_gadget(dwc);
3047         __dwc3_gadget_stop(dwc);
3048
3049         return 0;
3050 }
3051
3052 int dwc3_gadget_resume(struct dwc3 *dwc)
3053 {
3054         int                     ret;
3055
3056         if (!dwc->gadget_driver)
3057                 return 0;
3058
3059         ret = __dwc3_gadget_start(dwc);
3060         if (ret < 0)
3061                 goto err0;
3062
3063         ret = dwc3_gadget_run_stop(dwc, true, false);
3064         if (ret < 0)
3065                 goto err1;
3066
3067         return 0;
3068
3069 err1:
3070         __dwc3_gadget_stop(dwc);
3071
3072 err0:
3073         return ret;
3074 }
3075
3076 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3077 {
3078         if (dwc->pending_events) {
3079                 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3080                 dwc->pending_events = false;
3081                 enable_irq(dwc->irq_gadget);
3082         }
3083 }