drivers/usb/dwc3/ep0.c

   1 /**
   2  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/slab.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/list.h>
  27 #include <linux/dma-mapping.h>
  28
  29 #include <linux/usb/ch9.h>
  30 #include <linux/usb/gadget.h>
  31 #include <linux/usb/composite.h>
  32
  33 #include "core.h"
  34 #include "debug.h"
  35 #include "gadget.h"
  36 #include "io.h"
  37
  38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  40                 struct dwc3_ep *dep, struct dwc3_request *req);
  41
  42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
  43 {
  44         switch (state) {
  45         case EP0_UNCONNECTED:
  46                 return "Unconnected";
  47         case EP0_SETUP_PHASE:
  48                 return "Setup Phase";
  49         case EP0_DATA_PHASE:
  50                 return "Data Phase";
  51         case EP0_STATUS_PHASE:
  52                 return "Status Phase";
  53         default:
  54                 return "UNKNOWN";
  55         }
  56 }
  57
  58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
  59                 u32 len, u32 type, bool chain)
  60 {
  61         struct dwc3_gadget_ep_cmd_params params;
  62         struct dwc3_trb                 *trb;
  63         struct dwc3_ep                  *dep;
  64
  65         int                             ret;
  66
  67         dep = dwc->eps[epnum];
  68         if (dep->flags & DWC3_EP_BUSY) {
  69                 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
  70                 return 0;
  71         }
  72
  73         trb = &dwc->ep0_trb[dep->trb_enqueue];
  74
  75         if (chain)
  76                 dep->trb_enqueue++;
  77
  78         trb->bpl = lower_32_bits(buf_dma);
  79         trb->bph = upper_32_bits(buf_dma);
  80         trb->size = len;
  81         trb->ctrl = type;
  82
  83         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  84                         | DWC3_TRB_CTRL_ISP_IMI);
  85
  86         if (chain)
  87                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  88         else
  89                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  90                                 | DWC3_TRB_CTRL_LST);
  91
  92         if (chain)
  93                 return 0;
  94
  95         memset(&params, 0, sizeof(params));
  96         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  97         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  98
  99         trace_dwc3_prepare_trb(dep, trb);
 100
 101         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
 102         if (ret < 0) {
 103                 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
 104                                 dep->name);
 105                 return ret;
 106         }
 107
 108         dep->flags |= DWC3_EP_BUSY;
 109         dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
 110         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 111
 112         return 0;
 113 }
 114
 115 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
 116                 struct dwc3_request *req)
 117 {
 118         struct dwc3             *dwc = dep->dwc;
 119
 120         req->request.actual     = 0;
 121         req->request.status     = -EINPROGRESS;
 122         req->epnum              = dep->number;
 123
 124         list_add_tail(&req->list, &dep->pending_list);
 125
 126         /*
 127          * Gadget driver might not be quick enough to queue a request
 128          * before we get a Transfer Not Ready event on this endpoint.
 129          *
 130          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 131          * flag is set, it's telling us that as soon as Gadget queues the
 132          * required request, we should kick the transfer here because the
 133          * IRQ we were waiting for is long gone.
 134          */
 135         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 136                 unsigned        direction;
 137
 138                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 139
 140                 if (dwc->ep0state != EP0_DATA_PHASE) {
 141                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 142                         return 0;
 143                 }
 144
 145                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 146
 147                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 148                                 DWC3_EP0_DIR_IN);
 149
 150                 return 0;
 151         }
 152
 153         /*
 154          * In case gadget driver asked us to delay the STATUS phase,
 155          * handle it here.
 156          */
 157         if (dwc->delayed_status) {
 158                 unsigned        direction;
 159
 160                 direction = !dwc->ep0_expect_in;
 161                 dwc->delayed_status = false;
 162                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 163
 164                 if (dwc->ep0state == EP0_STATUS_PHASE)
 165                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 166                 else
 167                         dwc3_trace(trace_dwc3_ep0,
 168                                         "too early for delayed status");
 169
 170                 return 0;
 171         }
 172
 173         /*
 174          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 175          *
 176          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 177          * come before issueing Start Transfer command, but if we do, we will
 178          * miss situations where the host starts another SETUP phase instead of
 179          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 180          * Layer Compliance Suite.
 181          *
 182          * The problem surfaces due to the fact that in case of back-to-back
 183          * SETUP packets there will be no XferNotReady(DATA) generated and we
 184          * will be stuck waiting for XferNotReady(DATA) forever.
 185          *
 186          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 187          * it tells us to start Data Phase right away. It also mentions that if
 188          * we receive a SETUP phase instead of the DATA phase, core will issue
 189          * XferComplete for the DATA phase, before actually initiating it in
 190          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 191          * can only be used to print some debugging logs, as the core expects
 192          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 193          * just so it completes right away, without transferring anything and,
 194          * only then, we can go back to the SETUP phase.
 195          *
 196          * Because of this scenario, SNPS decided to change the programming
 197          * model of control transfers and support on-demand transfers only for
 198          * the STATUS phase. To fix the issue we have now, we will always wait
 199          * for gadget driver to queue the DATA phase's struct usb_request, then
 200          * start it right away.
 201          *
 202          * If we're actually in a 2-stage transfer, we will wait for
 203          * XferNotReady(STATUS).
 204          */
 205         if (dwc->three_stage_setup) {
 206                 unsigned        direction;
 207
 208                 direction = dwc->ep0_expect_in;
 209                 dwc->ep0state = EP0_DATA_PHASE;
 210
 211                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 212
 213                 dep->flags &= ~DWC3_EP0_DIR_IN;
 214         }
 215
 216         return 0;
 217 }
 218
 219 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 220                 gfp_t gfp_flags)
 221 {
 222         struct dwc3_request             *req = to_dwc3_request(request);
 223         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 224         struct dwc3                     *dwc = dep->dwc;
 225
 226         unsigned long                   flags;
 227
 228         int                             ret;
 229
 230         spin_lock_irqsave(&dwc->lock, flags);
 231         if (!dep->endpoint.desc) {
 232                 dwc3_trace(trace_dwc3_ep0,
 233                                 "trying to queue request %p to disabled %s",
 234                                 request, dep->name);
 235                 ret = -ESHUTDOWN;
 236                 goto out;
 237         }
 238
 239         /* we share one TRB for ep0/1 */
 240         if (!list_empty(&dep->pending_list)) {
 241                 ret = -EBUSY;
 242                 goto out;
 243         }
 244
 245         dwc3_trace(trace_dwc3_ep0,
 246                         "queueing request %p to %s length %d state '%s'",
 247                         request, dep->name, request->length,
 248                         dwc3_ep0_state_string(dwc->ep0state));
 249
 250         ret = __dwc3_gadget_ep0_queue(dep, req);
 251
 252 out:
 253         spin_unlock_irqrestore(&dwc->lock, flags);
 254
 255         return ret;
 256 }
 257
 258 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 259 {
 260         struct dwc3_ep          *dep;
 261
 262         /* reinitialize physical ep1 */
 263         dep = dwc->eps[1];
 264         dep->flags = DWC3_EP_ENABLED;
 265
 266         /* stall is always issued on EP0 */
 267         dep = dwc->eps[0];
 268         __dwc3_gadget_ep_set_halt(dep, 1, false);
 269         dep->flags = DWC3_EP_ENABLED;
 270         dwc->delayed_status = false;
 271
 272         if (!list_empty(&dep->pending_list)) {
 273                 struct dwc3_request     *req;
 274
 275                 req = next_request(&dep->pending_list);
 276                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 277         }
 278
 279         dwc->ep0state = EP0_SETUP_PHASE;
 280         dwc3_ep0_out_start(dwc);
 281 }
 282
 283 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 284 {
 285         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 286         struct dwc3                     *dwc = dep->dwc;
 287
 288         dwc3_ep0_stall_and_restart(dwc);
 289
 290         return 0;
 291 }
 292
 293 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 294 {
 295         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 296         struct dwc3                     *dwc = dep->dwc;
 297         unsigned long                   flags;
 298         int                             ret;
 299
 300         spin_lock_irqsave(&dwc->lock, flags);
 301         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 302         spin_unlock_irqrestore(&dwc->lock, flags);
 303
 304         return ret;
 305 }
 306
 307 void dwc3_ep0_out_start(struct dwc3 *dwc)
 308 {
 309         int                             ret;
 310
 311         ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
 312                         DWC3_TRBCTL_CONTROL_SETUP, false);
 313         WARN_ON(ret < 0);
 314 }
 315
 316 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 317 {
 318         struct dwc3_ep          *dep;
 319         u32                     windex = le16_to_cpu(wIndex_le);
 320         u32                     epnum;
 321
 322         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 323         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 324                 epnum |= 1;
 325
 326         dep = dwc->eps[epnum];
 327         if (dep->flags & DWC3_EP_ENABLED)
 328                 return dep;
 329
 330         return NULL;
 331 }
 332
 333 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 334 {
 335 }
 336 /*
 337  * ch 9.4.5
 338  */
 339 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 340                 struct usb_ctrlrequest *ctrl)
 341 {
 342         struct dwc3_ep          *dep;
 343         u32                     recip;
 344         u32                     reg;
 345         u16                     usb_status = 0;
 346         __le16                  *response_pkt;
 347
 348         recip = ctrl->bRequestType & USB_RECIP_MASK;
 349         switch (recip) {
 350         case USB_RECIP_DEVICE:
 351                 /*
 352                  * LTM will be set once we know how to set this in HW.
 353                  */
 354                 usb_status |= dwc->gadget.is_selfpowered;
 355
 356                 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
 357                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 358                         if (reg & DWC3_DCTL_INITU1ENA)
 359                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 360                         if (reg & DWC3_DCTL_INITU2ENA)
 361                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 362                 }
 363
 364                 break;
 365
 366         case USB_RECIP_INTERFACE:
 367                 /*
 368                  * Function Remote Wake Capable D0
 369                  * Function Remote Wakeup       D1
 370                  */
 371                 break;
 372
 373         case USB_RECIP_ENDPOINT:
 374                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 375                 if (!dep)
 376                         return -EINVAL;
 377
 378                 if (dep->flags & DWC3_EP_STALL)
 379                         usb_status = 1 << USB_ENDPOINT_HALT;
 380                 break;
 381         default:
 382                 return -EINVAL;
 383         }
 384
 385         response_pkt = (__le16 *) dwc->setup_buf;
 386         *response_pkt = cpu_to_le16(usb_status);
 387
 388         dep = dwc->eps[0];
 389         dwc->ep0_usb_req.dep = dep;
 390         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 391         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 392         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 393
 394         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 395 }
 396
 397 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 398                 struct usb_ctrlrequest *ctrl, int set)
 399 {
 400         struct dwc3_ep          *dep;
 401         u32                     recip;
 402         u32                     wValue;
 403         u32                     wIndex;
 404         u32                     reg;
 405         int                     ret;
 406         enum usb_device_state   state;
 407
 408         wValue = le16_to_cpu(ctrl->wValue);
 409         wIndex = le16_to_cpu(ctrl->wIndex);
 410         recip = ctrl->bRequestType & USB_RECIP_MASK;
 411         state = dwc->gadget.state;
 412
 413         switch (recip) {
 414         case USB_RECIP_DEVICE:
 415
 416                 switch (wValue) {
 417                 case USB_DEVICE_REMOTE_WAKEUP:
 418                         break;
 419                 /*
 420                  * 9.4.1 says only only for SS, in AddressState only for
 421                  * default control pipe
 422                  */
 423                 case USB_DEVICE_U1_ENABLE:
 424                         if (state != USB_STATE_CONFIGURED)
 425                                 return -EINVAL;
 426                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 427                                 return -EINVAL;
 428
 429                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 430                         if (set)
 431                                 reg |= DWC3_DCTL_INITU1ENA;
 432                         else
 433                                 reg &= ~DWC3_DCTL_INITU1ENA;
 434                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 435                         break;
 436
 437                 case USB_DEVICE_U2_ENABLE:
 438                         if (state != USB_STATE_CONFIGURED)
 439                                 return -EINVAL;
 440                         if (dwc->speed != DWC3_DSTS_SUPERSPEED)
 441                                 return -EINVAL;
 442
 443                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 444                         if (set)
 445                                 reg |= DWC3_DCTL_INITU2ENA;
 446                         else
 447                                 reg &= ~DWC3_DCTL_INITU2ENA;
 448                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 449                         break;
 450
 451                 case USB_DEVICE_LTM_ENABLE:
 452                         return -EINVAL;
 453
 454                 case USB_DEVICE_TEST_MODE:
 455                         if ((wIndex & 0xff) != 0)
 456                                 return -EINVAL;
 457                         if (!set)
 458                                 return -EINVAL;
 459
 460                         switch (wIndex >> 8) {
 461                         case TEST_J:
 462                         case TEST_K:
 463                         case TEST_SE0_NAK:
 464                         case TEST_PACKET:
 465                         case TEST_FORCE_EN:
 466                                 dwc->test_mode_nr = wIndex >> 8;
 467                                 dwc->test_mode = true;
 468                                 break;
 469                         default:
 470                                 return -EINVAL;
 471                         }
 472                         break;
 473                 default:
 474                         return -EINVAL;
 475                 }
 476                 break;
 477
 478         case USB_RECIP_INTERFACE:
 479                 switch (wValue) {
 480                 case USB_INTRF_FUNC_SUSPEND:
 481                         if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
 482                                 /* XXX enable Low power suspend */
 483                                 ;
 484                         if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
 485                                 /* XXX enable remote wakeup */
 486                                 ;
 487                         break;
 488                 default:
 489                         return -EINVAL;
 490                 }
 491                 break;
 492
 493         case USB_RECIP_ENDPOINT:
 494                 switch (wValue) {
 495                 case USB_ENDPOINT_HALT:
 496                         dep = dwc3_wIndex_to_dep(dwc, wIndex);
 497                         if (!dep)
 498                                 return -EINVAL;
 499                         if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 500                                 break;
 501                         ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 502                         if (ret)
 503                                 return -EINVAL;
 504                         break;
 505                 default:
 506                         return -EINVAL;
 507                 }
 508                 break;
 509
 510         default:
 511                 return -EINVAL;
 512         }
 513
 514         return 0;
 515 }
 516
 517 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 518 {
 519         enum usb_device_state state = dwc->gadget.state;
 520         u32 addr;
 521         u32 reg;
 522
 523         addr = le16_to_cpu(ctrl->wValue);
 524         if (addr > 127) {
 525                 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
 526                 return -EINVAL;
 527         }
 528
 529         if (state == USB_STATE_CONFIGURED) {
 530                 dwc3_trace(trace_dwc3_ep0,
 531                                 "trying to set address when configured");
 532                 return -EINVAL;
 533         }
 534
 535         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 536         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 537         reg |= DWC3_DCFG_DEVADDR(addr);
 538         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 539
 540         if (addr)
 541                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 542         else
 543                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 544
 545         return 0;
 546 }
 547
 548 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 549 {
 550         int ret;
 551
 552         spin_unlock(&dwc->lock);
 553         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 554         spin_lock(&dwc->lock);
 555         return ret;
 556 }
 557
 558 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 559 {
 560         enum usb_device_state state = dwc->gadget.state;
 561         u32 cfg;
 562         int ret;
 563         u32 reg;
 564
 565         cfg = le16_to_cpu(ctrl->wValue);
 566
 567         switch (state) {
 568         case USB_STATE_DEFAULT:
 569                 return -EINVAL;
 570
 571         case USB_STATE_ADDRESS:
 572                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 573                 /* if the cfg matches and the cfg is non zero */
 574                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 575
 576                         /*
 577                          * only change state if set_config has already
 578                          * been processed. If gadget driver returns
 579                          * USB_GADGET_DELAYED_STATUS, we will wait
 580                          * to change the state on the next usb_ep_queue()
 581                          */
 582                         if (ret == 0)
 583                                 usb_gadget_set_state(&dwc->gadget,
 584                                                 USB_STATE_CONFIGURED);
 585
 586                         /*
 587                          * Enable transition to U1/U2 state when
 588                          * nothing is pending from application.
 589                          */
 590                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 591                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 592                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 593                 }
 594                 break;
 595
 596         case USB_STATE_CONFIGURED:
 597                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 598                 if (!cfg && !ret)
 599                         usb_gadget_set_state(&dwc->gadget,
 600                                         USB_STATE_ADDRESS);
 601                 break;
 602         default:
 603                 ret = -EINVAL;
 604         }
 605         return ret;
 606 }
 607
 608 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 609 {
 610         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 611         struct dwc3     *dwc = dep->dwc;
 612
 613         u32             param = 0;
 614         u32             reg;
 615
 616         struct timing {
 617                 u8      u1sel;
 618                 u8      u1pel;
 619                 u16     u2sel;
 620                 u16     u2pel;
 621         } __packed timing;
 622
 623         int             ret;
 624
 625         memcpy(&timing, req->buf, sizeof(timing));
 626
 627         dwc->u1sel = timing.u1sel;
 628         dwc->u1pel = timing.u1pel;
 629         dwc->u2sel = le16_to_cpu(timing.u2sel);
 630         dwc->u2pel = le16_to_cpu(timing.u2pel);
 631
 632         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 633         if (reg & DWC3_DCTL_INITU2ENA)
 634                 param = dwc->u2pel;
 635         if (reg & DWC3_DCTL_INITU1ENA)
 636                 param = dwc->u1pel;
 637
 638         /*
 639          * According to Synopsys Databook, if parameter is
 640          * greater than 125, a value of zero should be
 641          * programmed in the register.
 642          */
 643         if (param > 125)
 644                 param = 0;
 645
 646         /* now that we have the time, issue DGCMD Set Sel */
 647         ret = dwc3_send_gadget_generic_command(dwc,
 648                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 649         WARN_ON(ret < 0);
 650 }
 651
 652 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 653 {
 654         struct dwc3_ep  *dep;
 655         enum usb_device_state state = dwc->gadget.state;
 656         u16             wLength;
 657         u16             wValue;
 658
 659         if (state == USB_STATE_DEFAULT)
 660                 return -EINVAL;
 661
 662         wValue = le16_to_cpu(ctrl->wValue);
 663         wLength = le16_to_cpu(ctrl->wLength);
 664
 665         if (wLength != 6) {
 666                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 667                                 wLength);
 668                 return -EINVAL;
 669         }
 670
 671         /*
 672          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 673          * queue a usb_request for 6 bytes.
 674          *
 675          * Remember, though, this controller can't handle non-wMaxPacketSize
 676          * aligned transfers on the OUT direction, so we queue a request for
 677          * wMaxPacketSize instead.
 678          */
 679         dep = dwc->eps[0];
 680         dwc->ep0_usb_req.dep = dep;
 681         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 682         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 683         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 684
 685         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 686 }
 687
 688 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 689 {
 690         u16             wLength;
 691         u16             wValue;
 692         u16             wIndex;
 693
 694         wValue = le16_to_cpu(ctrl->wValue);
 695         wLength = le16_to_cpu(ctrl->wLength);
 696         wIndex = le16_to_cpu(ctrl->wIndex);
 697
 698         if (wIndex || wLength)
 699                 return -EINVAL;
 700
 701         /*
 702          * REVISIT It's unclear from Databook what to do with this
 703          * value. For now, just cache it.
 704          */
 705         dwc->isoch_delay = wValue;
 706
 707         return 0;
 708 }
 709
 710 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 711 {
 712         int ret;
 713
 714         switch (ctrl->bRequest) {
 715         case USB_REQ_GET_STATUS:
 716                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS");
 717                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 718                 break;
 719         case USB_REQ_CLEAR_FEATURE:
 720                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE");
 721                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 722                 break;
 723         case USB_REQ_SET_FEATURE:
 724                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE");
 725                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 726                 break;
 727         case USB_REQ_SET_ADDRESS:
 728                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS");
 729                 ret = dwc3_ep0_set_address(dwc, ctrl);
 730                 break;
 731         case USB_REQ_SET_CONFIGURATION:
 732                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION");
 733                 ret = dwc3_ep0_set_config(dwc, ctrl);
 734                 break;
 735         case USB_REQ_SET_SEL:
 736                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL");
 737                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 738                 break;
 739         case USB_REQ_SET_ISOCH_DELAY:
 740                 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY");
 741                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 742                 break;
 743         default:
 744                 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver");
 745                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 746                 break;
 747         }
 748
 749         return ret;
 750 }
 751
 752 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 753                 const struct dwc3_event_depevt *event)
 754 {
 755         struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
 756         int ret = -EINVAL;
 757         u32 len;
 758
 759         if (!dwc->gadget_driver)
 760                 goto out;
 761
 762         trace_dwc3_ctrl_req(ctrl);
 763
 764         len = le16_to_cpu(ctrl->wLength);
 765         if (!len) {
 766                 dwc->three_stage_setup = false;
 767                 dwc->ep0_expect_in = false;
 768                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 769         } else {
 770                 dwc->three_stage_setup = true;
 771                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 772                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 773         }
 774
 775         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 776                 ret = dwc3_ep0_std_request(dwc, ctrl);
 777         else
 778                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 779
 780         if (ret == USB_GADGET_DELAYED_STATUS)
 781                 dwc->delayed_status = true;
 782
 783 out:
 784         if (ret < 0)
 785                 dwc3_ep0_stall_and_restart(dwc);
 786 }
 787
 788 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 789                 const struct dwc3_event_depevt *event)
 790 {
 791         struct dwc3_request     *r = NULL;
 792         struct usb_request      *ur;
 793         struct dwc3_trb         *trb;
 794         struct dwc3_ep          *ep0;
 795         unsigned                transfer_size = 0;
 796         unsigned                maxp;
 797         unsigned                remaining_ur_length;
 798         void                    *buf;
 799         u32                     transferred = 0;
 800         u32                     status;
 801         u32                     length;
 802         u8                      epnum;
 803
 804         epnum = event->endpoint_number;
 805         ep0 = dwc->eps[0];
 806
 807         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 808
 809         trb = dwc->ep0_trb;
 810
 811         trace_dwc3_complete_trb(ep0, trb);
 812
 813         r = next_request(&ep0->pending_list);
 814         if (!r)
 815                 return;
 816
 817         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 818         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 819                 dwc->setup_packet_pending = true;
 820
 821                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 822
 823                 if (r)
 824                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 825
 826                 return;
 827         }
 828
 829         ur = &r->request;
 830         buf = ur->buf;
 831         remaining_ur_length = ur->length;
 832
 833         length = trb->size & DWC3_TRB_SIZE_MASK;
 834
 835         maxp = ep0->endpoint.maxpacket;
 836
 837         if (dwc->ep0_bounced) {
 838                 /*
 839                  * Handle the first TRB before handling the bounce buffer if
 840                  * the request length is greater than the bounce buffer size
 841                  */
 842                 if (ur->length > DWC3_EP0_BOUNCE_SIZE) {
 843                         transfer_size = ALIGN(ur->length - maxp, maxp);
 844                         transferred = transfer_size - length;
 845                         buf = (u8 *)buf + transferred;
 846                         ur->actual += transferred;
 847                         remaining_ur_length -= transferred;
 848
 849                         trb++;
 850                         length = trb->size & DWC3_TRB_SIZE_MASK;
 851
 852                         ep0->trb_enqueue = 0;
 853                 }
 854
 855                 transfer_size = roundup((ur->length - transfer_size),
 856                                         maxp);
 857
 858                 transferred = min_t(u32, remaining_ur_length,
 859                                     transfer_size - length);
 860                 memcpy(buf, dwc->ep0_bounce, transferred);
 861         } else {
 862                 transferred = ur->length - length;
 863         }
 864
 865         ur->actual += transferred;
 866
 867         if ((epnum & 1) && ur->actual < ur->length) {
 868                 /* for some reason we did not get everything out */
 869
 870                 dwc3_ep0_stall_and_restart(dwc);
 871         } else {
 872                 dwc3_gadget_giveback(ep0, r, 0);
 873
 874                 if (IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 875                                 ur->length && ur->zero) {
 876                         int ret;
 877
 878                         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
 879
 880                         ret = dwc3_ep0_start_trans(dwc, epnum,
 881                                         dwc->ctrl_req_addr, 0,
 882                                         DWC3_TRBCTL_CONTROL_DATA, false);
 883                         WARN_ON(ret < 0);
 884                 }
 885         }
 886 }
 887
 888 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 889                 const struct dwc3_event_depevt *event)
 890 {
 891         struct dwc3_request     *r;
 892         struct dwc3_ep          *dep;
 893         struct dwc3_trb         *trb;
 894         u32                     status;
 895
 896         dep = dwc->eps[0];
 897         trb = dwc->ep0_trb;
 898
 899         trace_dwc3_complete_trb(dep, trb);
 900
 901         if (!list_empty(&dep->pending_list)) {
 902                 r = next_request(&dep->pending_list);
 903
 904                 dwc3_gadget_giveback(dep, r, 0);
 905         }
 906
 907         if (dwc->test_mode) {
 908                 int ret;
 909
 910                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 911                 if (ret < 0) {
 912                         dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
 913                                         dwc->test_mode_nr);
 914                         dwc3_ep0_stall_and_restart(dwc);
 915                         return;
 916                 }
 917         }
 918
 919         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 920         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 921                 dwc->setup_packet_pending = true;
 922                 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
 923         }
 924
 925         dwc->ep0state = EP0_SETUP_PHASE;
 926         dwc3_ep0_out_start(dwc);
 927 }
 928
 929 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 930                         const struct dwc3_event_depevt *event)
 931 {
 932         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 933
 934         dep->flags &= ~DWC3_EP_BUSY;
 935         dep->resource_index = 0;
 936         dwc->setup_packet_pending = false;
 937
 938         switch (dwc->ep0state) {
 939         case EP0_SETUP_PHASE:
 940                 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
 941                 dwc3_ep0_inspect_setup(dwc, event);
 942                 break;
 943
 944         case EP0_DATA_PHASE:
 945                 dwc3_trace(trace_dwc3_ep0, "Data Phase");
 946                 dwc3_ep0_complete_data(dwc, event);
 947                 break;
 948
 949         case EP0_STATUS_PHASE:
 950                 dwc3_trace(trace_dwc3_ep0, "Status Phase");
 951                 dwc3_ep0_complete_status(dwc, event);
 952                 break;
 953         default:
 954                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 955         }
 956 }
 957
 958 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 959                 struct dwc3_ep *dep, struct dwc3_request *req)
 960 {
 961         int                     ret;
 962
 963         req->direction = !!dep->number;
 964
 965         if (req->request.length == 0) {
 966                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 967                                 dwc->ctrl_req_addr, 0,
 968                                 DWC3_TRBCTL_CONTROL_DATA, false);
 969         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 970                         && (dep->number == 0)) {
 971                 u32     transfer_size = 0;
 972                 u32     maxpacket;
 973
 974                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
 975                                 dep->number);
 976                 if (ret) {
 977                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
 978                         return;
 979                 }
 980
 981                 maxpacket = dep->endpoint.maxpacket;
 982
 983                 if (req->request.length > DWC3_EP0_BOUNCE_SIZE) {
 984                         transfer_size = ALIGN(req->request.length - maxpacket,
 985                                               maxpacket);
 986                         ret = dwc3_ep0_start_trans(dwc, dep->number,
 987                                                    req->request.dma,
 988                                                    transfer_size,
 989                                                    DWC3_TRBCTL_CONTROL_DATA,
 990                                                    true);
 991                 }
 992
 993                 transfer_size = roundup((req->request.length - transfer_size),
 994                                         maxpacket);
 995
 996                 dwc->ep0_bounced = true;
 997
 998                 ret = dwc3_ep0_start_trans(dwc, dep->number,
 999                                 dwc->ep0_bounce_addr, transfer_size,
1000                                 DWC3_TRBCTL_CONTROL_DATA, false);
1001         } else {
1002                 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
1003                                 dep->number);
1004                 if (ret) {
1005                         dwc3_trace(trace_dwc3_ep0, "failed to map request\n");
1006                         return;
1007                 }
1008
1009                 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
1010                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1011                                 false);
1012         }
1013
1014         WARN_ON(ret < 0);
1015 }
1016
1017 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1018 {
1019         struct dwc3             *dwc = dep->dwc;
1020         u32                     type;
1021
1022         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1023                 : DWC3_TRBCTL_CONTROL_STATUS2;
1024
1025         return dwc3_ep0_start_trans(dwc, dep->number,
1026                         dwc->ctrl_req_addr, 0, type, false);
1027 }
1028
1029 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1030 {
1031         WARN_ON(dwc3_ep0_start_control_status(dep));
1032 }
1033
1034 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1035                 const struct dwc3_event_depevt *event)
1036 {
1037         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1038
1039         __dwc3_ep0_do_control_status(dwc, dep);
1040 }
1041
1042 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1043 {
1044         struct dwc3_gadget_ep_cmd_params params;
1045         u32                     cmd;
1046         int                     ret;
1047
1048         if (!dep->resource_index)
1049                 return;
1050
1051         cmd = DWC3_DEPCMD_ENDTRANSFER;
1052         cmd |= DWC3_DEPCMD_CMDIOC;
1053         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1054         memset(&params, 0, sizeof(params));
1055         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1056         WARN_ON_ONCE(ret);
1057         dep->resource_index = 0;
1058 }
1059
1060 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1061                 const struct dwc3_event_depevt *event)
1062 {
1063         switch (event->status) {
1064         case DEPEVT_STATUS_CONTROL_DATA:
1065                 dwc3_trace(trace_dwc3_ep0, "Control Data");
1066
1067                 /*
1068                  * We already have a DATA transfer in the controller's cache,
1069                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1070                  * it's for the wrong direction.
1071                  *
1072                  * In that case, we must issue END_TRANSFER command to the Data
1073                  * Phase we already have started and issue SetStall on the
1074                  * control endpoint.
1075                  */
1076                 if (dwc->ep0_expect_in != event->endpoint_number) {
1077                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1078
1079                         dwc3_trace(trace_dwc3_ep0,
1080                                         "Wrong direction for Data phase");
1081                         dwc3_ep0_end_control_data(dwc, dep);
1082                         dwc3_ep0_stall_and_restart(dwc);
1083                         return;
1084                 }
1085
1086                 break;
1087
1088         case DEPEVT_STATUS_CONTROL_STATUS:
1089                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1090                         return;
1091
1092                 dwc3_trace(trace_dwc3_ep0, "Control Status");
1093
1094                 dwc->ep0state = EP0_STATUS_PHASE;
1095
1096                 if (dwc->delayed_status) {
1097                         WARN_ON_ONCE(event->endpoint_number != 1);
1098                         dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1099                         return;
1100                 }
1101
1102                 dwc3_ep0_do_control_status(dwc, event);
1103         }
1104 }
1105
1106 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1107                 const struct dwc3_event_depevt *event)
1108 {
1109         dwc3_trace(trace_dwc3_ep0, "%s: state '%s'",
1110                         dwc3_ep_event_string(event),
1111                         dwc3_ep0_state_string(dwc->ep0state));
1112
1113         switch (event->endpoint_event) {
1114         case DWC3_DEPEVT_XFERCOMPLETE:
1115                 dwc3_ep0_xfer_complete(dwc, event);
1116                 break;
1117
1118         case DWC3_DEPEVT_XFERNOTREADY:
1119                 dwc3_ep0_xfernotready(dwc, event);
1120                 break;
1121
1122         case DWC3_DEPEVT_XFERINPROGRESS:
1123         case DWC3_DEPEVT_RXTXFIFOEVT:
1124         case DWC3_DEPEVT_STREAMEVT:
1125         case DWC3_DEPEVT_EPCMDCMPLT:
1126                 break;
1127         }
1128 }