2 * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/slab.h>
21 #include <linux/spinlock.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/interrupt.h>
26 #include <linux/list.h>
27 #include <linux/dma-mapping.h>
29 #include <linux/usb/ch9.h>
30 #include <linux/usb/gadget.h>
31 #include <linux/usb/composite.h>
38 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
39 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
40 struct dwc3_ep *dep, struct dwc3_request *req);
42 static const char *dwc3_ep0_state_string(enum dwc3_ep0_state state)
51 case EP0_STATUS_PHASE:
52 return "Status Phase";
58 static int dwc3_ep0_start_trans(struct dwc3 *dwc, u8 epnum, dma_addr_t buf_dma,
61 struct dwc3_gadget_ep_cmd_params params;
67 dep = dwc->eps[epnum];
68 if (dep->flags & DWC3_EP_BUSY) {
69 dwc3_trace(trace_dwc3_ep0, "%s still busy", dep->name);
75 trb->bpl = lower_32_bits(buf_dma);
76 trb->bph = upper_32_bits(buf_dma);
80 trb->ctrl |= (DWC3_TRB_CTRL_HWO
83 | DWC3_TRB_CTRL_ISP_IMI);
85 memset(¶ms, 0, sizeof(params));
86 params.param0 = upper_32_bits(dwc->ep0_trb_addr);
87 params.param1 = lower_32_bits(dwc->ep0_trb_addr);
89 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number,
90 DWC3_DEPCMD_STARTTRANSFER, ¶ms);
92 dwc3_trace(trace_dwc3_ep0, "%s STARTTRANSFER failed",
97 dep->flags |= DWC3_EP_BUSY;
98 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dwc,
101 dwc->ep0_next_event = DWC3_EP0_COMPLETE;
106 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
107 struct dwc3_request *req)
109 struct dwc3 *dwc = dep->dwc;
111 req->request.actual = 0;
112 req->request.status = -EINPROGRESS;
113 req->epnum = dep->number;
115 list_add_tail(&req->list, &dep->request_list);
118 * Gadget driver might not be quick enough to queue a request
119 * before we get a Transfer Not Ready event on this endpoint.
121 * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
122 * flag is set, it's telling us that as soon as Gadget queues the
123 * required request, we should kick the transfer here because the
124 * IRQ we were waiting for is long gone.
126 if (dep->flags & DWC3_EP_PENDING_REQUEST) {
129 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
131 if (dwc->ep0state != EP0_DATA_PHASE) {
132 dev_WARN(dwc->dev, "Unexpected pending request\n");
136 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
138 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
145 * In case gadget driver asked us to delay the STATUS phase,
148 if (dwc->delayed_status) {
151 direction = !dwc->ep0_expect_in;
152 dwc->delayed_status = false;
153 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
155 if (dwc->ep0state == EP0_STATUS_PHASE)
156 __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
158 dwc3_trace(trace_dwc3_ep0,
159 "too early for delayed status");
165 * Unfortunately we have uncovered a limitation wrt the Data Phase.
167 * Section 9.4 says we can wait for the XferNotReady(DATA) event to
168 * come before issueing Start Transfer command, but if we do, we will
169 * miss situations where the host starts another SETUP phase instead of
170 * the DATA phase. Such cases happen at least on TD.7.6 of the Link
171 * Layer Compliance Suite.
173 * The problem surfaces due to the fact that in case of back-to-back
174 * SETUP packets there will be no XferNotReady(DATA) generated and we
175 * will be stuck waiting for XferNotReady(DATA) forever.
177 * By looking at tables 9-13 and 9-14 of the Databook, we can see that
178 * it tells us to start Data Phase right away. It also mentions that if
179 * we receive a SETUP phase instead of the DATA phase, core will issue
180 * XferComplete for the DATA phase, before actually initiating it in
181 * the wire, with the TRB's status set to "SETUP_PENDING". Such status
182 * can only be used to print some debugging logs, as the core expects
183 * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
184 * just so it completes right away, without transferring anything and,
185 * only then, we can go back to the SETUP phase.
187 * Because of this scenario, SNPS decided to change the programming
188 * model of control transfers and support on-demand transfers only for
189 * the STATUS phase. To fix the issue we have now, we will always wait
190 * for gadget driver to queue the DATA phase's struct usb_request, then
191 * start it right away.
193 * If we're actually in a 2-stage transfer, we will wait for
194 * XferNotReady(STATUS).
196 if (dwc->three_stage_setup) {
199 direction = dwc->ep0_expect_in;
200 dwc->ep0state = EP0_DATA_PHASE;
202 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
204 dep->flags &= ~DWC3_EP0_DIR_IN;
210 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
213 struct dwc3_request *req = to_dwc3_request(request);
214 struct dwc3_ep *dep = to_dwc3_ep(ep);
215 struct dwc3 *dwc = dep->dwc;
221 spin_lock_irqsave(&dwc->lock, flags);
222 if (!dep->endpoint.desc) {
223 dwc3_trace(trace_dwc3_ep0,
224 "trying to queue request %p to disabled %s",
230 /* we share one TRB for ep0/1 */
231 if (!list_empty(&dep->request_list)) {
236 dwc3_trace(trace_dwc3_ep0,
237 "queueing request %p to %s length %d state '%s'",
238 request, dep->name, request->length,
239 dwc3_ep0_state_string(dwc->ep0state));
241 ret = __dwc3_gadget_ep0_queue(dep, req);
244 spin_unlock_irqrestore(&dwc->lock, flags);
249 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
253 /* reinitialize physical ep1 */
255 dep->flags = DWC3_EP_ENABLED;
257 /* stall is always issued on EP0 */
259 __dwc3_gadget_ep_set_halt(dep, 1);
260 dep->flags = DWC3_EP_ENABLED;
261 dwc->delayed_status = false;
263 if (!list_empty(&dep->request_list)) {
264 struct dwc3_request *req;
266 req = next_request(&dep->request_list);
267 dwc3_gadget_giveback(dep, req, -ECONNRESET);
270 dwc->ep0state = EP0_SETUP_PHASE;
271 dwc3_ep0_out_start(dwc);
274 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
276 struct dwc3_ep *dep = to_dwc3_ep(ep);
277 struct dwc3 *dwc = dep->dwc;
279 dwc3_ep0_stall_and_restart(dwc);
284 void dwc3_ep0_out_start(struct dwc3 *dwc)
288 ret = dwc3_ep0_start_trans(dwc, 0, dwc->ctrl_req_addr, 8,
289 DWC3_TRBCTL_CONTROL_SETUP);
293 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
296 u32 windex = le16_to_cpu(wIndex_le);
299 epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
300 if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
303 dep = dwc->eps[epnum];
304 if (dep->flags & DWC3_EP_ENABLED)
310 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
316 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
317 struct usb_ctrlrequest *ctrl)
323 __le16 *response_pkt;
325 recip = ctrl->bRequestType & USB_RECIP_MASK;
327 case USB_RECIP_DEVICE:
329 * LTM will be set once we know how to set this in HW.
331 usb_status |= dwc->is_selfpowered << USB_DEVICE_SELF_POWERED;
333 if (dwc->speed == DWC3_DSTS_SUPERSPEED) {
334 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
335 if (reg & DWC3_DCTL_INITU1ENA)
336 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
337 if (reg & DWC3_DCTL_INITU2ENA)
338 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
343 case USB_RECIP_INTERFACE:
345 * Function Remote Wake Capable D0
346 * Function Remote Wakeup D1
350 case USB_RECIP_ENDPOINT:
351 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
355 if (dep->flags & DWC3_EP_STALL)
356 usb_status = 1 << USB_ENDPOINT_HALT;
362 response_pkt = (__le16 *) dwc->setup_buf;
363 *response_pkt = cpu_to_le16(usb_status);
366 dwc->ep0_usb_req.dep = dep;
367 dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
368 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
369 dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
371 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
374 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
375 struct usb_ctrlrequest *ctrl, int set)
383 enum usb_device_state state;
385 wValue = le16_to_cpu(ctrl->wValue);
386 wIndex = le16_to_cpu(ctrl->wIndex);
387 recip = ctrl->bRequestType & USB_RECIP_MASK;
388 state = dwc->gadget.state;
391 case USB_RECIP_DEVICE:
394 case USB_DEVICE_REMOTE_WAKEUP:
397 * 9.4.1 says only only for SS, in AddressState only for
398 * default control pipe
400 case USB_DEVICE_U1_ENABLE:
401 if (state != USB_STATE_CONFIGURED)
403 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
406 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
408 reg |= DWC3_DCTL_INITU1ENA;
410 reg &= ~DWC3_DCTL_INITU1ENA;
411 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
414 case USB_DEVICE_U2_ENABLE:
415 if (state != USB_STATE_CONFIGURED)
417 if (dwc->speed != DWC3_DSTS_SUPERSPEED)
420 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
422 reg |= DWC3_DCTL_INITU2ENA;
424 reg &= ~DWC3_DCTL_INITU2ENA;
425 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
428 case USB_DEVICE_LTM_ENABLE:
432 case USB_DEVICE_TEST_MODE:
433 if ((wIndex & 0xff) != 0)
438 dwc->test_mode_nr = wIndex >> 8;
439 dwc->test_mode = true;
446 case USB_RECIP_INTERFACE:
448 case USB_INTRF_FUNC_SUSPEND:
449 if (wIndex & USB_INTRF_FUNC_SUSPEND_LP)
450 /* XXX enable Low power suspend */
452 if (wIndex & USB_INTRF_FUNC_SUSPEND_RW)
453 /* XXX enable remote wakeup */
461 case USB_RECIP_ENDPOINT:
463 case USB_ENDPOINT_HALT:
464 dep = dwc3_wIndex_to_dep(dwc, wIndex);
467 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
469 ret = __dwc3_gadget_ep_set_halt(dep, set);
485 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
487 enum usb_device_state state = dwc->gadget.state;
491 addr = le16_to_cpu(ctrl->wValue);
493 dwc3_trace(trace_dwc3_ep0, "invalid device address %d", addr);
497 if (state == USB_STATE_CONFIGURED) {
498 dwc3_trace(trace_dwc3_ep0,
499 "trying to set address when configured");
503 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
504 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
505 reg |= DWC3_DCFG_DEVADDR(addr);
506 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
509 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
511 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
516 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
520 spin_unlock(&dwc->lock);
521 ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
522 spin_lock(&dwc->lock);
526 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
528 enum usb_device_state state = dwc->gadget.state;
533 dwc->start_config_issued = false;
534 cfg = le16_to_cpu(ctrl->wValue);
537 case USB_STATE_DEFAULT:
541 case USB_STATE_ADDRESS:
542 ret = dwc3_ep0_delegate_req(dwc, ctrl);
543 /* if the cfg matches and the cfg is non zero */
544 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
547 * only change state if set_config has already
548 * been processed. If gadget driver returns
549 * USB_GADGET_DELAYED_STATUS, we will wait
550 * to change the state on the next usb_ep_queue()
553 usb_gadget_set_state(&dwc->gadget,
554 USB_STATE_CONFIGURED);
557 * Enable transition to U1/U2 state when
558 * nothing is pending from application.
560 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
561 reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
562 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
564 dwc->resize_fifos = true;
565 dwc3_trace(trace_dwc3_ep0, "resize FIFOs flag SET");
569 case USB_STATE_CONFIGURED:
570 ret = dwc3_ep0_delegate_req(dwc, ctrl);
572 usb_gadget_set_state(&dwc->gadget,
581 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
583 struct dwc3_ep *dep = to_dwc3_ep(ep);
584 struct dwc3 *dwc = dep->dwc;
598 memcpy(&timing, req->buf, sizeof(timing));
600 dwc->u1sel = timing.u1sel;
601 dwc->u1pel = timing.u1pel;
602 dwc->u2sel = le16_to_cpu(timing.u2sel);
603 dwc->u2pel = le16_to_cpu(timing.u2pel);
605 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
606 if (reg & DWC3_DCTL_INITU2ENA)
608 if (reg & DWC3_DCTL_INITU1ENA)
612 * According to Synopsys Databook, if parameter is
613 * greater than 125, a value of zero should be
614 * programmed in the register.
619 /* now that we have the time, issue DGCMD Set Sel */
620 ret = dwc3_send_gadget_generic_command(dwc,
621 DWC3_DGCMD_SET_PERIODIC_PAR, param);
625 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
628 enum usb_device_state state = dwc->gadget.state;
632 if (state == USB_STATE_DEFAULT)
635 wValue = le16_to_cpu(ctrl->wValue);
636 wLength = le16_to_cpu(ctrl->wLength);
639 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
645 * To handle Set SEL we need to receive 6 bytes from Host. So let's
646 * queue a usb_request for 6 bytes.
648 * Remember, though, this controller can't handle non-wMaxPacketSize
649 * aligned transfers on the OUT direction, so we queue a request for
650 * wMaxPacketSize instead.
653 dwc->ep0_usb_req.dep = dep;
654 dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
655 dwc->ep0_usb_req.request.buf = dwc->setup_buf;
656 dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
658 return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
661 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
667 wValue = le16_to_cpu(ctrl->wValue);
668 wLength = le16_to_cpu(ctrl->wLength);
669 wIndex = le16_to_cpu(ctrl->wIndex);
671 if (wIndex || wLength)
675 * REVISIT It's unclear from Databook what to do with this
676 * value. For now, just cache it.
678 dwc->isoch_delay = wValue;
683 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
687 switch (ctrl->bRequest) {
688 case USB_REQ_GET_STATUS:
689 dwc3_trace(trace_dwc3_ep0, "USB_REQ_GET_STATUS\n");
690 ret = dwc3_ep0_handle_status(dwc, ctrl);
692 case USB_REQ_CLEAR_FEATURE:
693 dwc3_trace(trace_dwc3_ep0, "USB_REQ_CLEAR_FEATURE\n");
694 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
696 case USB_REQ_SET_FEATURE:
697 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_FEATURE\n");
698 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
700 case USB_REQ_SET_ADDRESS:
701 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ADDRESS\n");
702 ret = dwc3_ep0_set_address(dwc, ctrl);
704 case USB_REQ_SET_CONFIGURATION:
705 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_CONFIGURATION\n");
706 ret = dwc3_ep0_set_config(dwc, ctrl);
708 case USB_REQ_SET_SEL:
709 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_SEL\n");
710 ret = dwc3_ep0_set_sel(dwc, ctrl);
712 case USB_REQ_SET_ISOCH_DELAY:
713 dwc3_trace(trace_dwc3_ep0, "USB_REQ_SET_ISOCH_DELAY\n");
714 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
717 dwc3_trace(trace_dwc3_ep0, "Forwarding to gadget driver\n");
718 ret = dwc3_ep0_delegate_req(dwc, ctrl);
725 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
726 const struct dwc3_event_depevt *event)
728 struct usb_ctrlrequest *ctrl = dwc->ctrl_req;
732 if (!dwc->gadget_driver)
735 trace_dwc3_ctrl_req(ctrl);
737 len = le16_to_cpu(ctrl->wLength);
739 dwc->three_stage_setup = false;
740 dwc->ep0_expect_in = false;
741 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
743 dwc->three_stage_setup = true;
744 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
745 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
748 if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
749 ret = dwc3_ep0_std_request(dwc, ctrl);
751 ret = dwc3_ep0_delegate_req(dwc, ctrl);
753 if (ret == USB_GADGET_DELAYED_STATUS)
754 dwc->delayed_status = true;
758 dwc3_ep0_stall_and_restart(dwc);
761 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
762 const struct dwc3_event_depevt *event)
764 struct dwc3_request *r = NULL;
765 struct usb_request *ur;
766 struct dwc3_trb *trb;
773 epnum = event->endpoint_number;
776 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
778 r = next_request(&ep0->request_list);
783 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
784 if (status == DWC3_TRBSTS_SETUP_PENDING) {
785 dwc3_trace(trace_dwc3_ep0, "Setup Pending received");
788 dwc3_gadget_giveback(ep0, r, -ECONNRESET);
793 length = trb->size & DWC3_TRB_SIZE_MASK;
795 if (dwc->ep0_bounced) {
796 unsigned transfer_size = ur->length;
797 unsigned maxp = ep0->endpoint.maxpacket;
799 transfer_size += (maxp - (transfer_size % maxp));
800 transferred = min_t(u32, ur->length,
801 transfer_size - length);
802 memcpy(ur->buf, dwc->ep0_bounce, transferred);
804 transferred = ur->length - length;
807 ur->actual += transferred;
809 if ((epnum & 1) && ur->actual < ur->length) {
810 /* for some reason we did not get everything out */
812 dwc3_ep0_stall_and_restart(dwc);
815 * handle the case where we have to send a zero packet. This
816 * seems to be case when req.length > maxpacket. Could it be?
819 dwc3_gadget_giveback(ep0, r, 0);
823 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
824 const struct dwc3_event_depevt *event)
826 struct dwc3_request *r;
828 struct dwc3_trb *trb;
834 if (!list_empty(&dep->request_list)) {
835 r = next_request(&dep->request_list);
837 dwc3_gadget_giveback(dep, r, 0);
840 if (dwc->test_mode) {
843 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
845 dwc3_trace(trace_dwc3_ep0, "Invalid Test #%d",
847 dwc3_ep0_stall_and_restart(dwc);
852 status = DWC3_TRB_SIZE_TRBSTS(trb->size);
853 if (status == DWC3_TRBSTS_SETUP_PENDING)
854 dwc3_trace(trace_dwc3_ep0, "Setup Pending received\n");
856 dwc->ep0state = EP0_SETUP_PHASE;
857 dwc3_ep0_out_start(dwc);
860 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
861 const struct dwc3_event_depevt *event)
863 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
865 dep->flags &= ~DWC3_EP_BUSY;
866 dep->resource_index = 0;
867 dwc->setup_packet_pending = false;
869 switch (dwc->ep0state) {
870 case EP0_SETUP_PHASE:
871 dwc3_trace(trace_dwc3_ep0, "Setup Phase");
872 dwc3_ep0_inspect_setup(dwc, event);
876 dwc3_trace(trace_dwc3_ep0, "Data Phase");
877 dwc3_ep0_complete_data(dwc, event);
880 case EP0_STATUS_PHASE:
881 dwc3_trace(trace_dwc3_ep0, "Status Phase");
882 dwc3_ep0_complete_status(dwc, event);
885 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
889 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
890 struct dwc3_ep *dep, struct dwc3_request *req)
894 req->direction = !!dep->number;
896 if (req->request.length == 0) {
897 ret = dwc3_ep0_start_trans(dwc, dep->number,
898 dwc->ctrl_req_addr, 0,
899 DWC3_TRBCTL_CONTROL_DATA);
900 } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
901 && (dep->number == 0)) {
905 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
908 dev_dbg(dwc->dev, "failed to map request\n");
912 WARN_ON(req->request.length > DWC3_EP0_BOUNCE_SIZE);
914 maxpacket = dep->endpoint.maxpacket;
915 transfer_size = roundup(req->request.length, maxpacket);
917 dwc->ep0_bounced = true;
920 * REVISIT in case request length is bigger than
921 * DWC3_EP0_BOUNCE_SIZE we will need two chained
922 * TRBs to handle the transfer.
924 ret = dwc3_ep0_start_trans(dwc, dep->number,
925 dwc->ep0_bounce_addr, transfer_size,
926 DWC3_TRBCTL_CONTROL_DATA);
928 ret = usb_gadget_map_request(&dwc->gadget, &req->request,
931 dev_dbg(dwc->dev, "failed to map request\n");
935 ret = dwc3_ep0_start_trans(dwc, dep->number, req->request.dma,
936 req->request.length, DWC3_TRBCTL_CONTROL_DATA);
942 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
944 struct dwc3 *dwc = dep->dwc;
947 type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
948 : DWC3_TRBCTL_CONTROL_STATUS2;
950 return dwc3_ep0_start_trans(dwc, dep->number,
951 dwc->ctrl_req_addr, 0, type);
954 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
956 if (dwc->resize_fifos) {
957 dwc3_trace(trace_dwc3_ep0, "Resizing FIFOs");
958 dwc3_gadget_resize_tx_fifos(dwc);
959 dwc->resize_fifos = 0;
962 WARN_ON(dwc3_ep0_start_control_status(dep));
965 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
966 const struct dwc3_event_depevt *event)
968 struct dwc3_ep *dep = dwc->eps[event->endpoint_number];
970 __dwc3_ep0_do_control_status(dwc, dep);
973 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
975 struct dwc3_gadget_ep_cmd_params params;
979 if (!dep->resource_index)
982 cmd = DWC3_DEPCMD_ENDTRANSFER;
983 cmd |= DWC3_DEPCMD_CMDIOC;
984 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
985 memset(¶ms, 0, sizeof(params));
986 ret = dwc3_send_gadget_ep_cmd(dwc, dep->number, cmd, ¶ms);
988 dep->resource_index = 0;
991 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
992 const struct dwc3_event_depevt *event)
994 dwc->setup_packet_pending = true;
996 switch (event->status) {
997 case DEPEVT_STATUS_CONTROL_DATA:
998 dwc3_trace(trace_dwc3_ep0, "Control Data");
1001 * We already have a DATA transfer in the controller's cache,
1002 * if we receive a XferNotReady(DATA) we will ignore it, unless
1003 * it's for the wrong direction.
1005 * In that case, we must issue END_TRANSFER command to the Data
1006 * Phase we already have started and issue SetStall on the
1009 if (dwc->ep0_expect_in != event->endpoint_number) {
1010 struct dwc3_ep *dep = dwc->eps[dwc->ep0_expect_in];
1012 dwc3_trace(trace_dwc3_ep0,
1013 "Wrong direction for Data phase");
1014 dwc3_ep0_end_control_data(dwc, dep);
1015 dwc3_ep0_stall_and_restart(dwc);
1021 case DEPEVT_STATUS_CONTROL_STATUS:
1022 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1025 dwc3_trace(trace_dwc3_ep0, "Control Status");
1027 dwc->ep0state = EP0_STATUS_PHASE;
1029 if (dwc->delayed_status) {
1030 WARN_ON_ONCE(event->endpoint_number != 1);
1031 dwc3_trace(trace_dwc3_ep0, "Delayed Status");
1035 dwc3_ep0_do_control_status(dwc, event);
1039 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1040 const struct dwc3_event_depevt *event)
1042 u8 epnum = event->endpoint_number;
1044 dwc3_trace(trace_dwc3_ep0, "%s while ep%d%s in state '%s'",
1045 dwc3_ep_event_string(event->endpoint_event),
1046 epnum >> 1, (epnum & 1) ? "in" : "out",
1047 dwc3_ep0_state_string(dwc->ep0state));
1049 switch (event->endpoint_event) {
1050 case DWC3_DEPEVT_XFERCOMPLETE:
1051 dwc3_ep0_xfer_complete(dwc, event);
1054 case DWC3_DEPEVT_XFERNOTREADY:
1055 dwc3_ep0_xfernotready(dwc, event);
1058 case DWC3_DEPEVT_XFERINPROGRESS:
1059 case DWC3_DEPEVT_RXTXFIFOEVT:
1060 case DWC3_DEPEVT_STREAMEVT:
1061 case DWC3_DEPEVT_EPCMDCMPLT: