2 * dwc3-rockchip.c - Rockchip Specific Glue layer
4 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
6 * Authors: William Wu <william.wu@rock-chips.com>
8 * This program is free software: you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 of
10 * the License as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
18 #include <linux/module.h>
19 #include <linux/mutex.h>
20 #include <linux/kernel.h>
21 #include <linux/slab.h>
22 #include <linux/platform_device.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/clk.h>
25 #include <linux/clk-provider.h>
27 #include <linux/of_platform.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/extcon.h>
30 #include <linux/freezer.h>
31 #include <linux/reset.h>
32 #include <linux/usb.h>
33 #include <linux/usb/hcd.h>
37 #include "../host/xhci.h"
39 #define DWC3_ROCKCHIP_AUTOSUSPEND_DELAY 500 /* ms */
41 struct dwc3_rockchip {
48 struct reset_control *otg_rst;
49 struct extcon_dev *edev;
50 struct notifier_block device_nb;
51 struct notifier_block host_nb;
52 struct work_struct otg_work;
56 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
57 unsigned long event, void *ptr)
59 struct dwc3_rockchip *rockchip =
60 container_of(nb, struct dwc3_rockchip, device_nb);
62 if (!rockchip->suspended)
63 schedule_work(&rockchip->otg_work);
68 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
69 unsigned long event, void *ptr)
71 struct dwc3_rockchip *rockchip =
72 container_of(nb, struct dwc3_rockchip, host_nb);
74 if (!rockchip->suspended)
75 schedule_work(&rockchip->otg_work);
80 static void dwc3_rockchip_otg_extcon_evt_work(struct work_struct *work)
82 struct dwc3_rockchip *rockchip =
83 container_of(work, struct dwc3_rockchip, otg_work);
84 struct dwc3 *dwc = rockchip->dwc;
85 struct extcon_dev *edev = rockchip->edev;
87 struct xhci_hcd *xhci;
92 mutex_lock(&rockchip->lock);
94 if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
95 if (rockchip->connected)
99 * If dr_mode is host only, never to set
100 * the mode to the peripheral mode.
102 if (dwc->dr_mode == USB_DR_MODE_HOST) {
103 dev_warn(rockchip->dev, "USB peripheral not support!\n");
108 * Assert otg reset can put the dwc in P2 state, it's
109 * necessary operation prior to phy power on. However,
110 * asserting the otg reset may affect dwc chip operation.
111 * The reset will clear all of the dwc controller registers.
112 * So we need to reinit the dwc controller after deassert
113 * the reset. We use pm runtime to initialize dwc controller.
114 * Also, there are no synchronization primitives, meaning
115 * the dwc3 core code could at least in theory access chip
116 * registers while the reset is asserted, with unknown impact.
118 reset_control_assert(rockchip->otg_rst);
119 usleep_range(1000, 1200);
120 reset_control_deassert(rockchip->otg_rst);
122 pm_runtime_get_sync(rockchip->dev);
123 pm_runtime_get_sync(dwc->dev);
125 spin_lock_irqsave(&dwc->lock, flags);
126 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
127 spin_unlock_irqrestore(&dwc->lock, flags);
129 rockchip->connected = true;
130 dev_info(rockchip->dev, "USB peripheral connected\n");
131 } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
132 if (rockchip->connected)
136 * If dr_mode is device only, never to
137 * set the mode to the host mode.
139 if (dwc->dr_mode == USB_DR_MODE_PERIPHERAL) {
140 dev_warn(rockchip->dev, "USB HOST not support!\n");
145 * Assert otg reset can put the dwc in P2 state, it's
146 * necessary operation prior to phy power on. However,
147 * asserting the otg reset may affect dwc chip operation.
148 * The reset will clear all of the dwc controller registers.
149 * So we need to reinit the dwc controller after deassert
150 * the reset. We use pm runtime to initialize dwc controller.
151 * Also, there are no synchronization primitives, meaning
152 * the dwc3 core code could at least in theory access chip
153 * registers while the reset is asserted, with unknown impact.
155 reset_control_assert(rockchip->otg_rst);
156 usleep_range(1000, 1200);
157 reset_control_deassert(rockchip->otg_rst);
160 * In usb3 phy init, it will access usb3 module, so we need
161 * to resume rockchip dev before phy init to make sure usb3
164 pm_runtime_get_sync(rockchip->dev);
167 * Don't abort on errors. If powering on a phy fails,
168 * we still need to init dwc controller and add the
169 * HCDs to avoid a crash when unloading the driver.
171 ret = phy_power_on(dwc->usb2_generic_phy);
173 dev_err(dwc->dev, "Failed to power on usb2 phy\n");
175 ret = phy_power_on(dwc->usb3_generic_phy);
177 phy_power_off(dwc->usb2_generic_phy);
178 dev_err(dwc->dev, "Failed to power on usb3 phy\n");
181 pm_runtime_get_sync(dwc->dev);
183 spin_lock_irqsave(&dwc->lock, flags);
184 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
185 spin_unlock_irqrestore(&dwc->lock, flags);
188 * The following sleep helps to ensure that inserted USB3
189 * Ethernet devices are discovered if already inserted
192 usleep_range(10000, 11000);
194 hcd = dev_get_drvdata(&dwc->xhci->dev);
196 if (hcd->state == HC_STATE_HALT) {
197 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
198 usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
201 rockchip->connected = true;
202 dev_info(rockchip->dev, "USB HOST connected\n");
204 if (!rockchip->connected)
207 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
210 * xhci does not support runtime pm. If HCDs are not removed
211 * here and and re-added after a cable is inserted, USB3
212 * connections will not work.
213 * A clean(er) solution would be to implement runtime pm
214 * support in xhci. After that is available, this code should
216 * HCDs have to be removed here to prevent attempts by the
217 * xhci code to access xhci registers after the call to
218 * pm_runtime_put_sync_suspend(). On rk3399, this can result
219 * in a crash under certain circumstances (this was observed
220 * on 3399 chromebook if the system is running on battery).
222 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
223 DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
224 hcd = dev_get_drvdata(&dwc->xhci->dev);
225 xhci = hcd_to_xhci(hcd);
227 if (hcd->state != HC_STATE_HALT) {
228 xhci->xhc_state |= XHCI_STATE_REMOVING;
232 * Wait until XHCI controller resume from
233 * PM suspend, them we can remove hcd safely.
235 while (dwc->xhci->dev.power.is_suspended) {
237 dev_err(rockchip->dev,
238 "wait for XHCI resume 10s timeout!\n");
244 #ifdef CONFIG_FREEZER
246 * usb_remove_hcd() may call usb_disconnect() to
247 * remove a block device pluged in before.
248 * Unfortunately, the block layer suspend/resume
249 * path is fundamentally broken due to freezable
250 * kthreads and workqueue and may deadlock if a
251 * block device gets removed while resume is in
254 * We need to add a ugly hack to avoid removing
255 * hcd and kicking off device removal while
256 * freezer is active. This is a joke but does
257 * avoid this particular deadlock when test with
258 * USB-C HUB and USB2/3 flash drive.
261 usleep_range(10000, 11000);
264 usb_remove_hcd(hcd->shared_hcd);
268 phy_power_off(dwc->usb2_generic_phy);
269 phy_power_off(dwc->usb3_generic_phy);
272 pm_runtime_put_sync(rockchip->dev);
273 pm_runtime_put_sync_suspend(dwc->dev);
275 rockchip->connected = false;
276 dev_info(rockchip->dev, "USB unconnected\n");
280 mutex_unlock(&rockchip->lock);
283 static int dwc3_rockchip_extcon_register(struct dwc3_rockchip *rockchip)
286 struct device *dev = rockchip->dev;
287 struct extcon_dev *edev;
289 if (device_property_read_bool(dev, "extcon")) {
290 edev = extcon_get_edev_by_phandle(dev, 0);
292 if (PTR_ERR(edev) != -EPROBE_DEFER)
293 dev_err(dev, "couldn't get extcon device\n");
294 return PTR_ERR(edev);
297 INIT_WORK(&rockchip->otg_work,
298 dwc3_rockchip_otg_extcon_evt_work);
300 rockchip->device_nb.notifier_call =
301 dwc3_rockchip_device_notifier;
302 ret = extcon_register_notifier(edev, EXTCON_USB,
303 &rockchip->device_nb);
305 dev_err(dev, "failed to register notifier for USB\n");
309 rockchip->host_nb.notifier_call =
310 dwc3_rockchip_host_notifier;
311 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
314 dev_err(dev, "failed to register notifier for USB HOST\n");
315 extcon_unregister_notifier(edev, EXTCON_USB,
316 &rockchip->device_nb);
320 rockchip->edev = edev;
326 static void dwc3_rockchip_extcon_unregister(struct dwc3_rockchip *rockchip)
331 extcon_unregister_notifier(rockchip->edev, EXTCON_USB,
332 &rockchip->device_nb);
333 extcon_unregister_notifier(rockchip->edev, EXTCON_USB_HOST,
335 cancel_work_sync(&rockchip->otg_work);
338 static int dwc3_rockchip_probe(struct platform_device *pdev)
340 struct dwc3_rockchip *rockchip;
341 struct device *dev = &pdev->dev;
342 struct device_node *np = dev->of_node, *child;
343 struct platform_device *child_pdev;
349 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
354 count = of_clk_get_parent_count(np);
358 rockchip->num_clocks = count;
360 rockchip->clks = devm_kcalloc(dev, rockchip->num_clocks,
361 sizeof(struct clk *), GFP_KERNEL);
365 platform_set_drvdata(pdev, rockchip);
367 mutex_init(&rockchip->lock);
371 mutex_lock(&rockchip->lock);
373 for (i = 0; i < rockchip->num_clocks; i++) {
376 clk = of_clk_get(np, i);
382 ret = clk_prepare_enable(clk);
388 rockchip->clks[i] = clk;
391 pm_runtime_set_active(dev);
392 pm_runtime_enable(dev);
393 ret = pm_runtime_get_sync(dev);
395 dev_err(dev, "get_sync failed with err %d\n", ret);
399 rockchip->otg_rst = devm_reset_control_get(dev, "usb3-otg");
400 if (IS_ERR(rockchip->otg_rst)) {
401 dev_err(dev, "could not get reset controller\n");
402 ret = PTR_ERR(rockchip->otg_rst);
406 child = of_get_child_by_name(np, "dwc3");
408 dev_err(dev, "failed to find dwc3 core node\n");
413 /* Allocate and initialize the core */
414 ret = of_platform_populate(np, NULL, NULL, dev);
416 dev_err(dev, "failed to create dwc3 core\n");
420 child_pdev = of_find_device_by_node(child);
422 dev_err(dev, "failed to find dwc3 core device\n");
427 rockchip->dwc = platform_get_drvdata(child_pdev);
428 if (!rockchip->dwc) {
429 dev_err(dev, "failed to get drvdata dwc3\n");
434 ret = dwc3_rockchip_extcon_register(rockchip);
438 if (rockchip->edev) {
439 if (rockchip->dwc->dr_mode == USB_DR_MODE_HOST ||
440 rockchip->dwc->dr_mode == USB_DR_MODE_OTG) {
441 struct usb_hcd *hcd =
442 dev_get_drvdata(&rockchip->dwc->xhci->dev);
444 dev_err(dev, "fail to get drvdata hcd\n");
448 if (hcd->state != HC_STATE_HALT) {
449 usb_remove_hcd(hcd->shared_hcd);
454 pm_runtime_set_autosuspend_delay(&child_pdev->dev,
455 DWC3_ROCKCHIP_AUTOSUSPEND_DELAY);
456 pm_runtime_allow(&child_pdev->dev);
457 pm_runtime_suspend(&child_pdev->dev);
458 pm_runtime_put_sync(dev);
460 if ((extcon_get_cable_state_(rockchip->edev,
462 (extcon_get_cable_state_(rockchip->edev,
463 EXTCON_USB_HOST) > 0))
464 schedule_work(&rockchip->otg_work);
467 mutex_unlock(&rockchip->lock);
472 dwc3_rockchip_extcon_unregister(rockchip);
475 of_platform_depopulate(dev);
478 pm_runtime_put_sync(dev);
479 pm_runtime_disable(dev);
482 for (i = 0; i < rockchip->num_clocks && rockchip->clks[i]; i++) {
483 if (!pm_runtime_status_suspended(dev))
484 clk_disable(rockchip->clks[i]);
485 clk_unprepare(rockchip->clks[i]);
486 clk_put(rockchip->clks[i]);
489 mutex_unlock(&rockchip->lock);
494 static int dwc3_rockchip_remove(struct platform_device *pdev)
496 struct dwc3_rockchip *rockchip = platform_get_drvdata(pdev);
497 struct device *dev = &pdev->dev;
500 dwc3_rockchip_extcon_unregister(rockchip);
502 /* Restore hcd state before unregistering xhci */
503 if (rockchip->edev && !rockchip->connected) {
504 struct usb_hcd *hcd =
505 dev_get_drvdata(&rockchip->dwc->xhci->dev);
507 pm_runtime_get_sync(dev);
510 * The xhci code does not expect that HCDs have been removed.
511 * It will unconditionally call usb_remove_hcd() when the xhci
512 * driver is unloaded in of_platform_depopulate(). This results
513 * in a crash if the HCDs were already removed. To avoid this
514 * crash, add the HCDs here as dummy operation.
515 * This code should be removed after pm runtime support
516 * has been added to xhci.
518 if (hcd->state == HC_STATE_HALT) {
519 usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
520 usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
524 of_platform_depopulate(dev);
526 pm_runtime_put_sync(dev);
527 pm_runtime_disable(dev);
529 for (i = 0; i < rockchip->num_clocks; i++) {
530 if (!pm_runtime_status_suspended(dev))
531 clk_disable(rockchip->clks[i]);
532 clk_unprepare(rockchip->clks[i]);
533 clk_put(rockchip->clks[i]);
540 static int dwc3_rockchip_runtime_suspend(struct device *dev)
542 struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
545 for (i = 0; i < rockchip->num_clocks; i++)
546 clk_disable(rockchip->clks[i]);
548 device_init_wakeup(dev, false);
553 static int dwc3_rockchip_runtime_resume(struct device *dev)
555 struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
558 for (i = 0; i < rockchip->num_clocks; i++)
559 clk_enable(rockchip->clks[i]);
561 device_init_wakeup(dev, true);
566 static int dwc3_rockchip_suspend(struct device *dev)
568 struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
570 rockchip->suspended = true;
571 cancel_work_sync(&rockchip->otg_work);
576 static int dwc3_rockchip_resume(struct device *dev)
578 struct dwc3_rockchip *rockchip = dev_get_drvdata(dev);
580 rockchip->suspended = false;
583 schedule_work(&rockchip->otg_work);
588 static const struct dev_pm_ops dwc3_rockchip_dev_pm_ops = {
589 SET_SYSTEM_SLEEP_PM_OPS(dwc3_rockchip_suspend, dwc3_rockchip_resume)
590 SET_RUNTIME_PM_OPS(dwc3_rockchip_runtime_suspend,
591 dwc3_rockchip_runtime_resume, NULL)
594 #define DEV_PM_OPS (&dwc3_rockchip_dev_pm_ops)
596 #define DEV_PM_OPS NULL
597 #endif /* CONFIG_PM */
599 static const struct of_device_id rockchip_dwc3_match[] = {
600 { .compatible = "rockchip,rk3399-dwc3" },
604 MODULE_DEVICE_TABLE(of, rockchip_dwc3_match);
606 static struct platform_driver dwc3_rockchip_driver = {
607 .probe = dwc3_rockchip_probe,
608 .remove = dwc3_rockchip_remove,
610 .name = "rockchip-dwc3",
611 .of_match_table = rockchip_dwc3_match,
616 module_platform_driver(dwc3_rockchip_driver);
618 MODULE_ALIAS("platform:rockchip-dwc3");
619 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
620 MODULE_LICENSE("GPL v2");
621 MODULE_DESCRIPTION("DesignWare USB3 ROCKCHIP Glue Layer");