2 * dwc3-omap.c - OMAP Specific Glue layer
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/slab.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/platform_device.h>
45 #include <linux/platform_data/dwc3-omap.h>
46 #include <linux/usb/dwc3-omap.h>
47 #include <linux/pm_runtime.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/ioport.h>
52 #include <linux/of_platform.h>
54 #include <linux/usb/otg.h>
57 * All these registers belong to OMAP's Wrapper around the
58 * DesignWare USB3 Core.
61 #define USBOTGSS_REVISION 0x0000
62 #define USBOTGSS_SYSCONFIG 0x0010
63 #define USBOTGSS_IRQ_EOI 0x0020
64 #define USBOTGSS_IRQSTATUS_RAW_0 0x0024
65 #define USBOTGSS_IRQSTATUS_0 0x0028
66 #define USBOTGSS_IRQENABLE_SET_0 0x002c
67 #define USBOTGSS_IRQENABLE_CLR_0 0x0030
68 #define USBOTGSS_IRQSTATUS_RAW_1 0x0034
69 #define USBOTGSS_IRQSTATUS_1 0x0038
70 #define USBOTGSS_IRQENABLE_SET_1 0x003c
71 #define USBOTGSS_IRQENABLE_CLR_1 0x0040
72 #define USBOTGSS_UTMI_OTG_CTRL 0x0080
73 #define USBOTGSS_UTMI_OTG_STATUS 0x0084
74 #define USBOTGSS_MMRAM_OFFSET 0x0100
75 #define USBOTGSS_FLADJ 0x0104
76 #define USBOTGSS_DEBUG_CFG 0x0108
77 #define USBOTGSS_DEBUG_DATA 0x010c
79 /* SYSCONFIG REGISTER */
80 #define USBOTGSS_SYSCONFIG_DMADISABLE (1 << 16)
82 /* IRQ_EOI REGISTER */
83 #define USBOTGSS_IRQ_EOI_LINE_NUMBER (1 << 0)
86 #define USBOTGSS_IRQO_COREIRQ_ST (1 << 0)
89 #define USBOTGSS_IRQ1_DMADISABLECLR (1 << 17)
90 #define USBOTGSS_IRQ1_OEVT (1 << 16)
91 #define USBOTGSS_IRQ1_DRVVBUS_RISE (1 << 13)
92 #define USBOTGSS_IRQ1_CHRGVBUS_RISE (1 << 12)
93 #define USBOTGSS_IRQ1_DISCHRGVBUS_RISE (1 << 11)
94 #define USBOTGSS_IRQ1_IDPULLUP_RISE (1 << 8)
95 #define USBOTGSS_IRQ1_DRVVBUS_FALL (1 << 5)
96 #define USBOTGSS_IRQ1_CHRGVBUS_FALL (1 << 4)
97 #define USBOTGSS_IRQ1_DISCHRGVBUS_FALL (1 << 3)
98 #define USBOTGSS_IRQ1_IDPULLUP_FALL (1 << 0)
100 /* UTMI_OTG_CTRL REGISTER */
101 #define USBOTGSS_UTMI_OTG_CTRL_DRVVBUS (1 << 5)
102 #define USBOTGSS_UTMI_OTG_CTRL_CHRGVBUS (1 << 4)
103 #define USBOTGSS_UTMI_OTG_CTRL_DISCHRGVBUS (1 << 3)
104 #define USBOTGSS_UTMI_OTG_CTRL_IDPULLUP (1 << 0)
106 /* UTMI_OTG_STATUS REGISTER */
107 #define USBOTGSS_UTMI_OTG_STATUS_SW_MODE (1 << 31)
108 #define USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT (1 << 9)
109 #define USBOTGSS_UTMI_OTG_STATUS_TXBITSTUFFENABLE (1 << 8)
110 #define USBOTGSS_UTMI_OTG_STATUS_IDDIG (1 << 4)
111 #define USBOTGSS_UTMI_OTG_STATUS_SESSEND (1 << 3)
112 #define USBOTGSS_UTMI_OTG_STATUS_SESSVALID (1 << 2)
113 #define USBOTGSS_UTMI_OTG_STATUS_VBUSVALID (1 << 1)
129 static struct dwc3_omap *_omap;
131 static inline u32 dwc3_omap_readl(void __iomem *base, u32 offset)
133 return readl(base + offset);
136 static inline void dwc3_omap_writel(void __iomem *base, u32 offset, u32 value)
138 writel(value, base + offset);
141 int dwc3_omap_mailbox(enum omap_dwc3_vbus_id_status status)
144 struct dwc3_omap *omap = _omap;
147 return -EPROBE_DEFER;
150 case OMAP_DWC3_ID_GROUND:
151 dev_dbg(omap->dev, "ID GND\n");
153 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
154 val &= ~(USBOTGSS_UTMI_OTG_STATUS_IDDIG
155 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
156 | USBOTGSS_UTMI_OTG_STATUS_SESSEND);
157 val |= USBOTGSS_UTMI_OTG_STATUS_SESSVALID
158 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
159 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
162 case OMAP_DWC3_VBUS_VALID:
163 dev_dbg(omap->dev, "VBUS Connect\n");
165 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
166 val &= ~USBOTGSS_UTMI_OTG_STATUS_SESSEND;
167 val |= USBOTGSS_UTMI_OTG_STATUS_IDDIG
168 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
169 | USBOTGSS_UTMI_OTG_STATUS_SESSVALID
170 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT;
171 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
174 case OMAP_DWC3_ID_FLOAT:
175 case OMAP_DWC3_VBUS_OFF:
176 dev_dbg(omap->dev, "VBUS Disconnect\n");
178 val = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
179 val &= ~(USBOTGSS_UTMI_OTG_STATUS_SESSVALID
180 | USBOTGSS_UTMI_OTG_STATUS_VBUSVALID
181 | USBOTGSS_UTMI_OTG_STATUS_POWERPRESENT);
182 val |= USBOTGSS_UTMI_OTG_STATUS_SESSEND
183 | USBOTGSS_UTMI_OTG_STATUS_IDDIG;
184 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, val);
188 dev_dbg(omap->dev, "ID float\n");
193 EXPORT_SYMBOL_GPL(dwc3_omap_mailbox);
195 static irqreturn_t dwc3_omap_interrupt(int irq, void *_omap)
197 struct dwc3_omap *omap = _omap;
200 spin_lock(&omap->lock);
202 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_1);
204 if (reg & USBOTGSS_IRQ1_DMADISABLECLR) {
205 dev_dbg(omap->dev, "DMA Disable was Cleared\n");
206 omap->dma_status = false;
209 if (reg & USBOTGSS_IRQ1_OEVT)
210 dev_dbg(omap->dev, "OTG Event\n");
212 if (reg & USBOTGSS_IRQ1_DRVVBUS_RISE)
213 dev_dbg(omap->dev, "DRVVBUS Rise\n");
215 if (reg & USBOTGSS_IRQ1_CHRGVBUS_RISE)
216 dev_dbg(omap->dev, "CHRGVBUS Rise\n");
218 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_RISE)
219 dev_dbg(omap->dev, "DISCHRGVBUS Rise\n");
221 if (reg & USBOTGSS_IRQ1_IDPULLUP_RISE)
222 dev_dbg(omap->dev, "IDPULLUP Rise\n");
224 if (reg & USBOTGSS_IRQ1_DRVVBUS_FALL)
225 dev_dbg(omap->dev, "DRVVBUS Fall\n");
227 if (reg & USBOTGSS_IRQ1_CHRGVBUS_FALL)
228 dev_dbg(omap->dev, "CHRGVBUS Fall\n");
230 if (reg & USBOTGSS_IRQ1_DISCHRGVBUS_FALL)
231 dev_dbg(omap->dev, "DISCHRGVBUS Fall\n");
233 if (reg & USBOTGSS_IRQ1_IDPULLUP_FALL)
234 dev_dbg(omap->dev, "IDPULLUP Fall\n");
236 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_1, reg);
238 reg = dwc3_omap_readl(omap->base, USBOTGSS_IRQSTATUS_0);
239 dwc3_omap_writel(omap->base, USBOTGSS_IRQSTATUS_0, reg);
241 spin_unlock(&omap->lock);
246 static int dwc3_omap_remove_core(struct device *dev, void *c)
248 struct platform_device *pdev = to_platform_device(dev);
250 platform_device_unregister(pdev);
255 static void dwc3_omap_enable_irqs(struct dwc3_omap *omap)
259 /* enable all IRQs */
260 reg = USBOTGSS_IRQO_COREIRQ_ST;
261 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, reg);
263 reg = (USBOTGSS_IRQ1_OEVT |
264 USBOTGSS_IRQ1_DRVVBUS_RISE |
265 USBOTGSS_IRQ1_CHRGVBUS_RISE |
266 USBOTGSS_IRQ1_DISCHRGVBUS_RISE |
267 USBOTGSS_IRQ1_IDPULLUP_RISE |
268 USBOTGSS_IRQ1_DRVVBUS_FALL |
269 USBOTGSS_IRQ1_CHRGVBUS_FALL |
270 USBOTGSS_IRQ1_DISCHRGVBUS_FALL |
271 USBOTGSS_IRQ1_IDPULLUP_FALL);
273 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, reg);
276 static void dwc3_omap_disable_irqs(struct dwc3_omap *omap)
278 /* disable all IRQs */
279 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_1, 0x00);
280 dwc3_omap_writel(omap->base, USBOTGSS_IRQENABLE_SET_0, 0x00);
283 static u64 dwc3_omap_dma_mask = DMA_BIT_MASK(32);
285 static int dwc3_omap_probe(struct platform_device *pdev)
287 struct device_node *node = pdev->dev.of_node;
289 struct dwc3_omap *omap;
290 struct resource *res;
291 struct device *dev = &pdev->dev;
303 dev_err(dev, "device node not found\n");
307 omap = devm_kzalloc(dev, sizeof(*omap), GFP_KERNEL);
309 dev_err(dev, "not enough memory\n");
313 platform_set_drvdata(pdev, omap);
315 irq = platform_get_irq(pdev, 0);
317 dev_err(dev, "missing IRQ resource\n");
321 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
323 dev_err(dev, "missing memory base resource\n");
327 base = devm_ioremap_nocache(dev, res->start, resource_size(res));
329 dev_err(dev, "ioremap failed\n");
333 spin_lock_init(&omap->lock);
338 dev->dma_mask = &dwc3_omap_dma_mask;
341 * REVISIT if we ever have two instances of the wrapper, we will be
346 pm_runtime_enable(dev);
347 ret = pm_runtime_get_sync(dev);
349 dev_err(dev, "get_sync failed with err %d\n", ret);
353 reg = dwc3_omap_readl(omap->base, USBOTGSS_UTMI_OTG_STATUS);
355 of_property_read_u32(node, "utmi-mode", &utmi_mode);
358 case DWC3_OMAP_UTMI_MODE_SW:
359 reg |= USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
361 case DWC3_OMAP_UTMI_MODE_HW:
362 reg &= ~USBOTGSS_UTMI_OTG_STATUS_SW_MODE;
365 dev_dbg(dev, "UNKNOWN utmi mode %d\n", utmi_mode);
368 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS, reg);
370 /* check the DMA Status */
371 reg = dwc3_omap_readl(omap->base, USBOTGSS_SYSCONFIG);
372 omap->dma_status = !!(reg & USBOTGSS_SYSCONFIG_DMADISABLE);
374 ret = devm_request_irq(dev, omap->irq, dwc3_omap_interrupt, 0,
377 dev_err(dev, "failed to request IRQ #%d --> %d\n",
382 dwc3_omap_enable_irqs(omap);
384 ret = of_platform_populate(node, NULL, NULL, dev);
386 dev_err(&pdev->dev, "failed to create dwc3 core\n");
393 static int dwc3_omap_remove(struct platform_device *pdev)
395 struct dwc3_omap *omap = platform_get_drvdata(pdev);
397 dwc3_omap_disable_irqs(omap);
398 pm_runtime_put_sync(&pdev->dev);
399 pm_runtime_disable(&pdev->dev);
400 device_for_each_child(&pdev->dev, NULL, dwc3_omap_remove_core);
405 static const struct of_device_id of_dwc3_match[] = {
407 .compatible = "ti,dwc3"
411 MODULE_DEVICE_TABLE(of, of_dwc3_match);
413 #ifdef CONFIG_PM_SLEEP
414 static int dwc3_omap_prepare(struct device *dev)
416 struct dwc3_omap *omap = dev_get_drvdata(dev);
418 dwc3_omap_disable_irqs(omap);
423 static void dwc3_omap_complete(struct device *dev)
425 struct dwc3_omap *omap = dev_get_drvdata(dev);
427 dwc3_omap_enable_irqs(omap);
430 static int dwc3_omap_suspend(struct device *dev)
432 struct dwc3_omap *omap = dev_get_drvdata(dev);
434 omap->utmi_otg_status = dwc3_omap_readl(omap->base,
435 USBOTGSS_UTMI_OTG_STATUS);
440 static int dwc3_omap_resume(struct device *dev)
442 struct dwc3_omap *omap = dev_get_drvdata(dev);
444 dwc3_omap_writel(omap->base, USBOTGSS_UTMI_OTG_STATUS,
445 omap->utmi_otg_status);
447 pm_runtime_disable(dev);
448 pm_runtime_set_active(dev);
449 pm_runtime_enable(dev);
454 static const struct dev_pm_ops dwc3_omap_dev_pm_ops = {
455 .prepare = dwc3_omap_prepare,
456 .complete = dwc3_omap_complete,
458 SET_SYSTEM_SLEEP_PM_OPS(dwc3_omap_suspend, dwc3_omap_resume)
461 #define DEV_PM_OPS (&dwc3_omap_dev_pm_ops)
463 #define DEV_PM_OPS NULL
464 #endif /* CONFIG_PM_SLEEP */
466 static struct platform_driver dwc3_omap_driver = {
467 .probe = dwc3_omap_probe,
468 .remove = dwc3_omap_remove,
471 .of_match_table = of_dwc3_match,
476 module_platform_driver(dwc3_omap_driver);
478 MODULE_ALIAS("platform:omap-dwc3");
479 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
480 MODULE_LICENSE("Dual BSD/GPL");
481 MODULE_DESCRIPTION("DesignWare USB3 OMAP Glue Layer");