2 * core.h - DesignWare USB3 DRD Core Header
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The names of the above-listed copyright holders may not be used
19 * to endorse or promote products derived from this software without
20 * specific prior written permission.
22 * ALTERNATIVELY, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2, as published by the Free
24 * Software Foundation.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
27 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
28 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
30 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
31 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
32 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
33 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
34 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
35 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
36 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 #ifndef __DRIVERS_USB_DWC3_CORE_H
40 #define __DRIVERS_USB_DWC3_CORE_H
42 #include <linux/device.h>
43 #include <linux/spinlock.h>
44 #include <linux/ioport.h>
45 #include <linux/list.h>
46 #include <linux/dma-mapping.h>
48 #include <linux/debugfs.h>
50 #include <linux/usb/ch9.h>
51 #include <linux/usb/gadget.h>
53 /* Global constants */
54 #define DWC3_EP0_BOUNCE_SIZE 512
55 #define DWC3_ENDPOINTS_NUM 32
56 #define DWC3_XHCI_RESOURCES_NUM 2
58 #define DWC3_EVENT_BUFFERS_SIZE PAGE_SIZE
59 #define DWC3_EVENT_TYPE_MASK 0xfe
61 #define DWC3_EVENT_TYPE_DEV 0
62 #define DWC3_EVENT_TYPE_CARKIT 3
63 #define DWC3_EVENT_TYPE_I2C 4
65 #define DWC3_DEVICE_EVENT_DISCONNECT 0
66 #define DWC3_DEVICE_EVENT_RESET 1
67 #define DWC3_DEVICE_EVENT_CONNECT_DONE 2
68 #define DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE 3
69 #define DWC3_DEVICE_EVENT_WAKEUP 4
70 #define DWC3_DEVICE_EVENT_HIBER_REQ 5
71 #define DWC3_DEVICE_EVENT_EOPF 6
72 #define DWC3_DEVICE_EVENT_SOF 7
73 #define DWC3_DEVICE_EVENT_ERRATIC_ERROR 9
74 #define DWC3_DEVICE_EVENT_CMD_CMPL 10
75 #define DWC3_DEVICE_EVENT_OVERFLOW 11
77 #define DWC3_GEVNTCOUNT_MASK 0xfffc
78 #define DWC3_GSNPSID_MASK 0xffff0000
79 #define DWC3_GSNPSREV_MASK 0xffff
81 /* DWC3 registers memory space boundries */
82 #define DWC3_XHCI_REGS_START 0x0
83 #define DWC3_XHCI_REGS_END 0x7fff
84 #define DWC3_GLOBALS_REGS_START 0xc100
85 #define DWC3_GLOBALS_REGS_END 0xc6ff
86 #define DWC3_DEVICE_REGS_START 0xc700
87 #define DWC3_DEVICE_REGS_END 0xcbff
88 #define DWC3_OTG_REGS_START 0xcc00
89 #define DWC3_OTG_REGS_END 0xccff
91 /* Global Registers */
92 #define DWC3_GSBUSCFG0 0xc100
93 #define DWC3_GSBUSCFG1 0xc104
94 #define DWC3_GTXTHRCFG 0xc108
95 #define DWC3_GRXTHRCFG 0xc10c
96 #define DWC3_GCTL 0xc110
97 #define DWC3_GEVTEN 0xc114
98 #define DWC3_GSTS 0xc118
99 #define DWC3_GSNPSID 0xc120
100 #define DWC3_GGPIO 0xc124
101 #define DWC3_GUID 0xc128
102 #define DWC3_GUCTL 0xc12c
103 #define DWC3_GBUSERRADDR0 0xc130
104 #define DWC3_GBUSERRADDR1 0xc134
105 #define DWC3_GPRTBIMAP0 0xc138
106 #define DWC3_GPRTBIMAP1 0xc13c
107 #define DWC3_GHWPARAMS0 0xc140
108 #define DWC3_GHWPARAMS1 0xc144
109 #define DWC3_GHWPARAMS2 0xc148
110 #define DWC3_GHWPARAMS3 0xc14c
111 #define DWC3_GHWPARAMS4 0xc150
112 #define DWC3_GHWPARAMS5 0xc154
113 #define DWC3_GHWPARAMS6 0xc158
114 #define DWC3_GHWPARAMS7 0xc15c
115 #define DWC3_GDBGFIFOSPACE 0xc160
116 #define DWC3_GDBGLTSSM 0xc164
117 #define DWC3_GPRTBIMAP_HS0 0xc180
118 #define DWC3_GPRTBIMAP_HS1 0xc184
119 #define DWC3_GPRTBIMAP_FS0 0xc188
120 #define DWC3_GPRTBIMAP_FS1 0xc18c
122 #define DWC3_GUSB2PHYCFG(n) (0xc200 + (n * 0x04))
123 #define DWC3_GUSB2I2CCTL(n) (0xc240 + (n * 0x04))
125 #define DWC3_GUSB2PHYACC(n) (0xc280 + (n * 0x04))
127 #define DWC3_GUSB3PIPECTL(n) (0xc2c0 + (n * 0x04))
129 #define DWC3_GTXFIFOSIZ(n) (0xc300 + (n * 0x04))
130 #define DWC3_GRXFIFOSIZ(n) (0xc380 + (n * 0x04))
132 #define DWC3_GEVNTADRLO(n) (0xc400 + (n * 0x10))
133 #define DWC3_GEVNTADRHI(n) (0xc404 + (n * 0x10))
134 #define DWC3_GEVNTSIZ(n) (0xc408 + (n * 0x10))
135 #define DWC3_GEVNTCOUNT(n) (0xc40c + (n * 0x10))
137 #define DWC3_GHWPARAMS8 0xc600
139 /* Device Registers */
140 #define DWC3_DCFG 0xc700
141 #define DWC3_DCTL 0xc704
142 #define DWC3_DEVTEN 0xc708
143 #define DWC3_DSTS 0xc70c
144 #define DWC3_DGCMDPAR 0xc710
145 #define DWC3_DGCMD 0xc714
146 #define DWC3_DALEPENA 0xc720
147 #define DWC3_DEPCMDPAR2(n) (0xc800 + (n * 0x10))
148 #define DWC3_DEPCMDPAR1(n) (0xc804 + (n * 0x10))
149 #define DWC3_DEPCMDPAR0(n) (0xc808 + (n * 0x10))
150 #define DWC3_DEPCMD(n) (0xc80c + (n * 0x10))
153 #define DWC3_OCFG 0xcc00
154 #define DWC3_OCTL 0xcc04
155 #define DWC3_OEVTEN 0xcc08
156 #define DWC3_OSTS 0xcc0C
160 /* Global Configuration Register */
161 #define DWC3_GCTL_PWRDNSCALE(n) ((n) << 19)
162 #define DWC3_GCTL_U2RSTECN (1 << 16)
163 #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
164 #define DWC3_GCTL_CLK_BUS (0)
165 #define DWC3_GCTL_CLK_PIPE (1)
166 #define DWC3_GCTL_CLK_PIPEHALF (2)
167 #define DWC3_GCTL_CLK_MASK (3)
169 #define DWC3_GCTL_PRTCAP(n) (((n) & (3 << 12)) >> 12)
170 #define DWC3_GCTL_PRTCAPDIR(n) ((n) << 12)
171 #define DWC3_GCTL_PRTCAP_HOST 1
172 #define DWC3_GCTL_PRTCAP_DEVICE 2
173 #define DWC3_GCTL_PRTCAP_OTG 3
175 #define DWC3_GCTL_CORESOFTRESET (1 << 11)
176 #define DWC3_GCTL_SCALEDOWN(n) ((n) << 4)
177 #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3)
178 #define DWC3_GCTL_DISSCRAMBLE (1 << 3)
179 #define DWC3_GCTL_GBLHIBERNATIONEN (1 << 1)
180 #define DWC3_GCTL_DSBLCLKGTNG (1 << 0)
182 /* Global USB2 PHY Configuration Register */
183 #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31)
184 #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
186 /* Global USB3 PIPE Control Register */
187 #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31)
188 #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17)
190 /* Global TX Fifo Size Register */
191 #define DWC3_GTXFIFOSIZ_TXFDEF(n) ((n) & 0xffff)
192 #define DWC3_GTXFIFOSIZ_TXFSTADDR(n) ((n) & 0xffff0000)
194 /* Global HWPARAMS1 Register */
195 #define DWC3_GHWPARAMS1_EN_PWROPT(n) (((n) & (3 << 24)) >> 24)
196 #define DWC3_GHWPARAMS1_EN_PWROPT_NO 0
197 #define DWC3_GHWPARAMS1_EN_PWROPT_CLK 1
198 #define DWC3_GHWPARAMS1_EN_PWROPT_HIB 2
199 #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24)
200 #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3)
202 /* Global HWPARAMS4 Register */
203 #define DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(n) (((n) & (0x0f << 13)) >> 13)
204 #define DWC3_MAX_HIBER_SCRATCHBUFS 15
206 /* Device Configuration Register */
207 #define DWC3_DCFG_LPM_CAP (1 << 22)
208 #define DWC3_DCFG_DEVADDR(addr) ((addr) << 3)
209 #define DWC3_DCFG_DEVADDR_MASK DWC3_DCFG_DEVADDR(0x7f)
211 #define DWC3_DCFG_SPEED_MASK (7 << 0)
212 #define DWC3_DCFG_SUPERSPEED (4 << 0)
213 #define DWC3_DCFG_HIGHSPEED (0 << 0)
214 #define DWC3_DCFG_FULLSPEED2 (1 << 0)
215 #define DWC3_DCFG_LOWSPEED (2 << 0)
216 #define DWC3_DCFG_FULLSPEED1 (3 << 0)
218 #define DWC3_DCFG_LPM_CAP (1 << 22)
220 /* Device Control Register */
221 #define DWC3_DCTL_RUN_STOP (1 << 31)
222 #define DWC3_DCTL_CSFTRST (1 << 30)
223 #define DWC3_DCTL_LSFTRST (1 << 29)
225 #define DWC3_DCTL_HIRD_THRES_MASK (0x1f << 24)
226 #define DWC3_DCTL_HIRD_THRES(n) ((n) << 24)
228 #define DWC3_DCTL_APPL1RES (1 << 23)
230 /* These apply for core versions 1.87a and earlier */
231 #define DWC3_DCTL_TRGTULST_MASK (0x0f << 17)
232 #define DWC3_DCTL_TRGTULST(n) ((n) << 17)
233 #define DWC3_DCTL_TRGTULST_U2 (DWC3_DCTL_TRGTULST(2))
234 #define DWC3_DCTL_TRGTULST_U3 (DWC3_DCTL_TRGTULST(3))
235 #define DWC3_DCTL_TRGTULST_SS_DIS (DWC3_DCTL_TRGTULST(4))
236 #define DWC3_DCTL_TRGTULST_RX_DET (DWC3_DCTL_TRGTULST(5))
237 #define DWC3_DCTL_TRGTULST_SS_INACT (DWC3_DCTL_TRGTULST(6))
239 /* These apply for core versions 1.94a and later */
240 #define DWC3_DCTL_KEEP_CONNECT (1 << 19)
241 #define DWC3_DCTL_L1_HIBER_EN (1 << 18)
242 #define DWC3_DCTL_CRS (1 << 17)
243 #define DWC3_DCTL_CSS (1 << 16)
245 #define DWC3_DCTL_INITU2ENA (1 << 12)
246 #define DWC3_DCTL_ACCEPTU2ENA (1 << 11)
247 #define DWC3_DCTL_INITU1ENA (1 << 10)
248 #define DWC3_DCTL_ACCEPTU1ENA (1 << 9)
249 #define DWC3_DCTL_TSTCTRL_MASK (0xf << 1)
251 #define DWC3_DCTL_ULSTCHNGREQ_MASK (0x0f << 5)
252 #define DWC3_DCTL_ULSTCHNGREQ(n) (((n) << 5) & DWC3_DCTL_ULSTCHNGREQ_MASK)
254 #define DWC3_DCTL_ULSTCHNG_NO_ACTION (DWC3_DCTL_ULSTCHNGREQ(0))
255 #define DWC3_DCTL_ULSTCHNG_SS_DISABLED (DWC3_DCTL_ULSTCHNGREQ(4))
256 #define DWC3_DCTL_ULSTCHNG_RX_DETECT (DWC3_DCTL_ULSTCHNGREQ(5))
257 #define DWC3_DCTL_ULSTCHNG_SS_INACTIVE (DWC3_DCTL_ULSTCHNGREQ(6))
258 #define DWC3_DCTL_ULSTCHNG_RECOVERY (DWC3_DCTL_ULSTCHNGREQ(8))
259 #define DWC3_DCTL_ULSTCHNG_COMPLIANCE (DWC3_DCTL_ULSTCHNGREQ(10))
260 #define DWC3_DCTL_ULSTCHNG_LOOPBACK (DWC3_DCTL_ULSTCHNGREQ(11))
262 /* Device Event Enable Register */
263 #define DWC3_DEVTEN_VNDRDEVTSTRCVEDEN (1 << 12)
264 #define DWC3_DEVTEN_EVNTOVERFLOWEN (1 << 11)
265 #define DWC3_DEVTEN_CMDCMPLTEN (1 << 10)
266 #define DWC3_DEVTEN_ERRTICERREN (1 << 9)
267 #define DWC3_DEVTEN_SOFEN (1 << 7)
268 #define DWC3_DEVTEN_EOPFEN (1 << 6)
269 #define DWC3_DEVTEN_HIBERNATIONREQEVTEN (1 << 5)
270 #define DWC3_DEVTEN_WKUPEVTEN (1 << 4)
271 #define DWC3_DEVTEN_ULSTCNGEN (1 << 3)
272 #define DWC3_DEVTEN_CONNECTDONEEN (1 << 2)
273 #define DWC3_DEVTEN_USBRSTEN (1 << 1)
274 #define DWC3_DEVTEN_DISCONNEVTEN (1 << 0)
276 /* Device Status Register */
277 #define DWC3_DSTS_DCNRD (1 << 29)
279 /* This applies for core versions 1.87a and earlier */
280 #define DWC3_DSTS_PWRUPREQ (1 << 24)
282 /* These apply for core versions 1.94a and later */
283 #define DWC3_DSTS_RSS (1 << 25)
284 #define DWC3_DSTS_SSS (1 << 24)
286 #define DWC3_DSTS_COREIDLE (1 << 23)
287 #define DWC3_DSTS_DEVCTRLHLT (1 << 22)
289 #define DWC3_DSTS_USBLNKST_MASK (0x0f << 18)
290 #define DWC3_DSTS_USBLNKST(n) (((n) & DWC3_DSTS_USBLNKST_MASK) >> 18)
292 #define DWC3_DSTS_RXFIFOEMPTY (1 << 17)
294 #define DWC3_DSTS_SOFFN_MASK (0x3fff << 3)
295 #define DWC3_DSTS_SOFFN(n) (((n) & DWC3_DSTS_SOFFN_MASK) >> 3)
297 #define DWC3_DSTS_CONNECTSPD (7 << 0)
299 #define DWC3_DSTS_SUPERSPEED (4 << 0)
300 #define DWC3_DSTS_HIGHSPEED (0 << 0)
301 #define DWC3_DSTS_FULLSPEED2 (1 << 0)
302 #define DWC3_DSTS_LOWSPEED (2 << 0)
303 #define DWC3_DSTS_FULLSPEED1 (3 << 0)
305 /* Device Generic Command Register */
306 #define DWC3_DGCMD_SET_LMP 0x01
307 #define DWC3_DGCMD_SET_PERIODIC_PAR 0x02
308 #define DWC3_DGCMD_XMIT_FUNCTION 0x03
310 /* These apply for core versions 1.94a and later */
311 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO 0x04
312 #define DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI 0x05
314 #define DWC3_DGCMD_SELECTED_FIFO_FLUSH 0x09
315 #define DWC3_DGCMD_ALL_FIFO_FLUSH 0x0a
316 #define DWC3_DGCMD_SET_ENDPOINT_NRDY 0x0c
317 #define DWC3_DGCMD_RUN_SOC_BUS_LOOPBACK 0x10
319 #define DWC3_DGCMD_STATUS(n) (((n) >> 15) & 1)
320 #define DWC3_DGCMD_CMDACT (1 << 10)
321 #define DWC3_DGCMD_CMDIOC (1 << 8)
323 /* Device Generic Command Parameter Register */
324 #define DWC3_DGCMDPAR_FORCE_LINKPM_ACCEPT (1 << 0)
325 #define DWC3_DGCMDPAR_FIFO_NUM(n) ((n) << 0)
326 #define DWC3_DGCMDPAR_RX_FIFO (0 << 5)
327 #define DWC3_DGCMDPAR_TX_FIFO (1 << 5)
328 #define DWC3_DGCMDPAR_LOOPBACK_DIS (0 << 0)
329 #define DWC3_DGCMDPAR_LOOPBACK_ENA (1 << 0)
331 /* Device Endpoint Command Register */
332 #define DWC3_DEPCMD_PARAM_SHIFT 16
333 #define DWC3_DEPCMD_PARAM(x) ((x) << DWC3_DEPCMD_PARAM_SHIFT)
334 #define DWC3_DEPCMD_GET_RSC_IDX(x) (((x) >> DWC3_DEPCMD_PARAM_SHIFT) & 0x7f)
335 #define DWC3_DEPCMD_STATUS(x) (((x) >> 15) & 1)
336 #define DWC3_DEPCMD_HIPRI_FORCERM (1 << 11)
337 #define DWC3_DEPCMD_CMDACT (1 << 10)
338 #define DWC3_DEPCMD_CMDIOC (1 << 8)
340 #define DWC3_DEPCMD_DEPSTARTCFG (0x09 << 0)
341 #define DWC3_DEPCMD_ENDTRANSFER (0x08 << 0)
342 #define DWC3_DEPCMD_UPDATETRANSFER (0x07 << 0)
343 #define DWC3_DEPCMD_STARTTRANSFER (0x06 << 0)
344 #define DWC3_DEPCMD_CLEARSTALL (0x05 << 0)
345 #define DWC3_DEPCMD_SETSTALL (0x04 << 0)
346 /* This applies for core versions 1.90a and earlier */
347 #define DWC3_DEPCMD_GETSEQNUMBER (0x03 << 0)
348 /* This applies for core versions 1.94a and later */
349 #define DWC3_DEPCMD_GETEPSTATE (0x03 << 0)
350 #define DWC3_DEPCMD_SETTRANSFRESOURCE (0x02 << 0)
351 #define DWC3_DEPCMD_SETEPCONFIG (0x01 << 0)
353 /* The EP number goes 0..31 so ep0 is always out and ep1 is always in */
354 #define DWC3_DALEPENA_EP(n) (1 << n)
356 #define DWC3_DEPCMD_TYPE_CONTROL 0
357 #define DWC3_DEPCMD_TYPE_ISOC 1
358 #define DWC3_DEPCMD_TYPE_BULK 2
359 #define DWC3_DEPCMD_TYPE_INTR 3
366 * struct dwc3_event_buffer - Software event buffer representation
367 * @list: a list of event buffers
369 * @length: size of this buffer
371 * @dwc: pointer to DWC controller
373 struct dwc3_event_buffer {
383 #define DWC3_EP_FLAG_STALLED (1 << 0)
384 #define DWC3_EP_FLAG_WEDGED (1 << 1)
386 #define DWC3_EP_DIRECTION_TX true
387 #define DWC3_EP_DIRECTION_RX false
389 #define DWC3_TRB_NUM 32
390 #define DWC3_TRB_MASK (DWC3_TRB_NUM - 1)
393 * struct dwc3_ep - device side endpoint representation
394 * @endpoint: usb endpoint
395 * @request_list: list of requests for this endpoint
396 * @req_queued: list of requests on this ep which have TRBs setup
397 * @trb_pool: array of transaction buffers
398 * @trb_pool_dma: dma address of @trb_pool
399 * @free_slot: next slot which is going to be used
400 * @busy_slot: first slot which is owned by HW
401 * @desc: usb_endpoint_descriptor pointer
402 * @dwc: pointer to DWC controller
403 * @flags: endpoint flags (wedged, stalled, ...)
404 * @current_trb: index of current used trb
405 * @number: endpoint number (1 - 15)
406 * @type: set to bmAttributes & USB_ENDPOINT_XFERTYPE_MASK
407 * @resource_index: Resource transfer index
408 * @current_uf: Current uf received through last event parameter
409 * @interval: the intervall on which the ISOC transfer is started
410 * @name: a human readable name e.g. ep1out-bulk
411 * @direction: true for TX, false for RX
412 * @stream_capable: true when streams are enabled
415 struct usb_ep endpoint;
416 struct list_head request_list;
417 struct list_head req_queued;
419 struct dwc3_trb *trb_pool;
420 dma_addr_t trb_pool_dma;
423 const struct usb_ss_ep_comp_descriptor *comp_desc;
427 #define DWC3_EP_ENABLED (1 << 0)
428 #define DWC3_EP_STALL (1 << 1)
429 #define DWC3_EP_WEDGE (1 << 2)
430 #define DWC3_EP_BUSY (1 << 4)
431 #define DWC3_EP_PENDING_REQUEST (1 << 5)
432 #define DWC3_EP_MISSED_ISOC (1 << 6)
434 /* This last one is specific to EP0 */
435 #define DWC3_EP0_DIR_IN (1 << 31)
437 unsigned current_trb;
447 unsigned direction:1;
448 unsigned stream_capable:1;
452 DWC3_PHY_UNKNOWN = 0,
458 DWC3_EP0_UNKNOWN = 0,
461 DWC3_EP0_NRDY_STATUS,
464 enum dwc3_ep0_state {
471 enum dwc3_link_state {
473 DWC3_LINK_STATE_U0 = 0x00, /* in HS, means ON */
474 DWC3_LINK_STATE_U1 = 0x01,
475 DWC3_LINK_STATE_U2 = 0x02, /* in HS, means SLEEP */
476 DWC3_LINK_STATE_U3 = 0x03, /* in HS, means SUSPEND */
477 DWC3_LINK_STATE_SS_DIS = 0x04,
478 DWC3_LINK_STATE_RX_DET = 0x05, /* in HS, means Early Suspend */
479 DWC3_LINK_STATE_SS_INACT = 0x06,
480 DWC3_LINK_STATE_POLL = 0x07,
481 DWC3_LINK_STATE_RECOV = 0x08,
482 DWC3_LINK_STATE_HRESET = 0x09,
483 DWC3_LINK_STATE_CMPLY = 0x0a,
484 DWC3_LINK_STATE_LPBK = 0x0b,
485 DWC3_LINK_STATE_RESET = 0x0e,
486 DWC3_LINK_STATE_RESUME = 0x0f,
487 DWC3_LINK_STATE_MASK = 0x0f,
490 enum dwc3_device_state {
493 DWC3_CONFIGURED_STATE,
496 /* TRB Length, PCM and Status */
497 #define DWC3_TRB_SIZE_MASK (0x00ffffff)
498 #define DWC3_TRB_SIZE_LENGTH(n) ((n) & DWC3_TRB_SIZE_MASK)
499 #define DWC3_TRB_SIZE_PCM1(n) (((n) & 0x03) << 24)
500 #define DWC3_TRB_SIZE_TRBSTS(n) (((n) & (0x0f << 28)) >> 28)
502 #define DWC3_TRBSTS_OK 0
503 #define DWC3_TRBSTS_MISSED_ISOC 1
504 #define DWC3_TRBSTS_SETUP_PENDING 2
505 #define DWC3_TRB_STS_XFER_IN_PROG 4
508 #define DWC3_TRB_CTRL_HWO (1 << 0)
509 #define DWC3_TRB_CTRL_LST (1 << 1)
510 #define DWC3_TRB_CTRL_CHN (1 << 2)
511 #define DWC3_TRB_CTRL_CSP (1 << 3)
512 #define DWC3_TRB_CTRL_TRBCTL(n) (((n) & 0x3f) << 4)
513 #define DWC3_TRB_CTRL_ISP_IMI (1 << 10)
514 #define DWC3_TRB_CTRL_IOC (1 << 11)
515 #define DWC3_TRB_CTRL_SID_SOFN(n) (((n) & 0xffff) << 14)
517 #define DWC3_TRBCTL_NORMAL DWC3_TRB_CTRL_TRBCTL(1)
518 #define DWC3_TRBCTL_CONTROL_SETUP DWC3_TRB_CTRL_TRBCTL(2)
519 #define DWC3_TRBCTL_CONTROL_STATUS2 DWC3_TRB_CTRL_TRBCTL(3)
520 #define DWC3_TRBCTL_CONTROL_STATUS3 DWC3_TRB_CTRL_TRBCTL(4)
521 #define DWC3_TRBCTL_CONTROL_DATA DWC3_TRB_CTRL_TRBCTL(5)
522 #define DWC3_TRBCTL_ISOCHRONOUS_FIRST DWC3_TRB_CTRL_TRBCTL(6)
523 #define DWC3_TRBCTL_ISOCHRONOUS DWC3_TRB_CTRL_TRBCTL(7)
524 #define DWC3_TRBCTL_LINK_TRB DWC3_TRB_CTRL_TRBCTL(8)
527 * struct dwc3_trb - transfer request block (hw format)
541 * dwc3_hwparams - copy of HWPARAMS registers
542 * @hwparams0 - GHWPARAMS0
543 * @hwparams1 - GHWPARAMS1
544 * @hwparams2 - GHWPARAMS2
545 * @hwparams3 - GHWPARAMS3
546 * @hwparams4 - GHWPARAMS4
547 * @hwparams5 - GHWPARAMS5
548 * @hwparams6 - GHWPARAMS6
549 * @hwparams7 - GHWPARAMS7
550 * @hwparams8 - GHWPARAMS8
552 struct dwc3_hwparams {
565 #define DWC3_MODE(n) ((n) & 0x7)
567 #define DWC3_MODE_DEVICE 0
568 #define DWC3_MODE_HOST 1
569 #define DWC3_MODE_DRD 2
570 #define DWC3_MODE_HUB 3
572 #define DWC3_MDWIDTH(n) (((n) & 0xff00) >> 8)
575 #define DWC3_NUM_INT(n) (((n) & (0x3f << 15)) >> 15)
578 #define DWC3_RAM1_DEPTH(n) ((n) & 0xffff)
580 struct dwc3_request {
581 struct usb_request request;
582 struct list_head list;
586 struct dwc3_trb *trb;
589 unsigned direction:1;
595 * struct dwc3_scratchpad_array - hibernation scratchpad array
596 * (format defined by hw)
598 struct dwc3_scratchpad_array {
599 __le64 dma_adr[DWC3_MAX_HIBER_SCRATCHBUFS];
603 * struct dwc3 - representation of our controller
604 * @ctrl_req: usb control request which is used for ep0
605 * @ep0_trb: trb which is used for the ctrl_req
606 * @ep0_bounce: bounce buffer for ep0
607 * @setup_buf: used while precessing STD USB requests
608 * @ctrl_req_addr: dma address of ctrl_req
609 * @ep0_trb: dma address of ep0_trb
610 * @ep0_usb_req: dummy req used while handling STD USB requests
611 * @ep0_bounce_addr: dma address of ep0_bounce
612 * @lock: for synchronizing
613 * @dev: pointer to our struct device
614 * @xhci: pointer to our xHCI child
615 * @event_buffer_list: a list of event buffers
616 * @gadget: device side representation of the peripheral controller
617 * @gadget_driver: pointer to the gadget driver
618 * @regs: base address for our registers
619 * @regs_size: address space size
621 * @num_event_buffers: calculated number of event buffers
622 * @u1u2: only used on revisions <1.83a for workaround
623 * @maximum_speed: maximum speed requested (mainly for testing purposes)
624 * @revision: revision register contents
625 * @mode: mode of operation
626 * @usb2_phy: pointer to USB2 PHY
627 * @usb3_phy: pointer to USB3 PHY
628 * @is_selfpowered: true when we are selfpowered
629 * @three_stage_setup: set if we perform a three phase setup
630 * @ep0_bounced: true when we used bounce buffer
631 * @ep0_expect_in: true when we expect a DATA IN transfer
632 * @start_config_issued: true when StartConfig command has been issued
633 * @setup_packet_pending: true when there's a Setup Packet in FIFO. Workaround
634 * @needs_fifo_resize: not all users might want fifo resizing, flag it
635 * @resize_fifos: tells us it's ok to reconfigure our TxFIFO sizes.
636 * @isoch_delay: wValue from Set Isochronous Delay request;
637 * @u2sel: parameter from Set SEL request.
638 * @u2pel: parameter from Set SEL request.
639 * @u1sel: parameter from Set SEL request.
640 * @u1pel: parameter from Set SEL request.
641 * @ep0_next_event: hold the next expected event
642 * @ep0state: state of endpoint zero
643 * @link_state: link state
644 * @speed: device speed (super, high, full, low)
645 * @mem: points to start of memory which is used for this struct.
646 * @hwparams: copy of hwparams registers
647 * @root: debugfs root folder pointer
650 struct usb_ctrlrequest *ctrl_req;
651 struct dwc3_trb *ep0_trb;
654 dma_addr_t ctrl_req_addr;
655 dma_addr_t ep0_trb_addr;
656 dma_addr_t ep0_bounce_addr;
657 struct dwc3_request ep0_usb_req;
662 struct platform_device *xhci;
663 struct resource xhci_resources[DWC3_XHCI_RESOURCES_NUM];
665 struct dwc3_event_buffer **ev_buffs;
666 struct dwc3_ep *eps[DWC3_ENDPOINTS_NUM];
668 struct usb_gadget gadget;
669 struct usb_gadget_driver *gadget_driver;
671 struct usb_phy *usb2_phy;
672 struct usb_phy *usb3_phy;
677 u32 num_event_buffers;
683 #define DWC3_REVISION_173A 0x5533173a
684 #define DWC3_REVISION_175A 0x5533175a
685 #define DWC3_REVISION_180A 0x5533180a
686 #define DWC3_REVISION_183A 0x5533183a
687 #define DWC3_REVISION_185A 0x5533185a
688 #define DWC3_REVISION_187A 0x5533187a
689 #define DWC3_REVISION_188A 0x5533188a
690 #define DWC3_REVISION_190A 0x5533190a
691 #define DWC3_REVISION_194A 0x5533194a
692 #define DWC3_REVISION_200A 0x5533200a
693 #define DWC3_REVISION_202A 0x5533202a
694 #define DWC3_REVISION_210A 0x5533210a
695 #define DWC3_REVISION_220A 0x5533220a
697 unsigned is_selfpowered:1;
698 unsigned three_stage_setup:1;
699 unsigned ep0_bounced:1;
700 unsigned ep0_expect_in:1;
701 unsigned start_config_issued:1;
702 unsigned setup_packet_pending:1;
703 unsigned delayed_status:1;
704 unsigned needs_fifo_resize:1;
705 unsigned resize_fifos:1;
707 enum dwc3_ep0_next ep0_next_event;
708 enum dwc3_ep0_state ep0state;
709 enum dwc3_link_state link_state;
710 enum dwc3_device_state dev_state;
722 struct dwc3_hwparams hwparams;
729 /* -------------------------------------------------------------------------- */
731 /* -------------------------------------------------------------------------- */
733 struct dwc3_event_type {
739 #define DWC3_DEPEVT_XFERCOMPLETE 0x01
740 #define DWC3_DEPEVT_XFERINPROGRESS 0x02
741 #define DWC3_DEPEVT_XFERNOTREADY 0x03
742 #define DWC3_DEPEVT_RXTXFIFOEVT 0x04
743 #define DWC3_DEPEVT_STREAMEVT 0x06
744 #define DWC3_DEPEVT_EPCMDCMPLT 0x07
747 * struct dwc3_event_depvt - Device Endpoint Events
748 * @one_bit: indicates this is an endpoint event (not used)
749 * @endpoint_number: number of the endpoint
750 * @endpoint_event: The event we have:
752 * 0x01 - XferComplete
753 * 0x02 - XferInProgress
754 * 0x03 - XferNotReady
755 * 0x04 - RxTxFifoEvt (IN->Underrun, OUT->Overrun)
759 * @reserved11_10: Reserved, don't use.
760 * @status: Indicates the status of the event. Refer to databook for
762 * @parameters: Parameters of the current event. Refer to databook for
765 struct dwc3_event_depevt {
767 u32 endpoint_number:5;
768 u32 endpoint_event:4;
772 /* Within XferNotReady */
773 #define DEPEVT_STATUS_TRANSFER_ACTIVE (1 << 3)
775 /* Within XferComplete */
776 #define DEPEVT_STATUS_BUSERR (1 << 0)
777 #define DEPEVT_STATUS_SHORT (1 << 1)
778 #define DEPEVT_STATUS_IOC (1 << 2)
779 #define DEPEVT_STATUS_LST (1 << 3)
781 /* Stream event only */
782 #define DEPEVT_STREAMEVT_FOUND 1
783 #define DEPEVT_STREAMEVT_NOTFOUND 2
785 /* Control-only Status */
786 #define DEPEVT_STATUS_CONTROL_DATA 1
787 #define DEPEVT_STATUS_CONTROL_STATUS 2
793 * struct dwc3_event_devt - Device Events
794 * @one_bit: indicates this is a non-endpoint event (not used)
795 * @device_event: indicates it's a device event. Should read as 0x00
796 * @type: indicates the type of device event.
809 * 12 - VndrDevTstRcved
810 * @reserved15_12: Reserved, not used
811 * @event_info: Information about this event
812 * @reserved31_24: Reserved, not used
814 struct dwc3_event_devt {
824 * struct dwc3_event_gevt - Other Core Events
825 * @one_bit: indicates this is a non-endpoint event (not used)
826 * @device_event: indicates it's (0x03) Carkit or (0x04) I2C event.
827 * @phy_port_number: self-explanatory
828 * @reserved31_12: Reserved, not used.
830 struct dwc3_event_gevt {
833 u32 phy_port_number:4;
834 u32 reserved31_12:20;
838 * union dwc3_event - representation of Event Buffer contents
839 * @raw: raw 32-bit event
840 * @type: the type of the event
841 * @depevt: Device Endpoint Event
842 * @devt: Device Event
843 * @gevt: Global Event
847 struct dwc3_event_type type;
848 struct dwc3_event_depevt depevt;
849 struct dwc3_event_devt devt;
850 struct dwc3_event_gevt gevt;
854 * DWC3 Features to be used as Driver Data
857 #define DWC3_HAS_PERIPHERAL BIT(0)
858 #define DWC3_HAS_XHCI BIT(1)
859 #define DWC3_HAS_OTG BIT(3)
862 void dwc3_set_mode(struct dwc3 *dwc, u32 mode);
863 int dwc3_gadget_resize_tx_fifos(struct dwc3 *dwc);
865 int dwc3_host_init(struct dwc3 *dwc);
866 void dwc3_host_exit(struct dwc3 *dwc);
868 int dwc3_gadget_init(struct dwc3 *dwc);
869 void dwc3_gadget_exit(struct dwc3 *dwc);
871 #endif /* __DRIVERS_USB_DWC3_CORE_H */