drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "platform_data.h"
  45 #include "core.h"
  46 #include "gadget.h"
  47 #include "io.h"
  48
  49 #include "debug.h"
  50
  51 /* -------------------------------------------------------------------------- */
  52
  53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  54 {
  55         u32 reg;
  56
  57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61 }
  62
  63 /**
  64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  65  * @dwc: pointer to our context structure
  66  */
  67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  68 {
  69         u32             reg;
  70         int             ret;
  71
  72         /* Before Resetting PHY, put Core in Reset */
  73         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  74         reg |= DWC3_GCTL_CORESOFTRESET;
  75         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  76
  77         /* Assert USB3 PHY reset */
  78         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  79         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  80         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  81
  82         /* Assert USB2 PHY reset */
  83         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  84         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  85         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  86
  87         usb_phy_init(dwc->usb2_phy);
  88         usb_phy_init(dwc->usb3_phy);
  89         ret = phy_init(dwc->usb2_generic_phy);
  90         if (ret < 0)
  91                 return ret;
  92
  93         ret = phy_init(dwc->usb3_generic_phy);
  94         if (ret < 0) {
  95                 phy_exit(dwc->usb2_generic_phy);
  96                 return ret;
  97         }
  98         mdelay(100);
  99
 100         /* Clear USB3 PHY reset */
 101         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 102         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 103         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 104
 105         /* Clear USB2 PHY reset */
 106         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 107         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 108         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 109
 110         mdelay(100);
 111
 112         /* After PHYs are stable we can take Core out of reset state */
 113         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 114         reg &= ~DWC3_GCTL_CORESOFTRESET;
 115         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 116
 117         return 0;
 118 }
 119
 120 /**
 121  * dwc3_soft_reset - Issue soft reset
 122  * @dwc: Pointer to our controller context structure
 123  */
 124 int dwc3_soft_reset(struct dwc3 *dwc)
 125 {
 126         unsigned long timeout;
 127         u32 reg;
 128
 129         timeout = jiffies + msecs_to_jiffies(500);
 130         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 131         do {
 132                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 133                 if (!(reg & DWC3_DCTL_CSFTRST))
 134                         break;
 135
 136                 if (time_after(jiffies, timeout)) {
 137                         dev_err(dwc->dev, "Reset Timed Out\n");
 138                         return -ETIMEDOUT;
 139                 }
 140
 141                 cpu_relax();
 142         } while (true);
 143
 144         return 0;
 145 }
 146
 147 /*
 148  * dwc3_frame_length_adjustment - Adjusts frame length if required
 149  * @dwc3: Pointer to our controller context structure
 150  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 151  */
 152 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 153 {
 154         u32 reg;
 155         u32 dft;
 156
 157         if (dwc->revision < DWC3_REVISION_250A)
 158                 return;
 159
 160         if (fladj == 0)
 161                 return;
 162
 163         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 164         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 165         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 166             "request value same as default, ignoring\n")) {
 167                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 168                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 169                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 170         }
 171 }
 172
 173 /**
 174  * dwc3_free_one_event_buffer - Frees one event buffer
 175  * @dwc: Pointer to our controller context structure
 176  * @evt: Pointer to event buffer to be freed
 177  */
 178 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 179                 struct dwc3_event_buffer *evt)
 180 {
 181         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 182 }
 183
 184 /**
 185  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 186  * @dwc: Pointer to our controller context structure
 187  * @length: size of the event buffer
 188  *
 189  * Returns a pointer to the allocated event buffer structure on success
 190  * otherwise ERR_PTR(errno).
 191  */
 192 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 193                 unsigned length)
 194 {
 195         struct dwc3_event_buffer        *evt;
 196
 197         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 198         if (!evt)
 199                 return ERR_PTR(-ENOMEM);
 200
 201         evt->dwc        = dwc;
 202         evt->length     = length;
 203         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 204                         &evt->dma, GFP_KERNEL);
 205         if (!evt->buf)
 206                 return ERR_PTR(-ENOMEM);
 207
 208         return evt;
 209 }
 210
 211 /**
 212  * dwc3_free_event_buffers - frees all allocated event buffers
 213  * @dwc: Pointer to our controller context structure
 214  */
 215 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 216 {
 217         struct dwc3_event_buffer        *evt;
 218         int i;
 219
 220         for (i = 0; i < dwc->num_event_buffers; i++) {
 221                 evt = dwc->ev_buffs[i];
 222                 if (evt)
 223                         dwc3_free_one_event_buffer(dwc, evt);
 224         }
 225 }
 226
 227 /**
 228  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 229  * @dwc: pointer to our controller context structure
 230  * @length: size of event buffer
 231  *
 232  * Returns 0 on success otherwise negative errno. In the error case, dwc
 233  * may contain some buffers allocated but not all which were requested.
 234  */
 235 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 236 {
 237         int                     num;
 238         int                     i;
 239
 240         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 241         dwc->num_event_buffers = num;
 242
 243         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 244                         GFP_KERNEL);
 245         if (!dwc->ev_buffs)
 246                 return -ENOMEM;
 247
 248         for (i = 0; i < num; i++) {
 249                 struct dwc3_event_buffer        *evt;
 250
 251                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 252                 if (IS_ERR(evt)) {
 253                         dev_err(dwc->dev, "can't allocate event buffer\n");
 254                         return PTR_ERR(evt);
 255                 }
 256                 dwc->ev_buffs[i] = evt;
 257         }
 258
 259         return 0;
 260 }
 261
 262 /**
 263  * dwc3_event_buffers_setup - setup our allocated event buffers
 264  * @dwc: pointer to our controller context structure
 265  *
 266  * Returns 0 on success otherwise negative errno.
 267  */
 268 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 269 {
 270         struct dwc3_event_buffer        *evt;
 271         int                             n;
 272
 273         for (n = 0; n < dwc->num_event_buffers; n++) {
 274                 evt = dwc->ev_buffs[n];
 275                 dwc3_trace(trace_dwc3_core,
 276                                 "Event buf %p dma %08llx length %d\n",
 277                                 evt->buf, (unsigned long long) evt->dma,
 278                                 evt->length);
 279
 280                 evt->lpos = 0;
 281
 282                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 283                                 lower_32_bits(evt->dma));
 284                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 285                                 upper_32_bits(evt->dma));
 286                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 287                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 288                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 289         }
 290
 291         return 0;
 292 }
 293
 294 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 295 {
 296         struct dwc3_event_buffer        *evt;
 297         int                             n;
 298
 299         for (n = 0; n < dwc->num_event_buffers; n++) {
 300                 evt = dwc->ev_buffs[n];
 301
 302                 evt->lpos = 0;
 303
 304                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 305                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 306                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 307                                 | DWC3_GEVNTSIZ_SIZE(0));
 308                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 309         }
 310 }
 311
 312 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 313 {
 314         if (!dwc->has_hibernation)
 315                 return 0;
 316
 317         if (!dwc->nr_scratch)
 318                 return 0;
 319
 320         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 321                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 322         if (!dwc->scratchbuf)
 323                 return -ENOMEM;
 324
 325         return 0;
 326 }
 327
 328 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 329 {
 330         dma_addr_t scratch_addr;
 331         u32 param;
 332         int ret;
 333
 334         if (!dwc->has_hibernation)
 335                 return 0;
 336
 337         if (!dwc->nr_scratch)
 338                 return 0;
 339
 340          /* should never fall here */
 341         if (!WARN_ON(dwc->scratchbuf))
 342                 return 0;
 343
 344         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 345                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 346                         DMA_BIDIRECTIONAL);
 347         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 348                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 349                 ret = -EFAULT;
 350                 goto err0;
 351         }
 352
 353         dwc->scratch_addr = scratch_addr;
 354
 355         param = lower_32_bits(scratch_addr);
 356
 357         ret = dwc3_send_gadget_generic_command(dwc,
 358                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 359         if (ret < 0)
 360                 goto err1;
 361
 362         param = upper_32_bits(scratch_addr);
 363
 364         ret = dwc3_send_gadget_generic_command(dwc,
 365                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 366         if (ret < 0)
 367                 goto err1;
 368
 369         return 0;
 370
 371 err1:
 372         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 373                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 374
 375 err0:
 376         return ret;
 377 }
 378
 379 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 380 {
 381         if (!dwc->has_hibernation)
 382                 return;
 383
 384         if (!dwc->nr_scratch)
 385                 return;
 386
 387          /* should never fall here */
 388         if (!WARN_ON(dwc->scratchbuf))
 389                 return;
 390
 391         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 392                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 393         kfree(dwc->scratchbuf);
 394 }
 395
 396 static void dwc3_core_num_eps(struct dwc3 *dwc)
 397 {
 398         struct dwc3_hwparams    *parms = &dwc->hwparams;
 399
 400         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 401         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 402
 403         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 404                         dwc->num_in_eps, dwc->num_out_eps);
 405 }
 406
 407 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 408 {
 409         struct dwc3_hwparams    *parms = &dwc->hwparams;
 410
 411         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 412         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 413         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 414         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 415         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 416         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 417         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 418         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 419         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 420 }
 421
 422 /**
 423  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 424  * @dwc: Pointer to our controller context structure
 425  *
 426  * Returns 0 on success. The USB PHY interfaces are configured but not
 427  * initialized. The PHY interfaces and the PHYs get initialized together with
 428  * the core in dwc3_core_init.
 429  */
 430 static int dwc3_phy_setup(struct dwc3 *dwc)
 431 {
 432         u32 reg;
 433         u32 usbtrdtim;
 434         int ret;
 435
 436         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 437
 438         /*
 439          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 440          * to '0' during coreConsultant configuration. So default value
 441          * will be '0' when the core is reset. Application needs to set it
 442          * to '1' after the core initialization is completed.
 443          */
 444         if (dwc->revision > DWC3_REVISION_194A)
 445                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 446
 447         if (dwc->u2ss_inp3_quirk)
 448                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 449
 450         if (dwc->req_p1p2p3_quirk)
 451                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 452
 453         if (dwc->del_p1p2p3_quirk)
 454                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 455
 456         if (dwc->del_phy_power_chg_quirk)
 457                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 458
 459         if (dwc->lfps_filter_quirk)
 460                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 461
 462         if (dwc->rx_detect_poll_quirk)
 463                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 464
 465         if (dwc->tx_de_emphasis_quirk)
 466                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 467
 468         if (dwc->dis_u3_susphy_quirk)
 469                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 470
 471         if (dwc->dis_del_phy_power_chg_quirk)
 472                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 473
 474         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 475
 476         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 477
 478         /* Select the HS PHY interface */
 479         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 480         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 481                 if (dwc->hsphy_interface &&
 482                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 483                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 484                         break;
 485                 } else if (dwc->hsphy_interface &&
 486                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 487                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 488                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 489                 } else {
 490                         /* Relying on default value. */
 491                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 492                                 break;
 493                 }
 494                 /* FALLTHROUGH */
 495         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 496                 /* Making sure the interface and PHY are operational */
 497                 ret = dwc3_soft_reset(dwc);
 498                 if (ret)
 499                         return ret;
 500
 501                 udelay(1);
 502
 503                 ret = dwc3_ulpi_init(dwc);
 504                 if (ret)
 505                         return ret;
 506                 /* FALLTHROUGH */
 507         default:
 508                 break;
 509         }
 510
 511         /*
 512          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 513          * '0' during coreConsultant configuration. So default value will
 514          * be '0' when the core is reset. Application needs to set it to
 515          * '1' after the core initialization is completed.
 516          */
 517         if (dwc->revision > DWC3_REVISION_194A)
 518                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 519
 520         if (dwc->dis_u2_susphy_quirk)
 521                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 522
 523         if (dwc->dis_enblslpm_quirk)
 524                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 525
 526         if (dwc->dis_u2_freeclk_exists_quirk)
 527                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 528
 529         if (dwc->phyif_utmi_16_bits)
 530                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
 531
 532         usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
 533                     USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
 534
 535         reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 536         reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
 537
 538         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 539
 540         return 0;
 541 }
 542
 543 /**
 544  * dwc3_core_init - Low-level initialization of DWC3 Core
 545  * @dwc: Pointer to our controller context structure
 546  *
 547  * Returns 0 on success otherwise negative errno.
 548  */
 549 static int dwc3_core_init(struct dwc3 *dwc)
 550 {
 551         u32                     hwparams4 = dwc->hwparams.hwparams4;
 552         u32                     reg;
 553         int                     ret;
 554
 555         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 556         /* This should read as U3 followed by revision number */
 557         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 558                 /* Detected DWC_usb3 IP */
 559                 dwc->revision = reg;
 560         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 561                 /* Detected DWC_usb31 IP */
 562                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 563                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 564         } else {
 565                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 566                 ret = -ENODEV;
 567                 goto err0;
 568         }
 569
 570         /*
 571          * Write Linux Version Code to our GUID register so it's easy to figure
 572          * out which kernel version a bug was found.
 573          */
 574         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 575
 576         /* Handle USB2.0-only core configuration */
 577         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 578                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 579                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 580                         dwc->maximum_speed = USB_SPEED_HIGH;
 581         }
 582
 583         /* issue device SoftReset too */
 584         ret = dwc3_soft_reset(dwc);
 585         if (ret)
 586                 goto err0;
 587
 588         ret = dwc3_core_soft_reset(dwc);
 589         if (ret)
 590                 goto err0;
 591
 592         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 593         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 594
 595         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 596         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 597                 /**
 598                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 599                  * issue which would cause xHCI compliance tests to fail.
 600                  *
 601                  * Because of that we cannot enable clock gating on such
 602                  * configurations.
 603                  *
 604                  * Refers to:
 605                  *
 606                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 607                  * SOF/ITP Mode Used
 608                  */
 609                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 610                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 611                                 (dwc->revision >= DWC3_REVISION_210A &&
 612                                 dwc->revision <= DWC3_REVISION_250A))
 613                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 614                 else
 615                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 616                 break;
 617         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 618                 /* enable hibernation here */
 619                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 620
 621                 /*
 622                  * REVISIT Enabling this bit so that host-mode hibernation
 623                  * will work. Device-mode hibernation is not yet implemented.
 624                  */
 625                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 626                 break;
 627         default:
 628                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 629         }
 630
 631         /* check if current dwc3 is on simulation board */
 632         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 633                 dwc3_trace(trace_dwc3_core,
 634                                 "running on FPGA platform\n");
 635                 dwc->is_fpga = true;
 636         }
 637
 638         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 639                         "disable_scramble cannot be used on non-FPGA builds\n");
 640
 641         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 642                 reg |= DWC3_GCTL_DISSCRAMBLE;
 643         else
 644                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 645
 646         if (dwc->u2exit_lfps_quirk)
 647                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 648
 649         /*
 650          * WORKAROUND: DWC3 revisions <1.90a have a bug
 651          * where the device can fail to connect at SuperSpeed
 652          * and falls back to high-speed mode which causes
 653          * the device to enter a Connect/Disconnect loop
 654          */
 655         if (dwc->revision < DWC3_REVISION_190A)
 656                 reg |= DWC3_GCTL_U2RSTECN;
 657
 658         dwc3_core_num_eps(dwc);
 659
 660         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 661
 662         ret = dwc3_alloc_scratch_buffers(dwc);
 663         if (ret)
 664                 goto err1;
 665
 666         ret = dwc3_setup_scratch_buffers(dwc);
 667         if (ret)
 668                 goto err2;
 669
 670         return 0;
 671
 672 err2:
 673         dwc3_free_scratch_buffers(dwc);
 674
 675 err1:
 676         usb_phy_shutdown(dwc->usb2_phy);
 677         usb_phy_shutdown(dwc->usb3_phy);
 678         phy_exit(dwc->usb2_generic_phy);
 679         phy_exit(dwc->usb3_generic_phy);
 680
 681 err0:
 682         return ret;
 683 }
 684
 685 static void dwc3_core_exit(struct dwc3 *dwc)
 686 {
 687         dwc3_free_scratch_buffers(dwc);
 688         usb_phy_shutdown(dwc->usb2_phy);
 689         usb_phy_shutdown(dwc->usb3_phy);
 690         phy_exit(dwc->usb2_generic_phy);
 691         phy_exit(dwc->usb3_generic_phy);
 692 }
 693
 694 static int dwc3_core_get_phy(struct dwc3 *dwc)
 695 {
 696         struct device           *dev = dwc->dev;
 697         struct device_node      *node = dev->of_node;
 698         int ret;
 699
 700         if (node) {
 701                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 702                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 703         } else {
 704                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 705                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 706         }
 707
 708         if (IS_ERR(dwc->usb2_phy)) {
 709                 ret = PTR_ERR(dwc->usb2_phy);
 710                 if (ret == -ENXIO || ret == -ENODEV) {
 711                         dwc->usb2_phy = NULL;
 712                 } else if (ret == -EPROBE_DEFER) {
 713                         return ret;
 714                 } else {
 715                         dev_err(dev, "no usb2 phy configured\n");
 716                         return ret;
 717                 }
 718         }
 719
 720         if (IS_ERR(dwc->usb3_phy)) {
 721                 ret = PTR_ERR(dwc->usb3_phy);
 722                 if (ret == -ENXIO || ret == -ENODEV) {
 723                         dwc->usb3_phy = NULL;
 724                 } else if (ret == -EPROBE_DEFER) {
 725                         return ret;
 726                 } else {
 727                         dev_err(dev, "no usb3 phy configured\n");
 728                         return ret;
 729                 }
 730         }
 731
 732         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 733         if (IS_ERR(dwc->usb2_generic_phy)) {
 734                 ret = PTR_ERR(dwc->usb2_generic_phy);
 735                 if (ret == -ENOSYS || ret == -ENODEV) {
 736                         dwc->usb2_generic_phy = NULL;
 737                 } else if (ret == -EPROBE_DEFER) {
 738                         return ret;
 739                 } else {
 740                         dev_err(dev, "no usb2 phy configured\n");
 741                         return ret;
 742                 }
 743         }
 744
 745         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 746         if (IS_ERR(dwc->usb3_generic_phy)) {
 747                 ret = PTR_ERR(dwc->usb3_generic_phy);
 748                 if (ret == -ENOSYS || ret == -ENODEV) {
 749                         dwc->usb3_generic_phy = NULL;
 750                 } else if (ret == -EPROBE_DEFER) {
 751                         return ret;
 752                 } else {
 753                         dev_err(dev, "no usb3 phy configured\n");
 754                         return ret;
 755                 }
 756         }
 757
 758         return 0;
 759 }
 760
 761 static int dwc3_core_init_mode(struct dwc3 *dwc)
 762 {
 763         struct device *dev = dwc->dev;
 764         int ret;
 765
 766         switch (dwc->dr_mode) {
 767         case USB_DR_MODE_PERIPHERAL:
 768                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 769                 ret = dwc3_gadget_init(dwc);
 770                 if (ret) {
 771                         dev_err(dev, "failed to initialize gadget\n");
 772                         return ret;
 773                 }
 774                 break;
 775         case USB_DR_MODE_HOST:
 776                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 777                 ret = dwc3_host_init(dwc);
 778                 if (ret) {
 779                         dev_err(dev, "failed to initialize host\n");
 780                         return ret;
 781                 }
 782                 break;
 783         case USB_DR_MODE_OTG:
 784                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 785                 ret = dwc3_host_init(dwc);
 786                 if (ret) {
 787                         dev_err(dev, "failed to initialize host\n");
 788                         return ret;
 789                 }
 790
 791                 ret = dwc3_gadget_init(dwc);
 792                 if (ret) {
 793                         dev_err(dev, "failed to initialize gadget\n");
 794                         return ret;
 795                 }
 796                 break;
 797         default:
 798                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 799                 return -EINVAL;
 800         }
 801
 802         return 0;
 803 }
 804
 805 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 806 {
 807         switch (dwc->dr_mode) {
 808         case USB_DR_MODE_PERIPHERAL:
 809                 dwc3_gadget_exit(dwc);
 810                 break;
 811         case USB_DR_MODE_HOST:
 812                 dwc3_host_exit(dwc);
 813                 break;
 814         case USB_DR_MODE_OTG:
 815                 dwc3_host_exit(dwc);
 816                 dwc3_gadget_exit(dwc);
 817                 break;
 818         default:
 819                 /* do nothing */
 820                 break;
 821         }
 822 }
 823
 824 /* Returns true if the controller is capable of DRD. */
 825 bool dwc3_hw_is_drd(struct dwc3 *dwc)
 826 {
 827         u32 op_mode = DWC3_GHWPARAMS0_USB3_MODE(dwc->hwparams.hwparams0);
 828
 829         return (op_mode == DWC3_GHWPARAMS0_USB3_DRD);
 830 }
 831
 832 bool dwc3_force_mode(struct dwc3 *dwc, u32 mode)
 833 {
 834         u32                     reg;
 835         unsigned long           flags;
 836         struct usb_hcd          *hcd;
 837
 838         /*
 839          * Force mode has no effect if the hardware is not drd mode.
 840          */
 841         if (!dwc3_hw_is_drd(dwc))
 842                 return false;
 843         /*
 844          * If dr_mode is either peripheral or host only, there is no
 845          * need to ever force the mode to the opposite mode.
 846          */
 847         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_DEVICE &&
 848                     dwc->dr_mode == USB_DR_MODE_HOST))
 849                 return false;
 850
 851         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_HOST &&
 852                     dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 853                 return false;
 854
 855         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 856         if (DWC3_GCTL_PRTCAP(reg) == mode)
 857                 return false;
 858
 859         hcd = dev_get_drvdata(&dwc->xhci->dev);
 860
 861         switch (mode) {
 862         case DWC3_GCTL_PRTCAP_DEVICE:
 863                 if (hcd->state != HC_STATE_HALT) {
 864                         usb_remove_hcd(hcd->shared_hcd);
 865                         usb_remove_hcd(hcd);
 866                 }
 867
 868                 spin_lock_irqsave(&dwc->lock, flags);
 869                 dwc3_set_mode(dwc, mode);
 870                 dwc3_gadget_restart(dwc, true);
 871                 spin_unlock_irqrestore(&dwc->lock, flags);
 872
 873                 break;
 874         case DWC3_GCTL_PRTCAP_HOST:
 875                 spin_lock_irqsave(&dwc->lock, flags);
 876                 dwc3_gadget_restart(dwc, false);
 877                 dwc3_set_mode(dwc, mode);
 878                 spin_unlock_irqrestore(&dwc->lock, flags);
 879
 880                 if (hcd->state == HC_STATE_HALT) {
 881                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 882                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 883                 }
 884
 885                 break;
 886         default:
 887                 /* do nothing  */
 888                 break;
 889         }
 890
 891         return true;
 892 }
 893
 894 #define DWC3_ALIGN_MASK         (16 - 1)
 895
 896 static int dwc3_probe(struct platform_device *pdev)
 897 {
 898         struct device           *dev = &pdev->dev;
 899         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 900         struct resource         *res;
 901         struct dwc3             *dwc;
 902         u8                      lpm_nyet_threshold;
 903         u8                      tx_de_emphasis;
 904         u8                      hird_threshold;
 905         u32                     fladj = 0;
 906
 907         int                     ret;
 908
 909         void __iomem            *regs;
 910         void                    *mem;
 911
 912         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 913         if (!mem)
 914                 return -ENOMEM;
 915
 916         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 917         dwc->mem = mem;
 918         dwc->dev = dev;
 919
 920         /* Try to set 64-bit DMA first */
 921         if (!pdev->dev.dma_mask)
 922                 /* Platform did not initialize dma_mask */
 923                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 924                                                    DMA_BIT_MASK(64));
 925         else
 926                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 927
 928         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 929         if (ret) {
 930                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 931                 if (ret)
 932                         return ret;
 933         }
 934
 935         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 936         if (!res) {
 937                 dev_err(dev, "missing IRQ\n");
 938                 return -ENODEV;
 939         }
 940         dwc->xhci_resources[1].start = res->start;
 941         dwc->xhci_resources[1].end = res->end;
 942         dwc->xhci_resources[1].flags = res->flags;
 943         dwc->xhci_resources[1].name = res->name;
 944
 945         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 946         if (!res) {
 947                 dev_err(dev, "missing memory resource\n");
 948                 return -ENODEV;
 949         }
 950
 951         dwc->xhci_resources[0].start = res->start;
 952         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 953                                         DWC3_XHCI_REGS_END;
 954         dwc->xhci_resources[0].flags = res->flags;
 955         dwc->xhci_resources[0].name = res->name;
 956
 957         res->start += DWC3_GLOBALS_REGS_START;
 958
 959         /*
 960          * Request memory region but exclude xHCI regs,
 961          * since it will be requested by the xhci-plat driver.
 962          */
 963         regs = devm_ioremap_resource(dev, res);
 964         if (IS_ERR(regs)) {
 965                 ret = PTR_ERR(regs);
 966                 goto err0;
 967         }
 968
 969         dwc->regs       = regs;
 970         dwc->regs_size  = resource_size(res);
 971
 972         /* default to highest possible threshold */
 973         lpm_nyet_threshold = 0xff;
 974
 975         /* default to -3.5dB de-emphasis */
 976         tx_de_emphasis = 1;
 977
 978         /*
 979          * default to assert utmi_sleep_n and use maximum allowed HIRD
 980          * threshold value of 0b1100
 981          */
 982         hird_threshold = 12;
 983
 984         dwc->maximum_speed = usb_get_maximum_speed(dev);
 985         dwc->dr_mode = usb_get_dr_mode(dev);
 986
 987         dwc->has_lpm_erratum = device_property_read_bool(dev,
 988                                 "snps,has-lpm-erratum");
 989         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 990                                 &lpm_nyet_threshold);
 991         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 992                                 "snps,is-utmi-l1-suspend");
 993         device_property_read_u8(dev, "snps,hird-threshold",
 994                                 &hird_threshold);
 995         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 996                                 "snps,usb3_lpm_capable");
 997
 998         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 999                                 "snps,disable_scramble_quirk");
1000         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1001                                 "snps,u2exit_lfps_quirk");
1002         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1003                                 "snps,u2ss_inp3_quirk");
1004         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1005                                 "snps,req_p1p2p3_quirk");
1006         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1007                                 "snps,del_p1p2p3_quirk");
1008         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1009                                 "snps,del_phy_power_chg_quirk");
1010         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1011                                 "snps,lfps_filter_quirk");
1012         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1013                                 "snps,rx_detect_poll_quirk");
1014         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1015                                 "snps,dis_u3_susphy_quirk");
1016         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1017                                 "snps,dis_u2_susphy_quirk");
1018         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1019                                 "snps,dis_enblslpm_quirk");
1020         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1021                                 "snps,dis_u2_freeclk_exists_quirk");
1022         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1023                                 "snps,dis_del_phy_power_chg_quirk");
1024         dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
1025                                 "snps,xhci_slow_suspend_quirk");
1026         dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
1027                                 "snps,phyif_utmi_16_bits");
1028
1029         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1030                                 "snps,tx_de_emphasis_quirk");
1031         device_property_read_u8(dev, "snps,tx_de_emphasis",
1032                                 &tx_de_emphasis);
1033         device_property_read_string(dev, "snps,hsphy_interface",
1034                                     &dwc->hsphy_interface);
1035         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1036                                  &fladj);
1037
1038         if (pdata) {
1039                 dwc->maximum_speed = pdata->maximum_speed;
1040                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1041                 if (pdata->lpm_nyet_threshold)
1042                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1043                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1044                 if (pdata->hird_threshold)
1045                         hird_threshold = pdata->hird_threshold;
1046
1047                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1048                 dwc->dr_mode = pdata->dr_mode;
1049
1050                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1051                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1052                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1053                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1054                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1055                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1056                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1057                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1058                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1059                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1060                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1061                 dwc->dis_u2_freeclk_exists_quirk =
1062                                         pdata->dis_u2_freeclk_exists_quirk;
1063                 dwc->dis_del_phy_power_chg_quirk =
1064                                         pdata->dis_del_phy_power_chg_quirk;
1065                 dwc->xhci_slow_suspend_quirk =
1066                                         pdata->xhci_slow_suspend_quirk;
1067                 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
1068
1069                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1070                 if (pdata->tx_de_emphasis)
1071                         tx_de_emphasis = pdata->tx_de_emphasis;
1072
1073                 dwc->hsphy_interface = pdata->hsphy_interface;
1074                 fladj = pdata->fladj_value;
1075         }
1076
1077         /* default to superspeed if no maximum_speed passed */
1078         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1079                 dwc->maximum_speed = USB_SPEED_SUPER;
1080
1081         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1082         dwc->tx_de_emphasis = tx_de_emphasis;
1083
1084         dwc->hird_threshold = hird_threshold
1085                 | (dwc->is_utmi_l1_suspend << 4);
1086
1087         platform_set_drvdata(pdev, dwc);
1088         dwc3_cache_hwparams(dwc);
1089
1090         ret = dwc3_phy_setup(dwc);
1091         if (ret)
1092                 goto err0;
1093
1094         ret = dwc3_core_get_phy(dwc);
1095         if (ret)
1096                 goto err0;
1097
1098         spin_lock_init(&dwc->lock);
1099
1100         if (!dev->dma_mask) {
1101                 dev->dma_mask = dev->parent->dma_mask;
1102                 dev->dma_parms = dev->parent->dma_parms;
1103                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1104         }
1105
1106         pm_runtime_enable(dev);
1107         pm_runtime_get_sync(dev);
1108         pm_runtime_forbid(dev);
1109
1110         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1111         if (ret) {
1112                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1113                 ret = -ENOMEM;
1114                 goto err1;
1115         }
1116
1117         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1118                 dwc->dr_mode = USB_DR_MODE_HOST;
1119         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1120                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1121
1122         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1123                 dwc->dr_mode = USB_DR_MODE_OTG;
1124
1125         ret = dwc3_core_init(dwc);
1126         if (ret) {
1127                 dev_err(dev, "failed to initialize core\n");
1128                 goto err1;
1129         }
1130
1131         /* Adjust Frame Length */
1132         dwc3_frame_length_adjustment(dwc, fladj);
1133
1134         usb_phy_set_suspend(dwc->usb2_phy, 0);
1135         usb_phy_set_suspend(dwc->usb3_phy, 0);
1136         ret = phy_power_on(dwc->usb2_generic_phy);
1137         if (ret < 0)
1138                 goto err2;
1139
1140         ret = phy_power_on(dwc->usb3_generic_phy);
1141         if (ret < 0)
1142                 goto err3;
1143
1144         ret = dwc3_event_buffers_setup(dwc);
1145         if (ret) {
1146                 dev_err(dwc->dev, "failed to setup event buffers\n");
1147                 goto err4;
1148         }
1149
1150         ret = dwc3_core_init_mode(dwc);
1151         if (ret)
1152                 goto err5;
1153
1154         ret = dwc3_debugfs_init(dwc);
1155         if (ret) {
1156                 dev_err(dev, "failed to initialize debugfs\n");
1157                 goto err6;
1158         }
1159
1160         pm_runtime_allow(dev);
1161
1162         return 0;
1163
1164 err6:
1165         dwc3_core_exit_mode(dwc);
1166
1167 err5:
1168         dwc3_event_buffers_cleanup(dwc);
1169
1170 err4:
1171         phy_power_off(dwc->usb3_generic_phy);
1172
1173 err3:
1174         phy_power_off(dwc->usb2_generic_phy);
1175
1176 err2:
1177         usb_phy_set_suspend(dwc->usb2_phy, 1);
1178         usb_phy_set_suspend(dwc->usb3_phy, 1);
1179         dwc3_core_exit(dwc);
1180
1181 err1:
1182         dwc3_free_event_buffers(dwc);
1183         dwc3_ulpi_exit(dwc);
1184
1185 err0:
1186         /*
1187          * restore res->start back to its original value so that, in case the
1188          * probe is deferred, we don't end up getting error in request the
1189          * memory region the next time probe is called.
1190          */
1191         res->start -= DWC3_GLOBALS_REGS_START;
1192
1193         return ret;
1194 }
1195
1196 static int dwc3_remove(struct platform_device *pdev)
1197 {
1198         struct dwc3     *dwc = platform_get_drvdata(pdev);
1199         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1200
1201         /*
1202          * restore res->start back to its original value so that, in case the
1203          * probe is deferred, we don't end up getting error in request the
1204          * memory region the next time probe is called.
1205          */
1206         res->start -= DWC3_GLOBALS_REGS_START;
1207
1208         dwc3_debugfs_exit(dwc);
1209         dwc3_core_exit_mode(dwc);
1210         dwc3_event_buffers_cleanup(dwc);
1211         dwc3_free_event_buffers(dwc);
1212
1213         usb_phy_set_suspend(dwc->usb2_phy, 1);
1214         usb_phy_set_suspend(dwc->usb3_phy, 1);
1215         phy_power_off(dwc->usb2_generic_phy);
1216         phy_power_off(dwc->usb3_generic_phy);
1217
1218         dwc3_core_exit(dwc);
1219         dwc3_ulpi_exit(dwc);
1220
1221         pm_runtime_put_sync(&pdev->dev);
1222         pm_runtime_disable(&pdev->dev);
1223
1224         return 0;
1225 }
1226
1227 #ifdef CONFIG_PM_SLEEP
1228 static int dwc3_suspend(struct device *dev)
1229 {
1230         struct dwc3     *dwc = dev_get_drvdata(dev);
1231         unsigned long   flags;
1232
1233         spin_lock_irqsave(&dwc->lock, flags);
1234
1235         switch (dwc->dr_mode) {
1236         case USB_DR_MODE_PERIPHERAL:
1237         case USB_DR_MODE_OTG:
1238                 dwc3_gadget_suspend(dwc);
1239                 /* FALLTHROUGH */
1240         case USB_DR_MODE_HOST:
1241         default:
1242                 dwc3_event_buffers_cleanup(dwc);
1243                 break;
1244         }
1245
1246         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1247         spin_unlock_irqrestore(&dwc->lock, flags);
1248
1249         usb_phy_shutdown(dwc->usb3_phy);
1250         usb_phy_shutdown(dwc->usb2_phy);
1251         phy_exit(dwc->usb2_generic_phy);
1252         phy_exit(dwc->usb3_generic_phy);
1253
1254         pinctrl_pm_select_sleep_state(dev);
1255
1256         return 0;
1257 }
1258
1259 static int dwc3_resume(struct device *dev)
1260 {
1261         struct dwc3     *dwc = dev_get_drvdata(dev);
1262         unsigned long   flags;
1263         int             ret;
1264
1265         pinctrl_pm_select_default_state(dev);
1266
1267         usb_phy_init(dwc->usb3_phy);
1268         usb_phy_init(dwc->usb2_phy);
1269         ret = phy_init(dwc->usb2_generic_phy);
1270         if (ret < 0)
1271                 return ret;
1272
1273         ret = phy_init(dwc->usb3_generic_phy);
1274         if (ret < 0)
1275                 goto err_usb2phy_init;
1276
1277         spin_lock_irqsave(&dwc->lock, flags);
1278
1279         dwc3_event_buffers_setup(dwc);
1280         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1281
1282         switch (dwc->dr_mode) {
1283         case USB_DR_MODE_PERIPHERAL:
1284         case USB_DR_MODE_OTG:
1285                 dwc3_gadget_resume(dwc);
1286                 /* FALLTHROUGH */
1287         case USB_DR_MODE_HOST:
1288         default:
1289                 /* do nothing */
1290                 break;
1291         }
1292
1293         spin_unlock_irqrestore(&dwc->lock, flags);
1294
1295         pm_runtime_disable(dev);
1296         pm_runtime_set_active(dev);
1297         pm_runtime_enable(dev);
1298
1299         return 0;
1300
1301 err_usb2phy_init:
1302         phy_exit(dwc->usb2_generic_phy);
1303
1304         return ret;
1305 }
1306
1307 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1308         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1309 };
1310
1311 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1312 #else
1313 #define DWC3_PM_OPS     NULL
1314 #endif
1315
1316 #ifdef CONFIG_OF
1317 static const struct of_device_id of_dwc3_match[] = {
1318         {
1319                 .compatible = "snps,dwc3"
1320         },
1321         {
1322                 .compatible = "synopsys,dwc3"
1323         },
1324         { },
1325 };
1326 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1327 #endif
1328
1329 #ifdef CONFIG_ACPI
1330
1331 #define ACPI_ID_INTEL_BSW       "808622B7"
1332
1333 static const struct acpi_device_id dwc3_acpi_match[] = {
1334         { ACPI_ID_INTEL_BSW, 0 },
1335         { },
1336 };
1337 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1338 #endif
1339
1340 static struct platform_driver dwc3_driver = {
1341         .probe          = dwc3_probe,
1342         .remove         = dwc3_remove,
1343         .driver         = {
1344                 .name   = "dwc3",
1345                 .of_match_table = of_match_ptr(of_dwc3_match),
1346                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1347                 .pm     = DWC3_PM_OPS,
1348         },
1349 };
1350
1351 module_platform_driver(dwc3_driver);
1352
1353 MODULE_ALIAS("platform:dwc3");
1354 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1355 MODULE_LICENSE("GPL v2");
1356 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");