drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "platform_data.h"
  45 #include "core.h"
  46 #include "gadget.h"
  47 #include "io.h"
  48
  49 #include "debug.h"
  50
  51 /* -------------------------------------------------------------------------- */
  52
  53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  54 {
  55         u32 reg;
  56
  57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61 }
  62
  63 /**
  64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  65  * @dwc: pointer to our context structure
  66  */
  67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  68 {
  69         u32             reg;
  70         int             retries = 1000;
  71         int             ret;
  72
  73         usb_phy_init(dwc->usb2_phy);
  74         usb_phy_init(dwc->usb3_phy);
  75         ret = phy_init(dwc->usb2_generic_phy);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = phy_init(dwc->usb3_generic_phy);
  80         if (ret < 0) {
  81                 phy_exit(dwc->usb2_generic_phy);
  82                 return ret;
  83         }
  84
  85         /*
  86          * We're resetting only the device side because, if we're in host mode,
  87          * XHCI driver will reset the host block. If dwc3 was configured for
  88          * host-only mode, then we can return early.
  89          */
  90         if (dwc->dr_mode == USB_DR_MODE_HOST)
  91                 return 0;
  92
  93         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  94         reg |= DWC3_DCTL_CSFTRST;
  95         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  96
  97         do {
  98                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  99                 if (!(reg & DWC3_DCTL_CSFTRST))
 100                         return 0;
 101
 102                 udelay(1);
 103         } while (--retries);
 104
 105         return -ETIMEDOUT;
 106 }
 107
 108 /**
 109  * dwc3_soft_reset - Issue soft reset
 110  * @dwc: Pointer to our controller context structure
 111  */
 112 static int dwc3_soft_reset(struct dwc3 *dwc)
 113 {
 114         unsigned long timeout;
 115         u32 reg;
 116
 117         timeout = jiffies + msecs_to_jiffies(500);
 118         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 119         do {
 120                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121                 if (!(reg & DWC3_DCTL_CSFTRST))
 122                         break;
 123
 124                 if (time_after(jiffies, timeout)) {
 125                         dev_err(dwc->dev, "Reset Timed Out\n");
 126                         return -ETIMEDOUT;
 127                 }
 128
 129                 cpu_relax();
 130         } while (true);
 131
 132         return 0;
 133 }
 134
 135 /*
 136  * dwc3_frame_length_adjustment - Adjusts frame length if required
 137  * @dwc3: Pointer to our controller context structure
 138  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 139  */
 140 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 141 {
 142         u32 reg;
 143         u32 dft;
 144
 145         if (dwc->revision < DWC3_REVISION_250A)
 146                 return;
 147
 148         if (fladj == 0)
 149                 return;
 150
 151         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 152         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 153         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 154             "request value same as default, ignoring\n")) {
 155                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 156                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 157                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 158         }
 159 }
 160
 161 /**
 162  * dwc3_free_one_event_buffer - Frees one event buffer
 163  * @dwc: Pointer to our controller context structure
 164  * @evt: Pointer to event buffer to be freed
 165  */
 166 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 167                 struct dwc3_event_buffer *evt)
 168 {
 169         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 170 }
 171
 172 /**
 173  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 174  * @dwc: Pointer to our controller context structure
 175  * @length: size of the event buffer
 176  *
 177  * Returns a pointer to the allocated event buffer structure on success
 178  * otherwise ERR_PTR(errno).
 179  */
 180 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 181                 unsigned length)
 182 {
 183         struct dwc3_event_buffer        *evt;
 184
 185         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 186         if (!evt)
 187                 return ERR_PTR(-ENOMEM);
 188
 189         evt->dwc        = dwc;
 190         evt->length     = length;
 191         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 192                         &evt->dma, GFP_KERNEL);
 193         if (!evt->buf)
 194                 return ERR_PTR(-ENOMEM);
 195
 196         return evt;
 197 }
 198
 199 /**
 200  * dwc3_free_event_buffers - frees all allocated event buffers
 201  * @dwc: Pointer to our controller context structure
 202  */
 203 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 204 {
 205         struct dwc3_event_buffer        *evt;
 206         int i;
 207
 208         for (i = 0; i < dwc->num_event_buffers; i++) {
 209                 evt = dwc->ev_buffs[i];
 210                 if (evt)
 211                         dwc3_free_one_event_buffer(dwc, evt);
 212         }
 213 }
 214
 215 /**
 216  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 217  * @dwc: pointer to our controller context structure
 218  * @length: size of event buffer
 219  *
 220  * Returns 0 on success otherwise negative errno. In the error case, dwc
 221  * may contain some buffers allocated but not all which were requested.
 222  */
 223 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 224 {
 225         int                     num;
 226         int                     i;
 227
 228         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 229         dwc->num_event_buffers = num;
 230
 231         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 232                         GFP_KERNEL);
 233         if (!dwc->ev_buffs)
 234                 return -ENOMEM;
 235
 236         for (i = 0; i < num; i++) {
 237                 struct dwc3_event_buffer        *evt;
 238
 239                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 240                 if (IS_ERR(evt)) {
 241                         dev_err(dwc->dev, "can't allocate event buffer\n");
 242                         return PTR_ERR(evt);
 243                 }
 244                 dwc->ev_buffs[i] = evt;
 245         }
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * dwc3_event_buffers_setup - setup our allocated event buffers
 252  * @dwc: pointer to our controller context structure
 253  *
 254  * Returns 0 on success otherwise negative errno.
 255  */
 256 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 257 {
 258         struct dwc3_event_buffer        *evt;
 259         int                             n;
 260
 261         for (n = 0; n < dwc->num_event_buffers; n++) {
 262                 evt = dwc->ev_buffs[n];
 263                 dwc3_trace(trace_dwc3_core,
 264                                 "Event buf %p dma %08llx length %d\n",
 265                                 evt->buf, (unsigned long long) evt->dma,
 266                                 evt->length);
 267
 268                 evt->lpos = 0;
 269
 270                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 271                                 lower_32_bits(evt->dma));
 272                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 273                                 upper_32_bits(evt->dma));
 274                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 275                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 276                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 277         }
 278
 279         return 0;
 280 }
 281
 282 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 283 {
 284         struct dwc3_event_buffer        *evt;
 285         int                             n;
 286
 287         for (n = 0; n < dwc->num_event_buffers; n++) {
 288                 evt = dwc->ev_buffs[n];
 289
 290                 evt->lpos = 0;
 291
 292                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 293                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 294                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 295                                 | DWC3_GEVNTSIZ_SIZE(0));
 296                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 297         }
 298 }
 299
 300 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 301 {
 302         if (!dwc->has_hibernation)
 303                 return 0;
 304
 305         if (!dwc->nr_scratch)
 306                 return 0;
 307
 308         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 309                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 310         if (!dwc->scratchbuf)
 311                 return -ENOMEM;
 312
 313         return 0;
 314 }
 315
 316 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 317 {
 318         dma_addr_t scratch_addr;
 319         u32 param;
 320         int ret;
 321
 322         if (!dwc->has_hibernation)
 323                 return 0;
 324
 325         if (!dwc->nr_scratch)
 326                 return 0;
 327
 328          /* should never fall here */
 329         if (!WARN_ON(dwc->scratchbuf))
 330                 return 0;
 331
 332         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 333                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 334                         DMA_BIDIRECTIONAL);
 335         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 336                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 337                 ret = -EFAULT;
 338                 goto err0;
 339         }
 340
 341         dwc->scratch_addr = scratch_addr;
 342
 343         param = lower_32_bits(scratch_addr);
 344
 345         ret = dwc3_send_gadget_generic_command(dwc,
 346                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 347         if (ret < 0)
 348                 goto err1;
 349
 350         param = upper_32_bits(scratch_addr);
 351
 352         ret = dwc3_send_gadget_generic_command(dwc,
 353                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 354         if (ret < 0)
 355                 goto err1;
 356
 357         return 0;
 358
 359 err1:
 360         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 361                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 362
 363 err0:
 364         return ret;
 365 }
 366
 367 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 368 {
 369         if (!dwc->has_hibernation)
 370                 return;
 371
 372         if (!dwc->nr_scratch)
 373                 return;
 374
 375          /* should never fall here */
 376         if (!WARN_ON(dwc->scratchbuf))
 377                 return;
 378
 379         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 380                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 381         kfree(dwc->scratchbuf);
 382 }
 383
 384 static void dwc3_core_num_eps(struct dwc3 *dwc)
 385 {
 386         struct dwc3_hwparams    *parms = &dwc->hwparams;
 387
 388         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 389         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 390
 391         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 392                         dwc->num_in_eps, dwc->num_out_eps);
 393 }
 394
 395 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 396 {
 397         struct dwc3_hwparams    *parms = &dwc->hwparams;
 398
 399         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 400         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 401         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 402         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 403         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 404         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 405         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 406         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 407         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 408 }
 409
 410 /**
 411  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 412  * @dwc: Pointer to our controller context structure
 413  *
 414  * Returns 0 on success. The USB PHY interfaces are configured but not
 415  * initialized. The PHY interfaces and the PHYs get initialized together with
 416  * the core in dwc3_core_init.
 417  */
 418 static int dwc3_phy_setup(struct dwc3 *dwc)
 419 {
 420         u32 reg;
 421         int ret;
 422
 423         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 424
 425         /*
 426          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 427          * to '0' during coreConsultant configuration. So default value
 428          * will be '0' when the core is reset. Application needs to set it
 429          * to '1' after the core initialization is completed.
 430          */
 431         if (dwc->revision > DWC3_REVISION_194A)
 432                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 433
 434         if (dwc->u2ss_inp3_quirk)
 435                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 436
 437         if (dwc->req_p1p2p3_quirk)
 438                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 439
 440         if (dwc->del_p1p2p3_quirk)
 441                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 442
 443         if (dwc->del_phy_power_chg_quirk)
 444                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 445
 446         if (dwc->lfps_filter_quirk)
 447                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 448
 449         if (dwc->rx_detect_poll_quirk)
 450                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 451
 452         if (dwc->tx_de_emphasis_quirk)
 453                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 454
 455         if (dwc->dis_u3_susphy_quirk)
 456                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 457
 458         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 459
 460         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 461
 462         /* Select the HS PHY interface */
 463         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 464         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 465                 if (dwc->hsphy_interface &&
 466                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 467                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 468                         break;
 469                 } else if (dwc->hsphy_interface &&
 470                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 471                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 472                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 473                 } else {
 474                         /* Relying on default value. */
 475                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 476                                 break;
 477                 }
 478                 /* FALLTHROUGH */
 479         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 480                 /* Making sure the interface and PHY are operational */
 481                 ret = dwc3_soft_reset(dwc);
 482                 if (ret)
 483                         return ret;
 484
 485                 udelay(1);
 486
 487                 ret = dwc3_ulpi_init(dwc);
 488                 if (ret)
 489                         return ret;
 490                 /* FALLTHROUGH */
 491         default:
 492                 break;
 493         }
 494
 495         /*
 496          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 497          * '0' during coreConsultant configuration. So default value will
 498          * be '0' when the core is reset. Application needs to set it to
 499          * '1' after the core initialization is completed.
 500          */
 501         if (dwc->revision > DWC3_REVISION_194A)
 502                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 503
 504         if (dwc->dis_u2_susphy_quirk)
 505                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 506
 507         if (dwc->dis_enblslpm_quirk)
 508                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 509
 510         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 511
 512         return 0;
 513 }
 514
 515 /**
 516  * dwc3_core_init - Low-level initialization of DWC3 Core
 517  * @dwc: Pointer to our controller context structure
 518  *
 519  * Returns 0 on success otherwise negative errno.
 520  */
 521 static int dwc3_core_init(struct dwc3 *dwc)
 522 {
 523         u32                     hwparams4 = dwc->hwparams.hwparams4;
 524         u32                     reg;
 525         int                     ret;
 526
 527         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 528         /* This should read as U3 followed by revision number */
 529         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 530                 /* Detected DWC_usb3 IP */
 531                 dwc->revision = reg;
 532         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 533                 /* Detected DWC_usb31 IP */
 534                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 535                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 536         } else {
 537                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 538                 ret = -ENODEV;
 539                 goto err0;
 540         }
 541
 542         /*
 543          * Write Linux Version Code to our GUID register so it's easy to figure
 544          * out which kernel version a bug was found.
 545          */
 546         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 547
 548         /* Handle USB2.0-only core configuration */
 549         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 550                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 551                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 552                         dwc->maximum_speed = USB_SPEED_HIGH;
 553         }
 554
 555         /* issue device SoftReset too */
 556         ret = dwc3_soft_reset(dwc);
 557         if (ret)
 558                 goto err0;
 559
 560         ret = dwc3_core_soft_reset(dwc);
 561         if (ret)
 562                 goto err0;
 563
 564         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 565         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 566
 567         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 568         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 569                 /**
 570                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 571                  * issue which would cause xHCI compliance tests to fail.
 572                  *
 573                  * Because of that we cannot enable clock gating on such
 574                  * configurations.
 575                  *
 576                  * Refers to:
 577                  *
 578                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 579                  * SOF/ITP Mode Used
 580                  */
 581                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 582                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 583                                 (dwc->revision >= DWC3_REVISION_210A &&
 584                                 dwc->revision <= DWC3_REVISION_250A))
 585                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 586                 else
 587                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 588                 break;
 589         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 590                 /* enable hibernation here */
 591                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 592
 593                 /*
 594                  * REVISIT Enabling this bit so that host-mode hibernation
 595                  * will work. Device-mode hibernation is not yet implemented.
 596                  */
 597                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 598                 break;
 599         default:
 600                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 601         }
 602
 603         /* check if current dwc3 is on simulation board */
 604         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 605                 dwc3_trace(trace_dwc3_core,
 606                                 "running on FPGA platform\n");
 607                 dwc->is_fpga = true;
 608         }
 609
 610         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 611                         "disable_scramble cannot be used on non-FPGA builds\n");
 612
 613         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 614                 reg |= DWC3_GCTL_DISSCRAMBLE;
 615         else
 616                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 617
 618         if (dwc->u2exit_lfps_quirk)
 619                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 620
 621         /*
 622          * WORKAROUND: DWC3 revisions <1.90a have a bug
 623          * where the device can fail to connect at SuperSpeed
 624          * and falls back to high-speed mode which causes
 625          * the device to enter a Connect/Disconnect loop
 626          */
 627         if (dwc->revision < DWC3_REVISION_190A)
 628                 reg |= DWC3_GCTL_U2RSTECN;
 629
 630         dwc3_core_num_eps(dwc);
 631
 632         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 633
 634         ret = dwc3_alloc_scratch_buffers(dwc);
 635         if (ret)
 636                 goto err1;
 637
 638         ret = dwc3_setup_scratch_buffers(dwc);
 639         if (ret)
 640                 goto err2;
 641
 642         return 0;
 643
 644 err2:
 645         dwc3_free_scratch_buffers(dwc);
 646
 647 err1:
 648         usb_phy_shutdown(dwc->usb2_phy);
 649         usb_phy_shutdown(dwc->usb3_phy);
 650         phy_exit(dwc->usb2_generic_phy);
 651         phy_exit(dwc->usb3_generic_phy);
 652
 653 err0:
 654         return ret;
 655 }
 656
 657 static void dwc3_core_exit(struct dwc3 *dwc)
 658 {
 659         dwc3_free_scratch_buffers(dwc);
 660         usb_phy_shutdown(dwc->usb2_phy);
 661         usb_phy_shutdown(dwc->usb3_phy);
 662         phy_exit(dwc->usb2_generic_phy);
 663         phy_exit(dwc->usb3_generic_phy);
 664 }
 665
 666 static int dwc3_core_get_phy(struct dwc3 *dwc)
 667 {
 668         struct device           *dev = dwc->dev;
 669         struct device_node      *node = dev->of_node;
 670         int ret;
 671
 672         if (node) {
 673                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 674                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 675         } else {
 676                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 677                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 678         }
 679
 680         if (IS_ERR(dwc->usb2_phy)) {
 681                 ret = PTR_ERR(dwc->usb2_phy);
 682                 if (ret == -ENXIO || ret == -ENODEV) {
 683                         dwc->usb2_phy = NULL;
 684                 } else if (ret == -EPROBE_DEFER) {
 685                         return ret;
 686                 } else {
 687                         dev_err(dev, "no usb2 phy configured\n");
 688                         return ret;
 689                 }
 690         }
 691
 692         if (IS_ERR(dwc->usb3_phy)) {
 693                 ret = PTR_ERR(dwc->usb3_phy);
 694                 if (ret == -ENXIO || ret == -ENODEV) {
 695                         dwc->usb3_phy = NULL;
 696                 } else if (ret == -EPROBE_DEFER) {
 697                         return ret;
 698                 } else {
 699                         dev_err(dev, "no usb3 phy configured\n");
 700                         return ret;
 701                 }
 702         }
 703
 704         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 705         if (IS_ERR(dwc->usb2_generic_phy)) {
 706                 ret = PTR_ERR(dwc->usb2_generic_phy);
 707                 if (ret == -ENOSYS || ret == -ENODEV) {
 708                         dwc->usb2_generic_phy = NULL;
 709                 } else if (ret == -EPROBE_DEFER) {
 710                         return ret;
 711                 } else {
 712                         dev_err(dev, "no usb2 phy configured\n");
 713                         return ret;
 714                 }
 715         }
 716
 717         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 718         if (IS_ERR(dwc->usb3_generic_phy)) {
 719                 ret = PTR_ERR(dwc->usb3_generic_phy);
 720                 if (ret == -ENOSYS || ret == -ENODEV) {
 721                         dwc->usb3_generic_phy = NULL;
 722                 } else if (ret == -EPROBE_DEFER) {
 723                         return ret;
 724                 } else {
 725                         dev_err(dev, "no usb3 phy configured\n");
 726                         return ret;
 727                 }
 728         }
 729
 730         return 0;
 731 }
 732
 733 static int dwc3_core_init_mode(struct dwc3 *dwc)
 734 {
 735         struct device *dev = dwc->dev;
 736         int ret;
 737
 738         switch (dwc->dr_mode) {
 739         case USB_DR_MODE_PERIPHERAL:
 740                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 741                 ret = dwc3_gadget_init(dwc);
 742                 if (ret) {
 743                         dev_err(dev, "failed to initialize gadget\n");
 744                         return ret;
 745                 }
 746                 break;
 747         case USB_DR_MODE_HOST:
 748                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 749                 ret = dwc3_host_init(dwc);
 750                 if (ret) {
 751                         dev_err(dev, "failed to initialize host\n");
 752                         return ret;
 753                 }
 754                 break;
 755         case USB_DR_MODE_OTG:
 756                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 757                 ret = dwc3_host_init(dwc);
 758                 if (ret) {
 759                         dev_err(dev, "failed to initialize host\n");
 760                         return ret;
 761                 }
 762
 763                 ret = dwc3_gadget_init(dwc);
 764                 if (ret) {
 765                         dev_err(dev, "failed to initialize gadget\n");
 766                         return ret;
 767                 }
 768                 break;
 769         default:
 770                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 771                 return -EINVAL;
 772         }
 773
 774         return 0;
 775 }
 776
 777 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 778 {
 779         switch (dwc->dr_mode) {
 780         case USB_DR_MODE_PERIPHERAL:
 781                 dwc3_gadget_exit(dwc);
 782                 break;
 783         case USB_DR_MODE_HOST:
 784                 dwc3_host_exit(dwc);
 785                 break;
 786         case USB_DR_MODE_OTG:
 787                 dwc3_host_exit(dwc);
 788                 dwc3_gadget_exit(dwc);
 789                 break;
 790         default:
 791                 /* do nothing */
 792                 break;
 793         }
 794 }
 795
 796 #define DWC3_ALIGN_MASK         (16 - 1)
 797
 798 static int dwc3_probe(struct platform_device *pdev)
 799 {
 800         struct device           *dev = &pdev->dev;
 801         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 802         struct resource         *res;
 803         struct dwc3             *dwc;
 804         u8                      lpm_nyet_threshold;
 805         u8                      tx_de_emphasis;
 806         u8                      hird_threshold;
 807         u32                     fladj = 0;
 808
 809         int                     ret;
 810
 811         void __iomem            *regs;
 812         void                    *mem;
 813
 814         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 815         if (!mem)
 816                 return -ENOMEM;
 817
 818         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 819         dwc->mem = mem;
 820         dwc->dev = dev;
 821
 822         /* Try to set 64-bit DMA first */
 823         if (!pdev->dev.dma_mask)
 824                 /* Platform did not initialize dma_mask */
 825                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 826                                                    DMA_BIT_MASK(64));
 827         else
 828                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 829
 830         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 831         if (ret) {
 832                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 833                 if (ret)
 834                         return ret;
 835         }
 836
 837         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 838         if (!res) {
 839                 dev_err(dev, "missing IRQ\n");
 840                 return -ENODEV;
 841         }
 842         dwc->xhci_resources[1].start = res->start;
 843         dwc->xhci_resources[1].end = res->end;
 844         dwc->xhci_resources[1].flags = res->flags;
 845         dwc->xhci_resources[1].name = res->name;
 846
 847         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 848         if (!res) {
 849                 dev_err(dev, "missing memory resource\n");
 850                 return -ENODEV;
 851         }
 852
 853         dwc->xhci_resources[0].start = res->start;
 854         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 855                                         DWC3_XHCI_REGS_END;
 856         dwc->xhci_resources[0].flags = res->flags;
 857         dwc->xhci_resources[0].name = res->name;
 858
 859         res->start += DWC3_GLOBALS_REGS_START;
 860
 861         /*
 862          * Request memory region but exclude xHCI regs,
 863          * since it will be requested by the xhci-plat driver.
 864          */
 865         regs = devm_ioremap_resource(dev, res);
 866         if (IS_ERR(regs)) {
 867                 ret = PTR_ERR(regs);
 868                 goto err0;
 869         }
 870
 871         dwc->regs       = regs;
 872         dwc->regs_size  = resource_size(res);
 873
 874         /* default to highest possible threshold */
 875         lpm_nyet_threshold = 0xff;
 876
 877         /* default to -3.5dB de-emphasis */
 878         tx_de_emphasis = 1;
 879
 880         /*
 881          * default to assert utmi_sleep_n and use maximum allowed HIRD
 882          * threshold value of 0b1100
 883          */
 884         hird_threshold = 12;
 885
 886         dwc->maximum_speed = usb_get_maximum_speed(dev);
 887         dwc->dr_mode = usb_get_dr_mode(dev);
 888
 889         dwc->has_lpm_erratum = device_property_read_bool(dev,
 890                                 "snps,has-lpm-erratum");
 891         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 892                                 &lpm_nyet_threshold);
 893         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 894                                 "snps,is-utmi-l1-suspend");
 895         device_property_read_u8(dev, "snps,hird-threshold",
 896                                 &hird_threshold);
 897         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 898                                 "snps,usb3_lpm_capable");
 899
 900         dwc->needs_fifo_resize = device_property_read_bool(dev,
 901                                 "tx-fifo-resize");
 902
 903         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 904                                 "snps,disable_scramble_quirk");
 905         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 906                                 "snps,u2exit_lfps_quirk");
 907         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 908                                 "snps,u2ss_inp3_quirk");
 909         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 910                                 "snps,req_p1p2p3_quirk");
 911         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 912                                 "snps,del_p1p2p3_quirk");
 913         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 914                                 "snps,del_phy_power_chg_quirk");
 915         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 916                                 "snps,lfps_filter_quirk");
 917         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
 918                                 "snps,rx_detect_poll_quirk");
 919         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
 920                                 "snps,dis_u3_susphy_quirk");
 921         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
 922                                 "snps,dis_u2_susphy_quirk");
 923         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
 924                                 "snps,dis_enblslpm_quirk");
 925
 926         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 927                                 "snps,tx_de_emphasis_quirk");
 928         device_property_read_u8(dev, "snps,tx_de_emphasis",
 929                                 &tx_de_emphasis);
 930         device_property_read_string(dev, "snps,hsphy_interface",
 931                                     &dwc->hsphy_interface);
 932         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
 933                                  &fladj);
 934
 935         if (pdata) {
 936                 dwc->maximum_speed = pdata->maximum_speed;
 937                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 938                 if (pdata->lpm_nyet_threshold)
 939                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
 940                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
 941                 if (pdata->hird_threshold)
 942                         hird_threshold = pdata->hird_threshold;
 943
 944                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 945                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
 946                 dwc->dr_mode = pdata->dr_mode;
 947
 948                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
 949                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
 950                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
 951                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
 952                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
 953                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
 954                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
 955                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
 956                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
 957                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
 958                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
 959
 960                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
 961                 if (pdata->tx_de_emphasis)
 962                         tx_de_emphasis = pdata->tx_de_emphasis;
 963
 964                 dwc->hsphy_interface = pdata->hsphy_interface;
 965                 fladj = pdata->fladj_value;
 966         }
 967
 968         /* default to superspeed if no maximum_speed passed */
 969         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 970                 dwc->maximum_speed = USB_SPEED_SUPER;
 971
 972         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 973         dwc->tx_de_emphasis = tx_de_emphasis;
 974
 975         dwc->hird_threshold = hird_threshold
 976                 | (dwc->is_utmi_l1_suspend << 4);
 977
 978         platform_set_drvdata(pdev, dwc);
 979         dwc3_cache_hwparams(dwc);
 980
 981         ret = dwc3_phy_setup(dwc);
 982         if (ret)
 983                 goto err0;
 984
 985         ret = dwc3_core_get_phy(dwc);
 986         if (ret)
 987                 goto err0;
 988
 989         spin_lock_init(&dwc->lock);
 990
 991         if (!dev->dma_mask) {
 992                 dev->dma_mask = dev->parent->dma_mask;
 993                 dev->dma_parms = dev->parent->dma_parms;
 994                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 995         }
 996
 997         pm_runtime_enable(dev);
 998         pm_runtime_get_sync(dev);
 999         pm_runtime_forbid(dev);
1000
1001         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1002         if (ret) {
1003                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1004                 ret = -ENOMEM;
1005                 goto err1;
1006         }
1007
1008         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1009                 dwc->dr_mode = USB_DR_MODE_HOST;
1010         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1011                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1012
1013         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1014                 dwc->dr_mode = USB_DR_MODE_OTG;
1015
1016         ret = dwc3_core_init(dwc);
1017         if (ret) {
1018                 dev_err(dev, "failed to initialize core\n");
1019                 goto err1;
1020         }
1021
1022         /* Adjust Frame Length */
1023         dwc3_frame_length_adjustment(dwc, fladj);
1024
1025         usb_phy_set_suspend(dwc->usb2_phy, 0);
1026         usb_phy_set_suspend(dwc->usb3_phy, 0);
1027         ret = phy_power_on(dwc->usb2_generic_phy);
1028         if (ret < 0)
1029                 goto err2;
1030
1031         ret = phy_power_on(dwc->usb3_generic_phy);
1032         if (ret < 0)
1033                 goto err3;
1034
1035         ret = dwc3_event_buffers_setup(dwc);
1036         if (ret) {
1037                 dev_err(dwc->dev, "failed to setup event buffers\n");
1038                 goto err4;
1039         }
1040
1041         ret = dwc3_core_init_mode(dwc);
1042         if (ret)
1043                 goto err5;
1044
1045         ret = dwc3_debugfs_init(dwc);
1046         if (ret) {
1047                 dev_err(dev, "failed to initialize debugfs\n");
1048                 goto err6;
1049         }
1050
1051         pm_runtime_allow(dev);
1052
1053         return 0;
1054
1055 err6:
1056         dwc3_core_exit_mode(dwc);
1057
1058 err5:
1059         dwc3_event_buffers_cleanup(dwc);
1060
1061 err4:
1062         phy_power_off(dwc->usb3_generic_phy);
1063
1064 err3:
1065         phy_power_off(dwc->usb2_generic_phy);
1066
1067 err2:
1068         usb_phy_set_suspend(dwc->usb2_phy, 1);
1069         usb_phy_set_suspend(dwc->usb3_phy, 1);
1070         dwc3_core_exit(dwc);
1071
1072 err1:
1073         dwc3_free_event_buffers(dwc);
1074         dwc3_ulpi_exit(dwc);
1075
1076 err0:
1077         /*
1078          * restore res->start back to its original value so that, in case the
1079          * probe is deferred, we don't end up getting error in request the
1080          * memory region the next time probe is called.
1081          */
1082         res->start -= DWC3_GLOBALS_REGS_START;
1083
1084         return ret;
1085 }
1086
1087 static int dwc3_remove(struct platform_device *pdev)
1088 {
1089         struct dwc3     *dwc = platform_get_drvdata(pdev);
1090         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1091
1092         /*
1093          * restore res->start back to its original value so that, in case the
1094          * probe is deferred, we don't end up getting error in request the
1095          * memory region the next time probe is called.
1096          */
1097         res->start -= DWC3_GLOBALS_REGS_START;
1098
1099         dwc3_debugfs_exit(dwc);
1100         dwc3_core_exit_mode(dwc);
1101         dwc3_event_buffers_cleanup(dwc);
1102         dwc3_free_event_buffers(dwc);
1103
1104         usb_phy_set_suspend(dwc->usb2_phy, 1);
1105         usb_phy_set_suspend(dwc->usb3_phy, 1);
1106         phy_power_off(dwc->usb2_generic_phy);
1107         phy_power_off(dwc->usb3_generic_phy);
1108
1109         dwc3_core_exit(dwc);
1110         dwc3_ulpi_exit(dwc);
1111
1112         pm_runtime_put_sync(&pdev->dev);
1113         pm_runtime_disable(&pdev->dev);
1114
1115         return 0;
1116 }
1117
1118 #ifdef CONFIG_PM_SLEEP
1119 static int dwc3_suspend(struct device *dev)
1120 {
1121         struct dwc3     *dwc = dev_get_drvdata(dev);
1122         unsigned long   flags;
1123
1124         spin_lock_irqsave(&dwc->lock, flags);
1125
1126         switch (dwc->dr_mode) {
1127         case USB_DR_MODE_PERIPHERAL:
1128         case USB_DR_MODE_OTG:
1129                 dwc3_gadget_suspend(dwc);
1130                 /* FALLTHROUGH */
1131         case USB_DR_MODE_HOST:
1132         default:
1133                 dwc3_event_buffers_cleanup(dwc);
1134                 break;
1135         }
1136
1137         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1138         spin_unlock_irqrestore(&dwc->lock, flags);
1139
1140         usb_phy_shutdown(dwc->usb3_phy);
1141         usb_phy_shutdown(dwc->usb2_phy);
1142         phy_exit(dwc->usb2_generic_phy);
1143         phy_exit(dwc->usb3_generic_phy);
1144
1145         pinctrl_pm_select_sleep_state(dev);
1146
1147         return 0;
1148 }
1149
1150 static int dwc3_resume(struct device *dev)
1151 {
1152         struct dwc3     *dwc = dev_get_drvdata(dev);
1153         unsigned long   flags;
1154         int             ret;
1155
1156         pinctrl_pm_select_default_state(dev);
1157
1158         usb_phy_init(dwc->usb3_phy);
1159         usb_phy_init(dwc->usb2_phy);
1160         ret = phy_init(dwc->usb2_generic_phy);
1161         if (ret < 0)
1162                 return ret;
1163
1164         ret = phy_init(dwc->usb3_generic_phy);
1165         if (ret < 0)
1166                 goto err_usb2phy_init;
1167
1168         spin_lock_irqsave(&dwc->lock, flags);
1169
1170         dwc3_event_buffers_setup(dwc);
1171         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1172
1173         switch (dwc->dr_mode) {
1174         case USB_DR_MODE_PERIPHERAL:
1175         case USB_DR_MODE_OTG:
1176                 dwc3_gadget_resume(dwc);
1177                 /* FALLTHROUGH */
1178         case USB_DR_MODE_HOST:
1179         default:
1180                 /* do nothing */
1181                 break;
1182         }
1183
1184         spin_unlock_irqrestore(&dwc->lock, flags);
1185
1186         pm_runtime_disable(dev);
1187         pm_runtime_set_active(dev);
1188         pm_runtime_enable(dev);
1189
1190         return 0;
1191
1192 err_usb2phy_init:
1193         phy_exit(dwc->usb2_generic_phy);
1194
1195         return ret;
1196 }
1197
1198 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1199         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1200 };
1201
1202 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1203 #else
1204 #define DWC3_PM_OPS     NULL
1205 #endif
1206
1207 #ifdef CONFIG_OF
1208 static const struct of_device_id of_dwc3_match[] = {
1209         {
1210                 .compatible = "snps,dwc3"
1211         },
1212         {
1213                 .compatible = "synopsys,dwc3"
1214         },
1215         { },
1216 };
1217 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1218 #endif
1219
1220 #ifdef CONFIG_ACPI
1221
1222 #define ACPI_ID_INTEL_BSW       "808622B7"
1223
1224 static const struct acpi_device_id dwc3_acpi_match[] = {
1225         { ACPI_ID_INTEL_BSW, 0 },
1226         { },
1227 };
1228 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1229 #endif
1230
1231 static struct platform_driver dwc3_driver = {
1232         .probe          = dwc3_probe,
1233         .remove         = dwc3_remove,
1234         .driver         = {
1235                 .name   = "dwc3",
1236                 .of_match_table = of_match_ptr(of_dwc3_match),
1237                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1238                 .pm     = DWC3_PM_OPS,
1239         },
1240 };
1241
1242 module_platform_driver(dwc3_driver);
1243
1244 MODULE_ALIAS("platform:dwc3");
1245 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1246 MODULE_LICENSE("GPL v2");
1247 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");