drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/extcon.h>
  36 #include <linux/of.h>
  37 #include <linux/acpi.h>
  38 #include <linux/pinctrl/consumer.h>
  39
  40 #include <linux/usb/ch9.h>
  41 #include <linux/usb/gadget.h>
  42 #include <linux/usb/of.h>
  43 #include <linux/usb/otg.h>
  44
  45 #include "platform_data.h"
  46 #include "core.h"
  47 #include "gadget.h"
  48 #include "io.h"
  49
  50 #include "debug.h"
  51
  52 /* -------------------------------------------------------------------------- */
  53
  54 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  55 {
  56         u32 reg;
  57
  58         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  59         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  60         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  61         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  62 }
  63
  64 /**
  65  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  66  * @dwc: pointer to our context structure
  67  */
  68 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  69 {
  70         u32             reg;
  71         int             retries = 1000;
  72         int             ret;
  73
  74         usb_phy_init(dwc->usb2_phy);
  75         usb_phy_init(dwc->usb3_phy);
  76         ret = phy_init(dwc->usb2_generic_phy);
  77         if (ret < 0)
  78                 return ret;
  79
  80         ret = phy_init(dwc->usb3_generic_phy);
  81         if (ret < 0) {
  82                 phy_exit(dwc->usb2_generic_phy);
  83                 return ret;
  84         }
  85
  86         /*
  87          * We're resetting only the device side because, if we're in host mode,
  88          * XHCI driver will reset the host block. If dwc3 was configured for
  89          * host-only mode, then we can return early.
  90          */
  91         if (dwc->dr_mode == USB_DR_MODE_HOST)
  92                 return 0;
  93
  94         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  95         reg |= DWC3_DCTL_CSFTRST;
  96         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  97
  98         do {
  99                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 100                 if (!(reg & DWC3_DCTL_CSFTRST))
 101                         return 0;
 102
 103                 udelay(1);
 104         } while (--retries);
 105
 106         return -ETIMEDOUT;
 107 }
 108
 109 /**
 110  * dwc3_soft_reset - Issue soft reset
 111  * @dwc: Pointer to our controller context structure
 112  */
 113 int dwc3_soft_reset(struct dwc3 *dwc)
 114 {
 115         unsigned long timeout;
 116         u32 reg;
 117
 118         timeout = jiffies + msecs_to_jiffies(500);
 119         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 120         do {
 121                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 122                 if (!(reg & DWC3_DCTL_CSFTRST))
 123                         break;
 124
 125                 if (time_after(jiffies, timeout)) {
 126                         dev_err(dwc->dev, "Reset Timed Out\n");
 127                         return -ETIMEDOUT;
 128                 }
 129
 130                 cpu_relax();
 131         } while (true);
 132
 133         return 0;
 134 }
 135
 136 /*
 137  * dwc3_frame_length_adjustment - Adjusts frame length if required
 138  * @dwc3: Pointer to our controller context structure
 139  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 140  */
 141 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 142 {
 143         u32 reg;
 144         u32 dft;
 145
 146         if (dwc->revision < DWC3_REVISION_250A)
 147                 return;
 148
 149         if (fladj == 0)
 150                 return;
 151
 152         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 153         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 154         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 155             "request value same as default, ignoring\n")) {
 156                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 157                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 158                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 159         }
 160 }
 161
 162 /**
 163  * dwc3_free_one_event_buffer - Frees one event buffer
 164  * @dwc: Pointer to our controller context structure
 165  * @evt: Pointer to event buffer to be freed
 166  */
 167 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 168                 struct dwc3_event_buffer *evt)
 169 {
 170         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 171 }
 172
 173 /**
 174  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 175  * @dwc: Pointer to our controller context structure
 176  * @length: size of the event buffer
 177  *
 178  * Returns a pointer to the allocated event buffer structure on success
 179  * otherwise ERR_PTR(errno).
 180  */
 181 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 182                 unsigned length)
 183 {
 184         struct dwc3_event_buffer        *evt;
 185
 186         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 187         if (!evt)
 188                 return ERR_PTR(-ENOMEM);
 189
 190         evt->dwc        = dwc;
 191         evt->length     = length;
 192         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 193                         &evt->dma, GFP_KERNEL);
 194         if (!evt->buf)
 195                 return ERR_PTR(-ENOMEM);
 196
 197         return evt;
 198 }
 199
 200 /**
 201  * dwc3_free_event_buffers - frees all allocated event buffers
 202  * @dwc: Pointer to our controller context structure
 203  */
 204 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 205 {
 206         struct dwc3_event_buffer        *evt;
 207         int i;
 208
 209         for (i = 0; i < dwc->num_event_buffers; i++) {
 210                 evt = dwc->ev_buffs[i];
 211                 if (evt)
 212                         dwc3_free_one_event_buffer(dwc, evt);
 213         }
 214 }
 215
 216 /**
 217  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 218  * @dwc: pointer to our controller context structure
 219  * @length: size of event buffer
 220  *
 221  * Returns 0 on success otherwise negative errno. In the error case, dwc
 222  * may contain some buffers allocated but not all which were requested.
 223  */
 224 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 225 {
 226         int                     num;
 227         int                     i;
 228
 229         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 230         dwc->num_event_buffers = num;
 231
 232         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 233                         GFP_KERNEL);
 234         if (!dwc->ev_buffs)
 235                 return -ENOMEM;
 236
 237         for (i = 0; i < num; i++) {
 238                 struct dwc3_event_buffer        *evt;
 239
 240                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 241                 if (IS_ERR(evt)) {
 242                         dev_err(dwc->dev, "can't allocate event buffer\n");
 243                         return PTR_ERR(evt);
 244                 }
 245                 dwc->ev_buffs[i] = evt;
 246         }
 247
 248         return 0;
 249 }
 250
 251 /**
 252  * dwc3_event_buffers_setup - setup our allocated event buffers
 253  * @dwc: pointer to our controller context structure
 254  *
 255  * Returns 0 on success otherwise negative errno.
 256  */
 257 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 258 {
 259         struct dwc3_event_buffer        *evt;
 260         int                             n;
 261
 262         for (n = 0; n < dwc->num_event_buffers; n++) {
 263                 evt = dwc->ev_buffs[n];
 264                 dwc3_trace(trace_dwc3_core,
 265                                 "Event buf %p dma %08llx length %d\n",
 266                                 evt->buf, (unsigned long long) evt->dma,
 267                                 evt->length);
 268
 269                 evt->lpos = 0;
 270
 271                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 272                                 lower_32_bits(evt->dma));
 273                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 274                                 upper_32_bits(evt->dma));
 275                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 276                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 277                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 278         }
 279
 280         return 0;
 281 }
 282
 283 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 284 {
 285         struct dwc3_event_buffer        *evt;
 286         int                             n;
 287
 288         for (n = 0; n < dwc->num_event_buffers; n++) {
 289                 evt = dwc->ev_buffs[n];
 290
 291                 evt->lpos = 0;
 292
 293                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 294                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 295                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 296                                 | DWC3_GEVNTSIZ_SIZE(0));
 297                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 298         }
 299 }
 300
 301 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 302 {
 303         if (!dwc->has_hibernation)
 304                 return 0;
 305
 306         if (!dwc->nr_scratch)
 307                 return 0;
 308
 309         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 310                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 311         if (!dwc->scratchbuf)
 312                 return -ENOMEM;
 313
 314         return 0;
 315 }
 316
 317 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 318 {
 319         dma_addr_t scratch_addr;
 320         u32 param;
 321         int ret;
 322
 323         if (!dwc->has_hibernation)
 324                 return 0;
 325
 326         if (!dwc->nr_scratch)
 327                 return 0;
 328
 329          /* should never fall here */
 330         if (!WARN_ON(dwc->scratchbuf))
 331                 return 0;
 332
 333         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 334                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 335                         DMA_BIDIRECTIONAL);
 336         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 337                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 338                 ret = -EFAULT;
 339                 goto err0;
 340         }
 341
 342         dwc->scratch_addr = scratch_addr;
 343
 344         param = lower_32_bits(scratch_addr);
 345
 346         ret = dwc3_send_gadget_generic_command(dwc,
 347                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 348         if (ret < 0)
 349                 goto err1;
 350
 351         param = upper_32_bits(scratch_addr);
 352
 353         ret = dwc3_send_gadget_generic_command(dwc,
 354                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 355         if (ret < 0)
 356                 goto err1;
 357
 358         return 0;
 359
 360 err1:
 361         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 362                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 363
 364 err0:
 365         return ret;
 366 }
 367
 368 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 369 {
 370         if (!dwc->has_hibernation)
 371                 return;
 372
 373         if (!dwc->nr_scratch)
 374                 return;
 375
 376          /* should never fall here */
 377         if (!WARN_ON(dwc->scratchbuf))
 378                 return;
 379
 380         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 381                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 382         kfree(dwc->scratchbuf);
 383 }
 384
 385 static void dwc3_core_num_eps(struct dwc3 *dwc)
 386 {
 387         struct dwc3_hwparams    *parms = &dwc->hwparams;
 388
 389         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 390         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 391
 392         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 393                         dwc->num_in_eps, dwc->num_out_eps);
 394 }
 395
 396 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 397 {
 398         struct dwc3_hwparams    *parms = &dwc->hwparams;
 399
 400         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 401         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 402         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 403         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 404         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 405         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 406         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 407         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 408         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 409 }
 410
 411 /**
 412  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 413  * @dwc: Pointer to our controller context structure
 414  *
 415  * Returns 0 on success. The USB PHY interfaces are configured but not
 416  * initialized. The PHY interfaces and the PHYs get initialized together with
 417  * the core in dwc3_core_init.
 418  */
 419 static int dwc3_phy_setup(struct dwc3 *dwc)
 420 {
 421         u32 reg;
 422         u32 usbtrdtim;
 423         int ret;
 424
 425         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 426
 427         /*
 428          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 429          * to '0' during coreConsultant configuration. So default value
 430          * will be '0' when the core is reset. Application needs to set it
 431          * to '1' after the core initialization is completed.
 432          */
 433         if (dwc->revision > DWC3_REVISION_194A)
 434                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 435
 436         if (dwc->u2ss_inp3_quirk)
 437                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 438
 439         if (dwc->req_p1p2p3_quirk)
 440                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 441
 442         if (dwc->del_p1p2p3_quirk)
 443                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 444
 445         if (dwc->del_phy_power_chg_quirk)
 446                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 447
 448         if (dwc->lfps_filter_quirk)
 449                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 450
 451         if (dwc->rx_detect_poll_quirk)
 452                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 453
 454         if (dwc->tx_de_emphasis_quirk)
 455                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 456
 457         if (dwc->dis_u3_susphy_quirk)
 458                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 459
 460         if (dwc->dis_del_phy_power_chg_quirk)
 461                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 462
 463         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 464
 465         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 466
 467         /* Select the HS PHY interface */
 468         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 469         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 470                 if (dwc->hsphy_interface &&
 471                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 472                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 473                         break;
 474                 } else if (dwc->hsphy_interface &&
 475                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 476                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 477                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 478                 } else {
 479                         /* Relying on default value. */
 480                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 481                                 break;
 482                 }
 483                 /* FALLTHROUGH */
 484         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 485                 /* Making sure the interface and PHY are operational */
 486                 ret = dwc3_soft_reset(dwc);
 487                 if (ret)
 488                         return ret;
 489
 490                 udelay(1);
 491
 492                 ret = dwc3_ulpi_init(dwc);
 493                 if (ret)
 494                         return ret;
 495                 /* FALLTHROUGH */
 496         default:
 497                 break;
 498         }
 499
 500         /*
 501          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 502          * '0' during coreConsultant configuration. So default value will
 503          * be '0' when the core is reset. Application needs to set it to
 504          * '1' after the core initialization is completed.
 505          */
 506         if (dwc->revision > DWC3_REVISION_194A)
 507                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 508
 509         if (dwc->dis_u2_susphy_quirk)
 510                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 511
 512         if (dwc->dis_enblslpm_quirk)
 513                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 514
 515         if (dwc->dis_u2_freeclk_exists_quirk)
 516                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 517
 518         if (dwc->phyif_utmi_16_bits)
 519                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
 520
 521         usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
 522                     USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
 523
 524         reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 525         reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
 526
 527         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 528
 529         return 0;
 530 }
 531
 532 /**
 533  * dwc3_core_init - Low-level initialization of DWC3 Core
 534  * @dwc: Pointer to our controller context structure
 535  *
 536  * Returns 0 on success otherwise negative errno.
 537  */
 538 static int dwc3_core_init(struct dwc3 *dwc)
 539 {
 540         u32                     hwparams4 = dwc->hwparams.hwparams4;
 541         u32                     reg;
 542         int                     ret;
 543
 544         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 545         /* This should read as U3 followed by revision number */
 546         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 547                 /* Detected DWC_usb3 IP */
 548                 dwc->revision = reg;
 549         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 550                 /* Detected DWC_usb31 IP */
 551                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 552                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 553         } else {
 554                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 555                 ret = -ENODEV;
 556                 goto err0;
 557         }
 558
 559         /*
 560          * Write Linux Version Code to our GUID register so it's easy to figure
 561          * out which kernel version a bug was found.
 562          */
 563         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 564
 565         /* Handle USB2.0-only core configuration */
 566         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 567                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 568                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 569                         dwc->maximum_speed = USB_SPEED_HIGH;
 570         }
 571
 572         /* issue device SoftReset too */
 573         ret = dwc3_soft_reset(dwc);
 574         if (ret)
 575                 goto err0;
 576
 577         ret = dwc3_core_soft_reset(dwc);
 578         if (ret)
 579                 goto err0;
 580
 581         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 582         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 583
 584         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 585         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 586                 /**
 587                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 588                  * issue which would cause xHCI compliance tests to fail.
 589                  *
 590                  * Because of that we cannot enable clock gating on such
 591                  * configurations.
 592                  *
 593                  * Refers to:
 594                  *
 595                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 596                  * SOF/ITP Mode Used
 597                  */
 598                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 599                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 600                                 (dwc->revision >= DWC3_REVISION_210A &&
 601                                 dwc->revision <= DWC3_REVISION_250A))
 602                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 603                 else
 604                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 605                 break;
 606         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 607                 /* enable hibernation here */
 608                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 609
 610                 /*
 611                  * REVISIT Enabling this bit so that host-mode hibernation
 612                  * will work. Device-mode hibernation is not yet implemented.
 613                  */
 614                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 615                 break;
 616         default:
 617                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 618         }
 619
 620         /* check if current dwc3 is on simulation board */
 621         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 622                 dwc3_trace(trace_dwc3_core,
 623                                 "running on FPGA platform\n");
 624                 dwc->is_fpga = true;
 625         }
 626
 627         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 628                         "disable_scramble cannot be used on non-FPGA builds\n");
 629
 630         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 631                 reg |= DWC3_GCTL_DISSCRAMBLE;
 632         else
 633                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 634
 635         if (dwc->u2exit_lfps_quirk)
 636                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 637
 638         /*
 639          * WORKAROUND: DWC3 revisions <1.90a have a bug
 640          * where the device can fail to connect at SuperSpeed
 641          * and falls back to high-speed mode which causes
 642          * the device to enter a Connect/Disconnect loop
 643          */
 644         if (dwc->revision < DWC3_REVISION_190A)
 645                 reg |= DWC3_GCTL_U2RSTECN;
 646
 647         dwc3_core_num_eps(dwc);
 648
 649         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 650
 651         ret = dwc3_alloc_scratch_buffers(dwc);
 652         if (ret)
 653                 goto err1;
 654
 655         ret = dwc3_setup_scratch_buffers(dwc);
 656         if (ret)
 657                 goto err2;
 658
 659         return 0;
 660
 661 err2:
 662         dwc3_free_scratch_buffers(dwc);
 663
 664 err1:
 665         usb_phy_shutdown(dwc->usb2_phy);
 666         usb_phy_shutdown(dwc->usb3_phy);
 667         phy_exit(dwc->usb2_generic_phy);
 668         phy_exit(dwc->usb3_generic_phy);
 669
 670 err0:
 671         return ret;
 672 }
 673
 674 static void dwc3_core_exit(struct dwc3 *dwc)
 675 {
 676         dwc3_free_scratch_buffers(dwc);
 677         usb_phy_shutdown(dwc->usb2_phy);
 678         usb_phy_shutdown(dwc->usb3_phy);
 679         phy_exit(dwc->usb2_generic_phy);
 680         phy_exit(dwc->usb3_generic_phy);
 681 }
 682
 683 static int dwc3_core_get_phy(struct dwc3 *dwc)
 684 {
 685         struct device           *dev = dwc->dev;
 686         struct device_node      *node = dev->of_node;
 687         int ret;
 688
 689         if (node) {
 690                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 691                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 692         } else {
 693                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 694                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 695         }
 696
 697         if (IS_ERR(dwc->usb2_phy)) {
 698                 ret = PTR_ERR(dwc->usb2_phy);
 699                 if (ret == -ENXIO || ret == -ENODEV) {
 700                         dwc->usb2_phy = NULL;
 701                 } else if (ret == -EPROBE_DEFER) {
 702                         return ret;
 703                 } else {
 704                         dev_err(dev, "no usb2 phy configured\n");
 705                         return ret;
 706                 }
 707         }
 708
 709         if (IS_ERR(dwc->usb3_phy)) {
 710                 ret = PTR_ERR(dwc->usb3_phy);
 711                 if (ret == -ENXIO || ret == -ENODEV) {
 712                         dwc->usb3_phy = NULL;
 713                 } else if (ret == -EPROBE_DEFER) {
 714                         return ret;
 715                 } else {
 716                         dev_err(dev, "no usb3 phy configured\n");
 717                         return ret;
 718                 }
 719         }
 720
 721         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 722         if (IS_ERR(dwc->usb2_generic_phy)) {
 723                 ret = PTR_ERR(dwc->usb2_generic_phy);
 724                 if (ret == -ENOSYS || ret == -ENODEV) {
 725                         dwc->usb2_generic_phy = NULL;
 726                 } else if (ret == -EPROBE_DEFER) {
 727                         return ret;
 728                 } else {
 729                         dev_err(dev, "no usb2 phy configured\n");
 730                         return ret;
 731                 }
 732         }
 733
 734         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 735         if (IS_ERR(dwc->usb3_generic_phy)) {
 736                 ret = PTR_ERR(dwc->usb3_generic_phy);
 737                 if (ret == -ENOSYS || ret == -ENODEV) {
 738                         dwc->usb3_generic_phy = NULL;
 739                 } else if (ret == -EPROBE_DEFER) {
 740                         return ret;
 741                 } else {
 742                         dev_err(dev, "no usb3 phy configured\n");
 743                         return ret;
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int dwc3_core_init_mode(struct dwc3 *dwc)
 751 {
 752         struct device *dev = dwc->dev;
 753         int ret;
 754
 755         switch (dwc->dr_mode) {
 756         case USB_DR_MODE_PERIPHERAL:
 757                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 758                 ret = dwc3_gadget_init(dwc);
 759                 if (ret) {
 760                         dev_err(dev, "failed to initialize gadget\n");
 761                         return ret;
 762                 }
 763                 break;
 764         case USB_DR_MODE_HOST:
 765                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 766                 ret = dwc3_host_init(dwc);
 767                 if (ret) {
 768                         dev_err(dev, "failed to initialize host\n");
 769                         return ret;
 770                 }
 771                 break;
 772         case USB_DR_MODE_OTG:
 773                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 774                 ret = dwc3_host_init(dwc);
 775                 if (ret) {
 776                         dev_err(dev, "failed to initialize host\n");
 777                         return ret;
 778                 }
 779
 780                 ret = dwc3_gadget_init(dwc);
 781                 if (ret) {
 782                         dev_err(dev, "failed to initialize gadget\n");
 783                         return ret;
 784                 }
 785                 break;
 786         default:
 787                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 788                 return -EINVAL;
 789         }
 790
 791         return 0;
 792 }
 793
 794 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 795 {
 796         switch (dwc->dr_mode) {
 797         case USB_DR_MODE_PERIPHERAL:
 798                 dwc3_gadget_exit(dwc);
 799                 break;
 800         case USB_DR_MODE_HOST:
 801                 dwc3_host_exit(dwc);
 802                 break;
 803         case USB_DR_MODE_OTG:
 804                 dwc3_host_exit(dwc);
 805                 dwc3_gadget_exit(dwc);
 806                 break;
 807         default:
 808                 /* do nothing */
 809                 break;
 810         }
 811 }
 812
 813 /* Returns true if the controller is capable of DRD. */
 814 bool dwc3_hw_is_drd(struct dwc3 *dwc)
 815 {
 816         u32 op_mode = DWC3_GHWPARAMS0_USB3_MODE(dwc->hwparams.hwparams0);
 817
 818         return (op_mode == DWC3_GHWPARAMS0_USB3_DRD);
 819 }
 820
 821 bool dwc3_force_mode(struct dwc3 *dwc, u32 mode)
 822 {
 823         u32                     reg;
 824         unsigned long           flags;
 825         struct usb_hcd          *hcd;
 826
 827         /*
 828          * Force mode has no effect if the hardware is not drd mode.
 829          */
 830         if (!dwc3_hw_is_drd(dwc))
 831                 return false;
 832         /*
 833          * If dr_mode is either peripheral or host only, there is no
 834          * need to ever force the mode to the opposite mode.
 835          */
 836         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_DEVICE &&
 837                     dwc->dr_mode == USB_DR_MODE_HOST))
 838                 return false;
 839
 840         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_HOST &&
 841                     dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 842                 return false;
 843
 844         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 845         if (DWC3_GCTL_PRTCAP(reg) == mode)
 846                 return false;
 847
 848         hcd = dev_get_drvdata(&dwc->xhci->dev);
 849
 850         switch (mode) {
 851         case DWC3_GCTL_PRTCAP_DEVICE:
 852                 if (hcd->state != HC_STATE_HALT) {
 853                         usb_remove_hcd(hcd->shared_hcd);
 854                         usb_remove_hcd(hcd);
 855                 }
 856
 857                 spin_lock_irqsave(&dwc->lock, flags);
 858                 dwc3_set_mode(dwc, mode);
 859                 dwc3_gadget_restart(dwc, true);
 860                 spin_unlock_irqrestore(&dwc->lock, flags);
 861
 862                 break;
 863         case DWC3_GCTL_PRTCAP_HOST:
 864                 spin_lock_irqsave(&dwc->lock, flags);
 865                 dwc3_gadget_restart(dwc, false);
 866                 dwc3_set_mode(dwc, mode);
 867                 spin_unlock_irqrestore(&dwc->lock, flags);
 868
 869                 if (hcd->state == HC_STATE_HALT) {
 870                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 871                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 872                 }
 873
 874                 break;
 875         default:
 876                 /* do nothing  */
 877                 break;
 878         }
 879
 880         return true;
 881 }
 882
 883 static void rockchip_otg_extcon_evt_worker(struct work_struct *work)
 884 {
 885         struct dwc3 *dwc =
 886                 container_of(work, struct dwc3, cable.otg_work.work);
 887         struct extcon_dev *edev = dwc->cable.edev;
 888         struct usb_hcd  *hcd;
 889         unsigned long   flags;
 890         int             ret;
 891         u32             reg;
 892
 893         if (extcon_get_cable_state_(edev, EXTCON_USB) > 0) {
 894                 dev_info(dwc->dev, "USB peripheral connected\n");
 895
 896                 if  (dwc->cable.connected) {
 897                         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 898
 899                         if (DWC3_GCTL_PRTCAP(reg) != DWC3_GCTL_PRTCAP_DEVICE) {
 900                                 spin_lock_irqsave(&dwc->lock, flags);
 901                                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 902                                 spin_unlock_irqrestore(&dwc->lock, flags);
 903                         }
 904
 905                         return;
 906                 }
 907
 908                 /*
 909                  * If dr_mode is host only, never to set
 910                  * the mode to the peripheral mode.
 911                  */
 912                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_HOST))
 913                         return;
 914
 915                 ret = phy_power_on(dwc->usb2_generic_phy);
 916                 if (ret < 0)
 917                         return;
 918
 919                 ret = phy_power_on(dwc->usb3_generic_phy);
 920                 if (ret < 0)
 921                         return;
 922
 923                 spin_lock_irqsave(&dwc->lock, flags);
 924
 925                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 926                 dwc3_gadget_restart(dwc, true);
 927
 928                 spin_unlock_irqrestore(&dwc->lock, flags);
 929
 930                 dwc->cable.connected = true;
 931         } else if (extcon_get_cable_state_(edev, EXTCON_USB_HOST) > 0) {
 932                 dev_info(dwc->dev, "USB HOST connected\n");
 933
 934                 if (dwc->cable.connected) {
 935                         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 936
 937                         if (DWC3_GCTL_PRTCAP(reg) != DWC3_GCTL_PRTCAP_HOST) {
 938                                 spin_lock_irqsave(&dwc->lock, flags);
 939                                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 940                                 spin_unlock_irqrestore(&dwc->lock, flags);
 941                         }
 942
 943                         return;
 944                 }
 945
 946                 /*
 947                  * If dr_mode is device only, never to
 948                  * set the mode to the host mode.
 949                  */
 950                 if (WARN_ON(dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 951                         return;
 952
 953                 ret = phy_power_on(dwc->usb2_generic_phy);
 954                 if (ret < 0)
 955                         return;
 956
 957                 ret = phy_power_on(dwc->usb3_generic_phy);
 958                 if (ret < 0)
 959                         return;
 960
 961                 hcd = dev_get_drvdata(&dwc->xhci->dev);
 962
 963                 spin_lock_irqsave(&dwc->lock, flags);
 964
 965                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 966
 967                 spin_unlock_irqrestore(&dwc->lock, flags);
 968
 969                 if (hcd->state == HC_STATE_HALT) {
 970                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 971                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 972                 }
 973
 974                 dwc->cable.connected = true;
 975         } else {
 976                 dev_info(dwc->dev, "USB unconnected\n");
 977
 978                 if (!dwc->cable.connected)
 979                         return;
 980
 981                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 982
 983                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_DEVICE ||
 984                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 985                         spin_lock_irqsave(&dwc->lock, flags);
 986                         dwc3_gadget_restart(dwc, false);
 987                         spin_unlock_irqrestore(&dwc->lock, flags);
 988                 }
 989
 990                 if (DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_HOST ||
 991                     DWC3_GCTL_PRTCAP(reg) == DWC3_GCTL_PRTCAP_OTG) {
 992                         hcd = dev_get_drvdata(&dwc->xhci->dev);
 993
 994                         if (hcd->state != HC_STATE_HALT) {
 995                                 usb_remove_hcd(hcd->shared_hcd);
 996                                 usb_remove_hcd(hcd);
 997                         }
 998                 }
 999
1000                 spin_lock_irqsave(&dwc->lock, flags);
1001
1002                 switch (dwc->dr_mode) {
1003                 case USB_DR_MODE_PERIPHERAL:
1004                         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1005                         break;
1006                 case USB_DR_MODE_HOST:
1007                         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
1008                         break;
1009                 case USB_DR_MODE_OTG:
1010                         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
1011                         break;
1012                 default:
1013                         return;
1014                 }
1015
1016                 spin_unlock_irqrestore(&dwc->lock, flags);
1017
1018                 phy_power_off(dwc->usb2_generic_phy);
1019                 phy_power_off(dwc->usb3_generic_phy);
1020
1021                 dwc->cable.connected = false;
1022         }
1023 }
1024
1025 static int dwc3_rockchip_device_notifier(struct notifier_block *nb,
1026                                          unsigned long event, void *ptr)
1027 {
1028         struct  dwc3 *dwc =
1029                 container_of(nb, struct dwc3, cable.device_nb);
1030
1031         schedule_delayed_work(&dwc->cable.otg_work, 0);
1032
1033         return NOTIFY_DONE;
1034 }
1035
1036 static int dwc3_rockchip_host_notifier(struct notifier_block *nb,
1037                                        unsigned long event, void *ptr)
1038 {
1039         struct  dwc3 *dwc =
1040                 container_of(nb, struct dwc3, cable.host_nb);
1041
1042         schedule_delayed_work(&dwc->cable.otg_work, 0);
1043
1044         return NOTIFY_DONE;
1045 }
1046
1047 #define DWC3_ALIGN_MASK         (16 - 1)
1048
1049 static int dwc3_probe(struct platform_device *pdev)
1050 {
1051         struct device           *dev = &pdev->dev;
1052         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
1053         struct resource         *res;
1054         struct dwc3             *dwc;
1055         u8                      lpm_nyet_threshold;
1056         u8                      tx_de_emphasis;
1057         u8                      hird_threshold;
1058         u32                     fladj = 0;
1059         struct extcon_dev       *edev;
1060
1061         int                     ret;
1062
1063         void __iomem            *regs;
1064         void                    *mem;
1065
1066         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
1067         if (!mem)
1068                 return -ENOMEM;
1069
1070         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
1071         dwc->mem = mem;
1072         dwc->dev = dev;
1073
1074         /* Try to set 64-bit DMA first */
1075         if (!pdev->dev.dma_mask)
1076                 /* Platform did not initialize dma_mask */
1077                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
1078                                                    DMA_BIT_MASK(64));
1079         else
1080                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1081
1082         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
1083         if (ret) {
1084                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1085                 if (ret)
1086                         return ret;
1087         }
1088
1089         if (device_property_read_bool(dev, "extcon")) {
1090                 edev = extcon_get_edev_by_phandle(dev, 0);
1091                 if (IS_ERR(edev)) {
1092                         if (PTR_ERR(edev) != -EPROBE_DEFER)
1093                                 dev_err(dev, "couldn't get extcon device\n");
1094                         return PTR_ERR(edev);
1095                 }
1096
1097                 /* Register for extcon notification */
1098                 INIT_DELAYED_WORK(&dwc->cable.otg_work,
1099                                   rockchip_otg_extcon_evt_worker);
1100                 dwc->cable.device_nb.notifier_call =
1101                                 dwc3_rockchip_device_notifier;
1102                 dwc->cable.host_nb.notifier_call =
1103                                 dwc3_rockchip_host_notifier;
1104
1105                 ret = extcon_register_notifier(edev, EXTCON_USB,
1106                                                &dwc->cable.device_nb);
1107                 if (ret < 0) {
1108                         dev_err(dev, "failed to register notifier for USB\n");
1109                         return ret;
1110                 }
1111
1112                 ret = extcon_register_notifier(edev, EXTCON_USB_HOST,
1113                                                &dwc->cable.host_nb);
1114                 if (ret < 0) {
1115                         dev_err(dev, "failed to register notifier for USB HOST\n");
1116                         extcon_unregister_notifier(edev, EXTCON_USB,
1117                                                    &dwc->cable.device_nb);
1118                         return ret;
1119                 }
1120
1121                 /*
1122                  * cable.connected flag is used for otg device/host
1123                  * connect status, true means connection and false
1124                  * means disconnection. However, we initialize the
1125                  * cable.connected with true, though nothing connect
1126                  * with the usb port. It aims to do phy power off
1127                  * and disable controller in cable.work.
1128                  */
1129                 dwc->cable.connected = true;
1130                 dwc->cable.edev = edev;
1131         }
1132
1133         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1134         if (!res) {
1135                 dev_err(dev, "missing IRQ\n");
1136                 return -ENODEV;
1137         }
1138         dwc->xhci_resources[1].start = res->start;
1139         dwc->xhci_resources[1].end = res->end;
1140         dwc->xhci_resources[1].flags = res->flags;
1141         dwc->xhci_resources[1].name = res->name;
1142
1143         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1144         if (!res) {
1145                 dev_err(dev, "missing memory resource\n");
1146                 return -ENODEV;
1147         }
1148
1149         dwc->xhci_resources[0].start = res->start;
1150         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1151                                         DWC3_XHCI_REGS_END;
1152         dwc->xhci_resources[0].flags = res->flags;
1153         dwc->xhci_resources[0].name = res->name;
1154
1155         res->start += DWC3_GLOBALS_REGS_START;
1156
1157         /*
1158          * Request memory region but exclude xHCI regs,
1159          * since it will be requested by the xhci-plat driver.
1160          */
1161         regs = devm_ioremap_resource(dev, res);
1162         if (IS_ERR(regs)) {
1163                 ret = PTR_ERR(regs);
1164                 goto err0;
1165         }
1166
1167         dwc->regs       = regs;
1168         dwc->regs_size  = resource_size(res);
1169
1170         /* default to highest possible threshold */
1171         lpm_nyet_threshold = 0xff;
1172
1173         /* default to -3.5dB de-emphasis */
1174         tx_de_emphasis = 1;
1175
1176         /*
1177          * default to assert utmi_sleep_n and use maximum allowed HIRD
1178          * threshold value of 0b1100
1179          */
1180         hird_threshold = 12;
1181
1182         dwc->maximum_speed = usb_get_maximum_speed(dev);
1183         dwc->dr_mode = usb_get_dr_mode(dev);
1184
1185         dwc->has_lpm_erratum = device_property_read_bool(dev,
1186                                 "snps,has-lpm-erratum");
1187         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1188                                 &lpm_nyet_threshold);
1189         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1190                                 "snps,is-utmi-l1-suspend");
1191         device_property_read_u8(dev, "snps,hird-threshold",
1192                                 &hird_threshold);
1193         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1194                                 "snps,usb3_lpm_capable");
1195
1196         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1197                                 "snps,disable_scramble_quirk");
1198         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1199                                 "snps,u2exit_lfps_quirk");
1200         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1201                                 "snps,u2ss_inp3_quirk");
1202         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1203                                 "snps,req_p1p2p3_quirk");
1204         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1205                                 "snps,del_p1p2p3_quirk");
1206         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1207                                 "snps,del_phy_power_chg_quirk");
1208         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1209                                 "snps,lfps_filter_quirk");
1210         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1211                                 "snps,rx_detect_poll_quirk");
1212         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1213                                 "snps,dis_u3_susphy_quirk");
1214         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1215                                 "snps,dis_u2_susphy_quirk");
1216         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1217                                 "snps,dis_enblslpm_quirk");
1218         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1219                                 "snps,dis_u2_freeclk_exists_quirk");
1220         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1221                                 "snps,dis_del_phy_power_chg_quirk");
1222         dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
1223                                 "snps,xhci_slow_suspend_quirk");
1224         dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
1225                                 "snps,phyif_utmi_16_bits");
1226
1227         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1228                                 "snps,tx_de_emphasis_quirk");
1229         device_property_read_u8(dev, "snps,tx_de_emphasis",
1230                                 &tx_de_emphasis);
1231         device_property_read_string(dev, "snps,hsphy_interface",
1232                                     &dwc->hsphy_interface);
1233         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1234                                  &fladj);
1235
1236         if (pdata) {
1237                 dwc->maximum_speed = pdata->maximum_speed;
1238                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1239                 if (pdata->lpm_nyet_threshold)
1240                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1241                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1242                 if (pdata->hird_threshold)
1243                         hird_threshold = pdata->hird_threshold;
1244
1245                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1246                 dwc->dr_mode = pdata->dr_mode;
1247
1248                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1249                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1250                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1251                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1252                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1253                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1254                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1255                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1256                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1257                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1258                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1259                 dwc->dis_u2_freeclk_exists_quirk =
1260                                         pdata->dis_u2_freeclk_exists_quirk;
1261                 dwc->dis_del_phy_power_chg_quirk =
1262                                         pdata->dis_del_phy_power_chg_quirk;
1263                 dwc->xhci_slow_suspend_quirk =
1264                                         pdata->xhci_slow_suspend_quirk;
1265                 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
1266
1267                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1268                 if (pdata->tx_de_emphasis)
1269                         tx_de_emphasis = pdata->tx_de_emphasis;
1270
1271                 dwc->hsphy_interface = pdata->hsphy_interface;
1272                 fladj = pdata->fladj_value;
1273         }
1274
1275         /* default to superspeed if no maximum_speed passed */
1276         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1277                 dwc->maximum_speed = USB_SPEED_SUPER;
1278
1279         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1280         dwc->tx_de_emphasis = tx_de_emphasis;
1281
1282         dwc->hird_threshold = hird_threshold
1283                 | (dwc->is_utmi_l1_suspend << 4);
1284
1285         platform_set_drvdata(pdev, dwc);
1286         dwc3_cache_hwparams(dwc);
1287
1288         ret = dwc3_phy_setup(dwc);
1289         if (ret)
1290                 goto err0;
1291
1292         ret = dwc3_core_get_phy(dwc);
1293         if (ret)
1294                 goto err0;
1295
1296         spin_lock_init(&dwc->lock);
1297
1298         if (!dev->dma_mask) {
1299                 dev->dma_mask = dev->parent->dma_mask;
1300                 dev->dma_parms = dev->parent->dma_parms;
1301                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1302         }
1303
1304         pm_runtime_enable(dev);
1305         pm_runtime_get_sync(dev);
1306         pm_runtime_forbid(dev);
1307
1308         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1309         if (ret) {
1310                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1311                 ret = -ENOMEM;
1312                 goto err1;
1313         }
1314
1315         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1316                 dwc->dr_mode = USB_DR_MODE_HOST;
1317         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1318                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1319
1320         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1321                 dwc->dr_mode = USB_DR_MODE_OTG;
1322
1323         ret = dwc3_core_init(dwc);
1324         if (ret) {
1325                 dev_err(dev, "failed to initialize core\n");
1326                 goto err1;
1327         }
1328
1329         /* Adjust Frame Length */
1330         dwc3_frame_length_adjustment(dwc, fladj);
1331
1332         usb_phy_set_suspend(dwc->usb2_phy, 0);
1333         usb_phy_set_suspend(dwc->usb3_phy, 0);
1334
1335         ret = phy_power_on(dwc->usb2_generic_phy);
1336         if (ret < 0)
1337                 goto err2;
1338
1339         ret = phy_power_on(dwc->usb3_generic_phy);
1340         if (ret < 0)
1341                 goto err3;
1342
1343         ret = dwc3_event_buffers_setup(dwc);
1344         if (ret) {
1345                 dev_err(dwc->dev, "failed to setup event buffers\n");
1346                 goto err4;
1347         }
1348
1349         ret = dwc3_core_init_mode(dwc);
1350         if (ret)
1351                 goto err5;
1352
1353         ret = dwc3_debugfs_init(dwc);
1354         if (ret) {
1355                 dev_err(dev, "failed to initialize debugfs\n");
1356                 goto err6;
1357         }
1358
1359         if (dwc->cable.edev)
1360                 schedule_delayed_work(&dwc->cable.otg_work, (2 * HZ));
1361
1362         pm_runtime_allow(dev);
1363
1364         return 0;
1365
1366 err6:
1367         dwc3_core_exit_mode(dwc);
1368
1369 err5:
1370         dwc3_event_buffers_cleanup(dwc);
1371
1372 err4:
1373         phy_power_off(dwc->usb3_generic_phy);
1374
1375 err3:
1376         phy_power_off(dwc->usb2_generic_phy);
1377
1378 err2:
1379         usb_phy_set_suspend(dwc->usb2_phy, 1);
1380         usb_phy_set_suspend(dwc->usb3_phy, 1);
1381         dwc3_core_exit(dwc);
1382
1383 err1:
1384         dwc3_free_event_buffers(dwc);
1385         dwc3_ulpi_exit(dwc);
1386
1387 err0:
1388         /*
1389          * restore res->start back to its original value so that, in case the
1390          * probe is deferred, we don't end up getting error in request the
1391          * memory region the next time probe is called.
1392          */
1393         res->start -= DWC3_GLOBALS_REGS_START;
1394
1395         return ret;
1396 }
1397
1398 static int dwc3_remove(struct platform_device *pdev)
1399 {
1400         struct dwc3     *dwc = platform_get_drvdata(pdev);
1401         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1402
1403         /*
1404          * restore res->start back to its original value so that, in case the
1405          * probe is deferred, we don't end up getting error in request the
1406          * memory region the next time probe is called.
1407          */
1408         res->start -= DWC3_GLOBALS_REGS_START;
1409
1410         dwc3_debugfs_exit(dwc);
1411         dwc3_core_exit_mode(dwc);
1412         dwc3_event_buffers_cleanup(dwc);
1413         dwc3_free_event_buffers(dwc);
1414
1415         usb_phy_set_suspend(dwc->usb2_phy, 1);
1416         usb_phy_set_suspend(dwc->usb3_phy, 1);
1417         phy_power_off(dwc->usb2_generic_phy);
1418         phy_power_off(dwc->usb3_generic_phy);
1419
1420         dwc3_core_exit(dwc);
1421         dwc3_ulpi_exit(dwc);
1422
1423         pm_runtime_put_sync(&pdev->dev);
1424         pm_runtime_disable(&pdev->dev);
1425
1426         return 0;
1427 }
1428
1429 #ifdef CONFIG_PM_SLEEP
1430 static int dwc3_suspend(struct device *dev)
1431 {
1432         struct dwc3     *dwc = dev_get_drvdata(dev);
1433         unsigned long   flags;
1434
1435         spin_lock_irqsave(&dwc->lock, flags);
1436
1437         switch (dwc->dr_mode) {
1438         case USB_DR_MODE_PERIPHERAL:
1439         case USB_DR_MODE_OTG:
1440                 dwc3_gadget_suspend(dwc);
1441                 /* FALLTHROUGH */
1442         case USB_DR_MODE_HOST:
1443         default:
1444                 dwc3_event_buffers_cleanup(dwc);
1445                 break;
1446         }
1447
1448         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1449         spin_unlock_irqrestore(&dwc->lock, flags);
1450
1451         usb_phy_shutdown(dwc->usb3_phy);
1452         usb_phy_shutdown(dwc->usb2_phy);
1453         phy_exit(dwc->usb2_generic_phy);
1454         phy_exit(dwc->usb3_generic_phy);
1455
1456         pinctrl_pm_select_sleep_state(dev);
1457
1458         return 0;
1459 }
1460
1461 static int dwc3_resume(struct device *dev)
1462 {
1463         struct dwc3     *dwc = dev_get_drvdata(dev);
1464         unsigned long   flags;
1465         int             ret;
1466
1467         pinctrl_pm_select_default_state(dev);
1468
1469         usb_phy_init(dwc->usb3_phy);
1470         usb_phy_init(dwc->usb2_phy);
1471         ret = phy_init(dwc->usb2_generic_phy);
1472         if (ret < 0)
1473                 return ret;
1474
1475         ret = phy_init(dwc->usb3_generic_phy);
1476         if (ret < 0)
1477                 goto err_usb2phy_init;
1478
1479         spin_lock_irqsave(&dwc->lock, flags);
1480
1481         dwc3_event_buffers_setup(dwc);
1482         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1483
1484         switch (dwc->dr_mode) {
1485         case USB_DR_MODE_PERIPHERAL:
1486         case USB_DR_MODE_OTG:
1487                 dwc3_gadget_resume(dwc);
1488                 /* FALLTHROUGH */
1489         case USB_DR_MODE_HOST:
1490         default:
1491                 /* do nothing */
1492                 break;
1493         }
1494
1495         spin_unlock_irqrestore(&dwc->lock, flags);
1496
1497         pm_runtime_disable(dev);
1498         pm_runtime_set_active(dev);
1499         pm_runtime_enable(dev);
1500
1501         return 0;
1502
1503 err_usb2phy_init:
1504         phy_exit(dwc->usb2_generic_phy);
1505
1506         return ret;
1507 }
1508
1509 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1510         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1511 };
1512
1513 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1514 #else
1515 #define DWC3_PM_OPS     NULL
1516 #endif
1517
1518 #ifdef CONFIG_OF
1519 static const struct of_device_id of_dwc3_match[] = {
1520         {
1521                 .compatible = "snps,dwc3"
1522         },
1523         {
1524                 .compatible = "synopsys,dwc3"
1525         },
1526         { },
1527 };
1528 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1529 #endif
1530
1531 #ifdef CONFIG_ACPI
1532
1533 #define ACPI_ID_INTEL_BSW       "808622B7"
1534
1535 static const struct acpi_device_id dwc3_acpi_match[] = {
1536         { ACPI_ID_INTEL_BSW, 0 },
1537         { },
1538 };
1539 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1540 #endif
1541
1542 static struct platform_driver dwc3_driver = {
1543         .probe          = dwc3_probe,
1544         .remove         = dwc3_remove,
1545         .driver         = {
1546                 .name   = "dwc3",
1547                 .of_match_table = of_match_ptr(of_dwc3_match),
1548                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1549                 .pm     = DWC3_PM_OPS,
1550         },
1551 };
1552
1553 module_platform_driver(dwc3_driver);
1554
1555 MODULE_ALIAS("platform:dwc3");
1556 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1557 MODULE_LICENSE("GPL v2");
1558 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");