drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37
  38 #include <linux/usb/ch9.h>
  39 #include <linux/usb/gadget.h>
  40 #include <linux/usb/of.h>
  41 #include <linux/usb/otg.h>
  42
  43 #include "platform_data.h"
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 /* -------------------------------------------------------------------------- */
  51
  52 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  53 {
  54         u32 reg;
  55
  56         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  57         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  58         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  59         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  60 }
  61
  62 /**
  63  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  64  * @dwc: pointer to our context structure
  65  */
  66 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  67 {
  68         u32             reg;
  69         int             ret;
  70
  71         /* Before Resetting PHY, put Core in Reset */
  72         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  73         reg |= DWC3_GCTL_CORESOFTRESET;
  74         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  75
  76         /* Assert USB3 PHY reset */
  77         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  78         reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  79         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  80
  81         /* Assert USB2 PHY reset */
  82         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  83         reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  84         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  85
  86         usb_phy_init(dwc->usb2_phy);
  87         usb_phy_init(dwc->usb3_phy);
  88         ret = phy_init(dwc->usb2_generic_phy);
  89         if (ret < 0)
  90                 return ret;
  91
  92         ret = phy_init(dwc->usb3_generic_phy);
  93         if (ret < 0) {
  94                 phy_exit(dwc->usb2_generic_phy);
  95                 return ret;
  96         }
  97         mdelay(100);
  98
  99         /* Clear USB3 PHY reset */
 100         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 101         reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
 102         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 103
 104         /* Clear USB2 PHY reset */
 105         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 106         reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
 107         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 108
 109         mdelay(100);
 110
 111         /* After PHYs are stable we can take Core out of reset state */
 112         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 113         reg &= ~DWC3_GCTL_CORESOFTRESET;
 114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 115
 116         return 0;
 117 }
 118
 119 /**
 120  * dwc3_soft_reset - Issue soft reset
 121  * @dwc: Pointer to our controller context structure
 122  */
 123 static int dwc3_soft_reset(struct dwc3 *dwc)
 124 {
 125         unsigned long timeout;
 126         u32 reg;
 127
 128         timeout = jiffies + msecs_to_jiffies(500);
 129         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 130         do {
 131                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 132                 if (!(reg & DWC3_DCTL_CSFTRST))
 133                         break;
 134
 135                 if (time_after(jiffies, timeout)) {
 136                         dev_err(dwc->dev, "Reset Timed Out\n");
 137                         return -ETIMEDOUT;
 138                 }
 139
 140                 cpu_relax();
 141         } while (true);
 142
 143         return 0;
 144 }
 145
 146 /**
 147  * dwc3_free_one_event_buffer - Frees one event buffer
 148  * @dwc: Pointer to our controller context structure
 149  * @evt: Pointer to event buffer to be freed
 150  */
 151 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 152                 struct dwc3_event_buffer *evt)
 153 {
 154         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 155 }
 156
 157 /**
 158  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 159  * @dwc: Pointer to our controller context structure
 160  * @length: size of the event buffer
 161  *
 162  * Returns a pointer to the allocated event buffer structure on success
 163  * otherwise ERR_PTR(errno).
 164  */
 165 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 166                 unsigned length)
 167 {
 168         struct dwc3_event_buffer        *evt;
 169
 170         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 171         if (!evt)
 172                 return ERR_PTR(-ENOMEM);
 173
 174         evt->dwc        = dwc;
 175         evt->length     = length;
 176         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 177                         &evt->dma, GFP_KERNEL);
 178         if (!evt->buf)
 179                 return ERR_PTR(-ENOMEM);
 180
 181         return evt;
 182 }
 183
 184 /**
 185  * dwc3_free_event_buffers - frees all allocated event buffers
 186  * @dwc: Pointer to our controller context structure
 187  */
 188 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 189 {
 190         struct dwc3_event_buffer        *evt;
 191         int i;
 192
 193         for (i = 0; i < dwc->num_event_buffers; i++) {
 194                 evt = dwc->ev_buffs[i];
 195                 if (evt)
 196                         dwc3_free_one_event_buffer(dwc, evt);
 197         }
 198 }
 199
 200 /**
 201  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 202  * @dwc: pointer to our controller context structure
 203  * @length: size of event buffer
 204  *
 205  * Returns 0 on success otherwise negative errno. In the error case, dwc
 206  * may contain some buffers allocated but not all which were requested.
 207  */
 208 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 209 {
 210         int                     num;
 211         int                     i;
 212
 213         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 214         dwc->num_event_buffers = num;
 215
 216         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 217                         GFP_KERNEL);
 218         if (!dwc->ev_buffs)
 219                 return -ENOMEM;
 220
 221         for (i = 0; i < num; i++) {
 222                 struct dwc3_event_buffer        *evt;
 223
 224                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 225                 if (IS_ERR(evt)) {
 226                         dev_err(dwc->dev, "can't allocate event buffer\n");
 227                         return PTR_ERR(evt);
 228                 }
 229                 dwc->ev_buffs[i] = evt;
 230         }
 231
 232         return 0;
 233 }
 234
 235 /**
 236  * dwc3_event_buffers_setup - setup our allocated event buffers
 237  * @dwc: pointer to our controller context structure
 238  *
 239  * Returns 0 on success otherwise negative errno.
 240  */
 241 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 242 {
 243         struct dwc3_event_buffer        *evt;
 244         int                             n;
 245
 246         for (n = 0; n < dwc->num_event_buffers; n++) {
 247                 evt = dwc->ev_buffs[n];
 248                 dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
 249                                 evt->buf, (unsigned long long) evt->dma,
 250                                 evt->length);
 251
 252                 evt->lpos = 0;
 253
 254                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 255                                 lower_32_bits(evt->dma));
 256                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 257                                 upper_32_bits(evt->dma));
 258                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 259                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 260                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 261         }
 262
 263         return 0;
 264 }
 265
 266 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 267 {
 268         struct dwc3_event_buffer        *evt;
 269         int                             n;
 270
 271         for (n = 0; n < dwc->num_event_buffers; n++) {
 272                 evt = dwc->ev_buffs[n];
 273
 274                 evt->lpos = 0;
 275
 276                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 277                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 278                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 279                                 | DWC3_GEVNTSIZ_SIZE(0));
 280                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 281         }
 282 }
 283
 284 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 285 {
 286         if (!dwc->has_hibernation)
 287                 return 0;
 288
 289         if (!dwc->nr_scratch)
 290                 return 0;
 291
 292         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 293                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 294         if (!dwc->scratchbuf)
 295                 return -ENOMEM;
 296
 297         return 0;
 298 }
 299
 300 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 301 {
 302         dma_addr_t scratch_addr;
 303         u32 param;
 304         int ret;
 305
 306         if (!dwc->has_hibernation)
 307                 return 0;
 308
 309         if (!dwc->nr_scratch)
 310                 return 0;
 311
 312          /* should never fall here */
 313         if (!WARN_ON(dwc->scratchbuf))
 314                 return 0;
 315
 316         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 317                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 318                         DMA_BIDIRECTIONAL);
 319         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 320                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 321                 ret = -EFAULT;
 322                 goto err0;
 323         }
 324
 325         dwc->scratch_addr = scratch_addr;
 326
 327         param = lower_32_bits(scratch_addr);
 328
 329         ret = dwc3_send_gadget_generic_command(dwc,
 330                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 331         if (ret < 0)
 332                 goto err1;
 333
 334         param = upper_32_bits(scratch_addr);
 335
 336         ret = dwc3_send_gadget_generic_command(dwc,
 337                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 338         if (ret < 0)
 339                 goto err1;
 340
 341         return 0;
 342
 343 err1:
 344         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 345                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 346
 347 err0:
 348         return ret;
 349 }
 350
 351 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 352 {
 353         if (!dwc->has_hibernation)
 354                 return;
 355
 356         if (!dwc->nr_scratch)
 357                 return;
 358
 359          /* should never fall here */
 360         if (!WARN_ON(dwc->scratchbuf))
 361                 return;
 362
 363         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 364                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 365         kfree(dwc->scratchbuf);
 366 }
 367
 368 static void dwc3_core_num_eps(struct dwc3 *dwc)
 369 {
 370         struct dwc3_hwparams    *parms = &dwc->hwparams;
 371
 372         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 373         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 374
 375         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 376                         dwc->num_in_eps, dwc->num_out_eps);
 377 }
 378
 379 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 380 {
 381         struct dwc3_hwparams    *parms = &dwc->hwparams;
 382
 383         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 384         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 385         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 386         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 387         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 388         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 389         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 390         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 391         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 392 }
 393
 394 /**
 395  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 396  * @dwc: Pointer to our controller context structure
 397  */
 398 static void dwc3_phy_setup(struct dwc3 *dwc)
 399 {
 400         u32 reg;
 401
 402         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 403
 404         /*
 405          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 406          * to '0' during coreConsultant configuration. So default value
 407          * will be '0' when the core is reset. Application needs to set it
 408          * to '1' after the core initialization is completed.
 409          */
 410         if (dwc->revision > DWC3_REVISION_194A)
 411                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 412
 413         if (dwc->u2ss_inp3_quirk)
 414                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 415
 416         if (dwc->req_p1p2p3_quirk)
 417                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 418
 419         if (dwc->del_p1p2p3_quirk)
 420                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 421
 422         if (dwc->del_phy_power_chg_quirk)
 423                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 424
 425         if (dwc->lfps_filter_quirk)
 426                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 427
 428         if (dwc->rx_detect_poll_quirk)
 429                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 430
 431         if (dwc->tx_de_emphasis_quirk)
 432                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 433
 434         if (dwc->dis_u3_susphy_quirk)
 435                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 436
 437         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 438
 439         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 440
 441         /*
 442          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 443          * '0' during coreConsultant configuration. So default value will
 444          * be '0' when the core is reset. Application needs to set it to
 445          * '1' after the core initialization is completed.
 446          */
 447         if (dwc->revision > DWC3_REVISION_194A)
 448                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 449
 450         if (dwc->dis_u2_susphy_quirk)
 451                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 452
 453         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 454 }
 455
 456 /**
 457  * dwc3_core_init - Low-level initialization of DWC3 Core
 458  * @dwc: Pointer to our controller context structure
 459  *
 460  * Returns 0 on success otherwise negative errno.
 461  */
 462 static int dwc3_core_init(struct dwc3 *dwc)
 463 {
 464         u32                     hwparams4 = dwc->hwparams.hwparams4;
 465         u32                     reg;
 466         int                     ret;
 467
 468         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 469         /* This should read as U3 followed by revision number */
 470         if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
 471                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 472                 ret = -ENODEV;
 473                 goto err0;
 474         }
 475         dwc->revision = reg;
 476
 477         /*
 478          * Write Linux Version Code to our GUID register so it's easy to figure
 479          * out which kernel version a bug was found.
 480          */
 481         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 482
 483         /* Handle USB2.0-only core configuration */
 484         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 485                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 486                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 487                         dwc->maximum_speed = USB_SPEED_HIGH;
 488         }
 489
 490         /* issue device SoftReset too */
 491         ret = dwc3_soft_reset(dwc);
 492         if (ret)
 493                 goto err0;
 494
 495         ret = dwc3_core_soft_reset(dwc);
 496         if (ret)
 497                 goto err0;
 498
 499         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 500         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 501
 502         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 503         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 504                 /**
 505                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 506                  * issue which would cause xHCI compliance tests to fail.
 507                  *
 508                  * Because of that we cannot enable clock gating on such
 509                  * configurations.
 510                  *
 511                  * Refers to:
 512                  *
 513                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 514                  * SOF/ITP Mode Used
 515                  */
 516                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 517                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 518                                 (dwc->revision >= DWC3_REVISION_210A &&
 519                                 dwc->revision <= DWC3_REVISION_250A))
 520                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 521                 else
 522                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 523                 break;
 524         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 525                 /* enable hibernation here */
 526                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 527
 528                 /*
 529                  * REVISIT Enabling this bit so that host-mode hibernation
 530                  * will work. Device-mode hibernation is not yet implemented.
 531                  */
 532                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 533                 break;
 534         default:
 535                 dev_dbg(dwc->dev, "No power optimization available\n");
 536         }
 537
 538         /* check if current dwc3 is on simulation board */
 539         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 540                 dev_dbg(dwc->dev, "it is on FPGA board\n");
 541                 dwc->is_fpga = true;
 542         }
 543
 544         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 545                         "disable_scramble cannot be used on non-FPGA builds\n");
 546
 547         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 548                 reg |= DWC3_GCTL_DISSCRAMBLE;
 549         else
 550                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 551
 552         if (dwc->u2exit_lfps_quirk)
 553                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 554
 555         /*
 556          * WORKAROUND: DWC3 revisions <1.90a have a bug
 557          * where the device can fail to connect at SuperSpeed
 558          * and falls back to high-speed mode which causes
 559          * the device to enter a Connect/Disconnect loop
 560          */
 561         if (dwc->revision < DWC3_REVISION_190A)
 562                 reg |= DWC3_GCTL_U2RSTECN;
 563
 564         dwc3_core_num_eps(dwc);
 565
 566         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 567
 568         ret = dwc3_alloc_scratch_buffers(dwc);
 569         if (ret)
 570                 goto err1;
 571
 572         ret = dwc3_setup_scratch_buffers(dwc);
 573         if (ret)
 574                 goto err2;
 575
 576         return 0;
 577
 578 err2:
 579         dwc3_free_scratch_buffers(dwc);
 580
 581 err1:
 582         usb_phy_shutdown(dwc->usb2_phy);
 583         usb_phy_shutdown(dwc->usb3_phy);
 584         phy_exit(dwc->usb2_generic_phy);
 585         phy_exit(dwc->usb3_generic_phy);
 586
 587 err0:
 588         return ret;
 589 }
 590
 591 static void dwc3_core_exit(struct dwc3 *dwc)
 592 {
 593         dwc3_free_scratch_buffers(dwc);
 594         usb_phy_shutdown(dwc->usb2_phy);
 595         usb_phy_shutdown(dwc->usb3_phy);
 596         phy_exit(dwc->usb2_generic_phy);
 597         phy_exit(dwc->usb3_generic_phy);
 598 }
 599
 600 static int dwc3_core_get_phy(struct dwc3 *dwc)
 601 {
 602         struct device           *dev = dwc->dev;
 603         struct device_node      *node = dev->of_node;
 604         int ret;
 605
 606         if (node) {
 607                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 608                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 609         } else {
 610                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 611                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 612         }
 613
 614         if (IS_ERR(dwc->usb2_phy)) {
 615                 ret = PTR_ERR(dwc->usb2_phy);
 616                 if (ret == -ENXIO || ret == -ENODEV) {
 617                         dwc->usb2_phy = NULL;
 618                 } else if (ret == -EPROBE_DEFER) {
 619                         return ret;
 620                 } else {
 621                         dev_err(dev, "no usb2 phy configured\n");
 622                         return ret;
 623                 }
 624         }
 625
 626         if (IS_ERR(dwc->usb3_phy)) {
 627                 ret = PTR_ERR(dwc->usb3_phy);
 628                 if (ret == -ENXIO || ret == -ENODEV) {
 629                         dwc->usb3_phy = NULL;
 630                 } else if (ret == -EPROBE_DEFER) {
 631                         return ret;
 632                 } else {
 633                         dev_err(dev, "no usb3 phy configured\n");
 634                         return ret;
 635                 }
 636         }
 637
 638         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 639         if (IS_ERR(dwc->usb2_generic_phy)) {
 640                 ret = PTR_ERR(dwc->usb2_generic_phy);
 641                 if (ret == -ENOSYS || ret == -ENODEV) {
 642                         dwc->usb2_generic_phy = NULL;
 643                 } else if (ret == -EPROBE_DEFER) {
 644                         return ret;
 645                 } else {
 646                         dev_err(dev, "no usb2 phy configured\n");
 647                         return ret;
 648                 }
 649         }
 650
 651         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 652         if (IS_ERR(dwc->usb3_generic_phy)) {
 653                 ret = PTR_ERR(dwc->usb3_generic_phy);
 654                 if (ret == -ENOSYS || ret == -ENODEV) {
 655                         dwc->usb3_generic_phy = NULL;
 656                 } else if (ret == -EPROBE_DEFER) {
 657                         return ret;
 658                 } else {
 659                         dev_err(dev, "no usb3 phy configured\n");
 660                         return ret;
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 static int dwc3_core_init_mode(struct dwc3 *dwc)
 668 {
 669         struct device *dev = dwc->dev;
 670         int ret;
 671
 672         switch (dwc->dr_mode) {
 673         case USB_DR_MODE_PERIPHERAL:
 674                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 675                 ret = dwc3_gadget_init(dwc);
 676                 if (ret) {
 677                         dev_err(dev, "failed to initialize gadget\n");
 678                         return ret;
 679                 }
 680                 break;
 681         case USB_DR_MODE_HOST:
 682                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 683                 ret = dwc3_host_init(dwc);
 684                 if (ret) {
 685                         dev_err(dev, "failed to initialize host\n");
 686                         return ret;
 687                 }
 688                 break;
 689         case USB_DR_MODE_OTG:
 690                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 691                 ret = dwc3_host_init(dwc);
 692                 if (ret) {
 693                         dev_err(dev, "failed to initialize host\n");
 694                         return ret;
 695                 }
 696
 697                 ret = dwc3_gadget_init(dwc);
 698                 if (ret) {
 699                         dev_err(dev, "failed to initialize gadget\n");
 700                         return ret;
 701                 }
 702                 break;
 703         default:
 704                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 705                 return -EINVAL;
 706         }
 707
 708         return 0;
 709 }
 710
 711 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 712 {
 713         switch (dwc->dr_mode) {
 714         case USB_DR_MODE_PERIPHERAL:
 715                 dwc3_gadget_exit(dwc);
 716                 break;
 717         case USB_DR_MODE_HOST:
 718                 dwc3_host_exit(dwc);
 719                 break;
 720         case USB_DR_MODE_OTG:
 721                 dwc3_host_exit(dwc);
 722                 dwc3_gadget_exit(dwc);
 723                 break;
 724         default:
 725                 /* do nothing */
 726                 break;
 727         }
 728 }
 729
 730 #define DWC3_ALIGN_MASK         (16 - 1)
 731
 732 static int dwc3_probe(struct platform_device *pdev)
 733 {
 734         struct device           *dev = &pdev->dev;
 735         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 736         struct device_node      *node = dev->of_node;
 737         struct resource         *res;
 738         struct dwc3             *dwc;
 739         u8                      lpm_nyet_threshold;
 740         u8                      tx_de_emphasis;
 741         u8                      hird_threshold;
 742
 743         int                     ret;
 744
 745         void __iomem            *regs;
 746         void                    *mem;
 747
 748         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 749         if (!mem)
 750                 return -ENOMEM;
 751
 752         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 753         dwc->mem = mem;
 754         dwc->dev = dev;
 755
 756         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 757         if (!res) {
 758                 dev_err(dev, "missing IRQ\n");
 759                 return -ENODEV;
 760         }
 761         dwc->xhci_resources[1].start = res->start;
 762         dwc->xhci_resources[1].end = res->end;
 763         dwc->xhci_resources[1].flags = res->flags;
 764         dwc->xhci_resources[1].name = res->name;
 765
 766         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 767         if (!res) {
 768                 dev_err(dev, "missing memory resource\n");
 769                 return -ENODEV;
 770         }
 771
 772         dwc->xhci_resources[0].start = res->start;
 773         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 774                                         DWC3_XHCI_REGS_END;
 775         dwc->xhci_resources[0].flags = res->flags;
 776         dwc->xhci_resources[0].name = res->name;
 777
 778         res->start += DWC3_GLOBALS_REGS_START;
 779
 780         /*
 781          * Request memory region but exclude xHCI regs,
 782          * since it will be requested by the xhci-plat driver.
 783          */
 784         regs = devm_ioremap_resource(dev, res);
 785         if (IS_ERR(regs)) {
 786                 ret = PTR_ERR(regs);
 787                 goto err0;
 788         }
 789
 790         dwc->regs       = regs;
 791         dwc->regs_size  = resource_size(res);
 792
 793         /* default to highest possible threshold */
 794         lpm_nyet_threshold = 0xff;
 795
 796         /* default to -3.5dB de-emphasis */
 797         tx_de_emphasis = 1;
 798
 799         /*
 800          * default to assert utmi_sleep_n and use maximum allowed HIRD
 801          * threshold value of 0b1100
 802          */
 803         hird_threshold = 12;
 804
 805         if (node) {
 806                 dwc->maximum_speed = of_usb_get_maximum_speed(node);
 807                 dwc->has_lpm_erratum = of_property_read_bool(node,
 808                                 "snps,has-lpm-erratum");
 809                 of_property_read_u8(node, "snps,lpm-nyet-threshold",
 810                                 &lpm_nyet_threshold);
 811                 dwc->is_utmi_l1_suspend = of_property_read_bool(node,
 812                                 "snps,is-utmi-l1-suspend");
 813                 of_property_read_u8(node, "snps,hird-threshold",
 814                                 &hird_threshold);
 815                 dwc->usb3_lpm_capable = of_property_read_bool(node,
 816                                 "snps,usb3_lpm_capable");
 817
 818                 dwc->needs_fifo_resize = of_property_read_bool(node,
 819                                 "tx-fifo-resize");
 820                 dwc->dr_mode = of_usb_get_dr_mode(node);
 821
 822                 dwc->disable_scramble_quirk = of_property_read_bool(node,
 823                                 "snps,disable_scramble_quirk");
 824                 dwc->u2exit_lfps_quirk = of_property_read_bool(node,
 825                                 "snps,u2exit_lfps_quirk");
 826                 dwc->u2ss_inp3_quirk = of_property_read_bool(node,
 827                                 "snps,u2ss_inp3_quirk");
 828                 dwc->req_p1p2p3_quirk = of_property_read_bool(node,
 829                                 "snps,req_p1p2p3_quirk");
 830                 dwc->del_p1p2p3_quirk = of_property_read_bool(node,
 831                                 "snps,del_p1p2p3_quirk");
 832                 dwc->del_phy_power_chg_quirk = of_property_read_bool(node,
 833                                 "snps,del_phy_power_chg_quirk");
 834                 dwc->lfps_filter_quirk = of_property_read_bool(node,
 835                                 "snps,lfps_filter_quirk");
 836                 dwc->rx_detect_poll_quirk = of_property_read_bool(node,
 837                                 "snps,rx_detect_poll_quirk");
 838                 dwc->dis_u3_susphy_quirk = of_property_read_bool(node,
 839                                 "snps,dis_u3_susphy_quirk");
 840                 dwc->dis_u2_susphy_quirk = of_property_read_bool(node,
 841                                 "snps,dis_u2_susphy_quirk");
 842
 843                 dwc->tx_de_emphasis_quirk = of_property_read_bool(node,
 844                                 "snps,tx_de_emphasis_quirk");
 845                 of_property_read_u8(node, "snps,tx_de_emphasis",
 846                                 &tx_de_emphasis);
 847         } else if (pdata) {
 848                 dwc->maximum_speed = pdata->maximum_speed;
 849                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
 850                 if (pdata->lpm_nyet_threshold)
 851                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
 852                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
 853                 if (pdata->hird_threshold)
 854                         hird_threshold = pdata->hird_threshold;
 855
 856                 dwc->needs_fifo_resize = pdata->tx_fifo_resize;
 857                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
 858                 dwc->dr_mode = pdata->dr_mode;
 859
 860                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
 861                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
 862                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
 863                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
 864                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
 865                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
 866                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
 867                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
 868                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
 869                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
 870
 871                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
 872                 if (pdata->tx_de_emphasis)
 873                         tx_de_emphasis = pdata->tx_de_emphasis;
 874         }
 875
 876         /* default to superspeed if no maximum_speed passed */
 877         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
 878                 dwc->maximum_speed = USB_SPEED_SUPER;
 879
 880         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
 881         dwc->tx_de_emphasis = tx_de_emphasis;
 882
 883         dwc->hird_threshold = hird_threshold
 884                 | (dwc->is_utmi_l1_suspend << 4);
 885
 886         platform_set_drvdata(pdev, dwc);
 887         dwc3_cache_hwparams(dwc);
 888
 889         dwc3_phy_setup(dwc);
 890
 891         ret = dwc3_core_get_phy(dwc);
 892         if (ret)
 893                 goto err0;
 894
 895         spin_lock_init(&dwc->lock);
 896
 897         if (!dev->dma_mask) {
 898                 dev->dma_mask = dev->parent->dma_mask;
 899                 dev->dma_parms = dev->parent->dma_parms;
 900                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
 901         }
 902
 903         pm_runtime_enable(dev);
 904         pm_runtime_get_sync(dev);
 905         pm_runtime_forbid(dev);
 906
 907         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
 908         if (ret) {
 909                 dev_err(dwc->dev, "failed to allocate event buffers\n");
 910                 ret = -ENOMEM;
 911                 goto err1;
 912         }
 913
 914         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
 915                 dwc->dr_mode = USB_DR_MODE_HOST;
 916         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
 917                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
 918
 919         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
 920                 dwc->dr_mode = USB_DR_MODE_OTG;
 921
 922         ret = dwc3_core_init(dwc);
 923         if (ret) {
 924                 dev_err(dev, "failed to initialize core\n");
 925                 goto err1;
 926         }
 927
 928         usb_phy_set_suspend(dwc->usb2_phy, 0);
 929         usb_phy_set_suspend(dwc->usb3_phy, 0);
 930         ret = phy_power_on(dwc->usb2_generic_phy);
 931         if (ret < 0)
 932                 goto err2;
 933
 934         ret = phy_power_on(dwc->usb3_generic_phy);
 935         if (ret < 0)
 936                 goto err3;
 937
 938         ret = dwc3_event_buffers_setup(dwc);
 939         if (ret) {
 940                 dev_err(dwc->dev, "failed to setup event buffers\n");
 941                 goto err4;
 942         }
 943
 944         ret = dwc3_core_init_mode(dwc);
 945         if (ret)
 946                 goto err5;
 947
 948         ret = dwc3_debugfs_init(dwc);
 949         if (ret) {
 950                 dev_err(dev, "failed to initialize debugfs\n");
 951                 goto err6;
 952         }
 953
 954         pm_runtime_allow(dev);
 955
 956         return 0;
 957
 958 err6:
 959         dwc3_core_exit_mode(dwc);
 960
 961 err5:
 962         dwc3_event_buffers_cleanup(dwc);
 963
 964 err4:
 965         phy_power_off(dwc->usb3_generic_phy);
 966
 967 err3:
 968         phy_power_off(dwc->usb2_generic_phy);
 969
 970 err2:
 971         usb_phy_set_suspend(dwc->usb2_phy, 1);
 972         usb_phy_set_suspend(dwc->usb3_phy, 1);
 973         dwc3_core_exit(dwc);
 974
 975 err1:
 976         dwc3_free_event_buffers(dwc);
 977
 978 err0:
 979         /*
 980          * restore res->start back to its original value so that, in case the
 981          * probe is deferred, we don't end up getting error in request the
 982          * memory region the next time probe is called.
 983          */
 984         res->start -= DWC3_GLOBALS_REGS_START;
 985
 986         return ret;
 987 }
 988
 989 static int dwc3_remove(struct platform_device *pdev)
 990 {
 991         struct dwc3     *dwc = platform_get_drvdata(pdev);
 992         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 993
 994         /*
 995          * restore res->start back to its original value so that, in case the
 996          * probe is deferred, we don't end up getting error in request the
 997          * memory region the next time probe is called.
 998          */
 999         res->start -= DWC3_GLOBALS_REGS_START;
1000
1001         dwc3_debugfs_exit(dwc);
1002         dwc3_core_exit_mode(dwc);
1003         dwc3_event_buffers_cleanup(dwc);
1004         dwc3_free_event_buffers(dwc);
1005
1006         usb_phy_set_suspend(dwc->usb2_phy, 1);
1007         usb_phy_set_suspend(dwc->usb3_phy, 1);
1008         phy_power_off(dwc->usb2_generic_phy);
1009         phy_power_off(dwc->usb3_generic_phy);
1010
1011         dwc3_core_exit(dwc);
1012
1013         pm_runtime_put_sync(&pdev->dev);
1014         pm_runtime_disable(&pdev->dev);
1015
1016         return 0;
1017 }
1018
1019 #ifdef CONFIG_PM_SLEEP
1020 static int dwc3_suspend(struct device *dev)
1021 {
1022         struct dwc3     *dwc = dev_get_drvdata(dev);
1023         unsigned long   flags;
1024
1025         spin_lock_irqsave(&dwc->lock, flags);
1026
1027         switch (dwc->dr_mode) {
1028         case USB_DR_MODE_PERIPHERAL:
1029         case USB_DR_MODE_OTG:
1030                 dwc3_gadget_suspend(dwc);
1031                 /* FALLTHROUGH */
1032         case USB_DR_MODE_HOST:
1033         default:
1034                 dwc3_event_buffers_cleanup(dwc);
1035                 break;
1036         }
1037
1038         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1039         spin_unlock_irqrestore(&dwc->lock, flags);
1040
1041         usb_phy_shutdown(dwc->usb3_phy);
1042         usb_phy_shutdown(dwc->usb2_phy);
1043         phy_exit(dwc->usb2_generic_phy);
1044         phy_exit(dwc->usb3_generic_phy);
1045
1046         return 0;
1047 }
1048
1049 static int dwc3_resume(struct device *dev)
1050 {
1051         struct dwc3     *dwc = dev_get_drvdata(dev);
1052         unsigned long   flags;
1053         int             ret;
1054
1055         usb_phy_init(dwc->usb3_phy);
1056         usb_phy_init(dwc->usb2_phy);
1057         ret = phy_init(dwc->usb2_generic_phy);
1058         if (ret < 0)
1059                 return ret;
1060
1061         ret = phy_init(dwc->usb3_generic_phy);
1062         if (ret < 0)
1063                 goto err_usb2phy_init;
1064
1065         spin_lock_irqsave(&dwc->lock, flags);
1066
1067         dwc3_event_buffers_setup(dwc);
1068         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1069
1070         switch (dwc->dr_mode) {
1071         case USB_DR_MODE_PERIPHERAL:
1072         case USB_DR_MODE_OTG:
1073                 dwc3_gadget_resume(dwc);
1074                 /* FALLTHROUGH */
1075         case USB_DR_MODE_HOST:
1076         default:
1077                 /* do nothing */
1078                 break;
1079         }
1080
1081         spin_unlock_irqrestore(&dwc->lock, flags);
1082
1083         pm_runtime_disable(dev);
1084         pm_runtime_set_active(dev);
1085         pm_runtime_enable(dev);
1086
1087         return 0;
1088
1089 err_usb2phy_init:
1090         phy_exit(dwc->usb2_generic_phy);
1091
1092         return ret;
1093 }
1094
1095 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1096         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1097 };
1098
1099 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1100 #else
1101 #define DWC3_PM_OPS     NULL
1102 #endif
1103
1104 #ifdef CONFIG_OF
1105 static const struct of_device_id of_dwc3_match[] = {
1106         {
1107                 .compatible = "snps,dwc3"
1108         },
1109         {
1110                 .compatible = "synopsys,dwc3"
1111         },
1112         { },
1113 };
1114 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1115 #endif
1116
1117 #ifdef CONFIG_ACPI
1118
1119 #define ACPI_ID_INTEL_BSW       "808622B7"
1120
1121 static const struct acpi_device_id dwc3_acpi_match[] = {
1122         { ACPI_ID_INTEL_BSW, 0 },
1123         { },
1124 };
1125 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1126 #endif
1127
1128 static struct platform_driver dwc3_driver = {
1129         .probe          = dwc3_probe,
1130         .remove         = dwc3_remove,
1131         .driver         = {
1132                 .name   = "dwc3",
1133                 .of_match_table = of_match_ptr(of_dwc3_match),
1134                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1135                 .pm     = DWC3_PM_OPS,
1136         },
1137 };
1138
1139 module_platform_driver(dwc3_driver);
1140
1141 MODULE_ALIAS("platform:dwc3");
1142 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1143 MODULE_LICENSE("GPL v2");
1144 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");