drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "platform_data.h"
  45 #include "core.h"
  46 #include "gadget.h"
  47 #include "io.h"
  48
  49 #include "debug.h"
  50
  51 /* -------------------------------------------------------------------------- */
  52
  53 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  54 {
  55         u32 reg;
  56
  57         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  58         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  59         reg |= DWC3_GCTL_PRTCAPDIR(mode);
  60         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  61 }
  62
  63 /**
  64  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  65  * @dwc: pointer to our context structure
  66  */
  67 static int dwc3_core_soft_reset(struct dwc3 *dwc)
  68 {
  69         u32             reg;
  70         int             retries = 1000;
  71         int             ret;
  72
  73         usb_phy_init(dwc->usb2_phy);
  74         usb_phy_init(dwc->usb3_phy);
  75         ret = phy_init(dwc->usb2_generic_phy);
  76         if (ret < 0)
  77                 return ret;
  78
  79         ret = phy_init(dwc->usb3_generic_phy);
  80         if (ret < 0) {
  81                 phy_exit(dwc->usb2_generic_phy);
  82                 return ret;
  83         }
  84
  85         /*
  86          * We're resetting only the device side because, if we're in host mode,
  87          * XHCI driver will reset the host block. If dwc3 was configured for
  88          * host-only mode, then we can return early.
  89          */
  90         if (dwc->dr_mode == USB_DR_MODE_HOST)
  91                 return 0;
  92
  93         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  94         reg |= DWC3_DCTL_CSFTRST;
  95         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
  96
  97         do {
  98                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  99                 if (!(reg & DWC3_DCTL_CSFTRST))
 100                         return 0;
 101
 102                 udelay(1);
 103         } while (--retries);
 104
 105         return -ETIMEDOUT;
 106 }
 107
 108 /**
 109  * dwc3_soft_reset - Issue soft reset
 110  * @dwc: Pointer to our controller context structure
 111  */
 112 int dwc3_soft_reset(struct dwc3 *dwc)
 113 {
 114         unsigned long timeout;
 115         u32 reg;
 116
 117         timeout = jiffies + msecs_to_jiffies(500);
 118         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 119         do {
 120                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 121                 if (!(reg & DWC3_DCTL_CSFTRST))
 122                         break;
 123
 124                 if (time_after(jiffies, timeout)) {
 125                         dev_err(dwc->dev, "Reset Timed Out\n");
 126                         return -ETIMEDOUT;
 127                 }
 128
 129                 cpu_relax();
 130         } while (true);
 131
 132         return 0;
 133 }
 134
 135 /*
 136  * dwc3_frame_length_adjustment - Adjusts frame length if required
 137  * @dwc3: Pointer to our controller context structure
 138  * @fladj: Value of GFLADJ_30MHZ to adjust frame length
 139  */
 140 static void dwc3_frame_length_adjustment(struct dwc3 *dwc, u32 fladj)
 141 {
 142         u32 reg;
 143         u32 dft;
 144
 145         if (dwc->revision < DWC3_REVISION_250A)
 146                 return;
 147
 148         if (fladj == 0)
 149                 return;
 150
 151         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 152         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 153         if (!dev_WARN_ONCE(dwc->dev, dft == fladj,
 154             "request value same as default, ignoring\n")) {
 155                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 156                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | fladj;
 157                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 158         }
 159 }
 160
 161 /**
 162  * dwc3_free_one_event_buffer - Frees one event buffer
 163  * @dwc: Pointer to our controller context structure
 164  * @evt: Pointer to event buffer to be freed
 165  */
 166 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 167                 struct dwc3_event_buffer *evt)
 168 {
 169         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 170 }
 171
 172 /**
 173  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 174  * @dwc: Pointer to our controller context structure
 175  * @length: size of the event buffer
 176  *
 177  * Returns a pointer to the allocated event buffer structure on success
 178  * otherwise ERR_PTR(errno).
 179  */
 180 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 181                 unsigned length)
 182 {
 183         struct dwc3_event_buffer        *evt;
 184
 185         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 186         if (!evt)
 187                 return ERR_PTR(-ENOMEM);
 188
 189         evt->dwc        = dwc;
 190         evt->length     = length;
 191         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 192                         &evt->dma, GFP_KERNEL);
 193         if (!evt->buf)
 194                 return ERR_PTR(-ENOMEM);
 195
 196         return evt;
 197 }
 198
 199 /**
 200  * dwc3_free_event_buffers - frees all allocated event buffers
 201  * @dwc: Pointer to our controller context structure
 202  */
 203 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 204 {
 205         struct dwc3_event_buffer        *evt;
 206         int i;
 207
 208         for (i = 0; i < dwc->num_event_buffers; i++) {
 209                 evt = dwc->ev_buffs[i];
 210                 if (evt)
 211                         dwc3_free_one_event_buffer(dwc, evt);
 212         }
 213 }
 214
 215 /**
 216  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 217  * @dwc: pointer to our controller context structure
 218  * @length: size of event buffer
 219  *
 220  * Returns 0 on success otherwise negative errno. In the error case, dwc
 221  * may contain some buffers allocated but not all which were requested.
 222  */
 223 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 224 {
 225         int                     num;
 226         int                     i;
 227
 228         num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
 229         dwc->num_event_buffers = num;
 230
 231         dwc->ev_buffs = devm_kzalloc(dwc->dev, sizeof(*dwc->ev_buffs) * num,
 232                         GFP_KERNEL);
 233         if (!dwc->ev_buffs)
 234                 return -ENOMEM;
 235
 236         for (i = 0; i < num; i++) {
 237                 struct dwc3_event_buffer        *evt;
 238
 239                 evt = dwc3_alloc_one_event_buffer(dwc, length);
 240                 if (IS_ERR(evt)) {
 241                         dev_err(dwc->dev, "can't allocate event buffer\n");
 242                         return PTR_ERR(evt);
 243                 }
 244                 dwc->ev_buffs[i] = evt;
 245         }
 246
 247         return 0;
 248 }
 249
 250 /**
 251  * dwc3_event_buffers_setup - setup our allocated event buffers
 252  * @dwc: pointer to our controller context structure
 253  *
 254  * Returns 0 on success otherwise negative errno.
 255  */
 256 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 257 {
 258         struct dwc3_event_buffer        *evt;
 259         int                             n;
 260
 261         for (n = 0; n < dwc->num_event_buffers; n++) {
 262                 evt = dwc->ev_buffs[n];
 263                 dwc3_trace(trace_dwc3_core,
 264                                 "Event buf %p dma %08llx length %d\n",
 265                                 evt->buf, (unsigned long long) evt->dma,
 266                                 evt->length);
 267
 268                 evt->lpos = 0;
 269
 270                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
 271                                 lower_32_bits(evt->dma));
 272                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
 273                                 upper_32_bits(evt->dma));
 274                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
 275                                 DWC3_GEVNTSIZ_SIZE(evt->length));
 276                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 277         }
 278
 279         return 0;
 280 }
 281
 282 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 283 {
 284         struct dwc3_event_buffer        *evt;
 285         int                             n;
 286
 287         for (n = 0; n < dwc->num_event_buffers; n++) {
 288                 evt = dwc->ev_buffs[n];
 289
 290                 evt->lpos = 0;
 291
 292                 dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
 293                 dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
 294                 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
 295                                 | DWC3_GEVNTSIZ_SIZE(0));
 296                 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
 297         }
 298 }
 299
 300 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 301 {
 302         if (!dwc->has_hibernation)
 303                 return 0;
 304
 305         if (!dwc->nr_scratch)
 306                 return 0;
 307
 308         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 309                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 310         if (!dwc->scratchbuf)
 311                 return -ENOMEM;
 312
 313         return 0;
 314 }
 315
 316 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 317 {
 318         dma_addr_t scratch_addr;
 319         u32 param;
 320         int ret;
 321
 322         if (!dwc->has_hibernation)
 323                 return 0;
 324
 325         if (!dwc->nr_scratch)
 326                 return 0;
 327
 328          /* should never fall here */
 329         if (!WARN_ON(dwc->scratchbuf))
 330                 return 0;
 331
 332         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 333                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 334                         DMA_BIDIRECTIONAL);
 335         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 336                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 337                 ret = -EFAULT;
 338                 goto err0;
 339         }
 340
 341         dwc->scratch_addr = scratch_addr;
 342
 343         param = lower_32_bits(scratch_addr);
 344
 345         ret = dwc3_send_gadget_generic_command(dwc,
 346                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 347         if (ret < 0)
 348                 goto err1;
 349
 350         param = upper_32_bits(scratch_addr);
 351
 352         ret = dwc3_send_gadget_generic_command(dwc,
 353                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 354         if (ret < 0)
 355                 goto err1;
 356
 357         return 0;
 358
 359 err1:
 360         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 361                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 362
 363 err0:
 364         return ret;
 365 }
 366
 367 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 368 {
 369         if (!dwc->has_hibernation)
 370                 return;
 371
 372         if (!dwc->nr_scratch)
 373                 return;
 374
 375          /* should never fall here */
 376         if (!WARN_ON(dwc->scratchbuf))
 377                 return;
 378
 379         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 380                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 381         kfree(dwc->scratchbuf);
 382 }
 383
 384 static void dwc3_core_num_eps(struct dwc3 *dwc)
 385 {
 386         struct dwc3_hwparams    *parms = &dwc->hwparams;
 387
 388         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 389         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 390
 391         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 392                         dwc->num_in_eps, dwc->num_out_eps);
 393 }
 394
 395 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 396 {
 397         struct dwc3_hwparams    *parms = &dwc->hwparams;
 398
 399         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 400         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 401         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 402         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 403         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 404         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 405         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 406         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 407         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 408 }
 409
 410 /**
 411  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 412  * @dwc: Pointer to our controller context structure
 413  *
 414  * Returns 0 on success. The USB PHY interfaces are configured but not
 415  * initialized. The PHY interfaces and the PHYs get initialized together with
 416  * the core in dwc3_core_init.
 417  */
 418 static int dwc3_phy_setup(struct dwc3 *dwc)
 419 {
 420         u32 reg;
 421         u32 usbtrdtim;
 422         int ret;
 423
 424         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 425
 426         /*
 427          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 428          * to '0' during coreConsultant configuration. So default value
 429          * will be '0' when the core is reset. Application needs to set it
 430          * to '1' after the core initialization is completed.
 431          */
 432         if (dwc->revision > DWC3_REVISION_194A)
 433                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 434
 435         if (dwc->u2ss_inp3_quirk)
 436                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 437
 438         if (dwc->req_p1p2p3_quirk)
 439                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 440
 441         if (dwc->del_p1p2p3_quirk)
 442                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 443
 444         if (dwc->del_phy_power_chg_quirk)
 445                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 446
 447         if (dwc->lfps_filter_quirk)
 448                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 449
 450         if (dwc->rx_detect_poll_quirk)
 451                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 452
 453         if (dwc->tx_de_emphasis_quirk)
 454                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 455
 456         if (dwc->dis_u3_susphy_quirk)
 457                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 458
 459         if (dwc->dis_del_phy_power_chg_quirk)
 460                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 461
 462         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 463
 464         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 465
 466         /* Select the HS PHY interface */
 467         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 468         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 469                 if (dwc->hsphy_interface &&
 470                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 471                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 472                         break;
 473                 } else if (dwc->hsphy_interface &&
 474                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 475                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 476                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 477                 } else {
 478                         /* Relying on default value. */
 479                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 480                                 break;
 481                 }
 482                 /* FALLTHROUGH */
 483         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 484                 /* Making sure the interface and PHY are operational */
 485                 ret = dwc3_soft_reset(dwc);
 486                 if (ret)
 487                         return ret;
 488
 489                 udelay(1);
 490
 491                 ret = dwc3_ulpi_init(dwc);
 492                 if (ret)
 493                         return ret;
 494                 /* FALLTHROUGH */
 495         default:
 496                 break;
 497         }
 498
 499         /*
 500          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 501          * '0' during coreConsultant configuration. So default value will
 502          * be '0' when the core is reset. Application needs to set it to
 503          * '1' after the core initialization is completed.
 504          */
 505         if (dwc->revision > DWC3_REVISION_194A)
 506                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 507
 508         if (dwc->dis_u2_susphy_quirk)
 509                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 510
 511         if (dwc->dis_enblslpm_quirk)
 512                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 513
 514         if (dwc->dis_u2_freeclk_exists_quirk)
 515                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 516
 517         if (dwc->phyif_utmi_16_bits)
 518                 reg |= DWC3_GUSB2PHYCFG_PHYIF;
 519
 520         usbtrdtim = (reg & DWC3_GUSB2PHYCFG_PHYIF) ?
 521                     USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
 522
 523         reg &= ~DWC3_GUSB2PHYCFG_USBTRDTIM_MASK;
 524         reg |= (usbtrdtim << DWC3_GUSB2PHYCFG_USBTRDTIM_SHIFT);
 525
 526         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 527
 528         return 0;
 529 }
 530
 531 /**
 532  * dwc3_core_init - Low-level initialization of DWC3 Core
 533  * @dwc: Pointer to our controller context structure
 534  *
 535  * Returns 0 on success otherwise negative errno.
 536  */
 537 static int dwc3_core_init(struct dwc3 *dwc)
 538 {
 539         u32                     hwparams4 = dwc->hwparams.hwparams4;
 540         u32                     reg;
 541         int                     ret;
 542
 543         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 544         /* This should read as U3 followed by revision number */
 545         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 546                 /* Detected DWC_usb3 IP */
 547                 dwc->revision = reg;
 548         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 549                 /* Detected DWC_usb31 IP */
 550                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 551                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 552         } else {
 553                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 554                 ret = -ENODEV;
 555                 goto err0;
 556         }
 557
 558         /*
 559          * Write Linux Version Code to our GUID register so it's easy to figure
 560          * out which kernel version a bug was found.
 561          */
 562         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 563
 564         /* Handle USB2.0-only core configuration */
 565         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 566                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 567                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 568                         dwc->maximum_speed = USB_SPEED_HIGH;
 569         }
 570
 571         /* issue device SoftReset too */
 572         ret = dwc3_soft_reset(dwc);
 573         if (ret)
 574                 goto err0;
 575
 576         ret = dwc3_core_soft_reset(dwc);
 577         if (ret)
 578                 goto err0;
 579
 580         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 581         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 582
 583         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 584         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 585                 /**
 586                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 587                  * issue which would cause xHCI compliance tests to fail.
 588                  *
 589                  * Because of that we cannot enable clock gating on such
 590                  * configurations.
 591                  *
 592                  * Refers to:
 593                  *
 594                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 595                  * SOF/ITP Mode Used
 596                  */
 597                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 598                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 599                                 (dwc->revision >= DWC3_REVISION_210A &&
 600                                 dwc->revision <= DWC3_REVISION_250A))
 601                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 602                 else
 603                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 604                 break;
 605         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 606                 /* enable hibernation here */
 607                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 608
 609                 /*
 610                  * REVISIT Enabling this bit so that host-mode hibernation
 611                  * will work. Device-mode hibernation is not yet implemented.
 612                  */
 613                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 614                 break;
 615         default:
 616                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 617         }
 618
 619         /* check if current dwc3 is on simulation board */
 620         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 621                 dwc3_trace(trace_dwc3_core,
 622                                 "running on FPGA platform\n");
 623                 dwc->is_fpga = true;
 624         }
 625
 626         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 627                         "disable_scramble cannot be used on non-FPGA builds\n");
 628
 629         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 630                 reg |= DWC3_GCTL_DISSCRAMBLE;
 631         else
 632                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 633
 634         if (dwc->u2exit_lfps_quirk)
 635                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 636
 637         /*
 638          * WORKAROUND: DWC3 revisions <1.90a have a bug
 639          * where the device can fail to connect at SuperSpeed
 640          * and falls back to high-speed mode which causes
 641          * the device to enter a Connect/Disconnect loop
 642          */
 643         if (dwc->revision < DWC3_REVISION_190A)
 644                 reg |= DWC3_GCTL_U2RSTECN;
 645
 646         dwc3_core_num_eps(dwc);
 647
 648         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 649
 650         ret = dwc3_alloc_scratch_buffers(dwc);
 651         if (ret)
 652                 goto err1;
 653
 654         ret = dwc3_setup_scratch_buffers(dwc);
 655         if (ret)
 656                 goto err2;
 657
 658         return 0;
 659
 660 err2:
 661         dwc3_free_scratch_buffers(dwc);
 662
 663 err1:
 664         usb_phy_shutdown(dwc->usb2_phy);
 665         usb_phy_shutdown(dwc->usb3_phy);
 666         phy_exit(dwc->usb2_generic_phy);
 667         phy_exit(dwc->usb3_generic_phy);
 668
 669 err0:
 670         return ret;
 671 }
 672
 673 static void dwc3_core_exit(struct dwc3 *dwc)
 674 {
 675         dwc3_free_scratch_buffers(dwc);
 676         usb_phy_shutdown(dwc->usb2_phy);
 677         usb_phy_shutdown(dwc->usb3_phy);
 678         phy_exit(dwc->usb2_generic_phy);
 679         phy_exit(dwc->usb3_generic_phy);
 680 }
 681
 682 static int dwc3_core_get_phy(struct dwc3 *dwc)
 683 {
 684         struct device           *dev = dwc->dev;
 685         struct device_node      *node = dev->of_node;
 686         int ret;
 687
 688         if (node) {
 689                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 690                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 691         } else {
 692                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 693                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 694         }
 695
 696         if (IS_ERR(dwc->usb2_phy)) {
 697                 ret = PTR_ERR(dwc->usb2_phy);
 698                 if (ret == -ENXIO || ret == -ENODEV) {
 699                         dwc->usb2_phy = NULL;
 700                 } else if (ret == -EPROBE_DEFER) {
 701                         return ret;
 702                 } else {
 703                         dev_err(dev, "no usb2 phy configured\n");
 704                         return ret;
 705                 }
 706         }
 707
 708         if (IS_ERR(dwc->usb3_phy)) {
 709                 ret = PTR_ERR(dwc->usb3_phy);
 710                 if (ret == -ENXIO || ret == -ENODEV) {
 711                         dwc->usb3_phy = NULL;
 712                 } else if (ret == -EPROBE_DEFER) {
 713                         return ret;
 714                 } else {
 715                         dev_err(dev, "no usb3 phy configured\n");
 716                         return ret;
 717                 }
 718         }
 719
 720         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 721         if (IS_ERR(dwc->usb2_generic_phy)) {
 722                 ret = PTR_ERR(dwc->usb2_generic_phy);
 723                 if (ret == -ENOSYS || ret == -ENODEV) {
 724                         dwc->usb2_generic_phy = NULL;
 725                 } else if (ret == -EPROBE_DEFER) {
 726                         return ret;
 727                 } else {
 728                         dev_err(dev, "no usb2 phy configured\n");
 729                         return ret;
 730                 }
 731         }
 732
 733         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 734         if (IS_ERR(dwc->usb3_generic_phy)) {
 735                 ret = PTR_ERR(dwc->usb3_generic_phy);
 736                 if (ret == -ENOSYS || ret == -ENODEV) {
 737                         dwc->usb3_generic_phy = NULL;
 738                 } else if (ret == -EPROBE_DEFER) {
 739                         return ret;
 740                 } else {
 741                         dev_err(dev, "no usb3 phy configured\n");
 742                         return ret;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int dwc3_core_init_mode(struct dwc3 *dwc)
 750 {
 751         struct device *dev = dwc->dev;
 752         int ret;
 753
 754         switch (dwc->dr_mode) {
 755         case USB_DR_MODE_PERIPHERAL:
 756                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 757                 ret = dwc3_gadget_init(dwc);
 758                 if (ret) {
 759                         dev_err(dev, "failed to initialize gadget\n");
 760                         return ret;
 761                 }
 762                 break;
 763         case USB_DR_MODE_HOST:
 764                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 765                 ret = dwc3_host_init(dwc);
 766                 if (ret) {
 767                         dev_err(dev, "failed to initialize host\n");
 768                         return ret;
 769                 }
 770                 break;
 771         case USB_DR_MODE_OTG:
 772                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 773                 ret = dwc3_host_init(dwc);
 774                 if (ret) {
 775                         dev_err(dev, "failed to initialize host\n");
 776                         return ret;
 777                 }
 778
 779                 ret = dwc3_gadget_init(dwc);
 780                 if (ret) {
 781                         dev_err(dev, "failed to initialize gadget\n");
 782                         return ret;
 783                 }
 784                 break;
 785         default:
 786                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 787                 return -EINVAL;
 788         }
 789
 790         return 0;
 791 }
 792
 793 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 794 {
 795         switch (dwc->dr_mode) {
 796         case USB_DR_MODE_PERIPHERAL:
 797                 dwc3_gadget_exit(dwc);
 798                 break;
 799         case USB_DR_MODE_HOST:
 800                 dwc3_host_exit(dwc);
 801                 break;
 802         case USB_DR_MODE_OTG:
 803                 dwc3_host_exit(dwc);
 804                 dwc3_gadget_exit(dwc);
 805                 break;
 806         default:
 807                 /* do nothing */
 808                 break;
 809         }
 810 }
 811
 812 /* Returns true if the controller is capable of DRD. */
 813 bool dwc3_hw_is_drd(struct dwc3 *dwc)
 814 {
 815         u32 op_mode = DWC3_GHWPARAMS0_USB3_MODE(dwc->hwparams.hwparams0);
 816
 817         return (op_mode == DWC3_GHWPARAMS0_USB3_DRD);
 818 }
 819
 820 bool dwc3_force_mode(struct dwc3 *dwc, u32 mode)
 821 {
 822         u32                     reg;
 823         unsigned long           flags;
 824         struct usb_hcd          *hcd;
 825
 826         /*
 827          * Force mode has no effect if the hardware is not drd mode.
 828          */
 829         if (!dwc3_hw_is_drd(dwc))
 830                 return false;
 831         /*
 832          * If dr_mode is either peripheral or host only, there is no
 833          * need to ever force the mode to the opposite mode.
 834          */
 835         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_DEVICE &&
 836                     dwc->dr_mode == USB_DR_MODE_HOST))
 837                 return false;
 838
 839         if (WARN_ON(mode == DWC3_GCTL_PRTCAP_HOST &&
 840                     dwc->dr_mode == USB_DR_MODE_PERIPHERAL))
 841                 return false;
 842
 843         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 844         if (DWC3_GCTL_PRTCAP(reg) == mode)
 845                 return false;
 846
 847         hcd = dev_get_drvdata(&dwc->xhci->dev);
 848
 849         switch (mode) {
 850         case DWC3_GCTL_PRTCAP_DEVICE:
 851                 if (hcd->state != HC_STATE_HALT) {
 852                         usb_remove_hcd(hcd->shared_hcd);
 853                         usb_remove_hcd(hcd);
 854                 }
 855
 856                 spin_lock_irqsave(&dwc->lock, flags);
 857                 dwc3_set_mode(dwc, mode);
 858                 dwc3_gadget_restart(dwc, true);
 859                 spin_unlock_irqrestore(&dwc->lock, flags);
 860
 861                 break;
 862         case DWC3_GCTL_PRTCAP_HOST:
 863                 spin_lock_irqsave(&dwc->lock, flags);
 864                 dwc3_gadget_restart(dwc, false);
 865                 dwc3_set_mode(dwc, mode);
 866                 spin_unlock_irqrestore(&dwc->lock, flags);
 867
 868                 if (hcd->state == HC_STATE_HALT) {
 869                         usb_add_hcd(hcd, hcd->irq, IRQF_SHARED);
 870                         usb_add_hcd(hcd->shared_hcd, hcd->irq, IRQF_SHARED);
 871                 }
 872
 873                 break;
 874         default:
 875                 /* do nothing  */
 876                 break;
 877         }
 878
 879         return true;
 880 }
 881
 882 #define DWC3_ALIGN_MASK         (16 - 1)
 883
 884 static int dwc3_probe(struct platform_device *pdev)
 885 {
 886         struct device           *dev = &pdev->dev;
 887         struct dwc3_platform_data *pdata = dev_get_platdata(dev);
 888         struct resource         *res;
 889         struct dwc3             *dwc;
 890         u8                      lpm_nyet_threshold;
 891         u8                      tx_de_emphasis;
 892         u8                      hird_threshold;
 893         u32                     fladj = 0;
 894
 895         int                     ret;
 896
 897         void __iomem            *regs;
 898         void                    *mem;
 899
 900         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 901         if (!mem)
 902                 return -ENOMEM;
 903
 904         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 905         dwc->mem = mem;
 906         dwc->dev = dev;
 907
 908         /* Try to set 64-bit DMA first */
 909         if (!pdev->dev.dma_mask)
 910                 /* Platform did not initialize dma_mask */
 911                 ret = dma_coerce_mask_and_coherent(&pdev->dev,
 912                                                    DMA_BIT_MASK(64));
 913         else
 914                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
 915
 916         /* If seting 64-bit DMA mask fails, fall back to 32-bit DMA mask */
 917         if (ret) {
 918                 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 919                 if (ret)
 920                         return ret;
 921         }
 922
 923         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 924         if (!res) {
 925                 dev_err(dev, "missing IRQ\n");
 926                 return -ENODEV;
 927         }
 928         dwc->xhci_resources[1].start = res->start;
 929         dwc->xhci_resources[1].end = res->end;
 930         dwc->xhci_resources[1].flags = res->flags;
 931         dwc->xhci_resources[1].name = res->name;
 932
 933         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 934         if (!res) {
 935                 dev_err(dev, "missing memory resource\n");
 936                 return -ENODEV;
 937         }
 938
 939         dwc->xhci_resources[0].start = res->start;
 940         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 941                                         DWC3_XHCI_REGS_END;
 942         dwc->xhci_resources[0].flags = res->flags;
 943         dwc->xhci_resources[0].name = res->name;
 944
 945         res->start += DWC3_GLOBALS_REGS_START;
 946
 947         /*
 948          * Request memory region but exclude xHCI regs,
 949          * since it will be requested by the xhci-plat driver.
 950          */
 951         regs = devm_ioremap_resource(dev, res);
 952         if (IS_ERR(regs)) {
 953                 ret = PTR_ERR(regs);
 954                 goto err0;
 955         }
 956
 957         dwc->regs       = regs;
 958         dwc->regs_size  = resource_size(res);
 959
 960         /* default to highest possible threshold */
 961         lpm_nyet_threshold = 0xff;
 962
 963         /* default to -3.5dB de-emphasis */
 964         tx_de_emphasis = 1;
 965
 966         /*
 967          * default to assert utmi_sleep_n and use maximum allowed HIRD
 968          * threshold value of 0b1100
 969          */
 970         hird_threshold = 12;
 971
 972         dwc->maximum_speed = usb_get_maximum_speed(dev);
 973         dwc->dr_mode = usb_get_dr_mode(dev);
 974
 975         dwc->has_lpm_erratum = device_property_read_bool(dev,
 976                                 "snps,has-lpm-erratum");
 977         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
 978                                 &lpm_nyet_threshold);
 979         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
 980                                 "snps,is-utmi-l1-suspend");
 981         device_property_read_u8(dev, "snps,hird-threshold",
 982                                 &hird_threshold);
 983         dwc->usb3_lpm_capable = device_property_read_bool(dev,
 984                                 "snps,usb3_lpm_capable");
 985
 986         dwc->disable_scramble_quirk = device_property_read_bool(dev,
 987                                 "snps,disable_scramble_quirk");
 988         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
 989                                 "snps,u2exit_lfps_quirk");
 990         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
 991                                 "snps,u2ss_inp3_quirk");
 992         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
 993                                 "snps,req_p1p2p3_quirk");
 994         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
 995                                 "snps,del_p1p2p3_quirk");
 996         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
 997                                 "snps,del_phy_power_chg_quirk");
 998         dwc->lfps_filter_quirk = device_property_read_bool(dev,
 999                                 "snps,lfps_filter_quirk");
1000         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1001                                 "snps,rx_detect_poll_quirk");
1002         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1003                                 "snps,dis_u3_susphy_quirk");
1004         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1005                                 "snps,dis_u2_susphy_quirk");
1006         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1007                                 "snps,dis_enblslpm_quirk");
1008         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1009                                 "snps,dis_u2_freeclk_exists_quirk");
1010         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1011                                 "snps,dis_del_phy_power_chg_quirk");
1012         dwc->xhci_slow_suspend_quirk = device_property_read_bool(dev,
1013                                 "snps,xhci_slow_suspend_quirk");
1014         dwc->phyif_utmi_16_bits = device_property_read_bool(dev,
1015                                 "snps,phyif_utmi_16_bits");
1016
1017         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1018                                 "snps,tx_de_emphasis_quirk");
1019         device_property_read_u8(dev, "snps,tx_de_emphasis",
1020                                 &tx_de_emphasis);
1021         device_property_read_string(dev, "snps,hsphy_interface",
1022                                     &dwc->hsphy_interface);
1023         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1024                                  &fladj);
1025
1026         if (pdata) {
1027                 dwc->maximum_speed = pdata->maximum_speed;
1028                 dwc->has_lpm_erratum = pdata->has_lpm_erratum;
1029                 if (pdata->lpm_nyet_threshold)
1030                         lpm_nyet_threshold = pdata->lpm_nyet_threshold;
1031                 dwc->is_utmi_l1_suspend = pdata->is_utmi_l1_suspend;
1032                 if (pdata->hird_threshold)
1033                         hird_threshold = pdata->hird_threshold;
1034
1035                 dwc->usb3_lpm_capable = pdata->usb3_lpm_capable;
1036                 dwc->dr_mode = pdata->dr_mode;
1037
1038                 dwc->disable_scramble_quirk = pdata->disable_scramble_quirk;
1039                 dwc->u2exit_lfps_quirk = pdata->u2exit_lfps_quirk;
1040                 dwc->u2ss_inp3_quirk = pdata->u2ss_inp3_quirk;
1041                 dwc->req_p1p2p3_quirk = pdata->req_p1p2p3_quirk;
1042                 dwc->del_p1p2p3_quirk = pdata->del_p1p2p3_quirk;
1043                 dwc->del_phy_power_chg_quirk = pdata->del_phy_power_chg_quirk;
1044                 dwc->lfps_filter_quirk = pdata->lfps_filter_quirk;
1045                 dwc->rx_detect_poll_quirk = pdata->rx_detect_poll_quirk;
1046                 dwc->dis_u3_susphy_quirk = pdata->dis_u3_susphy_quirk;
1047                 dwc->dis_u2_susphy_quirk = pdata->dis_u2_susphy_quirk;
1048                 dwc->dis_enblslpm_quirk = pdata->dis_enblslpm_quirk;
1049                 dwc->dis_u2_freeclk_exists_quirk =
1050                                         pdata->dis_u2_freeclk_exists_quirk;
1051                 dwc->dis_del_phy_power_chg_quirk =
1052                                         pdata->dis_del_phy_power_chg_quirk;
1053                 dwc->xhci_slow_suspend_quirk =
1054                                         pdata->xhci_slow_suspend_quirk;
1055                 dwc->phyif_utmi_16_bits = pdata->phyif_utmi_16_bits;
1056
1057                 dwc->tx_de_emphasis_quirk = pdata->tx_de_emphasis_quirk;
1058                 if (pdata->tx_de_emphasis)
1059                         tx_de_emphasis = pdata->tx_de_emphasis;
1060
1061                 dwc->hsphy_interface = pdata->hsphy_interface;
1062                 fladj = pdata->fladj_value;
1063         }
1064
1065         /* default to superspeed if no maximum_speed passed */
1066         if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
1067                 dwc->maximum_speed = USB_SPEED_SUPER;
1068
1069         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1070         dwc->tx_de_emphasis = tx_de_emphasis;
1071
1072         dwc->hird_threshold = hird_threshold
1073                 | (dwc->is_utmi_l1_suspend << 4);
1074
1075         platform_set_drvdata(pdev, dwc);
1076         dwc3_cache_hwparams(dwc);
1077
1078         ret = dwc3_phy_setup(dwc);
1079         if (ret)
1080                 goto err0;
1081
1082         ret = dwc3_core_get_phy(dwc);
1083         if (ret)
1084                 goto err0;
1085
1086         spin_lock_init(&dwc->lock);
1087
1088         if (!dev->dma_mask) {
1089                 dev->dma_mask = dev->parent->dma_mask;
1090                 dev->dma_parms = dev->parent->dma_parms;
1091                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1092         }
1093
1094         pm_runtime_enable(dev);
1095         pm_runtime_get_sync(dev);
1096         pm_runtime_forbid(dev);
1097
1098         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1099         if (ret) {
1100                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1101                 ret = -ENOMEM;
1102                 goto err1;
1103         }
1104
1105         if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
1106                 dwc->dr_mode = USB_DR_MODE_HOST;
1107         else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
1108                 dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
1109
1110         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
1111                 dwc->dr_mode = USB_DR_MODE_OTG;
1112
1113         ret = dwc3_core_init(dwc);
1114         if (ret) {
1115                 dev_err(dev, "failed to initialize core\n");
1116                 goto err1;
1117         }
1118
1119         /* Adjust Frame Length */
1120         dwc3_frame_length_adjustment(dwc, fladj);
1121
1122         usb_phy_set_suspend(dwc->usb2_phy, 0);
1123         usb_phy_set_suspend(dwc->usb3_phy, 0);
1124         ret = phy_power_on(dwc->usb2_generic_phy);
1125         if (ret < 0)
1126                 goto err2;
1127
1128         ret = phy_power_on(dwc->usb3_generic_phy);
1129         if (ret < 0)
1130                 goto err3;
1131
1132         ret = dwc3_event_buffers_setup(dwc);
1133         if (ret) {
1134                 dev_err(dwc->dev, "failed to setup event buffers\n");
1135                 goto err4;
1136         }
1137
1138         ret = dwc3_core_init_mode(dwc);
1139         if (ret)
1140                 goto err5;
1141
1142         ret = dwc3_debugfs_init(dwc);
1143         if (ret) {
1144                 dev_err(dev, "failed to initialize debugfs\n");
1145                 goto err6;
1146         }
1147
1148         pm_runtime_allow(dev);
1149
1150         return 0;
1151
1152 err6:
1153         dwc3_core_exit_mode(dwc);
1154
1155 err5:
1156         dwc3_event_buffers_cleanup(dwc);
1157
1158 err4:
1159         phy_power_off(dwc->usb3_generic_phy);
1160
1161 err3:
1162         phy_power_off(dwc->usb2_generic_phy);
1163
1164 err2:
1165         usb_phy_set_suspend(dwc->usb2_phy, 1);
1166         usb_phy_set_suspend(dwc->usb3_phy, 1);
1167         dwc3_core_exit(dwc);
1168
1169 err1:
1170         dwc3_free_event_buffers(dwc);
1171         dwc3_ulpi_exit(dwc);
1172
1173 err0:
1174         /*
1175          * restore res->start back to its original value so that, in case the
1176          * probe is deferred, we don't end up getting error in request the
1177          * memory region the next time probe is called.
1178          */
1179         res->start -= DWC3_GLOBALS_REGS_START;
1180
1181         return ret;
1182 }
1183
1184 static int dwc3_remove(struct platform_device *pdev)
1185 {
1186         struct dwc3     *dwc = platform_get_drvdata(pdev);
1187         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188
1189         /*
1190          * restore res->start back to its original value so that, in case the
1191          * probe is deferred, we don't end up getting error in request the
1192          * memory region the next time probe is called.
1193          */
1194         res->start -= DWC3_GLOBALS_REGS_START;
1195
1196         dwc3_debugfs_exit(dwc);
1197         dwc3_core_exit_mode(dwc);
1198         dwc3_event_buffers_cleanup(dwc);
1199         dwc3_free_event_buffers(dwc);
1200
1201         usb_phy_set_suspend(dwc->usb2_phy, 1);
1202         usb_phy_set_suspend(dwc->usb3_phy, 1);
1203         phy_power_off(dwc->usb2_generic_phy);
1204         phy_power_off(dwc->usb3_generic_phy);
1205
1206         dwc3_core_exit(dwc);
1207         dwc3_ulpi_exit(dwc);
1208
1209         pm_runtime_put_sync(&pdev->dev);
1210         pm_runtime_disable(&pdev->dev);
1211
1212         return 0;
1213 }
1214
1215 #ifdef CONFIG_PM_SLEEP
1216 static int dwc3_suspend(struct device *dev)
1217 {
1218         struct dwc3     *dwc = dev_get_drvdata(dev);
1219         unsigned long   flags;
1220
1221         spin_lock_irqsave(&dwc->lock, flags);
1222
1223         switch (dwc->dr_mode) {
1224         case USB_DR_MODE_PERIPHERAL:
1225         case USB_DR_MODE_OTG:
1226                 dwc3_gadget_suspend(dwc);
1227                 /* FALLTHROUGH */
1228         case USB_DR_MODE_HOST:
1229         default:
1230                 dwc3_event_buffers_cleanup(dwc);
1231                 break;
1232         }
1233
1234         dwc->gctl = dwc3_readl(dwc->regs, DWC3_GCTL);
1235         spin_unlock_irqrestore(&dwc->lock, flags);
1236
1237         usb_phy_shutdown(dwc->usb3_phy);
1238         usb_phy_shutdown(dwc->usb2_phy);
1239         phy_exit(dwc->usb2_generic_phy);
1240         phy_exit(dwc->usb3_generic_phy);
1241
1242         pinctrl_pm_select_sleep_state(dev);
1243
1244         return 0;
1245 }
1246
1247 static int dwc3_resume(struct device *dev)
1248 {
1249         struct dwc3     *dwc = dev_get_drvdata(dev);
1250         unsigned long   flags;
1251         int             ret;
1252
1253         pinctrl_pm_select_default_state(dev);
1254
1255         usb_phy_init(dwc->usb3_phy);
1256         usb_phy_init(dwc->usb2_phy);
1257         ret = phy_init(dwc->usb2_generic_phy);
1258         if (ret < 0)
1259                 return ret;
1260
1261         ret = phy_init(dwc->usb3_generic_phy);
1262         if (ret < 0)
1263                 goto err_usb2phy_init;
1264
1265         spin_lock_irqsave(&dwc->lock, flags);
1266
1267         dwc3_event_buffers_setup(dwc);
1268         dwc3_writel(dwc->regs, DWC3_GCTL, dwc->gctl);
1269
1270         switch (dwc->dr_mode) {
1271         case USB_DR_MODE_PERIPHERAL:
1272         case USB_DR_MODE_OTG:
1273                 dwc3_gadget_resume(dwc);
1274                 /* FALLTHROUGH */
1275         case USB_DR_MODE_HOST:
1276         default:
1277                 /* do nothing */
1278                 break;
1279         }
1280
1281         spin_unlock_irqrestore(&dwc->lock, flags);
1282
1283         pm_runtime_disable(dev);
1284         pm_runtime_set_active(dev);
1285         pm_runtime_enable(dev);
1286
1287         return 0;
1288
1289 err_usb2phy_init:
1290         phy_exit(dwc->usb2_generic_phy);
1291
1292         return ret;
1293 }
1294
1295 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1296         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1297 };
1298
1299 #define DWC3_PM_OPS     &(dwc3_dev_pm_ops)
1300 #else
1301 #define DWC3_PM_OPS     NULL
1302 #endif
1303
1304 #ifdef CONFIG_OF
1305 static const struct of_device_id of_dwc3_match[] = {
1306         {
1307                 .compatible = "snps,dwc3"
1308         },
1309         {
1310                 .compatible = "synopsys,dwc3"
1311         },
1312         { },
1313 };
1314 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1315 #endif
1316
1317 #ifdef CONFIG_ACPI
1318
1319 #define ACPI_ID_INTEL_BSW       "808622B7"
1320
1321 static const struct acpi_device_id dwc3_acpi_match[] = {
1322         { ACPI_ID_INTEL_BSW, 0 },
1323         { },
1324 };
1325 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1326 #endif
1327
1328 static struct platform_driver dwc3_driver = {
1329         .probe          = dwc3_probe,
1330         .remove         = dwc3_remove,
1331         .driver         = {
1332                 .name   = "dwc3",
1333                 .of_match_table = of_match_ptr(of_dwc3_match),
1334                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1335                 .pm     = DWC3_PM_OPS,
1336         },
1337 };
1338
1339 module_platform_driver(dwc3_driver);
1340
1341 MODULE_ALIAS("platform:dwc3");
1342 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1343 MODULE_LICENSE("GPL v2");
1344 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");