drivers/usb/dwc2/platform.c

   1 /*
   2  * platform.c - DesignWare HS OTG Controller platform driver
   3  *
   4  * Copyright (C) Matthijs Kooijman <matthijs@stdin.nl>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/slab.h>
  40 #include <linux/clk.h>
  41 #include <linux/device.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/of_device.h>
  44 #include <linux/mutex.h>
  45 #include <linux/platform_device.h>
  46 #include <linux/phy/phy.h>
  47 #include <linux/platform_data/s3c-hsotg.h>
  48
  49 #include <linux/usb/of.h>
  50
  51 #include "core.h"
  52 #include "hcd.h"
  53 #include "debug.h"
  54
  55 static const char dwc2_driver_name[] = "dwc2";
  56
  57 static const struct dwc2_core_params params_bcm2835 = {
  58         .otg_cap                        = 0,    /* HNP/SRP capable */
  59         .otg_ver                        = 0,    /* 1.3 */
  60         .dma_enable                     = 1,
  61         .dma_desc_enable                = 0,
  62         .speed                          = 0,    /* High Speed */
  63         .enable_dynamic_fifo            = 1,
  64         .en_multiple_tx_fifo            = 1,
  65         .host_rx_fifo_size              = 774,  /* 774 DWORDs */
  66         .host_nperio_tx_fifo_size       = 256,  /* 256 DWORDs */
  67         .host_perio_tx_fifo_size        = 512,  /* 512 DWORDs */
  68         .max_transfer_size              = 65535,
  69         .max_packet_count               = 511,
  70         .host_channels                  = 8,
  71         .phy_type                       = 1,    /* UTMI */
  72         .phy_utmi_width                 = 8,    /* 8 bits */
  73         .phy_ulpi_ddr                   = 0,    /* Single */
  74         .phy_ulpi_ext_vbus              = 0,
  75         .i2c_enable                     = 0,
  76         .ulpi_fs_ls                     = 0,
  77         .host_support_fs_ls_low_power   = 0,
  78         .host_ls_low_power_phy_clk      = 0,    /* 48 MHz */
  79         .ts_dline                       = 0,
  80         .reload_ctl                     = 0,
  81         .ahbcfg                         = 0x10,
  82         .uframe_sched                   = 0,
  83         .external_id_pin_ctl            = -1,
  84         .hibernation                    = -1,
  85 };
  86
  87 static const struct dwc2_core_params params_rk3066 = {
  88         .otg_cap                        = 2,    /* non-HNP/non-SRP */
  89         .otg_ver                        = -1,
  90         .dma_enable                     = -1,
  91         .dma_desc_enable                = 0,
  92         .speed                          = -1,
  93         .enable_dynamic_fifo            = 1,
  94         .en_multiple_tx_fifo            = -1,
  95         .host_rx_fifo_size              = 520,  /* 520 DWORDs */
  96         .host_nperio_tx_fifo_size       = 128,  /* 128 DWORDs */
  97         .host_perio_tx_fifo_size        = 256,  /* 256 DWORDs */
  98         .max_transfer_size              = 65535,
  99         .max_packet_count               = -1,
 100         .host_channels                  = -1,
 101         .phy_type                       = -1,
 102         .phy_utmi_width                 = -1,
 103         .phy_ulpi_ddr                   = -1,
 104         .phy_ulpi_ext_vbus              = -1,
 105         .i2c_enable                     = -1,
 106         .ulpi_fs_ls                     = -1,
 107         .host_support_fs_ls_low_power   = -1,
 108         .host_ls_low_power_phy_clk      = -1,
 109         .ts_dline                       = -1,
 110         .reload_ctl                     = -1,
 111         .ahbcfg                         = GAHBCFG_HBSTLEN_INCR16 <<
 112                                           GAHBCFG_HBSTLEN_SHIFT,
 113         .uframe_sched                   = -1,
 114         .external_id_pin_ctl            = -1,
 115         .hibernation                    = -1,
 116 };
 117
 118 static int __dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 119 {
 120         struct platform_device *pdev = to_platform_device(hsotg->dev);
 121         int ret;
 122
 123         ret = regulator_bulk_enable(ARRAY_SIZE(hsotg->supplies),
 124                                     hsotg->supplies);
 125         if (ret)
 126                 return ret;
 127
 128         if (hsotg->clk) {
 129                 ret = clk_prepare_enable(hsotg->clk);
 130                 if (ret)
 131                         return ret;
 132         }
 133
 134         if (hsotg->uphy)
 135                 ret = usb_phy_init(hsotg->uphy);
 136         else if (hsotg->plat && hsotg->plat->phy_init)
 137                 ret = hsotg->plat->phy_init(pdev, hsotg->plat->phy_type);
 138         else {
 139                 ret = phy_power_on(hsotg->phy);
 140                 if (ret == 0)
 141                         ret = phy_init(hsotg->phy);
 142         }
 143
 144         return ret;
 145 }
 146
 147 /**
 148  * dwc2_lowlevel_hw_enable - enable platform lowlevel hw resources
 149  * @hsotg: The driver state
 150  *
 151  * A wrapper for platform code responsible for controlling
 152  * low-level USB platform resources (phy, clock, regulators)
 153  */
 154 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg)
 155 {
 156         int ret = __dwc2_lowlevel_hw_enable(hsotg);
 157
 158         if (ret == 0)
 159                 hsotg->ll_hw_enabled = true;
 160         return ret;
 161 }
 162
 163 static int __dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 164 {
 165         struct platform_device *pdev = to_platform_device(hsotg->dev);
 166         int ret = 0;
 167
 168         if (hsotg->uphy)
 169                 usb_phy_shutdown(hsotg->uphy);
 170         else if (hsotg->plat && hsotg->plat->phy_exit)
 171                 ret = hsotg->plat->phy_exit(pdev, hsotg->plat->phy_type);
 172         else {
 173                 ret = phy_exit(hsotg->phy);
 174                 if (ret == 0)
 175                         ret = phy_power_off(hsotg->phy);
 176         }
 177         if (ret)
 178                 return ret;
 179
 180         if (hsotg->clk)
 181                 clk_disable_unprepare(hsotg->clk);
 182
 183         ret = regulator_bulk_disable(ARRAY_SIZE(hsotg->supplies),
 184                                      hsotg->supplies);
 185
 186         return ret;
 187 }
 188
 189 /**
 190  * dwc2_lowlevel_hw_disable - disable platform lowlevel hw resources
 191  * @hsotg: The driver state
 192  *
 193  * A wrapper for platform code responsible for controlling
 194  * low-level USB platform resources (phy, clock, regulators)
 195  */
 196 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg)
 197 {
 198         int ret = __dwc2_lowlevel_hw_disable(hsotg);
 199
 200         if (ret == 0)
 201                 hsotg->ll_hw_enabled = false;
 202         return ret;
 203 }
 204
 205 /* Only used to reset usb phy at interrupter runtime */
 206 static void dwc2_reset_phy_work(struct work_struct *data)
 207 {
 208         struct dwc2_hsotg *hsotg = container_of(data, struct dwc2_hsotg,
 209                         phy_rst_work);
 210         phy_reset(hsotg->phy);
 211 }
 212
 213 static int dwc2_lowlevel_hw_init(struct dwc2_hsotg *hsotg)
 214 {
 215         int i, ret;
 216
 217         /* Set default UTMI width */
 218         hsotg->phyif = GUSBCFG_PHYIF16;
 219
 220         /*
 221          * Attempt to find a generic PHY, then look for an old style
 222          * USB PHY and then fall back to pdata
 223          */
 224         hsotg->phy = devm_phy_get(hsotg->dev, "usb2-phy");
 225         if (IS_ERR(hsotg->phy)) {
 226                 ret = PTR_ERR(hsotg->phy);
 227                 switch (ret) {
 228                 case -ENODEV:
 229                 case -ENOSYS:
 230                         hsotg->phy = NULL;
 231                         break;
 232                 case -EPROBE_DEFER:
 233                         return ret;
 234                 default:
 235                         dev_err(hsotg->dev, "error getting phy %d\n", ret);
 236                         return ret;
 237                 }
 238         }
 239         INIT_WORK(&hsotg->phy_rst_work, dwc2_reset_phy_work);
 240
 241         if (!hsotg->phy) {
 242                 hsotg->uphy = devm_usb_get_phy(hsotg->dev, USB_PHY_TYPE_USB2);
 243                 if (IS_ERR(hsotg->uphy)) {
 244                         ret = PTR_ERR(hsotg->uphy);
 245                         switch (ret) {
 246                         case -ENODEV:
 247                         case -ENXIO:
 248                                 hsotg->uphy = NULL;
 249                                 break;
 250                         case -EPROBE_DEFER:
 251                                 return ret;
 252                         default:
 253                                 dev_err(hsotg->dev, "error getting usb phy %d\n",
 254                                         ret);
 255                                 return ret;
 256                         }
 257                 }
 258         }
 259
 260         hsotg->plat = dev_get_platdata(hsotg->dev);
 261
 262         if (hsotg->phy) {
 263                 /*
 264                  * If using the generic PHY framework, check if the PHY bus
 265                  * width is 8-bit and set the phyif appropriately.
 266                  */
 267                 if (phy_get_bus_width(hsotg->phy) == 8)
 268                         hsotg->phyif = GUSBCFG_PHYIF8;
 269         }
 270
 271         /* Clock */
 272         hsotg->clk = devm_clk_get(hsotg->dev, "otg");
 273         if (IS_ERR(hsotg->clk)) {
 274                 hsotg->clk = NULL;
 275                 dev_dbg(hsotg->dev, "cannot get otg clock\n");
 276         }
 277
 278         /* Regulators */
 279         for (i = 0; i < ARRAY_SIZE(hsotg->supplies); i++)
 280                 hsotg->supplies[i].supply = dwc2_hsotg_supply_names[i];
 281
 282         ret = devm_regulator_bulk_get(hsotg->dev, ARRAY_SIZE(hsotg->supplies),
 283                                       hsotg->supplies);
 284         if (ret) {
 285                 dev_err(hsotg->dev, "failed to request supplies: %d\n", ret);
 286                 return ret;
 287         }
 288         return 0;
 289 }
 290
 291 /**
 292  * dwc2_driver_remove() - Called when the DWC_otg core is unregistered with the
 293  * DWC_otg driver
 294  *
 295  * @dev: Platform device
 296  *
 297  * This routine is called, for example, when the rmmod command is executed. The
 298  * device may or may not be electrically present. If it is present, the driver
 299  * stops device processing. Any resources used on behalf of this device are
 300  * freed.
 301  */
 302 static int dwc2_driver_remove(struct platform_device *dev)
 303 {
 304         struct dwc2_hsotg *hsotg = platform_get_drvdata(dev);
 305
 306         dwc2_debugfs_exit(hsotg);
 307         if (hsotg->hcd_enabled)
 308                 dwc2_hcd_remove(hsotg);
 309         if (hsotg->gadget_enabled)
 310                 dwc2_hsotg_remove(hsotg);
 311
 312         if (hsotg->ll_hw_enabled)
 313                 dwc2_lowlevel_hw_disable(hsotg);
 314
 315         return 0;
 316 }
 317
 318 static const struct of_device_id dwc2_of_match_table[] = {
 319         { .compatible = "brcm,bcm2835-usb", .data = &params_bcm2835 },
 320         { .compatible = "rockchip,rk3066-usb", .data = &params_rk3066 },
 321         { .compatible = "snps,dwc2", .data = NULL },
 322         { .compatible = "samsung,s3c6400-hsotg", .data = NULL},
 323         {},
 324 };
 325 MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
 326
 327 /**
 328  * dwc2_driver_probe() - Called when the DWC_otg core is bound to the DWC_otg
 329  * driver
 330  *
 331  * @dev: Platform device
 332  *
 333  * This routine creates the driver components required to control the device
 334  * (core, HCD, and PCD) and initializes the device. The driver components are
 335  * stored in a dwc2_hsotg structure. A reference to the dwc2_hsotg is saved
 336  * in the device private data. This allows the driver to access the dwc2_hsotg
 337  * structure on subsequent calls to driver methods for this device.
 338  */
 339 static int dwc2_driver_probe(struct platform_device *dev)
 340 {
 341         const struct of_device_id *match;
 342         const struct dwc2_core_params *params;
 343         struct dwc2_core_params defparams;
 344         struct dwc2_hsotg *hsotg;
 345         struct resource *res;
 346         int retval;
 347         int irq;
 348
 349         match = of_match_device(dwc2_of_match_table, &dev->dev);
 350         if (match && match->data) {
 351                 params = match->data;
 352         } else {
 353                 /* Default all params to autodetect */
 354                 dwc2_set_all_params(&defparams, -1);
 355                 params = &defparams;
 356
 357                 /*
 358                  * Disable descriptor dma mode by default as the HW can support
 359                  * it, but does not support it for SPLIT transactions.
 360                  */
 361                 defparams.dma_desc_enable = 0;
 362         }
 363
 364         hsotg = devm_kzalloc(&dev->dev, sizeof(*hsotg), GFP_KERNEL);
 365         if (!hsotg)
 366                 return -ENOMEM;
 367
 368         hsotg->dev = &dev->dev;
 369
 370         /*
 371          * Use reasonable defaults so platforms don't have to provide these.
 372          */
 373         if (!dev->dev.dma_mask)
 374                 dev->dev.dma_mask = &dev->dev.coherent_dma_mask;
 375         retval = dma_set_coherent_mask(&dev->dev, DMA_BIT_MASK(32));
 376         if (retval)
 377                 return retval;
 378
 379         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
 380         hsotg->regs = devm_ioremap_resource(&dev->dev, res);
 381         if (IS_ERR(hsotg->regs))
 382                 return PTR_ERR(hsotg->regs);
 383
 384         dev_dbg(&dev->dev, "mapped PA %08lx to VA %p\n",
 385                 (unsigned long)res->start, hsotg->regs);
 386
 387         hsotg->dr_mode = usb_get_dr_mode(&dev->dev);
 388         if (IS_ENABLED(CONFIG_USB_DWC2_HOST) &&
 389                         hsotg->dr_mode != USB_DR_MODE_HOST) {
 390                 hsotg->dr_mode = USB_DR_MODE_HOST;
 391                 dev_warn(hsotg->dev,
 392                         "Configuration mismatch. Forcing host mode\n");
 393         } else if (IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) &&
 394                         hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 395                 hsotg->dr_mode = USB_DR_MODE_PERIPHERAL;
 396                 dev_warn(hsotg->dev,
 397                         "Configuration mismatch. Forcing peripheral mode\n");
 398         }
 399
 400         retval = dwc2_lowlevel_hw_init(hsotg);
 401         if (retval)
 402                 return retval;
 403
 404         spin_lock_init(&hsotg->lock);
 405
 406         hsotg->core_params = devm_kzalloc(&dev->dev,
 407                                 sizeof(*hsotg->core_params), GFP_KERNEL);
 408         if (!hsotg->core_params)
 409                 return -ENOMEM;
 410
 411         dwc2_set_all_params(hsotg->core_params, -1);
 412
 413         irq = platform_get_irq(dev, 0);
 414         if (irq < 0) {
 415                 dev_err(&dev->dev, "missing IRQ resource\n");
 416                 return irq;
 417         }
 418
 419         dev_dbg(hsotg->dev, "registering common handler for irq%d\n",
 420                 irq);
 421         retval = devm_request_irq(hsotg->dev, irq,
 422                                   dwc2_handle_common_intr, IRQF_SHARED,
 423                                   dev_name(hsotg->dev), hsotg);
 424         if (retval)
 425                 return retval;
 426
 427         retval = dwc2_lowlevel_hw_enable(hsotg);
 428         if (retval)
 429                 return retval;
 430
 431         /*
 432          * Reset before dwc2_get_hwparams() then it could get power-on real
 433          * reset value form registers.
 434          */
 435         dwc2_core_reset(hsotg);
 436
 437         /* Detect config values from hardware */
 438         retval = dwc2_get_hwparams(hsotg);
 439         if (retval)
 440                 goto error;
 441
 442         /* Validate parameter values */
 443         dwc2_set_parameters(hsotg, params);
 444
 445         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
 446                 retval = dwc2_gadget_init(hsotg, irq);
 447                 if (retval)
 448                         goto error;
 449                 hsotg->gadget_enabled = 1;
 450         }
 451
 452         if (hsotg->dr_mode != USB_DR_MODE_PERIPHERAL) {
 453                 retval = dwc2_hcd_init(hsotg, irq);
 454                 if (retval) {
 455                         if (hsotg->gadget_enabled)
 456                                 dwc2_hsotg_remove(hsotg);
 457                         goto error;
 458                 }
 459                 hsotg->hcd_enabled = 1;
 460         }
 461
 462         platform_set_drvdata(dev, hsotg);
 463
 464         dwc2_debugfs_init(hsotg);
 465
 466         /* Gadget code manages lowlevel hw on its own */
 467         if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL)
 468                 dwc2_lowlevel_hw_disable(hsotg);
 469
 470         return 0;
 471
 472 error:
 473         dwc2_lowlevel_hw_disable(hsotg);
 474         return retval;
 475 }
 476
 477 static int __maybe_unused dwc2_suspend(struct device *dev)
 478 {
 479         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 480         int ret = 0;
 481
 482         if (dwc2_is_device_mode(dwc2))
 483                 dwc2_hsotg_suspend(dwc2);
 484
 485         if (dwc2->ll_hw_enabled)
 486                 ret = __dwc2_lowlevel_hw_disable(dwc2);
 487
 488         return ret;
 489 }
 490
 491 static int __maybe_unused dwc2_resume(struct device *dev)
 492 {
 493         struct dwc2_hsotg *dwc2 = dev_get_drvdata(dev);
 494         int ret = 0;
 495
 496         if (dwc2->ll_hw_enabled) {
 497                 ret = __dwc2_lowlevel_hw_enable(dwc2);
 498                 if (ret)
 499                         return ret;
 500         }
 501
 502         if (dwc2_is_device_mode(dwc2))
 503                 ret = dwc2_hsotg_resume(dwc2);
 504
 505         return ret;
 506 }
 507
 508 static const struct dev_pm_ops dwc2_dev_pm_ops = {
 509         SET_SYSTEM_SLEEP_PM_OPS(dwc2_suspend, dwc2_resume)
 510 };
 511
 512 static struct platform_driver dwc2_platform_driver = {
 513         .driver = {
 514                 .name = dwc2_driver_name,
 515                 .of_match_table = dwc2_of_match_table,
 516                 .pm = &dwc2_dev_pm_ops,
 517         },
 518         .probe = dwc2_driver_probe,
 519         .remove = dwc2_driver_remove,
 520 };
 521
 522 module_platform_driver(dwc2_platform_driver);
 523
 524 MODULE_DESCRIPTION("DESIGNWARE HS OTG Platform Glue");
 525 MODULE_AUTHOR("Matthijs Kooijman <matthijs@stdin.nl>");
 526 MODULE_LICENSE("Dual BSD/GPL");