2 * hcd_intr.c - DesignWare HS OTG Controller host-mode interrupt handling
4 * Copyright (C) 2004-2013 Synopsys, Inc.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
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19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 * This file contains the interrupt handlers for Host mode
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/spinlock.h>
43 #include <linux/interrupt.h>
44 #include <linux/dma-mapping.h>
46 #include <linux/slab.h>
47 #include <linux/usb.h>
49 #include <linux/usb/hcd.h>
50 #include <linux/usb/ch11.h>
55 /* This function is for debug only */
56 static void dwc2_track_missed_sofs(struct dwc2_hsotg *hsotg)
58 u16 curr_frame_number = hsotg->frame_number;
59 u16 expected = dwc2_frame_num_inc(hsotg->last_frame_num, 1);
61 if (expected != curr_frame_number)
62 dwc2_sch_vdbg(hsotg, "MISSED SOF %04x != %04x\n",
63 expected, curr_frame_number);
65 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
66 if (hsotg->frame_num_idx < FRAME_NUM_ARRAY_SIZE) {
67 if (expected != curr_frame_number) {
68 hsotg->frame_num_array[hsotg->frame_num_idx] =
70 hsotg->last_frame_num_array[hsotg->frame_num_idx] =
71 hsotg->last_frame_num;
72 hsotg->frame_num_idx++;
74 } else if (!hsotg->dumped_frame_num_array) {
77 dev_info(hsotg->dev, "Frame Last Frame\n");
78 dev_info(hsotg->dev, "----- ----------\n");
79 for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) {
80 dev_info(hsotg->dev, "0x%04x 0x%04x\n",
81 hsotg->frame_num_array[i],
82 hsotg->last_frame_num_array[i]);
84 hsotg->dumped_frame_num_array = 1;
87 hsotg->last_frame_num = curr_frame_number;
90 static void dwc2_hc_handle_tt_clear(struct dwc2_hsotg *hsotg,
91 struct dwc2_host_chan *chan,
94 struct usb_device *root_hub = dwc2_hsotg_to_hcd(hsotg)->self.root_hub;
100 if (chan->qh->dev_speed == USB_SPEED_HIGH)
106 usb_urb = qtd->urb->priv;
107 if (!usb_urb || !usb_urb->dev || !usb_urb->dev->tt)
111 * The root hub doesn't really have a TT, but Linux thinks it
112 * does because how could you have a "high speed hub" that
113 * directly talks directly to low speed devices without a TT?
114 * It's all lies. Lies, I tell you.
116 if (usb_urb->dev->tt->hub == root_hub)
119 if (qtd->urb->status != -EPIPE && qtd->urb->status != -EREMOTEIO) {
120 chan->qh->tt_buffer_dirty = 1;
121 if (usb_hub_clear_tt_buffer(usb_urb))
122 /* Clear failed; let's hope things work anyway */
123 chan->qh->tt_buffer_dirty = 0;
128 * Handles the start-of-frame interrupt in host mode. Non-periodic
129 * transactions may be queued to the DWC_otg controller for the current
130 * (micro)frame. Periodic transactions may be queued to the controller
131 * for the next (micro)frame.
133 static void dwc2_sof_intr(struct dwc2_hsotg *hsotg)
135 struct list_head *qh_entry;
137 enum dwc2_transaction_type tr_type;
139 /* Clear interrupt */
140 dwc2_writel(GINTSTS_SOF, hsotg->regs + GINTSTS);
143 dev_vdbg(hsotg->dev, "--Start of Frame Interrupt--\n");
146 hsotg->frame_number = dwc2_hcd_get_frame_number(hsotg);
148 dwc2_track_missed_sofs(hsotg);
150 /* Determine whether any periodic QHs should be executed */
151 qh_entry = hsotg->periodic_sched_inactive.next;
152 while (qh_entry != &hsotg->periodic_sched_inactive) {
153 qh = list_entry(qh_entry, struct dwc2_qh, qh_list_entry);
154 qh_entry = qh_entry->next;
155 if (dwc2_frame_num_le(qh->next_active_frame,
156 hsotg->frame_number)) {
157 dwc2_sch_vdbg(hsotg, "QH=%p ready fn=%04x, nxt=%04x\n",
158 qh, hsotg->frame_number,
159 qh->next_active_frame);
162 * Move QH to the ready list to be executed next
165 list_move_tail(&qh->qh_list_entry,
166 &hsotg->periodic_sched_ready);
169 tr_type = dwc2_hcd_select_transactions(hsotg);
170 if (tr_type != DWC2_TRANSACTION_NONE)
171 dwc2_hcd_queue_transactions(hsotg, tr_type);
175 * Handles the Rx FIFO Level Interrupt, which indicates that there is
176 * at least one packet in the Rx FIFO. The packets are moved from the FIFO to
177 * memory if the DWC_otg controller is operating in Slave mode.
179 static void dwc2_rx_fifo_level_intr(struct dwc2_hsotg *hsotg)
181 u32 grxsts, chnum, bcnt, dpid, pktsts;
182 struct dwc2_host_chan *chan;
185 dev_vdbg(hsotg->dev, "--RxFIFO Level Interrupt--\n");
187 grxsts = dwc2_readl(hsotg->regs + GRXSTSP);
188 chnum = (grxsts & GRXSTS_HCHNUM_MASK) >> GRXSTS_HCHNUM_SHIFT;
189 chan = hsotg->hc_ptr_array[chnum];
191 dev_err(hsotg->dev, "Unable to get corresponding channel\n");
195 bcnt = (grxsts & GRXSTS_BYTECNT_MASK) >> GRXSTS_BYTECNT_SHIFT;
196 dpid = (grxsts & GRXSTS_DPID_MASK) >> GRXSTS_DPID_SHIFT;
197 pktsts = (grxsts & GRXSTS_PKTSTS_MASK) >> GRXSTS_PKTSTS_SHIFT;
201 dev_vdbg(hsotg->dev, " Ch num = %d\n", chnum);
202 dev_vdbg(hsotg->dev, " Count = %d\n", bcnt);
203 dev_vdbg(hsotg->dev, " DPID = %d, chan.dpid = %d\n", dpid,
204 chan->data_pid_start);
205 dev_vdbg(hsotg->dev, " PStatus = %d\n", pktsts);
209 case GRXSTS_PKTSTS_HCHIN:
210 /* Read the data into the host buffer */
212 dwc2_read_packet(hsotg, chan->xfer_buf, bcnt);
214 /* Update the HC fields for the next packet received */
215 chan->xfer_count += bcnt;
216 chan->xfer_buf += bcnt;
219 case GRXSTS_PKTSTS_HCHIN_XFER_COMP:
220 case GRXSTS_PKTSTS_DATATOGGLEERR:
221 case GRXSTS_PKTSTS_HCHHALTED:
222 /* Handled in interrupt, just ignore data */
226 "RxFIFO Level Interrupt: Unknown status %d\n", pktsts);
232 * This interrupt occurs when the non-periodic Tx FIFO is half-empty. More
233 * data packets may be written to the FIFO for OUT transfers. More requests
234 * may be written to the non-periodic request queue for IN transfers. This
235 * interrupt is enabled only in Slave mode.
237 static void dwc2_np_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
239 dev_vdbg(hsotg->dev, "--Non-Periodic TxFIFO Empty Interrupt--\n");
240 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_NON_PERIODIC);
244 * This interrupt occurs when the periodic Tx FIFO is half-empty. More data
245 * packets may be written to the FIFO for OUT transfers. More requests may be
246 * written to the periodic request queue for IN transfers. This interrupt is
247 * enabled only in Slave mode.
249 static void dwc2_perio_tx_fifo_empty_intr(struct dwc2_hsotg *hsotg)
252 dev_vdbg(hsotg->dev, "--Periodic TxFIFO Empty Interrupt--\n");
253 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_PERIODIC);
256 static void dwc2_hprt0_enable(struct dwc2_hsotg *hsotg, u32 hprt0,
259 struct dwc2_core_params *params = hsotg->core_params;
267 dev_vdbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
269 /* Every time when port enables calculate HFIR.FrInterval */
270 hfir = dwc2_readl(hsotg->regs + HFIR);
271 hfir &= ~HFIR_FRINT_MASK;
272 hfir |= dwc2_calc_frame_interval(hsotg) << HFIR_FRINT_SHIFT &
274 dwc2_writel(hfir, hsotg->regs + HFIR);
276 /* Check if we need to adjust the PHY clock speed for low power */
277 if (!params->host_support_fs_ls_low_power) {
278 /* Port has been enabled, set the reset change flag */
279 hsotg->flags.b.port_reset_change = 1;
283 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
284 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
286 if (prtspd == HPRT0_SPD_LOW_SPEED || prtspd == HPRT0_SPD_FULL_SPEED) {
288 if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL)) {
289 /* Set PHY low power clock select for FS/LS devices */
290 usbcfg |= GUSBCFG_PHY_LP_CLK_SEL;
291 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
295 hcfg = dwc2_readl(hsotg->regs + HCFG);
296 fslspclksel = (hcfg & HCFG_FSLSPCLKSEL_MASK) >>
297 HCFG_FSLSPCLKSEL_SHIFT;
299 if (prtspd == HPRT0_SPD_LOW_SPEED &&
300 params->host_ls_low_power_phy_clk ==
301 DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ) {
304 "FS_PHY programming HCFG to 6 MHz\n");
305 if (fslspclksel != HCFG_FSLSPCLKSEL_6_MHZ) {
306 fslspclksel = HCFG_FSLSPCLKSEL_6_MHZ;
307 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
308 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
309 dwc2_writel(hcfg, hsotg->regs + HCFG);
315 "FS_PHY programming HCFG to 48 MHz\n");
316 if (fslspclksel != HCFG_FSLSPCLKSEL_48_MHZ) {
317 fslspclksel = HCFG_FSLSPCLKSEL_48_MHZ;
318 hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
319 hcfg |= fslspclksel << HCFG_FSLSPCLKSEL_SHIFT;
320 dwc2_writel(hcfg, hsotg->regs + HCFG);
326 if (usbcfg & GUSBCFG_PHY_LP_CLK_SEL) {
327 usbcfg &= ~GUSBCFG_PHY_LP_CLK_SEL;
328 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
334 *hprt0_modify |= HPRT0_RST;
335 dwc2_writel(*hprt0_modify, hsotg->regs + HPRT0);
336 queue_delayed_work(hsotg->wq_otg, &hsotg->reset_work,
337 msecs_to_jiffies(60));
339 /* Port has been enabled, set the reset change flag */
340 hsotg->flags.b.port_reset_change = 1;
345 * There are multiple conditions that can cause a port interrupt. This function
346 * determines which interrupt conditions have occurred and handles them
349 static void dwc2_port_intr(struct dwc2_hsotg *hsotg)
354 dev_vdbg(hsotg->dev, "--Port Interrupt--\n");
356 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
357 hprt0_modify = hprt0;
360 * Clear appropriate bits in HPRT0 to clear the interrupt bit in
363 hprt0_modify &= ~(HPRT0_ENA | HPRT0_CONNDET | HPRT0_ENACHG |
367 * Port Connect Detected
368 * Set flag and clear if detected
370 if (hprt0 & HPRT0_CONNDET) {
371 dwc2_writel(hprt0_modify | HPRT0_CONNDET, hsotg->regs + HPRT0);
374 "--Port Interrupt HPRT0=0x%08x Port Connect Detected--\n",
376 dwc2_hcd_connect(hsotg);
379 * The Hub driver asserts a reset when it sees port connect
385 * Port Enable Changed
386 * Clear if detected - Set internal flag if disabled
388 if (hprt0 & HPRT0_ENACHG) {
389 dwc2_writel(hprt0_modify | HPRT0_ENACHG, hsotg->regs + HPRT0);
391 " --Port Interrupt HPRT0=0x%08x Port Enable Changed (now %d)--\n",
392 hprt0, !!(hprt0 & HPRT0_ENA));
393 if (hprt0 & HPRT0_ENA) {
394 hsotg->new_connection = true;
395 dwc2_hprt0_enable(hsotg, hprt0, &hprt0_modify);
397 hsotg->flags.b.port_enable_change = 1;
398 if (hsotg->core_params->dma_desc_fs_enable) {
401 hsotg->core_params->dma_desc_enable = 0;
402 hsotg->new_connection = false;
403 hcfg = dwc2_readl(hsotg->regs + HCFG);
404 hcfg &= ~HCFG_DESCDMA;
405 dwc2_writel(hcfg, hsotg->regs + HCFG);
410 /* Overcurrent Change Interrupt */
411 if (hprt0 & HPRT0_OVRCURRCHG) {
412 dwc2_writel(hprt0_modify | HPRT0_OVRCURRCHG,
413 hsotg->regs + HPRT0);
415 " --Port Interrupt HPRT0=0x%08x Port Overcurrent Changed--\n",
417 hsotg->flags.b.port_over_current_change = 1;
422 * Gets the actual length of a transfer after the transfer halts. halt_status
423 * holds the reason for the halt.
425 * For IN transfers where halt_status is DWC2_HC_XFER_COMPLETE, *short_read
426 * is set to 1 upon return if less than the requested number of bytes were
427 * transferred. short_read may also be NULL on entry, in which case it remains
430 static u32 dwc2_get_actual_xfer_length(struct dwc2_hsotg *hsotg,
431 struct dwc2_host_chan *chan, int chnum,
432 struct dwc2_qtd *qtd,
433 enum dwc2_halt_status halt_status,
436 u32 hctsiz, count, length;
438 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
440 if (halt_status == DWC2_HC_XFER_COMPLETE) {
441 if (chan->ep_is_in) {
442 count = (hctsiz & TSIZ_XFERSIZE_MASK) >>
444 length = chan->xfer_len - count;
445 if (short_read != NULL)
446 *short_read = (count != 0);
447 } else if (chan->qh->do_split) {
448 length = qtd->ssplit_out_xfer_count;
450 length = chan->xfer_len;
454 * Must use the hctsiz.pktcnt field to determine how much data
455 * has been transferred. This field reflects the number of
456 * packets that have been transferred via the USB. This is
457 * always an integral number of packets if the transfer was
458 * halted before its normal completion. (Can't use the
459 * hctsiz.xfersize field because that reflects the number of
460 * bytes transferred via the AHB, not the USB).
462 count = (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT;
463 length = (chan->start_pkt_count - count) * chan->max_packet;
470 * dwc2_update_urb_state() - Updates the state of the URB after a Transfer
471 * Complete interrupt on the host channel. Updates the actual_length field
472 * of the URB based on the number of bytes transferred via the host channel.
473 * Sets the URB status if the data transfer is finished.
475 * Return: 1 if the data transfer specified by the URB is completely finished,
478 static int dwc2_update_urb_state(struct dwc2_hsotg *hsotg,
479 struct dwc2_host_chan *chan, int chnum,
480 struct dwc2_hcd_urb *urb,
481 struct dwc2_qtd *qtd)
486 int xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
487 DWC2_HC_XFER_COMPLETE,
490 if (urb->actual_length + xfer_length > urb->length) {
491 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
492 xfer_length = urb->length - urb->actual_length;
495 dev_vdbg(hsotg->dev, "urb->actual_length=%d xfer_length=%d\n",
496 urb->actual_length, xfer_length);
497 urb->actual_length += xfer_length;
499 if (xfer_length && chan->ep_type == USB_ENDPOINT_XFER_BULK &&
500 (urb->flags & URB_SEND_ZERO_PACKET) &&
501 urb->actual_length >= urb->length &&
502 !(urb->length % chan->max_packet)) {
504 } else if (short_read || urb->actual_length >= urb->length) {
509 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
510 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
511 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
512 dev_vdbg(hsotg->dev, " chan->xfer_len %d\n", chan->xfer_len);
513 dev_vdbg(hsotg->dev, " hctsiz.xfersize %d\n",
514 (hctsiz & TSIZ_XFERSIZE_MASK) >> TSIZ_XFERSIZE_SHIFT);
515 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n", urb->length);
516 dev_vdbg(hsotg->dev, " urb->actual_length %d\n", urb->actual_length);
517 dev_vdbg(hsotg->dev, " short_read %d, xfer_done %d\n", short_read,
524 * Save the starting data toggle for the next transfer. The data toggle is
525 * saved in the QH for non-control transfers and it's saved in the QTD for
528 void dwc2_hcd_save_data_toggle(struct dwc2_hsotg *hsotg,
529 struct dwc2_host_chan *chan, int chnum,
530 struct dwc2_qtd *qtd)
532 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
533 u32 pid = (hctsiz & TSIZ_SC_MC_PID_MASK) >> TSIZ_SC_MC_PID_SHIFT;
535 if (chan->ep_type != USB_ENDPOINT_XFER_CONTROL) {
536 if (WARN(!chan || !chan->qh,
537 "chan->qh must be specified for non-control eps\n"))
540 if (pid == TSIZ_SC_MC_PID_DATA0)
541 chan->qh->data_toggle = DWC2_HC_PID_DATA0;
543 chan->qh->data_toggle = DWC2_HC_PID_DATA1;
546 "qtd must be specified for control eps\n"))
549 if (pid == TSIZ_SC_MC_PID_DATA0)
550 qtd->data_toggle = DWC2_HC_PID_DATA0;
552 qtd->data_toggle = DWC2_HC_PID_DATA1;
557 * dwc2_update_isoc_urb_state() - Updates the state of an Isochronous URB when
558 * the transfer is stopped for any reason. The fields of the current entry in
559 * the frame descriptor array are set based on the transfer state and the input
560 * halt_status. Completes the Isochronous URB if all the URB frames have been
563 * Return: DWC2_HC_XFER_COMPLETE if there are more frames remaining to be
564 * transferred in the URB. Otherwise return DWC2_HC_XFER_URB_COMPLETE.
566 static enum dwc2_halt_status dwc2_update_isoc_urb_state(
567 struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
568 int chnum, struct dwc2_qtd *qtd,
569 enum dwc2_halt_status halt_status)
571 struct dwc2_hcd_iso_packet_desc *frame_desc;
572 struct dwc2_hcd_urb *urb = qtd->urb;
575 return DWC2_HC_XFER_NO_HALT_STATUS;
577 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
579 switch (halt_status) {
580 case DWC2_HC_XFER_COMPLETE:
581 frame_desc->status = 0;
582 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
583 chan, chnum, qtd, halt_status, NULL);
585 case DWC2_HC_XFER_FRAME_OVERRUN:
588 frame_desc->status = -ENOSR;
590 frame_desc->status = -ECOMM;
591 frame_desc->actual_length = 0;
593 case DWC2_HC_XFER_BABBLE_ERR:
595 frame_desc->status = -EOVERFLOW;
596 /* Don't need to update actual_length in this case */
598 case DWC2_HC_XFER_XACT_ERR:
600 frame_desc->status = -EPROTO;
601 frame_desc->actual_length = dwc2_get_actual_xfer_length(hsotg,
602 chan, chnum, qtd, halt_status, NULL);
604 /* Skip whole frame */
605 if (chan->qh->do_split &&
606 chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
607 hsotg->core_params->dma_enable > 0) {
608 qtd->complete_split = 0;
609 qtd->isoc_split_offset = 0;
614 dev_err(hsotg->dev, "Unhandled halt_status (%d)\n",
619 if (++qtd->isoc_frame_index == urb->packet_count) {
621 * urb->status is not used for isoc transfers. The individual
622 * frame_desc statuses are used instead.
624 dwc2_host_complete(hsotg, qtd, 0);
625 halt_status = DWC2_HC_XFER_URB_COMPLETE;
627 halt_status = DWC2_HC_XFER_COMPLETE;
634 * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic
635 * QHs, removes the QH from the active non-periodic schedule. If any QTDs are
636 * still linked to the QH, the QH is added to the end of the inactive
637 * non-periodic schedule. For periodic QHs, removes the QH from the periodic
638 * schedule if no more QTDs are linked to the QH.
640 static void dwc2_deactivate_qh(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
643 int continue_split = 0;
644 struct dwc2_qtd *qtd;
647 dev_vdbg(hsotg->dev, " %s(%p,%p,%d)\n", __func__,
648 hsotg, qh, free_qtd);
650 if (list_empty(&qh->qtd_list)) {
651 dev_dbg(hsotg->dev, "## QTD list empty ##\n");
655 qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
657 if (qtd->complete_split)
659 else if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_MID ||
660 qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_END)
664 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
670 dwc2_hcd_qh_deactivate(hsotg, qh, continue_split);
674 * dwc2_release_channel() - Releases a host channel for use by other transfers
676 * @hsotg: The HCD state structure
677 * @chan: The host channel to release
678 * @qtd: The QTD associated with the host channel. This QTD may be
679 * freed if the transfer is complete or an error has occurred.
680 * @halt_status: Reason the channel is being released. This status
681 * determines the actions taken by this function.
683 * Also attempts to select and queue more transactions since at least one host
684 * channel is available.
686 static void dwc2_release_channel(struct dwc2_hsotg *hsotg,
687 struct dwc2_host_chan *chan,
688 struct dwc2_qtd *qtd,
689 enum dwc2_halt_status halt_status)
691 enum dwc2_transaction_type tr_type;
696 dev_vdbg(hsotg->dev, " %s: channel %d, halt_status %d\n",
697 __func__, chan->hc_num, halt_status);
699 switch (halt_status) {
700 case DWC2_HC_XFER_URB_COMPLETE:
703 case DWC2_HC_XFER_AHB_ERR:
704 case DWC2_HC_XFER_STALL:
705 case DWC2_HC_XFER_BABBLE_ERR:
708 case DWC2_HC_XFER_XACT_ERR:
709 if (qtd && qtd->error_count >= 3) {
711 " Complete URB with transaction error\n");
713 dwc2_host_complete(hsotg, qtd, -EPROTO);
716 case DWC2_HC_XFER_URB_DEQUEUE:
718 * The QTD has already been removed and the QH has been
719 * deactivated. Don't want to do anything except release the
720 * host channel and try to queue more transfers.
723 case DWC2_HC_XFER_PERIODIC_INCOMPLETE:
724 dev_vdbg(hsotg->dev, " Complete URB with I/O error\n");
726 dwc2_host_complete(hsotg, qtd, -EIO);
728 case DWC2_HC_XFER_NO_HALT_STATUS:
733 dwc2_deactivate_qh(hsotg, chan->qh, free_qtd);
737 * Release the host channel for use by other transfers. The cleanup
738 * function clears the channel interrupt enables and conditions, so
739 * there's no need to clear the Channel Halted interrupt separately.
741 if (!list_empty(&chan->hc_list_entry))
742 list_del(&chan->hc_list_entry);
743 dwc2_hc_cleanup(hsotg, chan);
744 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
746 if (hsotg->core_params->uframe_sched > 0) {
747 hsotg->available_host_channels++;
749 switch (chan->ep_type) {
750 case USB_ENDPOINT_XFER_CONTROL:
751 case USB_ENDPOINT_XFER_BULK:
752 hsotg->non_periodic_channels--;
756 * Don't release reservations for periodic channels
757 * here. That's done when a periodic transfer is
758 * descheduled (i.e. when the QH is removed from the
759 * periodic schedule).
765 haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
766 haintmsk &= ~(1 << chan->hc_num);
767 dwc2_writel(haintmsk, hsotg->regs + HAINTMSK);
769 /* Try to queue more transfers now that there's a free channel */
770 tr_type = dwc2_hcd_select_transactions(hsotg);
771 if (tr_type != DWC2_TRANSACTION_NONE)
772 dwc2_hcd_queue_transactions(hsotg, tr_type);
776 * Halts a host channel. If the channel cannot be halted immediately because
777 * the request queue is full, this function ensures that the FIFO empty
778 * interrupt for the appropriate queue is enabled so that the halt request can
779 * be queued when there is space in the request queue.
781 * This function may also be called in DMA mode. In that case, the channel is
782 * simply released since the core always halts the channel automatically in
785 static void dwc2_halt_channel(struct dwc2_hsotg *hsotg,
786 struct dwc2_host_chan *chan, struct dwc2_qtd *qtd,
787 enum dwc2_halt_status halt_status)
790 dev_vdbg(hsotg->dev, "%s()\n", __func__);
792 if (hsotg->core_params->dma_enable > 0) {
794 dev_vdbg(hsotg->dev, "DMA enabled\n");
795 dwc2_release_channel(hsotg, chan, qtd, halt_status);
799 /* Slave mode processing */
800 dwc2_hc_halt(hsotg, chan, halt_status);
802 if (chan->halt_on_queue) {
805 dev_vdbg(hsotg->dev, "Halt on queue\n");
806 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
807 chan->ep_type == USB_ENDPOINT_XFER_BULK) {
808 dev_vdbg(hsotg->dev, "control/bulk\n");
810 * Make sure the Non-periodic Tx FIFO empty interrupt
811 * is enabled so that the non-periodic schedule will
814 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
815 gintmsk |= GINTSTS_NPTXFEMP;
816 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
818 dev_vdbg(hsotg->dev, "isoc/intr\n");
820 * Move the QH from the periodic queued schedule to
821 * the periodic assigned schedule. This allows the
822 * halt to be queued when the periodic schedule is
825 list_move_tail(&chan->qh->qh_list_entry,
826 &hsotg->periodic_sched_assigned);
829 * Make sure the Periodic Tx FIFO Empty interrupt is
830 * enabled so that the periodic schedule will be
833 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
834 gintmsk |= GINTSTS_PTXFEMP;
835 dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
841 * Performs common cleanup for non-periodic transfers after a Transfer
842 * Complete interrupt. This function should be called after any endpoint type
843 * specific handling is finished to release the host channel.
845 static void dwc2_complete_non_periodic_xfer(struct dwc2_hsotg *hsotg,
846 struct dwc2_host_chan *chan,
847 int chnum, struct dwc2_qtd *qtd,
848 enum dwc2_halt_status halt_status)
850 dev_vdbg(hsotg->dev, "%s()\n", __func__);
852 qtd->error_count = 0;
854 if (chan->hcint & HCINTMSK_NYET) {
856 * Got a NYET on the last transaction of the transfer. This
857 * means that the endpoint should be in the PING state at the
858 * beginning of the next transfer.
860 dev_vdbg(hsotg->dev, "got NYET\n");
861 chan->qh->ping_state = 1;
865 * Always halt and release the host channel to make it available for
866 * more transfers. There may still be more phases for a control
867 * transfer or more data packets for a bulk transfer at this point,
868 * but the host channel is still halted. A channel will be reassigned
869 * to the transfer when the non-periodic schedule is processed after
870 * the channel is released. This allows transactions to be queued
871 * properly via dwc2_hcd_queue_transactions, which also enables the
872 * Tx FIFO Empty interrupt if necessary.
874 if (chan->ep_is_in) {
876 * IN transfers in Slave mode require an explicit disable to
877 * halt the channel. (In DMA mode, this call simply releases
880 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
883 * The channel is automatically disabled by the core for OUT
884 * transfers in Slave mode
886 dwc2_release_channel(hsotg, chan, qtd, halt_status);
891 * Performs common cleanup for periodic transfers after a Transfer Complete
892 * interrupt. This function should be called after any endpoint type specific
893 * handling is finished to release the host channel.
895 static void dwc2_complete_periodic_xfer(struct dwc2_hsotg *hsotg,
896 struct dwc2_host_chan *chan, int chnum,
897 struct dwc2_qtd *qtd,
898 enum dwc2_halt_status halt_status)
900 u32 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
902 qtd->error_count = 0;
904 if (!chan->ep_is_in || (hctsiz & TSIZ_PKTCNT_MASK) == 0)
905 /* Core halts channel in these cases */
906 dwc2_release_channel(hsotg, chan, qtd, halt_status);
908 /* Flush any outstanding requests from the Tx queue */
909 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
912 static int dwc2_xfercomp_isoc_split_in(struct dwc2_hsotg *hsotg,
913 struct dwc2_host_chan *chan, int chnum,
914 struct dwc2_qtd *qtd)
916 struct dwc2_hcd_iso_packet_desc *frame_desc;
922 frame_desc = &qtd->urb->iso_descs[qtd->isoc_frame_index];
923 len = dwc2_get_actual_xfer_length(hsotg, chan, chnum, qtd,
924 DWC2_HC_XFER_COMPLETE, NULL);
926 qtd->complete_split = 0;
927 qtd->isoc_split_offset = 0;
931 frame_desc->actual_length += len;
933 qtd->isoc_split_offset += len;
935 if (frame_desc->actual_length >= frame_desc->length) {
936 frame_desc->status = 0;
937 qtd->isoc_frame_index++;
938 qtd->complete_split = 0;
939 qtd->isoc_split_offset = 0;
942 if (qtd->isoc_frame_index == qtd->urb->packet_count) {
943 dwc2_host_complete(hsotg, qtd, 0);
944 dwc2_release_channel(hsotg, chan, qtd,
945 DWC2_HC_XFER_URB_COMPLETE);
947 dwc2_release_channel(hsotg, chan, qtd,
948 DWC2_HC_XFER_NO_HALT_STATUS);
951 return 1; /* Indicates that channel released */
955 * Handles a host channel Transfer Complete interrupt. This handler may be
956 * called in either DMA mode or Slave mode.
958 static void dwc2_hc_xfercomp_intr(struct dwc2_hsotg *hsotg,
959 struct dwc2_host_chan *chan, int chnum,
960 struct dwc2_qtd *qtd)
962 struct dwc2_hcd_urb *urb = qtd->urb;
963 enum dwc2_halt_status halt_status = DWC2_HC_XFER_COMPLETE;
969 "--Host Channel %d Interrupt: Transfer Complete--\n",
973 goto handle_xfercomp_done;
975 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
977 if (hsotg->core_params->dma_desc_enable > 0) {
978 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, halt_status);
979 if (pipe_type == USB_ENDPOINT_XFER_ISOC)
980 /* Do not disable the interrupt, just clear it */
982 goto handle_xfercomp_done;
985 /* Handle xfer complete on CSPLIT */
986 if (chan->qh->do_split) {
987 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && chan->ep_is_in &&
988 hsotg->core_params->dma_enable > 0) {
989 if (qtd->complete_split &&
990 dwc2_xfercomp_isoc_split_in(hsotg, chan, chnum,
992 goto handle_xfercomp_done;
994 qtd->complete_split = 0;
998 /* Update the QTD and URB states */
1000 case USB_ENDPOINT_XFER_CONTROL:
1001 switch (qtd->control_phase) {
1002 case DWC2_CONTROL_SETUP:
1003 if (urb->length > 0)
1004 qtd->control_phase = DWC2_CONTROL_DATA;
1006 qtd->control_phase = DWC2_CONTROL_STATUS;
1007 dev_vdbg(hsotg->dev,
1008 " Control setup transaction done\n");
1009 halt_status = DWC2_HC_XFER_COMPLETE;
1011 case DWC2_CONTROL_DATA:
1012 urb_xfer_done = dwc2_update_urb_state(hsotg, chan,
1014 if (urb_xfer_done) {
1015 qtd->control_phase = DWC2_CONTROL_STATUS;
1016 dev_vdbg(hsotg->dev,
1017 " Control data transfer done\n");
1019 dwc2_hcd_save_data_toggle(hsotg, chan, chnum,
1022 halt_status = DWC2_HC_XFER_COMPLETE;
1024 case DWC2_CONTROL_STATUS:
1025 dev_vdbg(hsotg->dev, " Control transfer complete\n");
1026 if (urb->status == -EINPROGRESS)
1028 dwc2_host_complete(hsotg, qtd, urb->status);
1029 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1033 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1036 case USB_ENDPOINT_XFER_BULK:
1037 dev_vdbg(hsotg->dev, " Bulk transfer complete\n");
1038 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1040 if (urb_xfer_done) {
1041 dwc2_host_complete(hsotg, qtd, urb->status);
1042 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1044 halt_status = DWC2_HC_XFER_COMPLETE;
1047 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1048 dwc2_complete_non_periodic_xfer(hsotg, chan, chnum, qtd,
1051 case USB_ENDPOINT_XFER_INT:
1052 dev_vdbg(hsotg->dev, " Interrupt transfer complete\n");
1053 urb_xfer_done = dwc2_update_urb_state(hsotg, chan, chnum, urb,
1057 * Interrupt URB is done on the first transfer complete
1060 if (urb_xfer_done) {
1061 dwc2_host_complete(hsotg, qtd, urb->status);
1062 halt_status = DWC2_HC_XFER_URB_COMPLETE;
1064 halt_status = DWC2_HC_XFER_COMPLETE;
1067 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1068 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1071 case USB_ENDPOINT_XFER_ISOC:
1073 dev_vdbg(hsotg->dev, " Isochronous transfer complete\n");
1074 if (qtd->isoc_split_pos == DWC2_HCSPLT_XACTPOS_ALL)
1075 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1076 chnum, qtd, DWC2_HC_XFER_COMPLETE);
1077 dwc2_complete_periodic_xfer(hsotg, chan, chnum, qtd,
1082 handle_xfercomp_done:
1083 disable_hc_int(hsotg, chnum, HCINTMSK_XFERCOMPL);
1087 * Handles a host channel STALL interrupt. This handler may be called in
1088 * either DMA mode or Slave mode.
1090 static void dwc2_hc_stall_intr(struct dwc2_hsotg *hsotg,
1091 struct dwc2_host_chan *chan, int chnum,
1092 struct dwc2_qtd *qtd)
1094 struct dwc2_hcd_urb *urb = qtd->urb;
1097 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: STALL Received--\n",
1100 if (hsotg->core_params->dma_desc_enable > 0) {
1101 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1102 DWC2_HC_XFER_STALL);
1103 goto handle_stall_done;
1107 goto handle_stall_halt;
1109 pipe_type = dwc2_hcd_get_pipe_type(&urb->pipe_info);
1111 if (pipe_type == USB_ENDPOINT_XFER_CONTROL)
1112 dwc2_host_complete(hsotg, qtd, -EPIPE);
1114 if (pipe_type == USB_ENDPOINT_XFER_BULK ||
1115 pipe_type == USB_ENDPOINT_XFER_INT) {
1116 dwc2_host_complete(hsotg, qtd, -EPIPE);
1118 * USB protocol requires resetting the data toggle for bulk
1119 * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT)
1120 * setup command is issued to the endpoint. Anticipate the
1121 * CLEAR_FEATURE command since a STALL has occurred and reset
1122 * the data toggle now.
1124 chan->qh->data_toggle = 0;
1128 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_STALL);
1131 disable_hc_int(hsotg, chnum, HCINTMSK_STALL);
1135 * Updates the state of the URB when a transfer has been stopped due to an
1136 * abnormal condition before the transfer completes. Modifies the
1137 * actual_length field of the URB to reflect the number of bytes that have
1138 * actually been transferred via the host channel.
1140 static void dwc2_update_urb_state_abn(struct dwc2_hsotg *hsotg,
1141 struct dwc2_host_chan *chan, int chnum,
1142 struct dwc2_hcd_urb *urb,
1143 struct dwc2_qtd *qtd,
1144 enum dwc2_halt_status halt_status)
1146 u32 xfer_length = dwc2_get_actual_xfer_length(hsotg, chan, chnum,
1147 qtd, halt_status, NULL);
1150 if (urb->actual_length + xfer_length > urb->length) {
1151 dev_warn(hsotg->dev, "%s(): trimming xfer length\n", __func__);
1152 xfer_length = urb->length - urb->actual_length;
1155 urb->actual_length += xfer_length;
1157 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1158 dev_vdbg(hsotg->dev, "DWC_otg: %s: %s, channel %d\n",
1159 __func__, (chan->ep_is_in ? "IN" : "OUT"), chnum);
1160 dev_vdbg(hsotg->dev, " chan->start_pkt_count %d\n",
1161 chan->start_pkt_count);
1162 dev_vdbg(hsotg->dev, " hctsiz.pktcnt %d\n",
1163 (hctsiz & TSIZ_PKTCNT_MASK) >> TSIZ_PKTCNT_SHIFT);
1164 dev_vdbg(hsotg->dev, " chan->max_packet %d\n", chan->max_packet);
1165 dev_vdbg(hsotg->dev, " bytes_transferred %d\n",
1167 dev_vdbg(hsotg->dev, " urb->actual_length %d\n",
1168 urb->actual_length);
1169 dev_vdbg(hsotg->dev, " urb->transfer_buffer_length %d\n",
1174 * Handles a host channel NAK interrupt. This handler may be called in either
1175 * DMA mode or Slave mode.
1177 static void dwc2_hc_nak_intr(struct dwc2_hsotg *hsotg,
1178 struct dwc2_host_chan *chan, int chnum,
1179 struct dwc2_qtd *qtd)
1182 dev_dbg(hsotg->dev, "%s: qtd is NULL\n", __func__);
1187 dev_dbg(hsotg->dev, "%s: qtd->urb is NULL\n", __func__);
1192 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NAK Received--\n",
1196 * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and
1197 * interrupt. Re-start the SSPLIT transfer.
1199 if (chan->do_split) {
1200 if (chan->complete_split)
1201 qtd->error_count = 0;
1202 qtd->complete_split = 0;
1203 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1204 goto handle_nak_done;
1207 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1208 case USB_ENDPOINT_XFER_CONTROL:
1209 case USB_ENDPOINT_XFER_BULK:
1210 if (hsotg->core_params->dma_enable > 0 && chan->ep_is_in) {
1212 * NAK interrupts are enabled on bulk/control IN
1213 * transfers in DMA mode for the sole purpose of
1214 * resetting the error count after a transaction error
1215 * occurs. The core will continue transferring data.
1217 qtd->error_count = 0;
1222 * NAK interrupts normally occur during OUT transfers in DMA
1223 * or Slave mode. For IN transfers, more requests will be
1224 * queued as request queue space is available.
1226 qtd->error_count = 0;
1228 if (!chan->qh->ping_state) {
1229 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1230 qtd, DWC2_HC_XFER_NAK);
1231 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1233 if (chan->speed == USB_SPEED_HIGH)
1234 chan->qh->ping_state = 1;
1238 * Halt the channel so the transfer can be re-started from
1239 * the appropriate point or the PING protocol will
1242 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1244 case USB_ENDPOINT_XFER_INT:
1245 qtd->error_count = 0;
1246 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NAK);
1248 case USB_ENDPOINT_XFER_ISOC:
1249 /* Should never get called for isochronous transfers */
1250 dev_err(hsotg->dev, "NACK interrupt for ISOC transfer\n");
1255 disable_hc_int(hsotg, chnum, HCINTMSK_NAK);
1259 * Handles a host channel ACK interrupt. This interrupt is enabled when
1260 * performing the PING protocol in Slave mode, when errors occur during
1261 * either Slave mode or DMA mode, and during Start Split transactions.
1263 static void dwc2_hc_ack_intr(struct dwc2_hsotg *hsotg,
1264 struct dwc2_host_chan *chan, int chnum,
1265 struct dwc2_qtd *qtd)
1267 struct dwc2_hcd_iso_packet_desc *frame_desc;
1270 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: ACK Received--\n",
1273 if (chan->do_split) {
1274 /* Handle ACK on SSPLIT. ACK should not occur in CSPLIT. */
1275 if (!chan->ep_is_in &&
1276 chan->data_pid_start != DWC2_HC_PID_SETUP)
1277 qtd->ssplit_out_xfer_count = chan->xfer_len;
1279 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC || chan->ep_is_in) {
1280 qtd->complete_split = 1;
1281 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1284 switch (chan->xact_pos) {
1285 case DWC2_HCSPLT_XACTPOS_ALL:
1287 case DWC2_HCSPLT_XACTPOS_END:
1288 qtd->isoc_split_pos = DWC2_HCSPLT_XACTPOS_ALL;
1289 qtd->isoc_split_offset = 0;
1291 case DWC2_HCSPLT_XACTPOS_BEGIN:
1292 case DWC2_HCSPLT_XACTPOS_MID:
1294 * For BEGIN or MID, calculate the length for
1295 * the next microframe to determine the correct
1296 * SSPLIT token, either MID or END
1298 frame_desc = &qtd->urb->iso_descs[
1299 qtd->isoc_frame_index];
1300 qtd->isoc_split_offset += 188;
1302 if (frame_desc->length - qtd->isoc_split_offset
1304 qtd->isoc_split_pos =
1305 DWC2_HCSPLT_XACTPOS_END;
1307 qtd->isoc_split_pos =
1308 DWC2_HCSPLT_XACTPOS_MID;
1313 qtd->error_count = 0;
1315 if (chan->qh->ping_state) {
1316 chan->qh->ping_state = 0;
1318 * Halt the channel so the transfer can be re-started
1319 * from the appropriate point. This only happens in
1320 * Slave mode. In DMA mode, the ping_state is cleared
1321 * when the transfer is started because the core
1322 * automatically executes the PING, then the transfer.
1324 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_ACK);
1329 * If the ACK occurred when _not_ in the PING state, let the channel
1330 * continue transferring data after clearing the error count
1332 disable_hc_int(hsotg, chnum, HCINTMSK_ACK);
1336 * Handles a host channel NYET interrupt. This interrupt should only occur on
1337 * Bulk and Control OUT endpoints and for complete split transactions. If a
1338 * NYET occurs at the same time as a Transfer Complete interrupt, it is
1339 * handled in the xfercomp interrupt handler, not here. This handler may be
1340 * called in either DMA mode or Slave mode.
1342 static void dwc2_hc_nyet_intr(struct dwc2_hsotg *hsotg,
1343 struct dwc2_host_chan *chan, int chnum,
1344 struct dwc2_qtd *qtd)
1347 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: NYET Received--\n",
1352 * re-do the CSPLIT immediately on non-periodic
1354 if (chan->do_split && chan->complete_split) {
1355 if (chan->ep_is_in && chan->ep_type == USB_ENDPOINT_XFER_ISOC &&
1356 hsotg->core_params->dma_enable > 0) {
1357 qtd->complete_split = 0;
1358 qtd->isoc_split_offset = 0;
1359 qtd->isoc_frame_index++;
1361 qtd->isoc_frame_index == qtd->urb->packet_count) {
1362 dwc2_host_complete(hsotg, qtd, 0);
1363 dwc2_release_channel(hsotg, chan, qtd,
1364 DWC2_HC_XFER_URB_COMPLETE);
1366 dwc2_release_channel(hsotg, chan, qtd,
1367 DWC2_HC_XFER_NO_HALT_STATUS);
1369 goto handle_nyet_done;
1372 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1373 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1374 struct dwc2_qh *qh = chan->qh;
1377 if (hsotg->core_params->uframe_sched <= 0) {
1378 int frnum = dwc2_hcd_get_frame_number(hsotg);
1380 /* Don't have num_hs_transfers; simple logic */
1381 past_end = dwc2_full_frame_num(frnum) !=
1382 dwc2_full_frame_num(qh->next_active_frame);
1387 * Figure out the end frame based on schedule.
1389 * We don't want to go on trying again and again
1390 * forever. Let's stop when we've done all the
1391 * transfers that were scheduled.
1393 * We're going to be comparing start_active_frame
1394 * and next_active_frame, both of which are 1
1395 * before the time the packet goes on the wire,
1396 * so that cancels out. Basically if had 1
1397 * transfer and we saw 1 NYET then we're done.
1398 * We're getting a NYET here so if next >=
1399 * (start + num_transfers) we're done. The
1400 * complexity is that for all but ISOC_OUT we
1403 end_frnum = dwc2_frame_num_inc(
1404 qh->start_active_frame,
1405 qh->num_hs_transfers);
1407 if (qh->ep_type != USB_ENDPOINT_XFER_ISOC ||
1410 dwc2_frame_num_inc(end_frnum, 1);
1412 past_end = dwc2_frame_num_le(
1413 end_frnum, qh->next_active_frame);
1417 /* Treat this as a transaction error. */
1420 * Todo: Fix system performance so this can
1421 * be treated as an error. Right now complete
1422 * splits cannot be scheduled precisely enough
1423 * due to other system activity, so this error
1424 * occurs regularly in Slave mode.
1428 qtd->complete_split = 0;
1429 dwc2_halt_channel(hsotg, chan, qtd,
1430 DWC2_HC_XFER_XACT_ERR);
1431 /* Todo: add support for isoc release */
1432 goto handle_nyet_done;
1436 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1437 goto handle_nyet_done;
1440 chan->qh->ping_state = 1;
1441 qtd->error_count = 0;
1443 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd,
1445 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1448 * Halt the channel and re-start the transfer so the PING protocol
1451 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_NYET);
1454 disable_hc_int(hsotg, chnum, HCINTMSK_NYET);
1458 * Handles a host channel babble interrupt. This handler may be called in
1459 * either DMA mode or Slave mode.
1461 static void dwc2_hc_babble_intr(struct dwc2_hsotg *hsotg,
1462 struct dwc2_host_chan *chan, int chnum,
1463 struct dwc2_qtd *qtd)
1465 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Babble Error--\n",
1468 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1470 if (hsotg->core_params->dma_desc_enable > 0) {
1471 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1472 DWC2_HC_XFER_BABBLE_ERR);
1476 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1477 dwc2_host_complete(hsotg, qtd, -EOVERFLOW);
1478 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_BABBLE_ERR);
1480 enum dwc2_halt_status halt_status;
1482 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1483 qtd, DWC2_HC_XFER_BABBLE_ERR);
1484 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1488 disable_hc_int(hsotg, chnum, HCINTMSK_BBLERR);
1492 * Handles a host channel AHB error interrupt. This handler is only called in
1495 static void dwc2_hc_ahberr_intr(struct dwc2_hsotg *hsotg,
1496 struct dwc2_host_chan *chan, int chnum,
1497 struct dwc2_qtd *qtd)
1499 struct dwc2_hcd_urb *urb = qtd->urb;
1500 char *pipetype, *speed;
1506 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: AHB Error--\n",
1510 goto handle_ahberr_halt;
1512 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1514 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1515 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1516 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1517 hc_dma = dwc2_readl(hsotg->regs + HCDMA(chnum));
1519 dev_err(hsotg->dev, "AHB ERROR, Channel %d\n", chnum);
1520 dev_err(hsotg->dev, " hcchar 0x%08x, hcsplt 0x%08x\n", hcchar, hcsplt);
1521 dev_err(hsotg->dev, " hctsiz 0x%08x, hc_dma 0x%08x\n", hctsiz, hc_dma);
1522 dev_err(hsotg->dev, " Device address: %d\n",
1523 dwc2_hcd_get_dev_addr(&urb->pipe_info));
1524 dev_err(hsotg->dev, " Endpoint: %d, %s\n",
1525 dwc2_hcd_get_ep_num(&urb->pipe_info),
1526 dwc2_hcd_is_pipe_in(&urb->pipe_info) ? "IN" : "OUT");
1528 switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
1529 case USB_ENDPOINT_XFER_CONTROL:
1530 pipetype = "CONTROL";
1532 case USB_ENDPOINT_XFER_BULK:
1535 case USB_ENDPOINT_XFER_INT:
1536 pipetype = "INTERRUPT";
1538 case USB_ENDPOINT_XFER_ISOC:
1539 pipetype = "ISOCHRONOUS";
1542 pipetype = "UNKNOWN";
1546 dev_err(hsotg->dev, " Endpoint type: %s\n", pipetype);
1548 switch (chan->speed) {
1549 case USB_SPEED_HIGH:
1552 case USB_SPEED_FULL:
1563 dev_err(hsotg->dev, " Speed: %s\n", speed);
1565 dev_err(hsotg->dev, " Max packet size: %d\n",
1566 dwc2_hcd_get_mps(&urb->pipe_info));
1567 dev_err(hsotg->dev, " Data buffer length: %d\n", urb->length);
1568 dev_err(hsotg->dev, " Transfer buffer: %p, Transfer DMA: %08lx\n",
1569 urb->buf, (unsigned long)urb->dma);
1570 dev_err(hsotg->dev, " Setup buffer: %p, Setup DMA: %08lx\n",
1571 urb->setup_packet, (unsigned long)urb->setup_dma);
1572 dev_err(hsotg->dev, " Interval: %d\n", urb->interval);
1574 /* Core halts the channel for Descriptor DMA mode */
1575 if (hsotg->core_params->dma_desc_enable > 0) {
1576 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1577 DWC2_HC_XFER_AHB_ERR);
1578 goto handle_ahberr_done;
1581 dwc2_host_complete(hsotg, qtd, -EIO);
1585 * Force a channel halt. Don't call dwc2_halt_channel because that won't
1586 * write to the HCCHARn register in DMA mode to force the halt.
1588 dwc2_hc_halt(hsotg, chan, DWC2_HC_XFER_AHB_ERR);
1591 disable_hc_int(hsotg, chnum, HCINTMSK_AHBERR);
1595 * Handles a host channel transaction error interrupt. This handler may be
1596 * called in either DMA mode or Slave mode.
1598 static void dwc2_hc_xacterr_intr(struct dwc2_hsotg *hsotg,
1599 struct dwc2_host_chan *chan, int chnum,
1600 struct dwc2_qtd *qtd)
1603 "--Host Channel %d Interrupt: Transaction Error--\n", chnum);
1605 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1607 if (hsotg->core_params->dma_desc_enable > 0) {
1608 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1609 DWC2_HC_XFER_XACT_ERR);
1610 goto handle_xacterr_done;
1613 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1614 case USB_ENDPOINT_XFER_CONTROL:
1615 case USB_ENDPOINT_XFER_BULK:
1617 if (!chan->qh->ping_state) {
1619 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1620 qtd, DWC2_HC_XFER_XACT_ERR);
1621 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1622 if (!chan->ep_is_in && chan->speed == USB_SPEED_HIGH)
1623 chan->qh->ping_state = 1;
1627 * Halt the channel so the transfer can be re-started from
1628 * the appropriate point or the PING protocol will start
1630 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1632 case USB_ENDPOINT_XFER_INT:
1634 if (chan->do_split && chan->complete_split)
1635 qtd->complete_split = 0;
1636 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1638 case USB_ENDPOINT_XFER_ISOC:
1640 enum dwc2_halt_status halt_status;
1642 halt_status = dwc2_update_isoc_urb_state(hsotg, chan,
1643 chnum, qtd, DWC2_HC_XFER_XACT_ERR);
1644 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1649 handle_xacterr_done:
1650 disable_hc_int(hsotg, chnum, HCINTMSK_XACTERR);
1654 * Handles a host channel frame overrun interrupt. This handler may be called
1655 * in either DMA mode or Slave mode.
1657 static void dwc2_hc_frmovrun_intr(struct dwc2_hsotg *hsotg,
1658 struct dwc2_host_chan *chan, int chnum,
1659 struct dwc2_qtd *qtd)
1661 enum dwc2_halt_status halt_status;
1664 dev_dbg(hsotg->dev, "--Host Channel %d Interrupt: Frame Overrun--\n",
1667 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1669 switch (dwc2_hcd_get_pipe_type(&qtd->urb->pipe_info)) {
1670 case USB_ENDPOINT_XFER_CONTROL:
1671 case USB_ENDPOINT_XFER_BULK:
1673 case USB_ENDPOINT_XFER_INT:
1674 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1676 case USB_ENDPOINT_XFER_ISOC:
1677 halt_status = dwc2_update_isoc_urb_state(hsotg, chan, chnum,
1678 qtd, DWC2_HC_XFER_FRAME_OVERRUN);
1679 dwc2_halt_channel(hsotg, chan, qtd, halt_status);
1683 disable_hc_int(hsotg, chnum, HCINTMSK_FRMOVRUN);
1687 * Handles a host channel data toggle error interrupt. This handler may be
1688 * called in either DMA mode or Slave mode.
1690 static void dwc2_hc_datatglerr_intr(struct dwc2_hsotg *hsotg,
1691 struct dwc2_host_chan *chan, int chnum,
1692 struct dwc2_qtd *qtd)
1695 "--Host Channel %d Interrupt: Data Toggle Error--\n", chnum);
1698 qtd->error_count = 0;
1701 "Data Toggle Error on OUT transfer, channel %d\n",
1704 dwc2_hc_handle_tt_clear(hsotg, chan, qtd);
1705 disable_hc_int(hsotg, chnum, HCINTMSK_DATATGLERR);
1709 * For debug only. It checks that a valid halt status is set and that
1710 * HCCHARn.chdis is clear. If there's a problem, corrective action is
1711 * taken and a warning is issued.
1713 * Return: true if halt status is ok, false otherwise
1715 static bool dwc2_halt_status_ok(struct dwc2_hsotg *hsotg,
1716 struct dwc2_host_chan *chan, int chnum,
1717 struct dwc2_qtd *qtd)
1725 if (chan->halt_status == DWC2_HC_XFER_NO_HALT_STATUS) {
1727 * This code is here only as a check. This condition should
1728 * never happen. Ignore the halt if it does occur.
1730 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1731 hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chnum));
1732 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1733 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chnum));
1735 "%s: chan->halt_status DWC2_HC_XFER_NO_HALT_STATUS,\n",
1738 "channel %d, hcchar 0x%08x, hctsiz 0x%08x,\n",
1739 chnum, hcchar, hctsiz);
1741 "hcint 0x%08x, hcintmsk 0x%08x, hcsplt 0x%08x,\n",
1742 chan->hcint, hcintmsk, hcsplt);
1744 dev_dbg(hsotg->dev, "qtd->complete_split %d\n",
1745 qtd->complete_split);
1746 dev_warn(hsotg->dev,
1747 "%s: no halt status, channel %d, ignoring interrupt\n",
1753 * This code is here only as a check. hcchar.chdis should never be set
1754 * when the halt interrupt occurs. Halt the channel again if it does
1757 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chnum));
1758 if (hcchar & HCCHAR_CHDIS) {
1759 dev_warn(hsotg->dev,
1760 "%s: hcchar.chdis set unexpectedly, hcchar 0x%08x, trying to halt again\n",
1762 chan->halt_pending = 0;
1763 dwc2_halt_channel(hsotg, chan, qtd, chan->halt_status);
1772 * Handles a host Channel Halted interrupt in DMA mode. This handler
1773 * determines the reason the channel halted and proceeds accordingly.
1775 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg,
1776 struct dwc2_host_chan *chan, int chnum,
1777 struct dwc2_qtd *qtd)
1780 int out_nak_enh = 0;
1783 dev_vdbg(hsotg->dev,
1784 "--Host Channel %d Interrupt: DMA Channel Halted--\n",
1788 * For core with OUT NAK enhancement, the flow for high-speed
1789 * CONTROL/BULK OUT is handled a little differently
1791 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
1792 if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in &&
1793 (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1794 chan->ep_type == USB_ENDPOINT_XFER_BULK)) {
1799 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1800 (chan->halt_status == DWC2_HC_XFER_AHB_ERR &&
1801 hsotg->core_params->dma_desc_enable <= 0)) {
1802 if (hsotg->core_params->dma_desc_enable > 0)
1803 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
1807 * Just release the channel. A dequeue can happen on a
1808 * transfer timeout. In the case of an AHB Error, the
1809 * channel was forced to halt because there's no way to
1810 * gracefully recover.
1812 dwc2_release_channel(hsotg, chan, qtd,
1817 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1819 if (chan->hcint & HCINTMSK_XFERCOMPL) {
1821 * Todo: This is here because of a possible hardware bug. Spec
1822 * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
1823 * interrupt w/ACK bit set should occur, but I only see the
1824 * XFERCOMP bit, even with it masked out. This is a workaround
1825 * for that behavior. Should fix this when hardware is fixed.
1827 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in)
1828 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1829 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
1830 } else if (chan->hcint & HCINTMSK_STALL) {
1831 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
1832 } else if ((chan->hcint & HCINTMSK_XACTERR) &&
1833 hsotg->core_params->dma_desc_enable <= 0) {
1836 (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
1837 dev_vdbg(hsotg->dev,
1838 "XactErr with NYET/NAK/ACK\n");
1839 qtd->error_count = 0;
1841 dev_vdbg(hsotg->dev,
1842 "XactErr without NYET/NAK/ACK\n");
1847 * Must handle xacterr before nak or ack. Could get a xacterr
1848 * at the same time as either of these on a BULK/CONTROL OUT
1849 * that started with a PING. The xacterr takes precedence.
1851 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1852 } else if ((chan->hcint & HCINTMSK_XCS_XACT) &&
1853 hsotg->core_params->dma_desc_enable > 0) {
1854 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
1855 } else if ((chan->hcint & HCINTMSK_AHBERR) &&
1856 hsotg->core_params->dma_desc_enable > 0) {
1857 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
1858 } else if (chan->hcint & HCINTMSK_BBLERR) {
1859 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
1860 } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
1861 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
1862 } else if (!out_nak_enh) {
1863 if (chan->hcint & HCINTMSK_NYET) {
1865 * Must handle nyet before nak or ack. Could get a nyet
1866 * at the same time as either of those on a BULK/CONTROL
1867 * OUT that started with a PING. The nyet takes
1870 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
1871 } else if ((chan->hcint & HCINTMSK_NAK) &&
1872 !(hcintmsk & HCINTMSK_NAK)) {
1874 * If nak is not masked, it's because a non-split IN
1875 * transfer is in an error state. In that case, the nak
1876 * is handled by the nak interrupt handler, not here.
1877 * Handle nak here for BULK/CONTROL OUT transfers, which
1878 * halt on a NAK to allow rewinding the buffer pointer.
1880 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
1881 } else if ((chan->hcint & HCINTMSK_ACK) &&
1882 !(hcintmsk & HCINTMSK_ACK)) {
1884 * If ack is not masked, it's because a non-split IN
1885 * transfer is in an error state. In that case, the ack
1886 * is handled by the ack interrupt handler, not here.
1887 * Handle ack here for split transfers. Start splits
1890 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
1892 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1893 chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1895 * A periodic transfer halted with no other
1896 * channel interrupts set. Assume it was halted
1897 * by the core because it could not be completed
1898 * in its scheduled (micro)frame.
1901 "%s: Halt channel %d (assume incomplete periodic transfer)\n",
1903 dwc2_halt_channel(hsotg, chan, qtd,
1904 DWC2_HC_XFER_PERIODIC_INCOMPLETE);
1907 "%s: Channel %d - ChHltd set, but reason is unknown\n",
1910 "hcint 0x%08x, intsts 0x%08x\n",
1912 dwc2_readl(hsotg->regs + GINTSTS));
1917 dev_info(hsotg->dev,
1918 "NYET/NAK/ACK/other in non-error case, 0x%08x\n",
1921 /* Failthrough: use 3-strikes rule */
1923 dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb,
1924 qtd, DWC2_HC_XFER_XACT_ERR);
1925 dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
1926 dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
1931 * Handles a host channel Channel Halted interrupt
1933 * In slave mode, this handler is called only when the driver specifically
1934 * requests a halt. This occurs during handling other host channel interrupts
1935 * (e.g. nak, xacterr, stall, nyet, etc.).
1937 * In DMA mode, this is the interrupt that occurs when the core has finished
1938 * processing a transfer on a channel. Other host channel interrupts (except
1939 * ahberr) are disabled in DMA mode.
1941 static void dwc2_hc_chhltd_intr(struct dwc2_hsotg *hsotg,
1942 struct dwc2_host_chan *chan, int chnum,
1943 struct dwc2_qtd *qtd)
1946 dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: Channel Halted--\n",
1949 if (hsotg->core_params->dma_enable > 0) {
1950 dwc2_hc_chhltd_intr_dma(hsotg, chan, chnum, qtd);
1952 if (!dwc2_halt_status_ok(hsotg, chan, chnum, qtd))
1954 dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
1959 * Check if the given qtd is still the top of the list (and thus valid).
1961 * If dwc2_hcd_qtd_unlink_and_free() has been called since we grabbed
1962 * the qtd from the top of the list, this will return false (otherwise true).
1964 static bool dwc2_check_qtd_still_ok(struct dwc2_qtd *qtd, struct dwc2_qh *qh)
1966 struct dwc2_qtd *cur_head;
1971 cur_head = list_first_entry(&qh->qtd_list, struct dwc2_qtd,
1973 return (cur_head == qtd);
1976 /* Handles interrupt for a specific Host Channel */
1977 static void dwc2_hc_n_intr(struct dwc2_hsotg *hsotg, int chnum)
1979 struct dwc2_qtd *qtd;
1980 struct dwc2_host_chan *chan;
1981 u32 hcint, hcintmsk;
1983 chan = hsotg->hc_ptr_array[chnum];
1985 hcint = dwc2_readl(hsotg->regs + HCINT(chnum));
1986 hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
1988 dev_err(hsotg->dev, "## hc_ptr_array for channel is NULL ##\n");
1989 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
1994 dev_vdbg(hsotg->dev, "--Host Channel Interrupt--, Channel %d\n",
1996 dev_vdbg(hsotg->dev,
1997 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
1998 hcint, hcintmsk, hcint & hcintmsk);
2001 dwc2_writel(hcint, hsotg->regs + HCINT(chnum));
2004 * If we got an interrupt after someone called
2005 * dwc2_hcd_endpoint_disable() we don't want to crash below
2008 dev_warn(hsotg->dev, "Interrupt on disabled channel\n");
2012 chan->hcint = hcint;
2016 * If the channel was halted due to a dequeue, the qtd list might
2017 * be empty or at least the first entry will not be the active qtd.
2018 * In this case, take a shortcut and just release the channel.
2020 if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE) {
2022 * If the channel was halted, this should be the only
2023 * interrupt unmasked
2025 WARN_ON(hcint != HCINTMSK_CHHLTD);
2026 if (hsotg->core_params->dma_desc_enable > 0)
2027 dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum,
2030 dwc2_release_channel(hsotg, chan, NULL,
2035 if (list_empty(&chan->qh->qtd_list)) {
2037 * TODO: Will this ever happen with the
2038 * DWC2_HC_XFER_URB_DEQUEUE handling above?
2040 dev_dbg(hsotg->dev, "## no QTD queued for channel %d ##\n",
2043 " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n",
2044 chan->hcint, hcintmsk, hcint);
2045 chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
2046 disable_hc_int(hsotg, chnum, HCINTMSK_CHHLTD);
2051 qtd = list_first_entry(&chan->qh->qtd_list, struct dwc2_qtd,
2054 if (hsotg->core_params->dma_enable <= 0) {
2055 if ((hcint & HCINTMSK_CHHLTD) && hcint != HCINTMSK_CHHLTD)
2056 hcint &= ~HCINTMSK_CHHLTD;
2059 if (hcint & HCINTMSK_XFERCOMPL) {
2060 dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
2062 * If NYET occurred at same time as Xfer Complete, the NYET is
2063 * handled by the Xfer Complete interrupt handler. Don't want
2064 * to call the NYET interrupt handler in this case.
2066 hcint &= ~HCINTMSK_NYET;
2069 if (hcint & HCINTMSK_CHHLTD) {
2070 dwc2_hc_chhltd_intr(hsotg, chan, chnum, qtd);
2071 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2074 if (hcint & HCINTMSK_AHBERR) {
2075 dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
2076 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2079 if (hcint & HCINTMSK_STALL) {
2080 dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
2081 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2084 if (hcint & HCINTMSK_NAK) {
2085 dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
2086 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2089 if (hcint & HCINTMSK_ACK) {
2090 dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
2091 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2094 if (hcint & HCINTMSK_NYET) {
2095 dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
2096 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2099 if (hcint & HCINTMSK_XACTERR) {
2100 dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
2101 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2104 if (hcint & HCINTMSK_BBLERR) {
2105 dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
2106 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2109 if (hcint & HCINTMSK_FRMOVRUN) {
2110 dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
2111 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2114 if (hcint & HCINTMSK_DATATGLERR) {
2115 dwc2_hc_datatglerr_intr(hsotg, chan, chnum, qtd);
2116 if (!dwc2_check_qtd_still_ok(qtd, chan->qh))
2125 * This interrupt indicates that one or more host channels has a pending
2126 * interrupt. There are multiple conditions that can cause each host channel
2127 * interrupt. This function determines which conditions have occurred for each
2128 * host channel interrupt and handles them appropriately.
2130 static void dwc2_hc_intr(struct dwc2_hsotg *hsotg)
2134 struct dwc2_host_chan *chan, *chan_tmp;
2136 haint = dwc2_readl(hsotg->regs + HAINT);
2138 dev_vdbg(hsotg->dev, "%s()\n", __func__);
2140 dev_vdbg(hsotg->dev, "HAINT=%08x\n", haint);
2144 * According to USB 2.0 spec section 11.18.8, a host must
2145 * issue complete-split transactions in a microframe for a
2146 * set of full-/low-speed endpoints in the same relative
2147 * order as the start-splits were issued in a microframe for.
2149 list_for_each_entry_safe(chan, chan_tmp, &hsotg->split_order,
2150 split_order_list_entry) {
2151 int hc_num = chan->hc_num;
2153 if (haint & (1 << hc_num)) {
2154 dwc2_hc_n_intr(hsotg, hc_num);
2155 haint &= ~(1 << hc_num);
2159 for (i = 0; i < hsotg->core_params->host_channels; i++) {
2160 if (haint & (1 << i))
2161 dwc2_hc_n_intr(hsotg, i);
2165 /* This function handles interrupts for the HCD */
2166 irqreturn_t dwc2_handle_hcd_intr(struct dwc2_hsotg *hsotg)
2168 u32 gintsts, dbg_gintsts;
2169 irqreturn_t retval = IRQ_NONE;
2171 if (!dwc2_is_controller_alive(hsotg)) {
2172 dev_warn(hsotg->dev, "Controller is dead\n");
2176 spin_lock(&hsotg->lock);
2178 /* Check if HOST Mode */
2179 if (dwc2_is_host_mode(hsotg)) {
2180 gintsts = dwc2_read_core_intr(hsotg);
2182 spin_unlock(&hsotg->lock);
2186 retval = IRQ_HANDLED;
2188 dbg_gintsts = gintsts;
2190 dbg_gintsts &= ~GINTSTS_SOF;
2193 dbg_gintsts &= ~(GINTSTS_HCHINT | GINTSTS_RXFLVL |
2196 /* Only print if there are any non-suppressed interrupts left */
2198 dev_vdbg(hsotg->dev,
2199 "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n",
2202 if (gintsts & GINTSTS_SOF)
2203 dwc2_sof_intr(hsotg);
2204 if (gintsts & GINTSTS_RXFLVL)
2205 dwc2_rx_fifo_level_intr(hsotg);
2206 if (gintsts & GINTSTS_NPTXFEMP)
2207 dwc2_np_tx_fifo_empty_intr(hsotg);
2208 if (gintsts & GINTSTS_PRTINT)
2209 dwc2_port_intr(hsotg);
2210 if (gintsts & GINTSTS_HCHINT)
2211 dwc2_hc_intr(hsotg);
2212 if (gintsts & GINTSTS_PTXFEMP)
2213 dwc2_perio_tx_fifo_empty_intr(hsotg);
2216 dev_vdbg(hsotg->dev,
2217 "DWC OTG HCD Finished Servicing Interrupts\n");
2218 dev_vdbg(hsotg->dev,
2219 "DWC OTG HCD gintsts=0x%08x gintmsk=0x%08x\n",
2220 dwc2_readl(hsotg->regs + GINTSTS),
2221 dwc2_readl(hsotg->regs + GINTMSK));
2225 spin_unlock(&hsotg->lock);