drivers/usb/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260         /* All channels have been freed, mark them available */
 261         if (hsotg->core_params->uframe_sched > 0) {
 262                 hsotg->available_host_channels =
 263                         hsotg->core_params->host_channels;
 264         } else {
 265                 hsotg->non_periodic_channels = 0;
 266                 hsotg->periodic_channels = 0;
 267         }
 268 }
 269
 270 /**
 271  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 272  *
 273  * @hsotg: Pointer to struct dwc2_hsotg
 274  *
 275  * Must be called with interrupt disabled and spinlock held
 276  */
 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 278 {
 279         u32 intr;
 280
 281         /* Set status flags for the hub driver */
 282         hsotg->flags.b.port_connect_status_change = 1;
 283         hsotg->flags.b.port_connect_status = 0;
 284
 285         /*
 286          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 287          * interrupt mask and status bits and disabling subsequent host
 288          * channel interrupts.
 289          */
 290         intr = dwc2_readl(hsotg->regs + GINTMSK);
 291         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 292         dwc2_writel(intr, hsotg->regs + GINTMSK);
 293         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 294         dwc2_writel(intr, hsotg->regs + GINTSTS);
 295
 296         /*
 297          * Turn off the vbus power only if the core has transitioned to device
 298          * mode. If still in host mode, need to keep power on to detect a
 299          * reconnection.
 300          */
 301         if (dwc2_is_device_mode(hsotg)) {
 302                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 303                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 304                         dwc2_writel(0, hsotg->regs + HPRT0);
 305                 }
 306
 307                 dwc2_disable_host_interrupts(hsotg);
 308         }
 309
 310         /* Respond with an error status to all URBs in the schedule */
 311         dwc2_kill_all_urbs(hsotg);
 312
 313         if (dwc2_is_host_mode(hsotg))
 314                 /* Clean up any host channels that were in use */
 315                 dwc2_hcd_cleanup_channels(hsotg);
 316
 317         dwc2_host_disconnect(hsotg);
 318 }
 319
 320 /**
 321  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 322  *
 323  * @hsotg: Pointer to struct dwc2_hsotg
 324  */
 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 326 {
 327         if (hsotg->bus_suspended) {
 328                 hsotg->flags.b.port_suspend_change = 1;
 329                 usb_hcd_resume_root_hub(hsotg->priv);
 330         }
 331
 332         if (hsotg->lx_state == DWC2_L1)
 333                 hsotg->flags.b.port_l1_change = 1;
 334 }
 335
 336 /**
 337  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 338  *
 339  * @hsotg: Pointer to struct dwc2_hsotg
 340  *
 341  * Must be called with interrupt disabled and spinlock held
 342  */
 343 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 344 {
 345         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 346
 347         /*
 348          * The root hub should be disconnected before this function is called.
 349          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 350          * and the QH lists (via ..._hcd_endpoint_disable).
 351          */
 352
 353         /* Turn off all host-specific interrupts */
 354         dwc2_disable_host_interrupts(hsotg);
 355
 356         /* Turn off the vbus power */
 357         dev_dbg(hsotg->dev, "PortPower off\n");
 358         dwc2_writel(0, hsotg->regs + HPRT0);
 359 }
 360
 361 /* Caller must hold driver lock */
 362 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 363                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
 364                                 struct dwc2_qtd *qtd)
 365 {
 366         u32 intr_mask;
 367         int retval;
 368         int dev_speed;
 369
 370         if (!hsotg->flags.b.port_connect_status) {
 371                 /* No longer connected */
 372                 dev_err(hsotg->dev, "Not connected\n");
 373                 return -ENODEV;
 374         }
 375
 376         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
 377
 378         /* Some configurations cannot support LS traffic on a FS root port */
 379         if ((dev_speed == USB_SPEED_LOW) &&
 380             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
 381             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
 382                 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 383                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 384
 385                 if (prtspd == HPRT0_SPD_FULL_SPEED)
 386                         return -ENODEV;
 387         }
 388
 389         if (!qtd)
 390                 return -EINVAL;
 391
 392         dwc2_hcd_qtd_init(qtd, urb);
 393         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
 394         if (retval) {
 395                 dev_err(hsotg->dev,
 396                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 397                         retval);
 398                 return retval;
 399         }
 400
 401         intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
 402         if (!(intr_mask & GINTSTS_SOF)) {
 403                 enum dwc2_transaction_type tr_type;
 404
 405                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 406                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 407                         /*
 408                          * Do not schedule SG transactions until qtd has
 409                          * URB_GIVEBACK_ASAP set
 410                          */
 411                         return 0;
 412
 413                 tr_type = dwc2_hcd_select_transactions(hsotg);
 414                 if (tr_type != DWC2_TRANSACTION_NONE)
 415                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* Must be called with interrupt disabled and spinlock held */
 422 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 423                                 struct dwc2_hcd_urb *urb)
 424 {
 425         struct dwc2_qh *qh;
 426         struct dwc2_qtd *urb_qtd;
 427
 428         urb_qtd = urb->qtd;
 429         if (!urb_qtd) {
 430                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 431                 return -EINVAL;
 432         }
 433
 434         qh = urb_qtd->qh;
 435         if (!qh) {
 436                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 437                 return -EINVAL;
 438         }
 439
 440         urb->priv = NULL;
 441
 442         if (urb_qtd->in_process && qh->channel) {
 443                 dwc2_dump_channel_info(hsotg, qh->channel);
 444
 445                 /* The QTD is in process (it has been assigned to a channel) */
 446                 if (hsotg->flags.b.port_connect_status)
 447                         /*
 448                          * If still connected (i.e. in host mode), halt the
 449                          * channel so it can be used for other transfers. If
 450                          * no longer connected, the host registers can't be
 451                          * written to halt the channel since the core is in
 452                          * device mode.
 453                          */
 454                         dwc2_hc_halt(hsotg, qh->channel,
 455                                      DWC2_HC_XFER_URB_DEQUEUE);
 456         }
 457
 458         /*
 459          * Free the QTD and clean up the associated QH. Leave the QH in the
 460          * schedule if it has any remaining QTDs.
 461          */
 462         if (hsotg->core_params->dma_desc_enable <= 0) {
 463                 u8 in_process = urb_qtd->in_process;
 464
 465                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 466                 if (in_process) {
 467                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 468                         qh->channel = NULL;
 469                 } else if (list_empty(&qh->qtd_list)) {
 470                         dwc2_hcd_qh_unlink(hsotg, qh);
 471                 }
 472         } else {
 473                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 474         }
 475
 476         return 0;
 477 }
 478
 479 /* Must NOT be called with interrupt disabled or spinlock held */
 480 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 481                                      struct usb_host_endpoint *ep, int retry)
 482 {
 483         struct dwc2_qtd *qtd, *qtd_tmp;
 484         struct dwc2_qh *qh;
 485         unsigned long flags;
 486         int rc;
 487
 488         spin_lock_irqsave(&hsotg->lock, flags);
 489
 490         qh = ep->hcpriv;
 491         if (!qh) {
 492                 rc = -EINVAL;
 493                 goto err;
 494         }
 495
 496         while (!list_empty(&qh->qtd_list) && retry--) {
 497                 if (retry == 0) {
 498                         dev_err(hsotg->dev,
 499                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 500                         rc = -EBUSY;
 501                         goto err;
 502                 }
 503
 504                 spin_unlock_irqrestore(&hsotg->lock, flags);
 505                 usleep_range(20000, 40000);
 506                 spin_lock_irqsave(&hsotg->lock, flags);
 507                 qh = ep->hcpriv;
 508                 if (!qh) {
 509                         rc = -EINVAL;
 510                         goto err;
 511                 }
 512         }
 513
 514         dwc2_hcd_qh_unlink(hsotg, qh);
 515
 516         /* Free each QTD in the QH's QTD list */
 517         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 518                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 519
 520         ep->hcpriv = NULL;
 521         spin_unlock_irqrestore(&hsotg->lock, flags);
 522         dwc2_hcd_qh_free(hsotg, qh);
 523
 524         return 0;
 525
 526 err:
 527         ep->hcpriv = NULL;
 528         spin_unlock_irqrestore(&hsotg->lock, flags);
 529
 530         return rc;
 531 }
 532
 533 /* Must be called with interrupt disabled and spinlock held */
 534 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 535                                    struct usb_host_endpoint *ep)
 536 {
 537         struct dwc2_qh *qh = ep->hcpriv;
 538
 539         if (!qh)
 540                 return -EINVAL;
 541
 542         qh->data_toggle = DWC2_HC_PID_DATA0;
 543
 544         return 0;
 545 }
 546
 547 /*
 548  * Initializes dynamic portions of the DWC_otg HCD state
 549  *
 550  * Must be called with interrupt disabled and spinlock held
 551  */
 552 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 553 {
 554         struct dwc2_host_chan *chan, *chan_tmp;
 555         int num_channels;
 556         int i;
 557
 558         hsotg->flags.d32 = 0;
 559         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 560
 561         if (hsotg->core_params->uframe_sched > 0) {
 562                 hsotg->available_host_channels =
 563                         hsotg->core_params->host_channels;
 564         } else {
 565                 hsotg->non_periodic_channels = 0;
 566                 hsotg->periodic_channels = 0;
 567         }
 568
 569         /*
 570          * Put all channels in the free channel list and clean up channel
 571          * states
 572          */
 573         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 574                                  hc_list_entry)
 575                 list_del_init(&chan->hc_list_entry);
 576
 577         num_channels = hsotg->core_params->host_channels;
 578         for (i = 0; i < num_channels; i++) {
 579                 chan = hsotg->hc_ptr_array[i];
 580                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 581                 dwc2_hc_cleanup(hsotg, chan);
 582         }
 583
 584         /* Initialize the DWC core for host mode operation */
 585         dwc2_core_host_init(hsotg);
 586 }
 587
 588 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 589                                struct dwc2_host_chan *chan,
 590                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 591 {
 592         int hub_addr, hub_port;
 593
 594         chan->do_split = 1;
 595         chan->xact_pos = qtd->isoc_split_pos;
 596         chan->complete_split = qtd->complete_split;
 597         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 598         chan->hub_addr = (u8)hub_addr;
 599         chan->hub_port = (u8)hub_port;
 600 }
 601
 602 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 603                                struct dwc2_host_chan *chan,
 604                                struct dwc2_qtd *qtd, void *bufptr)
 605 {
 606         struct dwc2_hcd_urb *urb = qtd->urb;
 607         struct dwc2_hcd_iso_packet_desc *frame_desc;
 608
 609         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 610         case USB_ENDPOINT_XFER_CONTROL:
 611                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 612
 613                 switch (qtd->control_phase) {
 614                 case DWC2_CONTROL_SETUP:
 615                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 616                         chan->do_ping = 0;
 617                         chan->ep_is_in = 0;
 618                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 619                         if (hsotg->core_params->dma_enable > 0)
 620                                 chan->xfer_dma = urb->setup_dma;
 621                         else
 622                                 chan->xfer_buf = urb->setup_packet;
 623                         chan->xfer_len = 8;
 624                         bufptr = NULL;
 625                         break;
 626
 627                 case DWC2_CONTROL_DATA:
 628                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 629                         chan->data_pid_start = qtd->data_toggle;
 630                         break;
 631
 632                 case DWC2_CONTROL_STATUS:
 633                         /*
 634                          * Direction is opposite of data direction or IN if no
 635                          * data
 636                          */
 637                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 638                         if (urb->length == 0)
 639                                 chan->ep_is_in = 1;
 640                         else
 641                                 chan->ep_is_in =
 642                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 643                         if (chan->ep_is_in)
 644                                 chan->do_ping = 0;
 645                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 646                         chan->xfer_len = 0;
 647                         if (hsotg->core_params->dma_enable > 0)
 648                                 chan->xfer_dma = hsotg->status_buf_dma;
 649                         else
 650                                 chan->xfer_buf = hsotg->status_buf;
 651                         bufptr = NULL;
 652                         break;
 653                 }
 654                 break;
 655
 656         case USB_ENDPOINT_XFER_BULK:
 657                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 658                 break;
 659
 660         case USB_ENDPOINT_XFER_INT:
 661                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 662                 break;
 663
 664         case USB_ENDPOINT_XFER_ISOC:
 665                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 666                 if (hsotg->core_params->dma_desc_enable > 0)
 667                         break;
 668
 669                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 670                 frame_desc->status = 0;
 671
 672                 if (hsotg->core_params->dma_enable > 0) {
 673                         chan->xfer_dma = urb->dma;
 674                         chan->xfer_dma += frame_desc->offset +
 675                                         qtd->isoc_split_offset;
 676                 } else {
 677                         chan->xfer_buf = urb->buf;
 678                         chan->xfer_buf += frame_desc->offset +
 679                                         qtd->isoc_split_offset;
 680                 }
 681
 682                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 683
 684                 /* For non-dword aligned buffers */
 685                 if (hsotg->core_params->dma_enable > 0 &&
 686                     (chan->xfer_dma & 0x3))
 687                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 688                                         qtd->isoc_split_offset;
 689                 else
 690                         bufptr = NULL;
 691
 692                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 693                         if (chan->xfer_len <= 188)
 694                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 695                         else
 696                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 697                 }
 698                 break;
 699         }
 700
 701         return bufptr;
 702 }
 703
 704 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 705                                    struct dwc2_host_chan *chan,
 706                                    struct dwc2_hcd_urb *urb, void *bufptr)
 707 {
 708         u32 buf_size;
 709         struct urb *usb_urb;
 710         struct usb_hcd *hcd;
 711
 712         if (!qh->dw_align_buf) {
 713                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 714                         buf_size = hsotg->core_params->max_transfer_size;
 715                 else
 716                         /* 3072 = 3 max-size Isoc packets */
 717                         buf_size = 3072;
 718
 719                 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
 720                 if (!qh->dw_align_buf)
 721                         return -ENOMEM;
 722                 qh->dw_align_buf_size = buf_size;
 723         }
 724
 725         if (chan->xfer_len) {
 726                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 727                 usb_urb = urb->priv;
 728
 729                 if (usb_urb) {
 730                         if (usb_urb->transfer_flags &
 731                             (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
 732                              URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
 733                                 hcd = dwc2_hsotg_to_hcd(hsotg);
 734                                 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
 735                         }
 736                         if (!chan->ep_is_in)
 737                                 memcpy(qh->dw_align_buf, bufptr,
 738                                        chan->xfer_len);
 739                 } else {
 740                         dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
 741                 }
 742         }
 743
 744         qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
 745                         qh->dw_align_buf, qh->dw_align_buf_size,
 746                         chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
 747         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
 748                 dev_err(hsotg->dev, "can't map align_buf\n");
 749                 chan->align_buf = 0;
 750                 return -EINVAL;
 751         }
 752
 753         chan->align_buf = qh->dw_align_buf_dma;
 754         return 0;
 755 }
 756
 757 /**
 758  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 759  * channel and initializes the host channel to perform the transactions. The
 760  * host channel is removed from the free list.
 761  *
 762  * @hsotg: The HCD state structure
 763  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 764  *         to a free host channel
 765  */
 766 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
 767 {
 768         struct dwc2_host_chan *chan;
 769         struct dwc2_hcd_urb *urb;
 770         struct dwc2_qtd *qtd;
 771         void *bufptr = NULL;
 772
 773         if (dbg_qh(qh))
 774                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 775
 776         if (list_empty(&qh->qtd_list)) {
 777                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 778                 return -ENOMEM;
 779         }
 780
 781         if (list_empty(&hsotg->free_hc_list)) {
 782                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 783                 return -ENOMEM;
 784         }
 785
 786         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 787                                 hc_list_entry);
 788
 789         /* Remove host channel from free list */
 790         list_del_init(&chan->hc_list_entry);
 791
 792         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 793         urb = qtd->urb;
 794         qh->channel = chan;
 795         qtd->in_process = 1;
 796
 797         /*
 798          * Use usb_pipedevice to determine device address. This address is
 799          * 0 before the SET_ADDRESS command and the correct address afterward.
 800          */
 801         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 802         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 803         chan->speed = qh->dev_speed;
 804         chan->max_packet = dwc2_max_packet(qh->maxp);
 805
 806         chan->xfer_started = 0;
 807         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 808         chan->error_state = (qtd->error_count > 0);
 809         chan->halt_on_queue = 0;
 810         chan->halt_pending = 0;
 811         chan->requests = 0;
 812
 813         /*
 814          * The following values may be modified in the transfer type section
 815          * below. The xfer_len value may be reduced when the transfer is
 816          * started to accommodate the max widths of the XferSize and PktCnt
 817          * fields in the HCTSIZn register.
 818          */
 819
 820         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 821         if (chan->ep_is_in)
 822                 chan->do_ping = 0;
 823         else
 824                 chan->do_ping = qh->ping_state;
 825
 826         chan->data_pid_start = qh->data_toggle;
 827         chan->multi_count = 1;
 828
 829         if (urb->actual_length > urb->length &&
 830                 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
 831                 urb->actual_length = urb->length;
 832
 833         if (hsotg->core_params->dma_enable > 0) {
 834                 chan->xfer_dma = urb->dma + urb->actual_length;
 835
 836                 /* For non-dword aligned case */
 837                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 838                     (chan->xfer_dma & 0x3))
 839                         bufptr = (u8 *)urb->buf + urb->actual_length;
 840         } else {
 841                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 842         }
 843
 844         chan->xfer_len = urb->length - urb->actual_length;
 845         chan->xfer_count = 0;
 846
 847         /* Set the split attributes if required */
 848         if (qh->do_split)
 849                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 850         else
 851                 chan->do_split = 0;
 852
 853         /* Set the transfer attributes */
 854         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 855
 856         /* Non DWORD-aligned buffer case */
 857         if (bufptr) {
 858                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 859                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
 860                         dev_err(hsotg->dev,
 861                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 862                                 __func__);
 863                         /* Add channel back to free list */
 864                         chan->align_buf = 0;
 865                         chan->multi_count = 0;
 866                         list_add_tail(&chan->hc_list_entry,
 867                                       &hsotg->free_hc_list);
 868                         qtd->in_process = 0;
 869                         qh->channel = NULL;
 870                         return -ENOMEM;
 871                 }
 872         } else {
 873                 chan->align_buf = 0;
 874         }
 875
 876         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 877             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 878                 /*
 879                  * This value may be modified when the transfer is started
 880                  * to reflect the actual transfer length
 881                  */
 882                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 883
 884         if (hsotg->core_params->dma_desc_enable > 0)
 885                 chan->desc_list_addr = qh->desc_list_dma;
 886
 887         dwc2_hc_init(hsotg, chan);
 888         chan->qh = qh;
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 895  * schedule and assigns them to available host channels. Called from the HCD
 896  * interrupt handler functions.
 897  *
 898  * @hsotg: The HCD state structure
 899  *
 900  * Return: The types of new transactions that were assigned to host channels
 901  */
 902 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 903                 struct dwc2_hsotg *hsotg)
 904 {
 905         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 906         struct list_head *qh_ptr;
 907         struct dwc2_qh *qh;
 908         int num_channels;
 909
 910 #ifdef DWC2_DEBUG_SOF
 911         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 912 #endif
 913
 914         /* Process entries in the periodic ready list */
 915         qh_ptr = hsotg->periodic_sched_ready.next;
 916         while (qh_ptr != &hsotg->periodic_sched_ready) {
 917                 if (list_empty(&hsotg->free_hc_list))
 918                         break;
 919                 if (hsotg->core_params->uframe_sched > 0) {
 920                         if (hsotg->available_host_channels <= 1)
 921                                 break;
 922                         hsotg->available_host_channels--;
 923                 }
 924                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 925                 if (dwc2_assign_and_init_hc(hsotg, qh))
 926                         break;
 927
 928                 /*
 929                  * Move the QH from the periodic ready schedule to the
 930                  * periodic assigned schedule
 931                  */
 932                 qh_ptr = qh_ptr->next;
 933                 list_move(&qh->qh_list_entry, &hsotg->periodic_sched_assigned);
 934                 ret_val = DWC2_TRANSACTION_PERIODIC;
 935         }
 936
 937         /*
 938          * Process entries in the inactive portion of the non-periodic
 939          * schedule. Some free host channels may not be used if they are
 940          * reserved for periodic transfers.
 941          */
 942         num_channels = hsotg->core_params->host_channels;
 943         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 944         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 945                 if (hsotg->core_params->uframe_sched <= 0 &&
 946                     hsotg->non_periodic_channels >= num_channels -
 947                                                 hsotg->periodic_channels)
 948                         break;
 949                 if (list_empty(&hsotg->free_hc_list))
 950                         break;
 951                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 952                 if (hsotg->core_params->uframe_sched > 0) {
 953                         if (hsotg->available_host_channels < 1)
 954                                 break;
 955                         hsotg->available_host_channels--;
 956                 }
 957
 958                 if (dwc2_assign_and_init_hc(hsotg, qh))
 959                         break;
 960
 961                 /*
 962                  * Move the QH from the non-periodic inactive schedule to the
 963                  * non-periodic active schedule
 964                  */
 965                 qh_ptr = qh_ptr->next;
 966                 list_move(&qh->qh_list_entry,
 967                           &hsotg->non_periodic_sched_active);
 968
 969                 if (ret_val == DWC2_TRANSACTION_NONE)
 970                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 971                 else
 972                         ret_val = DWC2_TRANSACTION_ALL;
 973
 974                 if (hsotg->core_params->uframe_sched <= 0)
 975                         hsotg->non_periodic_channels++;
 976         }
 977
 978         return ret_val;
 979 }
 980
 981 /**
 982  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 983  * a host channel associated with either a periodic or non-periodic transfer
 984  *
 985  * @hsotg: The HCD state structure
 986  * @chan:  Host channel descriptor associated with either a periodic or
 987  *         non-periodic transfer
 988  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 989  *                     for periodic transfers or the non-periodic Tx FIFO
 990  *                     for non-periodic transfers
 991  *
 992  * Return: 1 if a request is queued and more requests may be needed to
 993  * complete the transfer, 0 if no more requests are required for this
 994  * transfer, -1 if there is insufficient space in the Tx FIFO
 995  *
 996  * This function assumes that there is space available in the appropriate
 997  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 998  * it checks whether space is available in the appropriate Tx FIFO.
 999  *
1000  * Must be called with interrupt disabled and spinlock held
1001  */
1002 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1003                                   struct dwc2_host_chan *chan,
1004                                   u16 fifo_dwords_avail)
1005 {
1006         int retval = 0;
1007
1008         if (hsotg->core_params->dma_enable > 0) {
1009                 if (hsotg->core_params->dma_desc_enable > 0) {
1010                         if (!chan->xfer_started ||
1011                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1012                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1013                                 chan->qh->ping_state = 0;
1014                         }
1015                 } else if (!chan->xfer_started) {
1016                         dwc2_hc_start_transfer(hsotg, chan);
1017                         chan->qh->ping_state = 0;
1018                 }
1019         } else if (chan->halt_pending) {
1020                 /* Don't queue a request if the channel has been halted */
1021         } else if (chan->halt_on_queue) {
1022                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1023         } else if (chan->do_ping) {
1024                 if (!chan->xfer_started)
1025                         dwc2_hc_start_transfer(hsotg, chan);
1026         } else if (!chan->ep_is_in ||
1027                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
1028                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1029                         if (!chan->xfer_started) {
1030                                 dwc2_hc_start_transfer(hsotg, chan);
1031                                 retval = 1;
1032                         } else {
1033                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
1034                         }
1035                 } else {
1036                         retval = -1;
1037                 }
1038         } else {
1039                 if (!chan->xfer_started) {
1040                         dwc2_hc_start_transfer(hsotg, chan);
1041                         retval = 1;
1042                 } else {
1043                         retval = dwc2_hc_continue_transfer(hsotg, chan);
1044                 }
1045         }
1046
1047         return retval;
1048 }
1049
1050 /*
1051  * Processes periodic channels for the next frame and queues transactions for
1052  * these channels to the DWC_otg controller. After queueing transactions, the
1053  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1054  * to queue as Periodic Tx FIFO or request queue space becomes available.
1055  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1056  *
1057  * Must be called with interrupt disabled and spinlock held
1058  */
1059 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1060 {
1061         struct list_head *qh_ptr;
1062         struct dwc2_qh *qh;
1063         u32 tx_status;
1064         u32 fspcavail;
1065         u32 gintmsk;
1066         int status;
1067         int no_queue_space = 0;
1068         int no_fifo_space = 0;
1069         u32 qspcavail;
1070
1071         if (dbg_perio())
1072                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1073
1074         tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1075         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1076                     TXSTS_QSPCAVAIL_SHIFT;
1077         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1078                     TXSTS_FSPCAVAIL_SHIFT;
1079
1080         if (dbg_perio()) {
1081                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1082                          qspcavail);
1083                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1084                          fspcavail);
1085         }
1086
1087         qh_ptr = hsotg->periodic_sched_assigned.next;
1088         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1089                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1090                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1091                             TXSTS_QSPCAVAIL_SHIFT;
1092                 if (qspcavail == 0) {
1093                         no_queue_space = 1;
1094                         break;
1095                 }
1096
1097                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1098                 if (!qh->channel) {
1099                         qh_ptr = qh_ptr->next;
1100                         continue;
1101                 }
1102
1103                 /* Make sure EP's TT buffer is clean before queueing qtds */
1104                 if (qh->tt_buffer_dirty) {
1105                         qh_ptr = qh_ptr->next;
1106                         continue;
1107                 }
1108
1109                 /*
1110                  * Set a flag if we're queuing high-bandwidth in slave mode.
1111                  * The flag prevents any halts to get into the request queue in
1112                  * the middle of multiple high-bandwidth packets getting queued.
1113                  */
1114                 if (hsotg->core_params->dma_enable <= 0 &&
1115                                 qh->channel->multi_count > 1)
1116                         hsotg->queuing_high_bandwidth = 1;
1117
1118                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1119                             TXSTS_FSPCAVAIL_SHIFT;
1120                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1121                 if (status < 0) {
1122                         no_fifo_space = 1;
1123                         break;
1124                 }
1125
1126                 /*
1127                  * In Slave mode, stay on the current transfer until there is
1128                  * nothing more to do or the high-bandwidth request count is
1129                  * reached. In DMA mode, only need to queue one request. The
1130                  * controller automatically handles multiple packets for
1131                  * high-bandwidth transfers.
1132                  */
1133                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1134                     qh->channel->requests == qh->channel->multi_count) {
1135                         qh_ptr = qh_ptr->next;
1136                         /*
1137                          * Move the QH from the periodic assigned schedule to
1138                          * the periodic queued schedule
1139                          */
1140                         list_move(&qh->qh_list_entry,
1141                                   &hsotg->periodic_sched_queued);
1142
1143                         /* done queuing high bandwidth */
1144                         hsotg->queuing_high_bandwidth = 0;
1145                 }
1146         }
1147
1148         if (hsotg->core_params->dma_enable <= 0) {
1149                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1150                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1151                             TXSTS_QSPCAVAIL_SHIFT;
1152                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1153                             TXSTS_FSPCAVAIL_SHIFT;
1154                 if (dbg_perio()) {
1155                         dev_vdbg(hsotg->dev,
1156                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1157                                  qspcavail);
1158                         dev_vdbg(hsotg->dev,
1159                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1160                                  fspcavail);
1161                 }
1162
1163                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1164                     no_queue_space || no_fifo_space) {
1165                         /*
1166                          * May need to queue more transactions as the request
1167                          * queue or Tx FIFO empties. Enable the periodic Tx
1168                          * FIFO empty interrupt. (Always use the half-empty
1169                          * level to ensure that new requests are loaded as
1170                          * soon as possible.)
1171                          */
1172                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1173                         gintmsk |= GINTSTS_PTXFEMP;
1174                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1175                 } else {
1176                         /*
1177                          * Disable the Tx FIFO empty interrupt since there are
1178                          * no more transactions that need to be queued right
1179                          * now. This function is called from interrupt
1180                          * handlers to queue more transactions as transfer
1181                          * states change.
1182                          */
1183                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1184                         gintmsk &= ~GINTSTS_PTXFEMP;
1185                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1186                 }
1187         }
1188 }
1189
1190 /*
1191  * Processes active non-periodic channels and queues transactions for these
1192  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1193  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1194  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1195  * FIFO Empty interrupt is disabled.
1196  *
1197  * Must be called with interrupt disabled and spinlock held
1198  */
1199 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1200 {
1201         struct list_head *orig_qh_ptr;
1202         struct dwc2_qh *qh;
1203         u32 tx_status;
1204         u32 qspcavail;
1205         u32 fspcavail;
1206         u32 gintmsk;
1207         int status;
1208         int no_queue_space = 0;
1209         int no_fifo_space = 0;
1210         int more_to_do = 0;
1211
1212         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1213
1214         tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1215         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1216                     TXSTS_QSPCAVAIL_SHIFT;
1217         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1218                     TXSTS_FSPCAVAIL_SHIFT;
1219         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1220                  qspcavail);
1221         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1222                  fspcavail);
1223
1224         /*
1225          * Keep track of the starting point. Skip over the start-of-list
1226          * entry.
1227          */
1228         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1229                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1230         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1231
1232         /*
1233          * Process once through the active list or until no more space is
1234          * available in the request queue or the Tx FIFO
1235          */
1236         do {
1237                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1238                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1239                             TXSTS_QSPCAVAIL_SHIFT;
1240                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1241                         no_queue_space = 1;
1242                         break;
1243                 }
1244
1245                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1246                                 qh_list_entry);
1247                 if (!qh->channel)
1248                         goto next;
1249
1250                 /* Make sure EP's TT buffer is clean before queueing qtds */
1251                 if (qh->tt_buffer_dirty)
1252                         goto next;
1253
1254                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1255                             TXSTS_FSPCAVAIL_SHIFT;
1256                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1257
1258                 if (status > 0) {
1259                         more_to_do = 1;
1260                 } else if (status < 0) {
1261                         no_fifo_space = 1;
1262                         break;
1263                 }
1264 next:
1265                 /* Advance to next QH, skipping start-of-list entry */
1266                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1267                 if (hsotg->non_periodic_qh_ptr ==
1268                                 &hsotg->non_periodic_sched_active)
1269                         hsotg->non_periodic_qh_ptr =
1270                                         hsotg->non_periodic_qh_ptr->next;
1271         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1272
1273         if (hsotg->core_params->dma_enable <= 0) {
1274                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1275                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1276                             TXSTS_QSPCAVAIL_SHIFT;
1277                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1278                             TXSTS_FSPCAVAIL_SHIFT;
1279                 dev_vdbg(hsotg->dev,
1280                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1281                          qspcavail);
1282                 dev_vdbg(hsotg->dev,
1283                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1284                          fspcavail);
1285
1286                 if (more_to_do || no_queue_space || no_fifo_space) {
1287                         /*
1288                          * May need to queue more transactions as the request
1289                          * queue or Tx FIFO empties. Enable the non-periodic
1290                          * Tx FIFO empty interrupt. (Always use the half-empty
1291                          * level to ensure that new requests are loaded as
1292                          * soon as possible.)
1293                          */
1294                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1295                         gintmsk |= GINTSTS_NPTXFEMP;
1296                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1297                 } else {
1298                         /*
1299                          * Disable the Tx FIFO empty interrupt since there are
1300                          * no more transactions that need to be queued right
1301                          * now. This function is called from interrupt
1302                          * handlers to queue more transactions as transfer
1303                          * states change.
1304                          */
1305                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1306                         gintmsk &= ~GINTSTS_NPTXFEMP;
1307                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1308                 }
1309         }
1310 }
1311
1312 /**
1313  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1314  * and queues transactions for these channels to the DWC_otg controller. Called
1315  * from the HCD interrupt handler functions.
1316  *
1317  * @hsotg:   The HCD state structure
1318  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1319  *           or both)
1320  *
1321  * Must be called with interrupt disabled and spinlock held
1322  */
1323 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1324                                  enum dwc2_transaction_type tr_type)
1325 {
1326 #ifdef DWC2_DEBUG_SOF
1327         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1328 #endif
1329         /* Process host channels associated with periodic transfers */
1330         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1331              tr_type == DWC2_TRANSACTION_ALL) &&
1332             !list_empty(&hsotg->periodic_sched_assigned))
1333                 dwc2_process_periodic_channels(hsotg);
1334
1335         /* Process host channels associated with non-periodic transfers */
1336         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1337             tr_type == DWC2_TRANSACTION_ALL) {
1338                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1339                         dwc2_process_non_periodic_channels(hsotg);
1340                 } else {
1341                         /*
1342                          * Ensure NP Tx FIFO empty interrupt is disabled when
1343                          * there are no non-periodic transfers to process
1344                          */
1345                         u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1346
1347                         gintmsk &= ~GINTSTS_NPTXFEMP;
1348                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1349                 }
1350         }
1351 }
1352
1353 static void dwc2_conn_id_status_change(struct work_struct *work)
1354 {
1355         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1356                                                 wf_otg);
1357         u32 count = 0;
1358         u32 gotgctl;
1359         unsigned long flags;
1360
1361         dev_dbg(hsotg->dev, "%s()\n", __func__);
1362
1363         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1364         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1365         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1366                 !!(gotgctl & GOTGCTL_CONID_B));
1367
1368         /* B-Device connector (Device Mode) */
1369         if (gotgctl & GOTGCTL_CONID_B) {
1370                 /* Wait for switch to device mode */
1371                 dev_dbg(hsotg->dev, "connId B\n");
1372                 while (!dwc2_is_device_mode(hsotg)) {
1373                         dev_info(hsotg->dev,
1374                                  "Waiting for Peripheral Mode, Mode=%s\n",
1375                                  dwc2_is_host_mode(hsotg) ? "Host" :
1376                                  "Peripheral");
1377                         usleep_range(20000, 40000);
1378                         if (++count > 250)
1379                                 break;
1380                 }
1381                 if (count > 250)
1382                         dev_err(hsotg->dev,
1383                                 "Connection id status change timed out\n");
1384                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1385                 dwc2_core_init(hsotg, false);
1386                 dwc2_enable_global_interrupts(hsotg);
1387                 spin_lock_irqsave(&hsotg->lock, flags);
1388                 dwc2_hsotg_core_init_disconnected(hsotg, false);
1389                 spin_unlock_irqrestore(&hsotg->lock, flags);
1390                 dwc2_hsotg_core_connect(hsotg);
1391         } else {
1392                 /* A-Device connector (Host Mode) */
1393                 dev_dbg(hsotg->dev, "connId A\n");
1394                 while (!dwc2_is_host_mode(hsotg)) {
1395                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1396                                  dwc2_is_host_mode(hsotg) ?
1397                                  "Host" : "Peripheral");
1398                         usleep_range(20000, 40000);
1399                         if (++count > 250)
1400                                 break;
1401                 }
1402                 if (count > 250)
1403                         dev_err(hsotg->dev,
1404                                 "Connection id status change timed out\n");
1405                 hsotg->op_state = OTG_STATE_A_HOST;
1406
1407                 /* Initialize the Core for Host mode */
1408                 dwc2_core_init(hsotg, false);
1409                 dwc2_enable_global_interrupts(hsotg);
1410                 dwc2_hcd_start(hsotg);
1411         }
1412 }
1413
1414 static void dwc2_wakeup_detected(unsigned long data)
1415 {
1416         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1417         u32 hprt0;
1418
1419         dev_dbg(hsotg->dev, "%s()\n", __func__);
1420
1421         /*
1422          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1423          * so that OPT tests pass with all PHYs.)
1424          */
1425         hprt0 = dwc2_read_hprt0(hsotg);
1426         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1427         hprt0 &= ~HPRT0_RES;
1428         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1429         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1430                 dwc2_readl(hsotg->regs + HPRT0));
1431
1432         dwc2_hcd_rem_wakeup(hsotg);
1433         hsotg->bus_suspended = 0;
1434
1435         /* Change to L0 state */
1436         hsotg->lx_state = DWC2_L0;
1437 }
1438
1439 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1440 {
1441         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1442
1443         return hcd->self.b_hnp_enable;
1444 }
1445
1446 /* Must NOT be called with interrupt disabled or spinlock held */
1447 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1448 {
1449         unsigned long flags;
1450         u32 hprt0;
1451         u32 pcgctl;
1452         u32 gotgctl;
1453
1454         dev_dbg(hsotg->dev, "%s()\n", __func__);
1455
1456         spin_lock_irqsave(&hsotg->lock, flags);
1457
1458         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1459                 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1460                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1461                 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1462                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1463         }
1464
1465         hprt0 = dwc2_read_hprt0(hsotg);
1466         hprt0 |= HPRT0_SUSP;
1467         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1468
1469         hsotg->bus_suspended = 1;
1470
1471         /*
1472          * If hibernation is supported, Phy clock will be suspended
1473          * after registers are backuped.
1474          */
1475         if (!hsotg->core_params->hibernation) {
1476                 /* Suspend the Phy Clock */
1477                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1478                 pcgctl |= PCGCTL_STOPPCLK;
1479                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1480                 udelay(10);
1481         }
1482
1483         /* For HNP the bus must be suspended for at least 200ms */
1484         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1485                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1486                 pcgctl &= ~PCGCTL_STOPPCLK;
1487                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1488
1489                 spin_unlock_irqrestore(&hsotg->lock, flags);
1490
1491                 usleep_range(200000, 250000);
1492         } else {
1493                 spin_unlock_irqrestore(&hsotg->lock, flags);
1494         }
1495 }
1496
1497 /* Must NOT be called with interrupt disabled or spinlock held */
1498 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1499 {
1500         unsigned long flags;
1501         u32 hprt0;
1502         u32 pcgctl;
1503
1504         spin_lock_irqsave(&hsotg->lock, flags);
1505
1506         /*
1507          * If hibernation is supported, Phy clock is already resumed
1508          * after registers restore.
1509          */
1510         if (!hsotg->core_params->hibernation) {
1511                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1512                 pcgctl &= ~PCGCTL_STOPPCLK;
1513                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1514                 spin_unlock_irqrestore(&hsotg->lock, flags);
1515                 usleep_range(20000, 40000);
1516                 spin_lock_irqsave(&hsotg->lock, flags);
1517         }
1518
1519         hprt0 = dwc2_read_hprt0(hsotg);
1520         hprt0 |= HPRT0_RES;
1521         hprt0 &= ~HPRT0_SUSP;
1522         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1523         spin_unlock_irqrestore(&hsotg->lock, flags);
1524
1525         msleep(USB_RESUME_TIMEOUT);
1526
1527         spin_lock_irqsave(&hsotg->lock, flags);
1528         hprt0 = dwc2_read_hprt0(hsotg);
1529         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1530         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1531         hsotg->bus_suspended = 0;
1532         spin_unlock_irqrestore(&hsotg->lock, flags);
1533 }
1534
1535 /* Handles hub class-specific requests */
1536 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1537                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1538 {
1539         struct usb_hub_descriptor *hub_desc;
1540         int retval = 0;
1541         u32 hprt0;
1542         u32 port_status;
1543         u32 speed;
1544         u32 pcgctl;
1545
1546         switch (typereq) {
1547         case ClearHubFeature:
1548                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1549
1550                 switch (wvalue) {
1551                 case C_HUB_LOCAL_POWER:
1552                 case C_HUB_OVER_CURRENT:
1553                         /* Nothing required here */
1554                         break;
1555
1556                 default:
1557                         retval = -EINVAL;
1558                         dev_err(hsotg->dev,
1559                                 "ClearHubFeature request %1xh unknown\n",
1560                                 wvalue);
1561                 }
1562                 break;
1563
1564         case ClearPortFeature:
1565                 if (wvalue != USB_PORT_FEAT_L1)
1566                         if (!windex || windex > 1)
1567                                 goto error;
1568                 switch (wvalue) {
1569                 case USB_PORT_FEAT_ENABLE:
1570                         dev_dbg(hsotg->dev,
1571                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1572                         hprt0 = dwc2_read_hprt0(hsotg);
1573                         hprt0 |= HPRT0_ENA;
1574                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1575                         break;
1576
1577                 case USB_PORT_FEAT_SUSPEND:
1578                         dev_dbg(hsotg->dev,
1579                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1580
1581                         if (hsotg->bus_suspended)
1582                                 dwc2_port_resume(hsotg);
1583                         break;
1584
1585                 case USB_PORT_FEAT_POWER:
1586                         dev_dbg(hsotg->dev,
1587                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1588                         hprt0 = dwc2_read_hprt0(hsotg);
1589                         hprt0 &= ~HPRT0_PWR;
1590                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1591                         break;
1592
1593                 case USB_PORT_FEAT_INDICATOR:
1594                         dev_dbg(hsotg->dev,
1595                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1596                         /* Port indicator not supported */
1597                         break;
1598
1599                 case USB_PORT_FEAT_C_CONNECTION:
1600                         /*
1601                          * Clears driver's internal Connect Status Change flag
1602                          */
1603                         dev_dbg(hsotg->dev,
1604                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1605                         hsotg->flags.b.port_connect_status_change = 0;
1606                         break;
1607
1608                 case USB_PORT_FEAT_C_RESET:
1609                         /* Clears driver's internal Port Reset Change flag */
1610                         dev_dbg(hsotg->dev,
1611                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1612                         hsotg->flags.b.port_reset_change = 0;
1613                         break;
1614
1615                 case USB_PORT_FEAT_C_ENABLE:
1616                         /*
1617                          * Clears the driver's internal Port Enable/Disable
1618                          * Change flag
1619                          */
1620                         dev_dbg(hsotg->dev,
1621                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1622                         hsotg->flags.b.port_enable_change = 0;
1623                         break;
1624
1625                 case USB_PORT_FEAT_C_SUSPEND:
1626                         /*
1627                          * Clears the driver's internal Port Suspend Change
1628                          * flag, which is set when resume signaling on the host
1629                          * port is complete
1630                          */
1631                         dev_dbg(hsotg->dev,
1632                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1633                         hsotg->flags.b.port_suspend_change = 0;
1634                         break;
1635
1636                 case USB_PORT_FEAT_C_PORT_L1:
1637                         dev_dbg(hsotg->dev,
1638                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1639                         hsotg->flags.b.port_l1_change = 0;
1640                         break;
1641
1642                 case USB_PORT_FEAT_C_OVER_CURRENT:
1643                         dev_dbg(hsotg->dev,
1644                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1645                         hsotg->flags.b.port_over_current_change = 0;
1646                         break;
1647
1648                 default:
1649                         retval = -EINVAL;
1650                         dev_err(hsotg->dev,
1651                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1652                                 wvalue);
1653                 }
1654                 break;
1655
1656         case GetHubDescriptor:
1657                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1658                 hub_desc = (struct usb_hub_descriptor *)buf;
1659                 hub_desc->bDescLength = 9;
1660                 hub_desc->bDescriptorType = USB_DT_HUB;
1661                 hub_desc->bNbrPorts = 1;
1662                 hub_desc->wHubCharacteristics =
1663                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1664                                     HUB_CHAR_INDV_PORT_OCPM);
1665                 hub_desc->bPwrOn2PwrGood = 1;
1666                 hub_desc->bHubContrCurrent = 0;
1667                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1668                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1669                 break;
1670
1671         case GetHubStatus:
1672                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1673                 memset(buf, 0, 4);
1674                 break;
1675
1676         case GetPortStatus:
1677                 dev_vdbg(hsotg->dev,
1678                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1679                          hsotg->flags.d32);
1680                 if (!windex || windex > 1)
1681                         goto error;
1682
1683                 port_status = 0;
1684                 if (hsotg->flags.b.port_connect_status_change)
1685                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1686                 if (hsotg->flags.b.port_enable_change)
1687                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1688                 if (hsotg->flags.b.port_suspend_change)
1689                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1690                 if (hsotg->flags.b.port_l1_change)
1691                         port_status |= USB_PORT_STAT_C_L1 << 16;
1692                 if (hsotg->flags.b.port_reset_change)
1693                         port_status |= USB_PORT_STAT_C_RESET << 16;
1694                 if (hsotg->flags.b.port_over_current_change) {
1695                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1696                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1697                 }
1698
1699                 if (!hsotg->flags.b.port_connect_status) {
1700                         /*
1701                          * The port is disconnected, which means the core is
1702                          * either in device mode or it soon will be. Just
1703                          * return 0's for the remainder of the port status
1704                          * since the port register can't be read if the core
1705                          * is in device mode.
1706                          */
1707                         *(__le32 *)buf = cpu_to_le32(port_status);
1708                         break;
1709                 }
1710
1711                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1712                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1713
1714                 if (hprt0 & HPRT0_CONNSTS)
1715                         port_status |= USB_PORT_STAT_CONNECTION;
1716                 if (hprt0 & HPRT0_ENA)
1717                         port_status |= USB_PORT_STAT_ENABLE;
1718                 if (hprt0 & HPRT0_SUSP)
1719                         port_status |= USB_PORT_STAT_SUSPEND;
1720                 if (hprt0 & HPRT0_OVRCURRACT)
1721                         port_status |= USB_PORT_STAT_OVERCURRENT;
1722                 if (hprt0 & HPRT0_RST)
1723                         port_status |= USB_PORT_STAT_RESET;
1724                 if (hprt0 & HPRT0_PWR)
1725                         port_status |= USB_PORT_STAT_POWER;
1726
1727                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1728                 if (speed == HPRT0_SPD_HIGH_SPEED)
1729                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1730                 else if (speed == HPRT0_SPD_LOW_SPEED)
1731                         port_status |= USB_PORT_STAT_LOW_SPEED;
1732
1733                 if (hprt0 & HPRT0_TSTCTL_MASK)
1734                         port_status |= USB_PORT_STAT_TEST;
1735                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1736
1737                 if (hsotg->core_params->dma_desc_fs_enable) {
1738                         /*
1739                          * Enable descriptor DMA only if a full speed
1740                          * device is connected.
1741                          */
1742                         if (hsotg->new_connection &&
1743                             ((port_status &
1744                               (USB_PORT_STAT_CONNECTION |
1745                                USB_PORT_STAT_HIGH_SPEED |
1746                                USB_PORT_STAT_LOW_SPEED)) ==
1747                                USB_PORT_STAT_CONNECTION)) {
1748                                 u32 hcfg;
1749
1750                                 dev_info(hsotg->dev, "Enabling descriptor DMA mode\n");
1751                                 hsotg->core_params->dma_desc_enable = 1;
1752                                 hcfg = dwc2_readl(hsotg->regs + HCFG);
1753                                 hcfg |= HCFG_DESCDMA;
1754                                 dwc2_writel(hcfg, hsotg->regs + HCFG);
1755                                 hsotg->new_connection = false;
1756                         }
1757                 }
1758
1759                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1760                 *(__le32 *)buf = cpu_to_le32(port_status);
1761                 break;
1762
1763         case SetHubFeature:
1764                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1765                 /* No HUB features supported */
1766                 break;
1767
1768         case SetPortFeature:
1769                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1770                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1771                         goto error;
1772
1773                 if (!hsotg->flags.b.port_connect_status) {
1774                         /*
1775                          * The port is disconnected, which means the core is
1776                          * either in device mode or it soon will be. Just
1777                          * return without doing anything since the port
1778                          * register can't be written if the core is in device
1779                          * mode.
1780                          */
1781                         break;
1782                 }
1783
1784                 switch (wvalue) {
1785                 case USB_PORT_FEAT_SUSPEND:
1786                         dev_dbg(hsotg->dev,
1787                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1788                         if (windex != hsotg->otg_port)
1789                                 goto error;
1790                         dwc2_port_suspend(hsotg, windex);
1791                         break;
1792
1793                 case USB_PORT_FEAT_POWER:
1794                         dev_dbg(hsotg->dev,
1795                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1796                         hprt0 = dwc2_read_hprt0(hsotg);
1797                         hprt0 |= HPRT0_PWR;
1798                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1799                         break;
1800
1801                 case USB_PORT_FEAT_RESET:
1802                         hprt0 = dwc2_read_hprt0(hsotg);
1803                         dev_dbg(hsotg->dev,
1804                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1805                         pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1806                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1807                         dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1808                         /* ??? Original driver does this */
1809                         dwc2_writel(0, hsotg->regs + PCGCTL);
1810
1811                         hprt0 = dwc2_read_hprt0(hsotg);
1812                         /* Clear suspend bit if resetting from suspend state */
1813                         hprt0 &= ~HPRT0_SUSP;
1814
1815                         /*
1816                          * When B-Host the Port reset bit is set in the Start
1817                          * HCD Callback function, so that the reset is started
1818                          * within 1ms of the HNP success interrupt
1819                          */
1820                         if (!dwc2_hcd_is_b_host(hsotg)) {
1821                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1822                                 dev_dbg(hsotg->dev,
1823                                         "In host mode, hprt0=%08x\n", hprt0);
1824                                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1825                         }
1826
1827                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1828                         usleep_range(50000, 70000);
1829                         hprt0 &= ~HPRT0_RST;
1830                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1831                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1832                         break;
1833
1834                 case USB_PORT_FEAT_INDICATOR:
1835                         dev_dbg(hsotg->dev,
1836                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1837                         /* Not supported */
1838                         break;
1839
1840                 case USB_PORT_FEAT_TEST:
1841                         hprt0 = dwc2_read_hprt0(hsotg);
1842                         dev_dbg(hsotg->dev,
1843                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1844                         hprt0 &= ~HPRT0_TSTCTL_MASK;
1845                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1846                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1847                         break;
1848
1849                 default:
1850                         retval = -EINVAL;
1851                         dev_err(hsotg->dev,
1852                                 "SetPortFeature %1xh unknown or unsupported\n",
1853                                 wvalue);
1854                         break;
1855                 }
1856                 break;
1857
1858         default:
1859 error:
1860                 retval = -EINVAL;
1861                 dev_dbg(hsotg->dev,
1862                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1863                         typereq, windex, wvalue);
1864                 break;
1865         }
1866
1867         return retval;
1868 }
1869
1870 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1871 {
1872         int retval;
1873
1874         if (port != 1)
1875                 return -EINVAL;
1876
1877         retval = (hsotg->flags.b.port_connect_status_change ||
1878                   hsotg->flags.b.port_reset_change ||
1879                   hsotg->flags.b.port_enable_change ||
1880                   hsotg->flags.b.port_suspend_change ||
1881                   hsotg->flags.b.port_over_current_change);
1882
1883         if (retval) {
1884                 dev_dbg(hsotg->dev,
1885                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1886                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1887                         hsotg->flags.b.port_connect_status_change);
1888                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1889                         hsotg->flags.b.port_reset_change);
1890                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1891                         hsotg->flags.b.port_enable_change);
1892                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1893                         hsotg->flags.b.port_suspend_change);
1894                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1895                         hsotg->flags.b.port_over_current_change);
1896         }
1897
1898         return retval;
1899 }
1900
1901 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1902 {
1903         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
1904
1905 #ifdef DWC2_DEBUG_SOF
1906         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1907                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1908 #endif
1909         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1910 }
1911
1912 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1913 {
1914         return hsotg->op_state == OTG_STATE_B_HOST;
1915 }
1916
1917 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1918                                                int iso_desc_count,
1919                                                gfp_t mem_flags)
1920 {
1921         struct dwc2_hcd_urb *urb;
1922         u32 size = sizeof(*urb) + iso_desc_count *
1923                    sizeof(struct dwc2_hcd_iso_packet_desc);
1924
1925         urb = kzalloc(size, mem_flags);
1926         if (urb)
1927                 urb->packet_count = iso_desc_count;
1928         return urb;
1929 }
1930
1931 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1932                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1933                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1934 {
1935         if (dbg_perio() ||
1936             ep_type == USB_ENDPOINT_XFER_BULK ||
1937             ep_type == USB_ENDPOINT_XFER_CONTROL)
1938                 dev_vdbg(hsotg->dev,
1939                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1940                          dev_addr, ep_num, ep_dir, ep_type, mps);
1941         urb->pipe_info.dev_addr = dev_addr;
1942         urb->pipe_info.ep_num = ep_num;
1943         urb->pipe_info.pipe_type = ep_type;
1944         urb->pipe_info.pipe_dir = ep_dir;
1945         urb->pipe_info.mps = mps;
1946 }
1947
1948 /*
1949  * NOTE: This function will be removed once the peripheral controller code
1950  * is integrated and the driver is stable
1951  */
1952 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1953 {
1954 #ifdef DEBUG
1955         struct dwc2_host_chan *chan;
1956         struct dwc2_hcd_urb *urb;
1957         struct dwc2_qtd *qtd;
1958         int num_channels;
1959         u32 np_tx_status;
1960         u32 p_tx_status;
1961         int i;
1962
1963         num_channels = hsotg->core_params->host_channels;
1964         dev_dbg(hsotg->dev, "\n");
1965         dev_dbg(hsotg->dev,
1966                 "************************************************************\n");
1967         dev_dbg(hsotg->dev, "HCD State:\n");
1968         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1969
1970         for (i = 0; i < num_channels; i++) {
1971                 chan = hsotg->hc_ptr_array[i];
1972                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1973                 dev_dbg(hsotg->dev,
1974                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1975                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1976                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1977                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1978                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1979                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1980                         chan->data_pid_start);
1981                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1982                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1983                         chan->xfer_started);
1984                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1985                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1986                         (unsigned long)chan->xfer_dma);
1987                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1988                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1989                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1990                         chan->halt_on_queue);
1991                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1992                         chan->halt_pending);
1993                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1994                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1995                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1996                         chan->complete_split);
1997                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1998                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1999                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
2000                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
2001                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
2002
2003                 if (chan->xfer_started) {
2004                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
2005
2006                         hfnum = dwc2_readl(hsotg->regs + HFNUM);
2007                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
2008                         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
2009                         hcint = dwc2_readl(hsotg->regs + HCINT(i));
2010                         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
2011                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
2012                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
2013                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
2014                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
2015                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
2016                 }
2017
2018                 if (!(chan->xfer_started && chan->qh))
2019                         continue;
2020
2021                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
2022                         if (!qtd->in_process)
2023                                 break;
2024                         urb = qtd->urb;
2025                         dev_dbg(hsotg->dev, "    URB Info:\n");
2026                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
2027                                 qtd, urb);
2028                         if (urb) {
2029                                 dev_dbg(hsotg->dev,
2030                                         "      Dev: %d, EP: %d %s\n",
2031                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
2032                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
2033                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2034                                         "IN" : "OUT");
2035                                 dev_dbg(hsotg->dev,
2036                                         "      Max packet size: %d\n",
2037                                         dwc2_hcd_get_mps(&urb->pipe_info));
2038                                 dev_dbg(hsotg->dev,
2039                                         "      transfer_buffer: %p\n",
2040                                         urb->buf);
2041                                 dev_dbg(hsotg->dev,
2042                                         "      transfer_dma: %08lx\n",
2043                                         (unsigned long)urb->dma);
2044                                 dev_dbg(hsotg->dev,
2045                                         "      transfer_buffer_length: %d\n",
2046                                         urb->length);
2047                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
2048                                         urb->actual_length);
2049                         }
2050                 }
2051         }
2052
2053         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
2054                 hsotg->non_periodic_channels);
2055         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
2056                 hsotg->periodic_channels);
2057         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
2058         np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2059         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
2060                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2061         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
2062                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2063         p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2064         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
2065                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2066         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
2067                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2068         dwc2_hcd_dump_frrem(hsotg);
2069         dwc2_dump_global_registers(hsotg);
2070         dwc2_dump_host_registers(hsotg);
2071         dev_dbg(hsotg->dev,
2072                 "************************************************************\n");
2073         dev_dbg(hsotg->dev, "\n");
2074 #endif
2075 }
2076
2077 /*
2078  * NOTE: This function will be removed once the peripheral controller code
2079  * is integrated and the driver is stable
2080  */
2081 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2082 {
2083 #ifdef DWC2_DUMP_FRREM
2084         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2085         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2086                 hsotg->frrem_samples, hsotg->frrem_accum,
2087                 hsotg->frrem_samples > 0 ?
2088                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2089         dev_dbg(hsotg->dev, "\n");
2090         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2091         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2092                 hsotg->hfnum_7_samples,
2093                 hsotg->hfnum_7_frrem_accum,
2094                 hsotg->hfnum_7_samples > 0 ?
2095                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2096         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2097         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2098                 hsotg->hfnum_0_samples,
2099                 hsotg->hfnum_0_frrem_accum,
2100                 hsotg->hfnum_0_samples > 0 ?
2101                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2102         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2103         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2104                 hsotg->hfnum_other_samples,
2105                 hsotg->hfnum_other_frrem_accum,
2106                 hsotg->hfnum_other_samples > 0 ?
2107                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2108                 0);
2109         dev_dbg(hsotg->dev, "\n");
2110         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2111         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2112                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2113                 hsotg->hfnum_7_samples_a > 0 ?
2114                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2115         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2116         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2117                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2118                 hsotg->hfnum_0_samples_a > 0 ?
2119                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2120         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2121         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2122                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2123                 hsotg->hfnum_other_samples_a > 0 ?
2124                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2125                 : 0);
2126         dev_dbg(hsotg->dev, "\n");
2127         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2128         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2129                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2130                 hsotg->hfnum_7_samples_b > 0 ?
2131                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2132         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2133         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2134                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2135                 (hsotg->hfnum_0_samples_b > 0) ?
2136                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2137         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2138         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2139                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2140                 (hsotg->hfnum_other_samples_b > 0) ?
2141                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2142                 : 0);
2143 #endif
2144 }
2145
2146 struct wrapper_priv_data {
2147         struct dwc2_hsotg *hsotg;
2148 };
2149
2150 /* Gets the dwc2_hsotg from a usb_hcd */
2151 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2152 {
2153         struct wrapper_priv_data *p;
2154
2155         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2156         return p->hsotg;
2157 }
2158
2159 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2160
2161 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2162 {
2163         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2164
2165         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2166         _dwc2_hcd_start(hcd);
2167 }
2168
2169 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2170 {
2171         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2172
2173         hcd->self.is_b_host = 0;
2174 }
2175
2176 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2177                         int *hub_port)
2178 {
2179         struct urb *urb = context;
2180
2181         if (urb->dev->tt)
2182                 *hub_addr = urb->dev->tt->hub->devnum;
2183         else
2184                 *hub_addr = 0;
2185         *hub_port = urb->dev->ttport;
2186 }
2187
2188 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2189 {
2190         struct urb *urb = context;
2191
2192         return urb->dev->speed;
2193 }
2194
2195 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2196                                         struct urb *urb)
2197 {
2198         struct usb_bus *bus = hcd_to_bus(hcd);
2199
2200         if (urb->interval)
2201                 bus->bandwidth_allocated += bw / urb->interval;
2202         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2203                 bus->bandwidth_isoc_reqs++;
2204         else
2205                 bus->bandwidth_int_reqs++;
2206 }
2207
2208 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2209                                     struct urb *urb)
2210 {
2211         struct usb_bus *bus = hcd_to_bus(hcd);
2212
2213         if (urb->interval)
2214                 bus->bandwidth_allocated -= bw / urb->interval;
2215         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2216                 bus->bandwidth_isoc_reqs--;
2217         else
2218                 bus->bandwidth_int_reqs--;
2219 }
2220
2221 /*
2222  * Sets the final status of an URB and returns it to the upper layer. Any
2223  * required cleanup of the URB is performed.
2224  *
2225  * Must be called with interrupt disabled and spinlock held
2226  */
2227 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2228                         int status)
2229 {
2230         struct urb *urb;
2231         int i;
2232
2233         if (!qtd) {
2234                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2235                 return;
2236         }
2237
2238         if (!qtd->urb) {
2239                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2240                 return;
2241         }
2242
2243         urb = qtd->urb->priv;
2244         if (!urb) {
2245                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2246                 return;
2247         }
2248
2249         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2250
2251         if (dbg_urb(urb))
2252                 dev_vdbg(hsotg->dev,
2253                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2254                          __func__, urb, usb_pipedevice(urb->pipe),
2255                          usb_pipeendpoint(urb->pipe),
2256                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2257                          urb->actual_length);
2258
2259
2260         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2261                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2262                 for (i = 0; i < urb->number_of_packets; ++i) {
2263                         urb->iso_frame_desc[i].actual_length =
2264                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2265                                                 qtd->urb, i);
2266                         urb->iso_frame_desc[i].status =
2267                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2268                 }
2269         }
2270
2271         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2272                 for (i = 0; i < urb->number_of_packets; i++)
2273                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2274                                  i, urb->iso_frame_desc[i].status);
2275         }
2276
2277         urb->status = status;
2278         if (!status) {
2279                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2280                     urb->actual_length < urb->transfer_buffer_length)
2281                         urb->status = -EREMOTEIO;
2282         }
2283
2284         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2285             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2286                 struct usb_host_endpoint *ep = urb->ep;
2287
2288                 if (ep)
2289                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2290                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2291                                         urb);
2292         }
2293
2294         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2295         urb->hcpriv = NULL;
2296         kfree(qtd->urb);
2297         qtd->urb = NULL;
2298
2299         spin_unlock(&hsotg->lock);
2300         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2301         spin_lock(&hsotg->lock);
2302 }
2303
2304 /*
2305  * Work queue function for starting the HCD when A-Cable is connected
2306  */
2307 static void dwc2_hcd_start_func(struct work_struct *work)
2308 {
2309         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2310                                                 start_work.work);
2311
2312         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2313         dwc2_host_start(hsotg);
2314 }
2315
2316 /*
2317  * Reset work queue function
2318  */
2319 static void dwc2_hcd_reset_func(struct work_struct *work)
2320 {
2321         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2322                                                 reset_work.work);
2323         u32 hprt0;
2324
2325         dev_dbg(hsotg->dev, "USB RESET function called\n");
2326         hprt0 = dwc2_read_hprt0(hsotg);
2327         hprt0 &= ~HPRT0_RST;
2328         dwc2_writel(hprt0, hsotg->regs + HPRT0);
2329         hsotg->flags.b.port_reset_change = 1;
2330 }
2331
2332 /*
2333  * =========================================================================
2334  *  Linux HC Driver Functions
2335  * =========================================================================
2336  */
2337
2338 /*
2339  * Initializes the DWC_otg controller and its root hub and prepares it for host
2340  * mode operation. Activates the root port. Returns 0 on success and a negative
2341  * error code on failure.
2342  */
2343 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2344 {
2345         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2346         struct usb_bus *bus = hcd_to_bus(hcd);
2347         unsigned long flags;
2348
2349         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2350
2351         spin_lock_irqsave(&hsotg->lock, flags);
2352         hsotg->lx_state = DWC2_L0;
2353         hcd->state = HC_STATE_RUNNING;
2354         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2355
2356         if (dwc2_is_device_mode(hsotg)) {
2357                 spin_unlock_irqrestore(&hsotg->lock, flags);
2358                 return 0;       /* why 0 ?? */
2359         }
2360
2361         dwc2_hcd_reinit(hsotg);
2362
2363         /* Initialize and connect root hub if one is not already attached */
2364         if (bus->root_hub) {
2365                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2366                 /* Inform the HUB driver to resume */
2367                 usb_hcd_resume_root_hub(hcd);
2368         }
2369
2370         spin_unlock_irqrestore(&hsotg->lock, flags);
2371         return 0;
2372 }
2373
2374 /*
2375  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2376  * stopped.
2377  */
2378 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2379 {
2380         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2381         unsigned long flags;
2382
2383         /* Turn off all host-specific interrupts */
2384         dwc2_disable_host_interrupts(hsotg);
2385
2386         /* Wait for interrupt processing to finish */
2387         synchronize_irq(hcd->irq);
2388
2389         spin_lock_irqsave(&hsotg->lock, flags);
2390         /* Ensure hcd is disconnected */
2391         dwc2_hcd_disconnect(hsotg);
2392         dwc2_hcd_stop(hsotg);
2393         hsotg->lx_state = DWC2_L3;
2394         hcd->state = HC_STATE_HALT;
2395         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2396         spin_unlock_irqrestore(&hsotg->lock, flags);
2397
2398         usleep_range(1000, 3000);
2399 }
2400
2401 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2402 {
2403         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2404         unsigned long flags;
2405         int ret = 0;
2406         u32 hprt0;
2407
2408         spin_lock_irqsave(&hsotg->lock, flags);
2409
2410         if (hsotg->lx_state != DWC2_L0)
2411                 goto unlock;
2412
2413         if (!HCD_HW_ACCESSIBLE(hcd))
2414                 goto unlock;
2415
2416         if (!hsotg->core_params->hibernation)
2417                 goto skip_power_saving;
2418
2419         /*
2420          * Drive USB suspend and disable port Power
2421          * if usb bus is not suspended.
2422          */
2423         if (!hsotg->bus_suspended) {
2424                 hprt0 = dwc2_read_hprt0(hsotg);
2425                 hprt0 |= HPRT0_SUSP;
2426                 hprt0 &= ~HPRT0_PWR;
2427                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2428         }
2429
2430         /* Enter hibernation */
2431         ret = dwc2_enter_hibernation(hsotg);
2432         if (ret) {
2433                 if (ret != -ENOTSUPP)
2434                         dev_err(hsotg->dev,
2435                                 "enter hibernation failed\n");
2436                 goto skip_power_saving;
2437         }
2438
2439         /* Ask phy to be suspended */
2440         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2441                 spin_unlock_irqrestore(&hsotg->lock, flags);
2442                 usb_phy_set_suspend(hsotg->uphy, true);
2443                 spin_lock_irqsave(&hsotg->lock, flags);
2444         }
2445
2446         /* After entering hibernation, hardware is no more accessible */
2447         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2448
2449 skip_power_saving:
2450         hsotg->lx_state = DWC2_L2;
2451 unlock:
2452         spin_unlock_irqrestore(&hsotg->lock, flags);
2453
2454         return ret;
2455 }
2456
2457 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2458 {
2459         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2460         unsigned long flags;
2461         int ret = 0;
2462
2463         spin_lock_irqsave(&hsotg->lock, flags);
2464
2465         if (hsotg->lx_state != DWC2_L2)
2466                 goto unlock;
2467
2468         if (!hsotg->core_params->hibernation) {
2469                 hsotg->lx_state = DWC2_L0;
2470                 goto unlock;
2471         }
2472
2473         /*
2474          * Set HW accessible bit before powering on the controller
2475          * since an interrupt may rise.
2476          */
2477         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2478
2479         /*
2480          * Enable power if not already done.
2481          * This must not be spinlocked since duration
2482          * of this call is unknown.
2483          */
2484         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2485                 spin_unlock_irqrestore(&hsotg->lock, flags);
2486                 usb_phy_set_suspend(hsotg->uphy, false);
2487                 spin_lock_irqsave(&hsotg->lock, flags);
2488         }
2489
2490         /* Exit hibernation */
2491         ret = dwc2_exit_hibernation(hsotg, true);
2492         if (ret && (ret != -ENOTSUPP))
2493                 dev_err(hsotg->dev, "exit hibernation failed\n");
2494
2495         hsotg->lx_state = DWC2_L0;
2496
2497         spin_unlock_irqrestore(&hsotg->lock, flags);
2498
2499         if (hsotg->bus_suspended) {
2500                 spin_lock_irqsave(&hsotg->lock, flags);
2501                 hsotg->flags.b.port_suspend_change = 1;
2502                 spin_unlock_irqrestore(&hsotg->lock, flags);
2503                 dwc2_port_resume(hsotg);
2504         } else {
2505                 /* Wait for controller to correctly update D+/D- level */
2506                 usleep_range(3000, 5000);
2507
2508                 /*
2509                  * Clear Port Enable and Port Status changes.
2510                  * Enable Port Power.
2511                  */
2512                 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2513                                 HPRT0_ENACHG, hsotg->regs + HPRT0);
2514                 /* Wait for controller to detect Port Connect */
2515                 usleep_range(5000, 7000);
2516         }
2517
2518         return ret;
2519 unlock:
2520         spin_unlock_irqrestore(&hsotg->lock, flags);
2521
2522         return ret;
2523 }
2524
2525 /* Returns the current frame number */
2526 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2527 {
2528         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2529
2530         return dwc2_hcd_get_frame_number(hsotg);
2531 }
2532
2533 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2534                                char *fn_name)
2535 {
2536 #ifdef VERBOSE_DEBUG
2537         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2538         char *pipetype;
2539         char *speed;
2540
2541         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2542         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2543                  usb_pipedevice(urb->pipe));
2544         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2545                  usb_pipeendpoint(urb->pipe),
2546                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2547
2548         switch (usb_pipetype(urb->pipe)) {
2549         case PIPE_CONTROL:
2550                 pipetype = "CONTROL";
2551                 break;
2552         case PIPE_BULK:
2553                 pipetype = "BULK";
2554                 break;
2555         case PIPE_INTERRUPT:
2556                 pipetype = "INTERRUPT";
2557                 break;
2558         case PIPE_ISOCHRONOUS:
2559                 pipetype = "ISOCHRONOUS";
2560                 break;
2561         default:
2562                 pipetype = "UNKNOWN";
2563                 break;
2564         }
2565
2566         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2567                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2568                  "IN" : "OUT");
2569
2570         switch (urb->dev->speed) {
2571         case USB_SPEED_HIGH:
2572                 speed = "HIGH";
2573                 break;
2574         case USB_SPEED_FULL:
2575                 speed = "FULL";
2576                 break;
2577         case USB_SPEED_LOW:
2578                 speed = "LOW";
2579                 break;
2580         default:
2581                 speed = "UNKNOWN";
2582                 break;
2583         }
2584
2585         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2586         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2587                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2588         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2589                  urb->transfer_buffer_length);
2590         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2591                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2592         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2593                  urb->setup_packet, (unsigned long)urb->setup_dma);
2594         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2595
2596         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2597                 int i;
2598
2599                 for (i = 0; i < urb->number_of_packets; i++) {
2600                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2601                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2602                                  urb->iso_frame_desc[i].offset,
2603                                  urb->iso_frame_desc[i].length);
2604                 }
2605         }
2606 #endif
2607 }
2608
2609 /*
2610  * Starts processing a USB transfer request specified by a USB Request Block
2611  * (URB). mem_flags indicates the type of memory allocation to use while
2612  * processing this URB.
2613  */
2614 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2615                                  gfp_t mem_flags)
2616 {
2617         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2618         struct usb_host_endpoint *ep = urb->ep;
2619         struct dwc2_hcd_urb *dwc2_urb;
2620         int i;
2621         int retval;
2622         int alloc_bandwidth = 0;
2623         u8 ep_type = 0;
2624         u32 tflags = 0;
2625         void *buf;
2626         unsigned long flags;
2627         struct dwc2_qh *qh;
2628         bool qh_allocated = false;
2629         struct dwc2_qtd *qtd;
2630
2631         if (dbg_urb(urb)) {
2632                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2633                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2634         }
2635
2636         if (ep == NULL)
2637                 return -EINVAL;
2638
2639         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2640             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2641                 spin_lock_irqsave(&hsotg->lock, flags);
2642                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2643                         alloc_bandwidth = 1;
2644                 spin_unlock_irqrestore(&hsotg->lock, flags);
2645         }
2646
2647         switch (usb_pipetype(urb->pipe)) {
2648         case PIPE_CONTROL:
2649                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2650                 break;
2651         case PIPE_ISOCHRONOUS:
2652                 ep_type = USB_ENDPOINT_XFER_ISOC;
2653                 break;
2654         case PIPE_BULK:
2655                 ep_type = USB_ENDPOINT_XFER_BULK;
2656                 break;
2657         case PIPE_INTERRUPT:
2658                 ep_type = USB_ENDPOINT_XFER_INT;
2659                 break;
2660         default:
2661                 dev_warn(hsotg->dev, "Wrong ep type\n");
2662         }
2663
2664         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2665                                       mem_flags);
2666         if (!dwc2_urb)
2667                 return -ENOMEM;
2668
2669         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2670                                   usb_pipeendpoint(urb->pipe), ep_type,
2671                                   usb_pipein(urb->pipe),
2672                                   usb_maxpacket(urb->dev, urb->pipe,
2673                                                 !(usb_pipein(urb->pipe))));
2674
2675         buf = urb->transfer_buffer;
2676
2677         if (hcd->self.uses_dma) {
2678                 if (!buf && (urb->transfer_dma & 3)) {
2679                         dev_err(hsotg->dev,
2680                                 "%s: unaligned transfer with no transfer_buffer",
2681                                 __func__);
2682                         retval = -EINVAL;
2683                         goto fail0;
2684                 }
2685         }
2686
2687         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2688                 tflags |= URB_GIVEBACK_ASAP;
2689         if (urb->transfer_flags & URB_ZERO_PACKET)
2690                 tflags |= URB_SEND_ZERO_PACKET;
2691
2692         dwc2_urb->priv = urb;
2693         dwc2_urb->buf = buf;
2694         dwc2_urb->dma = urb->transfer_dma;
2695         dwc2_urb->length = urb->transfer_buffer_length;
2696         dwc2_urb->setup_packet = urb->setup_packet;
2697         dwc2_urb->setup_dma = urb->setup_dma;
2698         dwc2_urb->flags = tflags;
2699         dwc2_urb->interval = urb->interval;
2700         dwc2_urb->status = -EINPROGRESS;
2701
2702         for (i = 0; i < urb->number_of_packets; ++i)
2703                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2704                                                  urb->iso_frame_desc[i].offset,
2705                                                  urb->iso_frame_desc[i].length);
2706
2707         urb->hcpriv = dwc2_urb;
2708         qh = (struct dwc2_qh *) ep->hcpriv;
2709         /* Create QH for the endpoint if it doesn't exist */
2710         if (!qh) {
2711                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2712                 if (!qh) {
2713                         retval = -ENOMEM;
2714                         goto fail0;
2715                 }
2716                 ep->hcpriv = qh;
2717                 qh_allocated = true;
2718         }
2719
2720         qtd = kzalloc(sizeof(*qtd), mem_flags);
2721         if (!qtd) {
2722                 retval = -ENOMEM;
2723                 goto fail1;
2724         }
2725
2726         spin_lock_irqsave(&hsotg->lock, flags);
2727         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2728         if (retval)
2729                 goto fail2;
2730
2731         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
2732         if (retval)
2733                 goto fail3;
2734
2735         if (alloc_bandwidth) {
2736                 dwc2_allocate_bus_bandwidth(hcd,
2737                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2738                                 urb);
2739         }
2740
2741         spin_unlock_irqrestore(&hsotg->lock, flags);
2742
2743         return 0;
2744
2745 fail3:
2746         dwc2_urb->priv = NULL;
2747         usb_hcd_unlink_urb_from_ep(hcd, urb);
2748 fail2:
2749         spin_unlock_irqrestore(&hsotg->lock, flags);
2750         urb->hcpriv = NULL;
2751         kfree(qtd);
2752 fail1:
2753         if (qh_allocated) {
2754                 struct dwc2_qtd *qtd2, *qtd2_tmp;
2755
2756                 ep->hcpriv = NULL;
2757                 dwc2_hcd_qh_unlink(hsotg, qh);
2758                 /* Free each QTD in the QH's QTD list */
2759                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2760                                                          qtd_list_entry)
2761                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2762                 dwc2_hcd_qh_free(hsotg, qh);
2763         }
2764 fail0:
2765         kfree(dwc2_urb);
2766
2767         return retval;
2768 }
2769
2770 /*
2771  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2772  */
2773 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2774                                  int status)
2775 {
2776         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2777         int rc;
2778         unsigned long flags;
2779
2780         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2781         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2782
2783         spin_lock_irqsave(&hsotg->lock, flags);
2784
2785         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2786         if (rc)
2787                 goto out;
2788
2789         if (!urb->hcpriv) {
2790                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2791                 goto out;
2792         }
2793
2794         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2795
2796         usb_hcd_unlink_urb_from_ep(hcd, urb);
2797
2798         kfree(urb->hcpriv);
2799         urb->hcpriv = NULL;
2800
2801         /* Higher layer software sets URB status */
2802         spin_unlock(&hsotg->lock);
2803         usb_hcd_giveback_urb(hcd, urb, status);
2804         spin_lock(&hsotg->lock);
2805
2806         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2807         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2808 out:
2809         spin_unlock_irqrestore(&hsotg->lock, flags);
2810
2811         return rc;
2812 }
2813
2814 /*
2815  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2816  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2817  * must already be dequeued.
2818  */
2819 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2820                                        struct usb_host_endpoint *ep)
2821 {
2822         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2823
2824         dev_dbg(hsotg->dev,
2825                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2826                 ep->desc.bEndpointAddress, ep->hcpriv);
2827         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2828 }
2829
2830 /*
2831  * Resets endpoint specific parameter values, in current version used to reset
2832  * the data toggle (as a WA). This function can be called from usb_clear_halt
2833  * routine.
2834  */
2835 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2836                                      struct usb_host_endpoint *ep)
2837 {
2838         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2839         unsigned long flags;
2840
2841         dev_dbg(hsotg->dev,
2842                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2843                 ep->desc.bEndpointAddress);
2844
2845         spin_lock_irqsave(&hsotg->lock, flags);
2846         dwc2_hcd_endpoint_reset(hsotg, ep);
2847         spin_unlock_irqrestore(&hsotg->lock, flags);
2848 }
2849
2850 /*
2851  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2852  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2853  * interrupt.
2854  *
2855  * This function is called by the USB core when an interrupt occurs
2856  */
2857 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2858 {
2859         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2860
2861         return dwc2_handle_hcd_intr(hsotg);
2862 }
2863
2864 /*
2865  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2866  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2867  * is the status change indicator for the single root port. Returns 1 if either
2868  * change indicator is 1, otherwise returns 0.
2869  */
2870 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2871 {
2872         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2873
2874         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2875         return buf[0] != 0;
2876 }
2877
2878 /* Handles hub class-specific requests */
2879 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2880                                  u16 windex, char *buf, u16 wlength)
2881 {
2882         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2883                                           wvalue, windex, buf, wlength);
2884         return retval;
2885 }
2886
2887 /* Handles hub TT buffer clear completions */
2888 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2889                                                struct usb_host_endpoint *ep)
2890 {
2891         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2892         struct dwc2_qh *qh;
2893         unsigned long flags;
2894
2895         qh = ep->hcpriv;
2896         if (!qh)
2897                 return;
2898
2899         spin_lock_irqsave(&hsotg->lock, flags);
2900         qh->tt_buffer_dirty = 0;
2901
2902         if (hsotg->flags.b.port_connect_status)
2903                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2904
2905         spin_unlock_irqrestore(&hsotg->lock, flags);
2906 }
2907
2908 static struct hc_driver dwc2_hc_driver = {
2909         .description = "dwc2_hsotg",
2910         .product_desc = "DWC OTG Controller",
2911         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2912
2913         .irq = _dwc2_hcd_irq,
2914         .flags = HCD_MEMORY | HCD_USB2,
2915
2916         .start = _dwc2_hcd_start,
2917         .stop = _dwc2_hcd_stop,
2918         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2919         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2920         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2921         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2922         .get_frame_number = _dwc2_hcd_get_frame_number,
2923
2924         .hub_status_data = _dwc2_hcd_hub_status_data,
2925         .hub_control = _dwc2_hcd_hub_control,
2926         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2927
2928         .bus_suspend = _dwc2_hcd_suspend,
2929         .bus_resume = _dwc2_hcd_resume,
2930 };
2931
2932 /*
2933  * Frees secondary storage associated with the dwc2_hsotg structure contained
2934  * in the struct usb_hcd field
2935  */
2936 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2937 {
2938         u32 ahbcfg;
2939         u32 dctl;
2940         int i;
2941
2942         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2943
2944         /* Free memory for QH/QTD lists */
2945         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2946         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2947         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2948         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2949         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2950         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2951
2952         /* Free memory for the host channels */
2953         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2954                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2955
2956                 if (chan != NULL) {
2957                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2958                                 i, chan);
2959                         hsotg->hc_ptr_array[i] = NULL;
2960                         kfree(chan);
2961                 }
2962         }
2963
2964         if (hsotg->core_params->dma_enable > 0) {
2965                 if (hsotg->status_buf) {
2966                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2967                                           hsotg->status_buf,
2968                                           hsotg->status_buf_dma);
2969                         hsotg->status_buf = NULL;
2970                 }
2971         } else {
2972                 kfree(hsotg->status_buf);
2973                 hsotg->status_buf = NULL;
2974         }
2975
2976         ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2977
2978         /* Disable all interrupts */
2979         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2980         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2981         dwc2_writel(0, hsotg->regs + GINTMSK);
2982
2983         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2984                 dctl = dwc2_readl(hsotg->regs + DCTL);
2985                 dctl |= DCTL_SFTDISCON;
2986                 dwc2_writel(dctl, hsotg->regs + DCTL);
2987         }
2988
2989         if (hsotg->wq_otg) {
2990                 if (!cancel_work_sync(&hsotg->wf_otg))
2991                         flush_workqueue(hsotg->wq_otg);
2992                 destroy_workqueue(hsotg->wq_otg);
2993         }
2994
2995         del_timer(&hsotg->wkp_timer);
2996 }
2997
2998 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2999 {
3000         /* Turn off all host-specific interrupts */
3001         dwc2_disable_host_interrupts(hsotg);
3002
3003         dwc2_hcd_free(hsotg);
3004 }
3005
3006 /*
3007  * Initializes the HCD. This function allocates memory for and initializes the
3008  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
3009  * USB bus with the core and calls the hc_driver->start() function. It returns
3010  * a negative error on failure.
3011  */
3012 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
3013 {
3014         struct usb_hcd *hcd;
3015         struct dwc2_host_chan *channel;
3016         u32 hcfg;
3017         int i, num_channels;
3018         int retval;
3019
3020         if (usb_disabled())
3021                 return -ENODEV;
3022
3023         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
3024
3025         retval = -ENOMEM;
3026
3027         hcfg = dwc2_readl(hsotg->regs + HCFG);
3028         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
3029
3030 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3031         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3032                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3033         if (!hsotg->frame_num_array)
3034                 goto error1;
3035         hsotg->last_frame_num_array = kzalloc(
3036                         sizeof(*hsotg->last_frame_num_array) *
3037                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3038         if (!hsotg->last_frame_num_array)
3039                 goto error1;
3040         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3041 #endif
3042
3043         /* Check if the bus driver or platform code has setup a dma_mask */
3044         if (hsotg->core_params->dma_enable > 0 &&
3045             hsotg->dev->dma_mask == NULL) {
3046                 dev_warn(hsotg->dev,
3047                          "dma_mask not set, disabling DMA\n");
3048                 hsotg->core_params->dma_enable = 0;
3049                 hsotg->core_params->dma_desc_enable = 0;
3050         }
3051
3052         /* Set device flags indicating whether the HCD supports DMA */
3053         if (hsotg->core_params->dma_enable > 0) {
3054                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3055                         dev_warn(hsotg->dev, "can't set DMA mask\n");
3056                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3057                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
3058         }
3059
3060         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3061         if (!hcd)
3062                 goto error1;
3063
3064         if (hsotg->core_params->dma_enable <= 0)
3065                 hcd->self.uses_dma = 0;
3066
3067         hcd->has_tt = 1;
3068
3069         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3070         hsotg->priv = hcd;
3071
3072         /*
3073          * Disable the global interrupt until all the interrupt handlers are
3074          * installed
3075          */
3076         dwc2_disable_global_interrupts(hsotg);
3077
3078         /* Initialize the DWC_otg core, and select the Phy type */
3079         retval = dwc2_core_init(hsotg, true);
3080         if (retval)
3081                 goto error2;
3082
3083         /* Create new workqueue and init work */
3084         retval = -ENOMEM;
3085         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
3086         if (!hsotg->wq_otg) {
3087                 dev_err(hsotg->dev, "Failed to create workqueue\n");
3088                 goto error2;
3089         }
3090         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3091
3092         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3093                     (unsigned long)hsotg);
3094
3095         /* Initialize the non-periodic schedule */
3096         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3097         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3098
3099         /* Initialize the periodic schedule */
3100         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3101         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3102         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3103         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3104
3105         /*
3106          * Create a host channel descriptor for each host channel implemented
3107          * in the controller. Initialize the channel descriptor array.
3108          */
3109         INIT_LIST_HEAD(&hsotg->free_hc_list);
3110         num_channels = hsotg->core_params->host_channels;
3111         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3112
3113         for (i = 0; i < num_channels; i++) {
3114                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3115                 if (channel == NULL)
3116                         goto error3;
3117                 channel->hc_num = i;
3118                 hsotg->hc_ptr_array[i] = channel;
3119         }
3120
3121         if (hsotg->core_params->uframe_sched > 0)
3122                 dwc2_hcd_init_usecs(hsotg);
3123
3124         /* Initialize hsotg start work */
3125         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3126
3127         /* Initialize port reset work */
3128         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3129
3130         /*
3131          * Allocate space for storing data on status transactions. Normally no
3132          * data is sent, but this space acts as a bit bucket. This must be
3133          * done after usb_add_hcd since that function allocates the DMA buffer
3134          * pool.
3135          */
3136         if (hsotg->core_params->dma_enable > 0)
3137                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3138                                         DWC2_HCD_STATUS_BUF_SIZE,
3139                                         &hsotg->status_buf_dma, GFP_KERNEL);
3140         else
3141                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3142                                           GFP_KERNEL);
3143
3144         if (!hsotg->status_buf)
3145                 goto error3;
3146
3147         hsotg->otg_port = 1;
3148         hsotg->frame_list = NULL;
3149         hsotg->frame_list_dma = 0;
3150         hsotg->periodic_qh_count = 0;
3151
3152         /* Initiate lx_state to L3 disconnected state */
3153         hsotg->lx_state = DWC2_L3;
3154
3155         hcd->self.otg_port = hsotg->otg_port;
3156
3157         /* Don't support SG list at this point */
3158         hcd->self.sg_tablesize = 0;
3159
3160         if (!IS_ERR_OR_NULL(hsotg->uphy))
3161                 otg_set_host(hsotg->uphy->otg, &hcd->self);
3162
3163         /*
3164          * Finish generic HCD initialization and start the HCD. This function
3165          * allocates the DMA buffer pool, registers the USB bus, requests the
3166          * IRQ line, and calls hcd_start method.
3167          */
3168         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
3169         if (retval < 0)
3170                 goto error3;
3171
3172         device_wakeup_enable(hcd->self.controller);
3173
3174         dwc2_hcd_dump_state(hsotg);
3175
3176         dwc2_enable_global_interrupts(hsotg);
3177
3178         return 0;
3179
3180 error3:
3181         dwc2_hcd_release(hsotg);
3182 error2:
3183         usb_put_hcd(hcd);
3184 error1:
3185         kfree(hsotg->core_params);
3186
3187 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3188         kfree(hsotg->last_frame_num_array);
3189         kfree(hsotg->frame_num_array);
3190 #endif
3191
3192         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
3193         return retval;
3194 }
3195
3196 /*
3197  * Removes the HCD.
3198  * Frees memory and resources associated with the HCD and deregisters the bus.
3199  */
3200 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
3201 {
3202         struct usb_hcd *hcd;
3203
3204         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
3205
3206         hcd = dwc2_hsotg_to_hcd(hsotg);
3207         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
3208
3209         if (!hcd) {
3210                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3211                         __func__);
3212                 return;
3213         }
3214
3215         if (!IS_ERR_OR_NULL(hsotg->uphy))
3216                 otg_set_host(hsotg->uphy->otg, NULL);
3217
3218         usb_remove_hcd(hcd);
3219         hsotg->priv = NULL;
3220         dwc2_hcd_release(hsotg);
3221         usb_put_hcd(hcd);
3222
3223 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3224         kfree(hsotg->last_frame_num_array);
3225         kfree(hsotg->frame_num_array);
3226 #endif
3227 }