drivers/usb/dwc2/hcd.c

   1 /*
   2  * hcd.c - DesignWare HS OTG Controller host-mode routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * This file contains the core HCD code, and implements the Linux hc_driver
  39  * API
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/spinlock.h>
  44 #include <linux/interrupt.h>
  45 #include <linux/dma-mapping.h>
  46 #include <linux/delay.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 /**
  58  * dwc2_dump_channel_info() - Prints the state of a host channel
  59  *
  60  * @hsotg: Programming view of DWC_otg controller
  61  * @chan:  Pointer to the channel to dump
  62  *
  63  * Must be called with interrupt disabled and spinlock held
  64  *
  65  * NOTE: This function will be removed once the peripheral controller code
  66  * is integrated and the driver is stable
  67  */
  68 static void dwc2_dump_channel_info(struct dwc2_hsotg *hsotg,
  69                                    struct dwc2_host_chan *chan)
  70 {
  71 #ifdef VERBOSE_DEBUG
  72         int num_channels = hsotg->core_params->host_channels;
  73         struct dwc2_qh *qh;
  74         u32 hcchar;
  75         u32 hcsplt;
  76         u32 hctsiz;
  77         u32 hc_dma;
  78         int i;
  79
  80         if (chan == NULL)
  81                 return;
  82
  83         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
  84         hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
  85         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(chan->hc_num));
  86         hc_dma = dwc2_readl(hsotg->regs + HCDMA(chan->hc_num));
  87
  88         dev_dbg(hsotg->dev, "  Assigned to channel %p:\n", chan);
  89         dev_dbg(hsotg->dev, "    hcchar 0x%08x, hcsplt 0x%08x\n",
  90                 hcchar, hcsplt);
  91         dev_dbg(hsotg->dev, "    hctsiz 0x%08x, hc_dma 0x%08x\n",
  92                 hctsiz, hc_dma);
  93         dev_dbg(hsotg->dev, "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
  94                 chan->dev_addr, chan->ep_num, chan->ep_is_in);
  95         dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
  96         dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
  97         dev_dbg(hsotg->dev, "    data_pid_start: %d\n", chan->data_pid_start);
  98         dev_dbg(hsotg->dev, "    xfer_started: %d\n", chan->xfer_started);
  99         dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
 100         dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
 101         dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
 102                 (unsigned long)chan->xfer_dma);
 103         dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
 104         dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
 105         dev_dbg(hsotg->dev, "  NP inactive sched:\n");
 106         list_for_each_entry(qh, &hsotg->non_periodic_sched_inactive,
 107                             qh_list_entry)
 108                 dev_dbg(hsotg->dev, "    %p\n", qh);
 109         dev_dbg(hsotg->dev, "  NP active sched:\n");
 110         list_for_each_entry(qh, &hsotg->non_periodic_sched_active,
 111                             qh_list_entry)
 112                 dev_dbg(hsotg->dev, "    %p\n", qh);
 113         dev_dbg(hsotg->dev, "  Channels:\n");
 114         for (i = 0; i < num_channels; i++) {
 115                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
 116
 117                 dev_dbg(hsotg->dev, "    %2d: %p\n", i, chan);
 118         }
 119 #endif /* VERBOSE_DEBUG */
 120 }
 121
 122 /*
 123  * Processes all the URBs in a single list of QHs. Completes them with
 124  * -ETIMEDOUT and frees the QTD.
 125  *
 126  * Must be called with interrupt disabled and spinlock held
 127  */
 128 static void dwc2_kill_urbs_in_qh_list(struct dwc2_hsotg *hsotg,
 129                                       struct list_head *qh_list)
 130 {
 131         struct dwc2_qh *qh, *qh_tmp;
 132         struct dwc2_qtd *qtd, *qtd_tmp;
 133
 134         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 135                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 136                                          qtd_list_entry) {
 137                         dwc2_host_complete(hsotg, qtd, -ECONNRESET);
 138                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 139                 }
 140         }
 141 }
 142
 143 static void dwc2_qh_list_free(struct dwc2_hsotg *hsotg,
 144                               struct list_head *qh_list)
 145 {
 146         struct dwc2_qtd *qtd, *qtd_tmp;
 147         struct dwc2_qh *qh, *qh_tmp;
 148         unsigned long flags;
 149
 150         if (!qh_list->next)
 151                 /* The list hasn't been initialized yet */
 152                 return;
 153
 154         spin_lock_irqsave(&hsotg->lock, flags);
 155
 156         /* Ensure there are no QTDs or URBs left */
 157         dwc2_kill_urbs_in_qh_list(hsotg, qh_list);
 158
 159         list_for_each_entry_safe(qh, qh_tmp, qh_list, qh_list_entry) {
 160                 dwc2_hcd_qh_unlink(hsotg, qh);
 161
 162                 /* Free each QTD in the QH's QTD list */
 163                 list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list,
 164                                          qtd_list_entry)
 165                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 166
 167                 spin_unlock_irqrestore(&hsotg->lock, flags);
 168                 dwc2_hcd_qh_free(hsotg, qh);
 169                 spin_lock_irqsave(&hsotg->lock, flags);
 170         }
 171
 172         spin_unlock_irqrestore(&hsotg->lock, flags);
 173 }
 174
 175 /*
 176  * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
 177  * and periodic schedules. The QTD associated with each URB is removed from
 178  * the schedule and freed. This function may be called when a disconnect is
 179  * detected or when the HCD is being stopped.
 180  *
 181  * Must be called with interrupt disabled and spinlock held
 182  */
 183 static void dwc2_kill_all_urbs(struct dwc2_hsotg *hsotg)
 184 {
 185         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_inactive);
 186         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->non_periodic_sched_active);
 187         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_inactive);
 188         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_ready);
 189         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_assigned);
 190         dwc2_kill_urbs_in_qh_list(hsotg, &hsotg->periodic_sched_queued);
 191 }
 192
 193 /**
 194  * dwc2_hcd_start() - Starts the HCD when switching to Host mode
 195  *
 196  * @hsotg: Pointer to struct dwc2_hsotg
 197  */
 198 void dwc2_hcd_start(struct dwc2_hsotg *hsotg)
 199 {
 200         u32 hprt0;
 201
 202         if (hsotg->op_state == OTG_STATE_B_HOST) {
 203                 /*
 204                  * Reset the port. During a HNP mode switch the reset
 205                  * needs to occur within 1ms and have a duration of at
 206                  * least 50ms.
 207                  */
 208                 hprt0 = dwc2_read_hprt0(hsotg);
 209                 hprt0 |= HPRT0_RST;
 210                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
 211         }
 212
 213         queue_delayed_work(hsotg->wq_otg, &hsotg->start_work,
 214                            msecs_to_jiffies(50));
 215 }
 216
 217 /* Must be called with interrupt disabled and spinlock held */
 218 static void dwc2_hcd_cleanup_channels(struct dwc2_hsotg *hsotg)
 219 {
 220         int num_channels = hsotg->core_params->host_channels;
 221         struct dwc2_host_chan *channel;
 222         u32 hcchar;
 223         int i;
 224
 225         if (hsotg->core_params->dma_enable <= 0) {
 226                 /* Flush out any channel requests in slave mode */
 227                 for (i = 0; i < num_channels; i++) {
 228                         channel = hsotg->hc_ptr_array[i];
 229                         if (!list_empty(&channel->hc_list_entry))
 230                                 continue;
 231                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 232                         if (hcchar & HCCHAR_CHENA) {
 233                                 hcchar &= ~(HCCHAR_CHENA | HCCHAR_EPDIR);
 234                                 hcchar |= HCCHAR_CHDIS;
 235                                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 236                         }
 237                 }
 238         }
 239
 240         for (i = 0; i < num_channels; i++) {
 241                 channel = hsotg->hc_ptr_array[i];
 242                 if (!list_empty(&channel->hc_list_entry))
 243                         continue;
 244                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
 245                 if (hcchar & HCCHAR_CHENA) {
 246                         /* Halt the channel */
 247                         hcchar |= HCCHAR_CHDIS;
 248                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
 249                 }
 250
 251                 dwc2_hc_cleanup(hsotg, channel);
 252                 list_add_tail(&channel->hc_list_entry, &hsotg->free_hc_list);
 253                 /*
 254                  * Added for Descriptor DMA to prevent channel double cleanup in
 255                  * release_channel_ddma(), which is called from ep_disable when
 256                  * device disconnects
 257                  */
 258                 channel->qh = NULL;
 259         }
 260         /* All channels have been freed, mark them available */
 261         if (hsotg->core_params->uframe_sched > 0) {
 262                 hsotg->available_host_channels =
 263                         hsotg->core_params->host_channels;
 264         } else {
 265                 hsotg->non_periodic_channels = 0;
 266                 hsotg->periodic_channels = 0;
 267         }
 268 }
 269
 270 /**
 271  * dwc2_hcd_disconnect() - Handles disconnect of the HCD
 272  *
 273  * @hsotg: Pointer to struct dwc2_hsotg
 274  *
 275  * Must be called with interrupt disabled and spinlock held
 276  */
 277 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg)
 278 {
 279         u32 intr;
 280
 281         /* Set status flags for the hub driver */
 282         hsotg->flags.b.port_connect_status_change = 1;
 283         hsotg->flags.b.port_connect_status = 0;
 284
 285         /*
 286          * Shutdown any transfers in process by clearing the Tx FIFO Empty
 287          * interrupt mask and status bits and disabling subsequent host
 288          * channel interrupts.
 289          */
 290         intr = dwc2_readl(hsotg->regs + GINTMSK);
 291         intr &= ~(GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT);
 292         dwc2_writel(intr, hsotg->regs + GINTMSK);
 293         intr = GINTSTS_NPTXFEMP | GINTSTS_PTXFEMP | GINTSTS_HCHINT;
 294         dwc2_writel(intr, hsotg->regs + GINTSTS);
 295
 296         /*
 297          * Turn off the vbus power only if the core has transitioned to device
 298          * mode. If still in host mode, need to keep power on to detect a
 299          * reconnection.
 300          */
 301         if (dwc2_is_device_mode(hsotg)) {
 302                 if (hsotg->op_state != OTG_STATE_A_SUSPEND) {
 303                         dev_dbg(hsotg->dev, "Disconnect: PortPower off\n");
 304                         dwc2_writel(0, hsotg->regs + HPRT0);
 305                 }
 306
 307                 dwc2_disable_host_interrupts(hsotg);
 308         }
 309
 310         /* Respond with an error status to all URBs in the schedule */
 311         dwc2_kill_all_urbs(hsotg);
 312
 313         if (dwc2_is_host_mode(hsotg))
 314                 /* Clean up any host channels that were in use */
 315                 dwc2_hcd_cleanup_channels(hsotg);
 316
 317         dwc2_host_disconnect(hsotg);
 318 }
 319
 320 /**
 321  * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
 322  *
 323  * @hsotg: Pointer to struct dwc2_hsotg
 324  */
 325 static void dwc2_hcd_rem_wakeup(struct dwc2_hsotg *hsotg)
 326 {
 327         if (hsotg->bus_suspended) {
 328                 hsotg->flags.b.port_suspend_change = 1;
 329                 usb_hcd_resume_root_hub(hsotg->priv);
 330         }
 331
 332         if (hsotg->lx_state == DWC2_L1)
 333                 hsotg->flags.b.port_l1_change = 1;
 334 }
 335
 336 /**
 337  * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
 338  *
 339  * @hsotg: Pointer to struct dwc2_hsotg
 340  *
 341  * Must be called with interrupt disabled and spinlock held
 342  */
 343 void dwc2_hcd_stop(struct dwc2_hsotg *hsotg)
 344 {
 345         dev_dbg(hsotg->dev, "DWC OTG HCD STOP\n");
 346
 347         /*
 348          * The root hub should be disconnected before this function is called.
 349          * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
 350          * and the QH lists (via ..._hcd_endpoint_disable).
 351          */
 352
 353         /* Turn off all host-specific interrupts */
 354         dwc2_disable_host_interrupts(hsotg);
 355
 356         /* Turn off the vbus power */
 357         dev_dbg(hsotg->dev, "PortPower off\n");
 358         dwc2_writel(0, hsotg->regs + HPRT0);
 359 }
 360
 361 /* Caller must hold driver lock */
 362 static int dwc2_hcd_urb_enqueue(struct dwc2_hsotg *hsotg,
 363                                 struct dwc2_hcd_urb *urb, struct dwc2_qh *qh,
 364                                 struct dwc2_qtd *qtd)
 365 {
 366         u32 intr_mask;
 367         int retval;
 368         int dev_speed;
 369
 370         if (!hsotg->flags.b.port_connect_status) {
 371                 /* No longer connected */
 372                 dev_err(hsotg->dev, "Not connected\n");
 373                 return -ENODEV;
 374         }
 375
 376         dev_speed = dwc2_host_get_speed(hsotg, urb->priv);
 377
 378         /* Some configurations cannot support LS traffic on a FS root port */
 379         if ((dev_speed == USB_SPEED_LOW) &&
 380             (hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED) &&
 381             (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI)) {
 382                 u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
 383                 u32 prtspd = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
 384
 385                 if (prtspd == HPRT0_SPD_FULL_SPEED)
 386                         return -ENODEV;
 387         }
 388
 389         if (!qtd)
 390                 return -EINVAL;
 391
 392         dwc2_hcd_qtd_init(qtd, urb);
 393         retval = dwc2_hcd_qtd_add(hsotg, qtd, qh);
 394         if (retval) {
 395                 dev_err(hsotg->dev,
 396                         "DWC OTG HCD URB Enqueue failed adding QTD. Error status %d\n",
 397                         retval);
 398                 return retval;
 399         }
 400
 401         intr_mask = dwc2_readl(hsotg->regs + GINTMSK);
 402         if (!(intr_mask & GINTSTS_SOF)) {
 403                 enum dwc2_transaction_type tr_type;
 404
 405                 if (qtd->qh->ep_type == USB_ENDPOINT_XFER_BULK &&
 406                     !(qtd->urb->flags & URB_GIVEBACK_ASAP))
 407                         /*
 408                          * Do not schedule SG transactions until qtd has
 409                          * URB_GIVEBACK_ASAP set
 410                          */
 411                         return 0;
 412
 413                 tr_type = dwc2_hcd_select_transactions(hsotg);
 414                 if (tr_type != DWC2_TRANSACTION_NONE)
 415                         dwc2_hcd_queue_transactions(hsotg, tr_type);
 416         }
 417
 418         return 0;
 419 }
 420
 421 /* Must be called with interrupt disabled and spinlock held */
 422 static int dwc2_hcd_urb_dequeue(struct dwc2_hsotg *hsotg,
 423                                 struct dwc2_hcd_urb *urb)
 424 {
 425         struct dwc2_qh *qh;
 426         struct dwc2_qtd *urb_qtd;
 427
 428         urb_qtd = urb->qtd;
 429         if (!urb_qtd) {
 430                 dev_dbg(hsotg->dev, "## Urb QTD is NULL ##\n");
 431                 return -EINVAL;
 432         }
 433
 434         qh = urb_qtd->qh;
 435         if (!qh) {
 436                 dev_dbg(hsotg->dev, "## Urb QTD QH is NULL ##\n");
 437                 return -EINVAL;
 438         }
 439
 440         urb->priv = NULL;
 441
 442         if (urb_qtd->in_process && qh->channel) {
 443                 dwc2_dump_channel_info(hsotg, qh->channel);
 444
 445                 /* The QTD is in process (it has been assigned to a channel) */
 446                 if (hsotg->flags.b.port_connect_status)
 447                         /*
 448                          * If still connected (i.e. in host mode), halt the
 449                          * channel so it can be used for other transfers. If
 450                          * no longer connected, the host registers can't be
 451                          * written to halt the channel since the core is in
 452                          * device mode.
 453                          */
 454                         dwc2_hc_halt(hsotg, qh->channel,
 455                                      DWC2_HC_XFER_URB_DEQUEUE);
 456         }
 457
 458         /*
 459          * Free the QTD and clean up the associated QH. Leave the QH in the
 460          * schedule if it has any remaining QTDs.
 461          */
 462         if (hsotg->core_params->dma_desc_enable <= 0) {
 463                 u8 in_process = urb_qtd->in_process;
 464
 465                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 466                 if (in_process) {
 467                         dwc2_hcd_qh_deactivate(hsotg, qh, 0);
 468                         qh->channel = NULL;
 469                 } else if (list_empty(&qh->qtd_list)) {
 470                         dwc2_hcd_qh_unlink(hsotg, qh);
 471                 }
 472         } else {
 473                 dwc2_hcd_qtd_unlink_and_free(hsotg, urb_qtd, qh);
 474         }
 475
 476         return 0;
 477 }
 478
 479 /* Must NOT be called with interrupt disabled or spinlock held */
 480 static int dwc2_hcd_endpoint_disable(struct dwc2_hsotg *hsotg,
 481                                      struct usb_host_endpoint *ep, int retry)
 482 {
 483         struct dwc2_qtd *qtd, *qtd_tmp;
 484         struct dwc2_qh *qh;
 485         unsigned long flags;
 486         int rc;
 487
 488         spin_lock_irqsave(&hsotg->lock, flags);
 489
 490         qh = ep->hcpriv;
 491         if (!qh) {
 492                 rc = -EINVAL;
 493                 goto err;
 494         }
 495
 496         while (!list_empty(&qh->qtd_list) && retry--) {
 497                 if (retry == 0) {
 498                         dev_err(hsotg->dev,
 499                                 "## timeout in dwc2_hcd_endpoint_disable() ##\n");
 500                         rc = -EBUSY;
 501                         goto err;
 502                 }
 503
 504                 spin_unlock_irqrestore(&hsotg->lock, flags);
 505                 usleep_range(20000, 40000);
 506                 spin_lock_irqsave(&hsotg->lock, flags);
 507                 qh = ep->hcpriv;
 508                 if (!qh) {
 509                         rc = -EINVAL;
 510                         goto err;
 511                 }
 512         }
 513
 514         dwc2_hcd_qh_unlink(hsotg, qh);
 515
 516         /* Free each QTD in the QH's QTD list */
 517         list_for_each_entry_safe(qtd, qtd_tmp, &qh->qtd_list, qtd_list_entry)
 518                 dwc2_hcd_qtd_unlink_and_free(hsotg, qtd, qh);
 519
 520         ep->hcpriv = NULL;
 521         spin_unlock_irqrestore(&hsotg->lock, flags);
 522         dwc2_hcd_qh_free(hsotg, qh);
 523
 524         return 0;
 525
 526 err:
 527         ep->hcpriv = NULL;
 528         spin_unlock_irqrestore(&hsotg->lock, flags);
 529
 530         return rc;
 531 }
 532
 533 /* Must be called with interrupt disabled and spinlock held */
 534 static int dwc2_hcd_endpoint_reset(struct dwc2_hsotg *hsotg,
 535                                    struct usb_host_endpoint *ep)
 536 {
 537         struct dwc2_qh *qh = ep->hcpriv;
 538
 539         if (!qh)
 540                 return -EINVAL;
 541
 542         qh->data_toggle = DWC2_HC_PID_DATA0;
 543
 544         return 0;
 545 }
 546
 547 /*
 548  * Initializes dynamic portions of the DWC_otg HCD state
 549  *
 550  * Must be called with interrupt disabled and spinlock held
 551  */
 552 static void dwc2_hcd_reinit(struct dwc2_hsotg *hsotg)
 553 {
 554         struct dwc2_host_chan *chan, *chan_tmp;
 555         int num_channels;
 556         int i;
 557
 558         hsotg->flags.d32 = 0;
 559         hsotg->non_periodic_qh_ptr = &hsotg->non_periodic_sched_active;
 560
 561         if (hsotg->core_params->uframe_sched > 0) {
 562                 hsotg->available_host_channels =
 563                         hsotg->core_params->host_channels;
 564         } else {
 565                 hsotg->non_periodic_channels = 0;
 566                 hsotg->periodic_channels = 0;
 567         }
 568
 569         /*
 570          * Put all channels in the free channel list and clean up channel
 571          * states
 572          */
 573         list_for_each_entry_safe(chan, chan_tmp, &hsotg->free_hc_list,
 574                                  hc_list_entry)
 575                 list_del_init(&chan->hc_list_entry);
 576
 577         num_channels = hsotg->core_params->host_channels;
 578         for (i = 0; i < num_channels; i++) {
 579                 chan = hsotg->hc_ptr_array[i];
 580                 list_add_tail(&chan->hc_list_entry, &hsotg->free_hc_list);
 581                 dwc2_hc_cleanup(hsotg, chan);
 582         }
 583
 584         /* Initialize the DWC core for host mode operation */
 585         dwc2_core_host_init(hsotg);
 586 }
 587
 588 static void dwc2_hc_init_split(struct dwc2_hsotg *hsotg,
 589                                struct dwc2_host_chan *chan,
 590                                struct dwc2_qtd *qtd, struct dwc2_hcd_urb *urb)
 591 {
 592         int hub_addr, hub_port;
 593
 594         chan->do_split = 1;
 595         chan->xact_pos = qtd->isoc_split_pos;
 596         chan->complete_split = qtd->complete_split;
 597         dwc2_host_hub_info(hsotg, urb->priv, &hub_addr, &hub_port);
 598         chan->hub_addr = (u8)hub_addr;
 599         chan->hub_port = (u8)hub_port;
 600 }
 601
 602 static void *dwc2_hc_init_xfer(struct dwc2_hsotg *hsotg,
 603                                struct dwc2_host_chan *chan,
 604                                struct dwc2_qtd *qtd, void *bufptr)
 605 {
 606         struct dwc2_hcd_urb *urb = qtd->urb;
 607         struct dwc2_hcd_iso_packet_desc *frame_desc;
 608
 609         switch (dwc2_hcd_get_pipe_type(&urb->pipe_info)) {
 610         case USB_ENDPOINT_XFER_CONTROL:
 611                 chan->ep_type = USB_ENDPOINT_XFER_CONTROL;
 612
 613                 switch (qtd->control_phase) {
 614                 case DWC2_CONTROL_SETUP:
 615                         dev_vdbg(hsotg->dev, "  Control setup transaction\n");
 616                         chan->do_ping = 0;
 617                         chan->ep_is_in = 0;
 618                         chan->data_pid_start = DWC2_HC_PID_SETUP;
 619                         if (hsotg->core_params->dma_enable > 0)
 620                                 chan->xfer_dma = urb->setup_dma;
 621                         else
 622                                 chan->xfer_buf = urb->setup_packet;
 623                         chan->xfer_len = 8;
 624                         bufptr = NULL;
 625                         break;
 626
 627                 case DWC2_CONTROL_DATA:
 628                         dev_vdbg(hsotg->dev, "  Control data transaction\n");
 629                         chan->data_pid_start = qtd->data_toggle;
 630                         break;
 631
 632                 case DWC2_CONTROL_STATUS:
 633                         /*
 634                          * Direction is opposite of data direction or IN if no
 635                          * data
 636                          */
 637                         dev_vdbg(hsotg->dev, "  Control status transaction\n");
 638                         if (urb->length == 0)
 639                                 chan->ep_is_in = 1;
 640                         else
 641                                 chan->ep_is_in =
 642                                         dwc2_hcd_is_pipe_out(&urb->pipe_info);
 643                         if (chan->ep_is_in)
 644                                 chan->do_ping = 0;
 645                         chan->data_pid_start = DWC2_HC_PID_DATA1;
 646                         chan->xfer_len = 0;
 647                         if (hsotg->core_params->dma_enable > 0)
 648                                 chan->xfer_dma = hsotg->status_buf_dma;
 649                         else
 650                                 chan->xfer_buf = hsotg->status_buf;
 651                         bufptr = NULL;
 652                         break;
 653                 }
 654                 break;
 655
 656         case USB_ENDPOINT_XFER_BULK:
 657                 chan->ep_type = USB_ENDPOINT_XFER_BULK;
 658                 break;
 659
 660         case USB_ENDPOINT_XFER_INT:
 661                 chan->ep_type = USB_ENDPOINT_XFER_INT;
 662                 break;
 663
 664         case USB_ENDPOINT_XFER_ISOC:
 665                 chan->ep_type = USB_ENDPOINT_XFER_ISOC;
 666                 if (hsotg->core_params->dma_desc_enable > 0)
 667                         break;
 668
 669                 frame_desc = &urb->iso_descs[qtd->isoc_frame_index];
 670                 frame_desc->status = 0;
 671
 672                 if (hsotg->core_params->dma_enable > 0) {
 673                         chan->xfer_dma = urb->dma;
 674                         chan->xfer_dma += frame_desc->offset +
 675                                         qtd->isoc_split_offset;
 676                 } else {
 677                         chan->xfer_buf = urb->buf;
 678                         chan->xfer_buf += frame_desc->offset +
 679                                         qtd->isoc_split_offset;
 680                 }
 681
 682                 chan->xfer_len = frame_desc->length - qtd->isoc_split_offset;
 683
 684                 /* For non-dword aligned buffers */
 685                 if (hsotg->core_params->dma_enable > 0 &&
 686                     (chan->xfer_dma & 0x3))
 687                         bufptr = (u8 *)urb->buf + frame_desc->offset +
 688                                         qtd->isoc_split_offset;
 689                 else
 690                         bufptr = NULL;
 691
 692                 if (chan->xact_pos == DWC2_HCSPLT_XACTPOS_ALL) {
 693                         if (chan->xfer_len <= 188)
 694                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_ALL;
 695                         else
 696                                 chan->xact_pos = DWC2_HCSPLT_XACTPOS_BEGIN;
 697                 }
 698                 break;
 699         }
 700
 701         return bufptr;
 702 }
 703
 704 static int dwc2_hc_setup_align_buf(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh,
 705                                    struct dwc2_host_chan *chan,
 706                                    struct dwc2_hcd_urb *urb, void *bufptr)
 707 {
 708         u32 buf_size;
 709         struct urb *usb_urb;
 710         struct usb_hcd *hcd;
 711
 712         if (!qh->dw_align_buf) {
 713                 if (chan->ep_type != USB_ENDPOINT_XFER_ISOC)
 714                         buf_size = hsotg->core_params->max_transfer_size;
 715                 else
 716                         /* 3072 = 3 max-size Isoc packets */
 717                         buf_size = 3072;
 718
 719                 qh->dw_align_buf = kmalloc(buf_size, GFP_ATOMIC | GFP_DMA);
 720                 if (!qh->dw_align_buf)
 721                         return -ENOMEM;
 722                 qh->dw_align_buf_size = buf_size;
 723         }
 724
 725         if (chan->xfer_len) {
 726                 dev_vdbg(hsotg->dev, "%s(): non-aligned buffer\n", __func__);
 727                 usb_urb = urb->priv;
 728
 729                 if (usb_urb) {
 730                         if (usb_urb->transfer_flags &
 731                             (URB_SETUP_MAP_SINGLE | URB_DMA_MAP_SG |
 732                              URB_DMA_MAP_PAGE | URB_DMA_MAP_SINGLE)) {
 733                                 hcd = dwc2_hsotg_to_hcd(hsotg);
 734                                 usb_hcd_unmap_urb_for_dma(hcd, usb_urb);
 735                         }
 736                         if (!chan->ep_is_in)
 737                                 memcpy(qh->dw_align_buf, bufptr,
 738                                        chan->xfer_len);
 739                 } else {
 740                         dev_warn(hsotg->dev, "no URB in dwc2_urb\n");
 741                 }
 742         }
 743
 744         qh->dw_align_buf_dma = dma_map_single(hsotg->dev,
 745                         qh->dw_align_buf, qh->dw_align_buf_size,
 746                         chan->ep_is_in ? DMA_FROM_DEVICE : DMA_TO_DEVICE);
 747         if (dma_mapping_error(hsotg->dev, qh->dw_align_buf_dma)) {
 748                 dev_err(hsotg->dev, "can't map align_buf\n");
 749                 chan->align_buf = 0;
 750                 return -EINVAL;
 751         }
 752
 753         chan->align_buf = qh->dw_align_buf_dma;
 754         return 0;
 755 }
 756
 757 /**
 758  * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
 759  * channel and initializes the host channel to perform the transactions. The
 760  * host channel is removed from the free list.
 761  *
 762  * @hsotg: The HCD state structure
 763  * @qh:    Transactions from the first QTD for this QH are selected and assigned
 764  *         to a free host channel
 765  */
 766 static int dwc2_assign_and_init_hc(struct dwc2_hsotg *hsotg, struct dwc2_qh *qh)
 767 {
 768         struct dwc2_host_chan *chan;
 769         struct dwc2_hcd_urb *urb;
 770         struct dwc2_qtd *qtd;
 771         void *bufptr = NULL;
 772
 773         if (dbg_qh(qh))
 774                 dev_vdbg(hsotg->dev, "%s(%p,%p)\n", __func__, hsotg, qh);
 775
 776         if (list_empty(&qh->qtd_list)) {
 777                 dev_dbg(hsotg->dev, "No QTDs in QH list\n");
 778                 return -ENOMEM;
 779         }
 780
 781         if (list_empty(&hsotg->free_hc_list)) {
 782                 dev_dbg(hsotg->dev, "No free channel to assign\n");
 783                 return -ENOMEM;
 784         }
 785
 786         chan = list_first_entry(&hsotg->free_hc_list, struct dwc2_host_chan,
 787                                 hc_list_entry);
 788
 789         /* Remove host channel from free list */
 790         list_del_init(&chan->hc_list_entry);
 791
 792         qtd = list_first_entry(&qh->qtd_list, struct dwc2_qtd, qtd_list_entry);
 793         urb = qtd->urb;
 794         qh->channel = chan;
 795         qtd->in_process = 1;
 796
 797         /*
 798          * Use usb_pipedevice to determine device address. This address is
 799          * 0 before the SET_ADDRESS command and the correct address afterward.
 800          */
 801         chan->dev_addr = dwc2_hcd_get_dev_addr(&urb->pipe_info);
 802         chan->ep_num = dwc2_hcd_get_ep_num(&urb->pipe_info);
 803         chan->speed = qh->dev_speed;
 804         chan->max_packet = dwc2_max_packet(qh->maxp);
 805
 806         chan->xfer_started = 0;
 807         chan->halt_status = DWC2_HC_XFER_NO_HALT_STATUS;
 808         chan->error_state = (qtd->error_count > 0);
 809         chan->halt_on_queue = 0;
 810         chan->halt_pending = 0;
 811         chan->requests = 0;
 812
 813         /*
 814          * The following values may be modified in the transfer type section
 815          * below. The xfer_len value may be reduced when the transfer is
 816          * started to accommodate the max widths of the XferSize and PktCnt
 817          * fields in the HCTSIZn register.
 818          */
 819
 820         chan->ep_is_in = (dwc2_hcd_is_pipe_in(&urb->pipe_info) != 0);
 821         if (chan->ep_is_in)
 822                 chan->do_ping = 0;
 823         else
 824                 chan->do_ping = qh->ping_state;
 825
 826         chan->data_pid_start = qh->data_toggle;
 827         chan->multi_count = 1;
 828
 829         if (urb->actual_length > urb->length &&
 830                 !dwc2_hcd_is_pipe_in(&urb->pipe_info))
 831                 urb->actual_length = urb->length;
 832
 833         if (hsotg->core_params->dma_enable > 0) {
 834                 chan->xfer_dma = urb->dma + urb->actual_length;
 835
 836                 /* For non-dword aligned case */
 837                 if (hsotg->core_params->dma_desc_enable <= 0 &&
 838                     (chan->xfer_dma & 0x3))
 839                         bufptr = (u8 *)urb->buf + urb->actual_length;
 840         } else {
 841                 chan->xfer_buf = (u8 *)urb->buf + urb->actual_length;
 842         }
 843
 844         chan->xfer_len = urb->length - urb->actual_length;
 845         chan->xfer_count = 0;
 846
 847         /* Set the split attributes if required */
 848         if (qh->do_split)
 849                 dwc2_hc_init_split(hsotg, chan, qtd, urb);
 850         else
 851                 chan->do_split = 0;
 852
 853         /* Set the transfer attributes */
 854         bufptr = dwc2_hc_init_xfer(hsotg, chan, qtd, bufptr);
 855
 856         /* Non DWORD-aligned buffer case */
 857         if (bufptr) {
 858                 dev_vdbg(hsotg->dev, "Non-aligned buffer\n");
 859                 if (dwc2_hc_setup_align_buf(hsotg, qh, chan, urb, bufptr)) {
 860                         dev_err(hsotg->dev,
 861                                 "%s: Failed to allocate memory to handle non-dword aligned buffer\n",
 862                                 __func__);
 863                         /* Add channel back to free list */
 864                         chan->align_buf = 0;
 865                         chan->multi_count = 0;
 866                         list_add_tail(&chan->hc_list_entry,
 867                                       &hsotg->free_hc_list);
 868                         qtd->in_process = 0;
 869                         qh->channel = NULL;
 870                         return -ENOMEM;
 871                 }
 872         } else {
 873                 chan->align_buf = 0;
 874         }
 875
 876         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
 877             chan->ep_type == USB_ENDPOINT_XFER_ISOC)
 878                 /*
 879                  * This value may be modified when the transfer is started
 880                  * to reflect the actual transfer length
 881                  */
 882                 chan->multi_count = dwc2_hb_mult(qh->maxp);
 883
 884         if (hsotg->core_params->dma_desc_enable > 0)
 885                 chan->desc_list_addr = qh->desc_list_dma;
 886
 887         dwc2_hc_init(hsotg, chan);
 888         chan->qh = qh;
 889
 890         return 0;
 891 }
 892
 893 /**
 894  * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
 895  * schedule and assigns them to available host channels. Called from the HCD
 896  * interrupt handler functions.
 897  *
 898  * @hsotg: The HCD state structure
 899  *
 900  * Return: The types of new transactions that were assigned to host channels
 901  */
 902 enum dwc2_transaction_type dwc2_hcd_select_transactions(
 903                 struct dwc2_hsotg *hsotg)
 904 {
 905         enum dwc2_transaction_type ret_val = DWC2_TRANSACTION_NONE;
 906         struct list_head *qh_ptr;
 907         struct dwc2_qh *qh;
 908         int num_channels;
 909
 910 #ifdef DWC2_DEBUG_SOF
 911         dev_vdbg(hsotg->dev, "  Select Transactions\n");
 912 #endif
 913
 914         /* Process entries in the periodic ready list */
 915         qh_ptr = hsotg->periodic_sched_ready.next;
 916         while (qh_ptr != &hsotg->periodic_sched_ready) {
 917                 if (list_empty(&hsotg->free_hc_list))
 918                         break;
 919                 if (hsotg->core_params->uframe_sched > 0) {
 920                         if (hsotg->available_host_channels <= 1)
 921                                 break;
 922                         hsotg->available_host_channels--;
 923                 }
 924                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 925                 if (dwc2_assign_and_init_hc(hsotg, qh))
 926                         break;
 927
 928                 /*
 929                  * Move the QH from the periodic ready schedule to the
 930                  * periodic assigned schedule
 931                  */
 932                 qh_ptr = qh_ptr->next;
 933                 list_move_tail(&qh->qh_list_entry,
 934                                &hsotg->periodic_sched_assigned);
 935                 ret_val = DWC2_TRANSACTION_PERIODIC;
 936         }
 937
 938         /*
 939          * Process entries in the inactive portion of the non-periodic
 940          * schedule. Some free host channels may not be used if they are
 941          * reserved for periodic transfers.
 942          */
 943         num_channels = hsotg->core_params->host_channels;
 944         qh_ptr = hsotg->non_periodic_sched_inactive.next;
 945         while (qh_ptr != &hsotg->non_periodic_sched_inactive) {
 946                 if (hsotg->core_params->uframe_sched <= 0 &&
 947                     hsotg->non_periodic_channels >= num_channels -
 948                                                 hsotg->periodic_channels)
 949                         break;
 950                 if (list_empty(&hsotg->free_hc_list))
 951                         break;
 952                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
 953                 if (hsotg->core_params->uframe_sched > 0) {
 954                         if (hsotg->available_host_channels < 1)
 955                                 break;
 956                         hsotg->available_host_channels--;
 957                 }
 958
 959                 if (dwc2_assign_and_init_hc(hsotg, qh))
 960                         break;
 961
 962                 /*
 963                  * Move the QH from the non-periodic inactive schedule to the
 964                  * non-periodic active schedule
 965                  */
 966                 qh_ptr = qh_ptr->next;
 967                 list_move_tail(&qh->qh_list_entry,
 968                                &hsotg->non_periodic_sched_active);
 969
 970                 if (ret_val == DWC2_TRANSACTION_NONE)
 971                         ret_val = DWC2_TRANSACTION_NON_PERIODIC;
 972                 else
 973                         ret_val = DWC2_TRANSACTION_ALL;
 974
 975                 if (hsotg->core_params->uframe_sched <= 0)
 976                         hsotg->non_periodic_channels++;
 977         }
 978
 979         return ret_val;
 980 }
 981
 982 /**
 983  * dwc2_queue_transaction() - Attempts to queue a single transaction request for
 984  * a host channel associated with either a periodic or non-periodic transfer
 985  *
 986  * @hsotg: The HCD state structure
 987  * @chan:  Host channel descriptor associated with either a periodic or
 988  *         non-periodic transfer
 989  * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
 990  *                     for periodic transfers or the non-periodic Tx FIFO
 991  *                     for non-periodic transfers
 992  *
 993  * Return: 1 if a request is queued and more requests may be needed to
 994  * complete the transfer, 0 if no more requests are required for this
 995  * transfer, -1 if there is insufficient space in the Tx FIFO
 996  *
 997  * This function assumes that there is space available in the appropriate
 998  * request queue. For an OUT transfer or SETUP transaction in Slave mode,
 999  * it checks whether space is available in the appropriate Tx FIFO.
1000  *
1001  * Must be called with interrupt disabled and spinlock held
1002  */
1003 static int dwc2_queue_transaction(struct dwc2_hsotg *hsotg,
1004                                   struct dwc2_host_chan *chan,
1005                                   u16 fifo_dwords_avail)
1006 {
1007         int retval = 0;
1008
1009         if (hsotg->core_params->dma_enable > 0) {
1010                 if (hsotg->core_params->dma_desc_enable > 0) {
1011                         if (!chan->xfer_started ||
1012                             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1013                                 dwc2_hcd_start_xfer_ddma(hsotg, chan->qh);
1014                                 chan->qh->ping_state = 0;
1015                         }
1016                 } else if (!chan->xfer_started) {
1017                         dwc2_hc_start_transfer(hsotg, chan);
1018                         chan->qh->ping_state = 0;
1019                 }
1020         } else if (chan->halt_pending) {
1021                 /* Don't queue a request if the channel has been halted */
1022         } else if (chan->halt_on_queue) {
1023                 dwc2_hc_halt(hsotg, chan, chan->halt_status);
1024         } else if (chan->do_ping) {
1025                 if (!chan->xfer_started)
1026                         dwc2_hc_start_transfer(hsotg, chan);
1027         } else if (!chan->ep_is_in ||
1028                    chan->data_pid_start == DWC2_HC_PID_SETUP) {
1029                 if ((fifo_dwords_avail * 4) >= chan->max_packet) {
1030                         if (!chan->xfer_started) {
1031                                 dwc2_hc_start_transfer(hsotg, chan);
1032                                 retval = 1;
1033                         } else {
1034                                 retval = dwc2_hc_continue_transfer(hsotg, chan);
1035                         }
1036                 } else {
1037                         retval = -1;
1038                 }
1039         } else {
1040                 if (!chan->xfer_started) {
1041                         dwc2_hc_start_transfer(hsotg, chan);
1042                         retval = 1;
1043                 } else {
1044                         retval = dwc2_hc_continue_transfer(hsotg, chan);
1045                 }
1046         }
1047
1048         return retval;
1049 }
1050
1051 /*
1052  * Processes periodic channels for the next frame and queues transactions for
1053  * these channels to the DWC_otg controller. After queueing transactions, the
1054  * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
1055  * to queue as Periodic Tx FIFO or request queue space becomes available.
1056  * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
1057  *
1058  * Must be called with interrupt disabled and spinlock held
1059  */
1060 static void dwc2_process_periodic_channels(struct dwc2_hsotg *hsotg)
1061 {
1062         struct list_head *qh_ptr;
1063         struct dwc2_qh *qh;
1064         u32 tx_status;
1065         u32 fspcavail;
1066         u32 gintmsk;
1067         int status;
1068         int no_queue_space = 0;
1069         int no_fifo_space = 0;
1070         u32 qspcavail;
1071
1072         if (dbg_perio())
1073                 dev_vdbg(hsotg->dev, "Queue periodic transactions\n");
1074
1075         tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1076         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1077                     TXSTS_QSPCAVAIL_SHIFT;
1078         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1079                     TXSTS_FSPCAVAIL_SHIFT;
1080
1081         if (dbg_perio()) {
1082                 dev_vdbg(hsotg->dev, "  P Tx Req Queue Space Avail (before queue): %d\n",
1083                          qspcavail);
1084                 dev_vdbg(hsotg->dev, "  P Tx FIFO Space Avail (before queue): %d\n",
1085                          fspcavail);
1086         }
1087
1088         qh_ptr = hsotg->periodic_sched_assigned.next;
1089         while (qh_ptr != &hsotg->periodic_sched_assigned) {
1090                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1091                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1092                             TXSTS_QSPCAVAIL_SHIFT;
1093                 if (qspcavail == 0) {
1094                         no_queue_space = 1;
1095                         break;
1096                 }
1097
1098                 qh = list_entry(qh_ptr, struct dwc2_qh, qh_list_entry);
1099                 if (!qh->channel) {
1100                         qh_ptr = qh_ptr->next;
1101                         continue;
1102                 }
1103
1104                 /* Make sure EP's TT buffer is clean before queueing qtds */
1105                 if (qh->tt_buffer_dirty) {
1106                         qh_ptr = qh_ptr->next;
1107                         continue;
1108                 }
1109
1110                 /*
1111                  * Set a flag if we're queuing high-bandwidth in slave mode.
1112                  * The flag prevents any halts to get into the request queue in
1113                  * the middle of multiple high-bandwidth packets getting queued.
1114                  */
1115                 if (hsotg->core_params->dma_enable <= 0 &&
1116                                 qh->channel->multi_count > 1)
1117                         hsotg->queuing_high_bandwidth = 1;
1118
1119                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1120                             TXSTS_FSPCAVAIL_SHIFT;
1121                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1122                 if (status < 0) {
1123                         no_fifo_space = 1;
1124                         break;
1125                 }
1126
1127                 /*
1128                  * In Slave mode, stay on the current transfer until there is
1129                  * nothing more to do or the high-bandwidth request count is
1130                  * reached. In DMA mode, only need to queue one request. The
1131                  * controller automatically handles multiple packets for
1132                  * high-bandwidth transfers.
1133                  */
1134                 if (hsotg->core_params->dma_enable > 0 || status == 0 ||
1135                     qh->channel->requests == qh->channel->multi_count) {
1136                         qh_ptr = qh_ptr->next;
1137                         /*
1138                          * Move the QH from the periodic assigned schedule to
1139                          * the periodic queued schedule
1140                          */
1141                         list_move_tail(&qh->qh_list_entry,
1142                                        &hsotg->periodic_sched_queued);
1143
1144                         /* done queuing high bandwidth */
1145                         hsotg->queuing_high_bandwidth = 0;
1146                 }
1147         }
1148
1149         if (hsotg->core_params->dma_enable <= 0) {
1150                 tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
1151                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1152                             TXSTS_QSPCAVAIL_SHIFT;
1153                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1154                             TXSTS_FSPCAVAIL_SHIFT;
1155                 if (dbg_perio()) {
1156                         dev_vdbg(hsotg->dev,
1157                                  "  P Tx Req Queue Space Avail (after queue): %d\n",
1158                                  qspcavail);
1159                         dev_vdbg(hsotg->dev,
1160                                  "  P Tx FIFO Space Avail (after queue): %d\n",
1161                                  fspcavail);
1162                 }
1163
1164                 if (!list_empty(&hsotg->periodic_sched_assigned) ||
1165                     no_queue_space || no_fifo_space) {
1166                         /*
1167                          * May need to queue more transactions as the request
1168                          * queue or Tx FIFO empties. Enable the periodic Tx
1169                          * FIFO empty interrupt. (Always use the half-empty
1170                          * level to ensure that new requests are loaded as
1171                          * soon as possible.)
1172                          */
1173                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1174                         gintmsk |= GINTSTS_PTXFEMP;
1175                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1176                 } else {
1177                         /*
1178                          * Disable the Tx FIFO empty interrupt since there are
1179                          * no more transactions that need to be queued right
1180                          * now. This function is called from interrupt
1181                          * handlers to queue more transactions as transfer
1182                          * states change.
1183                          */
1184                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1185                         gintmsk &= ~GINTSTS_PTXFEMP;
1186                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1187                 }
1188         }
1189 }
1190
1191 /*
1192  * Processes active non-periodic channels and queues transactions for these
1193  * channels to the DWC_otg controller. After queueing transactions, the NP Tx
1194  * FIFO Empty interrupt is enabled if there are more transactions to queue as
1195  * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
1196  * FIFO Empty interrupt is disabled.
1197  *
1198  * Must be called with interrupt disabled and spinlock held
1199  */
1200 static void dwc2_process_non_periodic_channels(struct dwc2_hsotg *hsotg)
1201 {
1202         struct list_head *orig_qh_ptr;
1203         struct dwc2_qh *qh;
1204         u32 tx_status;
1205         u32 qspcavail;
1206         u32 fspcavail;
1207         u32 gintmsk;
1208         int status;
1209         int no_queue_space = 0;
1210         int no_fifo_space = 0;
1211         int more_to_do = 0;
1212
1213         dev_vdbg(hsotg->dev, "Queue non-periodic transactions\n");
1214
1215         tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1216         qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1217                     TXSTS_QSPCAVAIL_SHIFT;
1218         fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1219                     TXSTS_FSPCAVAIL_SHIFT;
1220         dev_vdbg(hsotg->dev, "  NP Tx Req Queue Space Avail (before queue): %d\n",
1221                  qspcavail);
1222         dev_vdbg(hsotg->dev, "  NP Tx FIFO Space Avail (before queue): %d\n",
1223                  fspcavail);
1224
1225         /*
1226          * Keep track of the starting point. Skip over the start-of-list
1227          * entry.
1228          */
1229         if (hsotg->non_periodic_qh_ptr == &hsotg->non_periodic_sched_active)
1230                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1231         orig_qh_ptr = hsotg->non_periodic_qh_ptr;
1232
1233         /*
1234          * Process once through the active list or until no more space is
1235          * available in the request queue or the Tx FIFO
1236          */
1237         do {
1238                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1239                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1240                             TXSTS_QSPCAVAIL_SHIFT;
1241                 if (hsotg->core_params->dma_enable <= 0 && qspcavail == 0) {
1242                         no_queue_space = 1;
1243                         break;
1244                 }
1245
1246                 qh = list_entry(hsotg->non_periodic_qh_ptr, struct dwc2_qh,
1247                                 qh_list_entry);
1248                 if (!qh->channel)
1249                         goto next;
1250
1251                 /* Make sure EP's TT buffer is clean before queueing qtds */
1252                 if (qh->tt_buffer_dirty)
1253                         goto next;
1254
1255                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1256                             TXSTS_FSPCAVAIL_SHIFT;
1257                 status = dwc2_queue_transaction(hsotg, qh->channel, fspcavail);
1258
1259                 if (status > 0) {
1260                         more_to_do = 1;
1261                 } else if (status < 0) {
1262                         no_fifo_space = 1;
1263                         break;
1264                 }
1265 next:
1266                 /* Advance to next QH, skipping start-of-list entry */
1267                 hsotg->non_periodic_qh_ptr = hsotg->non_periodic_qh_ptr->next;
1268                 if (hsotg->non_periodic_qh_ptr ==
1269                                 &hsotg->non_periodic_sched_active)
1270                         hsotg->non_periodic_qh_ptr =
1271                                         hsotg->non_periodic_qh_ptr->next;
1272         } while (hsotg->non_periodic_qh_ptr != orig_qh_ptr);
1273
1274         if (hsotg->core_params->dma_enable <= 0) {
1275                 tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
1276                 qspcavail = (tx_status & TXSTS_QSPCAVAIL_MASK) >>
1277                             TXSTS_QSPCAVAIL_SHIFT;
1278                 fspcavail = (tx_status & TXSTS_FSPCAVAIL_MASK) >>
1279                             TXSTS_FSPCAVAIL_SHIFT;
1280                 dev_vdbg(hsotg->dev,
1281                          "  NP Tx Req Queue Space Avail (after queue): %d\n",
1282                          qspcavail);
1283                 dev_vdbg(hsotg->dev,
1284                          "  NP Tx FIFO Space Avail (after queue): %d\n",
1285                          fspcavail);
1286
1287                 if (more_to_do || no_queue_space || no_fifo_space) {
1288                         /*
1289                          * May need to queue more transactions as the request
1290                          * queue or Tx FIFO empties. Enable the non-periodic
1291                          * Tx FIFO empty interrupt. (Always use the half-empty
1292                          * level to ensure that new requests are loaded as
1293                          * soon as possible.)
1294                          */
1295                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1296                         gintmsk |= GINTSTS_NPTXFEMP;
1297                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1298                 } else {
1299                         /*
1300                          * Disable the Tx FIFO empty interrupt since there are
1301                          * no more transactions that need to be queued right
1302                          * now. This function is called from interrupt
1303                          * handlers to queue more transactions as transfer
1304                          * states change.
1305                          */
1306                         gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1307                         gintmsk &= ~GINTSTS_NPTXFEMP;
1308                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1309                 }
1310         }
1311 }
1312
1313 /**
1314  * dwc2_hcd_queue_transactions() - Processes the currently active host channels
1315  * and queues transactions for these channels to the DWC_otg controller. Called
1316  * from the HCD interrupt handler functions.
1317  *
1318  * @hsotg:   The HCD state structure
1319  * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
1320  *           or both)
1321  *
1322  * Must be called with interrupt disabled and spinlock held
1323  */
1324 void dwc2_hcd_queue_transactions(struct dwc2_hsotg *hsotg,
1325                                  enum dwc2_transaction_type tr_type)
1326 {
1327 #ifdef DWC2_DEBUG_SOF
1328         dev_vdbg(hsotg->dev, "Queue Transactions\n");
1329 #endif
1330         /* Process host channels associated with periodic transfers */
1331         if ((tr_type == DWC2_TRANSACTION_PERIODIC ||
1332              tr_type == DWC2_TRANSACTION_ALL) &&
1333             !list_empty(&hsotg->periodic_sched_assigned))
1334                 dwc2_process_periodic_channels(hsotg);
1335
1336         /* Process host channels associated with non-periodic transfers */
1337         if (tr_type == DWC2_TRANSACTION_NON_PERIODIC ||
1338             tr_type == DWC2_TRANSACTION_ALL) {
1339                 if (!list_empty(&hsotg->non_periodic_sched_active)) {
1340                         dwc2_process_non_periodic_channels(hsotg);
1341                 } else {
1342                         /*
1343                          * Ensure NP Tx FIFO empty interrupt is disabled when
1344                          * there are no non-periodic transfers to process
1345                          */
1346                         u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
1347
1348                         gintmsk &= ~GINTSTS_NPTXFEMP;
1349                         dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
1350                 }
1351         }
1352 }
1353
1354 static void dwc2_conn_id_status_change(struct work_struct *work)
1355 {
1356         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
1357                                                 wf_otg);
1358         u32 count = 0;
1359         u32 gotgctl;
1360         unsigned long flags;
1361
1362         dev_dbg(hsotg->dev, "%s()\n", __func__);
1363
1364         gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1365         dev_dbg(hsotg->dev, "gotgctl=%0x\n", gotgctl);
1366         dev_dbg(hsotg->dev, "gotgctl.b.conidsts=%d\n",
1367                 !!(gotgctl & GOTGCTL_CONID_B));
1368
1369         /* B-Device connector (Device Mode) */
1370         if (gotgctl & GOTGCTL_CONID_B) {
1371                 /* Wait for switch to device mode */
1372                 dev_dbg(hsotg->dev, "connId B\n");
1373                 while (!dwc2_is_device_mode(hsotg)) {
1374                         dev_info(hsotg->dev,
1375                                  "Waiting for Peripheral Mode, Mode=%s\n",
1376                                  dwc2_is_host_mode(hsotg) ? "Host" :
1377                                  "Peripheral");
1378                         usleep_range(20000, 40000);
1379                         if (++count > 250)
1380                                 break;
1381                 }
1382                 if (count > 250)
1383                         dev_err(hsotg->dev,
1384                                 "Connection id status change timed out\n");
1385                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
1386                 dwc2_core_init(hsotg, false);
1387                 dwc2_enable_global_interrupts(hsotg);
1388                 spin_lock_irqsave(&hsotg->lock, flags);
1389                 dwc2_hsotg_core_init_disconnected(hsotg, false);
1390                 spin_unlock_irqrestore(&hsotg->lock, flags);
1391                 dwc2_hsotg_core_connect(hsotg);
1392         } else {
1393                 /* A-Device connector (Host Mode) */
1394                 dev_dbg(hsotg->dev, "connId A\n");
1395                 while (!dwc2_is_host_mode(hsotg)) {
1396                         dev_info(hsotg->dev, "Waiting for Host Mode, Mode=%s\n",
1397                                  dwc2_is_host_mode(hsotg) ?
1398                                  "Host" : "Peripheral");
1399                         usleep_range(20000, 40000);
1400                         if (++count > 250)
1401                                 break;
1402                 }
1403                 if (count > 250)
1404                         dev_err(hsotg->dev,
1405                                 "Connection id status change timed out\n");
1406                 hsotg->op_state = OTG_STATE_A_HOST;
1407
1408                 /* Initialize the Core for Host mode */
1409                 dwc2_core_init(hsotg, false);
1410                 dwc2_enable_global_interrupts(hsotg);
1411                 dwc2_hcd_start(hsotg);
1412         }
1413 }
1414
1415 static void dwc2_wakeup_detected(unsigned long data)
1416 {
1417         struct dwc2_hsotg *hsotg = (struct dwc2_hsotg *)data;
1418         u32 hprt0;
1419
1420         dev_dbg(hsotg->dev, "%s()\n", __func__);
1421
1422         /*
1423          * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
1424          * so that OPT tests pass with all PHYs.)
1425          */
1426         hprt0 = dwc2_read_hprt0(hsotg);
1427         dev_dbg(hsotg->dev, "Resume: HPRT0=%0x\n", hprt0);
1428         hprt0 &= ~HPRT0_RES;
1429         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1430         dev_dbg(hsotg->dev, "Clear Resume: HPRT0=%0x\n",
1431                 dwc2_readl(hsotg->regs + HPRT0));
1432
1433         dwc2_hcd_rem_wakeup(hsotg);
1434         hsotg->bus_suspended = 0;
1435
1436         /* Change to L0 state */
1437         hsotg->lx_state = DWC2_L0;
1438 }
1439
1440 static int dwc2_host_is_b_hnp_enabled(struct dwc2_hsotg *hsotg)
1441 {
1442         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
1443
1444         return hcd->self.b_hnp_enable;
1445 }
1446
1447 /* Must NOT be called with interrupt disabled or spinlock held */
1448 static void dwc2_port_suspend(struct dwc2_hsotg *hsotg, u16 windex)
1449 {
1450         unsigned long flags;
1451         u32 hprt0;
1452         u32 pcgctl;
1453         u32 gotgctl;
1454
1455         dev_dbg(hsotg->dev, "%s()\n", __func__);
1456
1457         spin_lock_irqsave(&hsotg->lock, flags);
1458
1459         if (windex == hsotg->otg_port && dwc2_host_is_b_hnp_enabled(hsotg)) {
1460                 gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1461                 gotgctl |= GOTGCTL_HSTSETHNPEN;
1462                 dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
1463                 hsotg->op_state = OTG_STATE_A_SUSPEND;
1464         }
1465
1466         hprt0 = dwc2_read_hprt0(hsotg);
1467         hprt0 |= HPRT0_SUSP;
1468         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1469
1470         hsotg->bus_suspended = 1;
1471
1472         /*
1473          * If hibernation is supported, Phy clock will be suspended
1474          * after registers are backuped.
1475          */
1476         if (!hsotg->core_params->hibernation) {
1477                 /* Suspend the Phy Clock */
1478                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1479                 pcgctl |= PCGCTL_STOPPCLK;
1480                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1481                 udelay(10);
1482         }
1483
1484         /* For HNP the bus must be suspended for at least 200ms */
1485         if (dwc2_host_is_b_hnp_enabled(hsotg)) {
1486                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1487                 pcgctl &= ~PCGCTL_STOPPCLK;
1488                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1489
1490                 spin_unlock_irqrestore(&hsotg->lock, flags);
1491
1492                 usleep_range(200000, 250000);
1493         } else {
1494                 spin_unlock_irqrestore(&hsotg->lock, flags);
1495         }
1496 }
1497
1498 /* Must NOT be called with interrupt disabled or spinlock held */
1499 static void dwc2_port_resume(struct dwc2_hsotg *hsotg)
1500 {
1501         unsigned long flags;
1502         u32 hprt0;
1503         u32 pcgctl;
1504
1505         spin_lock_irqsave(&hsotg->lock, flags);
1506
1507         /*
1508          * If hibernation is supported, Phy clock is already resumed
1509          * after registers restore.
1510          */
1511         if (!hsotg->core_params->hibernation) {
1512                 pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1513                 pcgctl &= ~PCGCTL_STOPPCLK;
1514                 dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1515                 spin_unlock_irqrestore(&hsotg->lock, flags);
1516                 usleep_range(20000, 40000);
1517                 spin_lock_irqsave(&hsotg->lock, flags);
1518         }
1519
1520         hprt0 = dwc2_read_hprt0(hsotg);
1521         hprt0 |= HPRT0_RES;
1522         hprt0 &= ~HPRT0_SUSP;
1523         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1524         spin_unlock_irqrestore(&hsotg->lock, flags);
1525
1526         msleep(USB_RESUME_TIMEOUT);
1527
1528         spin_lock_irqsave(&hsotg->lock, flags);
1529         hprt0 = dwc2_read_hprt0(hsotg);
1530         hprt0 &= ~(HPRT0_RES | HPRT0_SUSP);
1531         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1532         hsotg->bus_suspended = 0;
1533         spin_unlock_irqrestore(&hsotg->lock, flags);
1534 }
1535
1536 /* Handles hub class-specific requests */
1537 static int dwc2_hcd_hub_control(struct dwc2_hsotg *hsotg, u16 typereq,
1538                                 u16 wvalue, u16 windex, char *buf, u16 wlength)
1539 {
1540         struct usb_hub_descriptor *hub_desc;
1541         int retval = 0;
1542         u32 hprt0;
1543         u32 port_status;
1544         u32 speed;
1545         u32 pcgctl;
1546
1547         switch (typereq) {
1548         case ClearHubFeature:
1549                 dev_dbg(hsotg->dev, "ClearHubFeature %1xh\n", wvalue);
1550
1551                 switch (wvalue) {
1552                 case C_HUB_LOCAL_POWER:
1553                 case C_HUB_OVER_CURRENT:
1554                         /* Nothing required here */
1555                         break;
1556
1557                 default:
1558                         retval = -EINVAL;
1559                         dev_err(hsotg->dev,
1560                                 "ClearHubFeature request %1xh unknown\n",
1561                                 wvalue);
1562                 }
1563                 break;
1564
1565         case ClearPortFeature:
1566                 if (wvalue != USB_PORT_FEAT_L1)
1567                         if (!windex || windex > 1)
1568                                 goto error;
1569                 switch (wvalue) {
1570                 case USB_PORT_FEAT_ENABLE:
1571                         dev_dbg(hsotg->dev,
1572                                 "ClearPortFeature USB_PORT_FEAT_ENABLE\n");
1573                         hprt0 = dwc2_read_hprt0(hsotg);
1574                         hprt0 |= HPRT0_ENA;
1575                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1576                         break;
1577
1578                 case USB_PORT_FEAT_SUSPEND:
1579                         dev_dbg(hsotg->dev,
1580                                 "ClearPortFeature USB_PORT_FEAT_SUSPEND\n");
1581
1582                         if (hsotg->bus_suspended)
1583                                 dwc2_port_resume(hsotg);
1584                         break;
1585
1586                 case USB_PORT_FEAT_POWER:
1587                         dev_dbg(hsotg->dev,
1588                                 "ClearPortFeature USB_PORT_FEAT_POWER\n");
1589                         hprt0 = dwc2_read_hprt0(hsotg);
1590                         hprt0 &= ~HPRT0_PWR;
1591                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1592                         break;
1593
1594                 case USB_PORT_FEAT_INDICATOR:
1595                         dev_dbg(hsotg->dev,
1596                                 "ClearPortFeature USB_PORT_FEAT_INDICATOR\n");
1597                         /* Port indicator not supported */
1598                         break;
1599
1600                 case USB_PORT_FEAT_C_CONNECTION:
1601                         /*
1602                          * Clears driver's internal Connect Status Change flag
1603                          */
1604                         dev_dbg(hsotg->dev,
1605                                 "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n");
1606                         hsotg->flags.b.port_connect_status_change = 0;
1607                         break;
1608
1609                 case USB_PORT_FEAT_C_RESET:
1610                         /* Clears driver's internal Port Reset Change flag */
1611                         dev_dbg(hsotg->dev,
1612                                 "ClearPortFeature USB_PORT_FEAT_C_RESET\n");
1613                         hsotg->flags.b.port_reset_change = 0;
1614                         break;
1615
1616                 case USB_PORT_FEAT_C_ENABLE:
1617                         /*
1618                          * Clears the driver's internal Port Enable/Disable
1619                          * Change flag
1620                          */
1621                         dev_dbg(hsotg->dev,
1622                                 "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n");
1623                         hsotg->flags.b.port_enable_change = 0;
1624                         break;
1625
1626                 case USB_PORT_FEAT_C_SUSPEND:
1627                         /*
1628                          * Clears the driver's internal Port Suspend Change
1629                          * flag, which is set when resume signaling on the host
1630                          * port is complete
1631                          */
1632                         dev_dbg(hsotg->dev,
1633                                 "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n");
1634                         hsotg->flags.b.port_suspend_change = 0;
1635                         break;
1636
1637                 case USB_PORT_FEAT_C_PORT_L1:
1638                         dev_dbg(hsotg->dev,
1639                                 "ClearPortFeature USB_PORT_FEAT_C_PORT_L1\n");
1640                         hsotg->flags.b.port_l1_change = 0;
1641                         break;
1642
1643                 case USB_PORT_FEAT_C_OVER_CURRENT:
1644                         dev_dbg(hsotg->dev,
1645                                 "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n");
1646                         hsotg->flags.b.port_over_current_change = 0;
1647                         break;
1648
1649                 default:
1650                         retval = -EINVAL;
1651                         dev_err(hsotg->dev,
1652                                 "ClearPortFeature request %1xh unknown or unsupported\n",
1653                                 wvalue);
1654                 }
1655                 break;
1656
1657         case GetHubDescriptor:
1658                 dev_dbg(hsotg->dev, "GetHubDescriptor\n");
1659                 hub_desc = (struct usb_hub_descriptor *)buf;
1660                 hub_desc->bDescLength = 9;
1661                 hub_desc->bDescriptorType = USB_DT_HUB;
1662                 hub_desc->bNbrPorts = 1;
1663                 hub_desc->wHubCharacteristics =
1664                         cpu_to_le16(HUB_CHAR_COMMON_LPSM |
1665                                     HUB_CHAR_INDV_PORT_OCPM);
1666                 hub_desc->bPwrOn2PwrGood = 1;
1667                 hub_desc->bHubContrCurrent = 0;
1668                 hub_desc->u.hs.DeviceRemovable[0] = 0;
1669                 hub_desc->u.hs.DeviceRemovable[1] = 0xff;
1670                 break;
1671
1672         case GetHubStatus:
1673                 dev_dbg(hsotg->dev, "GetHubStatus\n");
1674                 memset(buf, 0, 4);
1675                 break;
1676
1677         case GetPortStatus:
1678                 dev_vdbg(hsotg->dev,
1679                          "GetPortStatus wIndex=0x%04x flags=0x%08x\n", windex,
1680                          hsotg->flags.d32);
1681                 if (!windex || windex > 1)
1682                         goto error;
1683
1684                 port_status = 0;
1685                 if (hsotg->flags.b.port_connect_status_change)
1686                         port_status |= USB_PORT_STAT_C_CONNECTION << 16;
1687                 if (hsotg->flags.b.port_enable_change)
1688                         port_status |= USB_PORT_STAT_C_ENABLE << 16;
1689                 if (hsotg->flags.b.port_suspend_change)
1690                         port_status |= USB_PORT_STAT_C_SUSPEND << 16;
1691                 if (hsotg->flags.b.port_l1_change)
1692                         port_status |= USB_PORT_STAT_C_L1 << 16;
1693                 if (hsotg->flags.b.port_reset_change)
1694                         port_status |= USB_PORT_STAT_C_RESET << 16;
1695                 if (hsotg->flags.b.port_over_current_change) {
1696                         dev_warn(hsotg->dev, "Overcurrent change detected\n");
1697                         port_status |= USB_PORT_STAT_C_OVERCURRENT << 16;
1698                 }
1699
1700                 if (!hsotg->flags.b.port_connect_status) {
1701                         /*
1702                          * The port is disconnected, which means the core is
1703                          * either in device mode or it soon will be. Just
1704                          * return 0's for the remainder of the port status
1705                          * since the port register can't be read if the core
1706                          * is in device mode.
1707                          */
1708                         *(__le32 *)buf = cpu_to_le32(port_status);
1709                         break;
1710                 }
1711
1712                 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
1713                 dev_vdbg(hsotg->dev, "  HPRT0: 0x%08x\n", hprt0);
1714
1715                 if (hprt0 & HPRT0_CONNSTS)
1716                         port_status |= USB_PORT_STAT_CONNECTION;
1717                 if (hprt0 & HPRT0_ENA)
1718                         port_status |= USB_PORT_STAT_ENABLE;
1719                 if (hprt0 & HPRT0_SUSP)
1720                         port_status |= USB_PORT_STAT_SUSPEND;
1721                 if (hprt0 & HPRT0_OVRCURRACT)
1722                         port_status |= USB_PORT_STAT_OVERCURRENT;
1723                 if (hprt0 & HPRT0_RST)
1724                         port_status |= USB_PORT_STAT_RESET;
1725                 if (hprt0 & HPRT0_PWR)
1726                         port_status |= USB_PORT_STAT_POWER;
1727
1728                 speed = (hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT;
1729                 if (speed == HPRT0_SPD_HIGH_SPEED)
1730                         port_status |= USB_PORT_STAT_HIGH_SPEED;
1731                 else if (speed == HPRT0_SPD_LOW_SPEED)
1732                         port_status |= USB_PORT_STAT_LOW_SPEED;
1733
1734                 if (hprt0 & HPRT0_TSTCTL_MASK)
1735                         port_status |= USB_PORT_STAT_TEST;
1736                 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
1737
1738                 dev_vdbg(hsotg->dev, "port_status=%08x\n", port_status);
1739                 *(__le32 *)buf = cpu_to_le32(port_status);
1740                 break;
1741
1742         case SetHubFeature:
1743                 dev_dbg(hsotg->dev, "SetHubFeature\n");
1744                 /* No HUB features supported */
1745                 break;
1746
1747         case SetPortFeature:
1748                 dev_dbg(hsotg->dev, "SetPortFeature\n");
1749                 if (wvalue != USB_PORT_FEAT_TEST && (!windex || windex > 1))
1750                         goto error;
1751
1752                 if (!hsotg->flags.b.port_connect_status) {
1753                         /*
1754                          * The port is disconnected, which means the core is
1755                          * either in device mode or it soon will be. Just
1756                          * return without doing anything since the port
1757                          * register can't be written if the core is in device
1758                          * mode.
1759                          */
1760                         break;
1761                 }
1762
1763                 switch (wvalue) {
1764                 case USB_PORT_FEAT_SUSPEND:
1765                         dev_dbg(hsotg->dev,
1766                                 "SetPortFeature - USB_PORT_FEAT_SUSPEND\n");
1767                         if (windex != hsotg->otg_port)
1768                                 goto error;
1769                         dwc2_port_suspend(hsotg, windex);
1770                         break;
1771
1772                 case USB_PORT_FEAT_POWER:
1773                         dev_dbg(hsotg->dev,
1774                                 "SetPortFeature - USB_PORT_FEAT_POWER\n");
1775                         hprt0 = dwc2_read_hprt0(hsotg);
1776                         hprt0 |= HPRT0_PWR;
1777                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1778                         break;
1779
1780                 case USB_PORT_FEAT_RESET:
1781                         hprt0 = dwc2_read_hprt0(hsotg);
1782                         dev_dbg(hsotg->dev,
1783                                 "SetPortFeature - USB_PORT_FEAT_RESET\n");
1784                         pcgctl = dwc2_readl(hsotg->regs + PCGCTL);
1785                         pcgctl &= ~(PCGCTL_ENBL_SLEEP_GATING | PCGCTL_STOPPCLK);
1786                         dwc2_writel(pcgctl, hsotg->regs + PCGCTL);
1787                         /* ??? Original driver does this */
1788                         dwc2_writel(0, hsotg->regs + PCGCTL);
1789
1790                         hprt0 = dwc2_read_hprt0(hsotg);
1791                         /* Clear suspend bit if resetting from suspend state */
1792                         hprt0 &= ~HPRT0_SUSP;
1793
1794                         /*
1795                          * When B-Host the Port reset bit is set in the Start
1796                          * HCD Callback function, so that the reset is started
1797                          * within 1ms of the HNP success interrupt
1798                          */
1799                         if (!dwc2_hcd_is_b_host(hsotg)) {
1800                                 hprt0 |= HPRT0_PWR | HPRT0_RST;
1801                                 dev_dbg(hsotg->dev,
1802                                         "In host mode, hprt0=%08x\n", hprt0);
1803                                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
1804                         }
1805
1806                         /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
1807                         usleep_range(50000, 70000);
1808                         hprt0 &= ~HPRT0_RST;
1809                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1810                         hsotg->lx_state = DWC2_L0; /* Now back to On state */
1811                         break;
1812
1813                 case USB_PORT_FEAT_INDICATOR:
1814                         dev_dbg(hsotg->dev,
1815                                 "SetPortFeature - USB_PORT_FEAT_INDICATOR\n");
1816                         /* Not supported */
1817                         break;
1818
1819                 case USB_PORT_FEAT_TEST:
1820                         hprt0 = dwc2_read_hprt0(hsotg);
1821                         dev_dbg(hsotg->dev,
1822                                 "SetPortFeature - USB_PORT_FEAT_TEST\n");
1823                         hprt0 &= ~HPRT0_TSTCTL_MASK;
1824                         hprt0 |= (windex >> 8) << HPRT0_TSTCTL_SHIFT;
1825                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1826                         break;
1827
1828                 default:
1829                         retval = -EINVAL;
1830                         dev_err(hsotg->dev,
1831                                 "SetPortFeature %1xh unknown or unsupported\n",
1832                                 wvalue);
1833                         break;
1834                 }
1835                 break;
1836
1837         default:
1838 error:
1839                 retval = -EINVAL;
1840                 dev_dbg(hsotg->dev,
1841                         "Unknown hub control request: %1xh wIndex: %1xh wValue: %1xh\n",
1842                         typereq, windex, wvalue);
1843                 break;
1844         }
1845
1846         return retval;
1847 }
1848
1849 static int dwc2_hcd_is_status_changed(struct dwc2_hsotg *hsotg, int port)
1850 {
1851         int retval;
1852
1853         if (port != 1)
1854                 return -EINVAL;
1855
1856         retval = (hsotg->flags.b.port_connect_status_change ||
1857                   hsotg->flags.b.port_reset_change ||
1858                   hsotg->flags.b.port_enable_change ||
1859                   hsotg->flags.b.port_suspend_change ||
1860                   hsotg->flags.b.port_over_current_change);
1861
1862         if (retval) {
1863                 dev_dbg(hsotg->dev,
1864                         "DWC OTG HCD HUB STATUS DATA: Root port status changed\n");
1865                 dev_dbg(hsotg->dev, "  port_connect_status_change: %d\n",
1866                         hsotg->flags.b.port_connect_status_change);
1867                 dev_dbg(hsotg->dev, "  port_reset_change: %d\n",
1868                         hsotg->flags.b.port_reset_change);
1869                 dev_dbg(hsotg->dev, "  port_enable_change: %d\n",
1870                         hsotg->flags.b.port_enable_change);
1871                 dev_dbg(hsotg->dev, "  port_suspend_change: %d\n",
1872                         hsotg->flags.b.port_suspend_change);
1873                 dev_dbg(hsotg->dev, "  port_over_current_change: %d\n",
1874                         hsotg->flags.b.port_over_current_change);
1875         }
1876
1877         return retval;
1878 }
1879
1880 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1881 {
1882         u32 hfnum = dwc2_readl(hsotg->regs + HFNUM);
1883
1884 #ifdef DWC2_DEBUG_SOF
1885         dev_vdbg(hsotg->dev, "DWC OTG HCD GET FRAME NUMBER %d\n",
1886                  (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT);
1887 #endif
1888         return (hfnum & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
1889 }
1890
1891 int dwc2_hcd_is_b_host(struct dwc2_hsotg *hsotg)
1892 {
1893         return hsotg->op_state == OTG_STATE_B_HOST;
1894 }
1895
1896 static struct dwc2_hcd_urb *dwc2_hcd_urb_alloc(struct dwc2_hsotg *hsotg,
1897                                                int iso_desc_count,
1898                                                gfp_t mem_flags)
1899 {
1900         struct dwc2_hcd_urb *urb;
1901         u32 size = sizeof(*urb) + iso_desc_count *
1902                    sizeof(struct dwc2_hcd_iso_packet_desc);
1903
1904         urb = kzalloc(size, mem_flags);
1905         if (urb)
1906                 urb->packet_count = iso_desc_count;
1907         return urb;
1908 }
1909
1910 static void dwc2_hcd_urb_set_pipeinfo(struct dwc2_hsotg *hsotg,
1911                                       struct dwc2_hcd_urb *urb, u8 dev_addr,
1912                                       u8 ep_num, u8 ep_type, u8 ep_dir, u16 mps)
1913 {
1914         if (dbg_perio() ||
1915             ep_type == USB_ENDPOINT_XFER_BULK ||
1916             ep_type == USB_ENDPOINT_XFER_CONTROL)
1917                 dev_vdbg(hsotg->dev,
1918                          "addr=%d, ep_num=%d, ep_dir=%1x, ep_type=%1x, mps=%d\n",
1919                          dev_addr, ep_num, ep_dir, ep_type, mps);
1920         urb->pipe_info.dev_addr = dev_addr;
1921         urb->pipe_info.ep_num = ep_num;
1922         urb->pipe_info.pipe_type = ep_type;
1923         urb->pipe_info.pipe_dir = ep_dir;
1924         urb->pipe_info.mps = mps;
1925 }
1926
1927 /*
1928  * NOTE: This function will be removed once the peripheral controller code
1929  * is integrated and the driver is stable
1930  */
1931 void dwc2_hcd_dump_state(struct dwc2_hsotg *hsotg)
1932 {
1933 #ifdef DEBUG
1934         struct dwc2_host_chan *chan;
1935         struct dwc2_hcd_urb *urb;
1936         struct dwc2_qtd *qtd;
1937         int num_channels;
1938         u32 np_tx_status;
1939         u32 p_tx_status;
1940         int i;
1941
1942         num_channels = hsotg->core_params->host_channels;
1943         dev_dbg(hsotg->dev, "\n");
1944         dev_dbg(hsotg->dev,
1945                 "************************************************************\n");
1946         dev_dbg(hsotg->dev, "HCD State:\n");
1947         dev_dbg(hsotg->dev, "  Num channels: %d\n", num_channels);
1948
1949         for (i = 0; i < num_channels; i++) {
1950                 chan = hsotg->hc_ptr_array[i];
1951                 dev_dbg(hsotg->dev, "  Channel %d:\n", i);
1952                 dev_dbg(hsotg->dev,
1953                         "    dev_addr: %d, ep_num: %d, ep_is_in: %d\n",
1954                         chan->dev_addr, chan->ep_num, chan->ep_is_in);
1955                 dev_dbg(hsotg->dev, "    speed: %d\n", chan->speed);
1956                 dev_dbg(hsotg->dev, "    ep_type: %d\n", chan->ep_type);
1957                 dev_dbg(hsotg->dev, "    max_packet: %d\n", chan->max_packet);
1958                 dev_dbg(hsotg->dev, "    data_pid_start: %d\n",
1959                         chan->data_pid_start);
1960                 dev_dbg(hsotg->dev, "    multi_count: %d\n", chan->multi_count);
1961                 dev_dbg(hsotg->dev, "    xfer_started: %d\n",
1962                         chan->xfer_started);
1963                 dev_dbg(hsotg->dev, "    xfer_buf: %p\n", chan->xfer_buf);
1964                 dev_dbg(hsotg->dev, "    xfer_dma: %08lx\n",
1965                         (unsigned long)chan->xfer_dma);
1966                 dev_dbg(hsotg->dev, "    xfer_len: %d\n", chan->xfer_len);
1967                 dev_dbg(hsotg->dev, "    xfer_count: %d\n", chan->xfer_count);
1968                 dev_dbg(hsotg->dev, "    halt_on_queue: %d\n",
1969                         chan->halt_on_queue);
1970                 dev_dbg(hsotg->dev, "    halt_pending: %d\n",
1971                         chan->halt_pending);
1972                 dev_dbg(hsotg->dev, "    halt_status: %d\n", chan->halt_status);
1973                 dev_dbg(hsotg->dev, "    do_split: %d\n", chan->do_split);
1974                 dev_dbg(hsotg->dev, "    complete_split: %d\n",
1975                         chan->complete_split);
1976                 dev_dbg(hsotg->dev, "    hub_addr: %d\n", chan->hub_addr);
1977                 dev_dbg(hsotg->dev, "    hub_port: %d\n", chan->hub_port);
1978                 dev_dbg(hsotg->dev, "    xact_pos: %d\n", chan->xact_pos);
1979                 dev_dbg(hsotg->dev, "    requests: %d\n", chan->requests);
1980                 dev_dbg(hsotg->dev, "    qh: %p\n", chan->qh);
1981
1982                 if (chan->xfer_started) {
1983                         u32 hfnum, hcchar, hctsiz, hcint, hcintmsk;
1984
1985                         hfnum = dwc2_readl(hsotg->regs + HFNUM);
1986                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1987                         hctsiz = dwc2_readl(hsotg->regs + HCTSIZ(i));
1988                         hcint = dwc2_readl(hsotg->regs + HCINT(i));
1989                         hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(i));
1990                         dev_dbg(hsotg->dev, "    hfnum: 0x%08x\n", hfnum);
1991                         dev_dbg(hsotg->dev, "    hcchar: 0x%08x\n", hcchar);
1992                         dev_dbg(hsotg->dev, "    hctsiz: 0x%08x\n", hctsiz);
1993                         dev_dbg(hsotg->dev, "    hcint: 0x%08x\n", hcint);
1994                         dev_dbg(hsotg->dev, "    hcintmsk: 0x%08x\n", hcintmsk);
1995                 }
1996
1997                 if (!(chan->xfer_started && chan->qh))
1998                         continue;
1999
2000                 list_for_each_entry(qtd, &chan->qh->qtd_list, qtd_list_entry) {
2001                         if (!qtd->in_process)
2002                                 break;
2003                         urb = qtd->urb;
2004                         dev_dbg(hsotg->dev, "    URB Info:\n");
2005                         dev_dbg(hsotg->dev, "      qtd: %p, urb: %p\n",
2006                                 qtd, urb);
2007                         if (urb) {
2008                                 dev_dbg(hsotg->dev,
2009                                         "      Dev: %d, EP: %d %s\n",
2010                                         dwc2_hcd_get_dev_addr(&urb->pipe_info),
2011                                         dwc2_hcd_get_ep_num(&urb->pipe_info),
2012                                         dwc2_hcd_is_pipe_in(&urb->pipe_info) ?
2013                                         "IN" : "OUT");
2014                                 dev_dbg(hsotg->dev,
2015                                         "      Max packet size: %d\n",
2016                                         dwc2_hcd_get_mps(&urb->pipe_info));
2017                                 dev_dbg(hsotg->dev,
2018                                         "      transfer_buffer: %p\n",
2019                                         urb->buf);
2020                                 dev_dbg(hsotg->dev,
2021                                         "      transfer_dma: %08lx\n",
2022                                         (unsigned long)urb->dma);
2023                                 dev_dbg(hsotg->dev,
2024                                         "      transfer_buffer_length: %d\n",
2025                                         urb->length);
2026                                 dev_dbg(hsotg->dev, "      actual_length: %d\n",
2027                                         urb->actual_length);
2028                         }
2029                 }
2030         }
2031
2032         dev_dbg(hsotg->dev, "  non_periodic_channels: %d\n",
2033                 hsotg->non_periodic_channels);
2034         dev_dbg(hsotg->dev, "  periodic_channels: %d\n",
2035                 hsotg->periodic_channels);
2036         dev_dbg(hsotg->dev, "  periodic_usecs: %d\n", hsotg->periodic_usecs);
2037         np_tx_status = dwc2_readl(hsotg->regs + GNPTXSTS);
2038         dev_dbg(hsotg->dev, "  NP Tx Req Queue Space Avail: %d\n",
2039                 (np_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2040         dev_dbg(hsotg->dev, "  NP Tx FIFO Space Avail: %d\n",
2041                 (np_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2042         p_tx_status = dwc2_readl(hsotg->regs + HPTXSTS);
2043         dev_dbg(hsotg->dev, "  P Tx Req Queue Space Avail: %d\n",
2044                 (p_tx_status & TXSTS_QSPCAVAIL_MASK) >> TXSTS_QSPCAVAIL_SHIFT);
2045         dev_dbg(hsotg->dev, "  P Tx FIFO Space Avail: %d\n",
2046                 (p_tx_status & TXSTS_FSPCAVAIL_MASK) >> TXSTS_FSPCAVAIL_SHIFT);
2047         dwc2_hcd_dump_frrem(hsotg);
2048         dwc2_dump_global_registers(hsotg);
2049         dwc2_dump_host_registers(hsotg);
2050         dev_dbg(hsotg->dev,
2051                 "************************************************************\n");
2052         dev_dbg(hsotg->dev, "\n");
2053 #endif
2054 }
2055
2056 /*
2057  * NOTE: This function will be removed once the peripheral controller code
2058  * is integrated and the driver is stable
2059  */
2060 void dwc2_hcd_dump_frrem(struct dwc2_hsotg *hsotg)
2061 {
2062 #ifdef DWC2_DUMP_FRREM
2063         dev_dbg(hsotg->dev, "Frame remaining at SOF:\n");
2064         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2065                 hsotg->frrem_samples, hsotg->frrem_accum,
2066                 hsotg->frrem_samples > 0 ?
2067                 hsotg->frrem_accum / hsotg->frrem_samples : 0);
2068         dev_dbg(hsotg->dev, "\n");
2069         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 7):\n");
2070         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2071                 hsotg->hfnum_7_samples,
2072                 hsotg->hfnum_7_frrem_accum,
2073                 hsotg->hfnum_7_samples > 0 ?
2074                 hsotg->hfnum_7_frrem_accum / hsotg->hfnum_7_samples : 0);
2075         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 0):\n");
2076         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2077                 hsotg->hfnum_0_samples,
2078                 hsotg->hfnum_0_frrem_accum,
2079                 hsotg->hfnum_0_samples > 0 ?
2080                 hsotg->hfnum_0_frrem_accum / hsotg->hfnum_0_samples : 0);
2081         dev_dbg(hsotg->dev, "Frame remaining at start_transfer (uframe 1-6):\n");
2082         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2083                 hsotg->hfnum_other_samples,
2084                 hsotg->hfnum_other_frrem_accum,
2085                 hsotg->hfnum_other_samples > 0 ?
2086                 hsotg->hfnum_other_frrem_accum / hsotg->hfnum_other_samples :
2087                 0);
2088         dev_dbg(hsotg->dev, "\n");
2089         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 7):\n");
2090         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2091                 hsotg->hfnum_7_samples_a, hsotg->hfnum_7_frrem_accum_a,
2092                 hsotg->hfnum_7_samples_a > 0 ?
2093                 hsotg->hfnum_7_frrem_accum_a / hsotg->hfnum_7_samples_a : 0);
2094         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 0):\n");
2095         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2096                 hsotg->hfnum_0_samples_a, hsotg->hfnum_0_frrem_accum_a,
2097                 hsotg->hfnum_0_samples_a > 0 ?
2098                 hsotg->hfnum_0_frrem_accum_a / hsotg->hfnum_0_samples_a : 0);
2099         dev_dbg(hsotg->dev, "Frame remaining at sample point A (uframe 1-6):\n");
2100         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2101                 hsotg->hfnum_other_samples_a, hsotg->hfnum_other_frrem_accum_a,
2102                 hsotg->hfnum_other_samples_a > 0 ?
2103                 hsotg->hfnum_other_frrem_accum_a / hsotg->hfnum_other_samples_a
2104                 : 0);
2105         dev_dbg(hsotg->dev, "\n");
2106         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 7):\n");
2107         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2108                 hsotg->hfnum_7_samples_b, hsotg->hfnum_7_frrem_accum_b,
2109                 hsotg->hfnum_7_samples_b > 0 ?
2110                 hsotg->hfnum_7_frrem_accum_b / hsotg->hfnum_7_samples_b : 0);
2111         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 0):\n");
2112         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2113                 hsotg->hfnum_0_samples_b, hsotg->hfnum_0_frrem_accum_b,
2114                 (hsotg->hfnum_0_samples_b > 0) ?
2115                 hsotg->hfnum_0_frrem_accum_b / hsotg->hfnum_0_samples_b : 0);
2116         dev_dbg(hsotg->dev, "Frame remaining at sample point B (uframe 1-6):\n");
2117         dev_dbg(hsotg->dev, "  samples %u, accum %llu, avg %llu\n",
2118                 hsotg->hfnum_other_samples_b, hsotg->hfnum_other_frrem_accum_b,
2119                 (hsotg->hfnum_other_samples_b > 0) ?
2120                 hsotg->hfnum_other_frrem_accum_b / hsotg->hfnum_other_samples_b
2121                 : 0);
2122 #endif
2123 }
2124
2125 struct wrapper_priv_data {
2126         struct dwc2_hsotg *hsotg;
2127 };
2128
2129 /* Gets the dwc2_hsotg from a usb_hcd */
2130 static struct dwc2_hsotg *dwc2_hcd_to_hsotg(struct usb_hcd *hcd)
2131 {
2132         struct wrapper_priv_data *p;
2133
2134         p = (struct wrapper_priv_data *) &hcd->hcd_priv;
2135         return p->hsotg;
2136 }
2137
2138 static int _dwc2_hcd_start(struct usb_hcd *hcd);
2139
2140 void dwc2_host_start(struct dwc2_hsotg *hsotg)
2141 {
2142         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2143
2144         hcd->self.is_b_host = dwc2_hcd_is_b_host(hsotg);
2145         _dwc2_hcd_start(hcd);
2146 }
2147
2148 void dwc2_host_disconnect(struct dwc2_hsotg *hsotg)
2149 {
2150         struct usb_hcd *hcd = dwc2_hsotg_to_hcd(hsotg);
2151
2152         hcd->self.is_b_host = 0;
2153 }
2154
2155 void dwc2_host_hub_info(struct dwc2_hsotg *hsotg, void *context, int *hub_addr,
2156                         int *hub_port)
2157 {
2158         struct urb *urb = context;
2159
2160         if (urb->dev->tt)
2161                 *hub_addr = urb->dev->tt->hub->devnum;
2162         else
2163                 *hub_addr = 0;
2164         *hub_port = urb->dev->ttport;
2165 }
2166
2167 int dwc2_host_get_speed(struct dwc2_hsotg *hsotg, void *context)
2168 {
2169         struct urb *urb = context;
2170
2171         return urb->dev->speed;
2172 }
2173
2174 static void dwc2_allocate_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2175                                         struct urb *urb)
2176 {
2177         struct usb_bus *bus = hcd_to_bus(hcd);
2178
2179         if (urb->interval)
2180                 bus->bandwidth_allocated += bw / urb->interval;
2181         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2182                 bus->bandwidth_isoc_reqs++;
2183         else
2184                 bus->bandwidth_int_reqs++;
2185 }
2186
2187 static void dwc2_free_bus_bandwidth(struct usb_hcd *hcd, u16 bw,
2188                                     struct urb *urb)
2189 {
2190         struct usb_bus *bus = hcd_to_bus(hcd);
2191
2192         if (urb->interval)
2193                 bus->bandwidth_allocated -= bw / urb->interval;
2194         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2195                 bus->bandwidth_isoc_reqs--;
2196         else
2197                 bus->bandwidth_int_reqs--;
2198 }
2199
2200 /*
2201  * Sets the final status of an URB and returns it to the upper layer. Any
2202  * required cleanup of the URB is performed.
2203  *
2204  * Must be called with interrupt disabled and spinlock held
2205  */
2206 void dwc2_host_complete(struct dwc2_hsotg *hsotg, struct dwc2_qtd *qtd,
2207                         int status)
2208 {
2209         struct urb *urb;
2210         int i;
2211
2212         if (!qtd) {
2213                 dev_dbg(hsotg->dev, "## %s: qtd is NULL ##\n", __func__);
2214                 return;
2215         }
2216
2217         if (!qtd->urb) {
2218                 dev_dbg(hsotg->dev, "## %s: qtd->urb is NULL ##\n", __func__);
2219                 return;
2220         }
2221
2222         urb = qtd->urb->priv;
2223         if (!urb) {
2224                 dev_dbg(hsotg->dev, "## %s: urb->priv is NULL ##\n", __func__);
2225                 return;
2226         }
2227
2228         urb->actual_length = dwc2_hcd_urb_get_actual_length(qtd->urb);
2229
2230         if (dbg_urb(urb))
2231                 dev_vdbg(hsotg->dev,
2232                          "%s: urb %p device %d ep %d-%s status %d actual %d\n",
2233                          __func__, urb, usb_pipedevice(urb->pipe),
2234                          usb_pipeendpoint(urb->pipe),
2235                          usb_pipein(urb->pipe) ? "IN" : "OUT", status,
2236                          urb->actual_length);
2237
2238
2239         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2240                 urb->error_count = dwc2_hcd_urb_get_error_count(qtd->urb);
2241                 for (i = 0; i < urb->number_of_packets; ++i) {
2242                         urb->iso_frame_desc[i].actual_length =
2243                                 dwc2_hcd_urb_get_iso_desc_actual_length(
2244                                                 qtd->urb, i);
2245                         urb->iso_frame_desc[i].status =
2246                                 dwc2_hcd_urb_get_iso_desc_status(qtd->urb, i);
2247                 }
2248         }
2249
2250         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS && dbg_perio()) {
2251                 for (i = 0; i < urb->number_of_packets; i++)
2252                         dev_vdbg(hsotg->dev, " ISO Desc %d status %d\n",
2253                                  i, urb->iso_frame_desc[i].status);
2254         }
2255
2256         urb->status = status;
2257         if (!status) {
2258                 if ((urb->transfer_flags & URB_SHORT_NOT_OK) &&
2259                     urb->actual_length < urb->transfer_buffer_length)
2260                         urb->status = -EREMOTEIO;
2261         }
2262
2263         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2264             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2265                 struct usb_host_endpoint *ep = urb->ep;
2266
2267                 if (ep)
2268                         dwc2_free_bus_bandwidth(dwc2_hsotg_to_hcd(hsotg),
2269                                         dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2270                                         urb);
2271         }
2272
2273         usb_hcd_unlink_urb_from_ep(dwc2_hsotg_to_hcd(hsotg), urb);
2274         urb->hcpriv = NULL;
2275         kfree(qtd->urb);
2276         qtd->urb = NULL;
2277
2278         spin_unlock(&hsotg->lock);
2279         usb_hcd_giveback_urb(dwc2_hsotg_to_hcd(hsotg), urb, status);
2280         spin_lock(&hsotg->lock);
2281 }
2282
2283 /*
2284  * Work queue function for starting the HCD when A-Cable is connected
2285  */
2286 static void dwc2_hcd_start_func(struct work_struct *work)
2287 {
2288         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2289                                                 start_work.work);
2290
2291         dev_dbg(hsotg->dev, "%s() %p\n", __func__, hsotg);
2292         dwc2_host_start(hsotg);
2293 }
2294
2295 /*
2296  * Reset work queue function
2297  */
2298 static void dwc2_hcd_reset_func(struct work_struct *work)
2299 {
2300         struct dwc2_hsotg *hsotg = container_of(work, struct dwc2_hsotg,
2301                                                 reset_work.work);
2302         u32 hprt0;
2303
2304         dev_dbg(hsotg->dev, "USB RESET function called\n");
2305         hprt0 = dwc2_read_hprt0(hsotg);
2306         hprt0 &= ~HPRT0_RST;
2307         dwc2_writel(hprt0, hsotg->regs + HPRT0);
2308         hsotg->flags.b.port_reset_change = 1;
2309 }
2310
2311 /*
2312  * =========================================================================
2313  *  Linux HC Driver Functions
2314  * =========================================================================
2315  */
2316
2317 /*
2318  * Initializes the DWC_otg controller and its root hub and prepares it for host
2319  * mode operation. Activates the root port. Returns 0 on success and a negative
2320  * error code on failure.
2321  */
2322 static int _dwc2_hcd_start(struct usb_hcd *hcd)
2323 {
2324         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2325         struct usb_bus *bus = hcd_to_bus(hcd);
2326         unsigned long flags;
2327
2328         dev_dbg(hsotg->dev, "DWC OTG HCD START\n");
2329
2330         spin_lock_irqsave(&hsotg->lock, flags);
2331         hsotg->lx_state = DWC2_L0;
2332         hcd->state = HC_STATE_RUNNING;
2333         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2334
2335         if (dwc2_is_device_mode(hsotg)) {
2336                 spin_unlock_irqrestore(&hsotg->lock, flags);
2337                 return 0;       /* why 0 ?? */
2338         }
2339
2340         dwc2_hcd_reinit(hsotg);
2341
2342         /* Initialize and connect root hub if one is not already attached */
2343         if (bus->root_hub) {
2344                 dev_dbg(hsotg->dev, "DWC OTG HCD Has Root Hub\n");
2345                 /* Inform the HUB driver to resume */
2346                 usb_hcd_resume_root_hub(hcd);
2347         }
2348
2349         spin_unlock_irqrestore(&hsotg->lock, flags);
2350         return 0;
2351 }
2352
2353 /*
2354  * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
2355  * stopped.
2356  */
2357 static void _dwc2_hcd_stop(struct usb_hcd *hcd)
2358 {
2359         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2360         unsigned long flags;
2361
2362         /* Turn off all host-specific interrupts */
2363         dwc2_disable_host_interrupts(hsotg);
2364
2365         /* Wait for interrupt processing to finish */
2366         synchronize_irq(hcd->irq);
2367
2368         spin_lock_irqsave(&hsotg->lock, flags);
2369         /* Ensure hcd is disconnected */
2370         dwc2_hcd_disconnect(hsotg);
2371         dwc2_hcd_stop(hsotg);
2372         hsotg->lx_state = DWC2_L3;
2373         hcd->state = HC_STATE_HALT;
2374         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2375         spin_unlock_irqrestore(&hsotg->lock, flags);
2376
2377         usleep_range(1000, 3000);
2378 }
2379
2380 static int _dwc2_hcd_suspend(struct usb_hcd *hcd)
2381 {
2382         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2383         unsigned long flags;
2384         int ret = 0;
2385         u32 hprt0;
2386
2387         spin_lock_irqsave(&hsotg->lock, flags);
2388
2389         if (hsotg->lx_state != DWC2_L0)
2390                 goto unlock;
2391
2392         if (!HCD_HW_ACCESSIBLE(hcd))
2393                 goto unlock;
2394
2395         if (!hsotg->core_params->hibernation)
2396                 goto skip_power_saving;
2397
2398         /*
2399          * Drive USB suspend and disable port Power
2400          * if usb bus is not suspended.
2401          */
2402         if (!hsotg->bus_suspended) {
2403                 hprt0 = dwc2_read_hprt0(hsotg);
2404                 hprt0 |= HPRT0_SUSP;
2405                 hprt0 &= ~HPRT0_PWR;
2406                 dwc2_writel(hprt0, hsotg->regs + HPRT0);
2407         }
2408
2409         /* Enter hibernation */
2410         ret = dwc2_enter_hibernation(hsotg);
2411         if (ret) {
2412                 if (ret != -ENOTSUPP)
2413                         dev_err(hsotg->dev,
2414                                 "enter hibernation failed\n");
2415                 goto skip_power_saving;
2416         }
2417
2418         /* Ask phy to be suspended */
2419         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2420                 spin_unlock_irqrestore(&hsotg->lock, flags);
2421                 usb_phy_set_suspend(hsotg->uphy, true);
2422                 spin_lock_irqsave(&hsotg->lock, flags);
2423         }
2424
2425         /* After entering hibernation, hardware is no more accessible */
2426         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2427
2428 skip_power_saving:
2429         hsotg->lx_state = DWC2_L2;
2430 unlock:
2431         spin_unlock_irqrestore(&hsotg->lock, flags);
2432
2433         return ret;
2434 }
2435
2436 static int _dwc2_hcd_resume(struct usb_hcd *hcd)
2437 {
2438         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2439         unsigned long flags;
2440         int ret = 0;
2441
2442         spin_lock_irqsave(&hsotg->lock, flags);
2443
2444         if (hsotg->lx_state != DWC2_L2)
2445                 goto unlock;
2446
2447         if (!hsotg->core_params->hibernation) {
2448                 hsotg->lx_state = DWC2_L0;
2449                 goto unlock;
2450         }
2451
2452         /*
2453          * Set HW accessible bit before powering on the controller
2454          * since an interrupt may rise.
2455          */
2456         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
2457
2458         /*
2459          * Enable power if not already done.
2460          * This must not be spinlocked since duration
2461          * of this call is unknown.
2462          */
2463         if (!IS_ERR_OR_NULL(hsotg->uphy)) {
2464                 spin_unlock_irqrestore(&hsotg->lock, flags);
2465                 usb_phy_set_suspend(hsotg->uphy, false);
2466                 spin_lock_irqsave(&hsotg->lock, flags);
2467         }
2468
2469         /* Exit hibernation */
2470         ret = dwc2_exit_hibernation(hsotg, true);
2471         if (ret && (ret != -ENOTSUPP))
2472                 dev_err(hsotg->dev, "exit hibernation failed\n");
2473
2474         hsotg->lx_state = DWC2_L0;
2475
2476         spin_unlock_irqrestore(&hsotg->lock, flags);
2477
2478         if (hsotg->bus_suspended) {
2479                 spin_lock_irqsave(&hsotg->lock, flags);
2480                 hsotg->flags.b.port_suspend_change = 1;
2481                 spin_unlock_irqrestore(&hsotg->lock, flags);
2482                 dwc2_port_resume(hsotg);
2483         } else {
2484                 /* Wait for controller to correctly update D+/D- level */
2485                 usleep_range(3000, 5000);
2486
2487                 /*
2488                  * Clear Port Enable and Port Status changes.
2489                  * Enable Port Power.
2490                  */
2491                 dwc2_writel(HPRT0_PWR | HPRT0_CONNDET |
2492                                 HPRT0_ENACHG, hsotg->regs + HPRT0);
2493                 /* Wait for controller to detect Port Connect */
2494                 usleep_range(5000, 7000);
2495         }
2496
2497         return ret;
2498 unlock:
2499         spin_unlock_irqrestore(&hsotg->lock, flags);
2500
2501         return ret;
2502 }
2503
2504 /* Returns the current frame number */
2505 static int _dwc2_hcd_get_frame_number(struct usb_hcd *hcd)
2506 {
2507         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2508
2509         return dwc2_hcd_get_frame_number(hsotg);
2510 }
2511
2512 static void dwc2_dump_urb_info(struct usb_hcd *hcd, struct urb *urb,
2513                                char *fn_name)
2514 {
2515 #ifdef VERBOSE_DEBUG
2516         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2517         char *pipetype;
2518         char *speed;
2519
2520         dev_vdbg(hsotg->dev, "%s, urb %p\n", fn_name, urb);
2521         dev_vdbg(hsotg->dev, "  Device address: %d\n",
2522                  usb_pipedevice(urb->pipe));
2523         dev_vdbg(hsotg->dev, "  Endpoint: %d, %s\n",
2524                  usb_pipeendpoint(urb->pipe),
2525                  usb_pipein(urb->pipe) ? "IN" : "OUT");
2526
2527         switch (usb_pipetype(urb->pipe)) {
2528         case PIPE_CONTROL:
2529                 pipetype = "CONTROL";
2530                 break;
2531         case PIPE_BULK:
2532                 pipetype = "BULK";
2533                 break;
2534         case PIPE_INTERRUPT:
2535                 pipetype = "INTERRUPT";
2536                 break;
2537         case PIPE_ISOCHRONOUS:
2538                 pipetype = "ISOCHRONOUS";
2539                 break;
2540         default:
2541                 pipetype = "UNKNOWN";
2542                 break;
2543         }
2544
2545         dev_vdbg(hsotg->dev, "  Endpoint type: %s %s (%s)\n", pipetype,
2546                  usb_urb_dir_in(urb) ? "IN" : "OUT", usb_pipein(urb->pipe) ?
2547                  "IN" : "OUT");
2548
2549         switch (urb->dev->speed) {
2550         case USB_SPEED_HIGH:
2551                 speed = "HIGH";
2552                 break;
2553         case USB_SPEED_FULL:
2554                 speed = "FULL";
2555                 break;
2556         case USB_SPEED_LOW:
2557                 speed = "LOW";
2558                 break;
2559         default:
2560                 speed = "UNKNOWN";
2561                 break;
2562         }
2563
2564         dev_vdbg(hsotg->dev, "  Speed: %s\n", speed);
2565         dev_vdbg(hsotg->dev, "  Max packet size: %d\n",
2566                  usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe)));
2567         dev_vdbg(hsotg->dev, "  Data buffer length: %d\n",
2568                  urb->transfer_buffer_length);
2569         dev_vdbg(hsotg->dev, "  Transfer buffer: %p, Transfer DMA: %08lx\n",
2570                  urb->transfer_buffer, (unsigned long)urb->transfer_dma);
2571         dev_vdbg(hsotg->dev, "  Setup buffer: %p, Setup DMA: %08lx\n",
2572                  urb->setup_packet, (unsigned long)urb->setup_dma);
2573         dev_vdbg(hsotg->dev, "  Interval: %d\n", urb->interval);
2574
2575         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
2576                 int i;
2577
2578                 for (i = 0; i < urb->number_of_packets; i++) {
2579                         dev_vdbg(hsotg->dev, "  ISO Desc %d:\n", i);
2580                         dev_vdbg(hsotg->dev, "    offset: %d, length %d\n",
2581                                  urb->iso_frame_desc[i].offset,
2582                                  urb->iso_frame_desc[i].length);
2583                 }
2584         }
2585 #endif
2586 }
2587
2588 /*
2589  * Starts processing a USB transfer request specified by a USB Request Block
2590  * (URB). mem_flags indicates the type of memory allocation to use while
2591  * processing this URB.
2592  */
2593 static int _dwc2_hcd_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
2594                                  gfp_t mem_flags)
2595 {
2596         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2597         struct usb_host_endpoint *ep = urb->ep;
2598         struct dwc2_hcd_urb *dwc2_urb;
2599         int i;
2600         int retval;
2601         int alloc_bandwidth = 0;
2602         u8 ep_type = 0;
2603         u32 tflags = 0;
2604         void *buf;
2605         unsigned long flags;
2606         struct dwc2_qh *qh;
2607         bool qh_allocated = false;
2608         struct dwc2_qtd *qtd;
2609
2610         if (dbg_urb(urb)) {
2611                 dev_vdbg(hsotg->dev, "DWC OTG HCD URB Enqueue\n");
2612                 dwc2_dump_urb_info(hcd, urb, "urb_enqueue");
2613         }
2614
2615         if (ep == NULL)
2616                 return -EINVAL;
2617
2618         if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS ||
2619             usb_pipetype(urb->pipe) == PIPE_INTERRUPT) {
2620                 spin_lock_irqsave(&hsotg->lock, flags);
2621                 if (!dwc2_hcd_is_bandwidth_allocated(hsotg, ep))
2622                         alloc_bandwidth = 1;
2623                 spin_unlock_irqrestore(&hsotg->lock, flags);
2624         }
2625
2626         switch (usb_pipetype(urb->pipe)) {
2627         case PIPE_CONTROL:
2628                 ep_type = USB_ENDPOINT_XFER_CONTROL;
2629                 break;
2630         case PIPE_ISOCHRONOUS:
2631                 ep_type = USB_ENDPOINT_XFER_ISOC;
2632                 break;
2633         case PIPE_BULK:
2634                 ep_type = USB_ENDPOINT_XFER_BULK;
2635                 break;
2636         case PIPE_INTERRUPT:
2637                 ep_type = USB_ENDPOINT_XFER_INT;
2638                 break;
2639         default:
2640                 dev_warn(hsotg->dev, "Wrong ep type\n");
2641         }
2642
2643         dwc2_urb = dwc2_hcd_urb_alloc(hsotg, urb->number_of_packets,
2644                                       mem_flags);
2645         if (!dwc2_urb)
2646                 return -ENOMEM;
2647
2648         dwc2_hcd_urb_set_pipeinfo(hsotg, dwc2_urb, usb_pipedevice(urb->pipe),
2649                                   usb_pipeendpoint(urb->pipe), ep_type,
2650                                   usb_pipein(urb->pipe),
2651                                   usb_maxpacket(urb->dev, urb->pipe,
2652                                                 !(usb_pipein(urb->pipe))));
2653
2654         buf = urb->transfer_buffer;
2655
2656         if (hcd->self.uses_dma) {
2657                 if (!buf && (urb->transfer_dma & 3)) {
2658                         dev_err(hsotg->dev,
2659                                 "%s: unaligned transfer with no transfer_buffer",
2660                                 __func__);
2661                         retval = -EINVAL;
2662                         goto fail0;
2663                 }
2664         }
2665
2666         if (!(urb->transfer_flags & URB_NO_INTERRUPT))
2667                 tflags |= URB_GIVEBACK_ASAP;
2668         if (urb->transfer_flags & URB_ZERO_PACKET)
2669                 tflags |= URB_SEND_ZERO_PACKET;
2670
2671         dwc2_urb->priv = urb;
2672         dwc2_urb->buf = buf;
2673         dwc2_urb->dma = urb->transfer_dma;
2674         dwc2_urb->length = urb->transfer_buffer_length;
2675         dwc2_urb->setup_packet = urb->setup_packet;
2676         dwc2_urb->setup_dma = urb->setup_dma;
2677         dwc2_urb->flags = tflags;
2678         dwc2_urb->interval = urb->interval;
2679         dwc2_urb->status = -EINPROGRESS;
2680
2681         for (i = 0; i < urb->number_of_packets; ++i)
2682                 dwc2_hcd_urb_set_iso_desc_params(dwc2_urb, i,
2683                                                  urb->iso_frame_desc[i].offset,
2684                                                  urb->iso_frame_desc[i].length);
2685
2686         urb->hcpriv = dwc2_urb;
2687         qh = (struct dwc2_qh *) ep->hcpriv;
2688         /* Create QH for the endpoint if it doesn't exist */
2689         if (!qh) {
2690                 qh = dwc2_hcd_qh_create(hsotg, dwc2_urb, mem_flags);
2691                 if (!qh) {
2692                         retval = -ENOMEM;
2693                         goto fail0;
2694                 }
2695                 ep->hcpriv = qh;
2696                 qh_allocated = true;
2697         }
2698
2699         qtd = kzalloc(sizeof(*qtd), mem_flags);
2700         if (!qtd) {
2701                 retval = -ENOMEM;
2702                 goto fail1;
2703         }
2704
2705         spin_lock_irqsave(&hsotg->lock, flags);
2706         retval = usb_hcd_link_urb_to_ep(hcd, urb);
2707         if (retval)
2708                 goto fail2;
2709
2710         retval = dwc2_hcd_urb_enqueue(hsotg, dwc2_urb, qh, qtd);
2711         if (retval)
2712                 goto fail3;
2713
2714         if (alloc_bandwidth) {
2715                 dwc2_allocate_bus_bandwidth(hcd,
2716                                 dwc2_hcd_get_ep_bandwidth(hsotg, ep),
2717                                 urb);
2718         }
2719
2720         spin_unlock_irqrestore(&hsotg->lock, flags);
2721
2722         return 0;
2723
2724 fail3:
2725         dwc2_urb->priv = NULL;
2726         usb_hcd_unlink_urb_from_ep(hcd, urb);
2727 fail2:
2728         spin_unlock_irqrestore(&hsotg->lock, flags);
2729         urb->hcpriv = NULL;
2730         kfree(qtd);
2731 fail1:
2732         if (qh_allocated) {
2733                 struct dwc2_qtd *qtd2, *qtd2_tmp;
2734
2735                 ep->hcpriv = NULL;
2736                 dwc2_hcd_qh_unlink(hsotg, qh);
2737                 /* Free each QTD in the QH's QTD list */
2738                 list_for_each_entry_safe(qtd2, qtd2_tmp, &qh->qtd_list,
2739                                                          qtd_list_entry)
2740                         dwc2_hcd_qtd_unlink_and_free(hsotg, qtd2, qh);
2741                 dwc2_hcd_qh_free(hsotg, qh);
2742         }
2743 fail0:
2744         kfree(dwc2_urb);
2745
2746         return retval;
2747 }
2748
2749 /*
2750  * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
2751  */
2752 static int _dwc2_hcd_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
2753                                  int status)
2754 {
2755         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2756         int rc;
2757         unsigned long flags;
2758
2759         dev_dbg(hsotg->dev, "DWC OTG HCD URB Dequeue\n");
2760         dwc2_dump_urb_info(hcd, urb, "urb_dequeue");
2761
2762         spin_lock_irqsave(&hsotg->lock, flags);
2763
2764         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
2765         if (rc)
2766                 goto out;
2767
2768         if (!urb->hcpriv) {
2769                 dev_dbg(hsotg->dev, "## urb->hcpriv is NULL ##\n");
2770                 goto out;
2771         }
2772
2773         rc = dwc2_hcd_urb_dequeue(hsotg, urb->hcpriv);
2774
2775         usb_hcd_unlink_urb_from_ep(hcd, urb);
2776
2777         kfree(urb->hcpriv);
2778         urb->hcpriv = NULL;
2779
2780         /* Higher layer software sets URB status */
2781         spin_unlock(&hsotg->lock);
2782         usb_hcd_giveback_urb(hcd, urb, status);
2783         spin_lock(&hsotg->lock);
2784
2785         dev_dbg(hsotg->dev, "Called usb_hcd_giveback_urb()\n");
2786         dev_dbg(hsotg->dev, "  urb->status = %d\n", urb->status);
2787 out:
2788         spin_unlock_irqrestore(&hsotg->lock, flags);
2789
2790         return rc;
2791 }
2792
2793 /*
2794  * Frees resources in the DWC_otg controller related to a given endpoint. Also
2795  * clears state in the HCD related to the endpoint. Any URBs for the endpoint
2796  * must already be dequeued.
2797  */
2798 static void _dwc2_hcd_endpoint_disable(struct usb_hcd *hcd,
2799                                        struct usb_host_endpoint *ep)
2800 {
2801         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2802
2803         dev_dbg(hsotg->dev,
2804                 "DWC OTG HCD EP DISABLE: bEndpointAddress=0x%02x, ep->hcpriv=%p\n",
2805                 ep->desc.bEndpointAddress, ep->hcpriv);
2806         dwc2_hcd_endpoint_disable(hsotg, ep, 250);
2807 }
2808
2809 /*
2810  * Resets endpoint specific parameter values, in current version used to reset
2811  * the data toggle (as a WA). This function can be called from usb_clear_halt
2812  * routine.
2813  */
2814 static void _dwc2_hcd_endpoint_reset(struct usb_hcd *hcd,
2815                                      struct usb_host_endpoint *ep)
2816 {
2817         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2818         unsigned long flags;
2819
2820         dev_dbg(hsotg->dev,
2821                 "DWC OTG HCD EP RESET: bEndpointAddress=0x%02x\n",
2822                 ep->desc.bEndpointAddress);
2823
2824         spin_lock_irqsave(&hsotg->lock, flags);
2825         dwc2_hcd_endpoint_reset(hsotg, ep);
2826         spin_unlock_irqrestore(&hsotg->lock, flags);
2827 }
2828
2829 /*
2830  * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
2831  * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
2832  * interrupt.
2833  *
2834  * This function is called by the USB core when an interrupt occurs
2835  */
2836 static irqreturn_t _dwc2_hcd_irq(struct usb_hcd *hcd)
2837 {
2838         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2839
2840         return dwc2_handle_hcd_intr(hsotg);
2841 }
2842
2843 /*
2844  * Creates Status Change bitmap for the root hub and root port. The bitmap is
2845  * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
2846  * is the status change indicator for the single root port. Returns 1 if either
2847  * change indicator is 1, otherwise returns 0.
2848  */
2849 static int _dwc2_hcd_hub_status_data(struct usb_hcd *hcd, char *buf)
2850 {
2851         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2852
2853         buf[0] = dwc2_hcd_is_status_changed(hsotg, 1) << 1;
2854         return buf[0] != 0;
2855 }
2856
2857 /* Handles hub class-specific requests */
2858 static int _dwc2_hcd_hub_control(struct usb_hcd *hcd, u16 typereq, u16 wvalue,
2859                                  u16 windex, char *buf, u16 wlength)
2860 {
2861         int retval = dwc2_hcd_hub_control(dwc2_hcd_to_hsotg(hcd), typereq,
2862                                           wvalue, windex, buf, wlength);
2863         return retval;
2864 }
2865
2866 /* Handles hub TT buffer clear completions */
2867 static void _dwc2_hcd_clear_tt_buffer_complete(struct usb_hcd *hcd,
2868                                                struct usb_host_endpoint *ep)
2869 {
2870         struct dwc2_hsotg *hsotg = dwc2_hcd_to_hsotg(hcd);
2871         struct dwc2_qh *qh;
2872         unsigned long flags;
2873
2874         qh = ep->hcpriv;
2875         if (!qh)
2876                 return;
2877
2878         spin_lock_irqsave(&hsotg->lock, flags);
2879         qh->tt_buffer_dirty = 0;
2880
2881         if (hsotg->flags.b.port_connect_status)
2882                 dwc2_hcd_queue_transactions(hsotg, DWC2_TRANSACTION_ALL);
2883
2884         spin_unlock_irqrestore(&hsotg->lock, flags);
2885 }
2886
2887 static struct hc_driver dwc2_hc_driver = {
2888         .description = "dwc2_hsotg",
2889         .product_desc = "DWC OTG Controller",
2890         .hcd_priv_size = sizeof(struct wrapper_priv_data),
2891
2892         .irq = _dwc2_hcd_irq,
2893         .flags = HCD_MEMORY | HCD_USB2,
2894
2895         .start = _dwc2_hcd_start,
2896         .stop = _dwc2_hcd_stop,
2897         .urb_enqueue = _dwc2_hcd_urb_enqueue,
2898         .urb_dequeue = _dwc2_hcd_urb_dequeue,
2899         .endpoint_disable = _dwc2_hcd_endpoint_disable,
2900         .endpoint_reset = _dwc2_hcd_endpoint_reset,
2901         .get_frame_number = _dwc2_hcd_get_frame_number,
2902
2903         .hub_status_data = _dwc2_hcd_hub_status_data,
2904         .hub_control = _dwc2_hcd_hub_control,
2905         .clear_tt_buffer_complete = _dwc2_hcd_clear_tt_buffer_complete,
2906
2907         .bus_suspend = _dwc2_hcd_suspend,
2908         .bus_resume = _dwc2_hcd_resume,
2909 };
2910
2911 /*
2912  * Frees secondary storage associated with the dwc2_hsotg structure contained
2913  * in the struct usb_hcd field
2914  */
2915 static void dwc2_hcd_free(struct dwc2_hsotg *hsotg)
2916 {
2917         u32 ahbcfg;
2918         u32 dctl;
2919         int i;
2920
2921         dev_dbg(hsotg->dev, "DWC OTG HCD FREE\n");
2922
2923         /* Free memory for QH/QTD lists */
2924         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_inactive);
2925         dwc2_qh_list_free(hsotg, &hsotg->non_periodic_sched_active);
2926         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_inactive);
2927         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_ready);
2928         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_assigned);
2929         dwc2_qh_list_free(hsotg, &hsotg->periodic_sched_queued);
2930
2931         /* Free memory for the host channels */
2932         for (i = 0; i < MAX_EPS_CHANNELS; i++) {
2933                 struct dwc2_host_chan *chan = hsotg->hc_ptr_array[i];
2934
2935                 if (chan != NULL) {
2936                         dev_dbg(hsotg->dev, "HCD Free channel #%i, chan=%p\n",
2937                                 i, chan);
2938                         hsotg->hc_ptr_array[i] = NULL;
2939                         kfree(chan);
2940                 }
2941         }
2942
2943         if (hsotg->core_params->dma_enable > 0) {
2944                 if (hsotg->status_buf) {
2945                         dma_free_coherent(hsotg->dev, DWC2_HCD_STATUS_BUF_SIZE,
2946                                           hsotg->status_buf,
2947                                           hsotg->status_buf_dma);
2948                         hsotg->status_buf = NULL;
2949                 }
2950         } else {
2951                 kfree(hsotg->status_buf);
2952                 hsotg->status_buf = NULL;
2953         }
2954
2955         ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
2956
2957         /* Disable all interrupts */
2958         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
2959         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
2960         dwc2_writel(0, hsotg->regs + GINTMSK);
2961
2962         if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a) {
2963                 dctl = dwc2_readl(hsotg->regs + DCTL);
2964                 dctl |= DCTL_SFTDISCON;
2965                 dwc2_writel(dctl, hsotg->regs + DCTL);
2966         }
2967
2968         if (hsotg->wq_otg) {
2969                 if (!cancel_work_sync(&hsotg->wf_otg))
2970                         flush_workqueue(hsotg->wq_otg);
2971                 destroy_workqueue(hsotg->wq_otg);
2972         }
2973
2974         del_timer(&hsotg->wkp_timer);
2975 }
2976
2977 static void dwc2_hcd_release(struct dwc2_hsotg *hsotg)
2978 {
2979         /* Turn off all host-specific interrupts */
2980         dwc2_disable_host_interrupts(hsotg);
2981
2982         dwc2_hcd_free(hsotg);
2983 }
2984
2985 /*
2986  * Initializes the HCD. This function allocates memory for and initializes the
2987  * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
2988  * USB bus with the core and calls the hc_driver->start() function. It returns
2989  * a negative error on failure.
2990  */
2991 int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq)
2992 {
2993         struct usb_hcd *hcd;
2994         struct dwc2_host_chan *channel;
2995         u32 hcfg;
2996         int i, num_channels;
2997         int retval;
2998
2999         if (usb_disabled())
3000                 return -ENODEV;
3001
3002         dev_dbg(hsotg->dev, "DWC OTG HCD INIT\n");
3003
3004         retval = -ENOMEM;
3005
3006         hcfg = dwc2_readl(hsotg->regs + HCFG);
3007         dev_dbg(hsotg->dev, "hcfg=%08x\n", hcfg);
3008
3009 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3010         hsotg->frame_num_array = kzalloc(sizeof(*hsotg->frame_num_array) *
3011                                          FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3012         if (!hsotg->frame_num_array)
3013                 goto error1;
3014         hsotg->last_frame_num_array = kzalloc(
3015                         sizeof(*hsotg->last_frame_num_array) *
3016                         FRAME_NUM_ARRAY_SIZE, GFP_KERNEL);
3017         if (!hsotg->last_frame_num_array)
3018                 goto error1;
3019         hsotg->last_frame_num = HFNUM_MAX_FRNUM;
3020 #endif
3021
3022         /* Check if the bus driver or platform code has setup a dma_mask */
3023         if (hsotg->core_params->dma_enable > 0 &&
3024             hsotg->dev->dma_mask == NULL) {
3025                 dev_warn(hsotg->dev,
3026                          "dma_mask not set, disabling DMA\n");
3027                 hsotg->core_params->dma_enable = 0;
3028                 hsotg->core_params->dma_desc_enable = 0;
3029         }
3030
3031         /* Set device flags indicating whether the HCD supports DMA */
3032         if (hsotg->core_params->dma_enable > 0) {
3033                 if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3034                         dev_warn(hsotg->dev, "can't set DMA mask\n");
3035                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
3036                         dev_warn(hsotg->dev, "can't set coherent DMA mask\n");
3037         }
3038
3039         hcd = usb_create_hcd(&dwc2_hc_driver, hsotg->dev, dev_name(hsotg->dev));
3040         if (!hcd)
3041                 goto error1;
3042
3043         if (hsotg->core_params->dma_enable <= 0)
3044                 hcd->self.uses_dma = 0;
3045
3046         hcd->has_tt = 1;
3047
3048         ((struct wrapper_priv_data *) &hcd->hcd_priv)->hsotg = hsotg;
3049         hsotg->priv = hcd;
3050
3051         /*
3052          * Disable the global interrupt until all the interrupt handlers are
3053          * installed
3054          */
3055         dwc2_disable_global_interrupts(hsotg);
3056
3057         /* Initialize the DWC_otg core, and select the Phy type */
3058         retval = dwc2_core_init(hsotg, true);
3059         if (retval)
3060                 goto error2;
3061
3062         /* Create new workqueue and init work */
3063         retval = -ENOMEM;
3064         hsotg->wq_otg = create_singlethread_workqueue("dwc2");
3065         if (!hsotg->wq_otg) {
3066                 dev_err(hsotg->dev, "Failed to create workqueue\n");
3067                 goto error2;
3068         }
3069         INIT_WORK(&hsotg->wf_otg, dwc2_conn_id_status_change);
3070
3071         setup_timer(&hsotg->wkp_timer, dwc2_wakeup_detected,
3072                     (unsigned long)hsotg);
3073
3074         /* Initialize the non-periodic schedule */
3075         INIT_LIST_HEAD(&hsotg->non_periodic_sched_inactive);
3076         INIT_LIST_HEAD(&hsotg->non_periodic_sched_active);
3077
3078         /* Initialize the periodic schedule */
3079         INIT_LIST_HEAD(&hsotg->periodic_sched_inactive);
3080         INIT_LIST_HEAD(&hsotg->periodic_sched_ready);
3081         INIT_LIST_HEAD(&hsotg->periodic_sched_assigned);
3082         INIT_LIST_HEAD(&hsotg->periodic_sched_queued);
3083
3084         /*
3085          * Create a host channel descriptor for each host channel implemented
3086          * in the controller. Initialize the channel descriptor array.
3087          */
3088         INIT_LIST_HEAD(&hsotg->free_hc_list);
3089         num_channels = hsotg->core_params->host_channels;
3090         memset(&hsotg->hc_ptr_array[0], 0, sizeof(hsotg->hc_ptr_array));
3091
3092         for (i = 0; i < num_channels; i++) {
3093                 channel = kzalloc(sizeof(*channel), GFP_KERNEL);
3094                 if (channel == NULL)
3095                         goto error3;
3096                 channel->hc_num = i;
3097                 hsotg->hc_ptr_array[i] = channel;
3098         }
3099
3100         if (hsotg->core_params->uframe_sched > 0)
3101                 dwc2_hcd_init_usecs(hsotg);
3102
3103         /* Initialize hsotg start work */
3104         INIT_DELAYED_WORK(&hsotg->start_work, dwc2_hcd_start_func);
3105
3106         /* Initialize port reset work */
3107         INIT_DELAYED_WORK(&hsotg->reset_work, dwc2_hcd_reset_func);
3108
3109         /*
3110          * Allocate space for storing data on status transactions. Normally no
3111          * data is sent, but this space acts as a bit bucket. This must be
3112          * done after usb_add_hcd since that function allocates the DMA buffer
3113          * pool.
3114          */
3115         if (hsotg->core_params->dma_enable > 0)
3116                 hsotg->status_buf = dma_alloc_coherent(hsotg->dev,
3117                                         DWC2_HCD_STATUS_BUF_SIZE,
3118                                         &hsotg->status_buf_dma, GFP_KERNEL);
3119         else
3120                 hsotg->status_buf = kzalloc(DWC2_HCD_STATUS_BUF_SIZE,
3121                                           GFP_KERNEL);
3122
3123         if (!hsotg->status_buf)
3124                 goto error3;
3125
3126         hsotg->otg_port = 1;
3127         hsotg->frame_list = NULL;
3128         hsotg->frame_list_dma = 0;
3129         hsotg->periodic_qh_count = 0;
3130
3131         /* Initiate lx_state to L3 disconnected state */
3132         hsotg->lx_state = DWC2_L3;
3133
3134         hcd->self.otg_port = hsotg->otg_port;
3135
3136         /* Don't support SG list at this point */
3137         hcd->self.sg_tablesize = 0;
3138
3139         if (!IS_ERR_OR_NULL(hsotg->uphy))
3140                 otg_set_host(hsotg->uphy->otg, &hcd->self);
3141
3142         /*
3143          * Finish generic HCD initialization and start the HCD. This function
3144          * allocates the DMA buffer pool, registers the USB bus, requests the
3145          * IRQ line, and calls hcd_start method.
3146          */
3147         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
3148         if (retval < 0)
3149                 goto error3;
3150
3151         device_wakeup_enable(hcd->self.controller);
3152
3153         dwc2_hcd_dump_state(hsotg);
3154
3155         dwc2_enable_global_interrupts(hsotg);
3156
3157         return 0;
3158
3159 error3:
3160         dwc2_hcd_release(hsotg);
3161 error2:
3162         usb_put_hcd(hcd);
3163 error1:
3164         kfree(hsotg->core_params);
3165
3166 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3167         kfree(hsotg->last_frame_num_array);
3168         kfree(hsotg->frame_num_array);
3169 #endif
3170
3171         dev_err(hsotg->dev, "%s() FAILED, returning %d\n", __func__, retval);
3172         return retval;
3173 }
3174
3175 /*
3176  * Removes the HCD.
3177  * Frees memory and resources associated with the HCD and deregisters the bus.
3178  */
3179 void dwc2_hcd_remove(struct dwc2_hsotg *hsotg)
3180 {
3181         struct usb_hcd *hcd;
3182
3183         dev_dbg(hsotg->dev, "DWC OTG HCD REMOVE\n");
3184
3185         hcd = dwc2_hsotg_to_hcd(hsotg);
3186         dev_dbg(hsotg->dev, "hsotg->hcd = %p\n", hcd);
3187
3188         if (!hcd) {
3189                 dev_dbg(hsotg->dev, "%s: dwc2_hsotg_to_hcd(hsotg) NULL!\n",
3190                         __func__);
3191                 return;
3192         }
3193
3194         if (!IS_ERR_OR_NULL(hsotg->uphy))
3195                 otg_set_host(hsotg->uphy->otg, NULL);
3196
3197         usb_remove_hcd(hcd);
3198         hsotg->priv = NULL;
3199         dwc2_hcd_release(hsotg);
3200         usb_put_hcd(hcd);
3201
3202 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
3203         kfree(hsotg->last_frame_num_array);
3204         kfree(hsotg->frame_num_array);
3205 #endif
3206 }