drivers/usb/dwc2/core.c

   1 /*
   2  * core.c - DesignWare HS OTG Controller common routines
   3  *
   4  * Copyright (C) 2004-2013 Synopsys, Inc.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions, and the following disclaimer,
  11  *    without modification.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. The names of the above-listed copyright holders may not be used
  16  *    to endorse or promote products derived from this software without
  17  *    specific prior written permission.
  18  *
  19  * ALTERNATIVELY, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") as published by the Free Software
  21  * Foundation; either version 2 of the License, or (at your option) any
  22  * later version.
  23  *
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35  */
  36
  37 /*
  38  * The Core code provides basic services for accessing and managing the
  39  * DWC_otg hardware. These services are used by both the Host Controller
  40  * Driver and the Peripheral Controller Driver.
  41  */
  42 #include <linux/kernel.h>
  43 #include <linux/module.h>
  44 #include <linux/moduleparam.h>
  45 #include <linux/spinlock.h>
  46 #include <linux/interrupt.h>
  47 #include <linux/dma-mapping.h>
  48 #include <linux/delay.h>
  49 #include <linux/io.h>
  50 #include <linux/slab.h>
  51 #include <linux/usb.h>
  52
  53 #include <linux/usb/hcd.h>
  54 #include <linux/usb/ch11.h>
  55
  56 #include "core.h"
  57 #include "hcd.h"
  58
  59 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
  60 /**
  61  * dwc2_backup_host_registers() - Backup controller host registers.
  62  * When suspending usb bus, registers needs to be backuped
  63  * if controller power is disabled once suspended.
  64  *
  65  * @hsotg: Programming view of the DWC_otg controller
  66  */
  67 static int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
  68 {
  69         struct dwc2_hregs_backup *hr;
  70         int i;
  71
  72         dev_dbg(hsotg->dev, "%s\n", __func__);
  73
  74         /* Backup Host regs */
  75         hr = &hsotg->hr_backup;
  76         hr->hcfg = dwc2_readl(hsotg->regs + HCFG);
  77         hr->haintmsk = dwc2_readl(hsotg->regs + HAINTMSK);
  78         for (i = 0; i < hsotg->core_params->host_channels; ++i)
  79                 hr->hcintmsk[i] = dwc2_readl(hsotg->regs + HCINTMSK(i));
  80
  81         hr->hprt0 = dwc2_read_hprt0(hsotg);
  82         hr->hfir = dwc2_readl(hsotg->regs + HFIR);
  83         hr->valid = true;
  84
  85         return 0;
  86 }
  87
  88 /**
  89  * dwc2_restore_host_registers() - Restore controller host registers.
  90  * When resuming usb bus, device registers needs to be restored
  91  * if controller power were disabled.
  92  *
  93  * @hsotg: Programming view of the DWC_otg controller
  94  */
  95 static int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
  96 {
  97         struct dwc2_hregs_backup *hr;
  98         int i;
  99
 100         dev_dbg(hsotg->dev, "%s\n", __func__);
 101
 102         /* Restore host regs */
 103         hr = &hsotg->hr_backup;
 104         if (!hr->valid) {
 105                 dev_err(hsotg->dev, "%s: no host registers to restore\n",
 106                                 __func__);
 107                 return -EINVAL;
 108         }
 109         hr->valid = false;
 110
 111         dwc2_writel(hr->hcfg, hsotg->regs + HCFG);
 112         dwc2_writel(hr->haintmsk, hsotg->regs + HAINTMSK);
 113
 114         for (i = 0; i < hsotg->core_params->host_channels; ++i)
 115                 dwc2_writel(hr->hcintmsk[i], hsotg->regs + HCINTMSK(i));
 116
 117         dwc2_writel(hr->hprt0, hsotg->regs + HPRT0);
 118         dwc2_writel(hr->hfir, hsotg->regs + HFIR);
 119         hsotg->frame_number = 0;
 120
 121         return 0;
 122 }
 123 #else
 124 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
 125 { return 0; }
 126
 127 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
 128 { return 0; }
 129 #endif
 130
 131 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
 132         IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
 133 /**
 134  * dwc2_backup_device_registers() - Backup controller device registers.
 135  * When suspending usb bus, registers needs to be backuped
 136  * if controller power is disabled once suspended.
 137  *
 138  * @hsotg: Programming view of the DWC_otg controller
 139  */
 140 static int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
 141 {
 142         struct dwc2_dregs_backup *dr;
 143         int i;
 144
 145         dev_dbg(hsotg->dev, "%s\n", __func__);
 146
 147         /* Backup dev regs */
 148         dr = &hsotg->dr_backup;
 149
 150         dr->dcfg = dwc2_readl(hsotg->regs + DCFG);
 151         dr->dctl = dwc2_readl(hsotg->regs + DCTL);
 152         dr->daintmsk = dwc2_readl(hsotg->regs + DAINTMSK);
 153         dr->diepmsk = dwc2_readl(hsotg->regs + DIEPMSK);
 154         dr->doepmsk = dwc2_readl(hsotg->regs + DOEPMSK);
 155
 156         for (i = 0; i < hsotg->num_of_eps; i++) {
 157                 /* Backup IN EPs */
 158                 dr->diepctl[i] = dwc2_readl(hsotg->regs + DIEPCTL(i));
 159
 160                 /* Ensure DATA PID is correctly configured */
 161                 if (dr->diepctl[i] & DXEPCTL_DPID)
 162                         dr->diepctl[i] |= DXEPCTL_SETD1PID;
 163                 else
 164                         dr->diepctl[i] |= DXEPCTL_SETD0PID;
 165
 166                 dr->dieptsiz[i] = dwc2_readl(hsotg->regs + DIEPTSIZ(i));
 167                 dr->diepdma[i] = dwc2_readl(hsotg->regs + DIEPDMA(i));
 168
 169                 /* Backup OUT EPs */
 170                 dr->doepctl[i] = dwc2_readl(hsotg->regs + DOEPCTL(i));
 171
 172                 /* Ensure DATA PID is correctly configured */
 173                 if (dr->doepctl[i] & DXEPCTL_DPID)
 174                         dr->doepctl[i] |= DXEPCTL_SETD1PID;
 175                 else
 176                         dr->doepctl[i] |= DXEPCTL_SETD0PID;
 177
 178                 dr->doeptsiz[i] = dwc2_readl(hsotg->regs + DOEPTSIZ(i));
 179                 dr->doepdma[i] = dwc2_readl(hsotg->regs + DOEPDMA(i));
 180         }
 181         dr->valid = true;
 182         return 0;
 183 }
 184
 185 /**
 186  * dwc2_restore_device_registers() - Restore controller device registers.
 187  * When resuming usb bus, device registers needs to be restored
 188  * if controller power were disabled.
 189  *
 190  * @hsotg: Programming view of the DWC_otg controller
 191  */
 192 static int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
 193 {
 194         struct dwc2_dregs_backup *dr;
 195         u32 dctl;
 196         int i;
 197
 198         dev_dbg(hsotg->dev, "%s\n", __func__);
 199
 200         /* Restore dev regs */
 201         dr = &hsotg->dr_backup;
 202         if (!dr->valid) {
 203                 dev_err(hsotg->dev, "%s: no device registers to restore\n",
 204                                 __func__);
 205                 return -EINVAL;
 206         }
 207         dr->valid = false;
 208
 209         dwc2_writel(dr->dcfg, hsotg->regs + DCFG);
 210         dwc2_writel(dr->dctl, hsotg->regs + DCTL);
 211         dwc2_writel(dr->daintmsk, hsotg->regs + DAINTMSK);
 212         dwc2_writel(dr->diepmsk, hsotg->regs + DIEPMSK);
 213         dwc2_writel(dr->doepmsk, hsotg->regs + DOEPMSK);
 214
 215         for (i = 0; i < hsotg->num_of_eps; i++) {
 216                 /* Restore IN EPs */
 217                 dwc2_writel(dr->diepctl[i], hsotg->regs + DIEPCTL(i));
 218                 dwc2_writel(dr->dieptsiz[i], hsotg->regs + DIEPTSIZ(i));
 219                 dwc2_writel(dr->diepdma[i], hsotg->regs + DIEPDMA(i));
 220
 221                 /* Restore OUT EPs */
 222                 dwc2_writel(dr->doepctl[i], hsotg->regs + DOEPCTL(i));
 223                 dwc2_writel(dr->doeptsiz[i], hsotg->regs + DOEPTSIZ(i));
 224                 dwc2_writel(dr->doepdma[i], hsotg->regs + DOEPDMA(i));
 225         }
 226
 227         /* Set the Power-On Programming done bit */
 228         dctl = dwc2_readl(hsotg->regs + DCTL);
 229         dctl |= DCTL_PWRONPRGDONE;
 230         dwc2_writel(dctl, hsotg->regs + DCTL);
 231
 232         return 0;
 233 }
 234 #else
 235 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
 236 { return 0; }
 237
 238 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
 239 { return 0; }
 240 #endif
 241
 242 /**
 243  * dwc2_backup_global_registers() - Backup global controller registers.
 244  * When suspending usb bus, registers needs to be backuped
 245  * if controller power is disabled once suspended.
 246  *
 247  * @hsotg: Programming view of the DWC_otg controller
 248  */
 249 static int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
 250 {
 251         struct dwc2_gregs_backup *gr;
 252         int i;
 253
 254         /* Backup global regs */
 255         gr = &hsotg->gr_backup;
 256
 257         gr->gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 258         gr->gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
 259         gr->gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 260         gr->gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 261         gr->grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 262         gr->gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
 263         gr->hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
 264         gr->gdfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
 265         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 266                 gr->dtxfsiz[i] = dwc2_readl(hsotg->regs + DPTXFSIZN(i));
 267
 268         gr->valid = true;
 269         return 0;
 270 }
 271
 272 /**
 273  * dwc2_restore_global_registers() - Restore controller global registers.
 274  * When resuming usb bus, device registers needs to be restored
 275  * if controller power were disabled.
 276  *
 277  * @hsotg: Programming view of the DWC_otg controller
 278  */
 279 static int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
 280 {
 281         struct dwc2_gregs_backup *gr;
 282         int i;
 283
 284         dev_dbg(hsotg->dev, "%s\n", __func__);
 285
 286         /* Restore global regs */
 287         gr = &hsotg->gr_backup;
 288         if (!gr->valid) {
 289                 dev_err(hsotg->dev, "%s: no global registers to restore\n",
 290                                 __func__);
 291                 return -EINVAL;
 292         }
 293         gr->valid = false;
 294
 295         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 296         dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
 297         dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
 298         dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
 299         dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
 300         dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
 301         dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
 302         dwc2_writel(gr->hptxfsiz, hsotg->regs + HPTXFSIZ);
 303         dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
 304         for (i = 0; i < MAX_EPS_CHANNELS; i++)
 305                 dwc2_writel(gr->dtxfsiz[i], hsotg->regs + DPTXFSIZN(i));
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * dwc2_exit_hibernation() - Exit controller from Partial Power Down.
 312  *
 313  * @hsotg: Programming view of the DWC_otg controller
 314  * @restore: Controller registers need to be restored
 315  */
 316 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore)
 317 {
 318         u32 pcgcctl;
 319         int ret = 0;
 320
 321         if (!hsotg->core_params->hibernation)
 322                 return -ENOTSUPP;
 323
 324         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 325         pcgcctl &= ~PCGCTL_STOPPCLK;
 326         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 327
 328         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 329         pcgcctl &= ~PCGCTL_PWRCLMP;
 330         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 331
 332         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 333         pcgcctl &= ~PCGCTL_RSTPDWNMODULE;
 334         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 335
 336         udelay(100);
 337         if (restore) {
 338                 ret = dwc2_restore_global_registers(hsotg);
 339                 if (ret) {
 340                         dev_err(hsotg->dev, "%s: failed to restore registers\n",
 341                                         __func__);
 342                         return ret;
 343                 }
 344                 if (dwc2_is_host_mode(hsotg)) {
 345                         ret = dwc2_restore_host_registers(hsotg);
 346                         if (ret) {
 347                                 dev_err(hsotg->dev, "%s: failed to restore host registers\n",
 348                                                 __func__);
 349                                 return ret;
 350                         }
 351                 } else {
 352                         ret = dwc2_restore_device_registers(hsotg);
 353                         if (ret) {
 354                                 dev_err(hsotg->dev, "%s: failed to restore device registers\n",
 355                                                 __func__);
 356                                 return ret;
 357                         }
 358                 }
 359         }
 360
 361         return ret;
 362 }
 363
 364 /**
 365  * dwc2_enter_hibernation() - Put controller in Partial Power Down.
 366  *
 367  * @hsotg: Programming view of the DWC_otg controller
 368  */
 369 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg)
 370 {
 371         u32 pcgcctl;
 372         int ret = 0;
 373
 374         if (!hsotg->core_params->hibernation)
 375                 return -ENOTSUPP;
 376
 377         /* Backup all registers */
 378         ret = dwc2_backup_global_registers(hsotg);
 379         if (ret) {
 380                 dev_err(hsotg->dev, "%s: failed to backup global registers\n",
 381                                 __func__);
 382                 return ret;
 383         }
 384
 385         if (dwc2_is_host_mode(hsotg)) {
 386                 ret = dwc2_backup_host_registers(hsotg);
 387                 if (ret) {
 388                         dev_err(hsotg->dev, "%s: failed to backup host registers\n",
 389                                         __func__);
 390                         return ret;
 391                 }
 392         } else {
 393                 ret = dwc2_backup_device_registers(hsotg);
 394                 if (ret) {
 395                         dev_err(hsotg->dev, "%s: failed to backup device registers\n",
 396                                         __func__);
 397                         return ret;
 398                 }
 399         }
 400
 401         /*
 402          * Clear any pending interrupts since dwc2 will not be able to
 403          * clear them after entering hibernation.
 404          */
 405         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 406
 407         /* Put the controller in low power state */
 408         pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
 409
 410         pcgcctl |= PCGCTL_PWRCLMP;
 411         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 412         ndelay(20);
 413
 414         pcgcctl |= PCGCTL_RSTPDWNMODULE;
 415         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 416         ndelay(20);
 417
 418         pcgcctl |= PCGCTL_STOPPCLK;
 419         dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
 420
 421         return ret;
 422 }
 423
 424 /**
 425  * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
 426  * used in both device and host modes
 427  *
 428  * @hsotg: Programming view of the DWC_otg controller
 429  */
 430 static void dwc2_enable_common_interrupts(struct dwc2_hsotg *hsotg)
 431 {
 432         u32 intmsk;
 433
 434         /* Clear any pending OTG Interrupts */
 435         dwc2_writel(0xffffffff, hsotg->regs + GOTGINT);
 436
 437         /* Clear any pending interrupts */
 438         dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
 439
 440         /* Enable the interrupts in the GINTMSK */
 441         intmsk = GINTSTS_MODEMIS | GINTSTS_OTGINT;
 442
 443         if (hsotg->core_params->dma_enable <= 0)
 444                 intmsk |= GINTSTS_RXFLVL;
 445         if (hsotg->core_params->external_id_pin_ctl <= 0)
 446                 intmsk |= GINTSTS_CONIDSTSCHNG;
 447
 448         intmsk |= GINTSTS_WKUPINT | GINTSTS_USBSUSP |
 449                   GINTSTS_SESSREQINT;
 450
 451         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 452 }
 453
 454 /*
 455  * Initializes the FSLSPClkSel field of the HCFG register depending on the
 456  * PHY type
 457  */
 458 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
 459 {
 460         u32 hcfg, val;
 461
 462         if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 463              hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 464              hsotg->core_params->ulpi_fs_ls > 0) ||
 465             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 466                 /* Full speed PHY */
 467                 val = HCFG_FSLSPCLKSEL_48_MHZ;
 468         } else {
 469                 /* High speed PHY running at full speed or high speed */
 470                 val = HCFG_FSLSPCLKSEL_30_60_MHZ;
 471         }
 472
 473         dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
 474         hcfg = dwc2_readl(hsotg->regs + HCFG);
 475         hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
 476         hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
 477         dwc2_writel(hcfg, hsotg->regs + HCFG);
 478 }
 479
 480 /*
 481  * Do core a soft reset of the core.  Be careful with this because it
 482  * resets all the internal state machines of the core.
 483  */
 484 int dwc2_core_reset(struct dwc2_hsotg *hsotg)
 485 {
 486         u32 greset;
 487         int count = 0;
 488         u32 gusbcfg;
 489
 490         dev_vdbg(hsotg->dev, "%s()\n", __func__);
 491
 492         /* Core Soft Reset */
 493         greset = dwc2_readl(hsotg->regs + GRSTCTL);
 494         greset |= GRSTCTL_CSFTRST;
 495         dwc2_writel(greset, hsotg->regs + GRSTCTL);
 496         do {
 497                 udelay(1);
 498                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 499                 if (++count > 50) {
 500                         dev_warn(hsotg->dev,
 501                                  "%s() HANG! Soft Reset GRSTCTL=%0x\n",
 502                                  __func__, greset);
 503                         return -EBUSY;
 504                 }
 505         } while (greset & GRSTCTL_CSFTRST);
 506
 507         /* Wait for AHB master IDLE state */
 508         count = 0;
 509         do {
 510                 udelay(1);
 511                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
 512                 if (++count > 50) {
 513                         dev_warn(hsotg->dev,
 514                                  "%s() HANG! AHB Idle GRSTCTL=%0x\n",
 515                                  __func__, greset);
 516                         return -EBUSY;
 517                 }
 518         } while (!(greset & GRSTCTL_AHBIDLE));
 519
 520         if (hsotg->dr_mode == USB_DR_MODE_HOST) {
 521                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 522                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 523                 gusbcfg |= GUSBCFG_FORCEHOSTMODE;
 524                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 525         } else if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) {
 526                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 527                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 528                 gusbcfg |= GUSBCFG_FORCEDEVMODE;
 529                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 530         } else if (hsotg->dr_mode == USB_DR_MODE_OTG) {
 531                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 532                 gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
 533                 gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
 534                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
 535         }
 536
 537         /*
 538          * NOTE: This long sleep is _very_ important, otherwise the core will
 539          * not stay in host mode after a connector ID change!
 540          */
 541         usleep_range(150000, 160000);
 542
 543         return 0;
 544 }
 545
 546 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 547 {
 548         u32 usbcfg, i2cctl;
 549         int retval = 0;
 550
 551         /*
 552          * core_init() is now called on every switch so only call the
 553          * following for the first time through
 554          */
 555         if (select_phy) {
 556                 dev_dbg(hsotg->dev, "FS PHY selected\n");
 557
 558                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 559                 if (!(usbcfg & GUSBCFG_PHYSEL)) {
 560                         usbcfg |= GUSBCFG_PHYSEL;
 561                         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 562
 563                         /* Reset after a PHY select */
 564                         retval = dwc2_core_reset(hsotg);
 565
 566                         if (retval) {
 567                                 dev_err(hsotg->dev,
 568                                         "%s: Reset failed, aborting", __func__);
 569                                 return retval;
 570                         }
 571                 }
 572         }
 573
 574         /*
 575          * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
 576          * do this on HNP Dev/Host mode switches (done in dev_init and
 577          * host_init).
 578          */
 579         if (dwc2_is_host_mode(hsotg))
 580                 dwc2_init_fs_ls_pclk_sel(hsotg);
 581
 582         if (hsotg->core_params->i2c_enable > 0) {
 583                 dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
 584
 585                 /* Program GUSBCFG.OtgUtmiFsSel to I2C */
 586                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 587                 usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
 588                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 589
 590                 /* Program GI2CCTL.I2CEn */
 591                 i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
 592                 i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
 593                 i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
 594                 i2cctl &= ~GI2CCTL_I2CEN;
 595                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 596                 i2cctl |= GI2CCTL_I2CEN;
 597                 dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
 598         }
 599
 600         return retval;
 601 }
 602
 603 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 604 {
 605         u32 usbcfg, usbcfg_old;
 606         int retval = 0;
 607
 608         if (!select_phy)
 609                 return 0;
 610
 611         usbcfg = usbcfg_old = dwc2_readl(hsotg->regs + GUSBCFG);
 612
 613         /*
 614          * HS PHY parameters. These parameters are preserved during soft reset
 615          * so only program the first time. Do a soft reset immediately after
 616          * setting phyif.
 617          */
 618         switch (hsotg->core_params->phy_type) {
 619         case DWC2_PHY_TYPE_PARAM_ULPI:
 620                 /* ULPI interface */
 621                 dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
 622                 usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
 623                 usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
 624                 if (hsotg->core_params->phy_ulpi_ddr > 0)
 625                         usbcfg |= GUSBCFG_DDRSEL;
 626                 break;
 627         case DWC2_PHY_TYPE_PARAM_UTMI:
 628                 /* UTMI+ interface */
 629                 dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
 630                 usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
 631                 if (hsotg->core_params->phy_utmi_width == 16)
 632                         usbcfg |= GUSBCFG_PHYIF16;
 633                 break;
 634         default:
 635                 dev_err(hsotg->dev, "FS PHY selected at HS!\n");
 636                 break;
 637         }
 638
 639         if (usbcfg != usbcfg_old) {
 640                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 641
 642                 /* Reset after setting the PHY parameters */
 643                 retval = dwc2_core_reset(hsotg);
 644                 if (retval) {
 645                         dev_err(hsotg->dev,
 646                                 "%s: Reset failed, aborting", __func__);
 647                         return retval;
 648                 }
 649         }
 650
 651         return retval;
 652 }
 653
 654 static int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
 655 {
 656         u32 usbcfg;
 657         int retval = 0;
 658
 659         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL &&
 660             hsotg->core_params->phy_type == DWC2_PHY_TYPE_PARAM_FS) {
 661                 /* If FS mode with FS PHY */
 662                 retval = dwc2_fs_phy_init(hsotg, select_phy);
 663                 if (retval)
 664                         return retval;
 665         } else {
 666                 /* High speed PHY */
 667                 retval = dwc2_hs_phy_init(hsotg, select_phy);
 668                 if (retval)
 669                         return retval;
 670         }
 671
 672         if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
 673             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
 674             hsotg->core_params->ulpi_fs_ls > 0) {
 675                 dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
 676                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 677                 usbcfg |= GUSBCFG_ULPI_FS_LS;
 678                 usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
 679                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 680         } else {
 681                 usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 682                 usbcfg &= ~GUSBCFG_ULPI_FS_LS;
 683                 usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
 684                 dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 685         }
 686
 687         return retval;
 688 }
 689
 690 static int dwc2_gahbcfg_init(struct dwc2_hsotg *hsotg)
 691 {
 692         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
 693
 694         switch (hsotg->hw_params.arch) {
 695         case GHWCFG2_EXT_DMA_ARCH:
 696                 dev_err(hsotg->dev, "External DMA Mode not supported\n");
 697                 return -EINVAL;
 698
 699         case GHWCFG2_INT_DMA_ARCH:
 700                 dev_dbg(hsotg->dev, "Internal DMA Mode\n");
 701                 if (hsotg->core_params->ahbcfg != -1) {
 702                         ahbcfg &= GAHBCFG_CTRL_MASK;
 703                         ahbcfg |= hsotg->core_params->ahbcfg &
 704                                   ~GAHBCFG_CTRL_MASK;
 705                 }
 706                 break;
 707
 708         case GHWCFG2_SLAVE_ONLY_ARCH:
 709         default:
 710                 dev_dbg(hsotg->dev, "Slave Only Mode\n");
 711                 break;
 712         }
 713
 714         dev_dbg(hsotg->dev, "dma_enable:%d dma_desc_enable:%d\n",
 715                 hsotg->core_params->dma_enable,
 716                 hsotg->core_params->dma_desc_enable);
 717
 718         if (hsotg->core_params->dma_enable > 0) {
 719                 if (hsotg->core_params->dma_desc_enable > 0)
 720                         dev_dbg(hsotg->dev, "Using Descriptor DMA mode\n");
 721                 else
 722                         dev_dbg(hsotg->dev, "Using Buffer DMA mode\n");
 723         } else {
 724                 dev_dbg(hsotg->dev, "Using Slave mode\n");
 725                 hsotg->core_params->dma_desc_enable = 0;
 726         }
 727
 728         if (hsotg->core_params->dma_enable > 0)
 729                 ahbcfg |= GAHBCFG_DMA_EN;
 730
 731         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
 732
 733         return 0;
 734 }
 735
 736 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg)
 737 {
 738         u32 usbcfg;
 739
 740         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 741         usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
 742
 743         switch (hsotg->hw_params.op_mode) {
 744         case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
 745                 if (hsotg->core_params->otg_cap ==
 746                                 DWC2_CAP_PARAM_HNP_SRP_CAPABLE)
 747                         usbcfg |= GUSBCFG_HNPCAP;
 748                 if (hsotg->core_params->otg_cap !=
 749                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 750                         usbcfg |= GUSBCFG_SRPCAP;
 751                 break;
 752
 753         case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
 754         case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
 755         case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
 756                 if (hsotg->core_params->otg_cap !=
 757                                 DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE)
 758                         usbcfg |= GUSBCFG_SRPCAP;
 759                 break;
 760
 761         case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
 762         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
 763         case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
 764         default:
 765                 break;
 766         }
 767
 768         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 769 }
 770
 771 /**
 772  * dwc2_core_init() - Initializes the DWC_otg controller registers and
 773  * prepares the core for device mode or host mode operation
 774  *
 775  * @hsotg:         Programming view of the DWC_otg controller
 776  * @initial_setup: If true then this is the first init for this instance.
 777  */
 778 int dwc2_core_init(struct dwc2_hsotg *hsotg, bool initial_setup)
 779 {
 780         u32 usbcfg, otgctl;
 781         int retval;
 782
 783         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
 784
 785         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
 786
 787         /* Set ULPI External VBUS bit if needed */
 788         usbcfg &= ~GUSBCFG_ULPI_EXT_VBUS_DRV;
 789         if (hsotg->core_params->phy_ulpi_ext_vbus ==
 790                                 DWC2_PHY_ULPI_EXTERNAL_VBUS)
 791                 usbcfg |= GUSBCFG_ULPI_EXT_VBUS_DRV;
 792
 793         /* Set external TS Dline pulsing bit if needed */
 794         usbcfg &= ~GUSBCFG_TERMSELDLPULSE;
 795         if (hsotg->core_params->ts_dline > 0)
 796                 usbcfg |= GUSBCFG_TERMSELDLPULSE;
 797
 798         dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
 799
 800         /*
 801          * Reset the Controller
 802          *
 803          * We only need to reset the controller if this is a re-init.
 804          * For the first init we know for sure that earlier code reset us (it
 805          * needed to in order to properly detect various parameters).
 806          */
 807         if (!initial_setup) {
 808                 retval = dwc2_core_reset(hsotg);
 809                 if (retval) {
 810                         dev_err(hsotg->dev, "%s(): Reset failed, aborting\n",
 811                                         __func__);
 812                         return retval;
 813                 }
 814         }
 815
 816         /*
 817          * This needs to happen in FS mode before any other programming occurs
 818          */
 819         retval = dwc2_phy_init(hsotg, initial_setup);
 820         if (retval)
 821                 return retval;
 822
 823         /* Program the GAHBCFG Register */
 824         retval = dwc2_gahbcfg_init(hsotg);
 825         if (retval)
 826                 return retval;
 827
 828         /* Program the GUSBCFG register */
 829         dwc2_gusbcfg_init(hsotg);
 830
 831         /* Program the GOTGCTL register */
 832         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
 833         otgctl &= ~GOTGCTL_OTGVER;
 834         if (hsotg->core_params->otg_ver > 0)
 835                 otgctl |= GOTGCTL_OTGVER;
 836         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
 837         dev_dbg(hsotg->dev, "OTG VER PARAM: %d\n", hsotg->core_params->otg_ver);
 838
 839         /* Clear the SRP success bit for FS-I2c */
 840         hsotg->srp_success = 0;
 841
 842         /* Enable common interrupts */
 843         dwc2_enable_common_interrupts(hsotg);
 844
 845         /*
 846          * Do device or host initialization based on mode during PCD and
 847          * HCD initialization
 848          */
 849         if (dwc2_is_host_mode(hsotg)) {
 850                 dev_dbg(hsotg->dev, "Host Mode\n");
 851                 hsotg->op_state = OTG_STATE_A_HOST;
 852         } else {
 853                 dev_dbg(hsotg->dev, "Device Mode\n");
 854                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 855         }
 856
 857         return 0;
 858 }
 859
 860 /**
 861  * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
 862  *
 863  * @hsotg: Programming view of DWC_otg controller
 864  */
 865 void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg)
 866 {
 867         u32 intmsk;
 868
 869         dev_dbg(hsotg->dev, "%s()\n", __func__);
 870
 871         /* Disable all interrupts */
 872         dwc2_writel(0, hsotg->regs + GINTMSK);
 873         dwc2_writel(0, hsotg->regs + HAINTMSK);
 874
 875         /* Enable the common interrupts */
 876         dwc2_enable_common_interrupts(hsotg);
 877
 878         /* Enable host mode interrupts without disturbing common interrupts */
 879         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 880         intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
 881         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 882 }
 883
 884 /**
 885  * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
 886  *
 887  * @hsotg: Programming view of DWC_otg controller
 888  */
 889 void dwc2_disable_host_interrupts(struct dwc2_hsotg *hsotg)
 890 {
 891         u32 intmsk = dwc2_readl(hsotg->regs + GINTMSK);
 892
 893         /* Disable host mode interrupts without disturbing common interrupts */
 894         intmsk &= ~(GINTSTS_SOF | GINTSTS_PRTINT | GINTSTS_HCHINT |
 895                     GINTSTS_PTXFEMP | GINTSTS_NPTXFEMP | GINTSTS_DISCONNINT);
 896         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
 897 }
 898
 899 /*
 900  * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
 901  * For system that have a total fifo depth that is smaller than the default
 902  * RX + TX fifo size.
 903  *
 904  * @hsotg: Programming view of DWC_otg controller
 905  */
 906 static void dwc2_calculate_dynamic_fifo(struct dwc2_hsotg *hsotg)
 907 {
 908         struct dwc2_core_params *params = hsotg->core_params;
 909         struct dwc2_hw_params *hw = &hsotg->hw_params;
 910         u32 rxfsiz, nptxfsiz, ptxfsiz, total_fifo_size;
 911
 912         total_fifo_size = hw->total_fifo_size;
 913         rxfsiz = params->host_rx_fifo_size;
 914         nptxfsiz = params->host_nperio_tx_fifo_size;
 915         ptxfsiz = params->host_perio_tx_fifo_size;
 916
 917         /*
 918          * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
 919          * allocation with support for high bandwidth endpoints. Synopsys
 920          * defines MPS(Max Packet size) for a periodic EP=1024, and for
 921          * non-periodic as 512.
 922          */
 923         if (total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)) {
 924                 /*
 925                  * For Buffer DMA mode/Scatter Gather DMA mode
 926                  * 2 * ((Largest Packet size / 4) + 1 + 1) + n
 927                  * with n = number of host channel.
 928                  * 2 * ((1024/4) + 2) = 516
 929                  */
 930                 rxfsiz = 516 + hw->host_channels;
 931
 932                 /*
 933                  * min non-periodic tx fifo depth
 934                  * 2 * (largest non-periodic USB packet used / 4)
 935                  * 2 * (512/4) = 256
 936                  */
 937                 nptxfsiz = 256;
 938
 939                 /*
 940                  * min periodic tx fifo depth
 941                  * (largest packet size*MC)/4
 942                  * (1024 * 3)/4 = 768
 943                  */
 944                 ptxfsiz = 768;
 945
 946                 params->host_rx_fifo_size = rxfsiz;
 947                 params->host_nperio_tx_fifo_size = nptxfsiz;
 948                 params->host_perio_tx_fifo_size = ptxfsiz;
 949         }
 950
 951         /*
 952          * If the summation of RX, NPTX and PTX fifo sizes is still
 953          * bigger than the total_fifo_size, then we have a problem.
 954          *
 955          * We won't be able to allocate as many endpoints. Right now,
 956          * we're just printing an error message, but ideally this FIFO
 957          * allocation algorithm would be improved in the future.
 958          *
 959          * FIXME improve this FIFO allocation algorithm.
 960          */
 961         if (unlikely(total_fifo_size < (rxfsiz + nptxfsiz + ptxfsiz)))
 962                 dev_err(hsotg->dev, "invalid fifo sizes\n");
 963 }
 964
 965 static void dwc2_config_fifos(struct dwc2_hsotg *hsotg)
 966 {
 967         struct dwc2_core_params *params = hsotg->core_params;
 968         u32 nptxfsiz, hptxfsiz, dfifocfg, grxfsiz;
 969
 970         if (!params->enable_dynamic_fifo)
 971                 return;
 972
 973         dwc2_calculate_dynamic_fifo(hsotg);
 974
 975         /* Rx FIFO */
 976         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
 977         dev_dbg(hsotg->dev, "initial grxfsiz=%08x\n", grxfsiz);
 978         grxfsiz &= ~GRXFSIZ_DEPTH_MASK;
 979         grxfsiz |= params->host_rx_fifo_size <<
 980                    GRXFSIZ_DEPTH_SHIFT & GRXFSIZ_DEPTH_MASK;
 981         dwc2_writel(grxfsiz, hsotg->regs + GRXFSIZ);
 982         dev_dbg(hsotg->dev, "new grxfsiz=%08x\n",
 983                 dwc2_readl(hsotg->regs + GRXFSIZ));
 984
 985         /* Non-periodic Tx FIFO */
 986         dev_dbg(hsotg->dev, "initial gnptxfsiz=%08x\n",
 987                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 988         nptxfsiz = params->host_nperio_tx_fifo_size <<
 989                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
 990         nptxfsiz |= params->host_rx_fifo_size <<
 991                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
 992         dwc2_writel(nptxfsiz, hsotg->regs + GNPTXFSIZ);
 993         dev_dbg(hsotg->dev, "new gnptxfsiz=%08x\n",
 994                 dwc2_readl(hsotg->regs + GNPTXFSIZ));
 995
 996         /* Periodic Tx FIFO */
 997         dev_dbg(hsotg->dev, "initial hptxfsiz=%08x\n",
 998                 dwc2_readl(hsotg->regs + HPTXFSIZ));
 999         hptxfsiz = params->host_perio_tx_fifo_size <<
1000                    FIFOSIZE_DEPTH_SHIFT & FIFOSIZE_DEPTH_MASK;
1001         hptxfsiz |= (params->host_rx_fifo_size +
1002                      params->host_nperio_tx_fifo_size) <<
1003                     FIFOSIZE_STARTADDR_SHIFT & FIFOSIZE_STARTADDR_MASK;
1004         dwc2_writel(hptxfsiz, hsotg->regs + HPTXFSIZ);
1005         dev_dbg(hsotg->dev, "new hptxfsiz=%08x\n",
1006                 dwc2_readl(hsotg->regs + HPTXFSIZ));
1007
1008         if (hsotg->core_params->en_multiple_tx_fifo > 0 &&
1009             hsotg->hw_params.snpsid <= DWC2_CORE_REV_2_94a) {
1010                 /*
1011                  * Global DFIFOCFG calculation for Host mode -
1012                  * include RxFIFO, NPTXFIFO and HPTXFIFO
1013                  */
1014                 dfifocfg = dwc2_readl(hsotg->regs + GDFIFOCFG);
1015                 dfifocfg &= ~GDFIFOCFG_EPINFOBASE_MASK;
1016                 dfifocfg |= (params->host_rx_fifo_size +
1017                              params->host_nperio_tx_fifo_size +
1018                              params->host_perio_tx_fifo_size) <<
1019                             GDFIFOCFG_EPINFOBASE_SHIFT &
1020                             GDFIFOCFG_EPINFOBASE_MASK;
1021                 dwc2_writel(dfifocfg, hsotg->regs + GDFIFOCFG);
1022         }
1023 }
1024
1025 /**
1026  * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
1027  * Host mode
1028  *
1029  * @hsotg: Programming view of DWC_otg controller
1030  *
1031  * This function flushes the Tx and Rx FIFOs and flushes any entries in the
1032  * request queues. Host channels are reset to ensure that they are ready for
1033  * performing transfers.
1034  */
1035 void dwc2_core_host_init(struct dwc2_hsotg *hsotg)
1036 {
1037         u32 hcfg, hfir, otgctl;
1038
1039         dev_dbg(hsotg->dev, "%s(%p)\n", __func__, hsotg);
1040
1041         /* Restart the Phy Clock */
1042         dwc2_writel(0, hsotg->regs + PCGCTL);
1043
1044         /* Initialize Host Configuration Register */
1045         dwc2_init_fs_ls_pclk_sel(hsotg);
1046         if (hsotg->core_params->speed == DWC2_SPEED_PARAM_FULL) {
1047                 hcfg = dwc2_readl(hsotg->regs + HCFG);
1048                 hcfg |= HCFG_FSLSSUPP;
1049                 dwc2_writel(hcfg, hsotg->regs + HCFG);
1050         }
1051
1052         /*
1053          * This bit allows dynamic reloading of the HFIR register during
1054          * runtime. This bit needs to be programmed during initial configuration
1055          * and its value must not be changed during runtime.
1056          */
1057         if (hsotg->core_params->reload_ctl > 0) {
1058                 hfir = dwc2_readl(hsotg->regs + HFIR);
1059                 hfir |= HFIR_RLDCTRL;
1060                 dwc2_writel(hfir, hsotg->regs + HFIR);
1061         }
1062
1063         if (hsotg->core_params->dma_desc_enable > 0) {
1064                 u32 op_mode = hsotg->hw_params.op_mode;
1065                 if (hsotg->hw_params.snpsid < DWC2_CORE_REV_2_90a ||
1066                     !hsotg->hw_params.dma_desc_enable ||
1067                     op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE ||
1068                     op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE ||
1069                     op_mode == GHWCFG2_OP_MODE_UNDEFINED) {
1070                         dev_err(hsotg->dev,
1071                                 "Hardware does not support descriptor DMA mode -\n");
1072                         dev_err(hsotg->dev,
1073                                 "falling back to buffer DMA mode.\n");
1074                         hsotg->core_params->dma_desc_enable = 0;
1075                 } else {
1076                         hcfg = dwc2_readl(hsotg->regs + HCFG);
1077                         hcfg |= HCFG_DESCDMA;
1078                         dwc2_writel(hcfg, hsotg->regs + HCFG);
1079                 }
1080         }
1081
1082         /* Configure data FIFO sizes */
1083         dwc2_config_fifos(hsotg);
1084
1085         /* TODO - check this */
1086         /* Clear Host Set HNP Enable in the OTG Control Register */
1087         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1088         otgctl &= ~GOTGCTL_HSTSETHNPEN;
1089         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1090
1091         /* Make sure the FIFOs are flushed */
1092         dwc2_flush_tx_fifo(hsotg, 0x10 /* all TX FIFOs */);
1093         dwc2_flush_rx_fifo(hsotg);
1094
1095         /* Clear Host Set HNP Enable in the OTG Control Register */
1096         otgctl = dwc2_readl(hsotg->regs + GOTGCTL);
1097         otgctl &= ~GOTGCTL_HSTSETHNPEN;
1098         dwc2_writel(otgctl, hsotg->regs + GOTGCTL);
1099
1100         if (hsotg->core_params->dma_desc_enable <= 0) {
1101                 int num_channels, i;
1102                 u32 hcchar;
1103
1104                 /* Flush out any leftover queued requests */
1105                 num_channels = hsotg->core_params->host_channels;
1106                 for (i = 0; i < num_channels; i++) {
1107                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1108                         hcchar &= ~HCCHAR_CHENA;
1109                         hcchar |= HCCHAR_CHDIS;
1110                         hcchar &= ~HCCHAR_EPDIR;
1111                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1112                 }
1113
1114                 /* Halt all channels to put them into a known state */
1115                 for (i = 0; i < num_channels; i++) {
1116                         int count = 0;
1117
1118                         hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1119                         hcchar |= HCCHAR_CHENA | HCCHAR_CHDIS;
1120                         hcchar &= ~HCCHAR_EPDIR;
1121                         dwc2_writel(hcchar, hsotg->regs + HCCHAR(i));
1122                         dev_dbg(hsotg->dev, "%s: Halt channel %d\n",
1123                                 __func__, i);
1124                         do {
1125                                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(i));
1126                                 if (++count > 1000) {
1127                                         dev_err(hsotg->dev,
1128                                                 "Unable to clear enable on channel %d\n",
1129                                                 i);
1130                                         break;
1131                                 }
1132                                 udelay(1);
1133                         } while (hcchar & HCCHAR_CHENA);
1134                 }
1135         }
1136
1137         /* Turn on the vbus power */
1138         dev_dbg(hsotg->dev, "Init: Port Power? op_state=%d\n", hsotg->op_state);
1139         if (hsotg->op_state == OTG_STATE_A_HOST) {
1140                 u32 hprt0 = dwc2_read_hprt0(hsotg);
1141
1142                 dev_dbg(hsotg->dev, "Init: Power Port (%d)\n",
1143                         !!(hprt0 & HPRT0_PWR));
1144                 if (!(hprt0 & HPRT0_PWR)) {
1145                         hprt0 |= HPRT0_PWR;
1146                         dwc2_writel(hprt0, hsotg->regs + HPRT0);
1147                 }
1148         }
1149
1150         dwc2_enable_host_interrupts(hsotg);
1151 }
1152
1153 static void dwc2_hc_enable_slave_ints(struct dwc2_hsotg *hsotg,
1154                                       struct dwc2_host_chan *chan)
1155 {
1156         u32 hcintmsk = HCINTMSK_CHHLTD;
1157
1158         switch (chan->ep_type) {
1159         case USB_ENDPOINT_XFER_CONTROL:
1160         case USB_ENDPOINT_XFER_BULK:
1161                 dev_vdbg(hsotg->dev, "control/bulk\n");
1162                 hcintmsk |= HCINTMSK_XFERCOMPL;
1163                 hcintmsk |= HCINTMSK_STALL;
1164                 hcintmsk |= HCINTMSK_XACTERR;
1165                 hcintmsk |= HCINTMSK_DATATGLERR;
1166                 if (chan->ep_is_in) {
1167                         hcintmsk |= HCINTMSK_BBLERR;
1168                 } else {
1169                         hcintmsk |= HCINTMSK_NAK;
1170                         hcintmsk |= HCINTMSK_NYET;
1171                         if (chan->do_ping)
1172                                 hcintmsk |= HCINTMSK_ACK;
1173                 }
1174
1175                 if (chan->do_split) {
1176                         hcintmsk |= HCINTMSK_NAK;
1177                         if (chan->complete_split)
1178                                 hcintmsk |= HCINTMSK_NYET;
1179                         else
1180                                 hcintmsk |= HCINTMSK_ACK;
1181                 }
1182
1183                 if (chan->error_state)
1184                         hcintmsk |= HCINTMSK_ACK;
1185                 break;
1186
1187         case USB_ENDPOINT_XFER_INT:
1188                 if (dbg_perio())
1189                         dev_vdbg(hsotg->dev, "intr\n");
1190                 hcintmsk |= HCINTMSK_XFERCOMPL;
1191                 hcintmsk |= HCINTMSK_NAK;
1192                 hcintmsk |= HCINTMSK_STALL;
1193                 hcintmsk |= HCINTMSK_XACTERR;
1194                 hcintmsk |= HCINTMSK_DATATGLERR;
1195                 hcintmsk |= HCINTMSK_FRMOVRUN;
1196
1197                 if (chan->ep_is_in)
1198                         hcintmsk |= HCINTMSK_BBLERR;
1199                 if (chan->error_state)
1200                         hcintmsk |= HCINTMSK_ACK;
1201                 if (chan->do_split) {
1202                         if (chan->complete_split)
1203                                 hcintmsk |= HCINTMSK_NYET;
1204                         else
1205                                 hcintmsk |= HCINTMSK_ACK;
1206                 }
1207                 break;
1208
1209         case USB_ENDPOINT_XFER_ISOC:
1210                 if (dbg_perio())
1211                         dev_vdbg(hsotg->dev, "isoc\n");
1212                 hcintmsk |= HCINTMSK_XFERCOMPL;
1213                 hcintmsk |= HCINTMSK_FRMOVRUN;
1214                 hcintmsk |= HCINTMSK_ACK;
1215
1216                 if (chan->ep_is_in) {
1217                         hcintmsk |= HCINTMSK_XACTERR;
1218                         hcintmsk |= HCINTMSK_BBLERR;
1219                 }
1220                 break;
1221         default:
1222                 dev_err(hsotg->dev, "## Unknown EP type ##\n");
1223                 break;
1224         }
1225
1226         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1227         if (dbg_hc(chan))
1228                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1229 }
1230
1231 static void dwc2_hc_enable_dma_ints(struct dwc2_hsotg *hsotg,
1232                                     struct dwc2_host_chan *chan)
1233 {
1234         u32 hcintmsk = HCINTMSK_CHHLTD;
1235
1236         /*
1237          * For Descriptor DMA mode core halts the channel on AHB error.
1238          * Interrupt is not required.
1239          */
1240         if (hsotg->core_params->dma_desc_enable <= 0) {
1241                 if (dbg_hc(chan))
1242                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1243                 hcintmsk |= HCINTMSK_AHBERR;
1244         } else {
1245                 if (dbg_hc(chan))
1246                         dev_vdbg(hsotg->dev, "desc DMA enabled\n");
1247                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1248                         hcintmsk |= HCINTMSK_XFERCOMPL;
1249         }
1250
1251         if (chan->error_state && !chan->do_split &&
1252             chan->ep_type != USB_ENDPOINT_XFER_ISOC) {
1253                 if (dbg_hc(chan))
1254                         dev_vdbg(hsotg->dev, "setting ACK\n");
1255                 hcintmsk |= HCINTMSK_ACK;
1256                 if (chan->ep_is_in) {
1257                         hcintmsk |= HCINTMSK_DATATGLERR;
1258                         if (chan->ep_type != USB_ENDPOINT_XFER_INT)
1259                                 hcintmsk |= HCINTMSK_NAK;
1260                 }
1261         }
1262
1263         dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1264         if (dbg_hc(chan))
1265                 dev_vdbg(hsotg->dev, "set HCINTMSK to %08x\n", hcintmsk);
1266 }
1267
1268 static void dwc2_hc_enable_ints(struct dwc2_hsotg *hsotg,
1269                                 struct dwc2_host_chan *chan)
1270 {
1271         u32 intmsk;
1272
1273         if (hsotg->core_params->dma_enable > 0) {
1274                 if (dbg_hc(chan))
1275                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1276                 dwc2_hc_enable_dma_ints(hsotg, chan);
1277         } else {
1278                 if (dbg_hc(chan))
1279                         dev_vdbg(hsotg->dev, "DMA disabled\n");
1280                 dwc2_hc_enable_slave_ints(hsotg, chan);
1281         }
1282
1283         /* Enable the top level host channel interrupt */
1284         intmsk = dwc2_readl(hsotg->regs + HAINTMSK);
1285         intmsk |= 1 << chan->hc_num;
1286         dwc2_writel(intmsk, hsotg->regs + HAINTMSK);
1287         if (dbg_hc(chan))
1288                 dev_vdbg(hsotg->dev, "set HAINTMSK to %08x\n", intmsk);
1289
1290         /* Make sure host channel interrupts are enabled */
1291         intmsk = dwc2_readl(hsotg->regs + GINTMSK);
1292         intmsk |= GINTSTS_HCHINT;
1293         dwc2_writel(intmsk, hsotg->regs + GINTMSK);
1294         if (dbg_hc(chan))
1295                 dev_vdbg(hsotg->dev, "set GINTMSK to %08x\n", intmsk);
1296 }
1297
1298 /**
1299  * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
1300  * a specific endpoint
1301  *
1302  * @hsotg: Programming view of DWC_otg controller
1303  * @chan:  Information needed to initialize the host channel
1304  *
1305  * The HCCHARn register is set up with the characteristics specified in chan.
1306  * Host channel interrupts that may need to be serviced while this transfer is
1307  * in progress are enabled.
1308  */
1309 void dwc2_hc_init(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1310 {
1311         u8 hc_num = chan->hc_num;
1312         u32 hcintmsk;
1313         u32 hcchar;
1314         u32 hcsplt = 0;
1315
1316         if (dbg_hc(chan))
1317                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1318
1319         /* Clear old interrupt conditions for this host channel */
1320         hcintmsk = 0xffffffff;
1321         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1322         dwc2_writel(hcintmsk, hsotg->regs + HCINT(hc_num));
1323
1324         /* Enable channel interrupts required for this transfer */
1325         dwc2_hc_enable_ints(hsotg, chan);
1326
1327         /*
1328          * Program the HCCHARn register with the endpoint characteristics for
1329          * the current transfer
1330          */
1331         hcchar = chan->dev_addr << HCCHAR_DEVADDR_SHIFT & HCCHAR_DEVADDR_MASK;
1332         hcchar |= chan->ep_num << HCCHAR_EPNUM_SHIFT & HCCHAR_EPNUM_MASK;
1333         if (chan->ep_is_in)
1334                 hcchar |= HCCHAR_EPDIR;
1335         if (chan->speed == USB_SPEED_LOW)
1336                 hcchar |= HCCHAR_LSPDDEV;
1337         hcchar |= chan->ep_type << HCCHAR_EPTYPE_SHIFT & HCCHAR_EPTYPE_MASK;
1338         hcchar |= chan->max_packet << HCCHAR_MPS_SHIFT & HCCHAR_MPS_MASK;
1339         dwc2_writel(hcchar, hsotg->regs + HCCHAR(hc_num));
1340         if (dbg_hc(chan)) {
1341                 dev_vdbg(hsotg->dev, "set HCCHAR(%d) to %08x\n",
1342                          hc_num, hcchar);
1343
1344                 dev_vdbg(hsotg->dev, "%s: Channel %d\n",
1345                          __func__, hc_num);
1346                 dev_vdbg(hsotg->dev, "   Dev Addr: %d\n",
1347                          chan->dev_addr);
1348                 dev_vdbg(hsotg->dev, "   Ep Num: %d\n",
1349                          chan->ep_num);
1350                 dev_vdbg(hsotg->dev, "   Is In: %d\n",
1351                          chan->ep_is_in);
1352                 dev_vdbg(hsotg->dev, "   Is Low Speed: %d\n",
1353                          chan->speed == USB_SPEED_LOW);
1354                 dev_vdbg(hsotg->dev, "   Ep Type: %d\n",
1355                          chan->ep_type);
1356                 dev_vdbg(hsotg->dev, "   Max Pkt: %d\n",
1357                          chan->max_packet);
1358         }
1359
1360         /* Program the HCSPLT register for SPLITs */
1361         if (chan->do_split) {
1362                 if (dbg_hc(chan))
1363                         dev_vdbg(hsotg->dev,
1364                                  "Programming HC %d with split --> %s\n",
1365                                  hc_num,
1366                                  chan->complete_split ? "CSPLIT" : "SSPLIT");
1367                 if (chan->complete_split)
1368                         hcsplt |= HCSPLT_COMPSPLT;
1369                 hcsplt |= chan->xact_pos << HCSPLT_XACTPOS_SHIFT &
1370                           HCSPLT_XACTPOS_MASK;
1371                 hcsplt |= chan->hub_addr << HCSPLT_HUBADDR_SHIFT &
1372                           HCSPLT_HUBADDR_MASK;
1373                 hcsplt |= chan->hub_port << HCSPLT_PRTADDR_SHIFT &
1374                           HCSPLT_PRTADDR_MASK;
1375                 if (dbg_hc(chan)) {
1376                         dev_vdbg(hsotg->dev, "    comp split %d\n",
1377                                  chan->complete_split);
1378                         dev_vdbg(hsotg->dev, "    xact pos %d\n",
1379                                  chan->xact_pos);
1380                         dev_vdbg(hsotg->dev, "    hub addr %d\n",
1381                                  chan->hub_addr);
1382                         dev_vdbg(hsotg->dev, "    hub port %d\n",
1383                                  chan->hub_port);
1384                         dev_vdbg(hsotg->dev, "    is_in %d\n",
1385                                  chan->ep_is_in);
1386                         dev_vdbg(hsotg->dev, "    Max Pkt %d\n",
1387                                  chan->max_packet);
1388                         dev_vdbg(hsotg->dev, "    xferlen %d\n",
1389                                  chan->xfer_len);
1390                 }
1391         }
1392
1393         dwc2_writel(hcsplt, hsotg->regs + HCSPLT(hc_num));
1394 }
1395
1396 /**
1397  * dwc2_hc_halt() - Attempts to halt a host channel
1398  *
1399  * @hsotg:       Controller register interface
1400  * @chan:        Host channel to halt
1401  * @halt_status: Reason for halting the channel
1402  *
1403  * This function should only be called in Slave mode or to abort a transfer in
1404  * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
1405  * controller halts the channel when the transfer is complete or a condition
1406  * occurs that requires application intervention.
1407  *
1408  * In slave mode, checks for a free request queue entry, then sets the Channel
1409  * Enable and Channel Disable bits of the Host Channel Characteristics
1410  * register of the specified channel to intiate the halt. If there is no free
1411  * request queue entry, sets only the Channel Disable bit of the HCCHARn
1412  * register to flush requests for this channel. In the latter case, sets a
1413  * flag to indicate that the host channel needs to be halted when a request
1414  * queue slot is open.
1415  *
1416  * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
1417  * HCCHARn register. The controller ensures there is space in the request
1418  * queue before submitting the halt request.
1419  *
1420  * Some time may elapse before the core flushes any posted requests for this
1421  * host channel and halts. The Channel Halted interrupt handler completes the
1422  * deactivation of the host channel.
1423  */
1424 void dwc2_hc_halt(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan,
1425                   enum dwc2_halt_status halt_status)
1426 {
1427         u32 nptxsts, hptxsts, hcchar;
1428
1429         if (dbg_hc(chan))
1430                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1431         if (halt_status == DWC2_HC_XFER_NO_HALT_STATUS)
1432                 dev_err(hsotg->dev, "!!! halt_status = %d !!!\n", halt_status);
1433
1434         if (halt_status == DWC2_HC_XFER_URB_DEQUEUE ||
1435             halt_status == DWC2_HC_XFER_AHB_ERR) {
1436                 /*
1437                  * Disable all channel interrupts except Ch Halted. The QTD
1438                  * and QH state associated with this transfer has been cleared
1439                  * (in the case of URB_DEQUEUE), so the channel needs to be
1440                  * shut down carefully to prevent crashes.
1441                  */
1442                 u32 hcintmsk = HCINTMSK_CHHLTD;
1443
1444                 dev_vdbg(hsotg->dev, "dequeue/error\n");
1445                 dwc2_writel(hcintmsk, hsotg->regs + HCINTMSK(chan->hc_num));
1446
1447                 /*
1448                  * Make sure no other interrupts besides halt are currently
1449                  * pending. Handling another interrupt could cause a crash due
1450                  * to the QTD and QH state.
1451                  */
1452                 dwc2_writel(~hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1453
1454                 /*
1455                  * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
1456                  * even if the channel was already halted for some other
1457                  * reason
1458                  */
1459                 chan->halt_status = halt_status;
1460
1461                 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1462                 if (!(hcchar & HCCHAR_CHENA)) {
1463                         /*
1464                          * The channel is either already halted or it hasn't
1465                          * started yet. In DMA mode, the transfer may halt if
1466                          * it finishes normally or a condition occurs that
1467                          * requires driver intervention. Don't want to halt
1468                          * the channel again. In either Slave or DMA mode,
1469                          * it's possible that the transfer has been assigned
1470                          * to a channel, but not started yet when an URB is
1471                          * dequeued. Don't want to halt a channel that hasn't
1472                          * started yet.
1473                          */
1474                         return;
1475                 }
1476         }
1477         if (chan->halt_pending) {
1478                 /*
1479                  * A halt has already been issued for this channel. This might
1480                  * happen when a transfer is aborted by a higher level in
1481                  * the stack.
1482                  */
1483                 dev_vdbg(hsotg->dev,
1484                          "*** %s: Channel %d, chan->halt_pending already set ***\n",
1485                          __func__, chan->hc_num);
1486                 return;
1487         }
1488
1489         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1490
1491         /* No need to set the bit in DDMA for disabling the channel */
1492         /* TODO check it everywhere channel is disabled */
1493         if (hsotg->core_params->dma_desc_enable <= 0) {
1494                 if (dbg_hc(chan))
1495                         dev_vdbg(hsotg->dev, "desc DMA disabled\n");
1496                 hcchar |= HCCHAR_CHENA;
1497         } else {
1498                 if (dbg_hc(chan))
1499                         dev_dbg(hsotg->dev, "desc DMA enabled\n");
1500         }
1501         hcchar |= HCCHAR_CHDIS;
1502
1503         if (hsotg->core_params->dma_enable <= 0) {
1504                 if (dbg_hc(chan))
1505                         dev_vdbg(hsotg->dev, "DMA not enabled\n");
1506                 hcchar |= HCCHAR_CHENA;
1507
1508                 /* Check for space in the request queue to issue the halt */
1509                 if (chan->ep_type == USB_ENDPOINT_XFER_CONTROL ||
1510                     chan->ep_type == USB_ENDPOINT_XFER_BULK) {
1511                         dev_vdbg(hsotg->dev, "control/bulk\n");
1512                         nptxsts = dwc2_readl(hsotg->regs + GNPTXSTS);
1513                         if ((nptxsts & TXSTS_QSPCAVAIL_MASK) == 0) {
1514                                 dev_vdbg(hsotg->dev, "Disabling channel\n");
1515                                 hcchar &= ~HCCHAR_CHENA;
1516                         }
1517                 } else {
1518                         if (dbg_perio())
1519                                 dev_vdbg(hsotg->dev, "isoc/intr\n");
1520                         hptxsts = dwc2_readl(hsotg->regs + HPTXSTS);
1521                         if ((hptxsts & TXSTS_QSPCAVAIL_MASK) == 0 ||
1522                             hsotg->queuing_high_bandwidth) {
1523                                 if (dbg_perio())
1524                                         dev_vdbg(hsotg->dev, "Disabling channel\n");
1525                                 hcchar &= ~HCCHAR_CHENA;
1526                         }
1527                 }
1528         } else {
1529                 if (dbg_hc(chan))
1530                         dev_vdbg(hsotg->dev, "DMA enabled\n");
1531         }
1532
1533         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1534         chan->halt_status = halt_status;
1535
1536         if (hcchar & HCCHAR_CHENA) {
1537                 if (dbg_hc(chan))
1538                         dev_vdbg(hsotg->dev, "Channel enabled\n");
1539                 chan->halt_pending = 1;
1540                 chan->halt_on_queue = 0;
1541         } else {
1542                 if (dbg_hc(chan))
1543                         dev_vdbg(hsotg->dev, "Channel disabled\n");
1544                 chan->halt_on_queue = 1;
1545         }
1546
1547         if (dbg_hc(chan)) {
1548                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1549                          chan->hc_num);
1550                 dev_vdbg(hsotg->dev, "   hcchar: 0x%08x\n",
1551                          hcchar);
1552                 dev_vdbg(hsotg->dev, "   halt_pending: %d\n",
1553                          chan->halt_pending);
1554                 dev_vdbg(hsotg->dev, "   halt_on_queue: %d\n",
1555                          chan->halt_on_queue);
1556                 dev_vdbg(hsotg->dev, "   halt_status: %d\n",
1557                          chan->halt_status);
1558         }
1559 }
1560
1561 /**
1562  * dwc2_hc_cleanup() - Clears the transfer state for a host channel
1563  *
1564  * @hsotg: Programming view of DWC_otg controller
1565  * @chan:  Identifies the host channel to clean up
1566  *
1567  * This function is normally called after a transfer is done and the host
1568  * channel is being released
1569  */
1570 void dwc2_hc_cleanup(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
1571 {
1572         u32 hcintmsk;
1573
1574         chan->xfer_started = 0;
1575
1576         /*
1577          * Clear channel interrupt enables and any unhandled channel interrupt
1578          * conditions
1579          */
1580         dwc2_writel(0, hsotg->regs + HCINTMSK(chan->hc_num));
1581         hcintmsk = 0xffffffff;
1582         hcintmsk &= ~HCINTMSK_RESERVED14_31;
1583         dwc2_writel(hcintmsk, hsotg->regs + HCINT(chan->hc_num));
1584 }
1585
1586 /**
1587  * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
1588  * which frame a periodic transfer should occur
1589  *
1590  * @hsotg:  Programming view of DWC_otg controller
1591  * @chan:   Identifies the host channel to set up and its properties
1592  * @hcchar: Current value of the HCCHAR register for the specified host channel
1593  *
1594  * This function has no effect on non-periodic transfers
1595  */
1596 static void dwc2_hc_set_even_odd_frame(struct dwc2_hsotg *hsotg,
1597                                        struct dwc2_host_chan *chan, u32 *hcchar)
1598 {
1599         if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1600             chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1601                 /* 1 if _next_ frame is odd, 0 if it's even */
1602                 if (!(dwc2_hcd_get_frame_number(hsotg) & 0x1))
1603                         *hcchar |= HCCHAR_ODDFRM;
1604         }
1605 }
1606
1607 static void dwc2_set_pid_isoc(struct dwc2_host_chan *chan)
1608 {
1609         /* Set up the initial PID for the transfer */
1610         if (chan->speed == USB_SPEED_HIGH) {
1611                 if (chan->ep_is_in) {
1612                         if (chan->multi_count == 1)
1613                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1614                         else if (chan->multi_count == 2)
1615                                 chan->data_pid_start = DWC2_HC_PID_DATA1;
1616                         else
1617                                 chan->data_pid_start = DWC2_HC_PID_DATA2;
1618                 } else {
1619                         if (chan->multi_count == 1)
1620                                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1621                         else
1622                                 chan->data_pid_start = DWC2_HC_PID_MDATA;
1623                 }
1624         } else {
1625                 chan->data_pid_start = DWC2_HC_PID_DATA0;
1626         }
1627 }
1628
1629 /**
1630  * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1631  * the Host Channel
1632  *
1633  * @hsotg: Programming view of DWC_otg controller
1634  * @chan:  Information needed to initialize the host channel
1635  *
1636  * This function should only be called in Slave mode. For a channel associated
1637  * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1638  * associated with a periodic EP, the periodic Tx FIFO is written.
1639  *
1640  * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1641  * the number of bytes written to the Tx FIFO.
1642  */
1643 static void dwc2_hc_write_packet(struct dwc2_hsotg *hsotg,
1644                                  struct dwc2_host_chan *chan)
1645 {
1646         u32 i;
1647         u32 remaining_count;
1648         u32 byte_count;
1649         u32 dword_count;
1650         u32 __iomem *data_fifo;
1651         u32 *data_buf = (u32 *)chan->xfer_buf;
1652
1653         if (dbg_hc(chan))
1654                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1655
1656         data_fifo = (u32 __iomem *)(hsotg->regs + HCFIFO(chan->hc_num));
1657
1658         remaining_count = chan->xfer_len - chan->xfer_count;
1659         if (remaining_count > chan->max_packet)
1660                 byte_count = chan->max_packet;
1661         else
1662                 byte_count = remaining_count;
1663
1664         dword_count = (byte_count + 3) / 4;
1665
1666         if (((unsigned long)data_buf & 0x3) == 0) {
1667                 /* xfer_buf is DWORD aligned */
1668                 for (i = 0; i < dword_count; i++, data_buf++)
1669                         dwc2_writel(*data_buf, data_fifo);
1670         } else {
1671                 /* xfer_buf is not DWORD aligned */
1672                 for (i = 0; i < dword_count; i++, data_buf++) {
1673                         u32 data = data_buf[0] | data_buf[1] << 8 |
1674                                    data_buf[2] << 16 | data_buf[3] << 24;
1675                         dwc2_writel(data, data_fifo);
1676                 }
1677         }
1678
1679         chan->xfer_count += byte_count;
1680         chan->xfer_buf += byte_count;
1681 }
1682
1683 /**
1684  * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1685  * channel and starts the transfer
1686  *
1687  * @hsotg: Programming view of DWC_otg controller
1688  * @chan:  Information needed to initialize the host channel. The xfer_len value
1689  *         may be reduced to accommodate the max widths of the XferSize and
1690  *         PktCnt fields in the HCTSIZn register. The multi_count value may be
1691  *         changed to reflect the final xfer_len value.
1692  *
1693  * This function may be called in either Slave mode or DMA mode. In Slave mode,
1694  * the caller must ensure that there is sufficient space in the request queue
1695  * and Tx Data FIFO.
1696  *
1697  * For an OUT transfer in Slave mode, it loads a data packet into the
1698  * appropriate FIFO. If necessary, additional data packets are loaded in the
1699  * Host ISR.
1700  *
1701  * For an IN transfer in Slave mode, a data packet is requested. The data
1702  * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1703  * additional data packets are requested in the Host ISR.
1704  *
1705  * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1706  * register along with a packet count of 1 and the channel is enabled. This
1707  * causes a single PING transaction to occur. Other fields in HCTSIZ are
1708  * simply set to 0 since no data transfer occurs in this case.
1709  *
1710  * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1711  * all the information required to perform the subsequent data transfer. In
1712  * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1713  * controller performs the entire PING protocol, then starts the data
1714  * transfer.
1715  */
1716 void dwc2_hc_start_transfer(struct dwc2_hsotg *hsotg,
1717                             struct dwc2_host_chan *chan)
1718 {
1719         u32 max_hc_xfer_size = hsotg->core_params->max_transfer_size;
1720         u16 max_hc_pkt_count = hsotg->core_params->max_packet_count;
1721         u32 hcchar;
1722         u32 hctsiz = 0;
1723         u16 num_packets;
1724
1725         if (dbg_hc(chan))
1726                 dev_vdbg(hsotg->dev, "%s()\n", __func__);
1727
1728         if (chan->do_ping) {
1729                 if (hsotg->core_params->dma_enable <= 0) {
1730                         if (dbg_hc(chan))
1731                                 dev_vdbg(hsotg->dev, "ping, no DMA\n");
1732                         dwc2_hc_do_ping(hsotg, chan);
1733                         chan->xfer_started = 1;
1734                         return;
1735                 } else {
1736                         if (dbg_hc(chan))
1737                                 dev_vdbg(hsotg->dev, "ping, DMA\n");
1738                         hctsiz |= TSIZ_DOPNG;
1739                 }
1740         }
1741
1742         if (chan->do_split) {
1743                 if (dbg_hc(chan))
1744                         dev_vdbg(hsotg->dev, "split\n");
1745                 num_packets = 1;
1746
1747                 if (chan->complete_split && !chan->ep_is_in)
1748                         /*
1749                          * For CSPLIT OUT Transfer, set the size to 0 so the
1750                          * core doesn't expect any data written to the FIFO
1751                          */
1752                         chan->xfer_len = 0;
1753                 else if (chan->ep_is_in || chan->xfer_len > chan->max_packet)
1754                         chan->xfer_len = chan->max_packet;
1755                 else if (!chan->ep_is_in && chan->xfer_len > 188)
1756                         chan->xfer_len = 188;
1757
1758                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1759                           TSIZ_XFERSIZE_MASK;
1760         } else {
1761                 if (dbg_hc(chan))
1762                         dev_vdbg(hsotg->dev, "no split\n");
1763                 /*
1764                  * Ensure that the transfer length and packet count will fit
1765                  * in the widths allocated for them in the HCTSIZn register
1766                  */
1767                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1768                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
1769                         /*
1770                          * Make sure the transfer size is no larger than one
1771                          * (micro)frame's worth of data. (A check was done
1772                          * when the periodic transfer was accepted to ensure
1773                          * that a (micro)frame's worth of data can be
1774                          * programmed into a channel.)
1775                          */
1776                         u32 max_periodic_len =
1777                                 chan->multi_count * chan->max_packet;
1778
1779                         if (chan->xfer_len > max_periodic_len)
1780                                 chan->xfer_len = max_periodic_len;
1781                 } else if (chan->xfer_len > max_hc_xfer_size) {
1782                         /*
1783                          * Make sure that xfer_len is a multiple of max packet
1784                          * size
1785                          */
1786                         chan->xfer_len =
1787                                 max_hc_xfer_size - chan->max_packet + 1;
1788                 }
1789
1790                 if (chan->xfer_len > 0) {
1791                         num_packets = (chan->xfer_len + chan->max_packet - 1) /
1792                                         chan->max_packet;
1793                         if (num_packets > max_hc_pkt_count) {
1794                                 num_packets = max_hc_pkt_count;
1795                                 chan->xfer_len = num_packets * chan->max_packet;
1796                         }
1797                 } else {
1798                         /* Need 1 packet for transfer length of 0 */
1799                         num_packets = 1;
1800                 }
1801
1802                 if (chan->ep_is_in)
1803                         /*
1804                          * Always program an integral # of max packets for IN
1805                          * transfers
1806                          */
1807                         chan->xfer_len = num_packets * chan->max_packet;
1808
1809                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
1810                     chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1811                         /*
1812                          * Make sure that the multi_count field matches the
1813                          * actual transfer length
1814                          */
1815                         chan->multi_count = num_packets;
1816
1817                 if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1818                         dwc2_set_pid_isoc(chan);
1819
1820                 hctsiz |= chan->xfer_len << TSIZ_XFERSIZE_SHIFT &
1821                           TSIZ_XFERSIZE_MASK;
1822         }
1823
1824         chan->start_pkt_count = num_packets;
1825         hctsiz |= num_packets << TSIZ_PKTCNT_SHIFT & TSIZ_PKTCNT_MASK;
1826         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1827                   TSIZ_SC_MC_PID_MASK;
1828         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1829         if (dbg_hc(chan)) {
1830                 dev_vdbg(hsotg->dev, "Wrote %08x to HCTSIZ(%d)\n",
1831                          hctsiz, chan->hc_num);
1832
1833                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1834                          chan->hc_num);
1835                 dev_vdbg(hsotg->dev, "   Xfer Size: %d\n",
1836                          (hctsiz & TSIZ_XFERSIZE_MASK) >>
1837                          TSIZ_XFERSIZE_SHIFT);
1838                 dev_vdbg(hsotg->dev, "   Num Pkts: %d\n",
1839                          (hctsiz & TSIZ_PKTCNT_MASK) >>
1840                          TSIZ_PKTCNT_SHIFT);
1841                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1842                          (hctsiz & TSIZ_SC_MC_PID_MASK) >>
1843                          TSIZ_SC_MC_PID_SHIFT);
1844         }
1845
1846         if (hsotg->core_params->dma_enable > 0) {
1847                 dma_addr_t dma_addr;
1848
1849                 if (chan->align_buf) {
1850                         if (dbg_hc(chan))
1851                                 dev_vdbg(hsotg->dev, "align_buf\n");
1852                         dma_addr = chan->align_buf;
1853                 } else {
1854                         dma_addr = chan->xfer_dma;
1855                 }
1856                 dwc2_writel((u32)dma_addr, hsotg->regs + HCDMA(chan->hc_num));
1857                 if (dbg_hc(chan))
1858                         dev_vdbg(hsotg->dev, "Wrote %08lx to HCDMA(%d)\n",
1859                                  (unsigned long)dma_addr, chan->hc_num);
1860         }
1861
1862         /* Start the split */
1863         if (chan->do_split) {
1864                 u32 hcsplt = dwc2_readl(hsotg->regs + HCSPLT(chan->hc_num));
1865
1866                 hcsplt |= HCSPLT_SPLTENA;
1867                 dwc2_writel(hcsplt, hsotg->regs + HCSPLT(chan->hc_num));
1868         }
1869
1870         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1871         hcchar &= ~HCCHAR_MULTICNT_MASK;
1872         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1873                   HCCHAR_MULTICNT_MASK;
1874         dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
1875
1876         if (hcchar & HCCHAR_CHDIS)
1877                 dev_warn(hsotg->dev,
1878                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1879                          __func__, chan->hc_num, hcchar);
1880
1881         /* Set host channel enable after all other setup is complete */
1882         hcchar |= HCCHAR_CHENA;
1883         hcchar &= ~HCCHAR_CHDIS;
1884
1885         if (dbg_hc(chan))
1886                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1887                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1888                          HCCHAR_MULTICNT_SHIFT);
1889
1890         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1891         if (dbg_hc(chan))
1892                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1893                          chan->hc_num);
1894
1895         chan->xfer_started = 1;
1896         chan->requests++;
1897
1898         if (hsotg->core_params->dma_enable <= 0 &&
1899             !chan->ep_is_in && chan->xfer_len > 0)
1900                 /* Load OUT packet into the appropriate Tx FIFO */
1901                 dwc2_hc_write_packet(hsotg, chan);
1902 }
1903
1904 /**
1905  * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1906  * host channel and starts the transfer in Descriptor DMA mode
1907  *
1908  * @hsotg: Programming view of DWC_otg controller
1909  * @chan:  Information needed to initialize the host channel
1910  *
1911  * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1912  * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1913  * with micro-frame bitmap.
1914  *
1915  * Initializes HCDMA register with descriptor list address and CTD value then
1916  * starts the transfer via enabling the channel.
1917  */
1918 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg,
1919                                  struct dwc2_host_chan *chan)
1920 {
1921         u32 hcchar;
1922         u32 hc_dma;
1923         u32 hctsiz = 0;
1924
1925         if (chan->do_ping)
1926                 hctsiz |= TSIZ_DOPNG;
1927
1928         if (chan->ep_type == USB_ENDPOINT_XFER_ISOC)
1929                 dwc2_set_pid_isoc(chan);
1930
1931         /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1932         hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT &
1933                   TSIZ_SC_MC_PID_MASK;
1934
1935         /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1936         hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
1937
1938         /* Non-zero only for high-speed interrupt endpoints */
1939         hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
1940
1941         if (dbg_hc(chan)) {
1942                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
1943                          chan->hc_num);
1944                 dev_vdbg(hsotg->dev, "   Start PID: %d\n",
1945                          chan->data_pid_start);
1946                 dev_vdbg(hsotg->dev, "   NTD: %d\n", chan->ntd - 1);
1947         }
1948
1949         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
1950
1951         hc_dma = (u32)chan->desc_list_addr & HCDMA_DMA_ADDR_MASK;
1952
1953         /* Always start from first descriptor */
1954         hc_dma &= ~HCDMA_CTD_MASK;
1955         dwc2_writel(hc_dma, hsotg->regs + HCDMA(chan->hc_num));
1956         if (dbg_hc(chan))
1957                 dev_vdbg(hsotg->dev, "Wrote %08x to HCDMA(%d)\n",
1958                          hc_dma, chan->hc_num);
1959
1960         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
1961         hcchar &= ~HCCHAR_MULTICNT_MASK;
1962         hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT &
1963                   HCCHAR_MULTICNT_MASK;
1964
1965         if (hcchar & HCCHAR_CHDIS)
1966                 dev_warn(hsotg->dev,
1967                          "%s: chdis set, channel %d, hcchar 0x%08x\n",
1968                          __func__, chan->hc_num, hcchar);
1969
1970         /* Set host channel enable after all other setup is complete */
1971         hcchar |= HCCHAR_CHENA;
1972         hcchar &= ~HCCHAR_CHDIS;
1973
1974         if (dbg_hc(chan))
1975                 dev_vdbg(hsotg->dev, "   Multi Cnt: %d\n",
1976                          (hcchar & HCCHAR_MULTICNT_MASK) >>
1977                          HCCHAR_MULTICNT_SHIFT);
1978
1979         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
1980         if (dbg_hc(chan))
1981                 dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar,
1982                          chan->hc_num);
1983
1984         chan->xfer_started = 1;
1985         chan->requests++;
1986 }
1987
1988 /**
1989  * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1990  * a previous call to dwc2_hc_start_transfer()
1991  *
1992  * @hsotg: Programming view of DWC_otg controller
1993  * @chan:  Information needed to initialize the host channel
1994  *
1995  * The caller must ensure there is sufficient space in the request queue and Tx
1996  * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1997  * the controller acts autonomously to complete transfers programmed to a host
1998  * channel.
1999  *
2000  * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
2001  * if there is any data remaining to be queued. For an IN transfer, another
2002  * data packet is always requested. For the SETUP phase of a control transfer,
2003  * this function does nothing.
2004  *
2005  * Return: 1 if a new request is queued, 0 if no more requests are required
2006  * for this transfer
2007  */
2008 int dwc2_hc_continue_transfer(struct dwc2_hsotg *hsotg,
2009                               struct dwc2_host_chan *chan)
2010 {
2011         if (dbg_hc(chan))
2012                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2013                          chan->hc_num);
2014
2015         if (chan->do_split)
2016                 /* SPLITs always queue just once per channel */
2017                 return 0;
2018
2019         if (chan->data_pid_start == DWC2_HC_PID_SETUP)
2020                 /* SETUPs are queued only once since they can't be NAK'd */
2021                 return 0;
2022
2023         if (chan->ep_is_in) {
2024                 /*
2025                  * Always queue another request for other IN transfers. If
2026                  * back-to-back INs are issued and NAKs are received for both,
2027                  * the driver may still be processing the first NAK when the
2028                  * second NAK is received. When the interrupt handler clears
2029                  * the NAK interrupt for the first NAK, the second NAK will
2030                  * not be seen. So we can't depend on the NAK interrupt
2031                  * handler to requeue a NAK'd request. Instead, IN requests
2032                  * are issued each time this function is called. When the
2033                  * transfer completes, the extra requests for the channel will
2034                  * be flushed.
2035                  */
2036                 u32 hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2037
2038                 dwc2_hc_set_even_odd_frame(hsotg, chan, &hcchar);
2039                 hcchar |= HCCHAR_CHENA;
2040                 hcchar &= ~HCCHAR_CHDIS;
2041                 if (dbg_hc(chan))
2042                         dev_vdbg(hsotg->dev, "   IN xfer: hcchar = 0x%08x\n",
2043                                  hcchar);
2044                 dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2045                 chan->requests++;
2046                 return 1;
2047         }
2048
2049         /* OUT transfers */
2050
2051         if (chan->xfer_count < chan->xfer_len) {
2052                 if (chan->ep_type == USB_ENDPOINT_XFER_INT ||
2053                     chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
2054                         u32 hcchar = dwc2_readl(hsotg->regs +
2055                                                 HCCHAR(chan->hc_num));
2056
2057                         dwc2_hc_set_even_odd_frame(hsotg, chan,
2058                                                    &hcchar);
2059                 }
2060
2061                 /* Load OUT packet into the appropriate Tx FIFO */
2062                 dwc2_hc_write_packet(hsotg, chan);
2063                 chan->requests++;
2064                 return 1;
2065         }
2066
2067         return 0;
2068 }
2069
2070 /**
2071  * dwc2_hc_do_ping() - Starts a PING transfer
2072  *
2073  * @hsotg: Programming view of DWC_otg controller
2074  * @chan:  Information needed to initialize the host channel
2075  *
2076  * This function should only be called in Slave mode. The Do Ping bit is set in
2077  * the HCTSIZ register, then the channel is enabled.
2078  */
2079 void dwc2_hc_do_ping(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan)
2080 {
2081         u32 hcchar;
2082         u32 hctsiz;
2083
2084         if (dbg_hc(chan))
2085                 dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__,
2086                          chan->hc_num);
2087
2088
2089         hctsiz = TSIZ_DOPNG;
2090         hctsiz |= 1 << TSIZ_PKTCNT_SHIFT;
2091         dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
2092
2093         hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
2094         hcchar |= HCCHAR_CHENA;
2095         hcchar &= ~HCCHAR_CHDIS;
2096         dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
2097 }
2098
2099 /**
2100  * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
2101  * the HFIR register according to PHY type and speed
2102  *
2103  * @hsotg: Programming view of DWC_otg controller
2104  *
2105  * NOTE: The caller can modify the value of the HFIR register only after the
2106  * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
2107  * has been set
2108  */
2109 u32 dwc2_calc_frame_interval(struct dwc2_hsotg *hsotg)
2110 {
2111         u32 usbcfg;
2112         u32 hprt0;
2113         int clock = 60; /* default value */
2114
2115         usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
2116         hprt0 = dwc2_readl(hsotg->regs + HPRT0);
2117
2118         if (!(usbcfg & GUSBCFG_PHYSEL) && (usbcfg & GUSBCFG_ULPI_UTMI_SEL) &&
2119             !(usbcfg & GUSBCFG_PHYIF16))
2120                 clock = 60;
2121         if ((usbcfg & GUSBCFG_PHYSEL) && hsotg->hw_params.fs_phy_type ==
2122             GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
2123                 clock = 48;
2124         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2125             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2126                 clock = 30;
2127         if (!(usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2128             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && !(usbcfg & GUSBCFG_PHYIF16))
2129                 clock = 60;
2130         if ((usbcfg & GUSBCFG_PHY_LP_CLK_SEL) && !(usbcfg & GUSBCFG_PHYSEL) &&
2131             !(usbcfg & GUSBCFG_ULPI_UTMI_SEL) && (usbcfg & GUSBCFG_PHYIF16))
2132                 clock = 48;
2133         if ((usbcfg & GUSBCFG_PHYSEL) && !(usbcfg & GUSBCFG_PHYIF16) &&
2134             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_SHARED_UTMI)
2135                 clock = 48;
2136         if ((usbcfg & GUSBCFG_PHYSEL) &&
2137             hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2138                 clock = 48;
2139
2140         if ((hprt0 & HPRT0_SPD_MASK) >> HPRT0_SPD_SHIFT == HPRT0_SPD_HIGH_SPEED)
2141                 /* High speed case */
2142                 return 125 * clock;
2143         else
2144                 /* FS/LS case */
2145                 return 1000 * clock;
2146 }
2147
2148 /**
2149  * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
2150  * buffer
2151  *
2152  * @core_if: Programming view of DWC_otg controller
2153  * @dest:    Destination buffer for the packet
2154  * @bytes:   Number of bytes to copy to the destination
2155  */
2156 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes)
2157 {
2158         u32 __iomem *fifo = hsotg->regs + HCFIFO(0);
2159         u32 *data_buf = (u32 *)dest;
2160         int word_count = (bytes + 3) / 4;
2161         int i;
2162
2163         /*
2164          * Todo: Account for the case where dest is not dword aligned. This
2165          * requires reading data from the FIFO into a u32 temp buffer, then
2166          * moving it into the data buffer.
2167          */
2168
2169         dev_vdbg(hsotg->dev, "%s(%p,%p,%d)\n", __func__, hsotg, dest, bytes);
2170
2171         for (i = 0; i < word_count; i++, data_buf++)
2172                 *data_buf = dwc2_readl(fifo);
2173 }
2174
2175 /**
2176  * dwc2_dump_host_registers() - Prints the host registers
2177  *
2178  * @hsotg: Programming view of DWC_otg controller
2179  *
2180  * NOTE: This function will be removed once the peripheral controller code
2181  * is integrated and the driver is stable
2182  */
2183 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
2184 {
2185 #ifdef DEBUG
2186         u32 __iomem *addr;
2187         int i;
2188
2189         dev_dbg(hsotg->dev, "Host Global Registers\n");
2190         addr = hsotg->regs + HCFG;
2191         dev_dbg(hsotg->dev, "HCFG        @0x%08lX : 0x%08X\n",
2192                 (unsigned long)addr, dwc2_readl(addr));
2193         addr = hsotg->regs + HFIR;
2194         dev_dbg(hsotg->dev, "HFIR        @0x%08lX : 0x%08X\n",
2195                 (unsigned long)addr, dwc2_readl(addr));
2196         addr = hsotg->regs + HFNUM;
2197         dev_dbg(hsotg->dev, "HFNUM       @0x%08lX : 0x%08X\n",
2198                 (unsigned long)addr, dwc2_readl(addr));
2199         addr = hsotg->regs + HPTXSTS;
2200         dev_dbg(hsotg->dev, "HPTXSTS     @0x%08lX : 0x%08X\n",
2201                 (unsigned long)addr, dwc2_readl(addr));
2202         addr = hsotg->regs + HAINT;
2203         dev_dbg(hsotg->dev, "HAINT       @0x%08lX : 0x%08X\n",
2204                 (unsigned long)addr, dwc2_readl(addr));
2205         addr = hsotg->regs + HAINTMSK;
2206         dev_dbg(hsotg->dev, "HAINTMSK    @0x%08lX : 0x%08X\n",
2207                 (unsigned long)addr, dwc2_readl(addr));
2208         if (hsotg->core_params->dma_desc_enable > 0) {
2209                 addr = hsotg->regs + HFLBADDR;
2210                 dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
2211                         (unsigned long)addr, dwc2_readl(addr));
2212         }
2213
2214         addr = hsotg->regs + HPRT0;
2215         dev_dbg(hsotg->dev, "HPRT0       @0x%08lX : 0x%08X\n",
2216                 (unsigned long)addr, dwc2_readl(addr));
2217
2218         for (i = 0; i < hsotg->core_params->host_channels; i++) {
2219                 dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
2220                 addr = hsotg->regs + HCCHAR(i);
2221                 dev_dbg(hsotg->dev, "HCCHAR      @0x%08lX : 0x%08X\n",
2222                         (unsigned long)addr, dwc2_readl(addr));
2223                 addr = hsotg->regs + HCSPLT(i);
2224                 dev_dbg(hsotg->dev, "HCSPLT      @0x%08lX : 0x%08X\n",
2225                         (unsigned long)addr, dwc2_readl(addr));
2226                 addr = hsotg->regs + HCINT(i);
2227                 dev_dbg(hsotg->dev, "HCINT       @0x%08lX : 0x%08X\n",
2228                         (unsigned long)addr, dwc2_readl(addr));
2229                 addr = hsotg->regs + HCINTMSK(i);
2230                 dev_dbg(hsotg->dev, "HCINTMSK    @0x%08lX : 0x%08X\n",
2231                         (unsigned long)addr, dwc2_readl(addr));
2232                 addr = hsotg->regs + HCTSIZ(i);
2233                 dev_dbg(hsotg->dev, "HCTSIZ      @0x%08lX : 0x%08X\n",
2234                         (unsigned long)addr, dwc2_readl(addr));
2235                 addr = hsotg->regs + HCDMA(i);
2236                 dev_dbg(hsotg->dev, "HCDMA       @0x%08lX : 0x%08X\n",
2237                         (unsigned long)addr, dwc2_readl(addr));
2238                 if (hsotg->core_params->dma_desc_enable > 0) {
2239                         addr = hsotg->regs + HCDMAB(i);
2240                         dev_dbg(hsotg->dev, "HCDMAB      @0x%08lX : 0x%08X\n",
2241                                 (unsigned long)addr, dwc2_readl(addr));
2242                 }
2243         }
2244 #endif
2245 }
2246
2247 /**
2248  * dwc2_dump_global_registers() - Prints the core global registers
2249  *
2250  * @hsotg: Programming view of DWC_otg controller
2251  *
2252  * NOTE: This function will be removed once the peripheral controller code
2253  * is integrated and the driver is stable
2254  */
2255 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
2256 {
2257 #ifdef DEBUG
2258         u32 __iomem *addr;
2259
2260         dev_dbg(hsotg->dev, "Core Global Registers\n");
2261         addr = hsotg->regs + GOTGCTL;
2262         dev_dbg(hsotg->dev, "GOTGCTL     @0x%08lX : 0x%08X\n",
2263                 (unsigned long)addr, dwc2_readl(addr));
2264         addr = hsotg->regs + GOTGINT;
2265         dev_dbg(hsotg->dev, "GOTGINT     @0x%08lX : 0x%08X\n",
2266                 (unsigned long)addr, dwc2_readl(addr));
2267         addr = hsotg->regs + GAHBCFG;
2268         dev_dbg(hsotg->dev, "GAHBCFG     @0x%08lX : 0x%08X\n",
2269                 (unsigned long)addr, dwc2_readl(addr));
2270         addr = hsotg->regs + GUSBCFG;
2271         dev_dbg(hsotg->dev, "GUSBCFG     @0x%08lX : 0x%08X\n",
2272                 (unsigned long)addr, dwc2_readl(addr));
2273         addr = hsotg->regs + GRSTCTL;
2274         dev_dbg(hsotg->dev, "GRSTCTL     @0x%08lX : 0x%08X\n",
2275                 (unsigned long)addr, dwc2_readl(addr));
2276         addr = hsotg->regs + GINTSTS;
2277         dev_dbg(hsotg->dev, "GINTSTS     @0x%08lX : 0x%08X\n",
2278                 (unsigned long)addr, dwc2_readl(addr));
2279         addr = hsotg->regs + GINTMSK;
2280         dev_dbg(hsotg->dev, "GINTMSK     @0x%08lX : 0x%08X\n",
2281                 (unsigned long)addr, dwc2_readl(addr));
2282         addr = hsotg->regs + GRXSTSR;
2283         dev_dbg(hsotg->dev, "GRXSTSR     @0x%08lX : 0x%08X\n",
2284                 (unsigned long)addr, dwc2_readl(addr));
2285         addr = hsotg->regs + GRXFSIZ;
2286         dev_dbg(hsotg->dev, "GRXFSIZ     @0x%08lX : 0x%08X\n",
2287                 (unsigned long)addr, dwc2_readl(addr));
2288         addr = hsotg->regs + GNPTXFSIZ;
2289         dev_dbg(hsotg->dev, "GNPTXFSIZ   @0x%08lX : 0x%08X\n",
2290                 (unsigned long)addr, dwc2_readl(addr));
2291         addr = hsotg->regs + GNPTXSTS;
2292         dev_dbg(hsotg->dev, "GNPTXSTS    @0x%08lX : 0x%08X\n",
2293                 (unsigned long)addr, dwc2_readl(addr));
2294         addr = hsotg->regs + GI2CCTL;
2295         dev_dbg(hsotg->dev, "GI2CCTL     @0x%08lX : 0x%08X\n",
2296                 (unsigned long)addr, dwc2_readl(addr));
2297         addr = hsotg->regs + GPVNDCTL;
2298         dev_dbg(hsotg->dev, "GPVNDCTL    @0x%08lX : 0x%08X\n",
2299                 (unsigned long)addr, dwc2_readl(addr));
2300         addr = hsotg->regs + GGPIO;
2301         dev_dbg(hsotg->dev, "GGPIO       @0x%08lX : 0x%08X\n",
2302                 (unsigned long)addr, dwc2_readl(addr));
2303         addr = hsotg->regs + GUID;
2304         dev_dbg(hsotg->dev, "GUID        @0x%08lX : 0x%08X\n",
2305                 (unsigned long)addr, dwc2_readl(addr));
2306         addr = hsotg->regs + GSNPSID;
2307         dev_dbg(hsotg->dev, "GSNPSID     @0x%08lX : 0x%08X\n",
2308                 (unsigned long)addr, dwc2_readl(addr));
2309         addr = hsotg->regs + GHWCFG1;
2310         dev_dbg(hsotg->dev, "GHWCFG1     @0x%08lX : 0x%08X\n",
2311                 (unsigned long)addr, dwc2_readl(addr));
2312         addr = hsotg->regs + GHWCFG2;
2313         dev_dbg(hsotg->dev, "GHWCFG2     @0x%08lX : 0x%08X\n",
2314                 (unsigned long)addr, dwc2_readl(addr));
2315         addr = hsotg->regs + GHWCFG3;
2316         dev_dbg(hsotg->dev, "GHWCFG3     @0x%08lX : 0x%08X\n",
2317                 (unsigned long)addr, dwc2_readl(addr));
2318         addr = hsotg->regs + GHWCFG4;
2319         dev_dbg(hsotg->dev, "GHWCFG4     @0x%08lX : 0x%08X\n",
2320                 (unsigned long)addr, dwc2_readl(addr));
2321         addr = hsotg->regs + GLPMCFG;
2322         dev_dbg(hsotg->dev, "GLPMCFG     @0x%08lX : 0x%08X\n",
2323                 (unsigned long)addr, dwc2_readl(addr));
2324         addr = hsotg->regs + GPWRDN;
2325         dev_dbg(hsotg->dev, "GPWRDN      @0x%08lX : 0x%08X\n",
2326                 (unsigned long)addr, dwc2_readl(addr));
2327         addr = hsotg->regs + GDFIFOCFG;
2328         dev_dbg(hsotg->dev, "GDFIFOCFG   @0x%08lX : 0x%08X\n",
2329                 (unsigned long)addr, dwc2_readl(addr));
2330         addr = hsotg->regs + HPTXFSIZ;
2331         dev_dbg(hsotg->dev, "HPTXFSIZ    @0x%08lX : 0x%08X\n",
2332                 (unsigned long)addr, dwc2_readl(addr));
2333
2334         addr = hsotg->regs + PCGCTL;
2335         dev_dbg(hsotg->dev, "PCGCTL      @0x%08lX : 0x%08X\n",
2336                 (unsigned long)addr, dwc2_readl(addr));
2337 #endif
2338 }
2339
2340 /**
2341  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
2342  *
2343  * @hsotg: Programming view of DWC_otg controller
2344  * @num:   Tx FIFO to flush
2345  */
2346 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
2347 {
2348         u32 greset;
2349         int count = 0;
2350
2351         dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
2352
2353         greset = GRSTCTL_TXFFLSH;
2354         greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
2355         dwc2_writel(greset, hsotg->regs + GRSTCTL);
2356
2357         do {
2358                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2359                 if (++count > 10000) {
2360                         dev_warn(hsotg->dev,
2361                                  "%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n",
2362                                  __func__, greset,
2363                                  dwc2_readl(hsotg->regs + GNPTXSTS));
2364                         break;
2365                 }
2366                 udelay(1);
2367         } while (greset & GRSTCTL_TXFFLSH);
2368
2369         /* Wait for at least 3 PHY Clocks */
2370         udelay(1);
2371 }
2372
2373 /**
2374  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
2375  *
2376  * @hsotg: Programming view of DWC_otg controller
2377  */
2378 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
2379 {
2380         u32 greset;
2381         int count = 0;
2382
2383         dev_vdbg(hsotg->dev, "%s()\n", __func__);
2384
2385         greset = GRSTCTL_RXFFLSH;
2386         dwc2_writel(greset, hsotg->regs + GRSTCTL);
2387
2388         do {
2389                 greset = dwc2_readl(hsotg->regs + GRSTCTL);
2390                 if (++count > 10000) {
2391                         dev_warn(hsotg->dev, "%s() HANG! GRSTCTL=%0x\n",
2392                                  __func__, greset);
2393                         break;
2394                 }
2395                 udelay(1);
2396         } while (greset & GRSTCTL_RXFFLSH);
2397
2398         /* Wait for at least 3 PHY Clocks */
2399         udelay(1);
2400 }
2401
2402 #define DWC2_OUT_OF_BOUNDS(a, b, c)     ((a) < (b) || (a) > (c))
2403
2404 /* Parameter access functions */
2405 void dwc2_set_param_otg_cap(struct dwc2_hsotg *hsotg, int val)
2406 {
2407         int valid = 1;
2408
2409         switch (val) {
2410         case DWC2_CAP_PARAM_HNP_SRP_CAPABLE:
2411                 if (hsotg->hw_params.op_mode != GHWCFG2_OP_MODE_HNP_SRP_CAPABLE)
2412                         valid = 0;
2413                 break;
2414         case DWC2_CAP_PARAM_SRP_ONLY_CAPABLE:
2415                 switch (hsotg->hw_params.op_mode) {
2416                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2417                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2418                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2419                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2420                         break;
2421                 default:
2422                         valid = 0;
2423                         break;
2424                 }
2425                 break;
2426         case DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE:
2427                 /* always valid */
2428                 break;
2429         default:
2430                 valid = 0;
2431                 break;
2432         }
2433
2434         if (!valid) {
2435                 if (val >= 0)
2436                         dev_err(hsotg->dev,
2437                                 "%d invalid for otg_cap parameter. Check HW configuration.\n",
2438                                 val);
2439                 switch (hsotg->hw_params.op_mode) {
2440                 case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
2441                         val = DWC2_CAP_PARAM_HNP_SRP_CAPABLE;
2442                         break;
2443                 case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
2444                 case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
2445                 case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
2446                         val = DWC2_CAP_PARAM_SRP_ONLY_CAPABLE;
2447                         break;
2448                 default:
2449                         val = DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE;
2450                         break;
2451                 }
2452                 dev_dbg(hsotg->dev, "Setting otg_cap to %d\n", val);
2453         }
2454
2455         hsotg->core_params->otg_cap = val;
2456 }
2457
2458 void dwc2_set_param_dma_enable(struct dwc2_hsotg *hsotg, int val)
2459 {
2460         int valid = 1;
2461
2462         if (val > 0 && hsotg->hw_params.arch == GHWCFG2_SLAVE_ONLY_ARCH)
2463                 valid = 0;
2464         if (val < 0)
2465                 valid = 0;
2466
2467         if (!valid) {
2468                 if (val >= 0)
2469                         dev_err(hsotg->dev,
2470                                 "%d invalid for dma_enable parameter. Check HW configuration.\n",
2471                                 val);
2472                 val = hsotg->hw_params.arch != GHWCFG2_SLAVE_ONLY_ARCH;
2473                 dev_dbg(hsotg->dev, "Setting dma_enable to %d\n", val);
2474         }
2475
2476         hsotg->core_params->dma_enable = val;
2477 }
2478
2479 void dwc2_set_param_dma_desc_enable(struct dwc2_hsotg *hsotg, int val)
2480 {
2481         int valid = 1;
2482
2483         if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2484                         !hsotg->hw_params.dma_desc_enable))
2485                 valid = 0;
2486         if (val < 0)
2487                 valid = 0;
2488
2489         if (!valid) {
2490                 if (val >= 0)
2491                         dev_err(hsotg->dev,
2492                                 "%d invalid for dma_desc_enable parameter. Check HW configuration.\n",
2493                                 val);
2494                 val = (hsotg->core_params->dma_enable > 0 &&
2495                         hsotg->hw_params.dma_desc_enable);
2496                 dev_dbg(hsotg->dev, "Setting dma_desc_enable to %d\n", val);
2497         }
2498
2499         hsotg->core_params->dma_desc_enable = val;
2500 }
2501
2502 void dwc2_set_param_dma_desc_fs_enable(struct dwc2_hsotg *hsotg, int val)
2503 {
2504         int valid = 1;
2505
2506         if (val > 0 && (hsotg->core_params->dma_enable <= 0 ||
2507                         !hsotg->hw_params.dma_desc_enable))
2508                 valid = 0;
2509         if (val < 0)
2510                 valid = 0;
2511
2512         if (!valid) {
2513                 if (val >= 0)
2514                         dev_err(hsotg->dev,
2515                                 "%d invalid for dma_desc_fs_enable parameter. Check HW configuration.\n",
2516                                 val);
2517                 val = (hsotg->core_params->dma_enable > 0 &&
2518                         hsotg->hw_params.dma_desc_enable);
2519         }
2520
2521         hsotg->core_params->dma_desc_fs_enable = val;
2522         dev_dbg(hsotg->dev, "Setting dma_desc_fs_enable to %d\n", val);
2523 }
2524
2525 void dwc2_set_param_host_support_fs_ls_low_power(struct dwc2_hsotg *hsotg,
2526                                                  int val)
2527 {
2528         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2529                 if (val >= 0) {
2530                         dev_err(hsotg->dev,
2531                                 "Wrong value for host_support_fs_low_power\n");
2532                         dev_err(hsotg->dev,
2533                                 "host_support_fs_low_power must be 0 or 1\n");
2534                 }
2535                 val = 0;
2536                 dev_dbg(hsotg->dev,
2537                         "Setting host_support_fs_low_power to %d\n", val);
2538         }
2539
2540         hsotg->core_params->host_support_fs_ls_low_power = val;
2541 }
2542
2543 void dwc2_set_param_enable_dynamic_fifo(struct dwc2_hsotg *hsotg, int val)
2544 {
2545         int valid = 1;
2546
2547         if (val > 0 && !hsotg->hw_params.enable_dynamic_fifo)
2548                 valid = 0;
2549         if (val < 0)
2550                 valid = 0;
2551
2552         if (!valid) {
2553                 if (val >= 0)
2554                         dev_err(hsotg->dev,
2555                                 "%d invalid for enable_dynamic_fifo parameter. Check HW configuration.\n",
2556                                 val);
2557                 val = hsotg->hw_params.enable_dynamic_fifo;
2558                 dev_dbg(hsotg->dev, "Setting enable_dynamic_fifo to %d\n", val);
2559         }
2560
2561         hsotg->core_params->enable_dynamic_fifo = val;
2562 }
2563
2564 void dwc2_set_param_host_rx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2565 {
2566         int valid = 1;
2567
2568         if (val < 16 || val > hsotg->hw_params.host_rx_fifo_size)
2569                 valid = 0;
2570
2571         if (!valid) {
2572                 if (val >= 0)
2573                         dev_err(hsotg->dev,
2574                                 "%d invalid for host_rx_fifo_size. Check HW configuration.\n",
2575                                 val);
2576                 val = hsotg->hw_params.host_rx_fifo_size;
2577                 dev_dbg(hsotg->dev, "Setting host_rx_fifo_size to %d\n", val);
2578         }
2579
2580         hsotg->core_params->host_rx_fifo_size = val;
2581 }
2582
2583 void dwc2_set_param_host_nperio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2584 {
2585         int valid = 1;
2586
2587         if (val < 16 || val > hsotg->hw_params.host_nperio_tx_fifo_size)
2588                 valid = 0;
2589
2590         if (!valid) {
2591                 if (val >= 0)
2592                         dev_err(hsotg->dev,
2593                                 "%d invalid for host_nperio_tx_fifo_size. Check HW configuration.\n",
2594                                 val);
2595                 val = hsotg->hw_params.host_nperio_tx_fifo_size;
2596                 dev_dbg(hsotg->dev, "Setting host_nperio_tx_fifo_size to %d\n",
2597                         val);
2598         }
2599
2600         hsotg->core_params->host_nperio_tx_fifo_size = val;
2601 }
2602
2603 void dwc2_set_param_host_perio_tx_fifo_size(struct dwc2_hsotg *hsotg, int val)
2604 {
2605         int valid = 1;
2606
2607         if (val < 16 || val > hsotg->hw_params.host_perio_tx_fifo_size)
2608                 valid = 0;
2609
2610         if (!valid) {
2611                 if (val >= 0)
2612                         dev_err(hsotg->dev,
2613                                 "%d invalid for host_perio_tx_fifo_size. Check HW configuration.\n",
2614                                 val);
2615                 val = hsotg->hw_params.host_perio_tx_fifo_size;
2616                 dev_dbg(hsotg->dev, "Setting host_perio_tx_fifo_size to %d\n",
2617                         val);
2618         }
2619
2620         hsotg->core_params->host_perio_tx_fifo_size = val;
2621 }
2622
2623 void dwc2_set_param_max_transfer_size(struct dwc2_hsotg *hsotg, int val)
2624 {
2625         int valid = 1;
2626
2627         if (val < 2047 || val > hsotg->hw_params.max_transfer_size)
2628                 valid = 0;
2629
2630         if (!valid) {
2631                 if (val >= 0)
2632                         dev_err(hsotg->dev,
2633                                 "%d invalid for max_transfer_size. Check HW configuration.\n",
2634                                 val);
2635                 val = hsotg->hw_params.max_transfer_size;
2636                 dev_dbg(hsotg->dev, "Setting max_transfer_size to %d\n", val);
2637         }
2638
2639         hsotg->core_params->max_transfer_size = val;
2640 }
2641
2642 void dwc2_set_param_max_packet_count(struct dwc2_hsotg *hsotg, int val)
2643 {
2644         int valid = 1;
2645
2646         if (val < 15 || val > hsotg->hw_params.max_packet_count)
2647                 valid = 0;
2648
2649         if (!valid) {
2650                 if (val >= 0)
2651                         dev_err(hsotg->dev,
2652                                 "%d invalid for max_packet_count. Check HW configuration.\n",
2653                                 val);
2654                 val = hsotg->hw_params.max_packet_count;
2655                 dev_dbg(hsotg->dev, "Setting max_packet_count to %d\n", val);
2656         }
2657
2658         hsotg->core_params->max_packet_count = val;
2659 }
2660
2661 void dwc2_set_param_host_channels(struct dwc2_hsotg *hsotg, int val)
2662 {
2663         int valid = 1;
2664
2665         if (val < 1 || val > hsotg->hw_params.host_channels)
2666                 valid = 0;
2667
2668         if (!valid) {
2669                 if (val >= 0)
2670                         dev_err(hsotg->dev,
2671                                 "%d invalid for host_channels. Check HW configuration.\n",
2672                                 val);
2673                 val = hsotg->hw_params.host_channels;
2674                 dev_dbg(hsotg->dev, "Setting host_channels to %d\n", val);
2675         }
2676
2677         hsotg->core_params->host_channels = val;
2678 }
2679
2680 void dwc2_set_param_phy_type(struct dwc2_hsotg *hsotg, int val)
2681 {
2682         int valid = 0;
2683         u32 hs_phy_type, fs_phy_type;
2684
2685         if (DWC2_OUT_OF_BOUNDS(val, DWC2_PHY_TYPE_PARAM_FS,
2686                                DWC2_PHY_TYPE_PARAM_ULPI)) {
2687                 if (val >= 0) {
2688                         dev_err(hsotg->dev, "Wrong value for phy_type\n");
2689                         dev_err(hsotg->dev, "phy_type must be 0, 1 or 2\n");
2690                 }
2691
2692                 valid = 0;
2693         }
2694
2695         hs_phy_type = hsotg->hw_params.hs_phy_type;
2696         fs_phy_type = hsotg->hw_params.fs_phy_type;
2697         if (val == DWC2_PHY_TYPE_PARAM_UTMI &&
2698             (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2699              hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2700                 valid = 1;
2701         else if (val == DWC2_PHY_TYPE_PARAM_ULPI &&
2702                  (hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI ||
2703                   hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI))
2704                 valid = 1;
2705         else if (val == DWC2_PHY_TYPE_PARAM_FS &&
2706                  fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED)
2707                 valid = 1;
2708
2709         if (!valid) {
2710                 if (val >= 0)
2711                         dev_err(hsotg->dev,
2712                                 "%d invalid for phy_type. Check HW configuration.\n",
2713                                 val);
2714                 val = DWC2_PHY_TYPE_PARAM_FS;
2715                 if (hs_phy_type != GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED) {
2716                         if (hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI ||
2717                             hs_phy_type == GHWCFG2_HS_PHY_TYPE_UTMI_ULPI)
2718                                 val = DWC2_PHY_TYPE_PARAM_UTMI;
2719                         else
2720                                 val = DWC2_PHY_TYPE_PARAM_ULPI;
2721                 }
2722                 dev_dbg(hsotg->dev, "Setting phy_type to %d\n", val);
2723         }
2724
2725         hsotg->core_params->phy_type = val;
2726 }
2727
2728 static int dwc2_get_param_phy_type(struct dwc2_hsotg *hsotg)
2729 {
2730         return hsotg->core_params->phy_type;
2731 }
2732
2733 void dwc2_set_param_speed(struct dwc2_hsotg *hsotg, int val)
2734 {
2735         int valid = 1;
2736
2737         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2738                 if (val >= 0) {
2739                         dev_err(hsotg->dev, "Wrong value for speed parameter\n");
2740                         dev_err(hsotg->dev, "max_speed parameter must be 0 or 1\n");
2741                 }
2742                 valid = 0;
2743         }
2744
2745         if (val == DWC2_SPEED_PARAM_HIGH &&
2746             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2747                 valid = 0;
2748
2749         if (!valid) {
2750                 if (val >= 0)
2751                         dev_err(hsotg->dev,
2752                                 "%d invalid for speed parameter. Check HW configuration.\n",
2753                                 val);
2754                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS ?
2755                                 DWC2_SPEED_PARAM_FULL : DWC2_SPEED_PARAM_HIGH;
2756                 dev_dbg(hsotg->dev, "Setting speed to %d\n", val);
2757         }
2758
2759         hsotg->core_params->speed = val;
2760 }
2761
2762 void dwc2_set_param_host_ls_low_power_phy_clk(struct dwc2_hsotg *hsotg, int val)
2763 {
2764         int valid = 1;
2765
2766         if (DWC2_OUT_OF_BOUNDS(val, DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ,
2767                                DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) {
2768                 if (val >= 0) {
2769                         dev_err(hsotg->dev,
2770                                 "Wrong value for host_ls_low_power_phy_clk parameter\n");
2771                         dev_err(hsotg->dev,
2772                                 "host_ls_low_power_phy_clk must be 0 or 1\n");
2773                 }
2774                 valid = 0;
2775         }
2776
2777         if (val == DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ &&
2778             dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS)
2779                 valid = 0;
2780
2781         if (!valid) {
2782                 if (val >= 0)
2783                         dev_err(hsotg->dev,
2784                                 "%d invalid for host_ls_low_power_phy_clk. Check HW configuration.\n",
2785                                 val);
2786                 val = dwc2_get_param_phy_type(hsotg) == DWC2_PHY_TYPE_PARAM_FS
2787                         ? DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ
2788                         : DWC2_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ;
2789                 dev_dbg(hsotg->dev, "Setting host_ls_low_power_phy_clk to %d\n",
2790                         val);
2791         }
2792
2793         hsotg->core_params->host_ls_low_power_phy_clk = val;
2794 }
2795
2796 void dwc2_set_param_phy_ulpi_ddr(struct dwc2_hsotg *hsotg, int val)
2797 {
2798         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2799                 if (val >= 0) {
2800                         dev_err(hsotg->dev, "Wrong value for phy_ulpi_ddr\n");
2801                         dev_err(hsotg->dev, "phy_upli_ddr must be 0 or 1\n");
2802                 }
2803                 val = 0;
2804                 dev_dbg(hsotg->dev, "Setting phy_upli_ddr to %d\n", val);
2805         }
2806
2807         hsotg->core_params->phy_ulpi_ddr = val;
2808 }
2809
2810 void dwc2_set_param_phy_ulpi_ext_vbus(struct dwc2_hsotg *hsotg, int val)
2811 {
2812         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2813                 if (val >= 0) {
2814                         dev_err(hsotg->dev,
2815                                 "Wrong value for phy_ulpi_ext_vbus\n");
2816                         dev_err(hsotg->dev,
2817                                 "phy_ulpi_ext_vbus must be 0 or 1\n");
2818                 }
2819                 val = 0;
2820                 dev_dbg(hsotg->dev, "Setting phy_ulpi_ext_vbus to %d\n", val);
2821         }
2822
2823         hsotg->core_params->phy_ulpi_ext_vbus = val;
2824 }
2825
2826 void dwc2_set_param_phy_utmi_width(struct dwc2_hsotg *hsotg, int val)
2827 {
2828         int valid = 0;
2829
2830         switch (hsotg->hw_params.utmi_phy_data_width) {
2831         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8:
2832                 valid = (val == 8);
2833                 break;
2834         case GHWCFG4_UTMI_PHY_DATA_WIDTH_16:
2835                 valid = (val == 16);
2836                 break;
2837         case GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16:
2838                 valid = (val == 8 || val == 16);
2839                 break;
2840         }
2841
2842         if (!valid) {
2843                 if (val >= 0) {
2844                         dev_err(hsotg->dev,
2845                                 "%d invalid for phy_utmi_width. Check HW configuration.\n",
2846                                 val);
2847                 }
2848                 val = (hsotg->hw_params.utmi_phy_data_width ==
2849                        GHWCFG4_UTMI_PHY_DATA_WIDTH_8) ? 8 : 16;
2850                 dev_dbg(hsotg->dev, "Setting phy_utmi_width to %d\n", val);
2851         }
2852
2853         hsotg->core_params->phy_utmi_width = val;
2854 }
2855
2856 void dwc2_set_param_ulpi_fs_ls(struct dwc2_hsotg *hsotg, int val)
2857 {
2858         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2859                 if (val >= 0) {
2860                         dev_err(hsotg->dev, "Wrong value for ulpi_fs_ls\n");
2861                         dev_err(hsotg->dev, "ulpi_fs_ls must be 0 or 1\n");
2862                 }
2863                 val = 0;
2864                 dev_dbg(hsotg->dev, "Setting ulpi_fs_ls to %d\n", val);
2865         }
2866
2867         hsotg->core_params->ulpi_fs_ls = val;
2868 }
2869
2870 void dwc2_set_param_ts_dline(struct dwc2_hsotg *hsotg, int val)
2871 {
2872         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2873                 if (val >= 0) {
2874                         dev_err(hsotg->dev, "Wrong value for ts_dline\n");
2875                         dev_err(hsotg->dev, "ts_dline must be 0 or 1\n");
2876                 }
2877                 val = 0;
2878                 dev_dbg(hsotg->dev, "Setting ts_dline to %d\n", val);
2879         }
2880
2881         hsotg->core_params->ts_dline = val;
2882 }
2883
2884 void dwc2_set_param_i2c_enable(struct dwc2_hsotg *hsotg, int val)
2885 {
2886         int valid = 1;
2887
2888         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2889                 if (val >= 0) {
2890                         dev_err(hsotg->dev, "Wrong value for i2c_enable\n");
2891                         dev_err(hsotg->dev, "i2c_enable must be 0 or 1\n");
2892                 }
2893
2894                 valid = 0;
2895         }
2896
2897         if (val == 1 && !(hsotg->hw_params.i2c_enable))
2898                 valid = 0;
2899
2900         if (!valid) {
2901                 if (val >= 0)
2902                         dev_err(hsotg->dev,
2903                                 "%d invalid for i2c_enable. Check HW configuration.\n",
2904                                 val);
2905                 val = hsotg->hw_params.i2c_enable;
2906                 dev_dbg(hsotg->dev, "Setting i2c_enable to %d\n", val);
2907         }
2908
2909         hsotg->core_params->i2c_enable = val;
2910 }
2911
2912 void dwc2_set_param_en_multiple_tx_fifo(struct dwc2_hsotg *hsotg, int val)
2913 {
2914         int valid = 1;
2915
2916         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2917                 if (val >= 0) {
2918                         dev_err(hsotg->dev,
2919                                 "Wrong value for en_multiple_tx_fifo,\n");
2920                         dev_err(hsotg->dev,
2921                                 "en_multiple_tx_fifo must be 0 or 1\n");
2922                 }
2923                 valid = 0;
2924         }
2925
2926         if (val == 1 && !hsotg->hw_params.en_multiple_tx_fifo)
2927                 valid = 0;
2928
2929         if (!valid) {
2930                 if (val >= 0)
2931                         dev_err(hsotg->dev,
2932                                 "%d invalid for parameter en_multiple_tx_fifo. Check HW configuration.\n",
2933                                 val);
2934                 val = hsotg->hw_params.en_multiple_tx_fifo;
2935                 dev_dbg(hsotg->dev, "Setting en_multiple_tx_fifo to %d\n", val);
2936         }
2937
2938         hsotg->core_params->en_multiple_tx_fifo = val;
2939 }
2940
2941 void dwc2_set_param_reload_ctl(struct dwc2_hsotg *hsotg, int val)
2942 {
2943         int valid = 1;
2944
2945         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2946                 if (val >= 0) {
2947                         dev_err(hsotg->dev,
2948                                 "'%d' invalid for parameter reload_ctl\n", val);
2949                         dev_err(hsotg->dev, "reload_ctl must be 0 or 1\n");
2950                 }
2951                 valid = 0;
2952         }
2953
2954         if (val == 1 && hsotg->hw_params.snpsid < DWC2_CORE_REV_2_92a)
2955                 valid = 0;
2956
2957         if (!valid) {
2958                 if (val >= 0)
2959                         dev_err(hsotg->dev,
2960                                 "%d invalid for parameter reload_ctl. Check HW configuration.\n",
2961                                 val);
2962                 val = hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_92a;
2963                 dev_dbg(hsotg->dev, "Setting reload_ctl to %d\n", val);
2964         }
2965
2966         hsotg->core_params->reload_ctl = val;
2967 }
2968
2969 void dwc2_set_param_ahbcfg(struct dwc2_hsotg *hsotg, int val)
2970 {
2971         if (val != -1)
2972                 hsotg->core_params->ahbcfg = val;
2973         else
2974                 hsotg->core_params->ahbcfg = GAHBCFG_HBSTLEN_INCR4 <<
2975                                                 GAHBCFG_HBSTLEN_SHIFT;
2976 }
2977
2978 void dwc2_set_param_otg_ver(struct dwc2_hsotg *hsotg, int val)
2979 {
2980         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2981                 if (val >= 0) {
2982                         dev_err(hsotg->dev,
2983                                 "'%d' invalid for parameter otg_ver\n", val);
2984                         dev_err(hsotg->dev,
2985                                 "otg_ver must be 0 (for OTG 1.3 support) or 1 (for OTG 2.0 support)\n");
2986                 }
2987                 val = 0;
2988                 dev_dbg(hsotg->dev, "Setting otg_ver to %d\n", val);
2989         }
2990
2991         hsotg->core_params->otg_ver = val;
2992 }
2993
2994 static void dwc2_set_param_uframe_sched(struct dwc2_hsotg *hsotg, int val)
2995 {
2996         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
2997                 if (val >= 0) {
2998                         dev_err(hsotg->dev,
2999                                 "'%d' invalid for parameter uframe_sched\n",
3000                                 val);
3001                         dev_err(hsotg->dev, "uframe_sched must be 0 or 1\n");
3002                 }
3003                 val = 1;
3004                 dev_dbg(hsotg->dev, "Setting uframe_sched to %d\n", val);
3005         }
3006
3007         hsotg->core_params->uframe_sched = val;
3008 }
3009
3010 static void dwc2_set_param_external_id_pin_ctl(struct dwc2_hsotg *hsotg,
3011                 int val)
3012 {
3013         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3014                 if (val >= 0) {
3015                         dev_err(hsotg->dev,
3016                                 "'%d' invalid for parameter external_id_pin_ctl\n",
3017                                 val);
3018                         dev_err(hsotg->dev, "external_id_pin_ctl must be 0 or 1\n");
3019                 }
3020                 val = 0;
3021                 dev_dbg(hsotg->dev, "Setting external_id_pin_ctl to %d\n", val);
3022         }
3023
3024         hsotg->core_params->external_id_pin_ctl = val;
3025 }
3026
3027 static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
3028                 int val)
3029 {
3030         if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
3031                 if (val >= 0) {
3032                         dev_err(hsotg->dev,
3033                                 "'%d' invalid for parameter hibernation\n",
3034                                 val);
3035                         dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
3036                 }
3037                 val = 0;
3038                 dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
3039         }
3040
3041         hsotg->core_params->hibernation = val;
3042 }
3043
3044 /*
3045  * This function is called during module intialization to pass module parameters
3046  * for the DWC_otg core.
3047  */
3048 void dwc2_set_parameters(struct dwc2_hsotg *hsotg,
3049                          const struct dwc2_core_params *params)
3050 {
3051         dev_dbg(hsotg->dev, "%s()\n", __func__);
3052
3053         dwc2_set_param_otg_cap(hsotg, params->otg_cap);
3054         dwc2_set_param_dma_enable(hsotg, params->dma_enable);
3055         dwc2_set_param_dma_desc_enable(hsotg, params->dma_desc_enable);
3056         dwc2_set_param_dma_desc_fs_enable(hsotg, params->dma_desc_fs_enable);
3057         dwc2_set_param_host_support_fs_ls_low_power(hsotg,
3058                         params->host_support_fs_ls_low_power);
3059         dwc2_set_param_enable_dynamic_fifo(hsotg,
3060                         params->enable_dynamic_fifo);
3061         dwc2_set_param_host_rx_fifo_size(hsotg,
3062                         params->host_rx_fifo_size);
3063         dwc2_set_param_host_nperio_tx_fifo_size(hsotg,
3064                         params->host_nperio_tx_fifo_size);
3065         dwc2_set_param_host_perio_tx_fifo_size(hsotg,
3066                         params->host_perio_tx_fifo_size);
3067         dwc2_set_param_max_transfer_size(hsotg,
3068                         params->max_transfer_size);
3069         dwc2_set_param_max_packet_count(hsotg,
3070                         params->max_packet_count);
3071         dwc2_set_param_host_channels(hsotg, params->host_channels);
3072         dwc2_set_param_phy_type(hsotg, params->phy_type);
3073         dwc2_set_param_speed(hsotg, params->speed);
3074         dwc2_set_param_host_ls_low_power_phy_clk(hsotg,
3075                         params->host_ls_low_power_phy_clk);
3076         dwc2_set_param_phy_ulpi_ddr(hsotg, params->phy_ulpi_ddr);
3077         dwc2_set_param_phy_ulpi_ext_vbus(hsotg,
3078                         params->phy_ulpi_ext_vbus);
3079         dwc2_set_param_phy_utmi_width(hsotg, params->phy_utmi_width);
3080         dwc2_set_param_ulpi_fs_ls(hsotg, params->ulpi_fs_ls);
3081         dwc2_set_param_ts_dline(hsotg, params->ts_dline);
3082         dwc2_set_param_i2c_enable(hsotg, params->i2c_enable);
3083         dwc2_set_param_en_multiple_tx_fifo(hsotg,
3084                         params->en_multiple_tx_fifo);
3085         dwc2_set_param_reload_ctl(hsotg, params->reload_ctl);
3086         dwc2_set_param_ahbcfg(hsotg, params->ahbcfg);
3087         dwc2_set_param_otg_ver(hsotg, params->otg_ver);
3088         dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
3089         dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
3090         dwc2_set_param_hibernation(hsotg, params->hibernation);
3091 }
3092
3093 /**
3094  * During device initialization, read various hardware configuration
3095  * registers and interpret the contents.
3096  */
3097 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg)
3098 {
3099         struct dwc2_hw_params *hw = &hsotg->hw_params;
3100         unsigned width;
3101         u32 hwcfg1, hwcfg2, hwcfg3, hwcfg4;
3102         u32 hptxfsiz, grxfsiz, gnptxfsiz;
3103         u32 gusbcfg = 0;
3104
3105         /*
3106          * Attempt to ensure this device is really a DWC_otg Controller.
3107          * Read and verify the GSNPSID register contents. The value should be
3108          * 0x45f42xxx or 0x45f43xxx, which corresponds to either "OT2" or "OT3",
3109          * as in "OTG version 2.xx" or "OTG version 3.xx".
3110          */
3111         hw->snpsid = dwc2_readl(hsotg->regs + GSNPSID);
3112         if ((hw->snpsid & 0xfffff000) != 0x4f542000 &&
3113             (hw->snpsid & 0xfffff000) != 0x4f543000) {
3114                 dev_err(hsotg->dev, "Bad value for GSNPSID: 0x%08x\n",
3115                         hw->snpsid);
3116                 return -ENODEV;
3117         }
3118
3119         dev_dbg(hsotg->dev, "Core Release: %1x.%1x%1x%1x (snpsid=%x)\n",
3120                 hw->snpsid >> 12 & 0xf, hw->snpsid >> 8 & 0xf,
3121                 hw->snpsid >> 4 & 0xf, hw->snpsid & 0xf, hw->snpsid);
3122
3123         hwcfg1 = dwc2_readl(hsotg->regs + GHWCFG1);
3124         hwcfg2 = dwc2_readl(hsotg->regs + GHWCFG2);
3125         hwcfg3 = dwc2_readl(hsotg->regs + GHWCFG3);
3126         hwcfg4 = dwc2_readl(hsotg->regs + GHWCFG4);
3127         grxfsiz = dwc2_readl(hsotg->regs + GRXFSIZ);
3128
3129         dev_dbg(hsotg->dev, "hwcfg1=%08x\n", hwcfg1);
3130         dev_dbg(hsotg->dev, "hwcfg2=%08x\n", hwcfg2);
3131         dev_dbg(hsotg->dev, "hwcfg3=%08x\n", hwcfg3);
3132         dev_dbg(hsotg->dev, "hwcfg4=%08x\n", hwcfg4);
3133         dev_dbg(hsotg->dev, "grxfsiz=%08x\n", grxfsiz);
3134
3135         /* Force host mode to get HPTXFSIZ / GNPTXFSIZ exact power on value */
3136         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3137                 gusbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
3138                 dwc2_writel(gusbcfg | GUSBCFG_FORCEHOSTMODE,
3139                             hsotg->regs + GUSBCFG);
3140                 usleep_range(25000, 50000);
3141         }
3142
3143         gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
3144         hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
3145         dev_dbg(hsotg->dev, "gnptxfsiz=%08x\n", gnptxfsiz);
3146         dev_dbg(hsotg->dev, "hptxfsiz=%08x\n", hptxfsiz);
3147         if (hsotg->dr_mode != USB_DR_MODE_HOST) {
3148                 dwc2_writel(gusbcfg, hsotg->regs + GUSBCFG);
3149                 usleep_range(25000, 50000);
3150         }
3151
3152         /* hwcfg2 */
3153         hw->op_mode = (hwcfg2 & GHWCFG2_OP_MODE_MASK) >>
3154                       GHWCFG2_OP_MODE_SHIFT;
3155         hw->arch = (hwcfg2 & GHWCFG2_ARCHITECTURE_MASK) >>
3156                    GHWCFG2_ARCHITECTURE_SHIFT;
3157         hw->enable_dynamic_fifo = !!(hwcfg2 & GHWCFG2_DYNAMIC_FIFO);
3158         hw->host_channels = 1 + ((hwcfg2 & GHWCFG2_NUM_HOST_CHAN_MASK) >>
3159                                 GHWCFG2_NUM_HOST_CHAN_SHIFT);
3160         hw->hs_phy_type = (hwcfg2 & GHWCFG2_HS_PHY_TYPE_MASK) >>
3161                           GHWCFG2_HS_PHY_TYPE_SHIFT;
3162         hw->fs_phy_type = (hwcfg2 & GHWCFG2_FS_PHY_TYPE_MASK) >>
3163                           GHWCFG2_FS_PHY_TYPE_SHIFT;
3164         hw->num_dev_ep = (hwcfg2 & GHWCFG2_NUM_DEV_EP_MASK) >>
3165                          GHWCFG2_NUM_DEV_EP_SHIFT;
3166         hw->nperio_tx_q_depth =
3167                 (hwcfg2 & GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK) >>
3168                 GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT << 1;
3169         hw->host_perio_tx_q_depth =
3170                 (hwcfg2 & GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK) >>
3171                 GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT << 1;
3172         hw->dev_token_q_depth =
3173                 (hwcfg2 & GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK) >>
3174                 GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT;
3175
3176         /* hwcfg3 */
3177         width = (hwcfg3 & GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK) >>
3178                 GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT;
3179         hw->max_transfer_size = (1 << (width + 11)) - 1;
3180         /*
3181          * Clip max_transfer_size to 65535. dwc2_hc_setup_align_buf() allocates
3182          * coherent buffers with this size, and if it's too large we can
3183          * exhaust the coherent DMA pool.
3184          */
3185         if (hw->max_transfer_size > 65535)
3186                 hw->max_transfer_size = 65535;
3187         width = (hwcfg3 & GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK) >>
3188                 GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT;
3189         hw->max_packet_count = (1 << (width + 4)) - 1;
3190         hw->i2c_enable = !!(hwcfg3 & GHWCFG3_I2C);
3191         hw->total_fifo_size = (hwcfg3 & GHWCFG3_DFIFO_DEPTH_MASK) >>
3192                               GHWCFG3_DFIFO_DEPTH_SHIFT;
3193
3194         /* hwcfg4 */
3195         hw->en_multiple_tx_fifo = !!(hwcfg4 & GHWCFG4_DED_FIFO_EN);
3196         hw->num_dev_perio_in_ep = (hwcfg4 & GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK) >>
3197                                   GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT;
3198         hw->dma_desc_enable = !!(hwcfg4 & GHWCFG4_DESC_DMA);
3199         hw->power_optimized = !!(hwcfg4 & GHWCFG4_POWER_OPTIMIZ);
3200         hw->utmi_phy_data_width = (hwcfg4 & GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK) >>
3201                                   GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT;
3202
3203         /* fifo sizes */
3204         hw->host_rx_fifo_size = (grxfsiz & GRXFSIZ_DEPTH_MASK) >>
3205                                 GRXFSIZ_DEPTH_SHIFT;
3206         hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3207                                        FIFOSIZE_DEPTH_SHIFT;
3208         hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >>
3209                                       FIFOSIZE_DEPTH_SHIFT;
3210
3211         dev_dbg(hsotg->dev, "Detected values from hardware:\n");
3212         dev_dbg(hsotg->dev, "  op_mode=%d\n",
3213                 hw->op_mode);
3214         dev_dbg(hsotg->dev, "  arch=%d\n",
3215                 hw->arch);
3216         dev_dbg(hsotg->dev, "  dma_desc_enable=%d\n",
3217                 hw->dma_desc_enable);
3218         dev_dbg(hsotg->dev, "  power_optimized=%d\n",
3219                 hw->power_optimized);
3220         dev_dbg(hsotg->dev, "  i2c_enable=%d\n",
3221                 hw->i2c_enable);
3222         dev_dbg(hsotg->dev, "  hs_phy_type=%d\n",
3223                 hw->hs_phy_type);
3224         dev_dbg(hsotg->dev, "  fs_phy_type=%d\n",
3225                 hw->fs_phy_type);
3226         dev_dbg(hsotg->dev, "  utmi_phy_data_width=%d\n",
3227                 hw->utmi_phy_data_width);
3228         dev_dbg(hsotg->dev, "  num_dev_ep=%d\n",
3229                 hw->num_dev_ep);
3230         dev_dbg(hsotg->dev, "  num_dev_perio_in_ep=%d\n",
3231                 hw->num_dev_perio_in_ep);
3232         dev_dbg(hsotg->dev, "  host_channels=%d\n",
3233                 hw->host_channels);
3234         dev_dbg(hsotg->dev, "  max_transfer_size=%d\n",
3235                 hw->max_transfer_size);
3236         dev_dbg(hsotg->dev, "  max_packet_count=%d\n",
3237                 hw->max_packet_count);
3238         dev_dbg(hsotg->dev, "  nperio_tx_q_depth=0x%0x\n",
3239                 hw->nperio_tx_q_depth);
3240         dev_dbg(hsotg->dev, "  host_perio_tx_q_depth=0x%0x\n",
3241                 hw->host_perio_tx_q_depth);
3242         dev_dbg(hsotg->dev, "  dev_token_q_depth=0x%0x\n",
3243                 hw->dev_token_q_depth);
3244         dev_dbg(hsotg->dev, "  enable_dynamic_fifo=%d\n",
3245                 hw->enable_dynamic_fifo);
3246         dev_dbg(hsotg->dev, "  en_multiple_tx_fifo=%d\n",
3247                 hw->en_multiple_tx_fifo);
3248         dev_dbg(hsotg->dev, "  total_fifo_size=%d\n",
3249                 hw->total_fifo_size);
3250         dev_dbg(hsotg->dev, "  host_rx_fifo_size=%d\n",
3251                 hw->host_rx_fifo_size);
3252         dev_dbg(hsotg->dev, "  host_nperio_tx_fifo_size=%d\n",
3253                 hw->host_nperio_tx_fifo_size);
3254         dev_dbg(hsotg->dev, "  host_perio_tx_fifo_size=%d\n",
3255                 hw->host_perio_tx_fifo_size);
3256         dev_dbg(hsotg->dev, "\n");
3257
3258         return 0;
3259 }
3260
3261 /*
3262  * Sets all parameters to the given value.
3263  *
3264  * Assumes that the dwc2_core_params struct contains only integers.
3265  */
3266 void dwc2_set_all_params(struct dwc2_core_params *params, int value)
3267 {
3268         int *p = (int *)params;
3269         size_t size = sizeof(*params) / sizeof(*p);
3270         int i;
3271
3272         for (i = 0; i < size; i++)
3273                 p[i] = value;
3274 }
3275
3276
3277 u16 dwc2_get_otg_version(struct dwc2_hsotg *hsotg)
3278 {
3279         return hsotg->core_params->otg_ver == 1 ? 0x0200 : 0x0103;
3280 }
3281
3282 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
3283 {
3284         if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
3285                 return false;
3286         else
3287                 return true;
3288 }
3289
3290 /**
3291  * dwc2_enable_global_interrupts() - Enables the controller's Global
3292  * Interrupt in the AHB Config register
3293  *
3294  * @hsotg: Programming view of DWC_otg controller
3295  */
3296 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
3297 {
3298         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3299
3300         ahbcfg |= GAHBCFG_GLBL_INTR_EN;
3301         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3302 }
3303
3304 /**
3305  * dwc2_disable_global_interrupts() - Disables the controller's Global
3306  * Interrupt in the AHB Config register
3307  *
3308  * @hsotg: Programming view of DWC_otg controller
3309  */
3310 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
3311 {
3312         u32 ahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
3313
3314         ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
3315         dwc2_writel(ahbcfg, hsotg->regs + GAHBCFG);
3316 }
3317
3318 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
3319 MODULE_AUTHOR("Synopsys, Inc.");
3320 MODULE_LICENSE("Dual BSD/GPL");