2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
34 #define CDNS_UART_TTY_NAME "ttyPS"
35 #define CDNS_UART_NAME "xuartps"
36 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38 #define CDNS_UART_NR_PORTS 2
39 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40 #define CDNS_UART_REGISTER_SPACE 0xFFF
42 #define cdns_uart_readl(offset) ioread32(port->membase + offset)
43 #define cdns_uart_writel(val, offset) iowrite32(val, port->membase + offset)
45 /* Rx Trigger level */
46 static int rx_trigger_level = 56;
47 module_param(rx_trigger_level, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
51 static int rx_timeout = 10;
52 module_param(rx_timeout, uint, S_IRUGO);
53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
55 /* Register offsets for the UART. */
56 #define CDNS_UART_CR_OFFSET 0x00 /* Control Register */
57 #define CDNS_UART_MR_OFFSET 0x04 /* Mode Register */
58 #define CDNS_UART_IER_OFFSET 0x08 /* Interrupt Enable */
59 #define CDNS_UART_IDR_OFFSET 0x0C /* Interrupt Disable */
60 #define CDNS_UART_IMR_OFFSET 0x10 /* Interrupt Mask */
61 #define CDNS_UART_ISR_OFFSET 0x14 /* Interrupt Status */
62 #define CDNS_UART_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator */
63 #define CDNS_UART_RXTOUT_OFFSET 0x1C /* RX Timeout */
64 #define CDNS_UART_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level */
65 #define CDNS_UART_MODEMCR_OFFSET 0x24 /* Modem Control */
66 #define CDNS_UART_MODEMSR_OFFSET 0x28 /* Modem Status */
67 #define CDNS_UART_SR_OFFSET 0x2C /* Channel Status */
68 #define CDNS_UART_FIFO_OFFSET 0x30 /* FIFO */
69 #define CDNS_UART_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider */
70 #define CDNS_UART_FLOWDEL_OFFSET 0x38 /* Flow Delay */
71 #define CDNS_UART_IRRX_PWIDTH_OFFSET 0x3C /* IR Min Received Pulse Width */
72 #define CDNS_UART_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse Width */
73 #define CDNS_UART_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level */
75 /* Control Register Bit Definitions */
76 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
77 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
78 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
79 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
80 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
81 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
82 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
83 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
84 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
88 * The mode register (MR) defines the mode of transfer as well as the data
89 * format. If this register is modified during transmission or reception,
90 * data validity cannot be guaranteed.
92 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
93 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
94 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
96 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
97 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
99 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
100 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
101 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
102 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
103 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
105 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
106 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
107 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
110 * Interrupt Registers:
111 * Interrupt control logic uses the interrupt enable register (IER) and the
112 * interrupt disable register (IDR) to set the value of the bits in the
113 * interrupt mask register (IMR). The IMR determines whether to pass an
114 * interrupt to the interrupt status register (ISR).
115 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
116 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
117 * Reading either IER or IDR returns 0x00.
118 * All four registers have the same bit definitions.
120 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
121 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
122 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
123 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
124 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
125 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
126 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
127 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
128 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
129 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
130 #define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
132 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
133 #define CDNS_UART_IXR_BRK 0x80000000
136 * Channel Status Register:
137 * The channel status register (CSR) is provided to enable the control logic
138 * to monitor the status of bits in the channel interrupt status register,
139 * even if these are masked out by the interrupt mask register.
141 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
142 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
143 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
144 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
146 /* baud dividers min/max values */
147 #define CDNS_UART_BDIV_MIN 4
148 #define CDNS_UART_BDIV_MAX 255
149 #define CDNS_UART_CD_MAX 65535
152 * struct cdns_uart - device data
153 * @port: Pointer to the UART port
154 * @uartclk: Reference clock
156 * @baud: Current baud rate
157 * @clk_rate_change_nb: Notifier block for clock changes
160 struct uart_port *port;
164 struct notifier_block clk_rate_change_nb;
166 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
170 * cdns_uart_isr - Interrupt handler
172 * @dev_id: Id of the port
176 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
178 struct uart_port *port = (struct uart_port *)dev_id;
180 unsigned int isrstatus, numbytes;
182 char status = TTY_NORMAL;
184 spin_lock_irqsave(&port->lock, flags);
186 /* Read the interrupt status register to determine which
187 * interrupt(s) is/are active.
189 isrstatus = cdns_uart_readl(CDNS_UART_ISR_OFFSET);
192 * There is no hardware break detection, so we interpret framing
193 * error with all-zeros data as a break sequence. Most of the time,
194 * there's another non-zero byte at the end of the sequence.
196 if (isrstatus & CDNS_UART_IXR_FRAMING) {
197 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
198 CDNS_UART_SR_RXEMPTY)) {
199 if (!cdns_uart_readl(CDNS_UART_FIFO_OFFSET)) {
200 port->read_status_mask |= CDNS_UART_IXR_BRK;
201 isrstatus &= ~CDNS_UART_IXR_FRAMING;
204 cdns_uart_writel(CDNS_UART_IXR_FRAMING, CDNS_UART_ISR_OFFSET);
207 /* drop byte with parity error if IGNPAR specified */
208 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
209 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
211 isrstatus &= port->read_status_mask;
212 isrstatus &= ~port->ignore_status_mask;
214 if ((isrstatus & CDNS_UART_IXR_TOUT) ||
215 (isrstatus & CDNS_UART_IXR_RXTRIG)) {
216 /* Receive Timeout Interrupt */
217 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
218 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
219 data = cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
221 /* Non-NULL byte after BREAK is garbage (99%) */
222 if (data && (port->read_status_mask &
223 CDNS_UART_IXR_BRK)) {
224 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
226 if (uart_handle_break(port))
232 * uart_handle_sysrq_char() doesn't work if
233 * spinlocked, for some reason
236 spin_unlock(&port->lock);
237 if (uart_handle_sysrq_char(port,
238 (unsigned char)data)) {
239 spin_lock(&port->lock);
242 spin_lock(&port->lock);
248 if (isrstatus & CDNS_UART_IXR_PARITY) {
249 port->icount.parity++;
251 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
252 port->icount.frame++;
254 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
255 port->icount.overrun++;
258 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
261 spin_unlock(&port->lock);
262 tty_flip_buffer_push(&port->state->port);
263 spin_lock(&port->lock);
266 /* Dispatch an appropriate handler */
267 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY) {
268 if (uart_circ_empty(&port->state->xmit)) {
269 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY,
270 CDNS_UART_IDR_OFFSET);
272 numbytes = port->fifosize;
273 /* Break if no more data available in the UART buffer */
275 if (uart_circ_empty(&port->state->xmit))
277 /* Get the data from the UART circular buffer
278 * and write it to the cdns_uart's TX_FIFO
282 port->state->xmit.buf[port->state->xmit.
283 tail], CDNS_UART_FIFO_OFFSET);
287 /* Adjust the tail of the UART buffer and wrap
288 * the buffer if it reaches limit.
290 port->state->xmit.tail =
291 (port->state->xmit.tail + 1) &
292 (UART_XMIT_SIZE - 1);
295 if (uart_circ_chars_pending(
296 &port->state->xmit) < WAKEUP_CHARS)
297 uart_write_wakeup(port);
301 cdns_uart_writel(isrstatus, CDNS_UART_ISR_OFFSET);
303 /* be sure to release the lock and tty before leaving */
304 spin_unlock_irqrestore(&port->lock, flags);
310 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
311 * @clk: UART module input clock
312 * @baud: Desired baud rate
313 * @rbdiv: BDIV value (return value)
314 * @rcd: CD value (return value)
315 * @div8: Value for clk_sel bit in mod (return value)
316 * Return: baud rate, requested baud when possible, or actual baud when there
317 * was too much error, zero if no valid divisors are found.
319 * Formula to obtain baud rate is
320 * baud_tx/rx rate = clk/CD * (BDIV + 1)
321 * input_clk = (Uart User Defined Clock or Apb Clock)
322 * depends on UCLKEN in MR Reg
323 * clk = input_clk or input_clk/8;
324 * depends on CLKS in MR reg
325 * CD and BDIV depends on values in
326 * baud rate generate register
327 * baud rate clock divisor register
329 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
330 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
333 unsigned int calc_baud;
334 unsigned int bestbaud = 0;
335 unsigned int bauderror;
336 unsigned int besterror = ~0;
338 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
345 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
346 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
347 if (cd < 1 || cd > CDNS_UART_CD_MAX)
350 calc_baud = clk / (cd * (bdiv + 1));
352 if (baud > calc_baud)
353 bauderror = baud - calc_baud;
355 bauderror = calc_baud - baud;
357 if (besterror > bauderror) {
360 bestbaud = calc_baud;
361 besterror = bauderror;
364 /* use the values when percent error is acceptable */
365 if (((besterror * 100) / baud) < 3)
372 * cdns_uart_set_baud_rate - Calculate and set the baud rate
373 * @port: Handle to the uart port structure
374 * @baud: Baud rate to set
375 * Return: baud rate, requested baud when possible, or actual baud when there
376 * was too much error, zero if no valid divisors are found.
378 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
381 unsigned int calc_baud;
382 u32 cd = 0, bdiv = 0;
385 struct cdns_uart *cdns_uart = port->private_data;
387 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
390 /* Write new divisors to hardware */
391 mreg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
393 mreg |= CDNS_UART_MR_CLKSEL;
395 mreg &= ~CDNS_UART_MR_CLKSEL;
396 cdns_uart_writel(mreg, CDNS_UART_MR_OFFSET);
397 cdns_uart_writel(cd, CDNS_UART_BAUDGEN_OFFSET);
398 cdns_uart_writel(bdiv, CDNS_UART_BAUDDIV_OFFSET);
399 cdns_uart->baud = baud;
404 #ifdef CONFIG_COMMON_CLK
406 * cdns_uart_clk_notitifer_cb - Clock notifier callback
407 * @nb: Notifier block
408 * @event: Notify event
409 * @data: Notifier data
410 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
412 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
413 unsigned long event, void *data)
416 struct uart_port *port;
418 struct clk_notifier_data *ndata = data;
419 unsigned long flags = 0;
420 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
422 port = cdns_uart->port;
427 case PRE_RATE_CHANGE:
433 * Find out if current baud-rate can be achieved with new clock
436 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
437 &bdiv, &cd, &div8)) {
438 dev_warn(port->dev, "clock rate change rejected\n");
442 spin_lock_irqsave(&cdns_uart->port->lock, flags);
444 /* Disable the TX and RX to set baud rate */
445 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
446 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
447 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
449 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
453 case POST_RATE_CHANGE:
455 * Set clk dividers to generate correct baud with new clock
459 spin_lock_irqsave(&cdns_uart->port->lock, flags);
462 port->uartclk = ndata->new_rate;
464 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
467 case ABORT_RATE_CHANGE:
469 spin_lock_irqsave(&cdns_uart->port->lock, flags);
471 /* Set TX/RX Reset */
472 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
473 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
474 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
476 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
477 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
481 * Clear the RX disable and TX disable bits and then set the TX
482 * enable bit and RX enable bit to enable the transmitter and
485 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
486 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
487 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
488 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
489 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
491 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
501 * cdns_uart_start_tx - Start transmitting bytes
502 * @port: Handle to the uart port structure
504 static void cdns_uart_start_tx(struct uart_port *port)
506 unsigned int status, numbytes = port->fifosize;
508 if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
511 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
512 /* Set the TX enable bit and clear the TX disable bit to enable the
515 cdns_uart_writel((status & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
516 CDNS_UART_CR_OFFSET);
518 while (numbytes-- && ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
519 CDNS_UART_SR_TXFULL)) != CDNS_UART_SR_TXFULL) {
520 /* Break if no more data available in the UART buffer */
521 if (uart_circ_empty(&port->state->xmit))
524 /* Get the data from the UART circular buffer and
525 * write it to the cdns_uart's TX_FIFO register.
528 port->state->xmit.buf[port->state->xmit.tail],
529 CDNS_UART_FIFO_OFFSET);
532 /* Adjust the tail of the UART buffer and wrap
533 * the buffer if it reaches limit.
535 port->state->xmit.tail = (port->state->xmit.tail + 1) &
536 (UART_XMIT_SIZE - 1);
538 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_ISR_OFFSET);
539 /* Enable the TX Empty interrupt */
540 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY, CDNS_UART_IER_OFFSET);
542 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
543 uart_write_wakeup(port);
547 * cdns_uart_stop_tx - Stop TX
548 * @port: Handle to the uart port structure
550 static void cdns_uart_stop_tx(struct uart_port *port)
554 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
555 regval |= CDNS_UART_CR_TX_DIS;
556 /* Disable the transmitter */
557 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
561 * cdns_uart_stop_rx - Stop RX
562 * @port: Handle to the uart port structure
564 static void cdns_uart_stop_rx(struct uart_port *port)
568 regval = cdns_uart_readl(CDNS_UART_CR_OFFSET);
569 regval |= CDNS_UART_CR_RX_DIS;
570 /* Disable the receiver */
571 cdns_uart_writel(regval, CDNS_UART_CR_OFFSET);
575 * cdns_uart_tx_empty - Check whether TX is empty
576 * @port: Handle to the uart port structure
578 * Return: TIOCSER_TEMT on success, 0 otherwise
580 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
584 status = cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY;
585 return status ? TIOCSER_TEMT : 0;
589 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
590 * transmitting char breaks
591 * @port: Handle to the uart port structure
592 * @ctl: Value based on which start or stop decision is taken
594 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
599 spin_lock_irqsave(&port->lock, flags);
601 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
604 cdns_uart_writel(CDNS_UART_CR_STARTBRK | status,
605 CDNS_UART_CR_OFFSET);
607 if ((status & CDNS_UART_CR_STOPBRK) == 0)
608 cdns_uart_writel(CDNS_UART_CR_STOPBRK | status,
609 CDNS_UART_CR_OFFSET);
611 spin_unlock_irqrestore(&port->lock, flags);
615 * cdns_uart_set_termios - termios operations, handling data length, parity,
616 * stop bits, flow control, baud rate
617 * @port: Handle to the uart port structure
618 * @termios: Handle to the input termios structure
619 * @old: Values of the previously saved termios structure
621 static void cdns_uart_set_termios(struct uart_port *port,
622 struct ktermios *termios, struct ktermios *old)
624 unsigned int cval = 0;
625 unsigned int baud, minbaud, maxbaud;
627 unsigned int ctrl_reg, mode_reg;
629 spin_lock_irqsave(&port->lock, flags);
631 /* Empty the receive FIFO 1st before making changes */
632 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) &
633 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
634 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
637 /* Disable the TX and RX to set baud rate */
638 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
639 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
640 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
643 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
644 * min and max baud should be calculated here based on port->uartclk.
645 * this way we get a valid baud and can safely call set_baud()
647 minbaud = port->uartclk /
648 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
649 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
650 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
651 baud = cdns_uart_set_baud_rate(port, baud);
652 if (tty_termios_baud_rate(termios))
653 tty_termios_encode_baud_rate(termios, baud, baud);
655 /* Update the per-port timeout. */
656 uart_update_timeout(port, termios->c_cflag, baud);
658 /* Set TX/RX Reset */
659 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
660 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
661 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
664 * Clear the RX disable and TX disable bits and then set the TX enable
665 * bit and RX enable bit to enable the transmitter and receiver.
667 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
668 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
669 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
670 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
672 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
674 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
675 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
676 port->ignore_status_mask = 0;
678 if (termios->c_iflag & INPCK)
679 port->read_status_mask |= CDNS_UART_IXR_PARITY |
680 CDNS_UART_IXR_FRAMING;
682 if (termios->c_iflag & IGNPAR)
683 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
684 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
686 /* ignore all characters if CREAD is not set */
687 if ((termios->c_cflag & CREAD) == 0)
688 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
689 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
690 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
692 mode_reg = cdns_uart_readl(CDNS_UART_MR_OFFSET);
694 /* Handling Data Size */
695 switch (termios->c_cflag & CSIZE) {
697 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
700 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
704 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
705 termios->c_cflag &= ~CSIZE;
706 termios->c_cflag |= CS8;
710 /* Handling Parity and Stop Bits length */
711 if (termios->c_cflag & CSTOPB)
712 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
714 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
716 if (termios->c_cflag & PARENB) {
717 /* Mark or Space parity */
718 if (termios->c_cflag & CMSPAR) {
719 if (termios->c_cflag & PARODD)
720 cval |= CDNS_UART_MR_PARITY_MARK;
722 cval |= CDNS_UART_MR_PARITY_SPACE;
724 if (termios->c_cflag & PARODD)
725 cval |= CDNS_UART_MR_PARITY_ODD;
727 cval |= CDNS_UART_MR_PARITY_EVEN;
730 cval |= CDNS_UART_MR_PARITY_NONE;
732 cval |= mode_reg & 1;
733 cdns_uart_writel(cval, CDNS_UART_MR_OFFSET);
735 spin_unlock_irqrestore(&port->lock, flags);
739 * cdns_uart_startup - Called when an application opens a cdns_uart port
740 * @port: Handle to the uart port structure
742 * Return: 0 on success, negative errno otherwise
744 static int cdns_uart_startup(struct uart_port *port)
746 unsigned int retval = 0, status = 0;
748 retval = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME,
753 /* Disable the TX and RX */
754 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
755 CDNS_UART_CR_OFFSET);
757 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
760 cdns_uart_writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
761 CDNS_UART_CR_OFFSET);
763 status = cdns_uart_readl(CDNS_UART_CR_OFFSET);
765 /* Clear the RX disable and TX disable bits and then set the TX enable
766 * bit and RX enable bit to enable the transmitter and receiver.
768 cdns_uart_writel((status & ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS))
769 | (CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN |
770 CDNS_UART_CR_STOPBRK), CDNS_UART_CR_OFFSET);
772 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
775 cdns_uart_writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
776 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
777 CDNS_UART_MR_OFFSET);
780 * Set the RX FIFO Trigger level to use most of the FIFO, but it
781 * can be tuned with a module parameter
783 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
786 * Receive Timeout register is enabled but it
787 * can be tuned with a module parameter
789 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
791 /* Clear out any pending interrupts before enabling them */
792 cdns_uart_writel(cdns_uart_readl(CDNS_UART_ISR_OFFSET),
793 CDNS_UART_ISR_OFFSET);
795 /* Set the Interrupt Registers with desired interrupts */
796 cdns_uart_writel(CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_PARITY |
797 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN |
798 CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT,
799 CDNS_UART_IER_OFFSET);
805 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
806 * @port: Handle to the uart port structure
808 static void cdns_uart_shutdown(struct uart_port *port)
812 /* Disable interrupts */
813 status = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
814 cdns_uart_writel(status, CDNS_UART_IDR_OFFSET);
816 /* Disable the TX and RX */
817 cdns_uart_writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
818 CDNS_UART_CR_OFFSET);
819 free_irq(port->irq, port);
823 * cdns_uart_type - Set UART type to cdns_uart port
824 * @port: Handle to the uart port structure
826 * Return: string on success, NULL otherwise
828 static const char *cdns_uart_type(struct uart_port *port)
830 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
834 * cdns_uart_verify_port - Verify the port params
835 * @port: Handle to the uart port structure
836 * @ser: Handle to the structure whose members are compared
838 * Return: 0 on success, negative errno otherwise.
840 static int cdns_uart_verify_port(struct uart_port *port,
841 struct serial_struct *ser)
843 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
845 if (port->irq != ser->irq)
847 if (ser->io_type != UPIO_MEM)
849 if (port->iobase != ser->port)
857 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
858 * called when the driver adds a cdns_uart port via
859 * uart_add_one_port()
860 * @port: Handle to the uart port structure
862 * Return: 0 on success, negative errno otherwise.
864 static int cdns_uart_request_port(struct uart_port *port)
866 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
871 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
872 if (!port->membase) {
873 dev_err(port->dev, "Unable to map registers\n");
874 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
881 * cdns_uart_release_port - Release UART port
882 * @port: Handle to the uart port structure
884 * Release the memory region attached to a cdns_uart port. Called when the
885 * driver removes a cdns_uart port via uart_remove_one_port().
887 static void cdns_uart_release_port(struct uart_port *port)
889 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
890 iounmap(port->membase);
891 port->membase = NULL;
895 * cdns_uart_config_port - Configure UART port
896 * @port: Handle to the uart port structure
899 static void cdns_uart_config_port(struct uart_port *port, int flags)
901 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
902 port->type = PORT_XUARTPS;
906 * cdns_uart_get_mctrl - Get the modem control state
907 * @port: Handle to the uart port structure
909 * Return: the modem control state
911 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
913 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
916 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
921 #ifdef CONFIG_CONSOLE_POLL
922 static int cdns_uart_poll_get_char(struct uart_port *port)
927 /* Disable all interrupts */
928 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
929 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
931 /* Check if FIFO is empty */
932 if (cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_RXEMPTY)
934 else /* Read a character */
935 c = (unsigned char) cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
937 /* Enable interrupts */
938 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
943 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
947 /* Disable all interrupts */
948 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
949 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
951 /* Wait until FIFO is empty */
952 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
955 /* Write a character */
956 cdns_uart_writel(c, CDNS_UART_FIFO_OFFSET);
958 /* Wait until FIFO is empty */
959 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY))
962 /* Enable interrupts */
963 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
969 static struct uart_ops cdns_uart_ops = {
970 .set_mctrl = cdns_uart_set_mctrl,
971 .get_mctrl = cdns_uart_get_mctrl,
972 .start_tx = cdns_uart_start_tx,
973 .stop_tx = cdns_uart_stop_tx,
974 .stop_rx = cdns_uart_stop_rx,
975 .tx_empty = cdns_uart_tx_empty,
976 .break_ctl = cdns_uart_break_ctl,
977 .set_termios = cdns_uart_set_termios,
978 .startup = cdns_uart_startup,
979 .shutdown = cdns_uart_shutdown,
980 .type = cdns_uart_type,
981 .verify_port = cdns_uart_verify_port,
982 .request_port = cdns_uart_request_port,
983 .release_port = cdns_uart_release_port,
984 .config_port = cdns_uart_config_port,
985 #ifdef CONFIG_CONSOLE_POLL
986 .poll_get_char = cdns_uart_poll_get_char,
987 .poll_put_char = cdns_uart_poll_put_char,
991 static struct uart_port cdns_uart_port[2];
994 * cdns_uart_get_port - Configure the port from platform device resource info
997 * Return: a pointer to a uart_port or NULL for failure
999 static struct uart_port *cdns_uart_get_port(int id)
1001 struct uart_port *port;
1003 /* Try the given port id if failed use default method */
1004 if (cdns_uart_port[id].mapbase != 0) {
1005 /* Find the next unused port */
1006 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1007 if (cdns_uart_port[id].mapbase == 0)
1011 if (id >= CDNS_UART_NR_PORTS)
1014 port = &cdns_uart_port[id];
1016 /* At this point, we've got an empty uart_port struct, initialize it */
1017 spin_lock_init(&port->lock);
1018 port->membase = NULL;
1019 port->iobase = 1; /* mark port in use */
1021 port->type = PORT_UNKNOWN;
1022 port->iotype = UPIO_MEM32;
1023 port->flags = UPF_BOOT_AUTOCONF;
1024 port->ops = &cdns_uart_ops;
1025 port->fifosize = CDNS_UART_FIFO_SIZE;
1031 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1033 * cdns_uart_console_wait_tx - Wait for the TX to be full
1034 * @port: Handle to the uart port structure
1036 static void cdns_uart_console_wait_tx(struct uart_port *port)
1038 while ((cdns_uart_readl(CDNS_UART_SR_OFFSET) & CDNS_UART_SR_TXEMPTY)
1039 != CDNS_UART_SR_TXEMPTY)
1044 * cdns_uart_console_putchar - write the character to the FIFO buffer
1045 * @port: Handle to the uart port structure
1046 * @ch: Character to be written
1048 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1050 cdns_uart_console_wait_tx(port);
1051 cdns_uart_writel(ch, CDNS_UART_FIFO_OFFSET);
1054 static void cdns_early_write(struct console *con, const char *s, unsigned n)
1056 struct earlycon_device *dev = con->data;
1058 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1061 static int __init cdns_early_console_setup(struct earlycon_device *device,
1064 if (!device->port.membase)
1067 device->con->write = cdns_early_write;
1071 EARLYCON_DECLARE(cdns, cdns_early_console_setup);
1074 * cdns_uart_console_write - perform write operation
1075 * @co: Console handle
1076 * @s: Pointer to character array
1077 * @count: No of characters
1079 static void cdns_uart_console_write(struct console *co, const char *s,
1082 struct uart_port *port = &cdns_uart_port[co->index];
1083 unsigned long flags;
1084 unsigned int imr, ctrl;
1087 if (oops_in_progress)
1088 locked = spin_trylock_irqsave(&port->lock, flags);
1090 spin_lock_irqsave(&port->lock, flags);
1092 /* save and disable interrupt */
1093 imr = cdns_uart_readl(CDNS_UART_IMR_OFFSET);
1094 cdns_uart_writel(imr, CDNS_UART_IDR_OFFSET);
1097 * Make sure that the tx part is enabled. Set the TX enable bit and
1098 * clear the TX disable bit to enable the transmitter.
1100 ctrl = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1101 cdns_uart_writel((ctrl & ~CDNS_UART_CR_TX_DIS) | CDNS_UART_CR_TX_EN,
1102 CDNS_UART_CR_OFFSET);
1104 uart_console_write(port, s, count, cdns_uart_console_putchar);
1105 cdns_uart_console_wait_tx(port);
1107 cdns_uart_writel(ctrl, CDNS_UART_CR_OFFSET);
1109 /* restore interrupt state */
1110 cdns_uart_writel(imr, CDNS_UART_IER_OFFSET);
1113 spin_unlock_irqrestore(&port->lock, flags);
1117 * cdns_uart_console_setup - Initialize the uart to default config
1118 * @co: Console handle
1119 * @options: Initial settings of uart
1121 * Return: 0 on success, negative errno otherwise.
1123 static int __init cdns_uart_console_setup(struct console *co, char *options)
1125 struct uart_port *port = &cdns_uart_port[co->index];
1131 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1134 if (!port->mapbase) {
1135 pr_debug("console on ttyPS%i not present\n", co->index);
1140 uart_parse_options(options, &baud, &parity, &bits, &flow);
1142 return uart_set_options(port, co, baud, parity, bits, flow);
1145 static struct uart_driver cdns_uart_uart_driver;
1147 static struct console cdns_uart_console = {
1148 .name = CDNS_UART_TTY_NAME,
1149 .write = cdns_uart_console_write,
1150 .device = uart_console_device,
1151 .setup = cdns_uart_console_setup,
1152 .flags = CON_PRINTBUFFER,
1153 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1154 .data = &cdns_uart_uart_driver,
1158 * cdns_uart_console_init - Initialization call
1160 * Return: 0 on success, negative errno otherwise
1162 static int __init cdns_uart_console_init(void)
1164 register_console(&cdns_uart_console);
1168 console_initcall(cdns_uart_console_init);
1170 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1172 static struct uart_driver cdns_uart_uart_driver = {
1173 .owner = THIS_MODULE,
1174 .driver_name = CDNS_UART_NAME,
1175 .dev_name = CDNS_UART_TTY_NAME,
1176 .major = CDNS_UART_MAJOR,
1177 .minor = CDNS_UART_MINOR,
1178 .nr = CDNS_UART_NR_PORTS,
1179 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1180 .cons = &cdns_uart_console,
1184 #ifdef CONFIG_PM_SLEEP
1186 * cdns_uart_suspend - suspend event
1187 * @device: Pointer to the device structure
1191 static int cdns_uart_suspend(struct device *device)
1193 struct uart_port *port = dev_get_drvdata(device);
1194 struct tty_struct *tty;
1195 struct device *tty_dev;
1198 /* Get the tty which could be NULL so don't assume it's valid */
1199 tty = tty_port_tty_get(&port->state->port);
1202 may_wake = device_may_wakeup(tty_dev);
1207 * Call the API provided in serial_core.c file which handles
1210 uart_suspend_port(&cdns_uart_uart_driver, port);
1211 if (console_suspend_enabled && !may_wake) {
1212 struct cdns_uart *cdns_uart = port->private_data;
1214 clk_disable(cdns_uart->uartclk);
1215 clk_disable(cdns_uart->pclk);
1217 unsigned long flags = 0;
1219 spin_lock_irqsave(&port->lock, flags);
1220 /* Empty the receive FIFO 1st before making changes */
1221 while (!(cdns_uart_readl(CDNS_UART_SR_OFFSET) &
1222 CDNS_UART_SR_RXEMPTY))
1223 cdns_uart_readl(CDNS_UART_FIFO_OFFSET);
1224 /* set RX trigger level to 1 */
1225 cdns_uart_writel(1, CDNS_UART_RXWM_OFFSET);
1226 /* disable RX timeout interrups */
1227 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IDR_OFFSET);
1228 spin_unlock_irqrestore(&port->lock, flags);
1235 * cdns_uart_resume - Resume after a previous suspend
1236 * @device: Pointer to the device structure
1240 static int cdns_uart_resume(struct device *device)
1242 struct uart_port *port = dev_get_drvdata(device);
1243 unsigned long flags = 0;
1245 struct tty_struct *tty;
1246 struct device *tty_dev;
1249 /* Get the tty which could be NULL so don't assume it's valid */
1250 tty = tty_port_tty_get(&port->state->port);
1253 may_wake = device_may_wakeup(tty_dev);
1257 if (console_suspend_enabled && !may_wake) {
1258 struct cdns_uart *cdns_uart = port->private_data;
1260 clk_enable(cdns_uart->pclk);
1261 clk_enable(cdns_uart->uartclk);
1263 spin_lock_irqsave(&port->lock, flags);
1265 /* Set TX/RX Reset */
1266 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1267 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1268 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1269 while (cdns_uart_readl(CDNS_UART_CR_OFFSET) &
1270 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1273 /* restore rx timeout value */
1274 cdns_uart_writel(rx_timeout, CDNS_UART_RXTOUT_OFFSET);
1276 ctrl_reg = cdns_uart_readl(CDNS_UART_CR_OFFSET);
1277 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1278 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1279 cdns_uart_writel(ctrl_reg, CDNS_UART_CR_OFFSET);
1281 spin_unlock_irqrestore(&port->lock, flags);
1283 spin_lock_irqsave(&port->lock, flags);
1284 /* restore original rx trigger level */
1285 cdns_uart_writel(rx_trigger_level, CDNS_UART_RXWM_OFFSET);
1286 /* enable RX timeout interrupt */
1287 cdns_uart_writel(CDNS_UART_IXR_TOUT, CDNS_UART_IER_OFFSET);
1288 spin_unlock_irqrestore(&port->lock, flags);
1291 return uart_resume_port(&cdns_uart_uart_driver, port);
1293 #endif /* ! CONFIG_PM_SLEEP */
1295 static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1299 * cdns_uart_probe - Platform driver probe
1300 * @pdev: Pointer to the platform device structure
1302 * Return: 0 on success, negative errno otherwise
1304 static int cdns_uart_probe(struct platform_device *pdev)
1307 struct uart_port *port;
1308 struct resource *res, *res2;
1309 struct cdns_uart *cdns_uart_data;
1311 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1313 if (!cdns_uart_data)
1316 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1317 if (IS_ERR(cdns_uart_data->pclk)) {
1318 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1319 if (!IS_ERR(cdns_uart_data->pclk))
1320 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1322 if (IS_ERR(cdns_uart_data->pclk)) {
1323 dev_err(&pdev->dev, "pclk clock not found.\n");
1324 return PTR_ERR(cdns_uart_data->pclk);
1327 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1328 if (IS_ERR(cdns_uart_data->uartclk)) {
1329 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1330 if (!IS_ERR(cdns_uart_data->uartclk))
1331 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1333 if (IS_ERR(cdns_uart_data->uartclk)) {
1334 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1335 return PTR_ERR(cdns_uart_data->uartclk);
1338 rc = clk_prepare_enable(cdns_uart_data->pclk);
1340 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1343 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1345 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1346 goto err_out_clk_dis_pclk;
1349 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1352 goto err_out_clk_disable;
1355 res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1358 goto err_out_clk_disable;
1361 #ifdef CONFIG_COMMON_CLK
1362 cdns_uart_data->clk_rate_change_nb.notifier_call =
1363 cdns_uart_clk_notifier_cb;
1364 if (clk_notifier_register(cdns_uart_data->uartclk,
1365 &cdns_uart_data->clk_rate_change_nb))
1366 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1368 /* Look for a serialN alias */
1369 id = of_alias_get_id(pdev->dev.of_node, "serial");
1373 /* Initialize the port structure */
1374 port = cdns_uart_get_port(id);
1377 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1379 goto err_out_notif_unreg;
1381 /* Register the port.
1382 * This function also registers this device with the tty layer
1383 * and triggers invocation of the config_port() entry point.
1385 port->mapbase = res->start;
1386 port->irq = res2->start;
1387 port->dev = &pdev->dev;
1388 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1389 port->private_data = cdns_uart_data;
1390 cdns_uart_data->port = port;
1391 platform_set_drvdata(pdev, port);
1392 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1395 "uart_add_one_port() failed; err=%i\n", rc);
1396 goto err_out_notif_unreg;
1401 err_out_notif_unreg:
1402 #ifdef CONFIG_COMMON_CLK
1403 clk_notifier_unregister(cdns_uart_data->uartclk,
1404 &cdns_uart_data->clk_rate_change_nb);
1406 err_out_clk_disable:
1407 clk_disable_unprepare(cdns_uart_data->uartclk);
1408 err_out_clk_dis_pclk:
1409 clk_disable_unprepare(cdns_uart_data->pclk);
1415 * cdns_uart_remove - called when the platform driver is unregistered
1416 * @pdev: Pointer to the platform device structure
1418 * Return: 0 on success, negative errno otherwise
1420 static int cdns_uart_remove(struct platform_device *pdev)
1422 struct uart_port *port = platform_get_drvdata(pdev);
1423 struct cdns_uart *cdns_uart_data = port->private_data;
1426 /* Remove the cdns_uart port from the serial core */
1427 #ifdef CONFIG_COMMON_CLK
1428 clk_notifier_unregister(cdns_uart_data->uartclk,
1429 &cdns_uart_data->clk_rate_change_nb);
1431 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1433 clk_disable_unprepare(cdns_uart_data->uartclk);
1434 clk_disable_unprepare(cdns_uart_data->pclk);
1438 /* Match table for of_platform binding */
1439 static struct of_device_id cdns_uart_of_match[] = {
1440 { .compatible = "xlnx,xuartps", },
1441 { .compatible = "cdns,uart-r1p8", },
1444 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1446 static struct platform_driver cdns_uart_platform_driver = {
1447 .probe = cdns_uart_probe,
1448 .remove = cdns_uart_remove,
1450 .name = CDNS_UART_NAME,
1451 .of_match_table = cdns_uart_of_match,
1452 .pm = &cdns_uart_dev_pm_ops,
1456 static int __init cdns_uart_init(void)
1460 /* Register the cdns_uart driver with the serial core */
1461 retval = uart_register_driver(&cdns_uart_uart_driver);
1465 /* Register the platform driver */
1466 retval = platform_driver_register(&cdns_uart_platform_driver);
1468 uart_unregister_driver(&cdns_uart_uart_driver);
1473 static void __exit cdns_uart_exit(void)
1475 /* Unregister the platform driver */
1476 platform_driver_unregister(&cdns_uart_platform_driver);
1478 /* Unregister the cdns_uart driver */
1479 uart_unregister_driver(&cdns_uart_uart_driver);
1482 module_init(cdns_uart_init);
1483 module_exit(cdns_uart_exit);
1485 MODULE_DESCRIPTION("Driver for Cadence UART");
1486 MODULE_AUTHOR("Xilinx Inc.");
1487 MODULE_LICENSE("GPL");