2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
112 struct scatterlist sg_rx[2];
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
122 struct notifier_block freq_transition;
125 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
127 static struct sci_port sci_ports[SCI_NPORTS];
128 static struct uart_driver sci_uart_driver;
130 static inline struct sci_port *
131 to_sci_port(struct uart_port *uart)
133 return container_of(uart, struct sci_port, port);
136 struct plat_sci_reg {
140 /* Helper for invalidating specific entries of an inherited map. */
141 #define sci_reg_invalid { .offset = 0, .size = 0 }
143 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
144 [SCIx_PROBE_REGTYPE] = {
145 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
149 * Common SCI definitions, dependent on the port's regshift
152 [SCIx_SCI_REGTYPE] = {
153 [SCSMR] = { 0x00, 8 },
154 [SCBRR] = { 0x01, 8 },
155 [SCSCR] = { 0x02, 8 },
156 [SCxTDR] = { 0x03, 8 },
157 [SCxSR] = { 0x04, 8 },
158 [SCxRDR] = { 0x05, 8 },
159 [SCFCR] = sci_reg_invalid,
160 [SCFDR] = sci_reg_invalid,
161 [SCTFDR] = sci_reg_invalid,
162 [SCRFDR] = sci_reg_invalid,
163 [SCSPTR] = sci_reg_invalid,
164 [SCLSR] = sci_reg_invalid,
165 [HSSRR] = sci_reg_invalid,
166 [SCPCR] = sci_reg_invalid,
167 [SCPDR] = sci_reg_invalid,
171 * Common definitions for legacy IrDA ports, dependent on
174 [SCIx_IRDA_REGTYPE] = {
175 [SCSMR] = { 0x00, 8 },
176 [SCBRR] = { 0x01, 8 },
177 [SCSCR] = { 0x02, 8 },
178 [SCxTDR] = { 0x03, 8 },
179 [SCxSR] = { 0x04, 8 },
180 [SCxRDR] = { 0x05, 8 },
181 [SCFCR] = { 0x06, 8 },
182 [SCFDR] = { 0x07, 16 },
183 [SCTFDR] = sci_reg_invalid,
184 [SCRFDR] = sci_reg_invalid,
185 [SCSPTR] = sci_reg_invalid,
186 [SCLSR] = sci_reg_invalid,
187 [HSSRR] = sci_reg_invalid,
188 [SCPCR] = sci_reg_invalid,
189 [SCPDR] = sci_reg_invalid,
193 * Common SCIFA definitions.
195 [SCIx_SCIFA_REGTYPE] = {
196 [SCSMR] = { 0x00, 16 },
197 [SCBRR] = { 0x04, 8 },
198 [SCSCR] = { 0x08, 16 },
199 [SCxTDR] = { 0x20, 8 },
200 [SCxSR] = { 0x14, 16 },
201 [SCxRDR] = { 0x24, 8 },
202 [SCFCR] = { 0x18, 16 },
203 [SCFDR] = { 0x1c, 16 },
204 [SCTFDR] = sci_reg_invalid,
205 [SCRFDR] = sci_reg_invalid,
206 [SCSPTR] = sci_reg_invalid,
207 [SCLSR] = sci_reg_invalid,
208 [HSSRR] = sci_reg_invalid,
209 [SCPCR] = { 0x30, 16 },
210 [SCPDR] = { 0x34, 16 },
214 * Common SCIFB definitions.
216 [SCIx_SCIFB_REGTYPE] = {
217 [SCSMR] = { 0x00, 16 },
218 [SCBRR] = { 0x04, 8 },
219 [SCSCR] = { 0x08, 16 },
220 [SCxTDR] = { 0x40, 8 },
221 [SCxSR] = { 0x14, 16 },
222 [SCxRDR] = { 0x60, 8 },
223 [SCFCR] = { 0x18, 16 },
224 [SCFDR] = sci_reg_invalid,
225 [SCTFDR] = { 0x38, 16 },
226 [SCRFDR] = { 0x3c, 16 },
227 [SCSPTR] = sci_reg_invalid,
228 [SCLSR] = sci_reg_invalid,
229 [HSSRR] = sci_reg_invalid,
230 [SCPCR] = { 0x30, 16 },
231 [SCPDR] = { 0x34, 16 },
235 * Common SH-2(A) SCIF definitions for ports with FIFO data
238 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
239 [SCSMR] = { 0x00, 16 },
240 [SCBRR] = { 0x04, 8 },
241 [SCSCR] = { 0x08, 16 },
242 [SCxTDR] = { 0x0c, 8 },
243 [SCxSR] = { 0x10, 16 },
244 [SCxRDR] = { 0x14, 8 },
245 [SCFCR] = { 0x18, 16 },
246 [SCFDR] = { 0x1c, 16 },
247 [SCTFDR] = sci_reg_invalid,
248 [SCRFDR] = sci_reg_invalid,
249 [SCSPTR] = { 0x20, 16 },
250 [SCLSR] = { 0x24, 16 },
251 [HSSRR] = sci_reg_invalid,
252 [SCPCR] = sci_reg_invalid,
253 [SCPDR] = sci_reg_invalid,
257 * Common SH-3 SCIF definitions.
259 [SCIx_SH3_SCIF_REGTYPE] = {
260 [SCSMR] = { 0x00, 8 },
261 [SCBRR] = { 0x02, 8 },
262 [SCSCR] = { 0x04, 8 },
263 [SCxTDR] = { 0x06, 8 },
264 [SCxSR] = { 0x08, 16 },
265 [SCxRDR] = { 0x0a, 8 },
266 [SCFCR] = { 0x0c, 8 },
267 [SCFDR] = { 0x0e, 16 },
268 [SCTFDR] = sci_reg_invalid,
269 [SCRFDR] = sci_reg_invalid,
270 [SCSPTR] = sci_reg_invalid,
271 [SCLSR] = sci_reg_invalid,
272 [HSSRR] = sci_reg_invalid,
273 [SCPCR] = sci_reg_invalid,
274 [SCPDR] = sci_reg_invalid,
278 * Common SH-4(A) SCIF(B) definitions.
280 [SCIx_SH4_SCIF_REGTYPE] = {
281 [SCSMR] = { 0x00, 16 },
282 [SCBRR] = { 0x04, 8 },
283 [SCSCR] = { 0x08, 16 },
284 [SCxTDR] = { 0x0c, 8 },
285 [SCxSR] = { 0x10, 16 },
286 [SCxRDR] = { 0x14, 8 },
287 [SCFCR] = { 0x18, 16 },
288 [SCFDR] = { 0x1c, 16 },
289 [SCTFDR] = sci_reg_invalid,
290 [SCRFDR] = sci_reg_invalid,
291 [SCSPTR] = { 0x20, 16 },
292 [SCLSR] = { 0x24, 16 },
293 [HSSRR] = sci_reg_invalid,
294 [SCPCR] = sci_reg_invalid,
295 [SCPDR] = sci_reg_invalid,
299 * Common HSCIF definitions.
301 [SCIx_HSCIF_REGTYPE] = {
302 [SCSMR] = { 0x00, 16 },
303 [SCBRR] = { 0x04, 8 },
304 [SCSCR] = { 0x08, 16 },
305 [SCxTDR] = { 0x0c, 8 },
306 [SCxSR] = { 0x10, 16 },
307 [SCxRDR] = { 0x14, 8 },
308 [SCFCR] = { 0x18, 16 },
309 [SCFDR] = { 0x1c, 16 },
310 [SCTFDR] = sci_reg_invalid,
311 [SCRFDR] = sci_reg_invalid,
312 [SCSPTR] = { 0x20, 16 },
313 [SCLSR] = { 0x24, 16 },
314 [HSSRR] = { 0x40, 16 },
315 [SCPCR] = sci_reg_invalid,
316 [SCPDR] = sci_reg_invalid,
320 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
323 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
324 [SCSMR] = { 0x00, 16 },
325 [SCBRR] = { 0x04, 8 },
326 [SCSCR] = { 0x08, 16 },
327 [SCxTDR] = { 0x0c, 8 },
328 [SCxSR] = { 0x10, 16 },
329 [SCxRDR] = { 0x14, 8 },
330 [SCFCR] = { 0x18, 16 },
331 [SCFDR] = { 0x1c, 16 },
332 [SCTFDR] = sci_reg_invalid,
333 [SCRFDR] = sci_reg_invalid,
334 [SCSPTR] = sci_reg_invalid,
335 [SCLSR] = { 0x24, 16 },
336 [HSSRR] = sci_reg_invalid,
337 [SCPCR] = sci_reg_invalid,
338 [SCPDR] = sci_reg_invalid,
342 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
345 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
346 [SCSMR] = { 0x00, 16 },
347 [SCBRR] = { 0x04, 8 },
348 [SCSCR] = { 0x08, 16 },
349 [SCxTDR] = { 0x0c, 8 },
350 [SCxSR] = { 0x10, 16 },
351 [SCxRDR] = { 0x14, 8 },
352 [SCFCR] = { 0x18, 16 },
353 [SCFDR] = { 0x1c, 16 },
354 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
355 [SCRFDR] = { 0x20, 16 },
356 [SCSPTR] = { 0x24, 16 },
357 [SCLSR] = { 0x28, 16 },
358 [HSSRR] = sci_reg_invalid,
359 [SCPCR] = sci_reg_invalid,
360 [SCPDR] = sci_reg_invalid,
364 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
367 [SCIx_SH7705_SCIF_REGTYPE] = {
368 [SCSMR] = { 0x00, 16 },
369 [SCBRR] = { 0x04, 8 },
370 [SCSCR] = { 0x08, 16 },
371 [SCxTDR] = { 0x20, 8 },
372 [SCxSR] = { 0x14, 16 },
373 [SCxRDR] = { 0x24, 8 },
374 [SCFCR] = { 0x18, 16 },
375 [SCFDR] = { 0x1c, 16 },
376 [SCTFDR] = sci_reg_invalid,
377 [SCRFDR] = sci_reg_invalid,
378 [SCSPTR] = sci_reg_invalid,
379 [SCLSR] = sci_reg_invalid,
380 [HSSRR] = sci_reg_invalid,
381 [SCPCR] = sci_reg_invalid,
382 [SCPDR] = sci_reg_invalid,
386 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
389 * The "offset" here is rather misleading, in that it refers to an enum
390 * value relative to the port mapping rather than the fixed offset
391 * itself, which needs to be manually retrieved from the platform's
392 * register map for the given port.
394 static unsigned int sci_serial_in(struct uart_port *p, int offset)
396 const struct plat_sci_reg *reg = sci_getreg(p, offset);
399 return ioread8(p->membase + (reg->offset << p->regshift));
400 else if (reg->size == 16)
401 return ioread16(p->membase + (reg->offset << p->regshift));
403 WARN(1, "Invalid register access\n");
408 static void sci_serial_out(struct uart_port *p, int offset, int value)
410 const struct plat_sci_reg *reg = sci_getreg(p, offset);
413 iowrite8(value, p->membase + (reg->offset << p->regshift));
414 else if (reg->size == 16)
415 iowrite16(value, p->membase + (reg->offset << p->regshift));
417 WARN(1, "Invalid register access\n");
420 static int sci_probe_regmap(struct plat_sci_port *cfg)
424 cfg->regtype = SCIx_SCI_REGTYPE;
427 cfg->regtype = SCIx_IRDA_REGTYPE;
430 cfg->regtype = SCIx_SCIFA_REGTYPE;
433 cfg->regtype = SCIx_SCIFB_REGTYPE;
437 * The SH-4 is a bit of a misnomer here, although that's
438 * where this particular port layout originated. This
439 * configuration (or some slight variation thereof)
440 * remains the dominant model for all SCIFs.
442 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
445 cfg->regtype = SCIx_HSCIF_REGTYPE;
448 pr_err("Can't probe register map for given port\n");
455 static void sci_port_enable(struct sci_port *sci_port)
457 if (!sci_port->port.dev)
460 pm_runtime_get_sync(sci_port->port.dev);
462 clk_prepare_enable(sci_port->iclk);
463 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
464 clk_prepare_enable(sci_port->fclk);
467 static void sci_port_disable(struct sci_port *sci_port)
469 if (!sci_port->port.dev)
472 /* Cancel the break timer to ensure that the timer handler will not try
473 * to access the hardware with clocks and power disabled. Reset the
474 * break flag to make the break debouncing state machine ready for the
477 del_timer_sync(&sci_port->break_timer);
478 sci_port->break_flag = 0;
480 clk_disable_unprepare(sci_port->fclk);
481 clk_disable_unprepare(sci_port->iclk);
483 pm_runtime_put_sync(sci_port->port.dev);
486 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
489 * Not all ports (such as SCIFA) will support REIE. Rather than
490 * special-casing the port type, we check the port initialization
491 * IRQ enable mask to see whether the IRQ is desired at all. If
492 * it's unset, it's logically inferred that there's no point in
495 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
498 static void sci_start_tx(struct uart_port *port)
500 struct sci_port *s = to_sci_port(port);
503 #ifdef CONFIG_SERIAL_SH_SCI_DMA
504 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
505 u16 new, scr = serial_port_in(port, SCSCR);
507 new = scr | SCSCR_TDRQE;
509 new = scr & ~SCSCR_TDRQE;
511 serial_port_out(port, SCSCR, new);
514 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
515 dma_submit_error(s->cookie_tx)) {
517 schedule_work(&s->work_tx);
521 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
522 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
523 ctrl = serial_port_in(port, SCSCR);
524 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
528 static void sci_stop_tx(struct uart_port *port)
532 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
533 ctrl = serial_port_in(port, SCSCR);
535 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
536 ctrl &= ~SCSCR_TDRQE;
540 serial_port_out(port, SCSCR, ctrl);
543 static void sci_start_rx(struct uart_port *port)
547 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
549 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
550 ctrl &= ~SCSCR_RDRQE;
552 serial_port_out(port, SCSCR, ctrl);
555 static void sci_stop_rx(struct uart_port *port)
559 ctrl = serial_port_in(port, SCSCR);
561 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
562 ctrl &= ~SCSCR_RDRQE;
564 ctrl &= ~port_rx_irq_mask(port);
566 serial_port_out(port, SCSCR, ctrl);
569 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
571 if (port->type == PORT_SCI) {
572 /* Just store the mask */
573 serial_port_out(port, SCxSR, mask);
574 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
575 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
576 /* Only clear the status bits we want to clear */
577 serial_port_out(port, SCxSR,
578 serial_port_in(port, SCxSR) & mask);
580 /* Store the mask, clear parity/framing errors */
581 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
585 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
587 #ifdef CONFIG_CONSOLE_POLL
588 static int sci_poll_get_char(struct uart_port *port)
590 unsigned short status;
594 status = serial_port_in(port, SCxSR);
595 if (status & SCxSR_ERRORS(port)) {
596 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
602 if (!(status & SCxSR_RDxF(port)))
605 c = serial_port_in(port, SCxRDR);
608 serial_port_in(port, SCxSR);
609 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
615 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
617 unsigned short status;
620 status = serial_port_in(port, SCxSR);
621 } while (!(status & SCxSR_TDxE(port)));
623 serial_port_out(port, SCxTDR, c);
624 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
626 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
628 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
630 struct sci_port *s = to_sci_port(port);
631 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
634 * Use port-specific handler if provided.
636 if (s->cfg->ops && s->cfg->ops->init_pins) {
637 s->cfg->ops->init_pins(port, cflag);
642 * For the generic path SCSPTR is necessary. Bail out if that's
648 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
649 ((!(cflag & CRTSCTS)))) {
650 unsigned short status;
652 status = serial_port_in(port, SCSPTR);
653 status &= ~SCSPTR_CTSIO;
654 status |= SCSPTR_RTSIO;
655 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
659 static int sci_txfill(struct uart_port *port)
661 const struct plat_sci_reg *reg;
663 reg = sci_getreg(port, SCTFDR);
665 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
667 reg = sci_getreg(port, SCFDR);
669 return serial_port_in(port, SCFDR) >> 8;
671 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
674 static int sci_txroom(struct uart_port *port)
676 return port->fifosize - sci_txfill(port);
679 static int sci_rxfill(struct uart_port *port)
681 const struct plat_sci_reg *reg;
683 reg = sci_getreg(port, SCRFDR);
685 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
687 reg = sci_getreg(port, SCFDR);
689 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
691 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
695 * SCI helper for checking the state of the muxed port/RXD pins.
697 static inline int sci_rxd_in(struct uart_port *port)
699 struct sci_port *s = to_sci_port(port);
701 if (s->cfg->port_reg <= 0)
704 /* Cast for ARM damage */
705 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
708 /* ********************************************************************** *
709 * the interrupt related routines *
710 * ********************************************************************** */
712 static void sci_transmit_chars(struct uart_port *port)
714 struct circ_buf *xmit = &port->state->xmit;
715 unsigned int stopped = uart_tx_stopped(port);
716 unsigned short status;
720 status = serial_port_in(port, SCxSR);
721 if (!(status & SCxSR_TDxE(port))) {
722 ctrl = serial_port_in(port, SCSCR);
723 if (uart_circ_empty(xmit))
727 serial_port_out(port, SCSCR, ctrl);
731 count = sci_txroom(port);
739 } else if (!uart_circ_empty(xmit) && !stopped) {
740 c = xmit->buf[xmit->tail];
741 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
746 serial_port_out(port, SCxTDR, c);
749 } while (--count > 0);
751 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
753 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
754 uart_write_wakeup(port);
755 if (uart_circ_empty(xmit)) {
758 ctrl = serial_port_in(port, SCSCR);
760 if (port->type != PORT_SCI) {
761 serial_port_in(port, SCxSR); /* Dummy read */
762 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
766 serial_port_out(port, SCSCR, ctrl);
770 /* On SH3, SCIF may read end-of-break as a space->mark char */
771 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
773 static void sci_receive_chars(struct uart_port *port)
775 struct sci_port *sci_port = to_sci_port(port);
776 struct tty_port *tport = &port->state->port;
777 int i, count, copied = 0;
778 unsigned short status;
781 status = serial_port_in(port, SCxSR);
782 if (!(status & SCxSR_RDxF(port)))
786 /* Don't copy more bytes than there is room for in the buffer */
787 count = tty_buffer_request_room(tport, sci_rxfill(port));
789 /* If for any reason we can't copy more data, we're done! */
793 if (port->type == PORT_SCI) {
794 char c = serial_port_in(port, SCxRDR);
795 if (uart_handle_sysrq_char(port, c) ||
796 sci_port->break_flag)
799 tty_insert_flip_char(tport, c, TTY_NORMAL);
801 for (i = 0; i < count; i++) {
802 char c = serial_port_in(port, SCxRDR);
804 status = serial_port_in(port, SCxSR);
805 #if defined(CONFIG_CPU_SH3)
806 /* Skip "chars" during break */
807 if (sci_port->break_flag) {
809 (status & SCxSR_FER(port))) {
814 /* Nonzero => end-of-break */
815 dev_dbg(port->dev, "debounce<%02x>\n", c);
816 sci_port->break_flag = 0;
823 #endif /* CONFIG_CPU_SH3 */
824 if (uart_handle_sysrq_char(port, c)) {
829 /* Store data and status */
830 if (status & SCxSR_FER(port)) {
832 port->icount.frame++;
833 dev_notice(port->dev, "frame error\n");
834 } else if (status & SCxSR_PER(port)) {
836 port->icount.parity++;
837 dev_notice(port->dev, "parity error\n");
841 tty_insert_flip_char(tport, c, flag);
845 serial_port_in(port, SCxSR); /* dummy read */
846 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
849 port->icount.rx += count;
853 /* Tell the rest of the system the news. New characters! */
854 tty_flip_buffer_push(tport);
856 serial_port_in(port, SCxSR); /* dummy read */
857 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
861 #define SCI_BREAK_JIFFIES (HZ/20)
864 * The sci generates interrupts during the break,
865 * 1 per millisecond or so during the break period, for 9600 baud.
866 * So dont bother disabling interrupts.
867 * But dont want more than 1 break event.
868 * Use a kernel timer to periodically poll the rx line until
869 * the break is finished.
871 static inline void sci_schedule_break_timer(struct sci_port *port)
873 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
876 /* Ensure that two consecutive samples find the break over. */
877 static void sci_break_timer(unsigned long data)
879 struct sci_port *port = (struct sci_port *)data;
881 if (sci_rxd_in(&port->port) == 0) {
882 port->break_flag = 1;
883 sci_schedule_break_timer(port);
884 } else if (port->break_flag == 1) {
886 port->break_flag = 2;
887 sci_schedule_break_timer(port);
889 port->break_flag = 0;
892 static int sci_handle_errors(struct uart_port *port)
895 unsigned short status = serial_port_in(port, SCxSR);
896 struct tty_port *tport = &port->state->port;
897 struct sci_port *s = to_sci_port(port);
899 /* Handle overruns */
900 if (status & s->overrun_mask) {
901 port->icount.overrun++;
904 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
907 dev_notice(port->dev, "overrun error\n");
910 if (status & SCxSR_FER(port)) {
911 if (sci_rxd_in(port) == 0) {
912 /* Notify of BREAK */
913 struct sci_port *sci_port = to_sci_port(port);
915 if (!sci_port->break_flag) {
918 sci_port->break_flag = 1;
919 sci_schedule_break_timer(sci_port);
921 /* Do sysrq handling. */
922 if (uart_handle_break(port))
925 dev_dbg(port->dev, "BREAK detected\n");
927 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
933 port->icount.frame++;
935 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
938 dev_notice(port->dev, "frame error\n");
942 if (status & SCxSR_PER(port)) {
944 port->icount.parity++;
946 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
949 dev_notice(port->dev, "parity error\n");
953 tty_flip_buffer_push(tport);
958 static int sci_handle_fifo_overrun(struct uart_port *port)
960 struct tty_port *tport = &port->state->port;
961 struct sci_port *s = to_sci_port(port);
962 const struct plat_sci_reg *reg;
966 reg = sci_getreg(port, s->overrun_reg);
970 status = serial_port_in(port, s->overrun_reg);
971 if (status & s->overrun_mask) {
972 status &= ~s->overrun_mask;
973 serial_port_out(port, s->overrun_reg, status);
975 port->icount.overrun++;
977 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
978 tty_flip_buffer_push(tport);
980 dev_dbg(port->dev, "overrun error\n");
987 static int sci_handle_breaks(struct uart_port *port)
990 unsigned short status = serial_port_in(port, SCxSR);
991 struct tty_port *tport = &port->state->port;
992 struct sci_port *s = to_sci_port(port);
994 if (uart_handle_break(port))
997 if (!s->break_flag && status & SCxSR_BRK(port)) {
998 #if defined(CONFIG_CPU_SH3)
1005 /* Notify of BREAK */
1006 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1009 dev_dbg(port->dev, "BREAK detected\n");
1013 tty_flip_buffer_push(tport);
1015 copied += sci_handle_fifo_overrun(port);
1020 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1021 static void sci_dma_tx_complete(void *arg)
1023 struct sci_port *s = arg;
1024 struct uart_port *port = &s->port;
1025 struct circ_buf *xmit = &port->state->xmit;
1026 unsigned long flags;
1028 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1030 spin_lock_irqsave(&port->lock, flags);
1032 xmit->tail += s->tx_dma_len;
1033 xmit->tail &= UART_XMIT_SIZE - 1;
1035 port->icount.tx += s->tx_dma_len;
1037 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1038 uart_write_wakeup(port);
1040 if (!uart_circ_empty(xmit)) {
1042 schedule_work(&s->work_tx);
1044 s->cookie_tx = -EINVAL;
1045 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1046 u16 ctrl = serial_port_in(port, SCSCR);
1047 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1051 spin_unlock_irqrestore(&port->lock, flags);
1054 /* Locking: called with port lock held */
1055 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1057 struct uart_port *port = &s->port;
1058 struct tty_port *tport = &port->state->port;
1061 copied = tty_insert_flip_string(tport, buf, count);
1062 if (copied < count) {
1063 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1065 port->icount.buf_overrun++;
1068 port->icount.rx += copied;
1073 static int sci_dma_rx_find_active(struct sci_port *s)
1077 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1078 if (s->active_rx == s->cookie_rx[i])
1081 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1086 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1088 struct dma_chan *chan = s->chan_rx;
1089 struct uart_port *port = &s->port;
1090 unsigned long flags;
1092 spin_lock_irqsave(&port->lock, flags);
1094 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1095 spin_unlock_irqrestore(&port->lock, flags);
1096 dmaengine_terminate_all(chan);
1097 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1098 sg_dma_address(&s->sg_rx[0]));
1099 dma_release_channel(chan);
1104 static void sci_dma_rx_complete(void *arg)
1106 struct sci_port *s = arg;
1107 struct dma_chan *chan = s->chan_rx;
1108 struct uart_port *port = &s->port;
1109 struct dma_async_tx_descriptor *desc;
1110 unsigned long flags;
1111 int active, count = 0;
1113 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1116 spin_lock_irqsave(&port->lock, flags);
1118 active = sci_dma_rx_find_active(s);
1120 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1122 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1125 tty_flip_buffer_push(&port->state->port);
1127 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1129 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1133 desc->callback = sci_dma_rx_complete;
1134 desc->callback_param = s;
1135 s->cookie_rx[active] = dmaengine_submit(desc);
1136 if (dma_submit_error(s->cookie_rx[active]))
1139 s->active_rx = s->cookie_rx[!active];
1141 dma_async_issue_pending(chan);
1143 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1144 __func__, s->cookie_rx[active], active, s->active_rx);
1145 spin_unlock_irqrestore(&port->lock, flags);
1149 spin_unlock_irqrestore(&port->lock, flags);
1150 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1151 sci_rx_dma_release(s, true);
1154 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1156 struct dma_chan *chan = s->chan_tx;
1157 struct uart_port *port = &s->port;
1158 unsigned long flags;
1160 spin_lock_irqsave(&port->lock, flags);
1162 s->cookie_tx = -EINVAL;
1163 spin_unlock_irqrestore(&port->lock, flags);
1164 dmaengine_terminate_all(chan);
1165 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1167 dma_release_channel(chan);
1172 static void sci_submit_rx(struct sci_port *s)
1174 struct dma_chan *chan = s->chan_rx;
1177 for (i = 0; i < 2; i++) {
1178 struct scatterlist *sg = &s->sg_rx[i];
1179 struct dma_async_tx_descriptor *desc;
1181 desc = dmaengine_prep_slave_sg(chan,
1182 sg, 1, DMA_DEV_TO_MEM,
1183 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1187 desc->callback = sci_dma_rx_complete;
1188 desc->callback_param = s;
1189 s->cookie_rx[i] = dmaengine_submit(desc);
1190 if (dma_submit_error(s->cookie_rx[i]))
1193 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1194 s->cookie_rx[i], i);
1197 s->active_rx = s->cookie_rx[0];
1199 dma_async_issue_pending(chan);
1204 dmaengine_terminate_all(chan);
1205 for (i = 0; i < 2; i++)
1206 s->cookie_rx[i] = -EINVAL;
1207 s->active_rx = -EINVAL;
1208 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1209 sci_rx_dma_release(s, true);
1212 static void work_fn_tx(struct work_struct *work)
1214 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1215 struct dma_async_tx_descriptor *desc;
1216 struct dma_chan *chan = s->chan_tx;
1217 struct uart_port *port = &s->port;
1218 struct circ_buf *xmit = &port->state->xmit;
1223 * Port xmit buffer is already mapped, and it is one page... Just adjust
1224 * offsets and lengths. Since it is a circular buffer, we have to
1225 * transmit till the end, and then the rest. Take the port lock to get a
1226 * consistent xmit buffer state.
1228 spin_lock_irq(&port->lock);
1229 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1230 s->tx_dma_len = min_t(unsigned int,
1231 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1232 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1233 spin_unlock_irq(&port->lock);
1235 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1237 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1239 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1241 sci_tx_dma_release(s, true);
1245 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1248 spin_lock_irq(&port->lock);
1249 desc->callback = sci_dma_tx_complete;
1250 desc->callback_param = s;
1251 spin_unlock_irq(&port->lock);
1252 s->cookie_tx = dmaengine_submit(desc);
1253 if (dma_submit_error(s->cookie_tx)) {
1254 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1256 sci_tx_dma_release(s, true);
1260 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1261 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1263 dma_async_issue_pending(chan);
1266 static bool filter(struct dma_chan *chan, void *slave)
1268 struct sh_dmae_slave *param = slave;
1270 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1271 __func__, param->shdma_slave.slave_id);
1273 chan->private = ¶m->shdma_slave;
1277 static void rx_timer_fn(unsigned long arg)
1279 struct sci_port *s = (struct sci_port *)arg;
1280 struct dma_chan *chan = s->chan_rx;
1281 struct uart_port *port = &s->port;
1282 struct dma_tx_state state;
1283 enum dma_status status;
1284 unsigned long flags;
1289 spin_lock_irqsave(&port->lock, flags);
1291 dev_dbg(port->dev, "DMA Rx timed out\n");
1293 active = sci_dma_rx_find_active(s);
1295 spin_unlock_irqrestore(&port->lock, flags);
1299 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1300 if (status == DMA_COMPLETE) {
1301 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1302 s->active_rx, active);
1303 spin_unlock_irqrestore(&port->lock, flags);
1305 /* Let packet complete handler take care of the packet */
1309 dmaengine_pause(chan);
1312 * sometimes DMA transfer doesn't stop even if it is stopped and
1313 * data keeps on coming until transaction is complete so check
1314 * for DMA_COMPLETE again
1315 * Let packet complete handler take care of the packet
1317 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1318 if (status == DMA_COMPLETE) {
1319 spin_unlock_irqrestore(&port->lock, flags);
1320 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1324 /* Handle incomplete DMA receive */
1325 dmaengine_terminate_all(s->chan_rx);
1326 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1327 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1331 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1333 tty_flip_buffer_push(&port->state->port);
1336 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1339 /* Direct new serial port interrupts back to CPU */
1340 scr = serial_port_in(port, SCSCR);
1341 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1342 scr &= ~SCSCR_RDRQE;
1343 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1345 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1347 spin_unlock_irqrestore(&port->lock, flags);
1350 static void sci_request_dma(struct uart_port *port)
1352 struct sci_port *s = to_sci_port(port);
1353 struct sh_dmae_slave *param;
1354 struct dma_chan *chan;
1355 dma_cap_mask_t mask;
1357 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1359 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1363 dma_cap_set(DMA_SLAVE, mask);
1365 param = &s->param_tx;
1367 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1368 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1370 s->cookie_tx = -EINVAL;
1371 chan = dma_request_channel(mask, filter, param);
1372 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1375 /* UART circular tx buffer is an aligned page. */
1376 s->tx_dma_addr = dma_map_single(chan->device->dev,
1377 port->state->xmit.buf,
1380 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1381 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1382 dma_release_channel(chan);
1385 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1386 __func__, UART_XMIT_SIZE,
1387 port->state->xmit.buf, &s->tx_dma_addr);
1390 INIT_WORK(&s->work_tx, work_fn_tx);
1393 param = &s->param_rx;
1395 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1396 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1398 chan = dma_request_channel(mask, filter, param);
1399 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1407 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1408 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1412 "Failed to allocate Rx dma buffer, using PIO\n");
1413 dma_release_channel(chan);
1418 for (i = 0; i < 2; i++) {
1419 struct scatterlist *sg = &s->sg_rx[i];
1421 sg_init_table(sg, 1);
1423 sg_dma_address(sg) = dma;
1424 sg->length = s->buf_len_rx;
1426 buf += s->buf_len_rx;
1427 dma += s->buf_len_rx;
1430 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1432 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1437 static void sci_free_dma(struct uart_port *port)
1439 struct sci_port *s = to_sci_port(port);
1442 sci_tx_dma_release(s, false);
1444 sci_rx_dma_release(s, false);
1447 static inline void sci_request_dma(struct uart_port *port)
1451 static inline void sci_free_dma(struct uart_port *port)
1456 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1458 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1459 struct uart_port *port = ptr;
1460 struct sci_port *s = to_sci_port(port);
1463 u16 scr = serial_port_in(port, SCSCR);
1464 u16 ssr = serial_port_in(port, SCxSR);
1466 /* Disable future Rx interrupts */
1467 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1468 disable_irq_nosync(irq);
1474 serial_port_out(port, SCSCR, scr);
1475 /* Clear current interrupt */
1476 serial_port_out(port, SCxSR,
1477 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1478 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
1479 jiffies, s->rx_timeout);
1480 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1486 /* I think sci_receive_chars has to be called irrespective
1487 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1490 sci_receive_chars(ptr);
1495 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1497 struct uart_port *port = ptr;
1498 unsigned long flags;
1500 spin_lock_irqsave(&port->lock, flags);
1501 sci_transmit_chars(port);
1502 spin_unlock_irqrestore(&port->lock, flags);
1507 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1509 struct uart_port *port = ptr;
1510 struct sci_port *s = to_sci_port(port);
1513 if (port->type == PORT_SCI) {
1514 if (sci_handle_errors(port)) {
1515 /* discard character in rx buffer */
1516 serial_port_in(port, SCxSR);
1517 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1520 sci_handle_fifo_overrun(port);
1522 sci_receive_chars(ptr);
1525 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1527 /* Kick the transmission */
1529 sci_tx_interrupt(irq, ptr);
1534 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1536 struct uart_port *port = ptr;
1539 sci_handle_breaks(port);
1540 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1545 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1547 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1548 struct uart_port *port = ptr;
1549 struct sci_port *s = to_sci_port(port);
1550 irqreturn_t ret = IRQ_NONE;
1552 ssr_status = serial_port_in(port, SCxSR);
1553 scr_status = serial_port_in(port, SCSCR);
1554 if (s->overrun_reg == SCxSR)
1555 orer_status = ssr_status;
1557 if (sci_getreg(port, s->overrun_reg)->size)
1558 orer_status = serial_port_in(port, s->overrun_reg);
1561 err_enabled = scr_status & port_rx_irq_mask(port);
1564 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1566 ret = sci_tx_interrupt(irq, ptr);
1569 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1572 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1573 (scr_status & SCSCR_RIE))
1574 ret = sci_rx_interrupt(irq, ptr);
1576 /* Error Interrupt */
1577 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1578 ret = sci_er_interrupt(irq, ptr);
1580 /* Break Interrupt */
1581 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1582 ret = sci_br_interrupt(irq, ptr);
1584 /* Overrun Interrupt */
1585 if (orer_status & s->overrun_mask) {
1586 sci_handle_fifo_overrun(port);
1594 * Here we define a transition notifier so that we can update all of our
1595 * ports' baud rate when the peripheral clock changes.
1597 static int sci_notifier(struct notifier_block *self,
1598 unsigned long phase, void *p)
1600 struct sci_port *sci_port;
1601 unsigned long flags;
1603 sci_port = container_of(self, struct sci_port, freq_transition);
1605 if (phase == CPUFREQ_POSTCHANGE) {
1606 struct uart_port *port = &sci_port->port;
1608 spin_lock_irqsave(&port->lock, flags);
1609 port->uartclk = clk_get_rate(sci_port->iclk);
1610 spin_unlock_irqrestore(&port->lock, flags);
1616 static const struct sci_irq_desc {
1618 irq_handler_t handler;
1619 } sci_irq_desc[] = {
1621 * Split out handlers, the default case.
1625 .handler = sci_er_interrupt,
1630 .handler = sci_rx_interrupt,
1635 .handler = sci_tx_interrupt,
1640 .handler = sci_br_interrupt,
1644 * Special muxed handler.
1648 .handler = sci_mpxed_interrupt,
1652 static int sci_request_irq(struct sci_port *port)
1654 struct uart_port *up = &port->port;
1657 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1658 const struct sci_irq_desc *desc;
1661 if (SCIx_IRQ_IS_MUXED(port)) {
1665 irq = port->irqs[i];
1668 * Certain port types won't support all of the
1669 * available interrupt sources.
1671 if (unlikely(irq < 0))
1675 desc = sci_irq_desc + i;
1676 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1677 dev_name(up->dev), desc->desc);
1678 if (!port->irqstr[j])
1681 ret = request_irq(irq, desc->handler, up->irqflags,
1682 port->irqstr[j], port);
1683 if (unlikely(ret)) {
1684 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1693 free_irq(port->irqs[i], port);
1697 kfree(port->irqstr[j]);
1702 static void sci_free_irq(struct sci_port *port)
1707 * Intentionally in reverse order so we iterate over the muxed
1710 for (i = 0; i < SCIx_NR_IRQS; i++) {
1711 int irq = port->irqs[i];
1714 * Certain port types won't support all of the available
1715 * interrupt sources.
1717 if (unlikely(irq < 0))
1720 free_irq(port->irqs[i], port);
1721 kfree(port->irqstr[i]);
1723 if (SCIx_IRQ_IS_MUXED(port)) {
1724 /* If there's only one IRQ, we're done. */
1730 static unsigned int sci_tx_empty(struct uart_port *port)
1732 unsigned short status = serial_port_in(port, SCxSR);
1733 unsigned short in_tx_fifo = sci_txfill(port);
1735 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1739 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1740 * CTS/RTS is supported in hardware by at least one port and controlled
1741 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1742 * handled via the ->init_pins() op, which is a bit of a one-way street,
1743 * lacking any ability to defer pin control -- this will later be
1744 * converted over to the GPIO framework).
1746 * Other modes (such as loopback) are supported generically on certain
1747 * port types, but not others. For these it's sufficient to test for the
1748 * existence of the support register and simply ignore the port type.
1750 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1752 if (mctrl & TIOCM_LOOP) {
1753 const struct plat_sci_reg *reg;
1756 * Standard loopback mode for SCFCR ports.
1758 reg = sci_getreg(port, SCFCR);
1760 serial_port_out(port, SCFCR,
1761 serial_port_in(port, SCFCR) |
1766 static unsigned int sci_get_mctrl(struct uart_port *port)
1769 * CTS/RTS is handled in hardware when supported, while nothing
1770 * else is wired up. Keep it simple and simply assert DSR/CAR.
1772 return TIOCM_DSR | TIOCM_CAR;
1775 static void sci_break_ctl(struct uart_port *port, int break_state)
1777 struct sci_port *s = to_sci_port(port);
1778 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1779 unsigned short scscr, scsptr;
1781 /* check wheter the port has SCSPTR */
1784 * Not supported by hardware. Most parts couple break and rx
1785 * interrupts together, with break detection always enabled.
1790 scsptr = serial_port_in(port, SCSPTR);
1791 scscr = serial_port_in(port, SCSCR);
1793 if (break_state == -1) {
1794 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1797 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1801 serial_port_out(port, SCSPTR, scsptr);
1802 serial_port_out(port, SCSCR, scscr);
1805 static int sci_startup(struct uart_port *port)
1807 struct sci_port *s = to_sci_port(port);
1808 unsigned long flags;
1811 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1813 ret = sci_request_irq(s);
1814 if (unlikely(ret < 0))
1817 sci_request_dma(port);
1819 spin_lock_irqsave(&port->lock, flags);
1822 spin_unlock_irqrestore(&port->lock, flags);
1827 static void sci_shutdown(struct uart_port *port)
1829 struct sci_port *s = to_sci_port(port);
1830 unsigned long flags;
1832 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1834 spin_lock_irqsave(&port->lock, flags);
1837 spin_unlock_irqrestore(&port->lock, flags);
1839 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1841 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
1843 del_timer_sync(&s->rx_timer);
1851 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1854 if (s->sampling_rate)
1855 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1857 /* Warn, but use a safe default */
1860 return ((freq + 16 * bps) / (32 * bps) - 1);
1863 /* calculate frame length from SMR */
1864 static int sci_baud_calc_frame_len(unsigned int smr_val)
1868 if (smr_val & SCSMR_CHR)
1870 if (smr_val & SCSMR_PE)
1872 if (smr_val & SCSMR_STOP)
1879 /* calculate sample rate, BRR, and clock select for HSCIF */
1880 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1881 int *brr, unsigned int *srr,
1882 unsigned int *cks, int frame_len)
1884 int sr, c, br, err, recv_margin;
1885 int min_err = 1000; /* 100% */
1886 int recv_max_margin = 0;
1888 /* Find the combination of sample rate and clock select with the
1889 smallest deviation from the desired baud rate. */
1890 for (sr = 8; sr <= 32; sr++) {
1891 for (c = 0; c <= 3; c++) {
1892 /* integerized formulas from HSCIF documentation */
1893 br = DIV_ROUND_CLOSEST(freq, (sr *
1894 (1 << (2 * c + 1)) * bps)) - 1;
1895 br = clamp(br, 0, 255);
1896 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1897 (1 << (2 * c + 1)) / 1000)) -
1900 * M: Receive margin (%)
1901 * N: Ratio of bit rate to clock (N = sampling rate)
1902 * D: Clock duty (D = 0 to 1.0)
1903 * L: Frame length (L = 9 to 12)
1904 * F: Absolute value of clock frequency deviation
1906 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1907 * (|D - 0.5| / N * (1 + F))|
1908 * NOTE: Usually, treat D for 0.5, F is 0 by this
1911 recv_margin = abs((500 -
1912 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1913 if (abs(min_err) > abs(err)) {
1915 recv_max_margin = recv_margin;
1916 } else if ((min_err == err) &&
1917 (recv_margin > recv_max_margin))
1918 recv_max_margin = recv_margin;
1928 if (min_err == 1000) {
1937 static void sci_reset(struct uart_port *port)
1939 const struct plat_sci_reg *reg;
1940 unsigned int status;
1943 status = serial_port_in(port, SCxSR);
1944 } while (!(status & SCxSR_TEND(port)));
1946 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1948 reg = sci_getreg(port, SCFCR);
1950 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1953 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1954 struct ktermios *old)
1956 struct sci_port *s = to_sci_port(port);
1957 const struct plat_sci_reg *reg;
1958 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1960 unsigned int srr = 15;
1962 if ((termios->c_cflag & CSIZE) == CS7)
1963 smr_val |= SCSMR_CHR;
1964 if (termios->c_cflag & PARENB)
1965 smr_val |= SCSMR_PE;
1966 if (termios->c_cflag & PARODD)
1967 smr_val |= SCSMR_PE | SCSMR_ODD;
1968 if (termios->c_cflag & CSTOPB)
1969 smr_val |= SCSMR_STOP;
1972 * earlyprintk comes here early on with port->uartclk set to zero.
1973 * the clock framework is not up and running at this point so here
1974 * we assume that 115200 is the maximum baud rate. please note that
1975 * the baud rate is not programmed during earlyprintk - it is assumed
1976 * that the previous boot loader has enabled required clocks and
1977 * setup the baud rate generator hardware for us already.
1979 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1981 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1982 if (likely(baud && port->uartclk)) {
1983 if (s->cfg->type == PORT_HSCIF) {
1984 int frame_len = sci_baud_calc_frame_len(smr_val);
1985 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1988 t = sci_scbrr_calc(s, baud, port->uartclk);
1989 for (cks = 0; t >= 256 && cks <= 3; cks++)
1998 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
2000 uart_update_timeout(port, termios->c_cflag, baud);
2002 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
2003 __func__, smr_val, cks, t, s->cfg->scscr);
2006 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
2007 serial_port_out(port, SCBRR, t);
2008 reg = sci_getreg(port, HSSRR);
2010 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
2011 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
2013 serial_port_out(port, SCSMR, smr_val);
2015 sci_init_pins(port, termios->c_cflag);
2017 reg = sci_getreg(port, SCFCR);
2019 unsigned short ctrl = serial_port_in(port, SCFCR);
2021 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2022 if (termios->c_cflag & CRTSCTS)
2029 * As we've done a sci_reset() above, ensure we don't
2030 * interfere with the FIFOs while toggling MCE. As the
2031 * reset values could still be set, simply mask them out.
2033 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2035 serial_port_out(port, SCFCR, ctrl);
2038 serial_port_out(port, SCSCR, s->cfg->scscr);
2040 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2042 * Calculate delay for 2 DMA buffers (4 FIFO).
2043 * See serial_core.c::uart_update_timeout().
2044 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2045 * function calculates 1 jiffie for the data plus 5 jiffies for the
2046 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2047 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2048 * value obtained by this formula is too small. Therefore, if the value
2049 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2054 /* byte size and parity */
2055 switch (termios->c_cflag & CSIZE) {
2070 if (termios->c_cflag & CSTOPB)
2072 if (termios->c_cflag & PARENB)
2074 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2076 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2077 s->rx_timeout * 1000 / HZ, port->timeout);
2078 if (s->rx_timeout < msecs_to_jiffies(20))
2079 s->rx_timeout = msecs_to_jiffies(20);
2083 if ((termios->c_cflag & CREAD) != 0)
2086 sci_port_disable(s);
2089 static void sci_pm(struct uart_port *port, unsigned int state,
2090 unsigned int oldstate)
2092 struct sci_port *sci_port = to_sci_port(port);
2095 case UART_PM_STATE_OFF:
2096 sci_port_disable(sci_port);
2099 sci_port_enable(sci_port);
2104 static const char *sci_type(struct uart_port *port)
2106 switch (port->type) {
2124 static int sci_remap_port(struct uart_port *port)
2126 struct sci_port *sport = to_sci_port(port);
2129 * Nothing to do if there's already an established membase.
2134 if (port->flags & UPF_IOREMAP) {
2135 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2136 if (unlikely(!port->membase)) {
2137 dev_err(port->dev, "can't remap port#%d\n", port->line);
2142 * For the simple (and majority of) cases where we don't
2143 * need to do any remapping, just cast the cookie
2146 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2152 static void sci_release_port(struct uart_port *port)
2154 struct sci_port *sport = to_sci_port(port);
2156 if (port->flags & UPF_IOREMAP) {
2157 iounmap(port->membase);
2158 port->membase = NULL;
2161 release_mem_region(port->mapbase, sport->reg_size);
2164 static int sci_request_port(struct uart_port *port)
2166 struct resource *res;
2167 struct sci_port *sport = to_sci_port(port);
2170 res = request_mem_region(port->mapbase, sport->reg_size,
2171 dev_name(port->dev));
2172 if (unlikely(res == NULL)) {
2173 dev_err(port->dev, "request_mem_region failed.");
2177 ret = sci_remap_port(port);
2178 if (unlikely(ret != 0)) {
2179 release_resource(res);
2186 static void sci_config_port(struct uart_port *port, int flags)
2188 if (flags & UART_CONFIG_TYPE) {
2189 struct sci_port *sport = to_sci_port(port);
2191 port->type = sport->cfg->type;
2192 sci_request_port(port);
2196 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2198 if (ser->baud_base < 2400)
2199 /* No paper tape reader for Mitch.. */
2205 static struct uart_ops sci_uart_ops = {
2206 .tx_empty = sci_tx_empty,
2207 .set_mctrl = sci_set_mctrl,
2208 .get_mctrl = sci_get_mctrl,
2209 .start_tx = sci_start_tx,
2210 .stop_tx = sci_stop_tx,
2211 .stop_rx = sci_stop_rx,
2212 .break_ctl = sci_break_ctl,
2213 .startup = sci_startup,
2214 .shutdown = sci_shutdown,
2215 .set_termios = sci_set_termios,
2218 .release_port = sci_release_port,
2219 .request_port = sci_request_port,
2220 .config_port = sci_config_port,
2221 .verify_port = sci_verify_port,
2222 #ifdef CONFIG_CONSOLE_POLL
2223 .poll_get_char = sci_poll_get_char,
2224 .poll_put_char = sci_poll_put_char,
2228 static int sci_init_single(struct platform_device *dev,
2229 struct sci_port *sci_port, unsigned int index,
2230 struct plat_sci_port *p, bool early)
2232 struct uart_port *port = &sci_port->port;
2233 const struct resource *res;
2239 port->ops = &sci_uart_ops;
2240 port->iotype = UPIO_MEM;
2243 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2247 port->mapbase = res->start;
2248 sci_port->reg_size = resource_size(res);
2250 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2251 sci_port->irqs[i] = platform_get_irq(dev, i);
2253 /* The SCI generates several interrupts. They can be muxed together or
2254 * connected to different interrupt lines. In the muxed case only one
2255 * interrupt resource is specified. In the non-muxed case three or four
2256 * interrupt resources are specified, as the BRI interrupt is optional.
2258 if (sci_port->irqs[0] < 0)
2261 if (sci_port->irqs[1] < 0) {
2262 sci_port->irqs[1] = sci_port->irqs[0];
2263 sci_port->irqs[2] = sci_port->irqs[0];
2264 sci_port->irqs[3] = sci_port->irqs[0];
2267 if (p->regtype == SCIx_PROBE_REGTYPE) {
2268 ret = sci_probe_regmap(p);
2275 port->fifosize = 256;
2276 sci_port->overrun_reg = SCxSR;
2277 sci_port->overrun_mask = SCIFA_ORER;
2278 sci_port->sampling_rate = 16;
2281 port->fifosize = 128;
2282 sci_port->overrun_reg = SCLSR;
2283 sci_port->overrun_mask = SCLSR_ORER;
2284 sci_port->sampling_rate = 0;
2287 port->fifosize = 64;
2288 sci_port->overrun_reg = SCxSR;
2289 sci_port->overrun_mask = SCIFA_ORER;
2290 sci_port->sampling_rate = 16;
2293 port->fifosize = 16;
2294 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2295 sci_port->overrun_reg = SCxSR;
2296 sci_port->overrun_mask = SCIFA_ORER;
2297 sci_port->sampling_rate = 16;
2299 sci_port->overrun_reg = SCLSR;
2300 sci_port->overrun_mask = SCLSR_ORER;
2301 sci_port->sampling_rate = 32;
2306 sci_port->overrun_reg = SCxSR;
2307 sci_port->overrun_mask = SCI_ORER;
2308 sci_port->sampling_rate = 32;
2312 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2313 * match the SoC datasheet, this should be investigated. Let platform
2314 * data override the sampling rate for now.
2316 if (p->sampling_rate)
2317 sci_port->sampling_rate = p->sampling_rate;
2320 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2321 if (IS_ERR(sci_port->iclk)) {
2322 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2323 if (IS_ERR(sci_port->iclk)) {
2324 dev_err(&dev->dev, "can't get iclk\n");
2325 return PTR_ERR(sci_port->iclk);
2330 * The function clock is optional, ignore it if we can't
2333 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2334 if (IS_ERR(sci_port->fclk))
2335 sci_port->fclk = NULL;
2337 port->dev = &dev->dev;
2339 pm_runtime_enable(&dev->dev);
2342 sci_port->break_timer.data = (unsigned long)sci_port;
2343 sci_port->break_timer.function = sci_break_timer;
2344 init_timer(&sci_port->break_timer);
2347 * Establish some sensible defaults for the error detection.
2349 if (p->type == PORT_SCI) {
2350 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2351 sci_port->error_clear = SCI_ERROR_CLEAR;
2353 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2354 sci_port->error_clear = SCIF_ERROR_CLEAR;
2358 * Make the error mask inclusive of overrun detection, if
2361 if (sci_port->overrun_reg == SCxSR) {
2362 sci_port->error_mask |= sci_port->overrun_mask;
2363 sci_port->error_clear &= ~sci_port->overrun_mask;
2366 port->type = p->type;
2367 port->flags = UPF_FIXED_PORT | p->flags;
2368 port->regshift = p->regshift;
2371 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2372 * for the multi-IRQ ports, which is where we are primarily
2373 * concerned with the shutdown path synchronization.
2375 * For the muxed case there's nothing more to do.
2377 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2380 port->serial_in = sci_serial_in;
2381 port->serial_out = sci_serial_out;
2383 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2384 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2385 p->dma_slave_tx, p->dma_slave_rx);
2390 static void sci_cleanup_single(struct sci_port *port)
2392 clk_put(port->iclk);
2393 clk_put(port->fclk);
2395 pm_runtime_disable(port->port.dev);
2398 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2399 static void serial_console_putchar(struct uart_port *port, int ch)
2401 sci_poll_put_char(port, ch);
2405 * Print a string to the serial port trying not to disturb
2406 * any possible real use of the port...
2408 static void serial_console_write(struct console *co, const char *s,
2411 struct sci_port *sci_port = &sci_ports[co->index];
2412 struct uart_port *port = &sci_port->port;
2413 unsigned short bits, ctrl;
2414 unsigned long flags;
2417 local_irq_save(flags);
2420 else if (oops_in_progress)
2421 locked = spin_trylock(&port->lock);
2423 spin_lock(&port->lock);
2425 /* first save the SCSCR then disable the interrupts */
2426 ctrl = serial_port_in(port, SCSCR);
2427 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2429 uart_console_write(port, s, count, serial_console_putchar);
2431 /* wait until fifo is empty and last bit has been transmitted */
2432 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2433 while ((serial_port_in(port, SCxSR) & bits) != bits)
2436 /* restore the SCSCR */
2437 serial_port_out(port, SCSCR, ctrl);
2440 spin_unlock(&port->lock);
2441 local_irq_restore(flags);
2444 static int serial_console_setup(struct console *co, char *options)
2446 struct sci_port *sci_port;
2447 struct uart_port *port;
2455 * Refuse to handle any bogus ports.
2457 if (co->index < 0 || co->index >= SCI_NPORTS)
2460 sci_port = &sci_ports[co->index];
2461 port = &sci_port->port;
2464 * Refuse to handle uninitialized ports.
2469 ret = sci_remap_port(port);
2470 if (unlikely(ret != 0))
2474 uart_parse_options(options, &baud, &parity, &bits, &flow);
2476 return uart_set_options(port, co, baud, parity, bits, flow);
2479 static struct console serial_console = {
2481 .device = uart_console_device,
2482 .write = serial_console_write,
2483 .setup = serial_console_setup,
2484 .flags = CON_PRINTBUFFER,
2486 .data = &sci_uart_driver,
2489 static struct console early_serial_console = {
2490 .name = "early_ttySC",
2491 .write = serial_console_write,
2492 .flags = CON_PRINTBUFFER,
2496 static char early_serial_buf[32];
2498 static int sci_probe_earlyprintk(struct platform_device *pdev)
2500 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2502 if (early_serial_console.data)
2505 early_serial_console.index = pdev->id;
2507 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2509 serial_console_setup(&early_serial_console, early_serial_buf);
2511 if (!strstr(early_serial_buf, "keep"))
2512 early_serial_console.flags |= CON_BOOT;
2514 register_console(&early_serial_console);
2518 #define SCI_CONSOLE (&serial_console)
2521 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2526 #define SCI_CONSOLE NULL
2528 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2530 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2532 static struct uart_driver sci_uart_driver = {
2533 .owner = THIS_MODULE,
2534 .driver_name = "sci",
2535 .dev_name = "ttySC",
2537 .minor = SCI_MINOR_START,
2539 .cons = SCI_CONSOLE,
2542 static int sci_remove(struct platform_device *dev)
2544 struct sci_port *port = platform_get_drvdata(dev);
2546 cpufreq_unregister_notifier(&port->freq_transition,
2547 CPUFREQ_TRANSITION_NOTIFIER);
2549 uart_remove_one_port(&sci_uart_driver, &port->port);
2551 sci_cleanup_single(port);
2556 struct sci_port_info {
2558 unsigned int regtype;
2561 static const struct of_device_id of_sci_match[] = {
2563 .compatible = "renesas,scif",
2564 .data = &(const struct sci_port_info) {
2566 .regtype = SCIx_SH4_SCIF_REGTYPE,
2569 .compatible = "renesas,scifa",
2570 .data = &(const struct sci_port_info) {
2572 .regtype = SCIx_SCIFA_REGTYPE,
2575 .compatible = "renesas,scifb",
2576 .data = &(const struct sci_port_info) {
2578 .regtype = SCIx_SCIFB_REGTYPE,
2581 .compatible = "renesas,hscif",
2582 .data = &(const struct sci_port_info) {
2584 .regtype = SCIx_HSCIF_REGTYPE,
2587 .compatible = "renesas,sci",
2588 .data = &(const struct sci_port_info) {
2590 .regtype = SCIx_SCI_REGTYPE,
2596 MODULE_DEVICE_TABLE(of, of_sci_match);
2598 static struct plat_sci_port *
2599 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2601 struct device_node *np = pdev->dev.of_node;
2602 const struct of_device_id *match;
2603 const struct sci_port_info *info;
2604 struct plat_sci_port *p;
2607 if (!IS_ENABLED(CONFIG_OF) || !np)
2610 match = of_match_node(of_sci_match, pdev->dev.of_node);
2616 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2620 /* Get the line number for the aliases node. */
2621 id = of_alias_get_id(np, "serial");
2623 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2629 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2630 p->type = info->type;
2631 p->regtype = info->regtype;
2632 p->scscr = SCSCR_RE | SCSCR_TE;
2637 static int sci_probe_single(struct platform_device *dev,
2639 struct plat_sci_port *p,
2640 struct sci_port *sciport)
2645 if (unlikely(index >= SCI_NPORTS)) {
2646 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2647 index+1, SCI_NPORTS);
2648 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2652 ret = sci_init_single(dev, sciport, index, p, false);
2656 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2658 sci_cleanup_single(sciport);
2665 static int sci_probe(struct platform_device *dev)
2667 struct plat_sci_port *p;
2668 struct sci_port *sp;
2669 unsigned int dev_id;
2673 * If we've come here via earlyprintk initialization, head off to
2674 * the special early probe. We don't have sufficient device state
2675 * to make it beyond this yet.
2677 if (is_early_platform_device(dev))
2678 return sci_probe_earlyprintk(dev);
2680 if (dev->dev.of_node) {
2681 p = sci_parse_dt(dev, &dev_id);
2685 p = dev->dev.platform_data;
2687 dev_err(&dev->dev, "no platform data supplied\n");
2694 sp = &sci_ports[dev_id];
2695 platform_set_drvdata(dev, sp);
2697 ret = sci_probe_single(dev, dev_id, p, sp);
2701 sp->freq_transition.notifier_call = sci_notifier;
2703 ret = cpufreq_register_notifier(&sp->freq_transition,
2704 CPUFREQ_TRANSITION_NOTIFIER);
2705 if (unlikely(ret < 0)) {
2706 uart_remove_one_port(&sci_uart_driver, &sp->port);
2707 sci_cleanup_single(sp);
2711 #ifdef CONFIG_SH_STANDARD_BIOS
2712 sh_bios_gdb_detach();
2718 static __maybe_unused int sci_suspend(struct device *dev)
2720 struct sci_port *sport = dev_get_drvdata(dev);
2723 uart_suspend_port(&sci_uart_driver, &sport->port);
2728 static __maybe_unused int sci_resume(struct device *dev)
2730 struct sci_port *sport = dev_get_drvdata(dev);
2733 uart_resume_port(&sci_uart_driver, &sport->port);
2738 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2740 static struct platform_driver sci_driver = {
2742 .remove = sci_remove,
2745 .pm = &sci_dev_pm_ops,
2746 .of_match_table = of_match_ptr(of_sci_match),
2750 static int __init sci_init(void)
2754 pr_info("%s\n", banner);
2756 ret = uart_register_driver(&sci_uart_driver);
2757 if (likely(ret == 0)) {
2758 ret = platform_driver_register(&sci_driver);
2760 uart_unregister_driver(&sci_uart_driver);
2766 static void __exit sci_exit(void)
2768 platform_driver_unregister(&sci_driver);
2769 uart_unregister_driver(&sci_uart_driver);
2772 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2773 early_platform_init_buffer("earlyprintk", &sci_driver,
2774 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2776 module_init(sci_init);
2777 module_exit(sci_exit);
2779 MODULE_LICENSE("GPL");
2780 MODULE_ALIAS("platform:sh-sci");
2781 MODULE_AUTHOR("Paul Mundt");
2782 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");