2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int sampling_rate;
88 resource_size_t reg_size;
91 struct timer_list break_timer;
99 int irqs[SCIx_NR_IRQS];
100 char *irqstr[SCIx_NR_IRQS];
102 struct dma_chan *chan_tx;
103 struct dma_chan *chan_rx;
105 #ifdef CONFIG_SERIAL_SH_SCI_DMA
106 struct dma_async_tx_descriptor *desc_tx;
107 struct dma_async_tx_descriptor *desc_rx[2];
108 dma_cookie_t cookie_tx;
109 dma_cookie_t cookie_rx[2];
110 dma_cookie_t active_rx;
111 struct scatterlist sg_tx;
112 unsigned int sg_len_tx;
113 struct scatterlist sg_rx[2];
115 struct sh_dmae_slave param_tx;
116 struct sh_dmae_slave param_rx;
117 struct work_struct work_tx;
118 struct work_struct work_rx;
119 struct timer_list rx_timer;
120 unsigned int rx_timeout;
123 struct notifier_block freq_transition;
126 /* Function prototypes */
127 static void sci_start_tx(struct uart_port *port);
128 static void sci_stop_tx(struct uart_port *port);
129 static void sci_start_rx(struct uart_port *port);
131 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
133 static struct sci_port sci_ports[SCI_NPORTS];
134 static struct uart_driver sci_uart_driver;
136 static inline struct sci_port *
137 to_sci_port(struct uart_port *uart)
139 return container_of(uart, struct sci_port, port);
142 struct plat_sci_reg {
146 /* Helper for invalidating specific entries of an inherited map. */
147 #define sci_reg_invalid { .offset = 0, .size = 0 }
149 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
150 [SCIx_PROBE_REGTYPE] = {
151 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
155 * Common SCI definitions, dependent on the port's regshift
158 [SCIx_SCI_REGTYPE] = {
159 [SCSMR] = { 0x00, 8 },
160 [SCBRR] = { 0x01, 8 },
161 [SCSCR] = { 0x02, 8 },
162 [SCxTDR] = { 0x03, 8 },
163 [SCxSR] = { 0x04, 8 },
164 [SCxRDR] = { 0x05, 8 },
165 [SCFCR] = sci_reg_invalid,
166 [SCFDR] = sci_reg_invalid,
167 [SCTFDR] = sci_reg_invalid,
168 [SCRFDR] = sci_reg_invalid,
169 [SCSPTR] = sci_reg_invalid,
170 [SCLSR] = sci_reg_invalid,
171 [HSSRR] = sci_reg_invalid,
172 [SCPCR] = sci_reg_invalid,
173 [SCPDR] = sci_reg_invalid,
177 * Common definitions for legacy IrDA ports, dependent on
180 [SCIx_IRDA_REGTYPE] = {
181 [SCSMR] = { 0x00, 8 },
182 [SCBRR] = { 0x01, 8 },
183 [SCSCR] = { 0x02, 8 },
184 [SCxTDR] = { 0x03, 8 },
185 [SCxSR] = { 0x04, 8 },
186 [SCxRDR] = { 0x05, 8 },
187 [SCFCR] = { 0x06, 8 },
188 [SCFDR] = { 0x07, 16 },
189 [SCTFDR] = sci_reg_invalid,
190 [SCRFDR] = sci_reg_invalid,
191 [SCSPTR] = sci_reg_invalid,
192 [SCLSR] = sci_reg_invalid,
193 [HSSRR] = sci_reg_invalid,
194 [SCPCR] = sci_reg_invalid,
195 [SCPDR] = sci_reg_invalid,
199 * Common SCIFA definitions.
201 [SCIx_SCIFA_REGTYPE] = {
202 [SCSMR] = { 0x00, 16 },
203 [SCBRR] = { 0x04, 8 },
204 [SCSCR] = { 0x08, 16 },
205 [SCxTDR] = { 0x20, 8 },
206 [SCxSR] = { 0x14, 16 },
207 [SCxRDR] = { 0x24, 8 },
208 [SCFCR] = { 0x18, 16 },
209 [SCFDR] = { 0x1c, 16 },
210 [SCTFDR] = sci_reg_invalid,
211 [SCRFDR] = sci_reg_invalid,
212 [SCSPTR] = sci_reg_invalid,
213 [SCLSR] = sci_reg_invalid,
214 [HSSRR] = sci_reg_invalid,
215 [SCPCR] = { 0x30, 16 },
216 [SCPDR] = { 0x34, 16 },
220 * Common SCIFB definitions.
222 [SCIx_SCIFB_REGTYPE] = {
223 [SCSMR] = { 0x00, 16 },
224 [SCBRR] = { 0x04, 8 },
225 [SCSCR] = { 0x08, 16 },
226 [SCxTDR] = { 0x40, 8 },
227 [SCxSR] = { 0x14, 16 },
228 [SCxRDR] = { 0x60, 8 },
229 [SCFCR] = { 0x18, 16 },
230 [SCFDR] = sci_reg_invalid,
231 [SCTFDR] = { 0x38, 16 },
232 [SCRFDR] = { 0x3c, 16 },
233 [SCSPTR] = sci_reg_invalid,
234 [SCLSR] = sci_reg_invalid,
235 [HSSRR] = sci_reg_invalid,
236 [SCPCR] = { 0x30, 16 },
237 [SCPDR] = { 0x34, 16 },
241 * Common SH-2(A) SCIF definitions for ports with FIFO data
244 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
245 [SCSMR] = { 0x00, 16 },
246 [SCBRR] = { 0x04, 8 },
247 [SCSCR] = { 0x08, 16 },
248 [SCxTDR] = { 0x0c, 8 },
249 [SCxSR] = { 0x10, 16 },
250 [SCxRDR] = { 0x14, 8 },
251 [SCFCR] = { 0x18, 16 },
252 [SCFDR] = { 0x1c, 16 },
253 [SCTFDR] = sci_reg_invalid,
254 [SCRFDR] = sci_reg_invalid,
255 [SCSPTR] = { 0x20, 16 },
256 [SCLSR] = { 0x24, 16 },
257 [HSSRR] = sci_reg_invalid,
258 [SCPCR] = sci_reg_invalid,
259 [SCPDR] = sci_reg_invalid,
263 * Common SH-3 SCIF definitions.
265 [SCIx_SH3_SCIF_REGTYPE] = {
266 [SCSMR] = { 0x00, 8 },
267 [SCBRR] = { 0x02, 8 },
268 [SCSCR] = { 0x04, 8 },
269 [SCxTDR] = { 0x06, 8 },
270 [SCxSR] = { 0x08, 16 },
271 [SCxRDR] = { 0x0a, 8 },
272 [SCFCR] = { 0x0c, 8 },
273 [SCFDR] = { 0x0e, 16 },
274 [SCTFDR] = sci_reg_invalid,
275 [SCRFDR] = sci_reg_invalid,
276 [SCSPTR] = sci_reg_invalid,
277 [SCLSR] = sci_reg_invalid,
278 [HSSRR] = sci_reg_invalid,
279 [SCPCR] = sci_reg_invalid,
280 [SCPDR] = sci_reg_invalid,
284 * Common SH-4(A) SCIF(B) definitions.
286 [SCIx_SH4_SCIF_REGTYPE] = {
287 [SCSMR] = { 0x00, 16 },
288 [SCBRR] = { 0x04, 8 },
289 [SCSCR] = { 0x08, 16 },
290 [SCxTDR] = { 0x0c, 8 },
291 [SCxSR] = { 0x10, 16 },
292 [SCxRDR] = { 0x14, 8 },
293 [SCFCR] = { 0x18, 16 },
294 [SCFDR] = { 0x1c, 16 },
295 [SCTFDR] = sci_reg_invalid,
296 [SCRFDR] = sci_reg_invalid,
297 [SCSPTR] = { 0x20, 16 },
298 [SCLSR] = { 0x24, 16 },
299 [HSSRR] = sci_reg_invalid,
300 [SCPCR] = sci_reg_invalid,
301 [SCPDR] = sci_reg_invalid,
305 * Common HSCIF definitions.
307 [SCIx_HSCIF_REGTYPE] = {
308 [SCSMR] = { 0x00, 16 },
309 [SCBRR] = { 0x04, 8 },
310 [SCSCR] = { 0x08, 16 },
311 [SCxTDR] = { 0x0c, 8 },
312 [SCxSR] = { 0x10, 16 },
313 [SCxRDR] = { 0x14, 8 },
314 [SCFCR] = { 0x18, 16 },
315 [SCFDR] = { 0x1c, 16 },
316 [SCTFDR] = sci_reg_invalid,
317 [SCRFDR] = sci_reg_invalid,
318 [SCSPTR] = { 0x20, 16 },
319 [SCLSR] = { 0x24, 16 },
320 [HSSRR] = { 0x40, 16 },
321 [SCPCR] = sci_reg_invalid,
322 [SCPDR] = sci_reg_invalid,
326 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
329 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
330 [SCSMR] = { 0x00, 16 },
331 [SCBRR] = { 0x04, 8 },
332 [SCSCR] = { 0x08, 16 },
333 [SCxTDR] = { 0x0c, 8 },
334 [SCxSR] = { 0x10, 16 },
335 [SCxRDR] = { 0x14, 8 },
336 [SCFCR] = { 0x18, 16 },
337 [SCFDR] = { 0x1c, 16 },
338 [SCTFDR] = sci_reg_invalid,
339 [SCRFDR] = sci_reg_invalid,
340 [SCSPTR] = sci_reg_invalid,
341 [SCLSR] = { 0x24, 16 },
342 [HSSRR] = sci_reg_invalid,
343 [SCPCR] = sci_reg_invalid,
344 [SCPDR] = sci_reg_invalid,
348 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
351 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
352 [SCSMR] = { 0x00, 16 },
353 [SCBRR] = { 0x04, 8 },
354 [SCSCR] = { 0x08, 16 },
355 [SCxTDR] = { 0x0c, 8 },
356 [SCxSR] = { 0x10, 16 },
357 [SCxRDR] = { 0x14, 8 },
358 [SCFCR] = { 0x18, 16 },
359 [SCFDR] = { 0x1c, 16 },
360 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
361 [SCRFDR] = { 0x20, 16 },
362 [SCSPTR] = { 0x24, 16 },
363 [SCLSR] = { 0x28, 16 },
364 [HSSRR] = sci_reg_invalid,
365 [SCPCR] = sci_reg_invalid,
366 [SCPDR] = sci_reg_invalid,
370 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
373 [SCIx_SH7705_SCIF_REGTYPE] = {
374 [SCSMR] = { 0x00, 16 },
375 [SCBRR] = { 0x04, 8 },
376 [SCSCR] = { 0x08, 16 },
377 [SCxTDR] = { 0x20, 8 },
378 [SCxSR] = { 0x14, 16 },
379 [SCxRDR] = { 0x24, 8 },
380 [SCFCR] = { 0x18, 16 },
381 [SCFDR] = { 0x1c, 16 },
382 [SCTFDR] = sci_reg_invalid,
383 [SCRFDR] = sci_reg_invalid,
384 [SCSPTR] = sci_reg_invalid,
385 [SCLSR] = sci_reg_invalid,
386 [HSSRR] = sci_reg_invalid,
387 [SCPCR] = sci_reg_invalid,
388 [SCPDR] = sci_reg_invalid,
392 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
395 * The "offset" here is rather misleading, in that it refers to an enum
396 * value relative to the port mapping rather than the fixed offset
397 * itself, which needs to be manually retrieved from the platform's
398 * register map for the given port.
400 static unsigned int sci_serial_in(struct uart_port *p, int offset)
402 struct plat_sci_reg *reg = sci_getreg(p, offset);
405 return ioread8(p->membase + (reg->offset << p->regshift));
406 else if (reg->size == 16)
407 return ioread16(p->membase + (reg->offset << p->regshift));
409 WARN(1, "Invalid register access\n");
414 static void sci_serial_out(struct uart_port *p, int offset, int value)
416 struct plat_sci_reg *reg = sci_getreg(p, offset);
419 iowrite8(value, p->membase + (reg->offset << p->regshift));
420 else if (reg->size == 16)
421 iowrite16(value, p->membase + (reg->offset << p->regshift));
423 WARN(1, "Invalid register access\n");
426 static int sci_probe_regmap(struct plat_sci_port *cfg)
430 cfg->regtype = SCIx_SCI_REGTYPE;
433 cfg->regtype = SCIx_IRDA_REGTYPE;
436 cfg->regtype = SCIx_SCIFA_REGTYPE;
439 cfg->regtype = SCIx_SCIFB_REGTYPE;
443 * The SH-4 is a bit of a misnomer here, although that's
444 * where this particular port layout originated. This
445 * configuration (or some slight variation thereof)
446 * remains the dominant model for all SCIFs.
448 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
451 cfg->regtype = SCIx_HSCIF_REGTYPE;
454 pr_err("Can't probe register map for given port\n");
461 static void sci_port_enable(struct sci_port *sci_port)
463 if (!sci_port->port.dev)
466 pm_runtime_get_sync(sci_port->port.dev);
468 clk_prepare_enable(sci_port->iclk);
469 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
470 clk_prepare_enable(sci_port->fclk);
473 static void sci_port_disable(struct sci_port *sci_port)
475 if (!sci_port->port.dev)
478 /* Cancel the break timer to ensure that the timer handler will not try
479 * to access the hardware with clocks and power disabled. Reset the
480 * break flag to make the break debouncing state machine ready for the
483 del_timer_sync(&sci_port->break_timer);
484 sci_port->break_flag = 0;
486 clk_disable_unprepare(sci_port->fclk);
487 clk_disable_unprepare(sci_port->iclk);
489 pm_runtime_put_sync(sci_port->port.dev);
492 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
494 if (port->type == PORT_SCI) {
495 /* Just store the mask */
496 serial_port_out(port, SCxSR, mask);
497 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
498 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
499 /* Only clear the status bits we want to clear */
500 serial_port_out(port, SCxSR,
501 serial_port_in(port, SCxSR) & mask);
503 /* Store the mask, clear parity/framing errors */
504 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
508 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
510 #ifdef CONFIG_CONSOLE_POLL
511 static int sci_poll_get_char(struct uart_port *port)
513 unsigned short status;
517 status = serial_port_in(port, SCxSR);
518 if (status & SCxSR_ERRORS(port)) {
519 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
525 if (!(status & SCxSR_RDxF(port)))
528 c = serial_port_in(port, SCxRDR);
531 serial_port_in(port, SCxSR);
532 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
538 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
540 unsigned short status;
543 status = serial_port_in(port, SCxSR);
544 } while (!(status & SCxSR_TDxE(port)));
546 serial_port_out(port, SCxTDR, c);
547 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
549 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
551 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
553 struct sci_port *s = to_sci_port(port);
554 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
557 * Use port-specific handler if provided.
559 if (s->cfg->ops && s->cfg->ops->init_pins) {
560 s->cfg->ops->init_pins(port, cflag);
565 * For the generic path SCSPTR is necessary. Bail out if that's
571 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
572 ((!(cflag & CRTSCTS)))) {
573 unsigned short status;
575 status = serial_port_in(port, SCSPTR);
576 status &= ~SCSPTR_CTSIO;
577 status |= SCSPTR_RTSIO;
578 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
582 static int sci_txfill(struct uart_port *port)
584 struct plat_sci_reg *reg;
586 reg = sci_getreg(port, SCTFDR);
588 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
590 reg = sci_getreg(port, SCFDR);
592 return serial_port_in(port, SCFDR) >> 8;
594 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
597 static int sci_txroom(struct uart_port *port)
599 return port->fifosize - sci_txfill(port);
602 static int sci_rxfill(struct uart_port *port)
604 struct plat_sci_reg *reg;
606 reg = sci_getreg(port, SCRFDR);
608 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
610 reg = sci_getreg(port, SCFDR);
612 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
614 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
618 * SCI helper for checking the state of the muxed port/RXD pins.
620 static inline int sci_rxd_in(struct uart_port *port)
622 struct sci_port *s = to_sci_port(port);
624 if (s->cfg->port_reg <= 0)
627 /* Cast for ARM damage */
628 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
631 /* ********************************************************************** *
632 * the interrupt related routines *
633 * ********************************************************************** */
635 static void sci_transmit_chars(struct uart_port *port)
637 struct circ_buf *xmit = &port->state->xmit;
638 unsigned int stopped = uart_tx_stopped(port);
639 unsigned short status;
643 status = serial_port_in(port, SCxSR);
644 if (!(status & SCxSR_TDxE(port))) {
645 ctrl = serial_port_in(port, SCSCR);
646 if (uart_circ_empty(xmit))
650 serial_port_out(port, SCSCR, ctrl);
654 count = sci_txroom(port);
662 } else if (!uart_circ_empty(xmit) && !stopped) {
663 c = xmit->buf[xmit->tail];
664 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
669 serial_port_out(port, SCxTDR, c);
672 } while (--count > 0);
674 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
676 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
677 uart_write_wakeup(port);
678 if (uart_circ_empty(xmit)) {
681 ctrl = serial_port_in(port, SCSCR);
683 if (port->type != PORT_SCI) {
684 serial_port_in(port, SCxSR); /* Dummy read */
685 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
689 serial_port_out(port, SCSCR, ctrl);
693 /* On SH3, SCIF may read end-of-break as a space->mark char */
694 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
696 static void sci_receive_chars(struct uart_port *port)
698 struct sci_port *sci_port = to_sci_port(port);
699 struct tty_port *tport = &port->state->port;
700 int i, count, copied = 0;
701 unsigned short status;
704 status = serial_port_in(port, SCxSR);
705 if (!(status & SCxSR_RDxF(port)))
709 /* Don't copy more bytes than there is room for in the buffer */
710 count = tty_buffer_request_room(tport, sci_rxfill(port));
712 /* If for any reason we can't copy more data, we're done! */
716 if (port->type == PORT_SCI) {
717 char c = serial_port_in(port, SCxRDR);
718 if (uart_handle_sysrq_char(port, c) ||
719 sci_port->break_flag)
722 tty_insert_flip_char(tport, c, TTY_NORMAL);
724 for (i = 0; i < count; i++) {
725 char c = serial_port_in(port, SCxRDR);
727 status = serial_port_in(port, SCxSR);
728 #if defined(CONFIG_CPU_SH3)
729 /* Skip "chars" during break */
730 if (sci_port->break_flag) {
732 (status & SCxSR_FER(port))) {
737 /* Nonzero => end-of-break */
738 dev_dbg(port->dev, "debounce<%02x>\n", c);
739 sci_port->break_flag = 0;
746 #endif /* CONFIG_CPU_SH3 */
747 if (uart_handle_sysrq_char(port, c)) {
752 /* Store data and status */
753 if (status & SCxSR_FER(port)) {
755 port->icount.frame++;
756 dev_notice(port->dev, "frame error\n");
757 } else if (status & SCxSR_PER(port)) {
759 port->icount.parity++;
760 dev_notice(port->dev, "parity error\n");
764 tty_insert_flip_char(tport, c, flag);
768 serial_port_in(port, SCxSR); /* dummy read */
769 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
772 port->icount.rx += count;
776 /* Tell the rest of the system the news. New characters! */
777 tty_flip_buffer_push(tport);
779 serial_port_in(port, SCxSR); /* dummy read */
780 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
784 #define SCI_BREAK_JIFFIES (HZ/20)
787 * The sci generates interrupts during the break,
788 * 1 per millisecond or so during the break period, for 9600 baud.
789 * So dont bother disabling interrupts.
790 * But dont want more than 1 break event.
791 * Use a kernel timer to periodically poll the rx line until
792 * the break is finished.
794 static inline void sci_schedule_break_timer(struct sci_port *port)
796 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
799 /* Ensure that two consecutive samples find the break over. */
800 static void sci_break_timer(unsigned long data)
802 struct sci_port *port = (struct sci_port *)data;
804 if (sci_rxd_in(&port->port) == 0) {
805 port->break_flag = 1;
806 sci_schedule_break_timer(port);
807 } else if (port->break_flag == 1) {
809 port->break_flag = 2;
810 sci_schedule_break_timer(port);
812 port->break_flag = 0;
815 static int sci_handle_errors(struct uart_port *port)
818 unsigned short status = serial_port_in(port, SCxSR);
819 struct tty_port *tport = &port->state->port;
820 struct sci_port *s = to_sci_port(port);
822 /* Handle overruns */
823 if (status & s->overrun_mask) {
824 port->icount.overrun++;
827 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
830 dev_notice(port->dev, "overrun error\n");
833 if (status & SCxSR_FER(port)) {
834 if (sci_rxd_in(port) == 0) {
835 /* Notify of BREAK */
836 struct sci_port *sci_port = to_sci_port(port);
838 if (!sci_port->break_flag) {
841 sci_port->break_flag = 1;
842 sci_schedule_break_timer(sci_port);
844 /* Do sysrq handling. */
845 if (uart_handle_break(port))
848 dev_dbg(port->dev, "BREAK detected\n");
850 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
856 port->icount.frame++;
858 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
861 dev_notice(port->dev, "frame error\n");
865 if (status & SCxSR_PER(port)) {
867 port->icount.parity++;
869 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
872 dev_notice(port->dev, "parity error\n");
876 tty_flip_buffer_push(tport);
881 static int sci_handle_fifo_overrun(struct uart_port *port)
883 struct tty_port *tport = &port->state->port;
884 struct sci_port *s = to_sci_port(port);
885 struct plat_sci_reg *reg;
889 reg = sci_getreg(port, s->overrun_reg);
893 status = serial_port_in(port, s->overrun_reg);
894 if (status & s->overrun_mask) {
895 status &= ~s->overrun_mask;
896 serial_port_out(port, s->overrun_reg, status);
898 port->icount.overrun++;
900 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
901 tty_flip_buffer_push(tport);
903 dev_dbg(port->dev, "overrun error\n");
910 static int sci_handle_breaks(struct uart_port *port)
913 unsigned short status = serial_port_in(port, SCxSR);
914 struct tty_port *tport = &port->state->port;
915 struct sci_port *s = to_sci_port(port);
917 if (uart_handle_break(port))
920 if (!s->break_flag && status & SCxSR_BRK(port)) {
921 #if defined(CONFIG_CPU_SH3)
928 /* Notify of BREAK */
929 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
932 dev_dbg(port->dev, "BREAK detected\n");
936 tty_flip_buffer_push(tport);
938 copied += sci_handle_fifo_overrun(port);
943 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
945 #ifdef CONFIG_SERIAL_SH_SCI_DMA
946 struct uart_port *port = ptr;
947 struct sci_port *s = to_sci_port(port);
950 u16 scr = serial_port_in(port, SCSCR);
951 u16 ssr = serial_port_in(port, SCxSR);
953 /* Disable future Rx interrupts */
954 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
955 disable_irq_nosync(irq);
960 serial_port_out(port, SCSCR, scr);
961 /* Clear current interrupt */
962 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
963 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
964 jiffies, s->rx_timeout);
965 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
971 /* I think sci_receive_chars has to be called irrespective
972 * of whether the I_IXOFF is set, otherwise, how is the interrupt
975 sci_receive_chars(ptr);
980 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
982 struct uart_port *port = ptr;
985 spin_lock_irqsave(&port->lock, flags);
986 sci_transmit_chars(port);
987 spin_unlock_irqrestore(&port->lock, flags);
992 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
994 struct uart_port *port = ptr;
997 if (port->type == PORT_SCI) {
998 if (sci_handle_errors(port)) {
999 /* discard character in rx buffer */
1000 serial_port_in(port, SCxSR);
1001 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1004 sci_handle_fifo_overrun(port);
1005 sci_rx_interrupt(irq, ptr);
1008 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1010 /* Kick the transmission */
1011 sci_tx_interrupt(irq, ptr);
1016 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1018 struct uart_port *port = ptr;
1021 sci_handle_breaks(port);
1022 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1027 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1030 * Not all ports (such as SCIFA) will support REIE. Rather than
1031 * special-casing the port type, we check the port initialization
1032 * IRQ enable mask to see whether the IRQ is desired at all. If
1033 * it's unset, it's logically inferred that there's no point in
1036 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1039 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1041 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1042 struct uart_port *port = ptr;
1043 struct sci_port *s = to_sci_port(port);
1044 irqreturn_t ret = IRQ_NONE;
1046 ssr_status = serial_port_in(port, SCxSR);
1047 scr_status = serial_port_in(port, SCSCR);
1048 if (s->overrun_reg == SCxSR)
1049 orer_status = ssr_status;
1051 if (sci_getreg(port, s->overrun_reg)->size)
1052 orer_status = serial_port_in(port, s->overrun_reg);
1055 err_enabled = scr_status & port_rx_irq_mask(port);
1058 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1060 ret = sci_tx_interrupt(irq, ptr);
1063 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1066 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1067 (scr_status & SCSCR_RIE)) {
1068 if (port->type == PORT_SCIF || port->type == PORT_HSCIF)
1069 sci_handle_fifo_overrun(port);
1070 ret = sci_rx_interrupt(irq, ptr);
1073 /* Error Interrupt */
1074 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1075 ret = sci_er_interrupt(irq, ptr);
1077 /* Break Interrupt */
1078 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1079 ret = sci_br_interrupt(irq, ptr);
1081 /* Overrun Interrupt */
1082 if (orer_status & s->overrun_mask)
1083 sci_handle_fifo_overrun(port);
1089 * Here we define a transition notifier so that we can update all of our
1090 * ports' baud rate when the peripheral clock changes.
1092 static int sci_notifier(struct notifier_block *self,
1093 unsigned long phase, void *p)
1095 struct sci_port *sci_port;
1096 unsigned long flags;
1098 sci_port = container_of(self, struct sci_port, freq_transition);
1100 if (phase == CPUFREQ_POSTCHANGE) {
1101 struct uart_port *port = &sci_port->port;
1103 spin_lock_irqsave(&port->lock, flags);
1104 port->uartclk = clk_get_rate(sci_port->iclk);
1105 spin_unlock_irqrestore(&port->lock, flags);
1111 static struct sci_irq_desc {
1113 irq_handler_t handler;
1114 } sci_irq_desc[] = {
1116 * Split out handlers, the default case.
1120 .handler = sci_er_interrupt,
1125 .handler = sci_rx_interrupt,
1130 .handler = sci_tx_interrupt,
1135 .handler = sci_br_interrupt,
1139 * Special muxed handler.
1143 .handler = sci_mpxed_interrupt,
1147 static int sci_request_irq(struct sci_port *port)
1149 struct uart_port *up = &port->port;
1152 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1153 struct sci_irq_desc *desc;
1156 if (SCIx_IRQ_IS_MUXED(port)) {
1160 irq = port->irqs[i];
1163 * Certain port types won't support all of the
1164 * available interrupt sources.
1166 if (unlikely(irq < 0))
1170 desc = sci_irq_desc + i;
1171 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1172 dev_name(up->dev), desc->desc);
1173 if (!port->irqstr[j]) {
1174 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1179 ret = request_irq(irq, desc->handler, up->irqflags,
1180 port->irqstr[j], port);
1181 if (unlikely(ret)) {
1182 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1191 free_irq(port->irqs[i], port);
1195 kfree(port->irqstr[j]);
1200 static void sci_free_irq(struct sci_port *port)
1205 * Intentionally in reverse order so we iterate over the muxed
1208 for (i = 0; i < SCIx_NR_IRQS; i++) {
1209 int irq = port->irqs[i];
1212 * Certain port types won't support all of the available
1213 * interrupt sources.
1215 if (unlikely(irq < 0))
1218 free_irq(port->irqs[i], port);
1219 kfree(port->irqstr[i]);
1221 if (SCIx_IRQ_IS_MUXED(port)) {
1222 /* If there's only one IRQ, we're done. */
1228 static unsigned int sci_tx_empty(struct uart_port *port)
1230 unsigned short status = serial_port_in(port, SCxSR);
1231 unsigned short in_tx_fifo = sci_txfill(port);
1233 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1237 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1238 * CTS/RTS is supported in hardware by at least one port and controlled
1239 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1240 * handled via the ->init_pins() op, which is a bit of a one-way street,
1241 * lacking any ability to defer pin control -- this will later be
1242 * converted over to the GPIO framework).
1244 * Other modes (such as loopback) are supported generically on certain
1245 * port types, but not others. For these it's sufficient to test for the
1246 * existence of the support register and simply ignore the port type.
1248 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1250 if (mctrl & TIOCM_LOOP) {
1251 struct plat_sci_reg *reg;
1254 * Standard loopback mode for SCFCR ports.
1256 reg = sci_getreg(port, SCFCR);
1258 serial_port_out(port, SCFCR,
1259 serial_port_in(port, SCFCR) |
1264 static unsigned int sci_get_mctrl(struct uart_port *port)
1267 * CTS/RTS is handled in hardware when supported, while nothing
1268 * else is wired up. Keep it simple and simply assert DSR/CAR.
1270 return TIOCM_DSR | TIOCM_CAR;
1273 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1274 static void sci_dma_tx_complete(void *arg)
1276 struct sci_port *s = arg;
1277 struct uart_port *port = &s->port;
1278 struct circ_buf *xmit = &port->state->xmit;
1279 unsigned long flags;
1281 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1283 spin_lock_irqsave(&port->lock, flags);
1285 xmit->tail += sg_dma_len(&s->sg_tx);
1286 xmit->tail &= UART_XMIT_SIZE - 1;
1288 port->icount.tx += sg_dma_len(&s->sg_tx);
1290 async_tx_ack(s->desc_tx);
1293 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1294 uart_write_wakeup(port);
1296 if (!uart_circ_empty(xmit)) {
1298 schedule_work(&s->work_tx);
1300 s->cookie_tx = -EINVAL;
1301 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1302 u16 ctrl = serial_port_in(port, SCSCR);
1303 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1307 spin_unlock_irqrestore(&port->lock, flags);
1310 /* Locking: called with port lock held */
1311 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1313 struct uart_port *port = &s->port;
1314 struct tty_port *tport = &port->state->port;
1315 int i, active, room;
1317 room = tty_buffer_request_room(tport, count);
1319 if (s->active_rx == s->cookie_rx[0]) {
1321 } else if (s->active_rx == s->cookie_rx[1]) {
1324 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1329 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1334 for (i = 0; i < room; i++)
1335 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1338 port->icount.rx += room;
1343 static void sci_dma_rx_complete(void *arg)
1345 struct sci_port *s = arg;
1346 struct uart_port *port = &s->port;
1347 unsigned long flags;
1350 dev_dbg(port->dev, "%s(%d) active #%d\n",
1351 __func__, port->line, s->active_rx);
1353 spin_lock_irqsave(&port->lock, flags);
1355 count = sci_dma_rx_push(s, s->buf_len_rx);
1357 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1359 spin_unlock_irqrestore(&port->lock, flags);
1362 tty_flip_buffer_push(&port->state->port);
1364 schedule_work(&s->work_rx);
1367 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1369 struct dma_chan *chan = s->chan_rx;
1370 struct uart_port *port = &s->port;
1373 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1374 dma_release_channel(chan);
1375 if (sg_dma_address(&s->sg_rx[0]))
1376 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1377 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1382 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1384 struct dma_chan *chan = s->chan_tx;
1385 struct uart_port *port = &s->port;
1388 s->cookie_tx = -EINVAL;
1389 dma_release_channel(chan);
1394 static void sci_submit_rx(struct sci_port *s)
1396 struct dma_chan *chan = s->chan_rx;
1399 for (i = 0; i < 2; i++) {
1400 struct scatterlist *sg = &s->sg_rx[i];
1401 struct dma_async_tx_descriptor *desc;
1403 desc = dmaengine_prep_slave_sg(chan,
1404 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1407 s->desc_rx[i] = desc;
1408 desc->callback = sci_dma_rx_complete;
1409 desc->callback_param = s;
1410 s->cookie_rx[i] = desc->tx_submit(desc);
1413 if (!desc || s->cookie_rx[i] < 0) {
1415 async_tx_ack(s->desc_rx[0]);
1416 s->cookie_rx[0] = -EINVAL;
1420 s->cookie_rx[i] = -EINVAL;
1422 dev_warn(s->port.dev,
1423 "failed to re-start DMA, using PIO\n");
1424 sci_rx_dma_release(s, true);
1427 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1428 __func__, s->cookie_rx[i], i);
1431 s->active_rx = s->cookie_rx[0];
1433 dma_async_issue_pending(chan);
1436 static void work_fn_rx(struct work_struct *work)
1438 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1439 struct uart_port *port = &s->port;
1440 struct dma_async_tx_descriptor *desc;
1443 if (s->active_rx == s->cookie_rx[0]) {
1445 } else if (s->active_rx == s->cookie_rx[1]) {
1448 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1451 desc = s->desc_rx[new];
1453 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1455 /* Handle incomplete DMA receive */
1456 struct dma_chan *chan = s->chan_rx;
1457 struct shdma_desc *sh_desc = container_of(desc,
1458 struct shdma_desc, async_tx);
1459 unsigned long flags;
1462 dmaengine_terminate_all(chan);
1463 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1464 sh_desc->partial, sh_desc->cookie);
1466 spin_lock_irqsave(&port->lock, flags);
1467 count = sci_dma_rx_push(s, sh_desc->partial);
1468 spin_unlock_irqrestore(&port->lock, flags);
1471 tty_flip_buffer_push(&port->state->port);
1478 s->cookie_rx[new] = desc->tx_submit(desc);
1479 if (s->cookie_rx[new] < 0) {
1480 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1481 sci_rx_dma_release(s, true);
1485 s->active_rx = s->cookie_rx[!new];
1487 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1488 __func__, s->cookie_rx[new], new, s->active_rx);
1491 static void work_fn_tx(struct work_struct *work)
1493 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1494 struct dma_async_tx_descriptor *desc;
1495 struct dma_chan *chan = s->chan_tx;
1496 struct uart_port *port = &s->port;
1497 struct circ_buf *xmit = &port->state->xmit;
1498 struct scatterlist *sg = &s->sg_tx;
1502 * Port xmit buffer is already mapped, and it is one page... Just adjust
1503 * offsets and lengths. Since it is a circular buffer, we have to
1504 * transmit till the end, and then the rest. Take the port lock to get a
1505 * consistent xmit buffer state.
1507 spin_lock_irq(&port->lock);
1508 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1509 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1511 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1512 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1513 spin_unlock_irq(&port->lock);
1515 BUG_ON(!sg_dma_len(sg));
1517 desc = dmaengine_prep_slave_sg(chan,
1518 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1519 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1522 sci_tx_dma_release(s, true);
1526 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1528 spin_lock_irq(&port->lock);
1530 desc->callback = sci_dma_tx_complete;
1531 desc->callback_param = s;
1532 spin_unlock_irq(&port->lock);
1533 s->cookie_tx = desc->tx_submit(desc);
1534 if (s->cookie_tx < 0) {
1535 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1537 sci_tx_dma_release(s, true);
1541 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1542 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1544 dma_async_issue_pending(chan);
1548 static void sci_start_tx(struct uart_port *port)
1550 struct sci_port *s = to_sci_port(port);
1551 unsigned short ctrl;
1553 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1554 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1555 u16 new, scr = serial_port_in(port, SCSCR);
1557 new = scr | SCSCR_TDRQE;
1559 new = scr & ~SCSCR_TDRQE;
1561 serial_port_out(port, SCSCR, new);
1564 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1567 schedule_work(&s->work_tx);
1571 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1572 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1573 ctrl = serial_port_in(port, SCSCR);
1574 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1578 static void sci_stop_tx(struct uart_port *port)
1580 unsigned short ctrl;
1582 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1583 ctrl = serial_port_in(port, SCSCR);
1585 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1586 ctrl &= ~SCSCR_TDRQE;
1590 serial_port_out(port, SCSCR, ctrl);
1593 static void sci_start_rx(struct uart_port *port)
1595 unsigned short ctrl;
1597 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1600 ctrl &= ~SCSCR_RDRQE;
1602 serial_port_out(port, SCSCR, ctrl);
1605 static void sci_stop_rx(struct uart_port *port)
1607 unsigned short ctrl;
1609 ctrl = serial_port_in(port, SCSCR);
1611 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1612 ctrl &= ~SCSCR_RDRQE;
1614 ctrl &= ~port_rx_irq_mask(port);
1616 serial_port_out(port, SCSCR, ctrl);
1619 static void sci_break_ctl(struct uart_port *port, int break_state)
1621 struct sci_port *s = to_sci_port(port);
1622 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1623 unsigned short scscr, scsptr;
1625 /* check wheter the port has SCSPTR */
1628 * Not supported by hardware. Most parts couple break and rx
1629 * interrupts together, with break detection always enabled.
1634 scsptr = serial_port_in(port, SCSPTR);
1635 scscr = serial_port_in(port, SCSCR);
1637 if (break_state == -1) {
1638 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1641 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1645 serial_port_out(port, SCSPTR, scsptr);
1646 serial_port_out(port, SCSCR, scscr);
1649 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1650 static bool filter(struct dma_chan *chan, void *slave)
1652 struct sh_dmae_slave *param = slave;
1654 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1655 __func__, param->shdma_slave.slave_id);
1657 chan->private = ¶m->shdma_slave;
1661 static void rx_timer_fn(unsigned long arg)
1663 struct sci_port *s = (struct sci_port *)arg;
1664 struct uart_port *port = &s->port;
1665 u16 scr = serial_port_in(port, SCSCR);
1667 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1668 scr &= ~SCSCR_RDRQE;
1669 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1671 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1672 dev_dbg(port->dev, "DMA Rx timed out\n");
1673 schedule_work(&s->work_rx);
1676 static void sci_request_dma(struct uart_port *port)
1678 struct sci_port *s = to_sci_port(port);
1679 struct sh_dmae_slave *param;
1680 struct dma_chan *chan;
1681 dma_cap_mask_t mask;
1684 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1686 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1690 dma_cap_set(DMA_SLAVE, mask);
1692 param = &s->param_tx;
1694 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1695 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1697 s->cookie_tx = -EINVAL;
1698 chan = dma_request_channel(mask, filter, param);
1699 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1702 sg_init_table(&s->sg_tx, 1);
1703 /* UART circular tx buffer is an aligned page. */
1704 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1705 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1707 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1708 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1710 sci_tx_dma_release(s, false);
1712 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1714 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1715 &sg_dma_address(&s->sg_tx));
1717 s->sg_len_tx = nent;
1719 INIT_WORK(&s->work_tx, work_fn_tx);
1722 param = &s->param_rx;
1724 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1725 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1727 chan = dma_request_channel(mask, filter, param);
1728 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1736 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1737 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1738 &dma[0], GFP_KERNEL);
1742 "failed to allocate dma buffer, using PIO\n");
1743 sci_rx_dma_release(s, true);
1747 buf[1] = buf[0] + s->buf_len_rx;
1748 dma[1] = dma[0] + s->buf_len_rx;
1750 for (i = 0; i < 2; i++) {
1751 struct scatterlist *sg = &s->sg_rx[i];
1753 sg_init_table(sg, 1);
1754 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1755 (uintptr_t)buf[i] & ~PAGE_MASK);
1756 sg_dma_address(sg) = dma[i];
1759 INIT_WORK(&s->work_rx, work_fn_rx);
1760 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1766 static void sci_free_dma(struct uart_port *port)
1768 struct sci_port *s = to_sci_port(port);
1771 sci_tx_dma_release(s, false);
1773 sci_rx_dma_release(s, false);
1776 static inline void sci_request_dma(struct uart_port *port)
1780 static inline void sci_free_dma(struct uart_port *port)
1785 static int sci_startup(struct uart_port *port)
1787 struct sci_port *s = to_sci_port(port);
1788 unsigned long flags;
1791 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1793 ret = sci_request_irq(s);
1794 if (unlikely(ret < 0))
1797 sci_request_dma(port);
1799 spin_lock_irqsave(&port->lock, flags);
1802 spin_unlock_irqrestore(&port->lock, flags);
1807 static void sci_shutdown(struct uart_port *port)
1809 struct sci_port *s = to_sci_port(port);
1810 unsigned long flags;
1812 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1814 spin_lock_irqsave(&port->lock, flags);
1817 spin_unlock_irqrestore(&port->lock, flags);
1823 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1826 if (s->sampling_rate)
1827 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1829 /* Warn, but use a safe default */
1832 return ((freq + 16 * bps) / (32 * bps) - 1);
1835 /* calculate frame length from SMR */
1836 static int sci_baud_calc_frame_len(unsigned int smr_val)
1840 if (smr_val & SCSMR_CHR)
1842 if (smr_val & SCSMR_PE)
1844 if (smr_val & SCSMR_STOP)
1851 /* calculate sample rate, BRR, and clock select for HSCIF */
1852 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1853 int *brr, unsigned int *srr,
1854 unsigned int *cks, int frame_len)
1856 int sr, c, br, err, recv_margin;
1857 int min_err = 1000; /* 100% */
1858 int recv_max_margin = 0;
1860 /* Find the combination of sample rate and clock select with the
1861 smallest deviation from the desired baud rate. */
1862 for (sr = 8; sr <= 32; sr++) {
1863 for (c = 0; c <= 3; c++) {
1864 /* integerized formulas from HSCIF documentation */
1865 br = DIV_ROUND_CLOSEST(freq, (sr *
1866 (1 << (2 * c + 1)) * bps)) - 1;
1867 br = clamp(br, 0, 255);
1868 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1869 (1 << (2 * c + 1)) / 1000)) -
1872 * M: Receive margin (%)
1873 * N: Ratio of bit rate to clock (N = sampling rate)
1874 * D: Clock duty (D = 0 to 1.0)
1875 * L: Frame length (L = 9 to 12)
1876 * F: Absolute value of clock frequency deviation
1878 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1879 * (|D - 0.5| / N * (1 + F))|
1880 * NOTE: Usually, treat D for 0.5, F is 0 by this
1883 recv_margin = abs((500 -
1884 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1885 if (abs(min_err) > abs(err)) {
1887 recv_max_margin = recv_margin;
1888 } else if ((min_err == err) &&
1889 (recv_margin > recv_max_margin))
1890 recv_max_margin = recv_margin;
1900 if (min_err == 1000) {
1909 static void sci_reset(struct uart_port *port)
1911 struct plat_sci_reg *reg;
1912 unsigned int status;
1915 status = serial_port_in(port, SCxSR);
1916 } while (!(status & SCxSR_TEND(port)));
1918 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1920 reg = sci_getreg(port, SCFCR);
1922 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1925 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1926 struct ktermios *old)
1928 struct sci_port *s = to_sci_port(port);
1929 struct plat_sci_reg *reg;
1930 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1932 unsigned int srr = 15;
1934 if ((termios->c_cflag & CSIZE) == CS7)
1935 smr_val |= SCSMR_CHR;
1936 if (termios->c_cflag & PARENB)
1937 smr_val |= SCSMR_PE;
1938 if (termios->c_cflag & PARODD)
1939 smr_val |= SCSMR_PE | SCSMR_ODD;
1940 if (termios->c_cflag & CSTOPB)
1941 smr_val |= SCSMR_STOP;
1944 * earlyprintk comes here early on with port->uartclk set to zero.
1945 * the clock framework is not up and running at this point so here
1946 * we assume that 115200 is the maximum baud rate. please note that
1947 * the baud rate is not programmed during earlyprintk - it is assumed
1948 * that the previous boot loader has enabled required clocks and
1949 * setup the baud rate generator hardware for us already.
1951 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1953 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1954 if (likely(baud && port->uartclk)) {
1955 if (s->cfg->type == PORT_HSCIF) {
1956 int frame_len = sci_baud_calc_frame_len(smr_val);
1957 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1960 t = sci_scbrr_calc(s, baud, port->uartclk);
1961 for (cks = 0; t >= 256 && cks <= 3; cks++)
1970 smr_val |= serial_port_in(port, SCSMR) & 3;
1972 uart_update_timeout(port, termios->c_cflag, baud);
1974 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1975 __func__, smr_val, cks, t, s->cfg->scscr);
1978 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1979 serial_port_out(port, SCBRR, t);
1980 reg = sci_getreg(port, HSSRR);
1982 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1983 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1985 serial_port_out(port, SCSMR, smr_val);
1987 sci_init_pins(port, termios->c_cflag);
1989 reg = sci_getreg(port, SCFCR);
1991 unsigned short ctrl = serial_port_in(port, SCFCR);
1993 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1994 if (termios->c_cflag & CRTSCTS)
2001 * As we've done a sci_reset() above, ensure we don't
2002 * interfere with the FIFOs while toggling MCE. As the
2003 * reset values could still be set, simply mask them out.
2005 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2007 serial_port_out(port, SCFCR, ctrl);
2010 serial_port_out(port, SCSCR, s->cfg->scscr);
2012 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2014 * Calculate delay for 2 DMA buffers (4 FIFO).
2015 * See drivers/serial/serial_core.c::uart_update_timeout(). With 10
2016 * bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
2017 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
2018 * Then below we calculate 5 jiffies (20ms) for 2 DMA buffers (4 FIFO
2019 * sizes), but when performing a faster transfer, value obtained by
2020 * this formula is may not enough. Therefore, if value is smaller than
2021 * 20msec, this sets 20msec as timeout of DMA.
2026 /* byte size and parity */
2027 switch (termios->c_cflag & CSIZE) {
2042 if (termios->c_cflag & CSTOPB)
2044 if (termios->c_cflag & PARENB)
2046 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2048 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2049 s->rx_timeout * 1000 / HZ, port->timeout);
2050 if (s->rx_timeout < msecs_to_jiffies(20))
2051 s->rx_timeout = msecs_to_jiffies(20);
2055 if ((termios->c_cflag & CREAD) != 0)
2058 sci_port_disable(s);
2061 static void sci_pm(struct uart_port *port, unsigned int state,
2062 unsigned int oldstate)
2064 struct sci_port *sci_port = to_sci_port(port);
2067 case UART_PM_STATE_OFF:
2068 sci_port_disable(sci_port);
2071 sci_port_enable(sci_port);
2076 static const char *sci_type(struct uart_port *port)
2078 switch (port->type) {
2096 static int sci_remap_port(struct uart_port *port)
2098 struct sci_port *sport = to_sci_port(port);
2101 * Nothing to do if there's already an established membase.
2106 if (port->flags & UPF_IOREMAP) {
2107 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2108 if (unlikely(!port->membase)) {
2109 dev_err(port->dev, "can't remap port#%d\n", port->line);
2114 * For the simple (and majority of) cases where we don't
2115 * need to do any remapping, just cast the cookie
2118 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2124 static void sci_release_port(struct uart_port *port)
2126 struct sci_port *sport = to_sci_port(port);
2128 if (port->flags & UPF_IOREMAP) {
2129 iounmap(port->membase);
2130 port->membase = NULL;
2133 release_mem_region(port->mapbase, sport->reg_size);
2136 static int sci_request_port(struct uart_port *port)
2138 struct resource *res;
2139 struct sci_port *sport = to_sci_port(port);
2142 res = request_mem_region(port->mapbase, sport->reg_size,
2143 dev_name(port->dev));
2144 if (unlikely(res == NULL)) {
2145 dev_err(port->dev, "request_mem_region failed.");
2149 ret = sci_remap_port(port);
2150 if (unlikely(ret != 0)) {
2151 release_resource(res);
2158 static void sci_config_port(struct uart_port *port, int flags)
2160 if (flags & UART_CONFIG_TYPE) {
2161 struct sci_port *sport = to_sci_port(port);
2163 port->type = sport->cfg->type;
2164 sci_request_port(port);
2168 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2170 if (ser->baud_base < 2400)
2171 /* No paper tape reader for Mitch.. */
2177 static struct uart_ops sci_uart_ops = {
2178 .tx_empty = sci_tx_empty,
2179 .set_mctrl = sci_set_mctrl,
2180 .get_mctrl = sci_get_mctrl,
2181 .start_tx = sci_start_tx,
2182 .stop_tx = sci_stop_tx,
2183 .stop_rx = sci_stop_rx,
2184 .break_ctl = sci_break_ctl,
2185 .startup = sci_startup,
2186 .shutdown = sci_shutdown,
2187 .set_termios = sci_set_termios,
2190 .release_port = sci_release_port,
2191 .request_port = sci_request_port,
2192 .config_port = sci_config_port,
2193 .verify_port = sci_verify_port,
2194 #ifdef CONFIG_CONSOLE_POLL
2195 .poll_get_char = sci_poll_get_char,
2196 .poll_put_char = sci_poll_put_char,
2200 static int sci_init_single(struct platform_device *dev,
2201 struct sci_port *sci_port, unsigned int index,
2202 struct plat_sci_port *p, bool early)
2204 struct uart_port *port = &sci_port->port;
2205 const struct resource *res;
2206 unsigned int sampling_rate;
2212 port->ops = &sci_uart_ops;
2213 port->iotype = UPIO_MEM;
2216 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2220 port->mapbase = res->start;
2221 sci_port->reg_size = resource_size(res);
2223 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2224 sci_port->irqs[i] = platform_get_irq(dev, i);
2226 /* The SCI generates several interrupts. They can be muxed together or
2227 * connected to different interrupt lines. In the muxed case only one
2228 * interrupt resource is specified. In the non-muxed case three or four
2229 * interrupt resources are specified, as the BRI interrupt is optional.
2231 if (sci_port->irqs[0] < 0)
2234 if (sci_port->irqs[1] < 0) {
2235 sci_port->irqs[1] = sci_port->irqs[0];
2236 sci_port->irqs[2] = sci_port->irqs[0];
2237 sci_port->irqs[3] = sci_port->irqs[0];
2240 if (p->regtype == SCIx_PROBE_REGTYPE) {
2241 ret = sci_probe_regmap(p);
2248 port->fifosize = 256;
2249 sci_port->overrun_reg = SCxSR;
2250 sci_port->overrun_mask = SCIFA_ORER;
2254 port->fifosize = 128;
2256 sci_port->overrun_reg = SCLSR;
2257 sci_port->overrun_mask = SCLSR_ORER;
2260 port->fifosize = 64;
2261 sci_port->overrun_reg = SCxSR;
2262 sci_port->overrun_mask = SCIFA_ORER;
2266 port->fifosize = 16;
2267 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2268 sci_port->overrun_reg = SCxSR;
2269 sci_port->overrun_mask = SCIFA_ORER;
2272 sci_port->overrun_reg = SCLSR;
2273 sci_port->overrun_mask = SCLSR_ORER;
2279 sci_port->overrun_reg = SCxSR;
2280 sci_port->overrun_mask = SCI_ORER;
2285 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2286 * match the SoC datasheet, this should be investigated. Let platform
2287 * data override the sampling rate for now.
2289 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2293 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2294 if (IS_ERR(sci_port->iclk)) {
2295 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2296 if (IS_ERR(sci_port->iclk)) {
2297 dev_err(&dev->dev, "can't get iclk\n");
2298 return PTR_ERR(sci_port->iclk);
2303 * The function clock is optional, ignore it if we can't
2306 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2307 if (IS_ERR(sci_port->fclk))
2308 sci_port->fclk = NULL;
2310 port->dev = &dev->dev;
2312 pm_runtime_enable(&dev->dev);
2315 sci_port->break_timer.data = (unsigned long)sci_port;
2316 sci_port->break_timer.function = sci_break_timer;
2317 init_timer(&sci_port->break_timer);
2320 * Establish some sensible defaults for the error detection.
2322 sci_port->error_mask = (p->type == PORT_SCI) ?
2323 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2326 * Make the error mask inclusive of overrun detection, if
2329 if (sci_port->overrun_reg == SCxSR)
2330 sci_port->error_mask |= sci_port->overrun_mask;
2332 port->type = p->type;
2333 port->flags = UPF_FIXED_PORT | p->flags;
2334 port->regshift = p->regshift;
2337 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2338 * for the multi-IRQ ports, which is where we are primarily
2339 * concerned with the shutdown path synchronization.
2341 * For the muxed case there's nothing more to do.
2343 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2346 port->serial_in = sci_serial_in;
2347 port->serial_out = sci_serial_out;
2349 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2350 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2351 p->dma_slave_tx, p->dma_slave_rx);
2356 static void sci_cleanup_single(struct sci_port *port)
2358 clk_put(port->iclk);
2359 clk_put(port->fclk);
2361 pm_runtime_disable(port->port.dev);
2364 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2365 static void serial_console_putchar(struct uart_port *port, int ch)
2367 sci_poll_put_char(port, ch);
2371 * Print a string to the serial port trying not to disturb
2372 * any possible real use of the port...
2374 static void serial_console_write(struct console *co, const char *s,
2377 struct sci_port *sci_port = &sci_ports[co->index];
2378 struct uart_port *port = &sci_port->port;
2379 unsigned short bits, ctrl;
2380 unsigned long flags;
2383 local_irq_save(flags);
2386 else if (oops_in_progress)
2387 locked = spin_trylock(&port->lock);
2389 spin_lock(&port->lock);
2391 /* first save the SCSCR then disable the interrupts */
2392 ctrl = serial_port_in(port, SCSCR);
2393 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2395 uart_console_write(port, s, count, serial_console_putchar);
2397 /* wait until fifo is empty and last bit has been transmitted */
2398 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2399 while ((serial_port_in(port, SCxSR) & bits) != bits)
2402 /* restore the SCSCR */
2403 serial_port_out(port, SCSCR, ctrl);
2406 spin_unlock(&port->lock);
2407 local_irq_restore(flags);
2410 static int serial_console_setup(struct console *co, char *options)
2412 struct sci_port *sci_port;
2413 struct uart_port *port;
2421 * Refuse to handle any bogus ports.
2423 if (co->index < 0 || co->index >= SCI_NPORTS)
2426 sci_port = &sci_ports[co->index];
2427 port = &sci_port->port;
2430 * Refuse to handle uninitialized ports.
2435 ret = sci_remap_port(port);
2436 if (unlikely(ret != 0))
2440 uart_parse_options(options, &baud, &parity, &bits, &flow);
2442 return uart_set_options(port, co, baud, parity, bits, flow);
2445 static struct console serial_console = {
2447 .device = uart_console_device,
2448 .write = serial_console_write,
2449 .setup = serial_console_setup,
2450 .flags = CON_PRINTBUFFER,
2452 .data = &sci_uart_driver,
2455 static struct console early_serial_console = {
2456 .name = "early_ttySC",
2457 .write = serial_console_write,
2458 .flags = CON_PRINTBUFFER,
2462 static char early_serial_buf[32];
2464 static int sci_probe_earlyprintk(struct platform_device *pdev)
2466 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2468 if (early_serial_console.data)
2471 early_serial_console.index = pdev->id;
2473 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2475 serial_console_setup(&early_serial_console, early_serial_buf);
2477 if (!strstr(early_serial_buf, "keep"))
2478 early_serial_console.flags |= CON_BOOT;
2480 register_console(&early_serial_console);
2484 #define SCI_CONSOLE (&serial_console)
2487 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2492 #define SCI_CONSOLE NULL
2494 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2496 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2498 static struct uart_driver sci_uart_driver = {
2499 .owner = THIS_MODULE,
2500 .driver_name = "sci",
2501 .dev_name = "ttySC",
2503 .minor = SCI_MINOR_START,
2505 .cons = SCI_CONSOLE,
2508 static int sci_remove(struct platform_device *dev)
2510 struct sci_port *port = platform_get_drvdata(dev);
2512 cpufreq_unregister_notifier(&port->freq_transition,
2513 CPUFREQ_TRANSITION_NOTIFIER);
2515 uart_remove_one_port(&sci_uart_driver, &port->port);
2517 sci_cleanup_single(port);
2522 struct sci_port_info {
2524 unsigned int regtype;
2527 static const struct of_device_id of_sci_match[] = {
2529 .compatible = "renesas,scif",
2530 .data = &(const struct sci_port_info) {
2532 .regtype = SCIx_SH4_SCIF_REGTYPE,
2535 .compatible = "renesas,scifa",
2536 .data = &(const struct sci_port_info) {
2538 .regtype = SCIx_SCIFA_REGTYPE,
2541 .compatible = "renesas,scifb",
2542 .data = &(const struct sci_port_info) {
2544 .regtype = SCIx_SCIFB_REGTYPE,
2547 .compatible = "renesas,hscif",
2548 .data = &(const struct sci_port_info) {
2550 .regtype = SCIx_HSCIF_REGTYPE,
2553 .compatible = "renesas,sci",
2554 .data = &(const struct sci_port_info) {
2556 .regtype = SCIx_SCI_REGTYPE,
2562 MODULE_DEVICE_TABLE(of, of_sci_match);
2564 static struct plat_sci_port *
2565 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2567 struct device_node *np = pdev->dev.of_node;
2568 const struct of_device_id *match;
2569 const struct sci_port_info *info;
2570 struct plat_sci_port *p;
2573 if (!IS_ENABLED(CONFIG_OF) || !np)
2576 match = of_match_node(of_sci_match, pdev->dev.of_node);
2582 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2584 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2588 /* Get the line number for the aliases node. */
2589 id = of_alias_get_id(np, "serial");
2591 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2597 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2598 p->type = info->type;
2599 p->regtype = info->regtype;
2600 p->scscr = SCSCR_RE | SCSCR_TE;
2605 static int sci_probe_single(struct platform_device *dev,
2607 struct plat_sci_port *p,
2608 struct sci_port *sciport)
2613 if (unlikely(index >= SCI_NPORTS)) {
2614 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2615 index+1, SCI_NPORTS);
2616 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2620 ret = sci_init_single(dev, sciport, index, p, false);
2624 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2626 sci_cleanup_single(sciport);
2633 static int sci_probe(struct platform_device *dev)
2635 struct plat_sci_port *p;
2636 struct sci_port *sp;
2637 unsigned int dev_id;
2641 * If we've come here via earlyprintk initialization, head off to
2642 * the special early probe. We don't have sufficient device state
2643 * to make it beyond this yet.
2645 if (is_early_platform_device(dev))
2646 return sci_probe_earlyprintk(dev);
2648 if (dev->dev.of_node) {
2649 p = sci_parse_dt(dev, &dev_id);
2653 p = dev->dev.platform_data;
2655 dev_err(&dev->dev, "no platform data supplied\n");
2662 sp = &sci_ports[dev_id];
2663 platform_set_drvdata(dev, sp);
2665 ret = sci_probe_single(dev, dev_id, p, sp);
2669 sp->freq_transition.notifier_call = sci_notifier;
2671 ret = cpufreq_register_notifier(&sp->freq_transition,
2672 CPUFREQ_TRANSITION_NOTIFIER);
2673 if (unlikely(ret < 0)) {
2674 uart_remove_one_port(&sci_uart_driver, &sp->port);
2675 sci_cleanup_single(sp);
2679 #ifdef CONFIG_SH_STANDARD_BIOS
2680 sh_bios_gdb_detach();
2686 static __maybe_unused int sci_suspend(struct device *dev)
2688 struct sci_port *sport = dev_get_drvdata(dev);
2691 uart_suspend_port(&sci_uart_driver, &sport->port);
2696 static __maybe_unused int sci_resume(struct device *dev)
2698 struct sci_port *sport = dev_get_drvdata(dev);
2701 uart_resume_port(&sci_uart_driver, &sport->port);
2706 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2708 static struct platform_driver sci_driver = {
2710 .remove = sci_remove,
2713 .pm = &sci_dev_pm_ops,
2714 .of_match_table = of_match_ptr(of_sci_match),
2718 static int __init sci_init(void)
2722 pr_info("%s\n", banner);
2724 ret = uart_register_driver(&sci_uart_driver);
2725 if (likely(ret == 0)) {
2726 ret = platform_driver_register(&sci_driver);
2728 uart_unregister_driver(&sci_uart_driver);
2734 static void __exit sci_exit(void)
2736 platform_driver_unregister(&sci_driver);
2737 uart_unregister_driver(&sci_uart_driver);
2740 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2741 early_platform_init_buffer("earlyprintk", &sci_driver,
2742 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2744 module_init(sci_init);
2745 module_exit(sci_exit);
2747 MODULE_LICENSE("GPL");
2748 MODULE_ALIAS("platform:sh-sci");
2749 MODULE_AUTHOR("Paul Mundt");
2750 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");