2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
7 * based off of the old drivers/char/sh-sci.c by:
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
41 #include <linux/notifier.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
57 #include <asm/sh_bios.h>
62 /* Offsets into the sci_port->irqs array */
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
80 struct uart_port port;
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 unsigned int overrun_reg;
85 unsigned int overrun_mask;
86 unsigned int error_mask;
87 unsigned int error_clear;
88 unsigned int sampling_rate;
89 resource_size_t reg_size;
92 struct timer_list break_timer;
100 int irqs[SCIx_NR_IRQS];
101 char *irqstr[SCIx_NR_IRQS];
103 struct dma_chan *chan_tx;
104 struct dma_chan *chan_rx;
106 #ifdef CONFIG_SERIAL_SH_SCI_DMA
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 dma_addr_t tx_dma_addr;
111 unsigned int tx_dma_len;
112 struct scatterlist sg_rx[2];
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
122 struct notifier_block freq_transition;
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
138 return container_of(uart, struct sci_port, port);
141 struct plat_sci_reg {
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
148 static const struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
154 * Common SCI definitions, dependent on the port's regshift
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
171 [SCPCR] = sci_reg_invalid,
172 [SCPDR] = sci_reg_invalid,
176 * Common definitions for legacy IrDA ports, dependent on
179 [SCIx_IRDA_REGTYPE] = {
180 [SCSMR] = { 0x00, 8 },
181 [SCBRR] = { 0x01, 8 },
182 [SCSCR] = { 0x02, 8 },
183 [SCxTDR] = { 0x03, 8 },
184 [SCxSR] = { 0x04, 8 },
185 [SCxRDR] = { 0x05, 8 },
186 [SCFCR] = { 0x06, 8 },
187 [SCFDR] = { 0x07, 16 },
188 [SCTFDR] = sci_reg_invalid,
189 [SCRFDR] = sci_reg_invalid,
190 [SCSPTR] = sci_reg_invalid,
191 [SCLSR] = sci_reg_invalid,
192 [HSSRR] = sci_reg_invalid,
193 [SCPCR] = sci_reg_invalid,
194 [SCPDR] = sci_reg_invalid,
198 * Common SCIFA definitions.
200 [SCIx_SCIFA_REGTYPE] = {
201 [SCSMR] = { 0x00, 16 },
202 [SCBRR] = { 0x04, 8 },
203 [SCSCR] = { 0x08, 16 },
204 [SCxTDR] = { 0x20, 8 },
205 [SCxSR] = { 0x14, 16 },
206 [SCxRDR] = { 0x24, 8 },
207 [SCFCR] = { 0x18, 16 },
208 [SCFDR] = { 0x1c, 16 },
209 [SCTFDR] = sci_reg_invalid,
210 [SCRFDR] = sci_reg_invalid,
211 [SCSPTR] = sci_reg_invalid,
212 [SCLSR] = sci_reg_invalid,
213 [HSSRR] = sci_reg_invalid,
214 [SCPCR] = { 0x30, 16 },
215 [SCPDR] = { 0x34, 16 },
219 * Common SCIFB definitions.
221 [SCIx_SCIFB_REGTYPE] = {
222 [SCSMR] = { 0x00, 16 },
223 [SCBRR] = { 0x04, 8 },
224 [SCSCR] = { 0x08, 16 },
225 [SCxTDR] = { 0x40, 8 },
226 [SCxSR] = { 0x14, 16 },
227 [SCxRDR] = { 0x60, 8 },
228 [SCFCR] = { 0x18, 16 },
229 [SCFDR] = sci_reg_invalid,
230 [SCTFDR] = { 0x38, 16 },
231 [SCRFDR] = { 0x3c, 16 },
232 [SCSPTR] = sci_reg_invalid,
233 [SCLSR] = sci_reg_invalid,
234 [HSSRR] = sci_reg_invalid,
235 [SCPCR] = { 0x30, 16 },
236 [SCPDR] = { 0x34, 16 },
240 * Common SH-2(A) SCIF definitions for ports with FIFO data
243 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
244 [SCSMR] = { 0x00, 16 },
245 [SCBRR] = { 0x04, 8 },
246 [SCSCR] = { 0x08, 16 },
247 [SCxTDR] = { 0x0c, 8 },
248 [SCxSR] = { 0x10, 16 },
249 [SCxRDR] = { 0x14, 8 },
250 [SCFCR] = { 0x18, 16 },
251 [SCFDR] = { 0x1c, 16 },
252 [SCTFDR] = sci_reg_invalid,
253 [SCRFDR] = sci_reg_invalid,
254 [SCSPTR] = { 0x20, 16 },
255 [SCLSR] = { 0x24, 16 },
256 [HSSRR] = sci_reg_invalid,
257 [SCPCR] = sci_reg_invalid,
258 [SCPDR] = sci_reg_invalid,
262 * Common SH-3 SCIF definitions.
264 [SCIx_SH3_SCIF_REGTYPE] = {
265 [SCSMR] = { 0x00, 8 },
266 [SCBRR] = { 0x02, 8 },
267 [SCSCR] = { 0x04, 8 },
268 [SCxTDR] = { 0x06, 8 },
269 [SCxSR] = { 0x08, 16 },
270 [SCxRDR] = { 0x0a, 8 },
271 [SCFCR] = { 0x0c, 8 },
272 [SCFDR] = { 0x0e, 16 },
273 [SCTFDR] = sci_reg_invalid,
274 [SCRFDR] = sci_reg_invalid,
275 [SCSPTR] = sci_reg_invalid,
276 [SCLSR] = sci_reg_invalid,
277 [HSSRR] = sci_reg_invalid,
278 [SCPCR] = sci_reg_invalid,
279 [SCPDR] = sci_reg_invalid,
283 * Common SH-4(A) SCIF(B) definitions.
285 [SCIx_SH4_SCIF_REGTYPE] = {
286 [SCSMR] = { 0x00, 16 },
287 [SCBRR] = { 0x04, 8 },
288 [SCSCR] = { 0x08, 16 },
289 [SCxTDR] = { 0x0c, 8 },
290 [SCxSR] = { 0x10, 16 },
291 [SCxRDR] = { 0x14, 8 },
292 [SCFCR] = { 0x18, 16 },
293 [SCFDR] = { 0x1c, 16 },
294 [SCTFDR] = sci_reg_invalid,
295 [SCRFDR] = sci_reg_invalid,
296 [SCSPTR] = { 0x20, 16 },
297 [SCLSR] = { 0x24, 16 },
298 [HSSRR] = sci_reg_invalid,
299 [SCPCR] = sci_reg_invalid,
300 [SCPDR] = sci_reg_invalid,
304 * Common HSCIF definitions.
306 [SCIx_HSCIF_REGTYPE] = {
307 [SCSMR] = { 0x00, 16 },
308 [SCBRR] = { 0x04, 8 },
309 [SCSCR] = { 0x08, 16 },
310 [SCxTDR] = { 0x0c, 8 },
311 [SCxSR] = { 0x10, 16 },
312 [SCxRDR] = { 0x14, 8 },
313 [SCFCR] = { 0x18, 16 },
314 [SCFDR] = { 0x1c, 16 },
315 [SCTFDR] = sci_reg_invalid,
316 [SCRFDR] = sci_reg_invalid,
317 [SCSPTR] = { 0x20, 16 },
318 [SCLSR] = { 0x24, 16 },
319 [HSSRR] = { 0x40, 16 },
320 [SCPCR] = sci_reg_invalid,
321 [SCPDR] = sci_reg_invalid,
325 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
328 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
329 [SCSMR] = { 0x00, 16 },
330 [SCBRR] = { 0x04, 8 },
331 [SCSCR] = { 0x08, 16 },
332 [SCxTDR] = { 0x0c, 8 },
333 [SCxSR] = { 0x10, 16 },
334 [SCxRDR] = { 0x14, 8 },
335 [SCFCR] = { 0x18, 16 },
336 [SCFDR] = { 0x1c, 16 },
337 [SCTFDR] = sci_reg_invalid,
338 [SCRFDR] = sci_reg_invalid,
339 [SCSPTR] = sci_reg_invalid,
340 [SCLSR] = { 0x24, 16 },
341 [HSSRR] = sci_reg_invalid,
342 [SCPCR] = sci_reg_invalid,
343 [SCPDR] = sci_reg_invalid,
347 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
350 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
351 [SCSMR] = { 0x00, 16 },
352 [SCBRR] = { 0x04, 8 },
353 [SCSCR] = { 0x08, 16 },
354 [SCxTDR] = { 0x0c, 8 },
355 [SCxSR] = { 0x10, 16 },
356 [SCxRDR] = { 0x14, 8 },
357 [SCFCR] = { 0x18, 16 },
358 [SCFDR] = { 0x1c, 16 },
359 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
360 [SCRFDR] = { 0x20, 16 },
361 [SCSPTR] = { 0x24, 16 },
362 [SCLSR] = { 0x28, 16 },
363 [HSSRR] = sci_reg_invalid,
364 [SCPCR] = sci_reg_invalid,
365 [SCPDR] = sci_reg_invalid,
369 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
372 [SCIx_SH7705_SCIF_REGTYPE] = {
373 [SCSMR] = { 0x00, 16 },
374 [SCBRR] = { 0x04, 8 },
375 [SCSCR] = { 0x08, 16 },
376 [SCxTDR] = { 0x20, 8 },
377 [SCxSR] = { 0x14, 16 },
378 [SCxRDR] = { 0x24, 8 },
379 [SCFCR] = { 0x18, 16 },
380 [SCFDR] = { 0x1c, 16 },
381 [SCTFDR] = sci_reg_invalid,
382 [SCRFDR] = sci_reg_invalid,
383 [SCSPTR] = sci_reg_invalid,
384 [SCLSR] = sci_reg_invalid,
385 [HSSRR] = sci_reg_invalid,
386 [SCPCR] = sci_reg_invalid,
387 [SCPDR] = sci_reg_invalid,
391 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
394 * The "offset" here is rather misleading, in that it refers to an enum
395 * value relative to the port mapping rather than the fixed offset
396 * itself, which needs to be manually retrieved from the platform's
397 * register map for the given port.
399 static unsigned int sci_serial_in(struct uart_port *p, int offset)
401 const struct plat_sci_reg *reg = sci_getreg(p, offset);
404 return ioread8(p->membase + (reg->offset << p->regshift));
405 else if (reg->size == 16)
406 return ioread16(p->membase + (reg->offset << p->regshift));
408 WARN(1, "Invalid register access\n");
413 static void sci_serial_out(struct uart_port *p, int offset, int value)
415 const struct plat_sci_reg *reg = sci_getreg(p, offset);
418 iowrite8(value, p->membase + (reg->offset << p->regshift));
419 else if (reg->size == 16)
420 iowrite16(value, p->membase + (reg->offset << p->regshift));
422 WARN(1, "Invalid register access\n");
425 static int sci_probe_regmap(struct plat_sci_port *cfg)
429 cfg->regtype = SCIx_SCI_REGTYPE;
432 cfg->regtype = SCIx_IRDA_REGTYPE;
435 cfg->regtype = SCIx_SCIFA_REGTYPE;
438 cfg->regtype = SCIx_SCIFB_REGTYPE;
442 * The SH-4 is a bit of a misnomer here, although that's
443 * where this particular port layout originated. This
444 * configuration (or some slight variation thereof)
445 * remains the dominant model for all SCIFs.
447 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
450 cfg->regtype = SCIx_HSCIF_REGTYPE;
453 pr_err("Can't probe register map for given port\n");
460 static void sci_port_enable(struct sci_port *sci_port)
462 if (!sci_port->port.dev)
465 pm_runtime_get_sync(sci_port->port.dev);
467 clk_prepare_enable(sci_port->iclk);
468 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
469 clk_prepare_enable(sci_port->fclk);
472 static void sci_port_disable(struct sci_port *sci_port)
474 if (!sci_port->port.dev)
477 /* Cancel the break timer to ensure that the timer handler will not try
478 * to access the hardware with clocks and power disabled. Reset the
479 * break flag to make the break debouncing state machine ready for the
482 del_timer_sync(&sci_port->break_timer);
483 sci_port->break_flag = 0;
485 clk_disable_unprepare(sci_port->fclk);
486 clk_disable_unprepare(sci_port->iclk);
488 pm_runtime_put_sync(sci_port->port.dev);
491 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
493 if (port->type == PORT_SCI) {
494 /* Just store the mask */
495 serial_port_out(port, SCxSR, mask);
496 } else if (to_sci_port(port)->overrun_mask == SCIFA_ORER) {
497 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
498 /* Only clear the status bits we want to clear */
499 serial_port_out(port, SCxSR,
500 serial_port_in(port, SCxSR) & mask);
502 /* Store the mask, clear parity/framing errors */
503 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
507 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
509 #ifdef CONFIG_CONSOLE_POLL
510 static int sci_poll_get_char(struct uart_port *port)
512 unsigned short status;
516 status = serial_port_in(port, SCxSR);
517 if (status & SCxSR_ERRORS(port)) {
518 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
524 if (!(status & SCxSR_RDxF(port)))
527 c = serial_port_in(port, SCxRDR);
530 serial_port_in(port, SCxSR);
531 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
537 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
539 unsigned short status;
542 status = serial_port_in(port, SCxSR);
543 } while (!(status & SCxSR_TDxE(port)));
545 serial_port_out(port, SCxTDR, c);
546 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
548 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
550 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
552 struct sci_port *s = to_sci_port(port);
553 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
556 * Use port-specific handler if provided.
558 if (s->cfg->ops && s->cfg->ops->init_pins) {
559 s->cfg->ops->init_pins(port, cflag);
564 * For the generic path SCSPTR is necessary. Bail out if that's
570 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
571 ((!(cflag & CRTSCTS)))) {
572 unsigned short status;
574 status = serial_port_in(port, SCSPTR);
575 status &= ~SCSPTR_CTSIO;
576 status |= SCSPTR_RTSIO;
577 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
581 static int sci_txfill(struct uart_port *port)
583 const struct plat_sci_reg *reg;
585 reg = sci_getreg(port, SCTFDR);
587 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
589 reg = sci_getreg(port, SCFDR);
591 return serial_port_in(port, SCFDR) >> 8;
593 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
596 static int sci_txroom(struct uart_port *port)
598 return port->fifosize - sci_txfill(port);
601 static int sci_rxfill(struct uart_port *port)
603 const struct plat_sci_reg *reg;
605 reg = sci_getreg(port, SCRFDR);
607 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
609 reg = sci_getreg(port, SCFDR);
611 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
613 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
617 * SCI helper for checking the state of the muxed port/RXD pins.
619 static inline int sci_rxd_in(struct uart_port *port)
621 struct sci_port *s = to_sci_port(port);
623 if (s->cfg->port_reg <= 0)
626 /* Cast for ARM damage */
627 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
630 /* ********************************************************************** *
631 * the interrupt related routines *
632 * ********************************************************************** */
634 static void sci_transmit_chars(struct uart_port *port)
636 struct circ_buf *xmit = &port->state->xmit;
637 unsigned int stopped = uart_tx_stopped(port);
638 unsigned short status;
642 status = serial_port_in(port, SCxSR);
643 if (!(status & SCxSR_TDxE(port))) {
644 ctrl = serial_port_in(port, SCSCR);
645 if (uart_circ_empty(xmit))
649 serial_port_out(port, SCSCR, ctrl);
653 count = sci_txroom(port);
661 } else if (!uart_circ_empty(xmit) && !stopped) {
662 c = xmit->buf[xmit->tail];
663 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
668 serial_port_out(port, SCxTDR, c);
671 } while (--count > 0);
673 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
675 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
676 uart_write_wakeup(port);
677 if (uart_circ_empty(xmit)) {
680 ctrl = serial_port_in(port, SCSCR);
682 if (port->type != PORT_SCI) {
683 serial_port_in(port, SCxSR); /* Dummy read */
684 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
688 serial_port_out(port, SCSCR, ctrl);
692 /* On SH3, SCIF may read end-of-break as a space->mark char */
693 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
695 static void sci_receive_chars(struct uart_port *port)
697 struct sci_port *sci_port = to_sci_port(port);
698 struct tty_port *tport = &port->state->port;
699 int i, count, copied = 0;
700 unsigned short status;
703 status = serial_port_in(port, SCxSR);
704 if (!(status & SCxSR_RDxF(port)))
708 /* Don't copy more bytes than there is room for in the buffer */
709 count = tty_buffer_request_room(tport, sci_rxfill(port));
711 /* If for any reason we can't copy more data, we're done! */
715 if (port->type == PORT_SCI) {
716 char c = serial_port_in(port, SCxRDR);
717 if (uart_handle_sysrq_char(port, c) ||
718 sci_port->break_flag)
721 tty_insert_flip_char(tport, c, TTY_NORMAL);
723 for (i = 0; i < count; i++) {
724 char c = serial_port_in(port, SCxRDR);
726 status = serial_port_in(port, SCxSR);
727 #if defined(CONFIG_CPU_SH3)
728 /* Skip "chars" during break */
729 if (sci_port->break_flag) {
731 (status & SCxSR_FER(port))) {
736 /* Nonzero => end-of-break */
737 dev_dbg(port->dev, "debounce<%02x>\n", c);
738 sci_port->break_flag = 0;
745 #endif /* CONFIG_CPU_SH3 */
746 if (uart_handle_sysrq_char(port, c)) {
751 /* Store data and status */
752 if (status & SCxSR_FER(port)) {
754 port->icount.frame++;
755 dev_notice(port->dev, "frame error\n");
756 } else if (status & SCxSR_PER(port)) {
758 port->icount.parity++;
759 dev_notice(port->dev, "parity error\n");
763 tty_insert_flip_char(tport, c, flag);
767 serial_port_in(port, SCxSR); /* dummy read */
768 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
771 port->icount.rx += count;
775 /* Tell the rest of the system the news. New characters! */
776 tty_flip_buffer_push(tport);
778 serial_port_in(port, SCxSR); /* dummy read */
779 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
783 #define SCI_BREAK_JIFFIES (HZ/20)
786 * The sci generates interrupts during the break,
787 * 1 per millisecond or so during the break period, for 9600 baud.
788 * So dont bother disabling interrupts.
789 * But dont want more than 1 break event.
790 * Use a kernel timer to periodically poll the rx line until
791 * the break is finished.
793 static inline void sci_schedule_break_timer(struct sci_port *port)
795 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
798 /* Ensure that two consecutive samples find the break over. */
799 static void sci_break_timer(unsigned long data)
801 struct sci_port *port = (struct sci_port *)data;
803 if (sci_rxd_in(&port->port) == 0) {
804 port->break_flag = 1;
805 sci_schedule_break_timer(port);
806 } else if (port->break_flag == 1) {
808 port->break_flag = 2;
809 sci_schedule_break_timer(port);
811 port->break_flag = 0;
814 static int sci_handle_errors(struct uart_port *port)
817 unsigned short status = serial_port_in(port, SCxSR);
818 struct tty_port *tport = &port->state->port;
819 struct sci_port *s = to_sci_port(port);
821 /* Handle overruns */
822 if (status & s->overrun_mask) {
823 port->icount.overrun++;
826 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
829 dev_notice(port->dev, "overrun error\n");
832 if (status & SCxSR_FER(port)) {
833 if (sci_rxd_in(port) == 0) {
834 /* Notify of BREAK */
835 struct sci_port *sci_port = to_sci_port(port);
837 if (!sci_port->break_flag) {
840 sci_port->break_flag = 1;
841 sci_schedule_break_timer(sci_port);
843 /* Do sysrq handling. */
844 if (uart_handle_break(port))
847 dev_dbg(port->dev, "BREAK detected\n");
849 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
855 port->icount.frame++;
857 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
860 dev_notice(port->dev, "frame error\n");
864 if (status & SCxSR_PER(port)) {
866 port->icount.parity++;
868 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
871 dev_notice(port->dev, "parity error\n");
875 tty_flip_buffer_push(tport);
880 static int sci_handle_fifo_overrun(struct uart_port *port)
882 struct tty_port *tport = &port->state->port;
883 struct sci_port *s = to_sci_port(port);
884 const struct plat_sci_reg *reg;
888 reg = sci_getreg(port, s->overrun_reg);
892 status = serial_port_in(port, s->overrun_reg);
893 if (status & s->overrun_mask) {
894 status &= ~s->overrun_mask;
895 serial_port_out(port, s->overrun_reg, status);
897 port->icount.overrun++;
899 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
900 tty_flip_buffer_push(tport);
902 dev_dbg(port->dev, "overrun error\n");
909 static int sci_handle_breaks(struct uart_port *port)
912 unsigned short status = serial_port_in(port, SCxSR);
913 struct tty_port *tport = &port->state->port;
914 struct sci_port *s = to_sci_port(port);
916 if (uart_handle_break(port))
919 if (!s->break_flag && status & SCxSR_BRK(port)) {
920 #if defined(CONFIG_CPU_SH3)
927 /* Notify of BREAK */
928 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
931 dev_dbg(port->dev, "BREAK detected\n");
935 tty_flip_buffer_push(tport);
937 copied += sci_handle_fifo_overrun(port);
942 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
944 #ifdef CONFIG_SERIAL_SH_SCI_DMA
945 struct uart_port *port = ptr;
946 struct sci_port *s = to_sci_port(port);
949 u16 scr = serial_port_in(port, SCSCR);
950 u16 ssr = serial_port_in(port, SCxSR);
952 /* Disable future Rx interrupts */
953 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
954 disable_irq_nosync(irq);
959 serial_port_out(port, SCSCR, scr);
960 /* Clear current interrupt */
961 serial_port_out(port, SCxSR,
962 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
963 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
964 jiffies, s->rx_timeout);
965 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
971 /* I think sci_receive_chars has to be called irrespective
972 * of whether the I_IXOFF is set, otherwise, how is the interrupt
975 sci_receive_chars(ptr);
980 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
982 struct uart_port *port = ptr;
985 spin_lock_irqsave(&port->lock, flags);
986 sci_transmit_chars(port);
987 spin_unlock_irqrestore(&port->lock, flags);
992 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
994 struct uart_port *port = ptr;
997 if (port->type == PORT_SCI) {
998 if (sci_handle_errors(port)) {
999 /* discard character in rx buffer */
1000 serial_port_in(port, SCxSR);
1001 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1004 sci_handle_fifo_overrun(port);
1005 sci_rx_interrupt(irq, ptr);
1008 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1010 /* Kick the transmission */
1011 sci_tx_interrupt(irq, ptr);
1016 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1018 struct uart_port *port = ptr;
1021 sci_handle_breaks(port);
1022 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1027 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
1030 * Not all ports (such as SCIFA) will support REIE. Rather than
1031 * special-casing the port type, we check the port initialization
1032 * IRQ enable mask to see whether the IRQ is desired at all. If
1033 * it's unset, it's logically inferred that there's no point in
1036 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
1039 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1041 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1042 struct uart_port *port = ptr;
1043 struct sci_port *s = to_sci_port(port);
1044 irqreturn_t ret = IRQ_NONE;
1046 ssr_status = serial_port_in(port, SCxSR);
1047 scr_status = serial_port_in(port, SCSCR);
1048 if (s->overrun_reg == SCxSR)
1049 orer_status = ssr_status;
1051 if (sci_getreg(port, s->overrun_reg)->size)
1052 orer_status = serial_port_in(port, s->overrun_reg);
1055 err_enabled = scr_status & port_rx_irq_mask(port);
1058 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1060 ret = sci_tx_interrupt(irq, ptr);
1063 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1066 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1067 (scr_status & SCSCR_RIE))
1068 ret = sci_rx_interrupt(irq, ptr);
1070 /* Error Interrupt */
1071 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1072 ret = sci_er_interrupt(irq, ptr);
1074 /* Break Interrupt */
1075 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1076 ret = sci_br_interrupt(irq, ptr);
1078 /* Overrun Interrupt */
1079 if (orer_status & s->overrun_mask) {
1080 sci_handle_fifo_overrun(port);
1088 * Here we define a transition notifier so that we can update all of our
1089 * ports' baud rate when the peripheral clock changes.
1091 static int sci_notifier(struct notifier_block *self,
1092 unsigned long phase, void *p)
1094 struct sci_port *sci_port;
1095 unsigned long flags;
1097 sci_port = container_of(self, struct sci_port, freq_transition);
1099 if (phase == CPUFREQ_POSTCHANGE) {
1100 struct uart_port *port = &sci_port->port;
1102 spin_lock_irqsave(&port->lock, flags);
1103 port->uartclk = clk_get_rate(sci_port->iclk);
1104 spin_unlock_irqrestore(&port->lock, flags);
1110 static const struct sci_irq_desc {
1112 irq_handler_t handler;
1113 } sci_irq_desc[] = {
1115 * Split out handlers, the default case.
1119 .handler = sci_er_interrupt,
1124 .handler = sci_rx_interrupt,
1129 .handler = sci_tx_interrupt,
1134 .handler = sci_br_interrupt,
1138 * Special muxed handler.
1142 .handler = sci_mpxed_interrupt,
1146 static int sci_request_irq(struct sci_port *port)
1148 struct uart_port *up = &port->port;
1151 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1152 const struct sci_irq_desc *desc;
1155 if (SCIx_IRQ_IS_MUXED(port)) {
1159 irq = port->irqs[i];
1162 * Certain port types won't support all of the
1163 * available interrupt sources.
1165 if (unlikely(irq < 0))
1169 desc = sci_irq_desc + i;
1170 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1171 dev_name(up->dev), desc->desc);
1172 if (!port->irqstr[j])
1175 ret = request_irq(irq, desc->handler, up->irqflags,
1176 port->irqstr[j], port);
1177 if (unlikely(ret)) {
1178 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1187 free_irq(port->irqs[i], port);
1191 kfree(port->irqstr[j]);
1196 static void sci_free_irq(struct sci_port *port)
1201 * Intentionally in reverse order so we iterate over the muxed
1204 for (i = 0; i < SCIx_NR_IRQS; i++) {
1205 int irq = port->irqs[i];
1208 * Certain port types won't support all of the available
1209 * interrupt sources.
1211 if (unlikely(irq < 0))
1214 free_irq(port->irqs[i], port);
1215 kfree(port->irqstr[i]);
1217 if (SCIx_IRQ_IS_MUXED(port)) {
1218 /* If there's only one IRQ, we're done. */
1224 static unsigned int sci_tx_empty(struct uart_port *port)
1226 unsigned short status = serial_port_in(port, SCxSR);
1227 unsigned short in_tx_fifo = sci_txfill(port);
1229 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1233 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1234 * CTS/RTS is supported in hardware by at least one port and controlled
1235 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1236 * handled via the ->init_pins() op, which is a bit of a one-way street,
1237 * lacking any ability to defer pin control -- this will later be
1238 * converted over to the GPIO framework).
1240 * Other modes (such as loopback) are supported generically on certain
1241 * port types, but not others. For these it's sufficient to test for the
1242 * existence of the support register and simply ignore the port type.
1244 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1246 if (mctrl & TIOCM_LOOP) {
1247 const struct plat_sci_reg *reg;
1250 * Standard loopback mode for SCFCR ports.
1252 reg = sci_getreg(port, SCFCR);
1254 serial_port_out(port, SCFCR,
1255 serial_port_in(port, SCFCR) |
1260 static unsigned int sci_get_mctrl(struct uart_port *port)
1263 * CTS/RTS is handled in hardware when supported, while nothing
1264 * else is wired up. Keep it simple and simply assert DSR/CAR.
1266 return TIOCM_DSR | TIOCM_CAR;
1269 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1270 static void sci_dma_tx_complete(void *arg)
1272 struct sci_port *s = arg;
1273 struct uart_port *port = &s->port;
1274 struct circ_buf *xmit = &port->state->xmit;
1275 unsigned long flags;
1277 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1279 spin_lock_irqsave(&port->lock, flags);
1281 xmit->tail += s->tx_dma_len;
1282 xmit->tail &= UART_XMIT_SIZE - 1;
1284 port->icount.tx += s->tx_dma_len;
1286 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1287 uart_write_wakeup(port);
1289 if (!uart_circ_empty(xmit)) {
1291 schedule_work(&s->work_tx);
1293 s->cookie_tx = -EINVAL;
1294 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1295 u16 ctrl = serial_port_in(port, SCSCR);
1296 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1300 spin_unlock_irqrestore(&port->lock, flags);
1303 /* Locking: called with port lock held */
1304 static int sci_dma_rx_push(struct sci_port *s, struct scatterlist *sg,
1307 struct uart_port *port = &s->port;
1308 struct tty_port *tport = &port->state->port;
1311 room = tty_buffer_request_room(tport, count);
1314 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1319 for (i = 0; i < room; i++)
1320 tty_insert_flip_char(tport, ((u8 *)sg_virt(sg))[i], TTY_NORMAL);
1322 port->icount.rx += room;
1327 static int sci_dma_rx_find_active(struct sci_port *s)
1331 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1332 if (s->active_rx == s->cookie_rx[i])
1335 dev_err(s->port.dev, "%s: Rx cookie %d not found!\n", __func__,
1340 static void sci_dma_rx_complete(void *arg)
1342 struct sci_port *s = arg;
1343 struct uart_port *port = &s->port;
1344 unsigned long flags;
1345 int active, count = 0;
1347 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1350 spin_lock_irqsave(&port->lock, flags);
1352 active = sci_dma_rx_find_active(s);
1354 count = sci_dma_rx_push(s, &s->sg_rx[active], s->buf_len_rx);
1356 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1358 spin_unlock_irqrestore(&port->lock, flags);
1361 tty_flip_buffer_push(&port->state->port);
1363 schedule_work(&s->work_rx);
1366 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1368 struct dma_chan *chan = s->chan_rx;
1369 struct uart_port *port = &s->port;
1370 unsigned long flags;
1372 spin_lock_irqsave(&port->lock, flags);
1374 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1375 spin_unlock_irqrestore(&port->lock, flags);
1376 dmaengine_terminate_all(chan);
1377 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2,
1378 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1379 dma_release_channel(chan);
1384 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1386 struct dma_chan *chan = s->chan_tx;
1387 struct uart_port *port = &s->port;
1388 unsigned long flags;
1390 spin_lock_irqsave(&port->lock, flags);
1392 s->cookie_tx = -EINVAL;
1393 spin_unlock_irqrestore(&port->lock, flags);
1394 dmaengine_terminate_all(chan);
1395 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1397 dma_release_channel(chan);
1402 static void sci_submit_rx(struct sci_port *s)
1404 struct dma_chan *chan = s->chan_rx;
1407 for (i = 0; i < 2; i++) {
1408 struct scatterlist *sg = &s->sg_rx[i];
1409 struct dma_async_tx_descriptor *desc;
1411 desc = dmaengine_prep_slave_sg(chan,
1412 sg, 1, DMA_DEV_TO_MEM,
1413 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1417 desc->callback = sci_dma_rx_complete;
1418 desc->callback_param = s;
1419 s->cookie_rx[i] = dmaengine_submit(desc);
1420 if (dma_submit_error(s->cookie_rx[i]))
1423 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n", __func__,
1424 s->cookie_rx[i], i);
1427 s->active_rx = s->cookie_rx[0];
1429 dma_async_issue_pending(chan);
1434 dmaengine_terminate_all(chan);
1435 for (i = 0; i < 2; i++)
1436 s->cookie_rx[i] = -EINVAL;
1437 s->active_rx = -EINVAL;
1438 dev_warn(s->port.dev, "Failed to re-start Rx DMA, using PIO\n");
1439 sci_rx_dma_release(s, true);
1442 static void work_fn_rx(struct work_struct *work)
1444 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1445 struct uart_port *port = &s->port;
1446 struct dma_async_tx_descriptor *desc;
1447 struct dma_tx_state state;
1448 enum dma_status status;
1449 unsigned long flags;
1452 spin_lock_irqsave(&port->lock, flags);
1453 new = sci_dma_rx_find_active(s);
1455 spin_unlock_irqrestore(&port->lock, flags);
1459 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1460 if (status != DMA_COMPLETE) {
1461 /* Handle incomplete DMA receive */
1462 struct dma_chan *chan = s->chan_rx;
1466 dmaengine_terminate_all(chan);
1467 read = sg_dma_len(&s->sg_rx[new]) - state.residue;
1468 dev_dbg(port->dev, "Read %u bytes with cookie %d\n", read,
1471 count = sci_dma_rx_push(s, &s->sg_rx[new], read);
1474 tty_flip_buffer_push(&port->state->port);
1476 spin_unlock_irqrestore(&port->lock, flags);
1482 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[new], 1,
1484 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1488 desc->callback = sci_dma_rx_complete;
1489 desc->callback_param = s;
1490 s->cookie_rx[new] = dmaengine_submit(desc);
1491 if (dma_submit_error(s->cookie_rx[new]))
1494 s->active_rx = s->cookie_rx[!new];
1496 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1497 __func__, s->cookie_rx[new], new, s->active_rx);
1498 spin_unlock_irqrestore(&port->lock, flags);
1502 spin_unlock_irqrestore(&port->lock, flags);
1503 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1504 sci_rx_dma_release(s, true);
1507 static void work_fn_tx(struct work_struct *work)
1509 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1510 struct dma_async_tx_descriptor *desc;
1511 struct dma_chan *chan = s->chan_tx;
1512 struct uart_port *port = &s->port;
1513 struct circ_buf *xmit = &port->state->xmit;
1518 * Port xmit buffer is already mapped, and it is one page... Just adjust
1519 * offsets and lengths. Since it is a circular buffer, we have to
1520 * transmit till the end, and then the rest. Take the port lock to get a
1521 * consistent xmit buffer state.
1523 spin_lock_irq(&port->lock);
1524 buf = s->tx_dma_addr + (xmit->tail & (UART_XMIT_SIZE - 1));
1525 s->tx_dma_len = min_t(unsigned int,
1526 CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1527 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1528 spin_unlock_irq(&port->lock);
1530 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1532 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1534 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1536 sci_tx_dma_release(s, true);
1540 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1543 spin_lock_irq(&port->lock);
1544 desc->callback = sci_dma_tx_complete;
1545 desc->callback_param = s;
1546 spin_unlock_irq(&port->lock);
1547 s->cookie_tx = dmaengine_submit(desc);
1548 if (dma_submit_error(s->cookie_tx)) {
1549 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1551 sci_tx_dma_release(s, true);
1555 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1556 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1558 dma_async_issue_pending(chan);
1562 static void sci_start_tx(struct uart_port *port)
1564 struct sci_port *s = to_sci_port(port);
1565 unsigned short ctrl;
1567 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1568 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1569 u16 new, scr = serial_port_in(port, SCSCR);
1571 new = scr | SCSCR_TDRQE;
1573 new = scr & ~SCSCR_TDRQE;
1575 serial_port_out(port, SCSCR, new);
1578 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1579 dma_submit_error(s->cookie_tx)) {
1581 schedule_work(&s->work_tx);
1585 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1586 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1587 ctrl = serial_port_in(port, SCSCR);
1588 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1592 static void sci_stop_tx(struct uart_port *port)
1594 unsigned short ctrl;
1596 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1597 ctrl = serial_port_in(port, SCSCR);
1599 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1600 ctrl &= ~SCSCR_TDRQE;
1604 serial_port_out(port, SCSCR, ctrl);
1607 static void sci_start_rx(struct uart_port *port)
1609 unsigned short ctrl;
1611 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1613 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1614 ctrl &= ~SCSCR_RDRQE;
1616 serial_port_out(port, SCSCR, ctrl);
1619 static void sci_stop_rx(struct uart_port *port)
1621 unsigned short ctrl;
1623 ctrl = serial_port_in(port, SCSCR);
1625 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1626 ctrl &= ~SCSCR_RDRQE;
1628 ctrl &= ~port_rx_irq_mask(port);
1630 serial_port_out(port, SCSCR, ctrl);
1633 static void sci_break_ctl(struct uart_port *port, int break_state)
1635 struct sci_port *s = to_sci_port(port);
1636 const struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1637 unsigned short scscr, scsptr;
1639 /* check wheter the port has SCSPTR */
1642 * Not supported by hardware. Most parts couple break and rx
1643 * interrupts together, with break detection always enabled.
1648 scsptr = serial_port_in(port, SCSPTR);
1649 scscr = serial_port_in(port, SCSCR);
1651 if (break_state == -1) {
1652 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1655 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1659 serial_port_out(port, SCSPTR, scsptr);
1660 serial_port_out(port, SCSCR, scscr);
1663 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1664 static bool filter(struct dma_chan *chan, void *slave)
1666 struct sh_dmae_slave *param = slave;
1668 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1669 __func__, param->shdma_slave.slave_id);
1671 chan->private = ¶m->shdma_slave;
1675 static void rx_timer_fn(unsigned long arg)
1677 struct sci_port *s = (struct sci_port *)arg;
1678 struct uart_port *port = &s->port;
1679 u16 scr = serial_port_in(port, SCSCR);
1681 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1682 scr &= ~SCSCR_RDRQE;
1683 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1685 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1686 dev_dbg(port->dev, "DMA Rx timed out\n");
1687 schedule_work(&s->work_rx);
1690 static void sci_request_dma(struct uart_port *port)
1692 struct sci_port *s = to_sci_port(port);
1693 struct sh_dmae_slave *param;
1694 struct dma_chan *chan;
1695 dma_cap_mask_t mask;
1697 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1699 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1703 dma_cap_set(DMA_SLAVE, mask);
1705 param = &s->param_tx;
1707 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1708 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1710 s->cookie_tx = -EINVAL;
1711 chan = dma_request_channel(mask, filter, param);
1712 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1715 /* UART circular tx buffer is an aligned page. */
1716 s->tx_dma_addr = dma_map_single(chan->device->dev,
1717 port->state->xmit.buf,
1720 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1721 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1722 dma_release_channel(chan);
1725 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1726 __func__, UART_XMIT_SIZE,
1727 port->state->xmit.buf, &s->tx_dma_addr);
1730 INIT_WORK(&s->work_tx, work_fn_tx);
1733 param = &s->param_rx;
1735 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1736 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1738 chan = dma_request_channel(mask, filter, param);
1739 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1747 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1748 buf[0] = dma_alloc_coherent(chan->device->dev,
1749 s->buf_len_rx * 2, &dma[0],
1754 "Failed to allocate Rx dma buffer, using PIO\n");
1755 dma_release_channel(chan);
1761 buf[1] = buf[0] + s->buf_len_rx;
1762 dma[1] = dma[0] + s->buf_len_rx;
1764 for (i = 0; i < 2; i++) {
1765 struct scatterlist *sg = &s->sg_rx[i];
1767 sg_init_table(sg, 1);
1768 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1769 (uintptr_t)buf[i] & ~PAGE_MASK);
1770 sg_dma_address(sg) = dma[i];
1773 INIT_WORK(&s->work_rx, work_fn_rx);
1774 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1780 static void sci_free_dma(struct uart_port *port)
1782 struct sci_port *s = to_sci_port(port);
1785 sci_tx_dma_release(s, false);
1787 sci_rx_dma_release(s, false);
1790 static inline void sci_request_dma(struct uart_port *port)
1794 static inline void sci_free_dma(struct uart_port *port)
1799 static int sci_startup(struct uart_port *port)
1801 struct sci_port *s = to_sci_port(port);
1802 unsigned long flags;
1805 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1807 ret = sci_request_irq(s);
1808 if (unlikely(ret < 0))
1811 sci_request_dma(port);
1813 spin_lock_irqsave(&port->lock, flags);
1816 spin_unlock_irqrestore(&port->lock, flags);
1821 static void sci_shutdown(struct uart_port *port)
1823 struct sci_port *s = to_sci_port(port);
1824 unsigned long flags;
1826 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1828 spin_lock_irqsave(&port->lock, flags);
1831 spin_unlock_irqrestore(&port->lock, flags);
1837 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1840 if (s->sampling_rate)
1841 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1843 /* Warn, but use a safe default */
1846 return ((freq + 16 * bps) / (32 * bps) - 1);
1849 /* calculate frame length from SMR */
1850 static int sci_baud_calc_frame_len(unsigned int smr_val)
1854 if (smr_val & SCSMR_CHR)
1856 if (smr_val & SCSMR_PE)
1858 if (smr_val & SCSMR_STOP)
1865 /* calculate sample rate, BRR, and clock select for HSCIF */
1866 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1867 int *brr, unsigned int *srr,
1868 unsigned int *cks, int frame_len)
1870 int sr, c, br, err, recv_margin;
1871 int min_err = 1000; /* 100% */
1872 int recv_max_margin = 0;
1874 /* Find the combination of sample rate and clock select with the
1875 smallest deviation from the desired baud rate. */
1876 for (sr = 8; sr <= 32; sr++) {
1877 for (c = 0; c <= 3; c++) {
1878 /* integerized formulas from HSCIF documentation */
1879 br = DIV_ROUND_CLOSEST(freq, (sr *
1880 (1 << (2 * c + 1)) * bps)) - 1;
1881 br = clamp(br, 0, 255);
1882 err = DIV_ROUND_CLOSEST(freq, ((br + 1) * bps * sr *
1883 (1 << (2 * c + 1)) / 1000)) -
1886 * M: Receive margin (%)
1887 * N: Ratio of bit rate to clock (N = sampling rate)
1888 * D: Clock duty (D = 0 to 1.0)
1889 * L: Frame length (L = 9 to 12)
1890 * F: Absolute value of clock frequency deviation
1892 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
1893 * (|D - 0.5| / N * (1 + F))|
1894 * NOTE: Usually, treat D for 0.5, F is 0 by this
1897 recv_margin = abs((500 -
1898 DIV_ROUND_CLOSEST(1000, sr << 1)) / 10);
1899 if (abs(min_err) > abs(err)) {
1901 recv_max_margin = recv_margin;
1902 } else if ((min_err == err) &&
1903 (recv_margin > recv_max_margin))
1904 recv_max_margin = recv_margin;
1914 if (min_err == 1000) {
1923 static void sci_reset(struct uart_port *port)
1925 const struct plat_sci_reg *reg;
1926 unsigned int status;
1929 status = serial_port_in(port, SCxSR);
1930 } while (!(status & SCxSR_TEND(port)));
1932 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1934 reg = sci_getreg(port, SCFCR);
1936 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1939 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1940 struct ktermios *old)
1942 struct sci_port *s = to_sci_port(port);
1943 const struct plat_sci_reg *reg;
1944 unsigned int baud, smr_val = 0, max_baud, cks = 0;
1946 unsigned int srr = 15;
1948 if ((termios->c_cflag & CSIZE) == CS7)
1949 smr_val |= SCSMR_CHR;
1950 if (termios->c_cflag & PARENB)
1951 smr_val |= SCSMR_PE;
1952 if (termios->c_cflag & PARODD)
1953 smr_val |= SCSMR_PE | SCSMR_ODD;
1954 if (termios->c_cflag & CSTOPB)
1955 smr_val |= SCSMR_STOP;
1958 * earlyprintk comes here early on with port->uartclk set to zero.
1959 * the clock framework is not up and running at this point so here
1960 * we assume that 115200 is the maximum baud rate. please note that
1961 * the baud rate is not programmed during earlyprintk - it is assumed
1962 * that the previous boot loader has enabled required clocks and
1963 * setup the baud rate generator hardware for us already.
1965 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1967 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1968 if (likely(baud && port->uartclk)) {
1969 if (s->cfg->type == PORT_HSCIF) {
1970 int frame_len = sci_baud_calc_frame_len(smr_val);
1971 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1974 t = sci_scbrr_calc(s, baud, port->uartclk);
1975 for (cks = 0; t >= 256 && cks <= 3; cks++)
1984 smr_val |= serial_port_in(port, SCSMR) & SCSMR_CKS;
1986 uart_update_timeout(port, termios->c_cflag, baud);
1988 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1989 __func__, smr_val, cks, t, s->cfg->scscr);
1992 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1993 serial_port_out(port, SCBRR, t);
1994 reg = sci_getreg(port, HSSRR);
1996 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1997 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1999 serial_port_out(port, SCSMR, smr_val);
2001 sci_init_pins(port, termios->c_cflag);
2003 reg = sci_getreg(port, SCFCR);
2005 unsigned short ctrl = serial_port_in(port, SCFCR);
2007 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
2008 if (termios->c_cflag & CRTSCTS)
2015 * As we've done a sci_reset() above, ensure we don't
2016 * interfere with the FIFOs while toggling MCE. As the
2017 * reset values could still be set, simply mask them out.
2019 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2021 serial_port_out(port, SCFCR, ctrl);
2024 serial_port_out(port, SCSCR, s->cfg->scscr);
2026 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2028 * Calculate delay for 2 DMA buffers (4 FIFO).
2029 * See serial_core.c::uart_update_timeout().
2030 * With 10 bits (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above
2031 * function calculates 1 jiffie for the data plus 5 jiffies for the
2032 * "slop(e)." Then below we calculate 5 jiffies (20ms) for 2 DMA
2033 * buffers (4 FIFO sizes), but when performing a faster transfer, the
2034 * value obtained by this formula is too small. Therefore, if the value
2035 * is smaller than 20ms, use 20ms as the timeout value for DMA.
2040 /* byte size and parity */
2041 switch (termios->c_cflag & CSIZE) {
2056 if (termios->c_cflag & CSTOPB)
2058 if (termios->c_cflag & PARENB)
2060 s->rx_timeout = DIV_ROUND_UP((s->buf_len_rx * 2 * bits * HZ) /
2062 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
2063 s->rx_timeout * 1000 / HZ, port->timeout);
2064 if (s->rx_timeout < msecs_to_jiffies(20))
2065 s->rx_timeout = msecs_to_jiffies(20);
2069 if ((termios->c_cflag & CREAD) != 0)
2072 sci_port_disable(s);
2075 static void sci_pm(struct uart_port *port, unsigned int state,
2076 unsigned int oldstate)
2078 struct sci_port *sci_port = to_sci_port(port);
2081 case UART_PM_STATE_OFF:
2082 sci_port_disable(sci_port);
2085 sci_port_enable(sci_port);
2090 static const char *sci_type(struct uart_port *port)
2092 switch (port->type) {
2110 static int sci_remap_port(struct uart_port *port)
2112 struct sci_port *sport = to_sci_port(port);
2115 * Nothing to do if there's already an established membase.
2120 if (port->flags & UPF_IOREMAP) {
2121 port->membase = ioremap_nocache(port->mapbase, sport->reg_size);
2122 if (unlikely(!port->membase)) {
2123 dev_err(port->dev, "can't remap port#%d\n", port->line);
2128 * For the simple (and majority of) cases where we don't
2129 * need to do any remapping, just cast the cookie
2132 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2138 static void sci_release_port(struct uart_port *port)
2140 struct sci_port *sport = to_sci_port(port);
2142 if (port->flags & UPF_IOREMAP) {
2143 iounmap(port->membase);
2144 port->membase = NULL;
2147 release_mem_region(port->mapbase, sport->reg_size);
2150 static int sci_request_port(struct uart_port *port)
2152 struct resource *res;
2153 struct sci_port *sport = to_sci_port(port);
2156 res = request_mem_region(port->mapbase, sport->reg_size,
2157 dev_name(port->dev));
2158 if (unlikely(res == NULL)) {
2159 dev_err(port->dev, "request_mem_region failed.");
2163 ret = sci_remap_port(port);
2164 if (unlikely(ret != 0)) {
2165 release_resource(res);
2172 static void sci_config_port(struct uart_port *port, int flags)
2174 if (flags & UART_CONFIG_TYPE) {
2175 struct sci_port *sport = to_sci_port(port);
2177 port->type = sport->cfg->type;
2178 sci_request_port(port);
2182 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2184 if (ser->baud_base < 2400)
2185 /* No paper tape reader for Mitch.. */
2191 static struct uart_ops sci_uart_ops = {
2192 .tx_empty = sci_tx_empty,
2193 .set_mctrl = sci_set_mctrl,
2194 .get_mctrl = sci_get_mctrl,
2195 .start_tx = sci_start_tx,
2196 .stop_tx = sci_stop_tx,
2197 .stop_rx = sci_stop_rx,
2198 .break_ctl = sci_break_ctl,
2199 .startup = sci_startup,
2200 .shutdown = sci_shutdown,
2201 .set_termios = sci_set_termios,
2204 .release_port = sci_release_port,
2205 .request_port = sci_request_port,
2206 .config_port = sci_config_port,
2207 .verify_port = sci_verify_port,
2208 #ifdef CONFIG_CONSOLE_POLL
2209 .poll_get_char = sci_poll_get_char,
2210 .poll_put_char = sci_poll_put_char,
2214 static int sci_init_single(struct platform_device *dev,
2215 struct sci_port *sci_port, unsigned int index,
2216 struct plat_sci_port *p, bool early)
2218 struct uart_port *port = &sci_port->port;
2219 const struct resource *res;
2225 port->ops = &sci_uart_ops;
2226 port->iotype = UPIO_MEM;
2229 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2233 port->mapbase = res->start;
2234 sci_port->reg_size = resource_size(res);
2236 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2237 sci_port->irqs[i] = platform_get_irq(dev, i);
2239 /* The SCI generates several interrupts. They can be muxed together or
2240 * connected to different interrupt lines. In the muxed case only one
2241 * interrupt resource is specified. In the non-muxed case three or four
2242 * interrupt resources are specified, as the BRI interrupt is optional.
2244 if (sci_port->irqs[0] < 0)
2247 if (sci_port->irqs[1] < 0) {
2248 sci_port->irqs[1] = sci_port->irqs[0];
2249 sci_port->irqs[2] = sci_port->irqs[0];
2250 sci_port->irqs[3] = sci_port->irqs[0];
2253 if (p->regtype == SCIx_PROBE_REGTYPE) {
2254 ret = sci_probe_regmap(p);
2261 port->fifosize = 256;
2262 sci_port->overrun_reg = SCxSR;
2263 sci_port->overrun_mask = SCIFA_ORER;
2264 sci_port->sampling_rate = 16;
2267 port->fifosize = 128;
2268 sci_port->overrun_reg = SCLSR;
2269 sci_port->overrun_mask = SCLSR_ORER;
2270 sci_port->sampling_rate = 0;
2273 port->fifosize = 64;
2274 sci_port->overrun_reg = SCxSR;
2275 sci_port->overrun_mask = SCIFA_ORER;
2276 sci_port->sampling_rate = 16;
2279 port->fifosize = 16;
2280 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2281 sci_port->overrun_reg = SCxSR;
2282 sci_port->overrun_mask = SCIFA_ORER;
2283 sci_port->sampling_rate = 16;
2285 sci_port->overrun_reg = SCLSR;
2286 sci_port->overrun_mask = SCLSR_ORER;
2287 sci_port->sampling_rate = 32;
2292 sci_port->overrun_reg = SCxSR;
2293 sci_port->overrun_mask = SCI_ORER;
2294 sci_port->sampling_rate = 32;
2298 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2299 * match the SoC datasheet, this should be investigated. Let platform
2300 * data override the sampling rate for now.
2302 if (p->sampling_rate)
2303 sci_port->sampling_rate = p->sampling_rate;
2306 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2307 if (IS_ERR(sci_port->iclk)) {
2308 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2309 if (IS_ERR(sci_port->iclk)) {
2310 dev_err(&dev->dev, "can't get iclk\n");
2311 return PTR_ERR(sci_port->iclk);
2316 * The function clock is optional, ignore it if we can't
2319 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2320 if (IS_ERR(sci_port->fclk))
2321 sci_port->fclk = NULL;
2323 port->dev = &dev->dev;
2325 pm_runtime_enable(&dev->dev);
2328 sci_port->break_timer.data = (unsigned long)sci_port;
2329 sci_port->break_timer.function = sci_break_timer;
2330 init_timer(&sci_port->break_timer);
2333 * Establish some sensible defaults for the error detection.
2335 if (p->type == PORT_SCI) {
2336 sci_port->error_mask = SCI_DEFAULT_ERROR_MASK;
2337 sci_port->error_clear = SCI_ERROR_CLEAR;
2339 sci_port->error_mask = SCIF_DEFAULT_ERROR_MASK;
2340 sci_port->error_clear = SCIF_ERROR_CLEAR;
2344 * Make the error mask inclusive of overrun detection, if
2347 if (sci_port->overrun_reg == SCxSR) {
2348 sci_port->error_mask |= sci_port->overrun_mask;
2349 sci_port->error_clear &= ~sci_port->overrun_mask;
2352 port->type = p->type;
2353 port->flags = UPF_FIXED_PORT | p->flags;
2354 port->regshift = p->regshift;
2357 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2358 * for the multi-IRQ ports, which is where we are primarily
2359 * concerned with the shutdown path synchronization.
2361 * For the muxed case there's nothing more to do.
2363 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2366 port->serial_in = sci_serial_in;
2367 port->serial_out = sci_serial_out;
2369 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2370 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2371 p->dma_slave_tx, p->dma_slave_rx);
2376 static void sci_cleanup_single(struct sci_port *port)
2378 clk_put(port->iclk);
2379 clk_put(port->fclk);
2381 pm_runtime_disable(port->port.dev);
2384 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2385 static void serial_console_putchar(struct uart_port *port, int ch)
2387 sci_poll_put_char(port, ch);
2391 * Print a string to the serial port trying not to disturb
2392 * any possible real use of the port...
2394 static void serial_console_write(struct console *co, const char *s,
2397 struct sci_port *sci_port = &sci_ports[co->index];
2398 struct uart_port *port = &sci_port->port;
2399 unsigned short bits, ctrl;
2400 unsigned long flags;
2403 local_irq_save(flags);
2406 else if (oops_in_progress)
2407 locked = spin_trylock(&port->lock);
2409 spin_lock(&port->lock);
2411 /* first save the SCSCR then disable the interrupts */
2412 ctrl = serial_port_in(port, SCSCR);
2413 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2415 uart_console_write(port, s, count, serial_console_putchar);
2417 /* wait until fifo is empty and last bit has been transmitted */
2418 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2419 while ((serial_port_in(port, SCxSR) & bits) != bits)
2422 /* restore the SCSCR */
2423 serial_port_out(port, SCSCR, ctrl);
2426 spin_unlock(&port->lock);
2427 local_irq_restore(flags);
2430 static int serial_console_setup(struct console *co, char *options)
2432 struct sci_port *sci_port;
2433 struct uart_port *port;
2441 * Refuse to handle any bogus ports.
2443 if (co->index < 0 || co->index >= SCI_NPORTS)
2446 sci_port = &sci_ports[co->index];
2447 port = &sci_port->port;
2450 * Refuse to handle uninitialized ports.
2455 ret = sci_remap_port(port);
2456 if (unlikely(ret != 0))
2460 uart_parse_options(options, &baud, &parity, &bits, &flow);
2462 return uart_set_options(port, co, baud, parity, bits, flow);
2465 static struct console serial_console = {
2467 .device = uart_console_device,
2468 .write = serial_console_write,
2469 .setup = serial_console_setup,
2470 .flags = CON_PRINTBUFFER,
2472 .data = &sci_uart_driver,
2475 static struct console early_serial_console = {
2476 .name = "early_ttySC",
2477 .write = serial_console_write,
2478 .flags = CON_PRINTBUFFER,
2482 static char early_serial_buf[32];
2484 static int sci_probe_earlyprintk(struct platform_device *pdev)
2486 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2488 if (early_serial_console.data)
2491 early_serial_console.index = pdev->id;
2493 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2495 serial_console_setup(&early_serial_console, early_serial_buf);
2497 if (!strstr(early_serial_buf, "keep"))
2498 early_serial_console.flags |= CON_BOOT;
2500 register_console(&early_serial_console);
2504 #define SCI_CONSOLE (&serial_console)
2507 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2512 #define SCI_CONSOLE NULL
2514 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2516 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2518 static struct uart_driver sci_uart_driver = {
2519 .owner = THIS_MODULE,
2520 .driver_name = "sci",
2521 .dev_name = "ttySC",
2523 .minor = SCI_MINOR_START,
2525 .cons = SCI_CONSOLE,
2528 static int sci_remove(struct platform_device *dev)
2530 struct sci_port *port = platform_get_drvdata(dev);
2532 cpufreq_unregister_notifier(&port->freq_transition,
2533 CPUFREQ_TRANSITION_NOTIFIER);
2535 uart_remove_one_port(&sci_uart_driver, &port->port);
2537 sci_cleanup_single(port);
2542 struct sci_port_info {
2544 unsigned int regtype;
2547 static const struct of_device_id of_sci_match[] = {
2549 .compatible = "renesas,scif",
2550 .data = &(const struct sci_port_info) {
2552 .regtype = SCIx_SH4_SCIF_REGTYPE,
2555 .compatible = "renesas,scifa",
2556 .data = &(const struct sci_port_info) {
2558 .regtype = SCIx_SCIFA_REGTYPE,
2561 .compatible = "renesas,scifb",
2562 .data = &(const struct sci_port_info) {
2564 .regtype = SCIx_SCIFB_REGTYPE,
2567 .compatible = "renesas,hscif",
2568 .data = &(const struct sci_port_info) {
2570 .regtype = SCIx_HSCIF_REGTYPE,
2573 .compatible = "renesas,sci",
2574 .data = &(const struct sci_port_info) {
2576 .regtype = SCIx_SCI_REGTYPE,
2582 MODULE_DEVICE_TABLE(of, of_sci_match);
2584 static struct plat_sci_port *
2585 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2587 struct device_node *np = pdev->dev.of_node;
2588 const struct of_device_id *match;
2589 const struct sci_port_info *info;
2590 struct plat_sci_port *p;
2593 if (!IS_ENABLED(CONFIG_OF) || !np)
2596 match = of_match_node(of_sci_match, pdev->dev.of_node);
2602 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2606 /* Get the line number for the aliases node. */
2607 id = of_alias_get_id(np, "serial");
2609 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2615 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2616 p->type = info->type;
2617 p->regtype = info->regtype;
2618 p->scscr = SCSCR_RE | SCSCR_TE;
2623 static int sci_probe_single(struct platform_device *dev,
2625 struct plat_sci_port *p,
2626 struct sci_port *sciport)
2631 if (unlikely(index >= SCI_NPORTS)) {
2632 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2633 index+1, SCI_NPORTS);
2634 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2638 ret = sci_init_single(dev, sciport, index, p, false);
2642 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2644 sci_cleanup_single(sciport);
2651 static int sci_probe(struct platform_device *dev)
2653 struct plat_sci_port *p;
2654 struct sci_port *sp;
2655 unsigned int dev_id;
2659 * If we've come here via earlyprintk initialization, head off to
2660 * the special early probe. We don't have sufficient device state
2661 * to make it beyond this yet.
2663 if (is_early_platform_device(dev))
2664 return sci_probe_earlyprintk(dev);
2666 if (dev->dev.of_node) {
2667 p = sci_parse_dt(dev, &dev_id);
2671 p = dev->dev.platform_data;
2673 dev_err(&dev->dev, "no platform data supplied\n");
2680 sp = &sci_ports[dev_id];
2681 platform_set_drvdata(dev, sp);
2683 ret = sci_probe_single(dev, dev_id, p, sp);
2687 sp->freq_transition.notifier_call = sci_notifier;
2689 ret = cpufreq_register_notifier(&sp->freq_transition,
2690 CPUFREQ_TRANSITION_NOTIFIER);
2691 if (unlikely(ret < 0)) {
2692 uart_remove_one_port(&sci_uart_driver, &sp->port);
2693 sci_cleanup_single(sp);
2697 #ifdef CONFIG_SH_STANDARD_BIOS
2698 sh_bios_gdb_detach();
2704 static __maybe_unused int sci_suspend(struct device *dev)
2706 struct sci_port *sport = dev_get_drvdata(dev);
2709 uart_suspend_port(&sci_uart_driver, &sport->port);
2714 static __maybe_unused int sci_resume(struct device *dev)
2716 struct sci_port *sport = dev_get_drvdata(dev);
2719 uart_resume_port(&sci_uart_driver, &sport->port);
2724 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
2726 static struct platform_driver sci_driver = {
2728 .remove = sci_remove,
2731 .pm = &sci_dev_pm_ops,
2732 .of_match_table = of_match_ptr(of_sci_match),
2736 static int __init sci_init(void)
2740 pr_info("%s\n", banner);
2742 ret = uart_register_driver(&sci_uart_driver);
2743 if (likely(ret == 0)) {
2744 ret = platform_driver_register(&sci_driver);
2746 uart_unregister_driver(&sci_uart_driver);
2752 static void __exit sci_exit(void)
2754 platform_driver_unregister(&sci_driver);
2755 uart_unregister_driver(&sci_uart_driver);
2758 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2759 early_platform_init_buffer("earlyprintk", &sci_driver,
2760 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2762 module_init(sci_init);
2763 module_exit(sci_exit);
2765 MODULE_LICENSE("GPL");
2766 MODULE_ALIAS("platform:sh-sci");
2767 MODULE_AUTHOR("Paul Mundt");
2768 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");